Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 02:12:20.773250 lava-dispatcher, installed at version: 2024.01
2 02:12:20.774072 start: 0 validate
3 02:12:20.774570 Start time: 2024-11-08 02:12:20.774539+00:00 (UTC)
4 02:12:20.775115 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 02:12:20.775678 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 02:12:20.811766 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 02:12:20.812359 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-326-gaded6a2e0817%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 02:12:21.846708 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 02:12:21.847347 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-326-gaded6a2e0817%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 02:12:27.922601 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 02:12:27.923164 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-326-gaded6a2e0817%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 02:12:28.967175 validate duration: 8.19
14 02:12:28.968329 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 02:12:28.968739 start: 1.1 download-retry (timeout 00:10:00) [common]
16 02:12:28.969101 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 02:12:28.969728 Not decompressing ramdisk as can be used compressed.
18 02:12:28.970241 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 02:12:28.970520 saving as /var/lib/lava/dispatcher/tmp/957406/tftp-deploy-fl7e1zea/ramdisk/rootfs.cpio.gz
20 02:12:28.970807 total size: 8181887 (7 MB)
21 02:12:29.010201 progress 0 % (0 MB)
22 02:12:29.021432 progress 5 % (0 MB)
23 02:12:29.033086 progress 10 % (0 MB)
24 02:12:29.042413 progress 15 % (1 MB)
25 02:12:29.047689 progress 20 % (1 MB)
26 02:12:29.053396 progress 25 % (1 MB)
27 02:12:29.058778 progress 30 % (2 MB)
28 02:12:29.064602 progress 35 % (2 MB)
29 02:12:29.069884 progress 40 % (3 MB)
30 02:12:29.075763 progress 45 % (3 MB)
31 02:12:29.081152 progress 50 % (3 MB)
32 02:12:29.086848 progress 55 % (4 MB)
33 02:12:29.092142 progress 60 % (4 MB)
34 02:12:29.097695 progress 65 % (5 MB)
35 02:12:29.102921 progress 70 % (5 MB)
36 02:12:29.108643 progress 75 % (5 MB)
37 02:12:29.113904 progress 80 % (6 MB)
38 02:12:29.119479 progress 85 % (6 MB)
39 02:12:29.124794 progress 90 % (7 MB)
40 02:12:29.130338 progress 95 % (7 MB)
41 02:12:29.135117 progress 100 % (7 MB)
42 02:12:29.135804 7 MB downloaded in 0.16 s (47.30 MB/s)
43 02:12:29.136370 end: 1.1.1 http-download (duration 00:00:00) [common]
45 02:12:29.137267 end: 1.1 download-retry (duration 00:00:00) [common]
46 02:12:29.137568 start: 1.2 download-retry (timeout 00:10:00) [common]
47 02:12:29.137841 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 02:12:29.138328 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-326-gaded6a2e0817/arm64/defconfig/gcc-12/kernel/Image
49 02:12:29.138592 saving as /var/lib/lava/dispatcher/tmp/957406/tftp-deploy-fl7e1zea/kernel/Image
50 02:12:29.138834 total size: 45715968 (43 MB)
51 02:12:29.139082 No compression specified
52 02:12:29.177198 progress 0 % (0 MB)
53 02:12:29.208860 progress 5 % (2 MB)
54 02:12:29.241653 progress 10 % (4 MB)
55 02:12:29.271000 progress 15 % (6 MB)
56 02:12:29.300837 progress 20 % (8 MB)
57 02:12:29.330311 progress 25 % (10 MB)
58 02:12:29.359567 progress 30 % (13 MB)
59 02:12:29.388309 progress 35 % (15 MB)
60 02:12:29.416980 progress 40 % (17 MB)
61 02:12:29.444928 progress 45 % (19 MB)
62 02:12:29.473202 progress 50 % (21 MB)
63 02:12:29.501599 progress 55 % (24 MB)
64 02:12:29.529751 progress 60 % (26 MB)
65 02:12:29.557734 progress 65 % (28 MB)
66 02:12:29.585748 progress 70 % (30 MB)
67 02:12:29.613880 progress 75 % (32 MB)
68 02:12:29.641714 progress 80 % (34 MB)
69 02:12:29.669240 progress 85 % (37 MB)
70 02:12:29.697396 progress 90 % (39 MB)
71 02:12:29.725595 progress 95 % (41 MB)
72 02:12:29.753497 progress 100 % (43 MB)
73 02:12:29.754099 43 MB downloaded in 0.62 s (70.86 MB/s)
74 02:12:29.754621 end: 1.2.1 http-download (duration 00:00:01) [common]
76 02:12:29.755489 end: 1.2 download-retry (duration 00:00:01) [common]
77 02:12:29.755796 start: 1.3 download-retry (timeout 00:09:59) [common]
78 02:12:29.756121 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 02:12:29.756642 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-326-gaded6a2e0817/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 02:12:29.756951 saving as /var/lib/lava/dispatcher/tmp/957406/tftp-deploy-fl7e1zea/dtb/meson-g12b-a311d-libretech-cc.dtb
81 02:12:29.757179 total size: 54703 (0 MB)
82 02:12:29.757406 No compression specified
83 02:12:29.821322 progress 59 % (0 MB)
84 02:12:29.822178 progress 100 % (0 MB)
85 02:12:29.822741 0 MB downloaded in 0.07 s (0.80 MB/s)
86 02:12:29.823255 end: 1.3.1 http-download (duration 00:00:00) [common]
88 02:12:29.824153 end: 1.3 download-retry (duration 00:00:00) [common]
89 02:12:29.824443 start: 1.4 download-retry (timeout 00:09:59) [common]
90 02:12:29.824730 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 02:12:29.825206 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-326-gaded6a2e0817/arm64/defconfig/gcc-12/modules.tar.xz
92 02:12:29.825457 saving as /var/lib/lava/dispatcher/tmp/957406/tftp-deploy-fl7e1zea/modules/modules.tar
93 02:12:29.825672 total size: 11607064 (11 MB)
94 02:12:29.825894 Using unxz to decompress xz
95 02:12:29.872685 progress 0 % (0 MB)
96 02:12:29.938961 progress 5 % (0 MB)
97 02:12:30.013812 progress 10 % (1 MB)
98 02:12:30.110343 progress 15 % (1 MB)
99 02:12:30.203334 progress 20 % (2 MB)
100 02:12:30.282962 progress 25 % (2 MB)
101 02:12:30.359961 progress 30 % (3 MB)
102 02:12:30.435503 progress 35 % (3 MB)
103 02:12:30.513216 progress 40 % (4 MB)
104 02:12:30.590665 progress 45 % (5 MB)
105 02:12:30.675416 progress 50 % (5 MB)
106 02:12:30.753307 progress 55 % (6 MB)
107 02:12:30.839046 progress 60 % (6 MB)
108 02:12:30.919422 progress 65 % (7 MB)
109 02:12:30.996408 progress 70 % (7 MB)
110 02:12:31.079270 progress 75 % (8 MB)
111 02:12:31.162879 progress 80 % (8 MB)
112 02:12:31.243095 progress 85 % (9 MB)
113 02:12:31.321810 progress 90 % (9 MB)
114 02:12:31.399935 progress 95 % (10 MB)
115 02:12:31.477261 progress 100 % (11 MB)
116 02:12:31.488280 11 MB downloaded in 1.66 s (6.66 MB/s)
117 02:12:31.488991 end: 1.4.1 http-download (duration 00:00:02) [common]
119 02:12:31.489985 end: 1.4 download-retry (duration 00:00:02) [common]
120 02:12:31.490316 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 02:12:31.490646 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 02:12:31.490950 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 02:12:31.491266 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 02:12:31.492085 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5
125 02:12:31.493213 makedir: /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin
126 02:12:31.494031 makedir: /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/tests
127 02:12:31.494825 makedir: /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/results
128 02:12:31.495604 Creating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin/lava-add-keys
129 02:12:31.496905 Creating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin/lava-add-sources
130 02:12:31.498114 Creating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin/lava-background-process-start
131 02:12:31.499320 Creating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin/lava-background-process-stop
132 02:12:31.500623 Creating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin/lava-common-functions
133 02:12:31.501837 Creating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin/lava-echo-ipv4
134 02:12:31.503022 Creating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin/lava-install-packages
135 02:12:31.504217 Creating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin/lava-installed-packages
136 02:12:31.505395 Creating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin/lava-os-build
137 02:12:31.506568 Creating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin/lava-probe-channel
138 02:12:31.507706 Creating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin/lava-probe-ip
139 02:12:31.508955 Creating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin/lava-target-ip
140 02:12:31.510108 Creating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin/lava-target-mac
141 02:12:31.511247 Creating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin/lava-target-storage
142 02:12:31.512456 Creating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin/lava-test-case
143 02:12:31.513630 Creating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin/lava-test-event
144 02:12:31.514778 Creating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin/lava-test-feedback
145 02:12:31.515920 Creating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin/lava-test-raise
146 02:12:31.517140 Creating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin/lava-test-reference
147 02:12:31.518282 Creating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin/lava-test-runner
148 02:12:31.519454 Creating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin/lava-test-set
149 02:12:31.520662 Creating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin/lava-test-shell
150 02:12:31.521848 Updating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin/lava-install-packages (oe)
151 02:12:31.523127 Updating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/bin/lava-installed-packages (oe)
152 02:12:31.524180 Creating /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/environment
153 02:12:31.524706 LAVA metadata
154 02:12:31.525041 - LAVA_JOB_ID=957406
155 02:12:31.525312 - LAVA_DISPATCHER_IP=192.168.6.2
156 02:12:31.525768 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 02:12:31.527016 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 02:12:31.527410 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 02:12:31.527676 skipped lava-vland-overlay
160 02:12:31.527977 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 02:12:31.528326 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 02:12:31.528603 skipped lava-multinode-overlay
163 02:12:31.528904 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 02:12:31.529223 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 02:12:31.529529 Loading test definitions
166 02:12:31.529883 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 02:12:31.530158 Using /lava-957406 at stage 0
168 02:12:31.531654 uuid=957406_1.5.2.4.1 testdef=None
169 02:12:31.532070 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 02:12:31.532411 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 02:12:31.534655 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 02:12:31.535648 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 02:12:31.538506 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 02:12:31.539564 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 02:12:31.542359 runner path: /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/0/tests/0_dmesg test_uuid 957406_1.5.2.4.1
178 02:12:31.543095 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 02:12:31.544078 Creating lava-test-runner.conf files
181 02:12:31.544343 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/957406/lava-overlay-2pmd2kl5/lava-957406/0 for stage 0
182 02:12:31.544775 - 0_dmesg
183 02:12:31.545220 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 02:12:31.545569 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 02:12:31.575523 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 02:12:31.576120 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 02:12:31.576455 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 02:12:31.576802 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 02:12:31.577134 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 02:12:32.521899 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 02:12:32.522475 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 02:12:32.522782 extracting modules file /var/lib/lava/dispatcher/tmp/957406/tftp-deploy-fl7e1zea/modules/modules.tar to /var/lib/lava/dispatcher/tmp/957406/extract-overlay-ramdisk-0w_8baby/ramdisk
193 02:12:34.019514 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 02:12:34.020011 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 02:12:34.020295 [common] Applying overlay /var/lib/lava/dispatcher/tmp/957406/compress-overlay-v_5zuwj2/overlay-1.5.2.5.tar.gz to ramdisk
196 02:12:34.020511 [common] Applying overlay /var/lib/lava/dispatcher/tmp/957406/compress-overlay-v_5zuwj2/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/957406/extract-overlay-ramdisk-0w_8baby/ramdisk
197 02:12:34.053500 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 02:12:34.053978 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 02:12:34.054265 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 02:12:34.054500 Converting downloaded kernel to a uImage
201 02:12:34.054808 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/957406/tftp-deploy-fl7e1zea/kernel/Image /var/lib/lava/dispatcher/tmp/957406/tftp-deploy-fl7e1zea/kernel/uImage
202 02:12:34.510366 output: Image Name:
203 02:12:34.510793 output: Created: Fri Nov 8 02:12:34 2024
204 02:12:34.511004 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 02:12:34.511209 output: Data Size: 45715968 Bytes = 44644.50 KiB = 43.60 MiB
206 02:12:34.511411 output: Load Address: 01080000
207 02:12:34.511610 output: Entry Point: 01080000
208 02:12:34.511810 output:
209 02:12:34.512176 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 02:12:34.512451 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 02:12:34.512721 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 02:12:34.512976 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 02:12:34.513234 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 02:12:34.513502 Building ramdisk /var/lib/lava/dispatcher/tmp/957406/extract-overlay-ramdisk-0w_8baby/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/957406/extract-overlay-ramdisk-0w_8baby/ramdisk
215 02:12:36.990863 >> 181614 blocks
216 02:12:45.790133 Adding RAMdisk u-boot header.
217 02:12:45.790845 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/957406/extract-overlay-ramdisk-0w_8baby/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/957406/extract-overlay-ramdisk-0w_8baby/ramdisk.cpio.gz.uboot
218 02:12:46.052329 output: Image Name:
219 02:12:46.052846 output: Created: Fri Nov 8 02:12:45 2024
220 02:12:46.053105 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 02:12:46.053355 output: Data Size: 26062255 Bytes = 25451.42 KiB = 24.85 MiB
222 02:12:46.053600 output: Load Address: 00000000
223 02:12:46.053845 output: Entry Point: 00000000
224 02:12:46.054087 output:
225 02:12:46.054830 rename /var/lib/lava/dispatcher/tmp/957406/extract-overlay-ramdisk-0w_8baby/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/957406/tftp-deploy-fl7e1zea/ramdisk/ramdisk.cpio.gz.uboot
226 02:12:46.055332 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 02:12:46.055677 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 02:12:46.056114 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 02:12:46.056728 No LXC device requested
230 02:12:46.057387 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 02:12:46.058053 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 02:12:46.058687 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 02:12:46.059219 Checking files for TFTP limit of 4294967296 bytes.
234 02:12:46.062672 end: 1 tftp-deploy (duration 00:00:17) [common]
235 02:12:46.063408 start: 2 uboot-action (timeout 00:05:00) [common]
236 02:12:46.064116 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 02:12:46.064797 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 02:12:46.065454 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 02:12:46.066130 Using kernel file from prepare-kernel: 957406/tftp-deploy-fl7e1zea/kernel/uImage
240 02:12:46.066926 substitutions:
241 02:12:46.067451 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 02:12:46.067968 - {DTB_ADDR}: 0x01070000
243 02:12:46.068517 - {DTB}: 957406/tftp-deploy-fl7e1zea/dtb/meson-g12b-a311d-libretech-cc.dtb
244 02:12:46.069042 - {INITRD}: 957406/tftp-deploy-fl7e1zea/ramdisk/ramdisk.cpio.gz.uboot
245 02:12:46.069552 - {KERNEL_ADDR}: 0x01080000
246 02:12:46.070061 - {KERNEL}: 957406/tftp-deploy-fl7e1zea/kernel/uImage
247 02:12:46.070567 - {LAVA_MAC}: None
248 02:12:46.071119 - {PRESEED_CONFIG}: None
249 02:12:46.071627 - {PRESEED_LOCAL}: None
250 02:12:46.072165 - {RAMDISK_ADDR}: 0x08000000
251 02:12:46.072683 - {RAMDISK}: 957406/tftp-deploy-fl7e1zea/ramdisk/ramdisk.cpio.gz.uboot
252 02:12:46.073206 - {ROOT_PART}: None
253 02:12:46.073718 - {ROOT}: None
254 02:12:46.074234 - {SERVER_IP}: 192.168.6.2
255 02:12:46.074747 - {TEE_ADDR}: 0x83000000
256 02:12:46.075258 - {TEE}: None
257 02:12:46.075773 Parsed boot commands:
258 02:12:46.076305 - setenv autoload no
259 02:12:46.076822 - setenv initrd_high 0xffffffff
260 02:12:46.077330 - setenv fdt_high 0xffffffff
261 02:12:46.077837 - dhcp
262 02:12:46.078345 - setenv serverip 192.168.6.2
263 02:12:46.078859 - tftpboot 0x01080000 957406/tftp-deploy-fl7e1zea/kernel/uImage
264 02:12:46.079369 - tftpboot 0x08000000 957406/tftp-deploy-fl7e1zea/ramdisk/ramdisk.cpio.gz.uboot
265 02:12:46.079882 - tftpboot 0x01070000 957406/tftp-deploy-fl7e1zea/dtb/meson-g12b-a311d-libretech-cc.dtb
266 02:12:46.080426 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 02:12:46.080951 - bootm 0x01080000 0x08000000 0x01070000
268 02:12:46.081592 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 02:12:46.083545 start: 2.3 connect-device (timeout 00:05:00) [common]
271 02:12:46.084144 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 02:12:46.100717 Setting prompt string to ['lava-test: # ']
273 02:12:46.102590 end: 2.3 connect-device (duration 00:00:00) [common]
274 02:12:46.103578 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 02:12:46.104390 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 02:12:46.105071 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 02:12:46.106534 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 02:12:46.143720 >> OK - accepted request
279 02:12:46.145896 Returned 0 in 0 seconds
280 02:12:46.247258 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 02:12:46.249442 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 02:12:46.250166 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 02:12:46.250816 Setting prompt string to ['Hit any key to stop autoboot']
285 02:12:46.251386 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 02:12:46.253435 Trying 192.168.56.21...
287 02:12:46.254053 Connected to conserv1.
288 02:12:46.254592 Escape character is '^]'.
289 02:12:46.255112
290 02:12:46.255655 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 02:12:46.256241
292 02:12:58.171951 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 02:12:58.172507 bl2_stage_init 0x01
294 02:12:58.172803 bl2_stage_init 0x81
295 02:12:58.177403 hw id: 0x0000 - pwm id 0x01
296 02:12:58.177742 bl2_stage_init 0xc1
297 02:12:58.177971 bl2_stage_init 0x02
298 02:12:58.178188
299 02:12:58.182983 L0:00000000
300 02:12:58.183258 L1:20000703
301 02:12:58.183475 L2:00008067
302 02:12:58.183678 L3:14000000
303 02:12:58.185866 B2:00402000
304 02:12:58.186132 B1:e0f83180
305 02:12:58.186355
306 02:12:58.186566 TE: 58124
307 02:12:58.186766
308 02:12:58.196994 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 02:12:58.197293
310 02:12:58.197501 Board ID = 1
311 02:12:58.197703 Set A53 clk to 24M
312 02:12:58.197903 Set A73 clk to 24M
313 02:12:58.202593 Set clk81 to 24M
314 02:12:58.203078 A53 clk: 1200 MHz
315 02:12:58.203519 A73 clk: 1200 MHz
316 02:12:58.208221 CLK81: 166.6M
317 02:12:58.208733 smccc: 00012a92
318 02:12:58.213892 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 02:12:58.214382 board id: 1
320 02:12:58.219389 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 02:12:58.233327 fw parse done
322 02:12:58.239094 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 02:12:58.281755 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 02:12:58.292898 PIEI prepare done
325 02:12:58.293496 fastboot data load
326 02:12:58.293953 fastboot data verify
327 02:12:58.300586 verify result: 266
328 02:12:58.303972 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 02:12:58.304502 LPDDR4 probe
330 02:12:58.304946 ddr clk to 1584MHz
331 02:12:58.312020 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 02:12:58.349241
333 02:12:58.349851 dmc_version 0001
334 02:12:58.355883 Check phy result
335 02:12:58.361782 INFO : End of CA training
336 02:12:58.362295 INFO : End of initialization
337 02:12:58.367420 INFO : Training has run successfully!
338 02:12:58.367913 Check phy result
339 02:12:58.372967 INFO : End of initialization
340 02:12:58.373472 INFO : End of read enable training
341 02:12:58.378580 INFO : End of fine write leveling
342 02:12:58.384239 INFO : End of Write leveling coarse delay
343 02:12:58.384755 INFO : Training has run successfully!
344 02:12:58.385162 Check phy result
345 02:12:58.389760 INFO : End of initialization
346 02:12:58.390256 INFO : End of read dq deskew training
347 02:12:58.395423 INFO : End of MPR read delay center optimization
348 02:12:58.401077 INFO : End of write delay center optimization
349 02:12:58.406662 INFO : End of read delay center optimization
350 02:12:58.407214 INFO : End of max read latency training
351 02:12:58.412375 INFO : Training has run successfully!
352 02:12:58.412969 1D training succeed
353 02:12:58.421517 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 02:12:58.469056 Check phy result
355 02:12:58.469682 INFO : End of initialization
356 02:12:58.490780 INFO : End of 2D read delay Voltage center optimization
357 02:12:58.511010 INFO : End of 2D read delay Voltage center optimization
358 02:12:58.563001 INFO : End of 2D write delay Voltage center optimization
359 02:12:58.612401 INFO : End of 2D write delay Voltage center optimization
360 02:12:58.617971 INFO : Training has run successfully!
361 02:12:58.618592
362 02:12:58.619010 channel==0
363 02:12:58.623511 RxClkDly_Margin_A0==88 ps 9
364 02:12:58.624086 TxDqDly_Margin_A0==98 ps 10
365 02:12:58.629120 RxClkDly_Margin_A1==88 ps 9
366 02:12:58.629646 TxDqDly_Margin_A1==88 ps 9
367 02:12:58.630058 TrainedVREFDQ_A0==74
368 02:12:58.634696 TrainedVREFDQ_A1==74
369 02:12:58.635219 VrefDac_Margin_A0==25
370 02:12:58.635622 DeviceVref_Margin_A0==40
371 02:12:58.640302 VrefDac_Margin_A1==25
372 02:12:58.640812 DeviceVref_Margin_A1==40
373 02:12:58.641222
374 02:12:58.641620
375 02:12:58.642016 channel==1
376 02:12:58.645858 RxClkDly_Margin_A0==98 ps 10
377 02:12:58.646351 TxDqDly_Margin_A0==88 ps 9
378 02:12:58.651451 RxClkDly_Margin_A1==98 ps 10
379 02:12:58.651942 TxDqDly_Margin_A1==88 ps 9
380 02:12:58.657079 TrainedVREFDQ_A0==77
381 02:12:58.657571 TrainedVREFDQ_A1==77
382 02:12:58.657975 VrefDac_Margin_A0==22
383 02:12:58.662641 DeviceVref_Margin_A0==37
384 02:12:58.663135 VrefDac_Margin_A1==22
385 02:12:58.668387 DeviceVref_Margin_A1==37
386 02:12:58.668961
387 02:12:58.669374 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 02:12:58.669771
389 02:12:58.701810 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 02:12:58.702430 2D training succeed
391 02:12:58.707492 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 02:12:58.713099 auto size-- 65535DDR cs0 size: 2048MB
393 02:12:58.713585 DDR cs1 size: 2048MB
394 02:12:58.718705 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 02:12:58.719225 cs0 DataBus test pass
396 02:12:58.724290 cs1 DataBus test pass
397 02:12:58.724775 cs0 AddrBus test pass
398 02:12:58.725169 cs1 AddrBus test pass
399 02:12:58.725563
400 02:12:58.729863 100bdlr_step_size ps== 420
401 02:12:58.730364 result report
402 02:12:58.735501 boot times 0Enable ddr reg access
403 02:12:58.740740 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 02:12:58.754190 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 02:12:59.327909 0.0;M3 CHK:0;cm4_sp_mode 0
406 02:12:59.328591 MVN_1=0x00000000
407 02:12:59.333495 MVN_2=0x00000000
408 02:12:59.339108 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 02:12:59.339582 OPS=0x10
410 02:12:59.340018 ring efuse init
411 02:12:59.340422 chipver efuse init
412 02:12:59.344687 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 02:12:59.350307 [0.018961 Inits done]
414 02:12:59.350782 secure task start!
415 02:12:59.351183 high task start!
416 02:12:59.354886 low task start!
417 02:12:59.355354 run into bl31
418 02:12:59.361538 NOTICE: BL31: v1.3(release):4fc40b1
419 02:12:59.369355 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 02:12:59.369838 NOTICE: BL31: G12A normal boot!
421 02:12:59.395361 NOTICE: BL31: BL33 decompress pass
422 02:12:59.400938 ERROR: Error initializing runtime service opteed_fast
423 02:13:00.634066
424 02:13:00.634725
425 02:13:00.642619 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 02:13:00.643198
427 02:13:00.643634 Model: Libre Computer AML-A311D-CC Alta
428 02:13:00.851265 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 02:13:00.874341 DRAM: 2 GiB (effective 3.8 GiB)
430 02:13:01.017253 Core: 408 devices, 31 uclasses, devicetree: separate
431 02:13:01.023172 WDT: Not starting watchdog@f0d0
432 02:13:01.055470 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 02:13:01.067815 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 02:13:01.072966 ** Bad device specification mmc 0 **
435 02:13:01.083189 Card did not respond to voltage select! : -110
436 02:13:01.090877 ** Bad device specification mmc 0 **
437 02:13:01.091439 Couldn't find partition mmc 0
438 02:13:01.099411 Card did not respond to voltage select! : -110
439 02:13:01.104663 ** Bad device specification mmc 0 **
440 02:13:01.105184 Couldn't find partition mmc 0
441 02:13:01.109834 Error: could not access storage.
442 02:13:02.372794 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 02:13:02.373736 bl2_stage_init 0x01
444 02:13:02.374093 bl2_stage_init 0x81
445 02:13:02.378174 hw id: 0x0000 - pwm id 0x01
446 02:13:02.378621 bl2_stage_init 0xc1
447 02:13:02.379244 bl2_stage_init 0x02
448 02:13:02.379892
449 02:13:02.383890 L0:00000000
450 02:13:02.384447 L1:20000703
451 02:13:02.384901 L2:00008067
452 02:13:02.385344 L3:14000000
453 02:13:02.389582 B2:00402000
454 02:13:02.390074 B1:e0f83180
455 02:13:02.390522
456 02:13:02.390970 TE: 58167
457 02:13:02.391416
458 02:13:02.395024 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 02:13:02.395535
460 02:13:02.396007 Board ID = 1
461 02:13:02.401067 Set A53 clk to 24M
462 02:13:02.401650 Set A73 clk to 24M
463 02:13:02.402101 Set clk81 to 24M
464 02:13:02.406217 A53 clk: 1200 MHz
465 02:13:02.406707 A73 clk: 1200 MHz
466 02:13:02.407150 CLK81: 166.6M
467 02:13:02.407580 smccc: 00012abd
468 02:13:02.411843 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 02:13:02.417349 board id: 1
470 02:13:02.423259 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 02:13:02.433969 fw parse done
472 02:13:02.439917 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 02:13:02.482370 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 02:13:02.493248 PIEI prepare done
475 02:13:02.493744 fastboot data load
476 02:13:02.494192 fastboot data verify
477 02:13:02.499025 verify result: 266
478 02:13:02.504574 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 02:13:02.505080 LPDDR4 probe
480 02:13:02.505528 ddr clk to 1584MHz
481 02:13:02.512625 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 02:13:02.549998
483 02:13:02.550655 dmc_version 0001
484 02:13:02.556534 Check phy result
485 02:13:02.562341 INFO : End of CA training
486 02:13:02.562712 INFO : End of initialization
487 02:13:02.567933 INFO : Training has run successfully!
488 02:13:02.568825 Check phy result
489 02:13:02.573723 INFO : End of initialization
490 02:13:02.574394 INFO : End of read enable training
491 02:13:02.576900 INFO : End of fine write leveling
492 02:13:02.582424 INFO : End of Write leveling coarse delay
493 02:13:02.588018 INFO : Training has run successfully!
494 02:13:02.588695 Check phy result
495 02:13:02.589220 INFO : End of initialization
496 02:13:02.593592 INFO : End of read dq deskew training
497 02:13:02.599139 INFO : End of MPR read delay center optimization
498 02:13:02.599805 INFO : End of write delay center optimization
499 02:13:02.604730 INFO : End of read delay center optimization
500 02:13:02.610420 INFO : End of max read latency training
501 02:13:02.611136 INFO : Training has run successfully!
502 02:13:02.615958 1D training succeed
503 02:13:02.622034 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 02:13:02.669565 Check phy result
505 02:13:02.670284 INFO : End of initialization
506 02:13:02.690636 INFO : End of 2D read delay Voltage center optimization
507 02:13:02.711230 INFO : End of 2D read delay Voltage center optimization
508 02:13:02.763156 INFO : End of 2D write delay Voltage center optimization
509 02:13:02.812444 INFO : End of 2D write delay Voltage center optimization
510 02:13:02.818139 INFO : Training has run successfully!
511 02:13:02.818878
512 02:13:02.819511 channel==0
513 02:13:02.823502 RxClkDly_Margin_A0==88 ps 9
514 02:13:02.824214 TxDqDly_Margin_A0==98 ps 10
515 02:13:02.826927 RxClkDly_Margin_A1==88 ps 9
516 02:13:02.827594 TxDqDly_Margin_A1==98 ps 10
517 02:13:02.832443 TrainedVREFDQ_A0==74
518 02:13:02.833159 TrainedVREFDQ_A1==76
519 02:13:02.838108 VrefDac_Margin_A0==25
520 02:13:02.838870 DeviceVref_Margin_A0==40
521 02:13:02.839469 VrefDac_Margin_A1==25
522 02:13:02.843688 DeviceVref_Margin_A1==38
523 02:13:02.844729
524 02:13:02.845371
525 02:13:02.845792 channel==1
526 02:13:02.846193 RxClkDly_Margin_A0==98 ps 10
527 02:13:02.849202 TxDqDly_Margin_A0==98 ps 10
528 02:13:02.849671 RxClkDly_Margin_A1==98 ps 10
529 02:13:02.854811 TxDqDly_Margin_A1==88 ps 9
530 02:13:02.855334 TrainedVREFDQ_A0==77
531 02:13:02.855747 TrainedVREFDQ_A1==77
532 02:13:02.860397 VrefDac_Margin_A0==22
533 02:13:02.860901 DeviceVref_Margin_A0==37
534 02:13:02.866002 VrefDac_Margin_A1==24
535 02:13:02.866459 DeviceVref_Margin_A1==37
536 02:13:02.866860
537 02:13:02.871650 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 02:13:02.872149
539 02:13:02.899619 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
540 02:13:02.905060 2D training succeed
541 02:13:02.910653 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 02:13:02.911206 auto size-- 65535DDR cs0 size: 2048MB
543 02:13:02.916252 DDR cs1 size: 2048MB
544 02:13:02.916778 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 02:13:02.921912 cs0 DataBus test pass
546 02:13:02.922386 cs1 DataBus test pass
547 02:13:02.922791 cs0 AddrBus test pass
548 02:13:02.927488 cs1 AddrBus test pass
549 02:13:02.928042
550 02:13:02.928463 100bdlr_step_size ps== 420
551 02:13:02.928875 result report
552 02:13:02.933077 boot times 0Enable ddr reg access
553 02:13:02.941011 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 02:13:02.954363 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 02:13:03.526421 0.0;M3 CHK:0;cm4_sp_mode 0
556 02:13:03.527042 MVN_1=0x00000000
557 02:13:03.531956 MVN_2=0x00000000
558 02:13:03.537864 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 02:13:03.538390 OPS=0x10
560 02:13:03.538813 ring efuse init
561 02:13:03.539215 chipver efuse init
562 02:13:03.543238 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 02:13:03.548871 [0.018961 Inits done]
564 02:13:03.549396 secure task start!
565 02:13:03.549796 high task start!
566 02:13:03.553431 low task start!
567 02:13:03.554058 run into bl31
568 02:13:03.560093 NOTICE: BL31: v1.3(release):4fc40b1
569 02:13:03.568063 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 02:13:03.569011 NOTICE: BL31: G12A normal boot!
571 02:13:03.593314 NOTICE: BL31: BL33 decompress pass
572 02:13:03.598929 ERROR: Error initializing runtime service opteed_fast
573 02:13:04.831769
574 02:13:04.832413
575 02:13:04.840351 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 02:13:04.841143
577 02:13:04.841874 Model: Libre Computer AML-A311D-CC Alta
578 02:13:05.049575 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 02:13:05.072573 DRAM: 2 GiB (effective 3.8 GiB)
580 02:13:05.214990 Core: 408 devices, 31 uclasses, devicetree: separate
581 02:13:05.220830 WDT: Not starting watchdog@f0d0
582 02:13:05.253458 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 02:13:05.265537 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 02:13:05.270515 ** Bad device specification mmc 0 **
585 02:13:05.280971 Card did not respond to voltage select! : -110
586 02:13:05.287713 ** Bad device specification mmc 0 **
587 02:13:05.288328 Couldn't find partition mmc 0
588 02:13:05.296866 Card did not respond to voltage select! : -110
589 02:13:05.302378 ** Bad device specification mmc 0 **
590 02:13:05.302882 Couldn't find partition mmc 0
591 02:13:05.307455 Error: could not access storage.
592 02:13:05.651039 Net: eth0: ethernet@ff3f0000
593 02:13:05.651939 starting USB...
594 02:13:05.902802 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 02:13:05.903225 Starting the controller
596 02:13:05.909821 USB XHCI 1.10
597 02:13:07.622460 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 02:13:07.623083 bl2_stage_init 0x01
599 02:13:07.623537 bl2_stage_init 0x81
600 02:13:07.628096 hw id: 0x0000 - pwm id 0x01
601 02:13:07.628568 bl2_stage_init 0xc1
602 02:13:07.629032 bl2_stage_init 0x02
603 02:13:07.629461
604 02:13:07.633701 L0:00000000
605 02:13:07.634160 L1:20000703
606 02:13:07.634576 L2:00008067
607 02:13:07.634986 L3:14000000
608 02:13:07.636635 B2:00402000
609 02:13:07.637094 B1:e0f83180
610 02:13:07.637514
611 02:13:07.637937 TE: 58124
612 02:13:07.638352
613 02:13:07.647645 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 02:13:07.648149
615 02:13:07.648578 Board ID = 1
616 02:13:07.649004 Set A53 clk to 24M
617 02:13:07.649432 Set A73 clk to 24M
618 02:13:07.653251 Set clk81 to 24M
619 02:13:07.653705 A53 clk: 1200 MHz
620 02:13:07.654123 A73 clk: 1200 MHz
621 02:13:07.656754 CLK81: 166.6M
622 02:13:07.657197 smccc: 00012a91
623 02:13:07.662258 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 02:13:07.667921 board id: 1
625 02:13:07.672274 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 02:13:07.683796 fw parse done
627 02:13:07.688917 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 02:13:07.731494 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 02:13:07.743323 PIEI prepare done
630 02:13:07.743791 fastboot data load
631 02:13:07.744259 fastboot data verify
632 02:13:07.748900 verify result: 266
633 02:13:07.754526 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 02:13:07.754986 LPDDR4 probe
635 02:13:07.755405 ddr clk to 1584MHz
636 02:13:07.761514 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 02:13:07.798786
638 02:13:07.799316 dmc_version 0001
639 02:13:07.805570 Check phy result
640 02:13:07.812273 INFO : End of CA training
641 02:13:07.812730 INFO : End of initialization
642 02:13:07.817854 INFO : Training has run successfully!
643 02:13:07.818295 Check phy result
644 02:13:07.823521 INFO : End of initialization
645 02:13:07.823956 INFO : End of read enable training
646 02:13:07.826815 INFO : End of fine write leveling
647 02:13:07.832317 INFO : End of Write leveling coarse delay
648 02:13:07.838053 INFO : Training has run successfully!
649 02:13:07.838513 Check phy result
650 02:13:07.838922 INFO : End of initialization
651 02:13:07.843499 INFO : End of read dq deskew training
652 02:13:07.846902 INFO : End of MPR read delay center optimization
653 02:13:07.852622 INFO : End of write delay center optimization
654 02:13:07.858072 INFO : End of read delay center optimization
655 02:13:07.858525 INFO : End of max read latency training
656 02:13:07.863712 INFO : Training has run successfully!
657 02:13:07.864193 1D training succeed
658 02:13:07.870895 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 02:13:07.918687 Check phy result
660 02:13:07.919153 INFO : End of initialization
661 02:13:07.941150 INFO : End of 2D read delay Voltage center optimization
662 02:13:07.961340 INFO : End of 2D read delay Voltage center optimization
663 02:13:08.013016 INFO : End of 2D write delay Voltage center optimization
664 02:13:08.063194 INFO : End of 2D write delay Voltage center optimization
665 02:13:08.068761 INFO : Training has run successfully!
666 02:13:08.069231
667 02:13:08.069641 channel==0
668 02:13:08.074333 RxClkDly_Margin_A0==88 ps 9
669 02:13:08.074801 TxDqDly_Margin_A0==98 ps 10
670 02:13:08.079906 RxClkDly_Margin_A1==88 ps 9
671 02:13:08.080394 TxDqDly_Margin_A1==88 ps 9
672 02:13:08.080824 TrainedVREFDQ_A0==74
673 02:13:08.085496 TrainedVREFDQ_A1==75
674 02:13:08.085970 VrefDac_Margin_A0==25
675 02:13:08.086400 DeviceVref_Margin_A0==40
676 02:13:08.091212 VrefDac_Margin_A1==25
677 02:13:08.092146 DeviceVref_Margin_A1==39
678 02:13:08.092889
679 02:13:08.093644
680 02:13:08.094324 channel==1
681 02:13:08.096760 RxClkDly_Margin_A0==98 ps 10
682 02:13:08.097565 TxDqDly_Margin_A0==88 ps 9
683 02:13:08.102385 RxClkDly_Margin_A1==98 ps 10
684 02:13:08.103135 TxDqDly_Margin_A1==88 ps 9
685 02:13:08.107933 TrainedVREFDQ_A0==77
686 02:13:08.108695 TrainedVREFDQ_A1==77
687 02:13:08.109431 VrefDac_Margin_A0==22
688 02:13:08.113578 DeviceVref_Margin_A0==37
689 02:13:08.114347 VrefDac_Margin_A1==22
690 02:13:08.119254 DeviceVref_Margin_A1==37
691 02:13:08.120020
692 02:13:08.120735 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 02:13:08.121467
694 02:13:08.152680 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
695 02:13:08.153117 2D training succeed
696 02:13:08.158367 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 02:13:08.164076 auto size-- 65535DDR cs0 size: 2048MB
698 02:13:08.164907 DDR cs1 size: 2048MB
699 02:13:08.169513 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 02:13:08.170005 cs0 DataBus test pass
701 02:13:08.175132 cs1 DataBus test pass
702 02:13:08.175632 cs0 AddrBus test pass
703 02:13:08.176091 cs1 AddrBus test pass
704 02:13:08.176519
705 02:13:08.180708 100bdlr_step_size ps== 420
706 02:13:08.181221 result report
707 02:13:08.186336 boot times 0Enable ddr reg access
708 02:13:08.190594 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 02:13:08.204073 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 02:13:08.777131 0.0;M3 CHK:0;cm4_sp_mode 0
711 02:13:08.777773 MVN_1=0x00000000
712 02:13:08.782723 MVN_2=0x00000000
713 02:13:08.788391 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 02:13:08.788938 OPS=0x10
715 02:13:08.789348 ring efuse init
716 02:13:08.789747 chipver efuse init
717 02:13:08.793995 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 02:13:08.799600 [0.018961 Inits done]
719 02:13:08.799874 secure task start!
720 02:13:08.800110 high task start!
721 02:13:08.804166 low task start!
722 02:13:08.804630 run into bl31
723 02:13:08.810859 NOTICE: BL31: v1.3(release):4fc40b1
724 02:13:08.818626 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 02:13:08.819093 NOTICE: BL31: G12A normal boot!
726 02:13:08.844091 NOTICE: BL31: BL33 decompress pass
727 02:13:08.849729 ERROR: Error initializing runtime service opteed_fast
728 02:13:10.082448
729 02:13:10.082885
730 02:13:10.089816 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 02:13:10.090111
732 02:13:10.090352 Model: Libre Computer AML-A311D-CC Alta
733 02:13:10.299416 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 02:13:10.322745 DRAM: 2 GiB (effective 3.8 GiB)
735 02:13:10.465763 Core: 408 devices, 31 uclasses, devicetree: separate
736 02:13:10.471552 WDT: Not starting watchdog@f0d0
737 02:13:10.503788 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 02:13:10.516277 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 02:13:10.521155 ** Bad device specification mmc 0 **
740 02:13:10.531493 Card did not respond to voltage select! : -110
741 02:13:10.539189 ** Bad device specification mmc 0 **
742 02:13:10.539572 Couldn't find partition mmc 0
743 02:13:10.547495 Card did not respond to voltage select! : -110
744 02:13:10.552993 ** Bad device specification mmc 0 **
745 02:13:10.553313 Couldn't find partition mmc 0
746 02:13:10.558076 Error: could not access storage.
747 02:13:10.900578 Net: eth0: ethernet@ff3f0000
748 02:13:10.901201 starting USB...
749 02:13:11.152403 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 02:13:11.153017 Starting the controller
751 02:13:11.159343 USB XHCI 1.10
752 02:13:13.324433 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 02:13:13.325087 bl2_stage_init 0x01
754 02:13:13.325537 bl2_stage_init 0x81
755 02:13:13.329895 hw id: 0x0000 - pwm id 0x01
756 02:13:13.330399 bl2_stage_init 0xc1
757 02:13:13.330827 bl2_stage_init 0x02
758 02:13:13.331251
759 02:13:13.335512 L0:00000000
760 02:13:13.336037 L1:20000703
761 02:13:13.336475 L2:00008067
762 02:13:13.336915 L3:14000000
763 02:13:13.338705 B2:00402000
764 02:13:13.340200 B1:e0f83180
765 02:13:13.340945
766 02:13:13.344542 TE: 58159
767 02:13:13.346330
768 02:13:13.350763 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 02:13:13.352780
770 02:13:13.354122 Board ID = 1
771 02:13:13.354841 Set A53 clk to 24M
772 02:13:13.357451 Set A73 clk to 24M
773 02:13:13.359130 Set clk81 to 24M
774 02:13:13.360098 A53 clk: 1200 MHz
775 02:13:13.360887 A73 clk: 1200 MHz
776 02:13:13.361752 CLK81: 166.6M
777 02:13:13.364067 smccc: 00012ab5
778 02:13:13.367102 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 02:13:13.368254 board id: 1
780 02:13:13.375014 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 02:13:13.386835 fw parse done
782 02:13:13.391750 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 02:13:13.433439 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 02:13:13.445787 PIEI prepare done
785 02:13:13.446562 fastboot data load
786 02:13:13.446997 fastboot data verify
787 02:13:13.450748 verify result: 266
788 02:13:13.456283 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 02:13:13.456803 LPDDR4 probe
790 02:13:13.457243 ddr clk to 1584MHz
791 02:13:13.463322 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 02:13:13.501119
793 02:13:13.501698 dmc_version 0001
794 02:13:13.507438 Check phy result
795 02:13:13.514163 INFO : End of CA training
796 02:13:13.514753 INFO : End of initialization
797 02:13:13.519638 INFO : Training has run successfully!
798 02:13:13.520237 Check phy result
799 02:13:13.525228 INFO : End of initialization
800 02:13:13.525771 INFO : End of read enable training
801 02:13:13.530826 INFO : End of fine write leveling
802 02:13:13.536486 INFO : End of Write leveling coarse delay
803 02:13:13.537005 INFO : Training has run successfully!
804 02:13:13.537439 Check phy result
805 02:13:13.542104 INFO : End of initialization
806 02:13:13.542611 INFO : End of read dq deskew training
807 02:13:13.547666 INFO : End of MPR read delay center optimization
808 02:13:13.553250 INFO : End of write delay center optimization
809 02:13:13.558840 INFO : End of read delay center optimization
810 02:13:13.559346 INFO : End of max read latency training
811 02:13:13.564455 INFO : Training has run successfully!
812 02:13:13.564962 1D training succeed
813 02:13:13.573488 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 02:13:13.620820 Check phy result
815 02:13:13.621406 INFO : End of initialization
816 02:13:13.642030 INFO : End of 2D read delay Voltage center optimization
817 02:13:13.662712 INFO : End of 2D read delay Voltage center optimization
818 02:13:13.715079 INFO : End of 2D write delay Voltage center optimization
819 02:13:13.764620 INFO : End of 2D write delay Voltage center optimization
820 02:13:13.770155 INFO : Training has run successfully!
821 02:13:13.770639
822 02:13:13.771065 channel==0
823 02:13:13.775747 RxClkDly_Margin_A0==88 ps 9
824 02:13:13.776240 TxDqDly_Margin_A0==98 ps 10
825 02:13:13.781484 RxClkDly_Margin_A1==88 ps 9
826 02:13:13.781947 TxDqDly_Margin_A1==88 ps 9
827 02:13:13.782376 TrainedVREFDQ_A0==74
828 02:13:13.787023 TrainedVREFDQ_A1==74
829 02:13:13.787500 VrefDac_Margin_A0==25
830 02:13:13.787899 DeviceVref_Margin_A0==40
831 02:13:13.792571 VrefDac_Margin_A1==25
832 02:13:13.793055 DeviceVref_Margin_A1==40
833 02:13:13.793485
834 02:13:13.793891
835 02:13:13.794292 channel==1
836 02:13:13.798183 RxClkDly_Margin_A0==98 ps 10
837 02:13:13.798629 TxDqDly_Margin_A0==88 ps 9
838 02:13:13.803735 RxClkDly_Margin_A1==88 ps 9
839 02:13:13.804215 TxDqDly_Margin_A1==88 ps 9
840 02:13:13.809484 TrainedVREFDQ_A0==77
841 02:13:13.809937 TrainedVREFDQ_A1==77
842 02:13:13.810336 VrefDac_Margin_A0==22
843 02:13:13.814964 DeviceVref_Margin_A0==37
844 02:13:13.815416 VrefDac_Margin_A1==24
845 02:13:13.820574 DeviceVref_Margin_A1==37
846 02:13:13.821043
847 02:13:13.821436 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 02:13:13.821824
849 02:13:13.854148 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 0000005f
850 02:13:13.854556 2D training succeed
851 02:13:13.859712 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 02:13:13.865427 auto size-- 65535DDR cs0 size: 2048MB
853 02:13:13.865798 DDR cs1 size: 2048MB
854 02:13:13.870863 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 02:13:13.871145 cs0 DataBus test pass
856 02:13:13.876499 cs1 DataBus test pass
857 02:13:13.876745 cs0 AddrBus test pass
858 02:13:13.876949 cs1 AddrBus test pass
859 02:13:13.877149
860 02:13:13.882096 100bdlr_step_size ps== 420
861 02:13:13.882335 result report
862 02:13:13.887695 boot times 0Enable ddr reg access
863 02:13:13.892241 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 02:13:13.906374 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 02:13:14.480102 0.0;M3 CHK:0;cm4_sp_mode 0
866 02:13:14.480792 MVN_1=0x00000000
867 02:13:14.485540 MVN_2=0x00000000
868 02:13:14.491313 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 02:13:14.491861 OPS=0x10
870 02:13:14.492379 ring efuse init
871 02:13:14.492840 chipver efuse init
872 02:13:14.496914 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 02:13:14.502562 [0.018960 Inits done]
874 02:13:14.503070 secure task start!
875 02:13:14.503524 high task start!
876 02:13:14.506250 low task start!
877 02:13:14.506743 run into bl31
878 02:13:14.513780 NOTICE: BL31: v1.3(release):4fc40b1
879 02:13:14.520959 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 02:13:14.521473 NOTICE: BL31: G12A normal boot!
881 02:13:14.546888 NOTICE: BL31: BL33 decompress pass
882 02:13:14.552047 ERROR: Error initializing runtime service opteed_fast
883 02:13:15.785617
884 02:13:15.786280
885 02:13:15.793282 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 02:13:15.793790
887 02:13:15.794255 Model: Libre Computer AML-A311D-CC Alta
888 02:13:16.001934 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 02:13:16.024796 DRAM: 2 GiB (effective 3.8 GiB)
890 02:13:16.168884 Core: 408 devices, 31 uclasses, devicetree: separate
891 02:13:16.174447 WDT: Not starting watchdog@f0d0
892 02:13:16.206834 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 02:13:16.219278 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 02:13:16.224278 ** Bad device specification mmc 0 **
895 02:13:16.234605 Card did not respond to voltage select! : -110
896 02:13:16.241723 ** Bad device specification mmc 0 **
897 02:13:16.242224 Couldn't find partition mmc 0
898 02:13:16.250537 Card did not respond to voltage select! : -110
899 02:13:16.256081 ** Bad device specification mmc 0 **
900 02:13:16.256572 Couldn't find partition mmc 0
901 02:13:16.261107 Error: could not access storage.
902 02:13:16.604532 Net: eth0: ethernet@ff3f0000
903 02:13:16.604953 starting USB...
904 02:13:16.856584 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 02:13:16.857010 Starting the controller
906 02:13:16.862818 USB XHCI 1.10
907 02:13:18.724338 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 02:13:18.724759 bl2_stage_init 0x01
909 02:13:18.724972 bl2_stage_init 0x81
910 02:13:18.729889 hw id: 0x0000 - pwm id 0x01
911 02:13:18.730180 bl2_stage_init 0xc1
912 02:13:18.730406 bl2_stage_init 0x02
913 02:13:18.730610
914 02:13:18.735429 L0:00000000
915 02:13:18.735820 L1:20000703
916 02:13:18.736207 L2:00008067
917 02:13:18.736649 L3:14000000
918 02:13:18.738329 B2:00402000
919 02:13:18.738689 B1:e0f83180
920 02:13:18.738994
921 02:13:18.739297 TE: 58124
922 02:13:18.739521
923 02:13:18.749609 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 02:13:18.749925
925 02:13:18.750135 Board ID = 1
926 02:13:18.750336 Set A53 clk to 24M
927 02:13:18.750548 Set A73 clk to 24M
928 02:13:18.755101 Set clk81 to 24M
929 02:13:18.755509 A53 clk: 1200 MHz
930 02:13:18.755820 A73 clk: 1200 MHz
931 02:13:18.760627 CLK81: 166.6M
932 02:13:18.760906 smccc: 00012a92
933 02:13:18.766262 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 02:13:18.766550 board id: 1
935 02:13:18.775053 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 02:13:18.785573 fw parse done
937 02:13:18.791583 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 02:13:18.834102 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 02:13:18.844995 PIEI prepare done
940 02:13:18.845556 fastboot data load
941 02:13:18.846038 fastboot data verify
942 02:13:18.850560 verify result: 266
943 02:13:18.856215 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 02:13:18.856710 LPDDR4 probe
945 02:13:18.857153 ddr clk to 1584MHz
946 02:13:18.864282 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 02:13:18.901423
948 02:13:18.901969 dmc_version 0001
949 02:13:18.908114 Check phy result
950 02:13:18.913970 INFO : End of CA training
951 02:13:18.914464 INFO : End of initialization
952 02:13:18.919591 INFO : Training has run successfully!
953 02:13:18.920139 Check phy result
954 02:13:18.925228 INFO : End of initialization
955 02:13:18.925752 INFO : End of read enable training
956 02:13:18.928486 INFO : End of fine write leveling
957 02:13:18.934031 INFO : End of Write leveling coarse delay
958 02:13:18.939639 INFO : Training has run successfully!
959 02:13:18.940182 Check phy result
960 02:13:18.940654 INFO : End of initialization
961 02:13:18.945300 INFO : End of read dq deskew training
962 02:13:18.948651 INFO : End of MPR read delay center optimization
963 02:13:18.954269 INFO : End of write delay center optimization
964 02:13:18.959787 INFO : End of read delay center optimization
965 02:13:18.960378 INFO : End of max read latency training
966 02:13:18.965340 INFO : Training has run successfully!
967 02:13:18.965900 1D training succeed
968 02:13:18.973661 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 02:13:19.021228 Check phy result
970 02:13:19.021901 INFO : End of initialization
971 02:13:19.042831 INFO : End of 2D read delay Voltage center optimization
972 02:13:19.062947 INFO : End of 2D read delay Voltage center optimization
973 02:13:19.114867 INFO : End of 2D write delay Voltage center optimization
974 02:13:19.164120 INFO : End of 2D write delay Voltage center optimization
975 02:13:19.169793 INFO : Training has run successfully!
976 02:13:19.170408
977 02:13:19.170924 channel==0
978 02:13:19.175325 RxClkDly_Margin_A0==88 ps 9
979 02:13:19.175896 TxDqDly_Margin_A0==98 ps 10
980 02:13:19.178572 RxClkDly_Margin_A1==88 ps 9
981 02:13:19.179105 TxDqDly_Margin_A1==88 ps 9
982 02:13:19.184106 TrainedVREFDQ_A0==74
983 02:13:19.184667 TrainedVREFDQ_A1==74
984 02:13:19.185151 VrefDac_Margin_A0==25
985 02:13:19.189698 DeviceVref_Margin_A0==40
986 02:13:19.190239 VrefDac_Margin_A1==25
987 02:13:19.195332 DeviceVref_Margin_A1==40
988 02:13:19.195868
989 02:13:19.196421
990 02:13:19.196879 channel==1
991 02:13:19.197321 RxClkDly_Margin_A0==98 ps 10
992 02:13:19.200835 TxDqDly_Margin_A0==98 ps 10
993 02:13:19.201346 RxClkDly_Margin_A1==98 ps 10
994 02:13:19.206508 TxDqDly_Margin_A1==98 ps 10
995 02:13:19.207000 TrainedVREFDQ_A0==77
996 02:13:19.207457 TrainedVREFDQ_A1==77
997 02:13:19.212136 VrefDac_Margin_A0==22
998 02:13:19.212633 DeviceVref_Margin_A0==37
999 02:13:19.217725 VrefDac_Margin_A1==22
1000 02:13:19.218216 DeviceVref_Margin_A1==37
1001 02:13:19.218669
1002 02:13:19.223331 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 02:13:19.223825
1004 02:13:19.251357 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1005 02:13:19.256899 2D training succeed
1006 02:13:19.262370 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 02:13:19.262874 auto size-- 65535DDR cs0 size: 2048MB
1008 02:13:19.268048 DDR cs1 size: 2048MB
1009 02:13:19.268558 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 02:13:19.273587 cs0 DataBus test pass
1011 02:13:19.274093 cs1 DataBus test pass
1012 02:13:19.274558 cs0 AddrBus test pass
1013 02:13:19.279261 cs1 AddrBus test pass
1014 02:13:19.279756
1015 02:13:19.280268 100bdlr_step_size ps== 420
1016 02:13:19.280734 result report
1017 02:13:19.284762 boot times 0Enable ddr reg access
1018 02:13:19.292585 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 02:13:19.306029 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 02:13:19.878681 0.0;M3 CHK:0;cm4_sp_mode 0
1021 02:13:19.879362 MVN_1=0x00000000
1022 02:13:19.883581 MVN_2=0x00000000
1023 02:13:19.889332 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 02:13:19.889856 OPS=0x10
1025 02:13:19.890344 ring efuse init
1026 02:13:19.890801 chipver efuse init
1027 02:13:19.894952 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 02:13:19.900540 [0.018961 Inits done]
1029 02:13:19.901056 secure task start!
1030 02:13:19.901536 high task start!
1031 02:13:19.905102 low task start!
1032 02:13:19.905598 run into bl31
1033 02:13:19.911716 NOTICE: BL31: v1.3(release):4fc40b1
1034 02:13:19.919560 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 02:13:19.920102 NOTICE: BL31: G12A normal boot!
1036 02:13:19.945185 NOTICE: BL31: BL33 decompress pass
1037 02:13:19.950617 ERROR: Error initializing runtime service opteed_fast
1038 02:13:21.183601
1039 02:13:21.184055
1040 02:13:21.192428 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 02:13:21.192763
1042 02:13:21.192992 Model: Libre Computer AML-A311D-CC Alta
1043 02:13:21.400464 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 02:13:21.423829 DRAM: 2 GiB (effective 3.8 GiB)
1045 02:13:21.568275 Core: 408 devices, 31 uclasses, devicetree: separate
1046 02:13:21.576282 WDT: Not starting watchdog@f0d0
1047 02:13:21.604876 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 02:13:21.617323 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 02:13:21.622257 ** Bad device specification mmc 0 **
1050 02:13:21.632596 Card did not respond to voltage select! : -110
1051 02:13:21.640269 ** Bad device specification mmc 0 **
1052 02:13:21.640774 Couldn't find partition mmc 0
1053 02:13:21.648608 Card did not respond to voltage select! : -110
1054 02:13:21.654088 ** Bad device specification mmc 0 **
1055 02:13:21.654574 Couldn't find partition mmc 0
1056 02:13:21.659141 Error: could not access storage.
1057 02:13:22.000942 Net: eth0: ethernet@ff3f0000
1058 02:13:22.001574 starting USB...
1059 02:13:22.253474 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 02:13:22.254110 Starting the controller
1061 02:13:22.259697 USB XHCI 1.10
1062 02:13:23.814484 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 02:13:23.822175 scanning usb for storage devices... 0 Storage Device(s) found
1065 02:13:23.873901 Hit any key to stop autoboot: 1
1066 02:13:23.874742 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1067 02:13:23.875372 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1068 02:13:23.875871 Setting prompt string to ['=>']
1069 02:13:23.876438 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1070 02:13:23.879482 0
1071 02:13:23.880390 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 02:13:23.880913 Sending with 10 millisecond of delay
1074 02:13:25.016756 => setenv autoload no
1075 02:13:25.027390 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1076 02:13:25.032456 setenv autoload no
1077 02:13:25.033226 Sending with 10 millisecond of delay
1079 02:13:26.831562 => setenv initrd_high 0xffffffff
1080 02:13:26.842372 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1081 02:13:26.843177 setenv initrd_high 0xffffffff
1082 02:13:26.843882 Sending with 10 millisecond of delay
1084 02:13:28.461574 => setenv fdt_high 0xffffffff
1085 02:13:28.472627 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1086 02:13:28.473833 setenv fdt_high 0xffffffff
1087 02:13:28.474878 Sending with 10 millisecond of delay
1089 02:13:28.767195 => dhcp
1090 02:13:28.778297 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1091 02:13:28.779436 dhcp
1092 02:13:28.780133 Speed: 1000, full duplex
1093 02:13:28.780798 BOOTP broadcast 1
1094 02:13:28.787626 DHCP client bound to address 192.168.6.27 (10 ms)
1095 02:13:28.788735 Sending with 10 millisecond of delay
1097 02:13:30.468072 => setenv serverip 192.168.6.2
1098 02:13:30.478913 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1099 02:13:30.479888 setenv serverip 192.168.6.2
1100 02:13:30.480683 Sending with 10 millisecond of delay
1102 02:13:34.204904 => tftpboot 0x01080000 957406/tftp-deploy-fl7e1zea/kernel/uImage
1103 02:13:34.215740 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1104 02:13:34.216694 tftpboot 0x01080000 957406/tftp-deploy-fl7e1zea/kernel/uImage
1105 02:13:34.217206 Speed: 1000, full duplex
1106 02:13:34.217673 Using ethernet@ff3f0000 device
1107 02:13:34.218463 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1108 02:13:34.223771 Filename '957406/tftp-deploy-fl7e1zea/kernel/uImage'.
1109 02:13:34.227652 Load address: 0x1080000
1110 02:13:37.091795 Loading: *################################################## 43.6 MiB
1111 02:13:37.092522 15.2 MiB/s
1112 02:13:37.093020 done
1113 02:13:37.096218 Bytes transferred = 45716032 (2b99240 hex)
1114 02:13:37.097068 Sending with 10 millisecond of delay
1116 02:13:41.788772 => tftpboot 0x08000000 957406/tftp-deploy-fl7e1zea/ramdisk/ramdisk.cpio.gz.uboot
1117 02:13:41.799743 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1118 02:13:41.800826 tftpboot 0x08000000 957406/tftp-deploy-fl7e1zea/ramdisk/ramdisk.cpio.gz.uboot
1119 02:13:41.801335 Speed: 1000, full duplex
1120 02:13:41.801829 Using ethernet@ff3f0000 device
1121 02:13:41.802735 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1122 02:13:41.814399 Filename '957406/tftp-deploy-fl7e1zea/ramdisk/ramdisk.cpio.gz.uboot'.
1123 02:13:41.814738 Load address: 0x8000000
1124 02:13:48.597827 Loading: *###################T ############################## UDP wrong checksum 00000005 000018d6
1125 02:13:53.598312 T UDP wrong checksum 00000005 000018d6
1126 02:14:03.600897 T UDP wrong checksum 00000005 000018d6
1127 02:14:23.606309 T T T T T UDP wrong checksum 00000005 000018d6
1128 02:14:38.610822 T T
1129 02:14:38.611518 Retry count exceeded; starting again
1131 02:14:38.613123 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1134 02:14:38.615175 end: 2.4 uboot-commands (duration 00:01:53) [common]
1136 02:14:38.616755 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1138 02:14:38.617932 end: 2 uboot-action (duration 00:01:53) [common]
1140 02:14:38.619583 Cleaning after the job
1141 02:14:38.620211 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957406/tftp-deploy-fl7e1zea/ramdisk
1142 02:14:38.621543 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957406/tftp-deploy-fl7e1zea/kernel
1143 02:14:38.668589 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957406/tftp-deploy-fl7e1zea/dtb
1144 02:14:38.669374 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957406/tftp-deploy-fl7e1zea/modules
1145 02:14:38.688873 start: 4.1 power-off (timeout 00:00:30) [common]
1146 02:14:38.689508 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1147 02:14:38.723111 >> OK - accepted request
1148 02:14:38.725392 Returned 0 in 0 seconds
1149 02:14:38.826109 end: 4.1 power-off (duration 00:00:00) [common]
1151 02:14:38.827059 start: 4.2 read-feedback (timeout 00:10:00) [common]
1152 02:14:38.827707 Listened to connection for namespace 'common' for up to 1s
1153 02:14:39.828250 Finalising connection for namespace 'common'
1154 02:14:39.829047 Disconnecting from shell: Finalise
1155 02:14:39.829621 =>
1156 02:14:39.930717 end: 4.2 read-feedback (duration 00:00:01) [common]
1157 02:14:39.931405 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/957406
1158 02:14:40.228381 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/957406
1159 02:14:40.228993 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.