Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 00:50:14.329928 lava-dispatcher, installed at version: 2023.08
2 00:50:14.330246 start: 0 validate
3 00:50:14.330426 Start time: 2024-11-11 00:50:14.330414+00:00 (UTC)
4 00:50:14.330653 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz exists
5 00:50:14.821227 Validating that http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-415-g0e90fad093db9/arm/multi_v7_defconfig/gcc-12/kernel/zImage exists
6 00:50:14.934885 Validating that http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-415-g0e90fad093db9/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb exists
7 00:50:15.048252 Validating that http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz exists
8 00:50:15.161962 Validating that http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-415-g0e90fad093db9/arm/multi_v7_defconfig/gcc-12/modules.tar.xz exists
9 00:50:15.280329 validate duration: 0.95
11 00:50:15.281135 start: 1 tftp-deploy (timeout 00:10:00) [common]
12 00:50:15.281481 start: 1.1 download-retry (timeout 00:10:00) [common]
13 00:50:15.281788 start: 1.1.1 http-download (timeout 00:10:00) [common]
14 00:50:15.282245 Not decompressing ramdisk as can be used compressed.
15 00:50:15.282539 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
16 00:50:15.282778 saving as /var/lib/lava/dispatcher/tmp/1221114/tftp-deploy-z1p4nya7/ramdisk/initrd.cpio.gz
17 00:50:15.283021 total size: 4775763 (4 MB)
18 00:50:15.515993 progress 0 % (0 MB)
19 00:50:15.853755 progress 5 % (0 MB)
20 00:50:16.074836 progress 10 % (0 MB)
21 00:50:16.095324 progress 15 % (0 MB)
22 00:50:16.104473 progress 20 % (0 MB)
23 00:50:16.200459 progress 25 % (1 MB)
24 00:50:16.302328 progress 30 % (1 MB)
25 00:50:16.408003 progress 35 % (1 MB)
26 00:50:16.429292 progress 40 % (1 MB)
27 00:50:16.531536 progress 45 % (2 MB)
28 00:50:16.632039 progress 50 % (2 MB)
29 00:50:16.656242 progress 55 % (2 MB)
30 00:50:16.756657 progress 60 % (2 MB)
31 00:50:16.857222 progress 65 % (2 MB)
32 00:50:16.880455 progress 70 % (3 MB)
33 00:50:16.980454 progress 75 % (3 MB)
34 00:50:17.080019 progress 80 % (3 MB)
35 00:50:17.099774 progress 85 % (3 MB)
36 00:50:17.202046 progress 90 % (4 MB)
37 00:50:17.299561 progress 95 % (4 MB)
38 00:50:17.319969 progress 100 % (4 MB)
39 00:50:17.320486 4 MB downloaded in 2.04 s (2.24 MB/s)
40 00:50:17.320844 end: 1.1.1 http-download (duration 00:00:02) [common]
42 00:50:17.321439 end: 1.1 download-retry (duration 00:00:02) [common]
43 00:50:17.321653 start: 1.2 download-retry (timeout 00:09:58) [common]
44 00:50:17.321859 start: 1.2.1 http-download (timeout 00:09:58) [common]
45 00:50:17.322157 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-415-g0e90fad093db9/arm/multi_v7_defconfig/gcc-12/kernel/zImage
46 00:50:17.322305 saving as /var/lib/lava/dispatcher/tmp/1221114/tftp-deploy-z1p4nya7/kernel/zImage
47 00:50:17.322469 total size: 11448832 (10 MB)
48 00:50:17.322631 No compression specified
49 00:50:17.437559 progress 0 % (0 MB)
50 00:50:17.784802 progress 5 % (0 MB)
51 00:50:18.015281 progress 10 % (1 MB)
52 00:50:18.322982 progress 15 % (1 MB)
53 00:50:18.464451 progress 20 % (2 MB)
54 00:50:18.712189 progress 25 % (2 MB)
55 00:50:18.911584 progress 30 % (3 MB)
56 00:50:19.135727 progress 35 % (3 MB)
57 00:50:19.342921 progress 40 % (4 MB)
58 00:50:19.563146 progress 45 % (4 MB)
59 00:50:19.777043 progress 50 % (5 MB)
60 00:50:19.995015 progress 55 % (6 MB)
61 00:50:20.151722 progress 60 % (6 MB)
62 00:50:20.370504 progress 65 % (7 MB)
63 00:50:20.562628 progress 70 % (7 MB)
64 00:50:20.778909 progress 75 % (8 MB)
65 00:50:20.988349 progress 80 % (8 MB)
66 00:50:21.152336 progress 85 % (9 MB)
67 00:50:21.347212 progress 90 % (9 MB)
68 00:50:21.556628 progress 95 % (10 MB)
69 00:50:21.765774 progress 100 % (10 MB)
70 00:50:21.766364 10 MB downloaded in 4.44 s (2.46 MB/s)
71 00:50:21.766812 end: 1.2.1 http-download (duration 00:00:04) [common]
73 00:50:21.767624 end: 1.2 download-retry (duration 00:00:04) [common]
74 00:50:21.767914 start: 1.3 download-retry (timeout 00:09:54) [common]
75 00:50:21.768194 start: 1.3.1 http-download (timeout 00:09:54) [common]
76 00:50:21.768595 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-415-g0e90fad093db9/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
77 00:50:21.768849 saving as /var/lib/lava/dispatcher/tmp/1221114/tftp-deploy-z1p4nya7/dtb/am335x-boneblack.dtb
78 00:50:21.769066 total size: 70568 (0 MB)
79 00:50:21.769283 No compression specified
80 00:50:21.884984 progress 46 % (0 MB)
81 00:50:21.887763 progress 92 % (0 MB)
82 00:50:21.888757 progress 100 % (0 MB)
83 00:50:21.889157 0 MB downloaded in 0.12 s (0.56 MB/s)
84 00:50:21.889561 end: 1.3.1 http-download (duration 00:00:00) [common]
86 00:50:21.890360 end: 1.3 download-retry (duration 00:00:00) [common]
87 00:50:21.890641 start: 1.4 download-retry (timeout 00:09:53) [common]
88 00:50:21.890926 start: 1.4.1 http-download (timeout 00:09:53) [common]
89 00:50:21.891285 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
90 00:50:21.891514 saving as /var/lib/lava/dispatcher/tmp/1221114/tftp-deploy-z1p4nya7/nfsrootfs/full.rootfs.tar
91 00:50:21.891731 total size: 117747780 (112 MB)
92 00:50:21.891956 Using unxz to decompress xz
93 00:50:22.007999 progress 0 % (0 MB)
94 00:50:24.473863 progress 5 % (5 MB)
95 00:50:26.575204 progress 10 % (11 MB)
96 00:50:28.584232 progress 15 % (16 MB)
97 00:50:30.576326 progress 20 % (22 MB)
98 00:50:32.439017 progress 25 % (28 MB)
99 00:50:34.014155 progress 30 % (33 MB)
100 00:50:35.271967 progress 35 % (39 MB)
101 00:50:36.360385 progress 40 % (44 MB)
102 00:50:37.249913 progress 45 % (50 MB)
103 00:50:38.024781 progress 50 % (56 MB)
104 00:50:38.691060 progress 55 % (61 MB)
105 00:50:39.286990 progress 60 % (67 MB)
106 00:50:39.818084 progress 65 % (73 MB)
107 00:50:40.435501 progress 70 % (78 MB)
108 00:50:40.942406 progress 75 % (84 MB)
109 00:50:41.530434 progress 80 % (89 MB)
110 00:50:42.096742 progress 85 % (95 MB)
111 00:50:42.639800 progress 90 % (101 MB)
112 00:50:43.158250 progress 95 % (106 MB)
113 00:50:43.666051 progress 100 % (112 MB)
114 00:50:43.669629 112 MB downloaded in 21.78 s (5.16 MB/s)
115 00:50:43.669963 end: 1.4.1 http-download (duration 00:00:22) [common]
117 00:50:43.670562 end: 1.4 download-retry (duration 00:00:22) [common]
118 00:50:43.670773 start: 1.5 download-retry (timeout 00:09:32) [common]
119 00:50:43.670983 start: 1.5.1 http-download (timeout 00:09:32) [common]
120 00:50:43.671299 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-415-g0e90fad093db9/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
121 00:50:43.671460 saving as /var/lib/lava/dispatcher/tmp/1221114/tftp-deploy-z1p4nya7/modules/modules.tar
122 00:50:43.671621 total size: 6609812 (6 MB)
123 00:50:43.671784 Using unxz to decompress xz
124 00:50:43.787090 progress 0 % (0 MB)
125 00:50:44.016113 progress 5 % (0 MB)
126 00:50:44.232799 progress 10 % (0 MB)
127 00:50:44.262802 progress 15 % (0 MB)
128 00:50:44.342722 progress 20 % (1 MB)
129 00:50:44.368368 progress 25 % (1 MB)
130 00:50:44.393376 progress 30 % (1 MB)
131 00:50:44.500071 progress 35 % (2 MB)
132 00:50:44.585051 progress 40 % (2 MB)
133 00:50:44.609965 progress 45 % (2 MB)
134 00:50:44.797180 progress 50 % (3 MB)
135 00:50:44.820931 progress 55 % (3 MB)
136 00:50:44.849161 progress 60 % (3 MB)
137 00:50:44.908982 progress 65 % (4 MB)
138 00:50:44.949198 progress 70 % (4 MB)
139 00:50:45.047287 progress 75 % (4 MB)
140 00:50:45.140983 progress 80 % (5 MB)
141 00:50:45.176419 progress 85 % (5 MB)
142 00:50:45.274808 progress 90 % (5 MB)
143 00:50:45.368562 progress 95 % (6 MB)
144 00:50:45.400073 progress 100 % (6 MB)
145 00:50:45.403558 6 MB downloaded in 1.73 s (3.64 MB/s)
146 00:50:45.403897 end: 1.5.1 http-download (duration 00:00:02) [common]
148 00:50:45.404500 end: 1.5 download-retry (duration 00:00:02) [common]
149 00:50:45.404729 start: 1.6 prepare-tftp-overlay (timeout 00:09:30) [common]
150 00:50:45.404963 start: 1.6.1 extract-nfsrootfs (timeout 00:09:30) [common]
151 00:50:50.970672 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/1221114/extract-nfsrootfs-fi8dgaby
152 00:50:50.970977 end: 1.6.1 extract-nfsrootfs (duration 00:00:06) [common]
153 00:50:50.971128 start: 1.6.2 lava-overlay (timeout 00:09:24) [common]
154 00:50:50.971422 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4
155 00:50:50.971612 makedir: /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin
156 00:50:50.971756 makedir: /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/tests
157 00:50:50.971905 makedir: /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/results
158 00:50:50.972066 Creating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-add-keys
159 00:50:50.972289 Creating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-add-sources
160 00:50:50.972468 Creating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-background-process-start
161 00:50:50.972646 Creating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-background-process-stop
162 00:50:50.972845 Creating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-common-functions
163 00:50:50.973019 Creating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-echo-ipv4
164 00:50:50.973192 Creating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-install-packages
165 00:50:50.973364 Creating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-installed-packages
166 00:50:50.973535 Creating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-os-build
167 00:50:50.973706 Creating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-probe-channel
168 00:50:50.973876 Creating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-probe-ip
169 00:50:50.974049 Creating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-target-ip
170 00:50:50.974218 Creating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-target-mac
171 00:50:50.974386 Creating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-target-storage
172 00:50:50.974559 Creating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-test-case
173 00:50:50.974730 Creating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-test-event
174 00:50:50.974898 Creating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-test-feedback
175 00:50:50.975066 Creating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-test-raise
176 00:50:50.975235 Creating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-test-reference
177 00:50:50.975403 Creating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-test-runner
178 00:50:50.975572 Creating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-test-set
179 00:50:50.975739 Creating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-test-shell
180 00:50:50.975910 Updating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-add-keys (debian)
181 00:50:50.976133 Updating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-add-sources (debian)
182 00:50:50.976328 Updating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-install-packages (debian)
183 00:50:50.976520 Updating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-installed-packages (debian)
184 00:50:50.976852 Updating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/bin/lava-os-build (debian)
185 00:50:50.977024 Creating /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/environment
186 00:50:50.977154 LAVA metadata
187 00:50:50.977254 - LAVA_JOB_ID=1221114
188 00:50:50.977351 - LAVA_DISPATCHER_IP=192.168.11.5
189 00:50:50.977494 start: 1.6.2.1 ssh-authorize (timeout 00:09:24) [common]
190 00:50:50.977826 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
191 00:50:50.977951 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:24) [common]
192 00:50:50.978052 skipped lava-vland-overlay
193 00:50:50.978172 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
194 00:50:50.978290 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:24) [common]
195 00:50:50.978386 skipped lava-multinode-overlay
196 00:50:50.978498 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
197 00:50:50.978614 start: 1.6.2.4 test-definition (timeout 00:09:24) [common]
198 00:50:50.978715 Loading test definitions
199 00:50:50.978838 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:24) [common]
200 00:50:50.978938 Using /lava-1221114 at stage 0
201 00:50:50.979344 uuid=1221114_1.6.2.4.1 testdef=None
202 00:50:50.979467 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
203 00:50:50.979585 start: 1.6.2.4.2 test-overlay (timeout 00:09:24) [common]
204 00:50:50.980194 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
206 00:50:50.980530 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:24) [common]
207 00:50:50.981323 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
209 00:50:50.981669 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:24) [common]
210 00:50:50.982453 runner path: /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/0/tests/0_timesync-off test_uuid 1221114_1.6.2.4.1
211 00:50:50.982658 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
213 00:50:50.982999 start: 1.6.2.4.5 git-repo-action (timeout 00:09:24) [common]
214 00:50:50.983102 Using /lava-1221114 at stage 0
215 00:50:50.983242 Fetching tests from https://github.com/kernelci/test-definitions.git
216 00:50:50.983346 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/0/tests/1_kselftest-dt'
217 00:50:55.872211 Running '/usr/bin/git checkout kernelci.org
218 00:50:56.091527 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
219 00:50:56.092339 uuid=1221114_1.6.2.4.5 testdef=None
220 00:50:56.092546 end: 1.6.2.4.5 git-repo-action (duration 00:00:05) [common]
222 00:50:56.093026 start: 1.6.2.4.6 test-overlay (timeout 00:09:19) [common]
223 00:50:56.094557 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
225 00:50:56.095045 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:19) [common]
226 00:50:56.097171 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
228 00:50:56.097678 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:19) [common]
229 00:50:56.099725 runner path: /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/0/tests/1_kselftest-dt test_uuid 1221114_1.6.2.4.5
230 00:50:56.099890 BOARD='beaglebone-black'
231 00:50:56.100024 BRANCH='next'
232 00:50:56.100152 SKIPFILE='/dev/null'
233 00:50:56.100278 SKIP_INSTALL='True'
234 00:50:56.100403 TESTPROG_URL='http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-415-g0e90fad093db9/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
235 00:50:56.100532 TST_CASENAME=''
236 00:50:56.100656 TST_CMDFILES='dt'
237 00:50:56.100899 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
239 00:50:56.101217 Creating lava-test-runner.conf files
240 00:50:56.101309 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/1221114/lava-overlay-4ght74l4/lava-1221114/0 for stage 0
241 00:50:56.101436 - 0_timesync-off
242 00:50:56.101538 - 1_kselftest-dt
243 00:50:56.101671 end: 1.6.2.4 test-definition (duration 00:00:05) [common]
244 00:50:56.101786 start: 1.6.2.5 compress-overlay (timeout 00:09:19) [common]
245 00:51:04.633449 end: 1.6.2.5 compress-overlay (duration 00:00:09) [common]
246 00:51:04.633670 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
247 00:51:04.633819 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
248 00:51:04.633970 end: 1.6.2 lava-overlay (duration 00:00:14) [common]
249 00:51:04.634113 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
250 00:51:04.758202 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
251 00:51:04.758517 start: 1.6.4 extract-modules (timeout 00:09:11) [common]
252 00:51:04.758709 extracting modules file /var/lib/lava/dispatcher/tmp/1221114/tftp-deploy-z1p4nya7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1221114/extract-nfsrootfs-fi8dgaby
253 00:51:05.064762 extracting modules file /var/lib/lava/dispatcher/tmp/1221114/tftp-deploy-z1p4nya7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/1221114/extract-overlay-ramdisk-wq0sxbfa/ramdisk
254 00:51:05.372053 end: 1.6.4 extract-modules (duration 00:00:01) [common]
255 00:51:05.372278 start: 1.6.5 apply-overlay-tftp (timeout 00:09:10) [common]
256 00:51:05.372418 [common] Applying overlay to NFS
257 00:51:05.372527 [common] Applying overlay /var/lib/lava/dispatcher/tmp/1221114/compress-overlay-ey5wvgvl/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/1221114/extract-nfsrootfs-fi8dgaby
258 00:51:06.556662 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
259 00:51:06.556919 start: 1.6.6 prepare-kernel (timeout 00:09:09) [common]
260 00:51:06.557103 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:09) [common]
261 00:51:06.557289 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
262 00:51:06.557463 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
263 00:51:06.557634 start: 1.6.7 configure-preseed-file (timeout 00:09:09) [common]
264 00:51:06.557808 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
265 00:51:06.557984 start: 1.6.8 compress-ramdisk (timeout 00:09:09) [common]
266 00:51:06.558135 Building ramdisk /var/lib/lava/dispatcher/tmp/1221114/extract-overlay-ramdisk-wq0sxbfa/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/1221114/extract-overlay-ramdisk-wq0sxbfa/ramdisk
267 00:51:06.866082 >> 74903 blocks
268 00:51:08.797093 Adding RAMdisk u-boot header.
269 00:51:08.797390 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/1221114/extract-overlay-ramdisk-wq0sxbfa/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/1221114/extract-overlay-ramdisk-wq0sxbfa/ramdisk.cpio.gz.uboot
270 00:51:08.949221 output: Image Name:
271 00:51:08.949563 output: Created: Mon Nov 11 00:51:08 2024
272 00:51:08.949811 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
273 00:51:08.950049 output: Data Size: 14795571 Bytes = 14448.80 KiB = 14.11 MiB
274 00:51:08.950282 output: Load Address: 00000000
275 00:51:08.950511 output: Entry Point: 00000000
276 00:51:08.950741 output:
277 00:51:08.951120 rename /var/lib/lava/dispatcher/tmp/1221114/extract-overlay-ramdisk-wq0sxbfa/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/1221114/tftp-deploy-z1p4nya7/ramdisk/ramdisk.cpio.gz.uboot
278 00:51:08.951488 end: 1.6.8 compress-ramdisk (duration 00:00:02) [common]
279 00:51:08.951791 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
280 00:51:08.952103 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:06) [common]
281 00:51:08.952337 No LXC device requested
282 00:51:08.952650 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
283 00:51:08.953000 start: 1.8 deploy-device-env (timeout 00:09:06) [common]
284 00:51:08.953307 end: 1.8 deploy-device-env (duration 00:00:00) [common]
285 00:51:08.953546 Checking files for TFTP limit of 4294967296 bytes.
286 00:51:08.954860 end: 1 tftp-deploy (duration 00:00:54) [common]
287 00:51:08.955178 start: 2 uboot-action (timeout 00:05:00) [common]
288 00:51:08.955497 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
289 00:51:08.955804 end: 2.1 uboot-from-media (duration 00:00:00) [common]
290 00:51:08.956116 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
291 00:51:08.956560 substitutions:
292 00:51:08.956820 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
293 00:51:08.957072 - {DTB_ADDR}: 0x88000000
294 00:51:08.957327 - {DTB}: 1221114/tftp-deploy-z1p4nya7/dtb/am335x-boneblack.dtb
295 00:51:08.957581 - {INITRD}: 1221114/tftp-deploy-z1p4nya7/ramdisk/ramdisk.cpio.gz.uboot
296 00:51:08.957827 - {KERNEL_ADDR}: 0x82000000
297 00:51:08.958076 - {KERNEL}: 1221114/tftp-deploy-z1p4nya7/kernel/zImage
298 00:51:08.958328 - {LAVA_MAC}: None
299 00:51:08.958597 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/1221114/extract-nfsrootfs-fi8dgaby
300 00:51:08.958832 - {NFS_SERVER_IP}: 192.168.11.5
301 00:51:08.959087 - {PRESEED_CONFIG}: None
302 00:51:08.959334 - {PRESEED_LOCAL}: None
303 00:51:08.959582 - {RAMDISK_ADDR}: 0x83000000
304 00:51:08.959828 - {RAMDISK}: 1221114/tftp-deploy-z1p4nya7/ramdisk/ramdisk.cpio.gz.uboot
305 00:51:08.960074 - {ROOT_PART}: None
306 00:51:08.960315 - {ROOT}: None
307 00:51:08.960559 - {SERVER_IP}: 192.168.11.5
308 00:51:08.960838 - {TEE_ADDR}: 0x83000000
309 00:51:08.961080 - {TEE}: None
310 00:51:08.961322 Parsed boot commands:
311 00:51:08.961558 - setenv autoload no
312 00:51:08.961798 - setenv initrd_high 0xffffffff
313 00:51:08.962040 - setenv fdt_high 0xffffffff
314 00:51:08.962282 - dhcp
315 00:51:08.962521 - setenv serverip 192.168.11.5
316 00:51:08.962763 - tftp 0x82000000 1221114/tftp-deploy-z1p4nya7/kernel/zImage
317 00:51:08.963006 - tftp 0x83000000 1221114/tftp-deploy-z1p4nya7/ramdisk/ramdisk.cpio.gz.uboot
318 00:51:08.963249 - setenv initrd_size ${filesize}
319 00:51:08.963488 - tftp 0x88000000 1221114/tftp-deploy-z1p4nya7/dtb/am335x-boneblack.dtb
320 00:51:08.963719 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1221114/extract-nfsrootfs-fi8dgaby,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
321 00:51:08.963957 - bootz 0x82000000 0x83000000 0x88000000
322 00:51:08.964269 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
324 00:51:08.964955 start: 2.3 connect-device (timeout 00:05:00) [common]
325 00:51:08.965056 [common] connect-device Connecting to device using 'telnet 127.0.0.1 63003'
326 00:51:09.329195 Setting prompt string to ['lava-test: # ']
327 00:51:09.329636 end: 2.3 connect-device (duration 00:00:00) [common]
328 00:51:09.329787 start: 2.4 uboot-commands (timeout 00:05:00) [common]
329 00:51:09.329971 start: 2.4.1 reset-device (timeout 00:05:00) [common]
330 00:51:09.330104 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
331 00:51:09.330429 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/reset'
332 00:51:09.696903 Returned 0 in 0 seconds
333 00:51:09.797750 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
335 00:51:09.798636 end: 2.4.1 reset-device (duration 00:00:00) [common]
336 00:51:09.798965 start: 2.4.2 bootloader-interrupt (timeout 00:04:59) [common]
337 00:51:09.799255 Setting prompt string to ['Press SPACE to abort autoboot in 2 seconds']
338 00:51:09.799502 bootloader-interrupt: Wait for prompt ['Press SPACE to abort autoboot in 2 seconds'] (timeout 00:05:00)
339 00:51:09.800239 Trying 127.0.0.1...
340 00:51:09.800474 Connected to 127.0.0.1.
341 00:51:09.800683 Escape character is '^]'.
342 00:51:14.709617
343 00:51:14.713204 U-Boot SPL 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500)
344 00:51:14.769838 Trying to boot from MMC2
345 00:51:14.818213 Loading Environment from EXT4... Card did not respond to voltage select!
346 00:51:14.885424
347 00:51:14.885698
348 00:51:14.890888 U-Boot 2019.04-00002-gf15b99f0b6 (Oct 01 2019 - 09:28:05 -0500), Build: jenkins-github_Bootloader-Builder-131
349 00:51:14.891163
350 00:51:14.895824 CPU : AM335X-GP rev 2.1
351 00:51:14.949824 I2C: ready
352 00:51:14.950093 DRAM: 512 MiB
353 00:51:15.004029 No match for driver 'omap_hsmmc'
354 00:51:15.009652 No match for driver 'omap_hsmmc'
355 00:51:15.009931 Some drivers were not found
356 00:51:15.015860 Reset Source: Power-on reset has occurred.
357 00:51:15.016138 RTC 32KCLK Source: External.
358 00:51:15.023444 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
359 00:51:15.036705 Loading Environment from EXT4... Card did not respond to voltage select!
360 00:51:15.101277 Board: BeagleBone Black
361 00:51:15.105181 <ethaddr> not set. Validating first E-fuse MAC
362 00:51:15.161748 BeagleBone Black:
363 00:51:15.162064 BeagleBone: cape eeprom: i2c_probe: 0x54:
364 00:51:15.167350 BeagleBone: cape eeprom: i2c_probe: 0x55:
365 00:51:15.173351 BeagleBone: cape eeprom: i2c_probe: 0x56:
366 00:51:15.173616 BeagleBone: cape eeprom: i2c_probe: 0x57:
367 00:51:15.178272 Net: eth0: MII MODE
368 00:51:15.187671 cpsw, usb_ether
369 00:51:15.187945 Press SPACE to abort autoboot in 2 seconds
370 00:51:15.238745 end: 2.4.2 bootloader-interrupt (duration 00:00:05) [common]
371 00:51:15.239123 start: 2.4.3 bootloader-commands (timeout 00:04:54) [common]
372 00:51:15.239430 Setting prompt string to ['=> ']
373 00:51:15.239696 bootloader-commands: Wait for prompt ['=> '] (timeout 00:04:54)
374 00:51:15.242850 Setting prompt string to ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
375 00:51:15.243159 Sending with 10 millisecond of delay
377 00:51:16.377722 => setenv autoload no
378 00:51:16.388210 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:53)
379 00:51:16.390599 setenv autoload no
380 00:51:16.391062 Sending with 10 millisecond of delay
382 00:51:18.188099 => setenv initrd_high 0xffffffff
383 00:51:18.198617 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:51)
384 00:51:18.199091 setenv initrd_high 0xffffffff
385 00:51:18.199540 Sending with 10 millisecond of delay
387 00:51:19.815794 => setenv fdt_high 0xffffffff
388 00:51:19.826297 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
389 00:51:19.826754 setenv fdt_high 0xffffffff
390 00:51:19.827197 Sending with 10 millisecond of delay
392 00:51:20.118641 => dhcp
393 00:51:20.129027 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:49)
394 00:51:20.129461 dhcp
395 00:51:20.129692 link up on port 0, speed 100, full duplex
396 00:51:20.129912 BOOTP broadcast 1
397 00:51:20.138160 DHCP client bound to address 192.168.11.3 (4 ms)
398 00:51:20.138643 Sending with 10 millisecond of delay
400 00:51:21.875324 => setenv serverip 192.168.11.5
401 00:51:21.885828 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:47)
402 00:51:21.886301 setenv serverip 192.168.11.5
403 00:51:21.886750 Sending with 10 millisecond of delay
405 00:51:25.429768 => tftp 0x82000000 1221114/tftp-deploy-z1p4nya7/kernel/zImage
406 00:51:25.440242 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:44)
407 00:51:25.440774 tftp 0x82000000 1221114/tftp-deploy-z1p4nya7/kernel/zImage
408 00:51:25.441051 link up on port 0, speed 100, full duplex
409 00:51:25.441301 Using cpsw device
410 00:51:25.444493 TFTP from server 192.168.11.5; our IP address is 192.168.11.3
411 00:51:25.450059 Filename '1221114/tftp-deploy-z1p4nya7/kernel/zImage'.
412 00:51:25.457064 Load address: 0x82000000
413 00:51:25.651938 Loading: *#################################################################
414 00:51:25.826682 #################################################################
415 00:51:26.001416 #################################################################
416 00:51:26.176167 #################################################################
417 00:51:26.346244 #################################################################
418 00:51:26.513409 #################################################################
419 00:51:26.708355 #################################################################
420 00:51:26.883141 #################################################################
421 00:51:27.057008 #################################################################
422 00:51:27.231769 #################################################################
423 00:51:27.405909 #################################################################
424 00:51:27.576637 #################################################################
425 00:51:27.576979 5.2 MiB/s
426 00:51:27.577227 done
427 00:51:27.579314 Bytes transferred = 11448832 (aeb200 hex)
428 00:51:27.579784 Sending with 10 millisecond of delay
430 00:51:32.086372 => tftp 0x83000000 1221114/tftp-deploy-z1p4nya7/ramdisk/ramdisk.cpio.gz.uboot
431 00:51:32.096862 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:37)
432 00:51:32.097359 tftp 0x83000000 1221114/tftp-deploy-z1p4nya7/ramdisk/ramdisk.cpio.gz.uboot
433 00:51:32.097605 link up on port 0, speed 100, full duplex
434 00:51:32.097842 Using cpsw device
435 00:51:32.101108 TFTP from server 192.168.11.5; our IP address is 192.168.11.3
436 00:51:32.163804 Filename '1221114/tftp-deploy-z1p4nya7/ramdisk/ramdisk.cpio.gz.uboot'.
437 00:51:32.164076 Load address: 0x83000000
438 00:51:32.296626 Loading: *#################################################################
439 00:51:32.485654 #################################################################
440 00:51:32.658555 #################################################################
441 00:51:32.833086 #################################################################
442 00:51:33.017984 #################################################################
443 00:51:33.193418 #################################################################
444 00:51:33.369058 #################################################################
445 00:51:33.566131 #################################################################
446 00:51:33.717788 #################################################################
447 00:51:33.891203 #################################################################
448 00:51:34.065888 #################################################################
449 00:51:34.239280 #################################################################
450 00:51:34.413907 #################################################################
451 00:51:34.588681 #################################################################
452 00:51:34.758507 #################################################################
453 00:51:34.843878 #################################
454 00:51:34.844184 5.2 MiB/s
455 00:51:34.844446 done
456 00:51:34.849323 Bytes transferred = 14795635 (e1c373 hex)
457 00:51:34.849811 Sending with 10 millisecond of delay
459 00:51:36.706988 => setenv initrd_size ${filesize}
460 00:51:36.717495 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:32)
461 00:51:36.717964 setenv initrd_size ${filesize}
462 00:51:36.718412 Sending with 10 millisecond of delay
464 00:51:40.924071 => tftp 0x88000000 1221114/tftp-deploy-z1p4nya7/dtb/am335x-boneblack.dtb
465 00:51:40.934544 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:28)
466 00:51:40.935000 tftp 0x88000000 1221114/tftp-deploy-z1p4nya7/dtb/am335x-boneblack.dtb
467 00:51:40.935232 link up on port 0, speed 100, full duplex
468 00:51:40.935469 Using cpsw device
469 00:51:40.938674 TFTP from server 192.168.11.5; our IP address is 192.168.11.3
470 00:51:40.963496 Filename '1221114/tftp-deploy-z1p4nya7/dtb/am335x-boneblack.dtb'.
471 00:51:40.963794 Load address: 0x88000000
472 00:51:40.964038 Loading: *#####
473 00:51:40.964270 4.8 MiB/s
474 00:51:40.970171 done
475 00:51:40.970436 Bytes transferred = 70568 (113a8 hex)
476 00:51:40.970870 Sending with 10 millisecond of delay
478 00:51:54.269775 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1221114/extract-nfsrootfs-fi8dgaby,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
479 00:51:54.280261 bootloader-commands: Wait for prompt ['=> ', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:15)
480 00:51:54.280731 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1221114/extract-nfsrootfs-fi8dgaby,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
481 00:51:54.281190 Sending with 10 millisecond of delay
483 00:51:56.620097 => bootz 0x82000000 0x83000000 0x88000000
484 00:51:56.630595 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
485 00:51:56.630924 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:04:12)
486 00:51:56.631508 bootz 0x82000000 0x83000000 0x88000000
487 00:51:56.631759 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 00:51:56.632248 Image Name:
489 00:51:56.632475 Created: 2024-11-11 0:51:08 UTC
490 00:51:56.637891 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 00:51:56.643393 Data Size: 14795571 Bytes = 14.1 MiB
492 00:51:56.643668 Load Address: 00000000
493 00:51:56.650563 Entry Point: 00000000
494 00:51:56.787945 Verifying Checksum ... OK
495 00:51:56.788285 ## Flattened Device Tree blob at 88000000
496 00:51:56.794525 Booting using the fdt blob at 0x88000000
497 00:51:56.799353 Using Device Tree in place at 88000000, end 880143a7
498 00:51:56.807053
499 00:51:56.807331 Starting kernel ...
500 00:51:56.807556
501 00:51:56.808098 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 00:51:56.808398 start: 2.4.4 auto-login-action (timeout 00:04:12) [common]
503 00:51:56.808653 Setting prompt string to ['Linux version [0-9]']
504 00:51:56.808915 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid']
505 00:51:56.809163 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image', 'Ramdisk image is corrupt or invalid'] (timeout 00:05:00)
506 00:51:57.653644 [ 0.000000] Booting Linux on physical CPU 0x0
507 00:51:57.659700 start: 2.4.4.1 login-action (timeout 00:04:11) [common]
508 00:51:57.660005 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 00:51:57.660258 Setting prompt string to []
510 00:51:57.660517 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 00:51:57.660789 Using line separator: #'\n'#
512 00:51:57.661008 No login prompt set.
513 00:51:57.661233 Parsing kernel messages
514 00:51:57.661437 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 00:51:57.661822 [login-action] Waiting for messages, (timeout 00:04:11)
516 00:51:57.676458 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j372296-arm-gcc-12-multi-v7-defconfig-cqkrh) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Mon Nov 11 00:21:46 UTC 2024
517 00:51:57.682230 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
518 00:51:57.687978 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
519 00:51:57.699325 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
520 00:51:57.705112 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
521 00:51:57.710828 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
522 00:51:57.711103 [ 0.000000] Memory policy: Data cache writeback
523 00:51:57.717485 [ 0.000000] efi: UEFI not found.
524 00:51:57.723048 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
525 00:51:57.728699 [ 0.000000] Zone ranges:
526 00:51:57.734466 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
527 00:51:57.740232 [ 0.000000] Normal empty
528 00:51:57.740508 [ 0.000000] HighMem empty
529 00:51:57.745844 [ 0.000000] Movable zone start for each node
530 00:51:57.746120 [ 0.000000] Early memory node ranges
531 00:51:57.757355 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
532 00:51:57.762651 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
533 00:51:57.788222 [ 0.000000] CPU: All CPU(s) started in SVC mode.
534 00:51:57.793663 [ 0.000000] AM335X ES2.1 (sgx neon)
535 00:51:57.805341 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
536 00:51:57.823107 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.11.5:/var/lib/lava/dispatcher/tmp/1221114/extract-nfsrootfs-fi8dgaby,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
537 00:51:57.834602 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
538 00:51:57.840338 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
539 00:51:57.846088 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
540 00:51:57.856266 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
541 00:51:57.885233 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
542 00:51:57.891226 <6>[ 0.000000] trace event string verifier disabled
543 00:51:57.891502 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
544 00:51:57.896969 <6>[ 0.000000] rcu: RCU event tracing is enabled.
545 00:51:57.908351 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
546 00:51:57.914091 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
547 00:51:57.921422 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
548 00:51:57.936430 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
549 00:51:57.953604 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
550 00:51:57.960298 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
551 00:51:58.052846 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
552 00:51:58.064331 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
553 00:51:58.071092 <6>[ 0.008336] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
554 00:51:58.084160 <6>[ 0.019150] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
555 00:51:58.091496 <6>[ 0.033967] Console: colour dummy device 80x30
556 00:51:58.097421 Matched prompt #6: WARNING:
557 00:51:58.097709 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
558 00:51:58.102959 <3>[ 0.038868] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
559 00:51:58.108721 <3>[ 0.045936] This ensures that you still see kernel messages. Please
560 00:51:58.111920 <3>[ 0.052661] update your kernel commandline.
561 00:51:58.152587 <6>[ 0.057272] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
562 00:51:58.158355 <6>[ 0.096147] CPU: Testing write buffer coherency: ok
563 00:51:58.164349 <6>[ 0.101512] CPU0: Spectre v2: using BPIALL workaround
564 00:51:58.164624 <6>[ 0.106978] pid_max: default: 32768 minimum: 301
565 00:51:58.175827 <6>[ 0.112169] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
566 00:51:58.182608 <6>[ 0.119988] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 00:51:58.189634 <6>[ 0.129342] CPU0: thread -1, cpu 0, socket -1, mpidr 0
568 00:51:58.255341 <6>[ 0.189531] Setting up static identity map for 0x80300000 - 0x803000ac
569 00:51:58.261086 <6>[ 0.199125] rcu: Hierarchical SRCU implementation.
570 00:51:58.264776 <6>[ 0.204408] rcu: Max phase no-delay instances is 1000.
571 00:51:58.273243 <6>[ 0.215427] EFI services will not be available.
572 00:51:58.278999 <6>[ 0.220767] smp: Bringing up secondary CPUs ...
573 00:51:58.284840 <6>[ 0.225738] smp: Brought up 1 node, 1 CPU
574 00:51:58.290577 <6>[ 0.230229] SMP: Total of 1 processors activated (996.14 BogoMIPS).
575 00:51:58.296456 <6>[ 0.236948] CPU: All CPU(s) started in SVC mode.
576 00:51:58.316885 <6>[ 0.242151] Memory: 405992K/522240K available (16384K kernel code, 2543K rwdata, 6788K rodata, 2048K init, 430K bss, 49056K reserved, 65536K cma-reserved, 0K highmem)
577 00:51:58.317169 <6>[ 0.258424] devtmpfs: initialized
578 00:51:58.339195 <6>[ 0.275596] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
579 00:51:58.350698 <6>[ 0.284199] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
580 00:51:58.356641 <6>[ 0.294637] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
581 00:51:58.367262 <6>[ 0.306905] pinctrl core: initialized pinctrl subsystem
582 00:51:58.376614 <6>[ 0.317573] DMI not present or invalid.
583 00:51:58.385015 <6>[ 0.323427] NET: Registered PF_NETLINK/PF_ROUTE protocol family
584 00:51:58.394537 <6>[ 0.332414] DMA: preallocated 256 KiB pool for atomic coherent allocations
585 00:51:58.409639 <6>[ 0.343916] thermal_sys: Registered thermal governor 'step_wise'
586 00:51:58.409913 <6>[ 0.344083] cpuidle: using governor menu
587 00:51:58.437425 <6>[ 0.379969] No ATAGs?
588 00:51:58.443628 <6>[ 0.382610] hw-breakpoint: debug architecture 0x4 unsupported.
589 00:51:58.453848 <6>[ 0.394512] Serial: AMBA PL011 UART driver
590 00:51:58.482984 <6>[ 0.425414] iommu: Default domain type: Translated
591 00:51:58.492162 <6>[ 0.430752] iommu: DMA domain TLB invalidation policy: strict mode
592 00:51:58.519068 <5>[ 0.460844] SCSI subsystem initialized
593 00:51:58.524862 <6>[ 0.465729] usbcore: registered new interface driver usbfs
594 00:51:58.530570 <6>[ 0.471755] usbcore: registered new interface driver hub
595 00:51:58.537489 <6>[ 0.477539] usbcore: registered new device driver usb
596 00:51:58.543193 <6>[ 0.484045] pps_core: LinuxPPS API ver. 1 registered
597 00:51:58.554703 <6>[ 0.489474] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
598 00:51:58.561880 <6>[ 0.499158] PTP clock support registered
599 00:51:58.562155 <6>[ 0.503628] EDAC MC: Ver: 3.0.0
600 00:51:58.613598 <6>[ 0.553470] scmi_core: SCMI protocol bus registered
601 00:51:58.638106 <6>[ 0.579991] vgaarb: loaded
602 00:51:58.644265 <6>[ 0.583766] clocksource: Switched to clocksource dmtimer
603 00:51:58.668844 <6>[ 0.610929] NET: Registered PF_INET protocol family
604 00:51:58.681329 <6>[ 0.616624] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
605 00:51:58.687057 <6>[ 0.625465] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
606 00:51:58.698557 <6>[ 0.634389] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
607 00:51:58.704307 <6>[ 0.642632] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
608 00:51:58.715947 <6>[ 0.650919] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
609 00:51:58.721807 <6>[ 0.658637] TCP: Hash tables configured (established 4096 bind 4096)
610 00:51:58.727560 <6>[ 0.665566] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
611 00:51:58.733452 <6>[ 0.672576] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
612 00:51:58.740988 <6>[ 0.680178] NET: Registered PF_UNIX/PF_LOCAL protocol family
613 00:51:58.826940 <6>[ 0.763874] RPC: Registered named UNIX socket transport module.
614 00:51:58.827277 <6>[ 0.770260] RPC: Registered udp transport module.
615 00:51:58.832831 <6>[ 0.775400] RPC: Registered tcp transport module.
616 00:51:58.838555 <6>[ 0.780506] RPC: Registered tcp-with-tls transport module.
617 00:51:58.851586 <6>[ 0.786428] RPC: Registered tcp NFSv4.1 backchannel transport module.
618 00:51:58.851864 <6>[ 0.793334] PCI: CLS 0 bytes, default 64
619 00:51:58.858603 <5>[ 0.799134] Initialise system trusted keyrings
620 00:51:58.879806 <6>[ 0.819249] Trying to unpack rootfs image as initramfs...
621 00:51:58.958058 <6>[ 0.894351] workingset: timestamp_bits=30 max_order=17 bucket_order=0
622 00:51:58.962846 <6>[ 0.901831] squashfs: version 4.0 (2009/01/31) Phillip Lougher
623 00:51:59.002057 <5>[ 0.944583] NFS: Registering the id_resolver key type
624 00:51:59.007924 <5>[ 0.950183] Key type id_resolver registered
625 00:51:59.013800 <5>[ 0.954882] Key type id_legacy registered
626 00:51:59.019543 <6>[ 0.959322] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
627 00:51:59.029091 <6>[ 0.966527] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
628 00:51:59.112324 <5>[ 1.054844] Key type asymmetric registered
629 00:51:59.118188 <5>[ 1.059368] Asymmetric key parser 'x509' registered
630 00:51:59.129798 <6>[ 1.064862] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
631 00:51:59.130074 <6>[ 1.072751] io scheduler mq-deadline registered
632 00:51:59.135428 <6>[ 1.077709] io scheduler kyber registered
633 00:51:59.140964 <6>[ 1.082161] io scheduler bfq registered
634 00:51:59.280613 <6>[ 1.219412] ledtrig-cpu: registered to indicate activity on CPUs
635 00:51:59.539657 <6>[ 1.478254] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
636 00:51:59.586899 <6>[ 1.529068] msm_serial: driver initialized
637 00:51:59.592890 <6>[ 1.534094] SuperH (H)SCI(F) driver initialized
638 00:51:59.598879 <6>[ 1.539238] STMicroelectronics ASC driver initialized
639 00:51:59.604159 <6>[ 1.544906] STM32 USART driver initialized
640 00:51:59.728726 <6>[ 1.670605] brd: module loaded
641 00:51:59.759570 <6>[ 1.701410] loop: module loaded
642 00:51:59.800088 <6>[ 1.741580] CAN device driver interface
643 00:51:59.806748 <6>[ 1.746890] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
644 00:51:59.812370 <6>[ 1.753953] e1000e: Intel(R) PRO/1000 Network Driver
645 00:51:59.818286 <6>[ 1.759339] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
646 00:51:59.823993 <6>[ 1.765794] igb: Intel(R) Gigabit Ethernet Network Driver
647 00:51:59.832172 <6>[ 1.771615] igb: Copyright (c) 2007-2014 Intel Corporation.
648 00:51:59.844125 <6>[ 1.780903] pegasus: Pegasus/Pegasus II USB Ethernet driver
649 00:51:59.849889 <6>[ 1.787059] usbcore: registered new interface driver pegasus
650 00:51:59.855774 <6>[ 1.793187] usbcore: registered new interface driver asix
651 00:51:59.861402 <6>[ 1.799067] usbcore: registered new interface driver ax88179_178a
652 00:51:59.867135 <6>[ 1.805656] usbcore: registered new interface driver cdc_ether
653 00:51:59.873016 <6>[ 1.811952] usbcore: registered new interface driver smsc75xx
654 00:51:59.878760 <6>[ 1.818191] usbcore: registered new interface driver smsc95xx
655 00:51:59.884514 <6>[ 1.824431] usbcore: registered new interface driver net1080
656 00:51:59.890402 <6>[ 1.830548] usbcore: registered new interface driver cdc_subset
657 00:51:59.896136 <6>[ 1.836972] usbcore: registered new interface driver zaurus
658 00:51:59.903812 <6>[ 1.843015] usbcore: registered new interface driver cdc_ncm
659 00:51:59.913608 <6>[ 1.852555] usbcore: registered new interface driver usb-storage
660 00:51:59.923075 <6>[ 1.863823] i2c_dev: i2c /dev entries driver
661 00:51:59.947688 <5>[ 1.882169] cpuidle: enable-method property 'ti,am3352' found operations
662 00:51:59.953510 <6>[ 1.891726] sdhci: Secure Digital Host Controller Interface driver
663 00:51:59.961051 <6>[ 1.898475] sdhci: Copyright(c) Pierre Ossman
664 00:51:59.968152 <6>[ 1.905024] Synopsys Designware Multimedia Card Interface Driver
665 00:51:59.973564 <6>[ 1.912857] sdhci-pltfm: SDHCI platform and OF driver helper
666 00:51:59.987812 <6>[ 1.922740] usbcore: registered new interface driver usbhid
667 00:51:59.988090 <6>[ 1.928861] usbhid: USB HID core driver
668 00:52:00.000495 <6>[ 1.940464] NET: Registered PF_INET6 protocol family
669 00:52:00.453206 <6>[ 2.395680] Segment Routing with IPv6
670 00:52:00.459098 <6>[ 2.399825] In-situ OAM (IOAM) with IPv6
671 00:52:00.465718 <6>[ 2.404369] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
672 00:52:00.471472 <6>[ 2.411618] NET: Registered PF_PACKET protocol family
673 00:52:00.477347 <6>[ 2.417190] can: controller area network core
674 00:52:00.483094 <6>[ 2.422014] NET: Registered PF_CAN protocol family
675 00:52:00.483375 <6>[ 2.427241] can: raw protocol
676 00:52:00.488842 <6>[ 2.430567] can: broadcast manager protocol
677 00:52:00.495343 <6>[ 2.435161] can: netlink gateway - max_hops=1
678 00:52:00.501468 <5>[ 2.440641] Key type dns_resolver registered
679 00:52:00.507719 <6>[ 2.445716] ThumbEE CPU extension supported.
680 00:52:00.507999 <5>[ 2.450404] Registering SWP/SWPB emulation handler
681 00:52:00.517534 <3>[ 2.456110] omap_voltage_late_init: Voltage driver support not added
682 00:52:00.704194 <5>[ 2.644398] Loading compiled-in X.509 certificates
683 00:52:00.833124 <6>[ 2.762790] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
684 00:52:00.840301 <6>[ 2.779456] pinctrl-single 44e10800.pinmux: 142 pins, size 568
685 00:52:00.866559 <3>[ 2.803094] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
686 00:52:01.089951 <3>[ 3.026503] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
687 00:52:01.284625 <6>[ 3.225563] OMAP GPIO hardware version 0.1
688 00:52:01.305524 <6>[ 3.244338] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
689 00:52:01.397336 <4>[ 3.335933] at24 2-0054: supply vcc not found, using dummy regulator
690 00:52:01.437504 <4>[ 3.376106] at24 2-0055: supply vcc not found, using dummy regulator
691 00:52:01.471246 <4>[ 3.409860] at24 2-0056: supply vcc not found, using dummy regulator
692 00:52:01.512935 <4>[ 3.451660] at24 2-0057: supply vcc not found, using dummy regulator
693 00:52:01.549085 <6>[ 3.488565] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
694 00:52:01.624269 <3>[ 3.559684] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
695 00:52:01.648701 <6>[ 3.580489] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
696 00:52:01.670691 <4>[ 3.606549] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
697 00:52:01.678380 <4>[ 3.615760] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
698 00:52:01.806312 <6>[ 3.745073] omap_rng 48310000.rng: Random Number Generator ver. 20
699 00:52:01.829545 <5>[ 3.771212] random: crng init done
700 00:52:01.896454 <6>[ 3.838934] Freeing initrd memory: 14452K
701 00:52:01.906232 <6>[ 3.843583] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
702 00:52:01.959823 <6>[ 3.896212] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
703 00:52:01.965679 <6>[ 3.906540] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
704 00:52:01.973978 <6>[ 3.913881] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
705 00:52:01.985614 <6>[ 3.921330] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
706 00:52:01.997116 <6>[ 3.929466] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
707 00:52:02.004471 <6>[ 3.941099] cpsw-switch 4a100000.switch: Detected MACID = 64:cf:d9:3f:a0:d5
708 00:52:02.015305 <5>[ 3.950136] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
709 00:52:02.043149 <3>[ 3.979889] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
710 00:52:02.048787 <6>[ 3.988475] edma 49000000.dma: TI EDMA DMA engine driver
711 00:52:02.119626 <3>[ 4.055755] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
712 00:52:02.134258 <6>[ 4.070071] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
713 00:52:02.147195 <3>[ 4.087123] l3-aon-clkctrl:0000:0: failed to disable
714 00:52:02.195379 <6>[ 4.132064] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
715 00:52:02.201010 <6>[ 4.141575] printk: legacy console [ttyS0] enabled
716 00:52:02.206733 <6>[ 4.141575] printk: legacy console [ttyS0] enabled
717 00:52:02.212339 <6>[ 4.151920] printk: legacy bootconsole [omap8250] disabled
718 00:52:02.218173 <6>[ 4.151920] printk: legacy bootconsole [omap8250] disabled
719 00:52:02.258736 <4>[ 4.194517] tps65217-pmic: Failed to locate of_node [id: -1]
720 00:52:02.262274 <4>[ 4.201908] tps65217-bl: Failed to locate of_node [id: -1]
721 00:52:02.278758 <6>[ 4.221579] tps65217 0-0024: TPS65217 ID 0xe version 1.2
722 00:52:02.297213 <6>[ 4.228531] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
723 00:52:02.308884 <6>[ 4.242224] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
724 00:52:02.314531 <6>[ 4.254116] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
725 00:52:02.336585 <6>[ 4.273688] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
726 00:52:02.342477 <6>[ 4.282869] sdhci-omap 48060000.mmc: Got CD GPIO
727 00:52:02.350545 <4>[ 4.288034] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
728 00:52:02.365261 <4>[ 4.301669] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
729 00:52:02.371601 <4>[ 4.310320] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
730 00:52:02.381399 <4>[ 4.318998] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
731 00:52:02.505140 <6>[ 4.443356] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
732 00:52:02.554082 <6>[ 4.490081] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
733 00:52:02.560703 <6>[ 4.499445] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
734 00:52:02.569908 <6>[ 4.508454] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
735 00:52:02.652025 <6>[ 4.591722] mmc1: new high speed MMC card at address 0001
736 00:52:02.660151 <6>[ 4.600826] mmcblk1: mmc1:0001 M62704 3.56 GiB
737 00:52:02.671176 <6>[ 4.611898] mmcblk1: p1
738 00:52:02.676629 <6>[ 4.616824] mmcblk1boot0: mmc1:0001 M62704 2.00 MiB
739 00:52:02.686973 <6>[ 4.627268] mmcblk1boot1: mmc1:0001 M62704 2.00 MiB
740 00:52:02.700813 <6>[ 4.637725] mmcblk1rpmb: mmc1:0001 M62704 512 KiB, chardev (236:0)
741 00:52:02.710025 <6>[ 4.644587] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
742 00:52:05.857793 <6>[ 7.794804] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
743 00:52:05.931019 <5>[ 7.833775] Sending DHCP requests ., OK
744 00:52:05.942471 <6>[ 7.878205] IP-Config: Got DHCP answer from 192.168.11.1, my address is 192.168.11.3
745 00:52:05.942713 <6>[ 7.886454] IP-Config: Complete:
746 00:52:05.953792 <6>[ 7.889995] device=eth0, hwaddr=64:cf:d9:3f:a0:d5, ipaddr=192.168.11.3, mask=255.255.255.0, gw=192.168.11.1
747 00:52:05.959542 <6>[ 7.900590] host=192.168.11.3, domain=usen.ad.jp, nis-domain=(none)
748 00:52:05.971791 <6>[ 7.907672] bootserver=0.0.0.0, rootserver=192.168.11.5, rootpath=
749 00:52:05.972063 <6>[ 7.907706] nameserver0=192.168.11.1
750 00:52:05.977885 <6>[ 7.919995] clk: Disabling unused clocks
751 00:52:05.984592 <6>[ 7.924749] PM: genpd: Disabling unused power domains
752 00:52:06.004049 <6>[ 7.943399] Freeing unused kernel image (initmem) memory: 2048K
753 00:52:06.011434 <6>[ 7.953076] Run /init as init process
754 00:52:06.036339 Loading, please wait...
755 00:52:06.111864 Starting systemd-udevd version 252.22-1~deb12u1
756 00:52:09.160742 <4>[ 11.096380] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
757 00:52:09.359703 <4>[ 11.295387] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
758 00:52:09.511337 <6>[ 11.454438] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
759 00:52:09.521939 <6>[ 11.460110] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
760 00:52:09.755216 <6>[ 11.696972] hub 1-0:1.0: USB hub found
761 00:52:09.781085 <6>[ 11.722656] hub 1-0:1.0: 1 port detected
762 00:52:10.006502 <6>[ 11.947865] tda998x 0-0070: found TDA19988
763 00:52:12.628493 Begin: Loading essential drivers ... done.
764 00:52:12.634058 Begin: Running /scripts/init-premount ... done.
765 00:52:12.639682 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
766 00:52:12.653482 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
767 00:52:12.653753 Device /sys/class/net/eth0 found
768 00:52:12.653971 done.
769 00:52:12.732153 Begin: Waiting up to 180 secs for any network device to become available ... done.
770 00:52:12.826401 IP-Config: eth0 hardware address 64:cf:d9:3f:a0:d5 mtu 1500 DHCP
771 00:52:12.826887 IP-Config: eth0 guessed broadcast address 192.168.11.255
772 00:52:12.831961 IP-Config: eth0 complete (dhcp from 192.168.11.1):
773 00:52:12.843030 address: 192.168.11.3 broadcast: 192.168.11.255 netmask: 255.255.255.0
774 00:52:12.848649 gateway: 192.168.11.1 dns0 : 192.168.11.1 dns1 : 0.0.0.0
775 00:52:12.854333 domain : usen.ad.jp
776 00:52:12.859251 rootserver: 192.168.11.1 rootpath:
777 00:52:12.859530 filename :
778 00:52:12.938614 done.
779 00:52:12.958319 Begin: Running /scripts/nfs-bottom ... done.
780 00:52:13.021163 Begin: Running /scripts/init-bottom ... done.
781 00:52:14.506951 <30>[ 16.445809] systemd[1]: System time before build time, advancing clock.
782 00:52:14.730560 <30>[ 16.643310] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
783 00:52:14.739934 <30>[ 16.680650] systemd[1]: Detected architecture arm.
784 00:52:14.752666
785 00:52:14.752959 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
786 00:52:14.753186
787 00:52:14.783826 <30>[ 16.723381] systemd[1]: Hostname set to <debian-bookworm-armhf>.
788 00:52:16.911212 <30>[ 18.849672] systemd[1]: Queued start job for default target graphical.target.
789 00:52:16.928280 <30>[ 18.864833] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
790 00:52:16.935824 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
791 00:52:16.962326 <30>[ 18.900171] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
792 00:52:16.975322 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
793 00:52:17.000560 <30>[ 18.936159] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
794 00:52:17.007897 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
795 00:52:17.029310 <30>[ 18.965969] systemd[1]: Created slice user.slice - User and Session Slice.
796 00:52:17.035951 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
797 00:52:17.061995 <30>[ 18.996480] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
798 00:52:17.074528 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
799 00:52:17.097945 <30>[ 19.034909] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
800 00:52:17.106991 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
801 00:52:17.138654 <30>[ 19.064645] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
802 00:52:17.144947 <30>[ 19.085095] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
803 00:52:17.153491 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
804 00:52:17.177191 <30>[ 19.114292] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
805 00:52:17.185369 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
806 00:52:17.207814 <30>[ 19.144630] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
807 00:52:17.216409 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
808 00:52:17.237692 <30>[ 19.174733] systemd[1]: Reached target paths.target - Path Units.
809 00:52:17.242736 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
810 00:52:17.267435 <30>[ 19.204498] systemd[1]: Reached target remote-fs.target - Remote File Systems.
811 00:52:17.274737 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
812 00:52:17.297441 <30>[ 19.234499] systemd[1]: Reached target slices.target - Slice Units.
813 00:52:17.302898 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
814 00:52:17.327437 <30>[ 19.264595] systemd[1]: Reached target swap.target - Swaps.
815 00:52:17.331480 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
816 00:52:17.357687 <30>[ 19.294526] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
817 00:52:17.366500 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
818 00:52:17.388560 <30>[ 19.325299] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
819 00:52:17.396790 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
820 00:52:17.476273 <30>[ 19.408206] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
821 00:52:17.488978 <30>[ 19.425888] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
822 00:52:17.497312 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
823 00:52:17.520387 <30>[ 19.456484] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
824 00:52:17.527819 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
825 00:52:17.550133 <30>[ 19.486941] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
826 00:52:17.558227 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
827 00:52:17.583179 <30>[ 19.518818] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
828 00:52:17.588676 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
829 00:52:17.619929 <30>[ 19.555500] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
830 00:52:17.627398 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
831 00:52:17.654599 <30>[ 19.585536] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
832 00:52:17.673349 <30>[ 19.604157] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
833 00:52:17.717598 <30>[ 19.655382] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
834 00:52:17.738641 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
835 00:52:17.761629 <30>[ 19.699290] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
836 00:52:17.792491 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
837 00:52:17.861820 <30>[ 19.798523] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
838 00:52:17.874285 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
839 00:52:17.918050 <30>[ 19.855359] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
840 00:52:17.937078 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
841 00:52:17.988209 <30>[ 19.925736] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
842 00:52:18.008588 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
843 00:52:18.038160 <30>[ 19.975071] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
844 00:52:18.045084 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
845 00:52:18.081083 <30>[ 20.018042] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
846 00:52:18.117583 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
847 00:52:18.166957 <30>[ 20.105035] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
848 00:52:18.185747 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
849 00:52:18.218331 <30>[ 20.156317] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
850 00:52:18.248227 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
851 00:52:18.276523 <28>[ 20.208533] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
852 00:52:18.284944 <28>[ 20.222189] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
853 00:52:18.329828 <30>[ 20.268338] systemd[1]: Starting systemd-journald.service - Journal Service...
854 00:52:18.347326 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
855 00:52:18.429071 <30>[ 20.366793] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
856 00:52:18.445920 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
857 00:52:18.489147 <30>[ 20.427037] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
858 00:52:18.538175 Starting [0;1;39msystemd-network-g… units from Kernel command line...
859 00:52:18.602828 <30>[ 20.539310] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
860 00:52:18.652330 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
861 00:52:18.709854 <30>[ 20.647113] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
862 00:52:18.767131 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
863 00:52:18.830264 <30>[ 20.768380] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
864 00:52:18.887128 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
865 00:52:18.917248 <30>[ 20.855319] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
866 00:52:18.944631 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
867 00:52:18.971886 <30>[ 20.908774] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
868 00:52:19.000907 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
869 00:52:19.169549 <30>[ 21.108290] systemd[1]: modprobe@configfs.service: Deactivated successfully.
870 00:52:19.208134 <30>[ 21.145655] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
871 00:52:19.229323 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
872 00:52:19.235523 <30>[ 21.175524] systemd[1]: Started systemd-journald.service - Journal Service.
873 00:52:19.245092 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
874 00:52:19.287299 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
875 00:52:19.316593 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
876 00:52:19.347194 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
877 00:52:19.372000 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
878 00:52:19.411450 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
879 00:52:19.447306 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
880 00:52:19.469665 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
881 00:52:19.497547 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
882 00:52:19.527094 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
883 00:52:19.590252 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
884 00:52:19.636845 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
885 00:52:19.707394 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
886 00:52:19.779636 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
887 00:52:19.853107 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
888 00:52:20.000582 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
889 00:52:20.042582 <46>[ 21.980619] systemd-journald[162]: Received client request to flush runtime journal.
890 00:52:20.178581 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
891 00:52:20.229785 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
892 00:52:21.018819 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
893 00:52:21.080159 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
894 00:52:21.838260 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
895 00:52:21.982760 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
896 00:52:22.017003 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
897 00:52:22.037000 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
898 00:52:22.107177 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
899 00:52:22.153897 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
900 00:52:23.101335 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
901 00:52:23.168969 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
902 00:52:23.277720 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
903 00:52:23.400659 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
904 00:52:23.473261 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
905 00:52:25.317019 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
906 00:52:25.868126 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
907 00:52:26.202218 <5>[ 28.140676] cfg80211: Loading compiled-in X.509 certificates for regulatory database
908 00:52:26.968692 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
909 00:52:27.665869 <5>[ 29.606375] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
910 00:52:27.757364 <5>[ 29.696439] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
911 00:52:27.785701 <4>[ 29.724133] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
912 00:52:27.791564 <6>[ 29.733116] cfg80211: failed to load regulatory.db
913 00:52:28.069049 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
914 00:52:28.402004 <46>[ 30.330483] systemd-journald[162]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
915 00:52:28.558122 <46>[ 30.489696] systemd-journald[162]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
916 00:52:28.750665 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
917 00:52:37.384562 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
918 00:52:37.407580 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
919 00:52:37.428754 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
920 00:52:37.448882 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
921 00:52:37.507308 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
922 00:52:37.542612 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
923 00:52:37.590541 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
924 00:52:37.652658 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
925 00:52:37.717877 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
926 00:52:37.741749 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
927 00:52:37.771745 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
928 00:52:37.813741 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
929 00:52:37.840387 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
930 00:52:37.895506 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
931 00:52:37.929749 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
932 00:52:37.969234 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
933 00:52:38.019752 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
934 00:52:38.067236 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
935 00:52:38.089501 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
936 00:52:38.117052 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
937 00:52:38.154626 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
938 00:52:38.177247 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
939 00:52:38.199519 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
940 00:52:38.277482 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
941 00:52:38.313423 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
942 00:52:38.424947 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
943 00:52:38.497416 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
944 00:52:38.568553 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
945 00:52:38.626154 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
946 00:52:38.647589 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
947 00:52:38.837040 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
948 00:52:38.886602 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
949 00:52:38.957803 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
950 00:52:38.976043 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
951 00:52:39.039275 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
952 00:52:39.227349 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
953 00:52:39.552493 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
954 00:52:39.609377 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
955 00:52:39.641776 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
956 00:52:39.730852 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
957 00:52:39.902514 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
958 00:52:40.017000
959 00:52:40.017464 Debian GNU/Linux 1worm-armhf login: root (automatic login)
960 00:52:40.020269
961 00:52:40.366481 Linux debian-bookworm-armhf 6.12.0-rc6 #1 SMP Mon Nov 11 00:21:46 UTC 2024 armv7l
962 00:52:40.366785
963 00:52:40.372016 The programs included with the Debian GNU/Linux system are free software;
964 00:52:40.377680 the exact distribution terms for each program are described in the
965 00:52:40.383244 individual files in /usr/share/doc/*/copyright.
966 00:52:40.383485
967 00:52:40.391219 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
968 00:52:40.391497 permitted by applicable law.
969 00:52:45.013951 Unable to match end of the kernel message
971 00:52:45.014767 Setting prompt string to ['/ #']
972 00:52:45.015067 end: 2.4.4.1 login-action (duration 00:00:47) [common]
974 00:52:45.015750 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
975 00:52:45.016037 start: 2.4.5 expect-shell-connection (timeout 00:03:24) [common]
976 00:52:45.016283 Setting prompt string to ['/ #']
977 00:52:45.016492 Forcing a shell prompt, looking for ['/ #']
979 00:52:45.067041 / #
980 00:52:45.067417 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
981 00:52:45.067674 Waiting using forced prompt support (timeout 00:02:30)
982 00:52:45.071919
983 00:52:45.079944 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
984 00:52:45.080273 start: 2.4.6 export-device-env (timeout 00:03:24) [common]
985 00:52:45.080532 Sending with 10 millisecond of delay
987 00:52:50.129332 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1221114/extract-nfsrootfs-fi8dgaby'
988 00:52:50.139923 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/1221114/extract-nfsrootfs-fi8dgaby'
989 00:52:50.141040 Sending with 10 millisecond of delay
991 00:52:52.299316 / # export NFS_SERVER_IP='192.168.11.5'
992 00:52:52.309884 export NFS_SERVER_IP='192.168.11.5'
993 00:52:52.310923 end: 2.4.6 export-device-env (duration 00:00:07) [common]
994 00:52:52.311268 end: 2.4 uboot-commands (duration 00:01:43) [common]
995 00:52:52.311580 end: 2 uboot-action (duration 00:01:43) [common]
996 00:52:52.311892 start: 3 lava-test-retry (timeout 00:07:23) [common]
997 00:52:52.312197 start: 3.1 lava-test-shell (timeout 00:07:23) [common]
998 00:52:52.312459 Using namespace: common
1000 00:52:52.413162 / # #
1001 00:52:52.413686 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1002 00:52:52.417919 #
1003 00:52:52.423889 Using /lava-1221114
1005 00:52:52.524616 / # export SHELL=/bin/bash
1006 00:52:52.529439 export SHELL=/bin/bash
1008 00:52:52.636050 / # . /lava-1221114/environment
1009 00:52:52.640925 . /lava-1221114/environment
1011 00:52:52.753913 / # /lava-1221114/bin/lava-test-runner /lava-1221114/0
1012 00:52:52.754292 Test shell timeout: 10s (minimum of the action and connection timeout)
1013 00:52:52.758644 /lava-1221114/bin/lava-test-runner /lava-1221114/0
1014 00:52:53.176043 + export TESTRUN_ID=0_timesync-off
1015 00:52:53.184013 + TESTRUN_ID=0_timesync-off
1016 00:52:53.184271 + cd /lava-1221114/0/tests/0_timesync-off
1017 00:52:53.184503 ++ cat uuid
1018 00:52:53.200458 + UUID=1221114_1.6.2.4.1
1019 00:52:53.200728 + set +x
1020 00:52:53.206082 <LAVA_SIGNAL_STARTRUN 0_timesync-off 1221114_1.6.2.4.1>
1021 00:52:53.206570 Received signal: <STARTRUN> 0_timesync-off 1221114_1.6.2.4.1
1022 00:52:53.206825 Starting test lava.0_timesync-off (1221114_1.6.2.4.1)
1023 00:52:53.207134 Skipping test definition patterns.
1024 00:52:53.209291 + systemctl stop systemd-timesyncd
1025 00:52:53.482842 + set +x
1026 00:52:53.483328 Received signal: <ENDRUN> 0_timesync-off 1221114_1.6.2.4.1
1027 00:52:53.483614 Ending use of test pattern.
1028 00:52:53.483840 Ending test lava.0_timesync-off (1221114_1.6.2.4.1), duration 0.28
1030 00:52:53.485974 <LAVA_SIGNAL_ENDRUN 0_timesync-off 1221114_1.6.2.4.1>
1031 00:52:53.714866 + export TESTRUN_ID=1_kselftest-dt
1032 00:52:53.722868 + TESTRUN_ID=1_kselftest-dt
1033 00:52:53.723122 + cd /lava-1221114/0/tests/1_kselftest-dt
1034 00:52:53.723354 ++ cat uuid
1035 00:52:53.739197 + UUID=1221114_1.6.2.4.5
1036 00:52:53.739472 + set +x
1037 00:52:53.744800 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 1221114_1.6.2.4.5>
1038 00:52:53.745103 + cd ./automated/linux/kselftest/
1039 00:52:53.745574 Received signal: <STARTRUN> 1_kselftest-dt 1221114_1.6.2.4.5
1040 00:52:53.745842 Starting test lava.1_kselftest-dt (1221114_1.6.2.4.5)
1041 00:52:53.746146 Skipping test definition patterns.
1042 00:52:53.772981 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-415-g0e90fad093db9/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1043 00:52:53.891151 INFO: install_deps skipped
1044 00:52:54.475842 --2024-11-11 00:52:54-- http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-415-g0e90fad093db9/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1045 00:52:54.493360 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1046 00:52:54.608094 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1047 00:52:54.719838 HTTP request sent, awaiting response... 200 OK
1048 00:52:54.720121 Length: 4106648 (3.9M) [application/octet-stream]
1049 00:52:54.725344 Saving to: 'kselftest_armhf.tar.gz'
1050 00:52:54.725626
1051 00:52:56.626807 kselftest_armhf.tar 0%[ ] 0 --.-KB/s kselftest_armhf.tar 1%[ ] 49.92K 223KB/s kselftest_armhf.tar 4%[ ] 192.39K 431KB/s kselftest_armhf.tar 18%[==> ] 722.54K 1.05MB/s kselftest_armhf.tar 35%[======> ] 1.39M 1.60MB/s kselftest_armhf.tar 48%[========> ] 1.89M 1.77MB/s kselftest_armhf.tar 60%[===========> ] 2.38M 1.88MB/s kselftest_armhf.tar 73%[=============> ] 2.89M 1.95MB/s kselftest_armhf.tar 85%[================> ] 3.34M 1.98MB/s kselftest_armhf.tar 98%[==================> ] 3.84M 2.03MB/s kselftest_armhf.tar 100%[===================>] 3.92M 2.06MB/s in 1.9s
1052 00:52:56.627208
1053 00:52:57.147652 2024-11-11 00:52:56 (2.06 MB/s) - 'kselftest_armhf.tar.gz' saved [4106648/4106648]
1054 00:52:57.148007
1055 00:53:19.320569 skiplist:
1056 00:53:19.320978 ========================================
1057 00:53:19.326157 ========================================
1058 00:53:19.433453 dt:test_unprobed_devices.sh
1059 00:53:19.465583 ============== Tests to run ===============
1060 00:53:19.473884 dt:test_unprobed_devices.sh
1061 00:53:19.477809 ===========End Tests to run ===============
1062 00:53:19.490143 shardfile-dt pass
1063 00:53:19.732481 <12>[ 81.676718] kselftest: Running tests in dt
1064 00:53:19.760462 TAP version 13
1065 00:53:19.783758 1..1
1066 00:53:19.837527 # timeout set to 45
1067 00:53:19.837798 # selftests: dt: test_unprobed_devices.sh
1068 00:53:20.664687 # TAP version 13
1069 00:53:45.826459 # 1..257
1070 00:53:46.003398 # ok 1 / # SKIP
1071 00:53:46.020211 # ok 2 /clk_mcasp0
1072 00:53:46.092057 # ok 3 /clk_mcasp0_fixed # SKIP
1073 00:53:46.166117 # ok 4 /cpus/cpu@0 # SKIP
1074 00:53:46.232647 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1075 00:53:46.253620 # ok 6 /fixedregulator0
1076 00:53:46.275479 # ok 7 /leds
1077 00:53:46.295128 # ok 8 /ocp
1078 00:53:46.320168 # ok 9 /ocp/interconnect@44c00000
1079 00:53:46.347159 # ok 10 /ocp/interconnect@44c00000/segment@0
1080 00:53:46.365721 # ok 11 /ocp/interconnect@44c00000/segment@100000
1081 00:53:46.394057 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1082 00:53:46.459782 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1083 00:53:46.480994 # ok 14 /ocp/interconnect@44c00000/segment@200000
1084 00:53:46.504768 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1085 00:53:46.610003 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1086 00:53:46.682746 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1087 00:53:46.755194 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1088 00:53:46.826621 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1089 00:53:46.898878 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1090 00:53:46.970754 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1091 00:53:47.047865 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1092 00:53:47.120899 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1093 00:53:47.192938 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1094 00:53:47.270354 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1095 00:53:47.335483 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1096 00:53:47.408744 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1097 00:53:47.481352 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1098 00:53:47.554099 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1099 00:53:47.626624 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1100 00:53:47.699467 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1101 00:53:47.771272 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1102 00:53:47.844944 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1103 00:53:47.916436 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1104 00:53:47.989880 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1105 00:53:48.061935 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1106 00:53:48.134878 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1107 00:53:48.212045 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1108 00:53:48.283327 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1109 00:53:48.356833 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1110 00:53:48.426417 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1111 00:53:48.499947 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1112 00:53:48.572496 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1113 00:53:48.650104 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1114 00:53:48.722532 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1115 00:53:48.794000 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1116 00:53:48.868152 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1117 00:53:48.941050 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1118 00:53:49.013593 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1119 00:53:49.082857 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1120 00:53:49.160092 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1121 00:53:49.233609 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1122 00:53:49.302208 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1123 00:53:49.376221 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1124 00:53:49.449184 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1125 00:53:49.521570 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1126 00:53:49.599132 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1127 00:53:49.666592 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1128 00:53:49.739481 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1129 00:53:49.813473 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1130 00:53:49.884875 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1131 00:53:49.958486 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1132 00:53:50.031109 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1133 00:53:50.107003 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1134 00:53:50.179106 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1135 00:53:50.248982 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1136 00:53:50.322102 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1137 00:53:50.396404 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1138 00:53:50.468778 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1139 00:53:50.541997 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1140 00:53:50.614763 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1141 00:53:50.687650 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1142 00:53:50.760153 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1143 00:53:50.832925 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1144 00:53:50.911845 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1145 00:53:50.983335 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1146 00:53:51.053585 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1147 00:53:51.125615 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1148 00:53:51.199580 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1149 00:53:51.272696 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1150 00:53:51.349793 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1151 00:53:51.418986 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1152 00:53:51.491000 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1153 00:53:51.563874 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1154 00:53:51.637100 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1155 00:53:51.710226 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1156 00:53:51.787660 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1157 00:53:51.855945 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1158 00:53:51.930798 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1159 00:53:52.004522 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1160 00:53:52.074155 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1161 00:53:52.149269 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1162 00:53:52.221746 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1163 00:53:52.299903 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1164 00:53:52.316848 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1165 00:53:52.341813 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1166 00:53:52.364650 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1167 00:53:52.389022 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1168 00:53:52.413424 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1169 00:53:52.437026 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1170 00:53:52.464222 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1171 00:53:52.483205 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1172 00:53:52.592761 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1173 00:53:52.615386 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1174 00:53:52.640376 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1175 00:53:52.664240 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1176 00:53:52.771438 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1177 00:53:52.846286 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1178 00:53:52.918935 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1179 00:53:52.991186 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1180 00:53:53.064055 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1181 00:53:53.136201 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1182 00:53:53.212937 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1183 00:53:53.284059 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1184 00:53:53.358550 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1185 00:53:53.428653 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1186 00:53:53.501422 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1187 00:53:53.574034 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1188 00:53:53.645151 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1189 00:53:53.720788 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1190 00:53:53.794446 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1191 00:53:53.872429 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1192 00:53:53.890398 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1193 00:53:53.962021 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1194 00:53:54.036792 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1195 00:53:54.110358 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1196 00:53:54.130136 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1197 00:53:54.201885 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1198 00:53:54.224541 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1199 00:53:54.301005 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1200 00:53:54.326398 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1201 00:53:54.345878 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1202 00:53:54.370076 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1203 00:53:54.393626 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1204 00:53:54.416031 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1205 00:53:54.441872 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1206 00:53:54.471219 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1207 00:53:54.544127 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1208 00:53:54.564033 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1209 00:53:54.587324 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1210 00:53:54.660953 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1211 00:53:54.732878 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1212 00:53:54.754136 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1213 00:53:54.856401 # not ok 144 /ocp/interconnect@47c00000
1214 00:53:54.928766 # not ok 145 /ocp/interconnect@47c00000/segment@0
1215 00:53:54.954780 # ok 146 /ocp/interconnect@48000000
1216 00:53:54.978462 # ok 147 /ocp/interconnect@48000000/segment@0
1217 00:53:54.999159 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1218 00:53:55.026839 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1219 00:53:55.049676 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1220 00:53:55.077242 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1221 00:53:55.098117 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1222 00:53:55.121352 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1223 00:53:55.140638 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1224 00:53:55.213942 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1225 00:53:55.290800 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1226 00:53:55.308370 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1227 00:53:55.333064 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1228 00:53:55.355435 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1229 00:53:55.379775 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1230 00:53:55.402691 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1231 00:53:55.430201 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1232 00:53:55.449536 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1233 00:53:55.478004 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1234 00:53:55.499749 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1235 00:53:55.527689 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1236 00:53:55.548838 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1237 00:53:55.570223 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1238 00:53:55.596592 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1239 00:53:55.620098 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1240 00:53:55.639129 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1241 00:53:55.663678 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1242 00:53:55.685904 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1243 00:53:55.715189 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1244 00:53:55.731768 # ok 175 /ocp/interconnect@48000000/segment@100000
1245 00:53:55.756769 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1246 00:53:55.781361 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1247 00:53:55.855335 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1248 00:53:55.928911 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1249 00:53:55.999081 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1250 00:53:56.073330 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1251 00:53:56.144121 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1252 00:53:56.218083 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1253 00:53:56.292222 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1254 00:53:56.362810 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1255 00:53:56.382666 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1256 00:53:56.405873 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1257 00:53:56.429748 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1258 00:53:56.457545 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1259 00:53:56.479947 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1260 00:53:56.508205 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1261 00:53:56.523947 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1262 00:53:56.549166 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1263 00:53:56.572470 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1264 00:53:56.595647 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1265 00:53:56.620023 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1266 00:53:56.643611 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1267 00:53:56.663774 # ok 198 /ocp/interconnect@48000000/segment@200000
1268 00:53:56.689657 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1269 00:53:56.761713 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1270 00:53:56.782188 # ok 201 /ocp/interconnect@48000000/segment@300000
1271 00:53:56.809641 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1272 00:53:56.834952 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1273 00:53:56.858890 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1274 00:53:56.880040 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1275 00:53:56.900877 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1276 00:53:56.924874 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1277 00:53:57.000836 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1278 00:53:57.016796 # ok 209 /ocp/interconnect@4a000000
1279 00:53:57.044384 # ok 210 /ocp/interconnect@4a000000/segment@0
1280 00:53:57.069268 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1281 00:53:57.090220 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1282 00:53:57.118649 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1283 00:53:57.139736 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1284 00:53:57.207863 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1285 00:53:57.315023 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1286 00:53:57.388134 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1287 00:53:57.493243 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1288 00:53:57.564840 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1289 00:53:57.636378 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1290 00:53:57.736146 # not ok 221 /ocp/interconnect@4b140000
1291 00:53:57.814023 # not ok 222 /ocp/interconnect@4b140000/segment@0
1292 00:53:57.886816 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1293 00:53:57.903809 # ok 224 /ocp/target-module@40300000
1294 00:53:57.927682 # ok 225 /ocp/target-module@40300000/sram@0
1295 00:53:58.001823 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1296 00:53:58.078757 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1297 00:53:58.097063 # ok 228 /ocp/target-module@47400000
1298 00:53:58.126834 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1299 00:53:58.141674 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1300 00:53:58.165170 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1301 00:53:58.193739 # ok 232 /ocp/target-module@47400000/usb@1400
1302 00:53:58.215173 # ok 233 /ocp/target-module@47400000/usb@1800
1303 00:53:58.237099 # ok 234 /ocp/target-module@47810000
1304 00:53:58.257093 # ok 235 /ocp/target-module@49000000
1305 00:53:58.282744 # ok 236 /ocp/target-module@49000000/dma@0
1306 00:53:58.301250 # ok 237 /ocp/target-module@49800000
1307 00:53:58.327633 # ok 238 /ocp/target-module@49800000/dma@0
1308 00:53:58.350360 # ok 239 /ocp/target-module@49900000
1309 00:53:58.374380 # ok 240 /ocp/target-module@49900000/dma@0
1310 00:53:58.396008 # ok 241 /ocp/target-module@49a00000
1311 00:53:58.414667 # ok 242 /ocp/target-module@49a00000/dma@0
1312 00:53:58.436966 # ok 243 /ocp/target-module@4c000000
1313 00:53:58.513987 # not ok 244 /ocp/target-module@4c000000/emif@0
1314 00:53:58.535110 # ok 245 /ocp/target-module@50000000
1315 00:53:58.552212 # ok 246 /ocp/target-module@53100000
1316 00:53:58.625695 # not ok 247 /ocp/target-module@53100000/sham@0
1317 00:53:58.647459 # ok 248 /ocp/target-module@53500000
1318 00:53:58.724495 # not ok 249 /ocp/target-module@53500000/aes@0
1319 00:53:58.745613 # ok 250 /ocp/target-module@56000000
1320 00:53:58.846985 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1321 00:53:58.917576 # ok 252 /opp-table # SKIP
1322 00:53:58.992749 # ok 253 /soc # SKIP
1323 00:53:59.009130 # ok 254 /sound
1324 00:53:59.033693 # ok 255 /target-module@4b000000
1325 00:53:59.062947 # ok 256 /target-module@4b000000/target-module@140000
1326 00:53:59.079688 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1327 00:53:59.088193 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1328 00:53:59.096049 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1329 00:54:01.218419 dt_test_unprobed_devices_sh_ skip
1330 00:54:01.223916 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1331 00:54:01.229542 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1332 00:54:01.229809 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1333 00:54:01.235034 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1334 00:54:01.240656 dt_test_unprobed_devices_sh_fixedregulator0 pass
1335 00:54:01.246286 dt_test_unprobed_devices_sh_leds pass
1336 00:54:01.246553 dt_test_unprobed_devices_sh_ocp pass
1337 00:54:01.251905 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1338 00:54:01.257535 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1339 00:54:01.263163 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1340 00:54:01.274433 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1341 00:54:01.279908 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1342 00:54:01.285529 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1343 00:54:01.296782 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1344 00:54:01.302407 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1345 00:54:01.313557 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1346 00:54:01.324813 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1347 00:54:01.336046 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1348 00:54:01.341670 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1349 00:54:01.352818 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1350 00:54:01.364042 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1351 00:54:01.375296 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1352 00:54:01.386421 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1353 00:54:01.392062 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1354 00:54:01.403290 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1355 00:54:01.414420 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1356 00:54:01.425668 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1357 00:54:01.436805 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1358 00:54:01.442475 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1359 00:54:01.453686 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1360 00:54:01.464843 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1361 00:54:01.476054 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1362 00:54:01.481538 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1363 00:54:01.492817 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1364 00:54:01.503922 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1365 00:54:01.515168 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1366 00:54:01.526455 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1367 00:54:01.531958 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1368 00:54:01.543203 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1369 00:54:01.554456 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1370 00:54:01.565568 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1371 00:54:01.576722 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1372 00:54:01.587933 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1373 00:54:01.599157 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1374 00:54:01.610414 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1375 00:54:01.621543 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1376 00:54:01.632668 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1377 00:54:01.643916 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1378 00:54:01.655039 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1379 00:54:01.666322 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1380 00:54:01.677478 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1381 00:54:01.688647 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1382 00:54:01.699769 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1383 00:54:01.711017 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1384 00:54:01.722143 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1385 00:54:01.733393 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1386 00:54:01.744516 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1387 00:54:01.755743 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1388 00:54:01.767014 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1389 00:54:01.778140 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1390 00:54:01.789391 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1391 00:54:01.800497 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1392 00:54:01.811763 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1393 00:54:01.817388 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1394 00:54:01.828516 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1395 00:54:01.839704 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1396 00:54:01.850864 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1397 00:54:01.862100 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1398 00:54:01.873404 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1399 00:54:01.884449 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1400 00:54:01.895760 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1401 00:54:01.906885 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1402 00:54:01.918133 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1403 00:54:01.929359 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1404 00:54:01.940507 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1405 00:54:01.951762 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1406 00:54:01.962882 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1407 00:54:01.974135 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1408 00:54:01.985432 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1409 00:54:01.996509 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1410 00:54:02.007633 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1411 00:54:02.013286 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1412 00:54:02.024511 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1413 00:54:02.035626 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1414 00:54:02.046884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1415 00:54:02.058003 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1416 00:54:02.063629 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1417 00:54:02.080379 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1418 00:54:02.091625 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1419 00:54:02.097145 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1420 00:54:02.114001 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1421 00:54:02.125165 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1422 00:54:02.136382 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1423 00:54:02.142002 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1424 00:54:02.153134 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1425 00:54:02.164372 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1426 00:54:02.170003 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1427 00:54:02.181156 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1428 00:54:02.192375 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1429 00:54:02.197874 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1430 00:54:02.209154 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1431 00:54:02.214750 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1432 00:54:02.225873 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1433 00:54:02.237131 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1434 00:54:02.248375 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1435 00:54:02.259496 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1436 00:54:02.270623 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1437 00:54:02.281872 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1438 00:54:02.293017 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1439 00:54:02.304243 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1440 00:54:02.315497 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1441 00:54:02.326617 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1442 00:54:02.337748 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1443 00:54:02.348996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1444 00:54:02.365743 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1445 00:54:02.377041 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1446 00:54:02.388117 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1447 00:54:02.399367 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1448 00:54:02.410492 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1449 00:54:02.427367 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1450 00:54:02.438492 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1451 00:54:02.449739 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1452 00:54:02.460872 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1453 00:54:02.466494 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1454 00:54:02.477744 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1455 00:54:02.488922 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1456 00:54:02.494486 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1457 00:54:02.505616 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1458 00:54:02.511366 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1459 00:54:02.522490 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1460 00:54:02.527987 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1461 00:54:02.539364 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1462 00:54:02.544930 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1463 00:54:02.555994 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1464 00:54:02.561612 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1465 00:54:02.572924 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1466 00:54:02.583986 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1467 00:54:02.595233 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1468 00:54:02.606423 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1469 00:54:02.617624 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1470 00:54:02.623123 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1471 00:54:02.634377 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1472 00:54:02.639999 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1473 00:54:02.645621 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1474 00:54:02.651121 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1475 00:54:02.656769 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1476 00:54:02.662373 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1477 00:54:02.673498 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1478 00:54:02.679121 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1479 00:54:02.684760 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1480 00:54:02.695871 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1481 00:54:02.701498 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1482 00:54:02.712771 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1483 00:54:02.718368 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1484 00:54:02.729493 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1485 00:54:02.735118 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1486 00:54:02.746366 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1487 00:54:02.751870 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1488 00:54:02.763117 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1489 00:54:02.768618 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1490 00:54:02.779870 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1491 00:54:02.785494 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1492 00:54:02.796706 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1493 00:54:02.802356 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1494 00:54:02.807852 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1495 00:54:02.818978 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1496 00:54:02.824651 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1497 00:54:02.835847 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1498 00:54:02.841508 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1499 00:54:02.852616 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1500 00:54:02.858222 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1501 00:54:02.869382 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1502 00:54:02.874972 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1503 00:54:02.880597 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1504 00:54:02.891720 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1505 00:54:02.897401 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1506 00:54:02.908593 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1507 00:54:02.919721 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1508 00:54:02.930967 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1509 00:54:02.942109 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1510 00:54:02.953397 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1511 00:54:02.964466 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1512 00:54:02.975715 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1513 00:54:02.986849 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1514 00:54:02.992466 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1515 00:54:03.003716 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1516 00:54:03.009400 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1517 00:54:03.020464 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1518 00:54:03.026160 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1519 00:54:03.037406 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1520 00:54:03.042884 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1521 00:54:03.053985 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1522 00:54:03.059612 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1523 00:54:03.070867 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1524 00:54:03.076507 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1525 00:54:03.087622 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1526 00:54:03.093247 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1527 00:54:03.104366 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1528 00:54:03.109986 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1529 00:54:03.115620 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1530 00:54:03.126714 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1531 00:54:03.132359 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1532 00:54:03.143586 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1533 00:54:03.149325 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1534 00:54:03.160303 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1535 00:54:03.165932 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1536 00:54:03.177162 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1537 00:54:03.182723 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1538 00:54:03.188363 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1539 00:54:03.193954 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1540 00:54:03.205131 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1541 00:54:03.216343 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1542 00:54:03.221828 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1543 00:54:03.227452 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1544 00:54:03.238719 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1545 00:54:03.249845 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1546 00:54:03.261128 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1547 00:54:03.272306 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1548 00:54:03.277826 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1549 00:54:03.283450 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1550 00:54:03.289151 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1551 00:54:03.294710 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1552 00:54:03.300328 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1553 00:54:03.305973 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1554 00:54:03.317130 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1555 00:54:03.322739 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1556 00:54:03.328325 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1557 00:54:03.333988 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1558 00:54:03.339652 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1559 00:54:03.350754 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1560 00:54:03.356385 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1561 00:54:03.361969 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1562 00:54:03.367608 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1563 00:54:03.373096 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1564 00:54:03.378718 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1565 00:54:03.384343 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1566 00:54:03.389958 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1567 00:54:03.395577 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1568 00:54:03.401126 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1569 00:54:03.406703 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1570 00:54:03.412340 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1571 00:54:03.417970 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1572 00:54:03.423451 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1573 00:54:03.429222 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1574 00:54:03.434732 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1575 00:54:03.440340 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1576 00:54:03.445948 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1577 00:54:03.451589 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1578 00:54:03.457235 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1579 00:54:03.462699 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1580 00:54:03.462978 dt_test_unprobed_devices_sh_opp-table skip
1581 00:54:03.468343 dt_test_unprobed_devices_sh_soc skip
1582 00:54:03.473967 dt_test_unprobed_devices_sh_sound pass
1583 00:54:03.479583 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1584 00:54:03.485110 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1585 00:54:03.490702 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1586 00:54:03.496341 dt_test_unprobed_devices_sh fail
1587 00:54:03.496618 + ../../utils/send-to-lava.sh ./output/result.txt
1588 00:54:03.501952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1589 00:54:03.502543 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1591 00:54:03.511019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1592 00:54:03.511509 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1594 00:54:03.608738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1595 00:54:03.609219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1597 00:54:03.705880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1598 00:54:03.706356 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1600 00:54:03.799484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1601 00:54:03.800059 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1603 00:54:03.897415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1604 00:54:03.897900 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1606 00:54:03.994525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1607 00:54:03.995002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1609 00:54:04.092636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1610 00:54:04.093195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1612 00:54:04.191762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1613 00:54:04.192283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1615 00:54:04.290880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1616 00:54:04.291320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1618 00:54:04.394144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1619 00:54:04.394622 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1621 00:54:04.494757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1622 00:54:04.495253 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1624 00:54:04.594511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1625 00:54:04.594995 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1627 00:54:04.693601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1628 00:54:04.694090 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1630 00:54:04.791015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1631 00:54:04.791504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1633 00:54:04.891528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1634 00:54:04.892088 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1636 00:54:04.988136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1637 00:54:04.988626 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1639 00:54:05.089374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1640 00:54:05.089876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1642 00:54:05.189130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1643 00:54:05.189723 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1645 00:54:05.288377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1646 00:54:05.288878 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1648 00:54:05.388213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1649 00:54:05.388750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1651 00:54:05.486621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1652 00:54:05.487136 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1654 00:54:05.586749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1655 00:54:05.587263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1657 00:54:05.689489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1658 00:54:05.690003 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1660 00:54:05.789359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1661 00:54:05.789859 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1663 00:54:05.888410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1664 00:54:05.888987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1666 00:54:05.985329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1667 00:54:05.985817 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1669 00:54:06.086043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1670 00:54:06.086536 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1672 00:54:06.186293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1673 00:54:06.186892 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1675 00:54:06.284673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1676 00:54:06.285217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1678 00:54:06.379657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1679 00:54:06.380169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1681 00:54:06.477761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1682 00:54:06.478247 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1684 00:54:06.574270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1685 00:54:06.574733 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1687 00:54:06.672308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1688 00:54:06.672793 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1690 00:54:06.769427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1691 00:54:06.769913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1693 00:54:06.868902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1694 00:54:06.869484 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1696 00:54:06.967646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1697 00:54:06.968136 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1699 00:54:07.065880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1700 00:54:07.066371 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1702 00:54:07.164460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1703 00:54:07.165128 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1705 00:54:07.264154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1706 00:54:07.264647 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1708 00:54:07.363462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1709 00:54:07.363951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1711 00:54:07.457946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1712 00:54:07.458424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1714 00:54:07.553560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1715 00:54:07.554039 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1717 00:54:07.649679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1718 00:54:07.650176 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1720 00:54:07.750797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1721 00:54:07.751281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1723 00:54:07.849805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1724 00:54:07.850355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1726 00:54:07.949451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1727 00:54:07.949940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1729 00:54:08.047517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1730 00:54:08.048035 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1732 00:54:08.146971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1733 00:54:08.147496 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1735 00:54:08.262592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1736 00:54:08.263156 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1738 00:54:08.365277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1739 00:54:08.365769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1741 00:54:08.460952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1742 00:54:08.461446 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1744 00:54:08.559334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1745 00:54:08.559824 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1747 00:54:08.656620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1748 00:54:08.657141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1750 00:54:08.753856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1751 00:54:08.754348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1753 00:54:08.850955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1754 00:54:08.851518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1756 00:54:08.951208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1757 00:54:08.951699 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1759 00:54:09.049957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1760 00:54:09.050449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1762 00:54:09.146711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1763 00:54:09.147193 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1765 00:54:09.242494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1766 00:54:09.243048 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1768 00:54:09.341157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1769 00:54:09.341641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1771 00:54:09.439752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1772 00:54:09.440240 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1774 00:54:09.538480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1775 00:54:09.538961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1777 00:54:09.638625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1778 00:54:09.639109 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1780 00:54:09.738848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1781 00:54:09.739331 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1783 00:54:09.835111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1784 00:54:09.835661 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1786 00:54:09.932462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1787 00:54:09.932959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1789 00:54:10.029598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1790 00:54:10.030078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1792 00:54:10.124015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1793 00:54:10.124493 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1795 00:54:10.220619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1796 00:54:10.221192 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1798 00:54:10.319918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1799 00:54:10.320440 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1801 00:54:10.418629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1802 00:54:10.419239 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1804 00:54:10.519749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1805 00:54:10.520247 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1807 00:54:10.620576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1808 00:54:10.621140 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1810 00:54:10.719592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1811 00:54:10.720131 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1813 00:54:10.819564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1814 00:54:10.820146 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1816 00:54:10.920285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1817 00:54:10.920778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1819 00:54:11.018706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1820 00:54:11.019219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1822 00:54:11.118945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1823 00:54:11.119444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1825 00:54:11.215529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1826 00:54:11.216078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1828 00:54:11.311086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1829 00:54:11.311564 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1831 00:54:11.409134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1832 00:54:11.409632 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1834 00:54:11.509355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1835 00:54:11.509831 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1837 00:54:11.603350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1838 00:54:11.603840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1840 00:54:11.699390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1841 00:54:11.699875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1843 00:54:11.795325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1844 00:54:11.795807 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1846 00:54:11.890346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1847 00:54:11.890899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1849 00:54:11.984223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1850 00:54:11.984738 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1852 00:54:12.077698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1853 00:54:12.078173 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1855 00:54:12.175578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1856 00:54:12.176146 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1858 00:54:12.270755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1859 00:54:12.271237 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1861 00:54:12.364221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1862 00:54:12.364730 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1864 00:54:12.461061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1865 00:54:12.461542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1867 00:54:12.557049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1868 00:54:12.557541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1870 00:54:12.653392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1871 00:54:12.653876 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1873 00:54:12.745862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1874 00:54:12.746340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1876 00:54:12.845011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1877 00:54:12.845554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1879 00:54:12.941007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1880 00:54:12.941486 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1882 00:54:13.038757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1883 00:54:13.039236 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1885 00:54:13.133153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1886 00:54:13.133634 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1888 00:54:13.229519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1889 00:54:13.230069 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1891 00:54:13.323397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1892 00:54:13.323875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1894 00:54:13.422328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1895 00:54:13.422815 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1897 00:54:13.517749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1898 00:54:13.518238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1900 00:54:13.614074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1901 00:54:13.614562 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1903 00:54:13.710198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1904 00:54:13.710715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1906 00:54:13.806123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1907 00:54:13.806624 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1909 00:54:13.905814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1910 00:54:13.906372 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1912 00:54:14.004014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1913 00:54:14.004494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1915 00:54:14.099247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1916 00:54:14.099732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1918 00:54:14.198998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1919 00:54:14.199577 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1921 00:54:14.297648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1922 00:54:14.298132 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1924 00:54:14.397409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1925 00:54:14.397915 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1927 00:54:14.493665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1928 00:54:14.494167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1930 00:54:14.591550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1931 00:54:14.592040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1933 00:54:14.689661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1934 00:54:14.690156 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1936 00:54:14.787533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1937 00:54:14.788024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1939 00:54:14.885309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1940 00:54:14.885872 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1942 00:54:14.984546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1943 00:54:14.985060 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1945 00:54:15.080963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1946 00:54:15.081442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1948 00:54:15.178471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1950 00:54:15.181772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1951 00:54:15.274596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1953 00:54:15.277739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1954 00:54:15.372137 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1956 00:54:15.375109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1957 00:54:15.472953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1958 00:54:15.473460 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1960 00:54:15.571111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1961 00:54:15.571606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1963 00:54:15.667755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1964 00:54:15.668281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1966 00:54:15.765473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1967 00:54:15.765962 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1969 00:54:15.864088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1970 00:54:15.864637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1972 00:54:15.961681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1973 00:54:15.962164 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1975 00:54:16.056446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1976 00:54:16.056947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1978 00:54:16.156239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1979 00:54:16.156753 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1981 00:54:16.256123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1982 00:54:16.256683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1984 00:54:16.354916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1985 00:54:16.355392 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1987 00:54:16.450995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1988 00:54:16.451483 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1990 00:54:16.548744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1991 00:54:16.549229 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1993 00:54:16.646777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1994 00:54:16.647257 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1996 00:54:16.744882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1997 00:54:16.745356 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1999 00:54:16.845050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2000 00:54:16.845572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2002 00:54:16.945020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2003 00:54:16.945506 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2005 00:54:17.039646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2006 00:54:17.040126 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2008 00:54:17.133263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2009 00:54:17.133747 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2011 00:54:17.234023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2012 00:54:17.234572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2014 00:54:17.330757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2015 00:54:17.331235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2017 00:54:17.422880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2018 00:54:17.423358 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2020 00:54:17.516808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2021 00:54:17.517297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2023 00:54:17.611405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2024 00:54:17.611896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2026 00:54:17.705417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2027 00:54:17.705903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2029 00:54:17.799399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2030 00:54:17.799895 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2032 00:54:17.897424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2033 00:54:17.898009 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2035 00:54:17.993355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2036 00:54:17.993844 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2038 00:54:18.090700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2039 00:54:18.091191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2041 00:54:18.183794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2042 00:54:18.184283 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2044 00:54:18.281151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2045 00:54:18.281719 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2047 00:54:18.377839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2048 00:54:18.378327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2050 00:54:18.471661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2051 00:54:18.472150 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2053 00:54:18.567862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2054 00:54:18.568346 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2056 00:54:18.662001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2057 00:54:18.662515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2059 00:54:18.757113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2060 00:54:18.757598 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2062 00:54:18.851125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2063 00:54:18.851674 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2065 00:54:18.946458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2066 00:54:18.946949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2068 00:54:19.040198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2069 00:54:19.040690 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2071 00:54:19.135691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2072 00:54:19.136180 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2074 00:54:19.229586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2075 00:54:19.230146 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2077 00:54:19.326314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2078 00:54:19.326809 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2080 00:54:19.420077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2081 00:54:19.420566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2083 00:54:19.514809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2084 00:54:19.515297 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2086 00:54:19.609571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2087 00:54:19.610062 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2089 00:54:19.709103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2090 00:54:19.709590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2092 00:54:19.807061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2093 00:54:19.807553 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2095 00:54:19.901997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2096 00:54:19.902558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2098 00:54:19.999656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2099 00:54:20.000145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2101 00:54:20.092668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2102 00:54:20.093176 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2104 00:54:20.190489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2105 00:54:20.190970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2107 00:54:20.281181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2108 00:54:20.281740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2110 00:54:20.374836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2111 00:54:20.375315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2113 00:54:20.466140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2114 00:54:20.466619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2116 00:54:20.561993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2117 00:54:20.562471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2119 00:54:20.657177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2120 00:54:20.657730 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2122 00:54:20.756290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2123 00:54:20.756770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2125 00:54:20.853284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2126 00:54:20.853847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2128 00:54:20.943871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2129 00:54:20.944360 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2131 00:54:21.039267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2132 00:54:21.039754 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2134 00:54:21.131861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2135 00:54:21.132349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2137 00:54:21.228992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2138 00:54:21.229550 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2140 00:54:21.321615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2141 00:54:21.322103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2143 00:54:21.417625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2144 00:54:21.418112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2146 00:54:21.509850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2147 00:54:21.510330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2149 00:54:21.605374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2150 00:54:21.605864 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2152 00:54:21.706564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2153 00:54:21.707050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2155 00:54:21.806398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2156 00:54:21.806880 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2158 00:54:21.903999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2159 00:54:21.904539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2161 00:54:22.002994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2162 00:54:22.003474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2164 00:54:22.099824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2165 00:54:22.100311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2167 00:54:22.198093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2168 00:54:22.198600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2170 00:54:22.296856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2171 00:54:22.297430 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2173 00:54:22.396687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2174 00:54:22.397192 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2176 00:54:22.494184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2177 00:54:22.494687 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2179 00:54:22.590316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2180 00:54:22.590845 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2182 00:54:22.681193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2183 00:54:22.681693 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2185 00:54:22.777798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2186 00:54:22.778294 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2188 00:54:22.871312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2189 00:54:22.871874 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2191 00:54:22.963682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2192 00:54:22.964168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2194 00:54:23.060880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2195 00:54:23.061368 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2197 00:54:23.156803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2198 00:54:23.157291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2200 00:54:23.254676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2201 00:54:23.255259 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2203 00:54:23.350035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2204 00:54:23.350561 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2206 00:54:23.446783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2207 00:54:23.447282 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2209 00:54:23.546344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2210 00:54:23.546854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2212 00:54:23.647312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2213 00:54:23.647808 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2215 00:54:23.740793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2216 00:54:23.741305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2218 00:54:23.841165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2219 00:54:23.841662 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2221 00:54:23.945409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2222 00:54:23.945986 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2224 00:54:24.044503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2225 00:54:24.045028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2227 00:54:24.145644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2228 00:54:24.146144 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2230 00:54:24.245420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2231 00:54:24.245988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2233 00:54:24.343994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2234 00:54:24.344473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2236 00:54:24.443839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2237 00:54:24.444335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2239 00:54:24.545366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2240 00:54:24.545853 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2242 00:54:24.640745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2243 00:54:24.641242 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2245 00:54:24.735701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2246 00:54:24.736197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2248 00:54:24.836612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2249 00:54:24.837142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2251 00:54:24.930132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2252 00:54:24.930686 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2254 00:54:25.027575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2255 00:54:25.028056 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2257 00:54:25.124975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2258 00:54:25.125457 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2260 00:54:25.222621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2261 00:54:25.223183 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2263 00:54:25.321230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2264 00:54:25.321722 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2266 00:54:25.422063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2267 00:54:25.422545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2269 00:54:25.521870 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2271 00:54:25.524728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2272 00:54:25.616930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2273 00:54:25.617413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2275 00:54:25.715947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2276 00:54:25.716442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2278 00:54:25.813551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2279 00:54:25.814032 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2281 00:54:25.910319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2282 00:54:25.910896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2284 00:54:26.008662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2285 00:54:26.009163 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2287 00:54:26.106705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2288 00:54:26.107195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2290 00:54:26.203411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2291 00:54:26.203901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2293 00:54:26.302537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2294 00:54:26.303109 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2296 00:54:26.400655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2297 00:54:26.401184 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2299 00:54:26.499294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2300 00:54:26.499782 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2302 00:54:26.598266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2303 00:54:26.598723 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2305 00:54:26.692868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2306 00:54:26.693349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2308 00:54:26.793281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2309 00:54:26.793759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2311 00:54:26.891539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2312 00:54:26.892087 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2314 00:54:26.988644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2315 00:54:26.989148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2317 00:54:27.083752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2318 00:54:27.084246 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2320 00:54:27.184798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2321 00:54:27.185277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2323 00:54:27.283504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2324 00:54:27.284059 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2326 00:54:27.382872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2327 00:54:27.383350 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2329 00:54:27.481825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2330 00:54:27.482310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2332 00:54:27.580043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2333 00:54:27.580524 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2335 00:54:27.678970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2336 00:54:27.679441 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2338 00:54:27.777522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2339 00:54:27.777973 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2341 00:54:27.873573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2342 00:54:27.874126 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2344 00:54:27.968756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2345 00:54:27.969224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2347 00:54:28.066288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2348 00:54:28.066780 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2350 00:54:28.164048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2351 00:54:28.164541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2353 00:54:28.263893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2354 00:54:28.264453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2356 00:54:28.365784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2357 00:54:28.366288 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2359 00:54:28.465275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2360 00:54:28.465773 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2362 00:54:28.562022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2363 00:54:28.562308 + set +x
2364 00:54:28.562760 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2366 00:54:28.566258 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 1221114_1.6.2.4.5>
2367 00:54:28.566743 Received signal: <ENDRUN> 1_kselftest-dt 1221114_1.6.2.4.5
2368 00:54:28.566995 Ending use of test pattern.
2369 00:54:28.567215 Ending test lava.1_kselftest-dt (1221114_1.6.2.4.5), duration 94.82
2371 00:54:28.571626 <LAVA_TEST_RUNNER EXIT>
2372 00:54:28.572110 ok: lava_test_shell seems to have completed
2373 00:54:28.577981 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2374 00:54:28.579041 end: 3.1 lava-test-shell (duration 00:01:36) [common]
2375 00:54:28.579338 end: 3 lava-test-retry (duration 00:01:36) [common]
2376 00:54:28.579642 start: 4 finalize (timeout 00:05:47) [common]
2377 00:54:28.579951 start: 4.1 power-off (timeout 00:00:30) [common]
2378 00:54:28.580334 Calling: 'curl' 'http://192.168.11.5:18083/1-1.3.4/1/off'
2379 00:54:28.944927 Returned 0 in 0 seconds
2380 00:54:29.045842 end: 4.1 power-off (duration 00:00:00) [common]
2382 00:54:29.046761 start: 4.2 read-feedback (timeout 00:05:46) [common]
2383 00:54:29.047390 Listened to connection for namespace 'common' for up to 1s
2384 00:54:29.047945 Listened to connection for namespace 'common' for up to 1s
2385 00:54:30.048266 Finalising connection for namespace 'common'
2386 00:54:30.048694 Disconnecting from shell: Finalise
2387 00:54:30.049001 / #
2388 00:54:30.149539 end: 4.2 read-feedback (duration 00:00:01) [common]
2389 00:54:30.149902 end: 4 finalize (duration 00:00:02) [common]
2390 00:54:30.150259 Cleaning after the job
2391 00:54:30.150582 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1221114/tftp-deploy-z1p4nya7/ramdisk
2392 00:54:30.154212 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1221114/tftp-deploy-z1p4nya7/kernel
2393 00:54:30.157126 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1221114/tftp-deploy-z1p4nya7/dtb
2394 00:54:30.157596 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1221114/tftp-deploy-z1p4nya7/nfsrootfs
2395 00:54:30.211437 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/1221114/tftp-deploy-z1p4nya7/modules
2396 00:54:30.214798 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/1221114
2397 00:54:30.869028 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/1221114
2398 00:54:30.869301 Job finished correctly