Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 00:39:03.824490 lava-dispatcher, installed at version: 2024.01
2 00:39:03.825318 start: 0 validate
3 00:39:03.825797 Start time: 2024-11-11 00:39:03.825766+00:00 (UTC)
4 00:39:03.826328 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 00:39:03.826875 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 00:39:03.873693 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 00:39:03.874315 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-415-g0e90fad093db9%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 00:39:03.907279 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 00:39:03.907926 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-415-g0e90fad093db9%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 00:39:04.960595 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 00:39:04.961107 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-415-g0e90fad093db9%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 00:39:05.010388 validate duration: 1.18
14 00:39:05.011878 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 00:39:05.012549 start: 1.1 download-retry (timeout 00:10:00) [common]
16 00:39:05.013132 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 00:39:05.014108 Not decompressing ramdisk as can be used compressed.
18 00:39:05.014860 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 00:39:05.015315 saving as /var/lib/lava/dispatcher/tmp/973335/tftp-deploy-_xtyjg5m/ramdisk/rootfs.cpio.gz
20 00:39:05.015795 total size: 8181887 (7 MB)
21 00:39:05.057988 progress 0 % (0 MB)
22 00:39:05.071889 progress 5 % (0 MB)
23 00:39:05.082892 progress 10 % (0 MB)
24 00:39:05.090144 progress 15 % (1 MB)
25 00:39:05.096857 progress 20 % (1 MB)
26 00:39:05.103875 progress 25 % (1 MB)
27 00:39:05.110543 progress 30 % (2 MB)
28 00:39:05.117552 progress 35 % (2 MB)
29 00:39:05.123870 progress 40 % (3 MB)
30 00:39:05.130764 progress 45 % (3 MB)
31 00:39:05.137118 progress 50 % (3 MB)
32 00:39:05.143886 progress 55 % (4 MB)
33 00:39:05.150248 progress 60 % (4 MB)
34 00:39:05.157013 progress 65 % (5 MB)
35 00:39:05.163291 progress 70 % (5 MB)
36 00:39:05.170054 progress 75 % (5 MB)
37 00:39:05.176395 progress 80 % (6 MB)
38 00:39:05.183131 progress 85 % (6 MB)
39 00:39:05.189432 progress 90 % (7 MB)
40 00:39:05.196252 progress 95 % (7 MB)
41 00:39:05.202078 progress 100 % (7 MB)
42 00:39:05.202837 7 MB downloaded in 0.19 s (41.72 MB/s)
43 00:39:05.203510 end: 1.1.1 http-download (duration 00:00:00) [common]
45 00:39:05.204663 end: 1.1 download-retry (duration 00:00:00) [common]
46 00:39:05.205040 start: 1.2 download-retry (timeout 00:10:00) [common]
47 00:39:05.205384 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 00:39:05.206067 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-415-g0e90fad093db9/arm64/defconfig/gcc-12/kernel/Image
49 00:39:05.206375 saving as /var/lib/lava/dispatcher/tmp/973335/tftp-deploy-_xtyjg5m/kernel/Image
50 00:39:05.206633 total size: 45715968 (43 MB)
51 00:39:05.206902 No compression specified
52 00:39:05.248243 progress 0 % (0 MB)
53 00:39:05.276337 progress 5 % (2 MB)
54 00:39:05.304187 progress 10 % (4 MB)
55 00:39:05.331816 progress 15 % (6 MB)
56 00:39:05.359537 progress 20 % (8 MB)
57 00:39:05.386916 progress 25 % (10 MB)
58 00:39:05.414691 progress 30 % (13 MB)
59 00:39:05.442643 progress 35 % (15 MB)
60 00:39:05.470457 progress 40 % (17 MB)
61 00:39:05.498067 progress 45 % (19 MB)
62 00:39:05.526353 progress 50 % (21 MB)
63 00:39:05.554762 progress 55 % (24 MB)
64 00:39:05.583068 progress 60 % (26 MB)
65 00:39:05.610695 progress 65 % (28 MB)
66 00:39:05.638947 progress 70 % (30 MB)
67 00:39:05.667610 progress 75 % (32 MB)
68 00:39:05.696488 progress 80 % (34 MB)
69 00:39:05.724741 progress 85 % (37 MB)
70 00:39:05.753654 progress 90 % (39 MB)
71 00:39:05.782173 progress 95 % (41 MB)
72 00:39:05.810119 progress 100 % (43 MB)
73 00:39:05.810710 43 MB downloaded in 0.60 s (72.17 MB/s)
74 00:39:05.811198 end: 1.2.1 http-download (duration 00:00:01) [common]
76 00:39:05.812030 end: 1.2 download-retry (duration 00:00:01) [common]
77 00:39:05.812312 start: 1.3 download-retry (timeout 00:09:59) [common]
78 00:39:05.812577 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 00:39:05.813052 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-415-g0e90fad093db9/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 00:39:05.813321 saving as /var/lib/lava/dispatcher/tmp/973335/tftp-deploy-_xtyjg5m/dtb/meson-g12b-a311d-libretech-cc.dtb
81 00:39:05.813529 total size: 54703 (0 MB)
82 00:39:05.813738 No compression specified
83 00:39:05.850255 progress 59 % (0 MB)
84 00:39:05.851147 progress 100 % (0 MB)
85 00:39:05.851719 0 MB downloaded in 0.04 s (1.37 MB/s)
86 00:39:05.852279 end: 1.3.1 http-download (duration 00:00:00) [common]
88 00:39:05.853123 end: 1.3 download-retry (duration 00:00:00) [common]
89 00:39:05.853385 start: 1.4 download-retry (timeout 00:09:59) [common]
90 00:39:05.853677 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 00:39:05.854186 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-415-g0e90fad093db9/arm64/defconfig/gcc-12/modules.tar.xz
92 00:39:05.854441 saving as /var/lib/lava/dispatcher/tmp/973335/tftp-deploy-_xtyjg5m/modules/modules.tar
93 00:39:05.854648 total size: 11620588 (11 MB)
94 00:39:05.854858 Using unxz to decompress xz
95 00:39:05.894127 progress 0 % (0 MB)
96 00:39:05.976943 progress 5 % (0 MB)
97 00:39:06.055602 progress 10 % (1 MB)
98 00:39:06.154749 progress 15 % (1 MB)
99 00:39:06.247307 progress 20 % (2 MB)
100 00:39:06.327451 progress 25 % (2 MB)
101 00:39:06.403554 progress 30 % (3 MB)
102 00:39:06.483222 progress 35 % (3 MB)
103 00:39:06.556657 progress 40 % (4 MB)
104 00:39:06.633048 progress 45 % (5 MB)
105 00:39:06.719637 progress 50 % (5 MB)
106 00:39:06.802349 progress 55 % (6 MB)
107 00:39:06.883565 progress 60 % (6 MB)
108 00:39:06.965672 progress 65 % (7 MB)
109 00:39:07.047514 progress 70 % (7 MB)
110 00:39:07.127226 progress 75 % (8 MB)
111 00:39:07.212078 progress 80 % (8 MB)
112 00:39:07.293476 progress 85 % (9 MB)
113 00:39:07.378127 progress 90 % (10 MB)
114 00:39:07.452156 progress 95 % (10 MB)
115 00:39:07.529407 progress 100 % (11 MB)
116 00:39:07.543214 11 MB downloaded in 1.69 s (6.56 MB/s)
117 00:39:07.543895 end: 1.4.1 http-download (duration 00:00:02) [common]
119 00:39:07.545468 end: 1.4 download-retry (duration 00:00:02) [common]
120 00:39:07.545997 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 00:39:07.546514 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 00:39:07.546999 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 00:39:07.547495 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 00:39:07.548530 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_
125 00:39:07.549382 makedir: /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin
126 00:39:07.550019 makedir: /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/tests
127 00:39:07.550630 makedir: /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/results
128 00:39:07.551239 Creating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin/lava-add-keys
129 00:39:07.552238 Creating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin/lava-add-sources
130 00:39:07.553209 Creating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin/lava-background-process-start
131 00:39:07.554167 Creating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin/lava-background-process-stop
132 00:39:07.555159 Creating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin/lava-common-functions
133 00:39:07.556147 Creating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin/lava-echo-ipv4
134 00:39:07.557098 Creating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin/lava-install-packages
135 00:39:07.558008 Creating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin/lava-installed-packages
136 00:39:07.558914 Creating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin/lava-os-build
137 00:39:07.559928 Creating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin/lava-probe-channel
138 00:39:07.560925 Creating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin/lava-probe-ip
139 00:39:07.561847 Creating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin/lava-target-ip
140 00:39:07.562761 Creating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin/lava-target-mac
141 00:39:07.563670 Creating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin/lava-target-storage
142 00:39:07.564640 Creating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin/lava-test-case
143 00:39:07.565555 Creating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin/lava-test-event
144 00:39:07.566487 Creating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin/lava-test-feedback
145 00:39:07.567393 Creating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin/lava-test-raise
146 00:39:07.568337 Creating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin/lava-test-reference
147 00:39:07.569275 Creating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin/lava-test-runner
148 00:39:07.570189 Creating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin/lava-test-set
149 00:39:07.571093 Creating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin/lava-test-shell
150 00:39:07.572136 Updating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin/lava-install-packages (oe)
151 00:39:07.573190 Updating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/bin/lava-installed-packages (oe)
152 00:39:07.574041 Creating /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/environment
153 00:39:07.574781 LAVA metadata
154 00:39:07.575267 - LAVA_JOB_ID=973335
155 00:39:07.575689 - LAVA_DISPATCHER_IP=192.168.6.2
156 00:39:07.576419 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 00:39:07.578298 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 00:39:07.578920 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 00:39:07.579332 skipped lava-vland-overlay
160 00:39:07.579820 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 00:39:07.580377 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 00:39:07.580811 skipped lava-multinode-overlay
163 00:39:07.581298 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 00:39:07.581795 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 00:39:07.582271 Loading test definitions
166 00:39:07.582820 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 00:39:07.583259 Using /lava-973335 at stage 0
168 00:39:07.585571 uuid=973335_1.5.2.4.1 testdef=None
169 00:39:07.586188 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 00:39:07.586707 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 00:39:07.593283 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 00:39:07.594272 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 00:39:07.596969 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 00:39:07.598045 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 00:39:07.600642 runner path: /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/0/tests/0_dmesg test_uuid 973335_1.5.2.4.1
178 00:39:07.601292 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 00:39:07.602204 Creating lava-test-runner.conf files
181 00:39:07.602472 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/973335/lava-overlay-39uiouz_/lava-973335/0 for stage 0
182 00:39:07.602913 - 0_dmesg
183 00:39:07.603356 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 00:39:07.603689 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 00:39:07.630632 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 00:39:07.631122 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 00:39:07.631453 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 00:39:07.631780 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 00:39:07.632137 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 00:39:08.568652 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 00:39:08.569235 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 00:39:08.569744 extracting modules file /var/lib/lava/dispatcher/tmp/973335/tftp-deploy-_xtyjg5m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/973335/extract-overlay-ramdisk-5xa0zc2p/ramdisk
193 00:39:09.913468 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 00:39:09.913994 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 00:39:09.914262 [common] Applying overlay /var/lib/lava/dispatcher/tmp/973335/compress-overlay-j4vy6y5v/overlay-1.5.2.5.tar.gz to ramdisk
196 00:39:09.914473 [common] Applying overlay /var/lib/lava/dispatcher/tmp/973335/compress-overlay-j4vy6y5v/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/973335/extract-overlay-ramdisk-5xa0zc2p/ramdisk
197 00:39:09.944478 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 00:39:09.944896 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 00:39:09.945165 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 00:39:09.945393 Converting downloaded kernel to a uImage
201 00:39:09.945700 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/973335/tftp-deploy-_xtyjg5m/kernel/Image /var/lib/lava/dispatcher/tmp/973335/tftp-deploy-_xtyjg5m/kernel/uImage
202 00:39:10.419483 output: Image Name:
203 00:39:10.419910 output: Created: Mon Nov 11 00:39:09 2024
204 00:39:10.420159 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 00:39:10.420369 output: Data Size: 45715968 Bytes = 44644.50 KiB = 43.60 MiB
206 00:39:10.420570 output: Load Address: 01080000
207 00:39:10.420768 output: Entry Point: 01080000
208 00:39:10.420967 output:
209 00:39:10.421301 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 00:39:10.421567 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 00:39:10.421833 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 00:39:10.422082 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 00:39:10.422334 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 00:39:10.422588 Building ramdisk /var/lib/lava/dispatcher/tmp/973335/extract-overlay-ramdisk-5xa0zc2p/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/973335/extract-overlay-ramdisk-5xa0zc2p/ramdisk
215 00:39:13.050056 >> 181614 blocks
216 00:39:21.552837 Adding RAMdisk u-boot header.
217 00:39:21.553299 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/973335/extract-overlay-ramdisk-5xa0zc2p/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/973335/extract-overlay-ramdisk-5xa0zc2p/ramdisk.cpio.gz.uboot
218 00:39:21.825639 output: Image Name:
219 00:39:21.826069 output: Created: Mon Nov 11 00:39:21 2024
220 00:39:21.826281 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 00:39:21.826484 output: Data Size: 26062431 Bytes = 25451.59 KiB = 24.86 MiB
222 00:39:21.826683 output: Load Address: 00000000
223 00:39:21.826881 output: Entry Point: 00000000
224 00:39:21.827080 output:
225 00:39:21.827731 rename /var/lib/lava/dispatcher/tmp/973335/extract-overlay-ramdisk-5xa0zc2p/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/973335/tftp-deploy-_xtyjg5m/ramdisk/ramdisk.cpio.gz.uboot
226 00:39:21.828299 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 00:39:21.828901 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 00:39:21.829473 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 00:39:21.829969 No LXC device requested
230 00:39:21.830514 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 00:39:21.831064 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 00:39:21.831598 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 00:39:21.832080 Checking files for TFTP limit of 4294967296 bytes.
234 00:39:21.834985 end: 1 tftp-deploy (duration 00:00:17) [common]
235 00:39:21.835607 start: 2 uboot-action (timeout 00:05:00) [common]
236 00:39:21.836216 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 00:39:21.836765 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 00:39:21.837310 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 00:39:21.837887 Using kernel file from prepare-kernel: 973335/tftp-deploy-_xtyjg5m/kernel/uImage
240 00:39:21.838568 substitutions:
241 00:39:21.839018 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 00:39:21.839457 - {DTB_ADDR}: 0x01070000
243 00:39:21.839891 - {DTB}: 973335/tftp-deploy-_xtyjg5m/dtb/meson-g12b-a311d-libretech-cc.dtb
244 00:39:21.840367 - {INITRD}: 973335/tftp-deploy-_xtyjg5m/ramdisk/ramdisk.cpio.gz.uboot
245 00:39:21.840809 - {KERNEL_ADDR}: 0x01080000
246 00:39:21.841240 - {KERNEL}: 973335/tftp-deploy-_xtyjg5m/kernel/uImage
247 00:39:21.841678 - {LAVA_MAC}: None
248 00:39:21.842151 - {PRESEED_CONFIG}: None
249 00:39:21.842588 - {PRESEED_LOCAL}: None
250 00:39:21.843021 - {RAMDISK_ADDR}: 0x08000000
251 00:39:21.843447 - {RAMDISK}: 973335/tftp-deploy-_xtyjg5m/ramdisk/ramdisk.cpio.gz.uboot
252 00:39:21.843880 - {ROOT_PART}: None
253 00:39:21.844344 - {ROOT}: None
254 00:39:21.844774 - {SERVER_IP}: 192.168.6.2
255 00:39:21.845208 - {TEE_ADDR}: 0x83000000
256 00:39:21.845635 - {TEE}: None
257 00:39:21.846063 Parsed boot commands:
258 00:39:21.846478 - setenv autoload no
259 00:39:21.846906 - setenv initrd_high 0xffffffff
260 00:39:21.847331 - setenv fdt_high 0xffffffff
261 00:39:21.847756 - dhcp
262 00:39:21.848213 - setenv serverip 192.168.6.2
263 00:39:21.848641 - tftpboot 0x01080000 973335/tftp-deploy-_xtyjg5m/kernel/uImage
264 00:39:21.849071 - tftpboot 0x08000000 973335/tftp-deploy-_xtyjg5m/ramdisk/ramdisk.cpio.gz.uboot
265 00:39:21.849499 - tftpboot 0x01070000 973335/tftp-deploy-_xtyjg5m/dtb/meson-g12b-a311d-libretech-cc.dtb
266 00:39:21.849928 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 00:39:21.850382 - bootm 0x01080000 0x08000000 0x01070000
268 00:39:21.850945 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 00:39:21.852633 start: 2.3 connect-device (timeout 00:05:00) [common]
271 00:39:21.853125 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 00:39:21.868691 Setting prompt string to ['lava-test: # ']
273 00:39:21.870293 end: 2.3 connect-device (duration 00:00:00) [common]
274 00:39:21.870946 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 00:39:21.871531 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 00:39:21.872133 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 00:39:21.873376 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 00:39:21.910840 >> OK - accepted request
279 00:39:21.913049 Returned 0 in 0 seconds
280 00:39:22.014110 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 00:39:22.015156 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 00:39:22.015504 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 00:39:22.015810 Setting prompt string to ['Hit any key to stop autoboot']
285 00:39:22.016119 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 00:39:22.017115 Trying 192.168.56.21...
287 00:39:22.017400 Connected to conserv1.
288 00:39:22.017631 Escape character is '^]'.
289 00:39:22.017868
290 00:39:22.018108 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 00:39:22.018344
292 00:39:32.544769 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 00:39:32.545222 bl2_stage_init 0x01
294 00:39:32.545456 bl2_stage_init 0x81
295 00:39:32.550371 hw id: 0x0000 - pwm id 0x01
296 00:39:32.550703 bl2_stage_init 0xc1
297 00:39:32.550918 bl2_stage_init 0x02
298 00:39:32.551131
299 00:39:32.555882 L0:00000000
300 00:39:32.556209 L1:20000703
301 00:39:32.556414 L2:00008067
302 00:39:32.556609 L3:14000000
303 00:39:32.558773 B2:00402000
304 00:39:32.559037 B1:e0f83180
305 00:39:32.559242
306 00:39:32.559445 TE: 58124
307 00:39:32.559646
308 00:39:32.570004 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 00:39:32.570368
310 00:39:32.570580 Board ID = 1
311 00:39:32.570782 Set A53 clk to 24M
312 00:39:32.570984 Set A73 clk to 24M
313 00:39:32.575641 Set clk81 to 24M
314 00:39:32.575918 A53 clk: 1200 MHz
315 00:39:32.576275 A73 clk: 1200 MHz
316 00:39:32.581155 CLK81: 166.6M
317 00:39:32.581660 smccc: 00012a92
318 00:39:32.586730 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 00:39:32.587231 board id: 1
320 00:39:32.595321 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 00:39:32.606212 fw parse done
322 00:39:32.612041 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 00:39:32.654578 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 00:39:32.665493 PIEI prepare done
325 00:39:32.665998 fastboot data load
326 00:39:32.666431 fastboot data verify
327 00:39:32.671153 verify result: 266
328 00:39:32.676834 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 00:39:32.677344 LPDDR4 probe
330 00:39:32.677776 ddr clk to 1584MHz
331 00:39:32.684663 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 00:39:32.722017
333 00:39:32.722582 dmc_version 0001
334 00:39:32.728634 Check phy result
335 00:39:32.734366 INFO : End of CA training
336 00:39:32.734651 INFO : End of initialization
337 00:39:32.740047 INFO : Training has run successfully!
338 00:39:32.740331 Check phy result
339 00:39:32.745582 INFO : End of initialization
340 00:39:32.745859 INFO : End of read enable training
341 00:39:32.751167 INFO : End of fine write leveling
342 00:39:32.756803 INFO : End of Write leveling coarse delay
343 00:39:32.757121 INFO : Training has run successfully!
344 00:39:32.757329 Check phy result
345 00:39:32.762301 INFO : End of initialization
346 00:39:32.762711 INFO : End of read dq deskew training
347 00:39:32.768020 INFO : End of MPR read delay center optimization
348 00:39:32.773509 INFO : End of write delay center optimization
349 00:39:32.779096 INFO : End of read delay center optimization
350 00:39:32.779523 INFO : End of max read latency training
351 00:39:32.784722 INFO : Training has run successfully!
352 00:39:32.785040 1D training succeed
353 00:39:32.794028 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 00:39:32.841609 Check phy result
355 00:39:32.841992 INFO : End of initialization
356 00:39:32.864214 INFO : End of 2D read delay Voltage center optimization
357 00:39:32.884440 INFO : End of 2D read delay Voltage center optimization
358 00:39:32.936671 INFO : End of 2D write delay Voltage center optimization
359 00:39:32.985843 INFO : End of 2D write delay Voltage center optimization
360 00:39:32.991465 INFO : Training has run successfully!
361 00:39:32.991975
362 00:39:32.992500 channel==0
363 00:39:32.997154 RxClkDly_Margin_A0==88 ps 9
364 00:39:32.997647 TxDqDly_Margin_A0==98 ps 10
365 00:39:33.002711 RxClkDly_Margin_A1==88 ps 9
366 00:39:33.003220 TxDqDly_Margin_A1==98 ps 10
367 00:39:33.003685 TrainedVREFDQ_A0==74
368 00:39:33.008312 TrainedVREFDQ_A1==74
369 00:39:33.008806 VrefDac_Margin_A0==24
370 00:39:33.009260 DeviceVref_Margin_A0==40
371 00:39:33.013803 VrefDac_Margin_A1==24
372 00:39:33.014306 DeviceVref_Margin_A1==40
373 00:39:33.014764
374 00:39:33.015218
375 00:39:33.019909 channel==1
376 00:39:33.020436 RxClkDly_Margin_A0==98 ps 10
377 00:39:33.020894 TxDqDly_Margin_A0==88 ps 9
378 00:39:33.025288 RxClkDly_Margin_A1==88 ps 9
379 00:39:33.025865 TxDqDly_Margin_A1==88 ps 9
380 00:39:33.030884 TrainedVREFDQ_A0==77
381 00:39:33.031404 TrainedVREFDQ_A1==77
382 00:39:33.031866 VrefDac_Margin_A0==22
383 00:39:33.036439 DeviceVref_Margin_A0==37
384 00:39:33.036935 VrefDac_Margin_A1==24
385 00:39:33.041836 DeviceVref_Margin_A1==37
386 00:39:33.042320
387 00:39:33.042783 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 00:39:33.043236
389 00:39:33.075439 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 0000001a 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
390 00:39:33.076059 2D training succeed
391 00:39:33.081099 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 00:39:33.086522 auto size-- 65535DDR cs0 size: 2048MB
393 00:39:33.087015 DDR cs1 size: 2048MB
394 00:39:33.092146 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 00:39:33.092646 cs0 DataBus test pass
396 00:39:33.097711 cs1 DataBus test pass
397 00:39:33.098203 cs0 AddrBus test pass
398 00:39:33.098656 cs1 AddrBus test pass
399 00:39:33.099103
400 00:39:33.103300 100bdlr_step_size ps== 420
401 00:39:33.103802 result report
402 00:39:33.108990 boot times 0Enable ddr reg access
403 00:39:33.114172 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 00:39:33.127660 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 00:39:33.701426 0.0;M3 CHK:0;cm4_sp_mode 0
406 00:39:33.702104 MVN_1=0x00000000
407 00:39:33.706813 MVN_2=0x00000000
408 00:39:33.712592 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 00:39:33.713088 OPS=0x10
410 00:39:33.713548 ring efuse init
411 00:39:33.713992 chipver efuse init
412 00:39:33.718193 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 00:39:33.723747 [0.018961 Inits done]
414 00:39:33.724277 secure task start!
415 00:39:33.724735 high task start!
416 00:39:33.728348 low task start!
417 00:39:33.728831 run into bl31
418 00:39:33.735136 NOTICE: BL31: v1.3(release):4fc40b1
419 00:39:33.742833 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 00:39:33.743333 NOTICE: BL31: G12A normal boot!
421 00:39:33.768162 NOTICE: BL31: BL33 decompress pass
422 00:39:33.773835 ERROR: Error initializing runtime service opteed_fast
423 00:39:35.006891
424 00:39:35.007548
425 00:39:35.015240 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 00:39:35.015750
427 00:39:35.016250 Model: Libre Computer AML-A311D-CC Alta
428 00:39:35.223723 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 00:39:35.247066 DRAM: 2 GiB (effective 3.8 GiB)
430 00:39:35.390211 Core: 408 devices, 31 uclasses, devicetree: separate
431 00:39:35.395848 WDT: Not starting watchdog@f0d0
432 00:39:35.428221 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 00:39:35.440629 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 00:39:35.445628 ** Bad device specification mmc 0 **
435 00:39:35.455909 Card did not respond to voltage select! : -110
436 00:39:35.463584 ** Bad device specification mmc 0 **
437 00:39:35.464094 Couldn't find partition mmc 0
438 00:39:35.471886 Card did not respond to voltage select! : -110
439 00:39:35.477408 ** Bad device specification mmc 0 **
440 00:39:35.477886 Couldn't find partition mmc 0
441 00:39:35.482490 Error: could not access storage.
442 00:39:36.745036 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 00:39:36.745704 bl2_stage_init 0x01
444 00:39:36.746185 bl2_stage_init 0x81
445 00:39:36.750568 hw id: 0x0000 - pwm id 0x01
446 00:39:36.751062 bl2_stage_init 0xc1
447 00:39:36.751518 bl2_stage_init 0x02
448 00:39:36.751963
449 00:39:36.756170 L0:00000000
450 00:39:36.756659 L1:20000703
451 00:39:36.757109 L2:00008067
452 00:39:36.757551 L3:14000000
453 00:39:36.759054 B2:00402000
454 00:39:36.759545 B1:e0f83180
455 00:39:36.760022
456 00:39:36.760478 TE: 58124
457 00:39:36.760925
458 00:39:36.770228 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 00:39:36.770751
460 00:39:36.771203 Board ID = 1
461 00:39:36.771645 Set A53 clk to 24M
462 00:39:36.772127 Set A73 clk to 24M
463 00:39:36.775856 Set clk81 to 24M
464 00:39:36.776367 A53 clk: 1200 MHz
465 00:39:36.776815 A73 clk: 1200 MHz
466 00:39:36.781562 CLK81: 166.6M
467 00:39:36.782087 smccc: 00012a92
468 00:39:36.787059 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 00:39:36.787553 board id: 1
470 00:39:36.795650 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 00:39:36.806316 fw parse done
472 00:39:36.812255 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 00:39:36.854923 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 00:39:36.865765 PIEI prepare done
475 00:39:36.866248 fastboot data load
476 00:39:36.866700 fastboot data verify
477 00:39:36.871396 verify result: 266
478 00:39:36.876981 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 00:39:36.877460 LPDDR4 probe
480 00:39:36.877907 ddr clk to 1584MHz
481 00:39:36.884965 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 00:39:36.922215
483 00:39:36.922713 dmc_version 0001
484 00:39:36.928972 Check phy result
485 00:39:36.934774 INFO : End of CA training
486 00:39:36.935248 INFO : End of initialization
487 00:39:36.940378 INFO : Training has run successfully!
488 00:39:36.940856 Check phy result
489 00:39:36.945973 INFO : End of initialization
490 00:39:36.946442 INFO : End of read enable training
491 00:39:36.951567 INFO : End of fine write leveling
492 00:39:36.957215 INFO : End of Write leveling coarse delay
493 00:39:36.957732 INFO : Training has run successfully!
494 00:39:36.958198 Check phy result
495 00:39:36.962802 INFO : End of initialization
496 00:39:36.963288 INFO : End of read dq deskew training
497 00:39:36.968384 INFO : End of MPR read delay center optimization
498 00:39:36.973988 INFO : End of write delay center optimization
499 00:39:36.979584 INFO : End of read delay center optimization
500 00:39:36.980089 INFO : End of max read latency training
501 00:39:36.985210 INFO : Training has run successfully!
502 00:39:36.985688 1D training succeed
503 00:39:36.994373 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 00:39:37.042076 Check phy result
505 00:39:37.042583 INFO : End of initialization
506 00:39:37.063690 INFO : End of 2D read delay Voltage center optimization
507 00:39:37.083685 INFO : End of 2D read delay Voltage center optimization
508 00:39:37.135664 INFO : End of 2D write delay Voltage center optimization
509 00:39:37.184801 INFO : End of 2D write delay Voltage center optimization
510 00:39:37.190385 INFO : Training has run successfully!
511 00:39:37.190872
512 00:39:37.191325 channel==0
513 00:39:37.195976 RxClkDly_Margin_A0==88 ps 9
514 00:39:37.196480 TxDqDly_Margin_A0==98 ps 10
515 00:39:37.201639 RxClkDly_Margin_A1==88 ps 9
516 00:39:37.202118 TxDqDly_Margin_A1==98 ps 10
517 00:39:37.202571 TrainedVREFDQ_A0==74
518 00:39:37.207172 TrainedVREFDQ_A1==75
519 00:39:37.207660 VrefDac_Margin_A0==25
520 00:39:37.208140 DeviceVref_Margin_A0==40
521 00:39:37.212799 VrefDac_Margin_A1==24
522 00:39:37.213283 DeviceVref_Margin_A1==39
523 00:39:37.213728
524 00:39:37.214169
525 00:39:37.218382 channel==1
526 00:39:37.218856 RxClkDly_Margin_A0==98 ps 10
527 00:39:37.219301 TxDqDly_Margin_A0==88 ps 9
528 00:39:37.223970 RxClkDly_Margin_A1==88 ps 9
529 00:39:37.224470 TxDqDly_Margin_A1==88 ps 9
530 00:39:37.229767 TrainedVREFDQ_A0==77
531 00:39:37.230246 TrainedVREFDQ_A1==77
532 00:39:37.230693 VrefDac_Margin_A0==22
533 00:39:37.235251 DeviceVref_Margin_A0==37
534 00:39:37.235724 VrefDac_Margin_A1==24
535 00:39:37.240779 DeviceVref_Margin_A1==37
536 00:39:37.241247
537 00:39:37.241691 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 00:39:37.242127
539 00:39:37.274368 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
540 00:39:37.274904 2D training succeed
541 00:39:37.279951 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 00:39:37.285659 auto size-- 65535DDR cs0 size: 2048MB
543 00:39:37.286142 DDR cs1 size: 2048MB
544 00:39:37.291165 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 00:39:37.291647 cs0 DataBus test pass
546 00:39:37.296759 cs1 DataBus test pass
547 00:39:37.297238 cs0 AddrBus test pass
548 00:39:37.297681 cs1 AddrBus test pass
549 00:39:37.298124
550 00:39:37.302403 100bdlr_step_size ps== 420
551 00:39:37.302891 result report
552 00:39:37.308005 boot times 0Enable ddr reg access
553 00:39:37.313226 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 00:39:37.326783 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 00:39:37.898964 0.0;M3 CHK:0;cm4_sp_mode 0
556 00:39:37.899619 MVN_1=0x00000000
557 00:39:37.904245 MVN_2=0x00000000
558 00:39:37.910011 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 00:39:37.910539 OPS=0x10
560 00:39:37.910994 ring efuse init
561 00:39:37.911463 chipver efuse init
562 00:39:37.915617 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 00:39:37.921206 [0.018961 Inits done]
564 00:39:37.921673 secure task start!
565 00:39:37.922098 high task start!
566 00:39:37.925765 low task start!
567 00:39:37.926225 run into bl31
568 00:39:37.932465 NOTICE: BL31: v1.3(release):4fc40b1
569 00:39:37.940188 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 00:39:37.940662 NOTICE: BL31: G12A normal boot!
571 00:39:37.965571 NOTICE: BL31: BL33 decompress pass
572 00:39:37.971221 ERROR: Error initializing runtime service opteed_fast
573 00:39:39.204330
574 00:39:39.204956
575 00:39:39.212739 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 00:39:39.213234
577 00:39:39.213693 Model: Libre Computer AML-A311D-CC Alta
578 00:39:39.421422 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 00:39:39.444665 DRAM: 2 GiB (effective 3.8 GiB)
580 00:39:39.587604 Core: 408 devices, 31 uclasses, devicetree: separate
581 00:39:39.593337 WDT: Not starting watchdog@f0d0
582 00:39:39.625641 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 00:39:39.638127 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 00:39:39.643211 ** Bad device specification mmc 0 **
585 00:39:39.653379 Card did not respond to voltage select! : -110
586 00:39:39.661183 ** Bad device specification mmc 0 **
587 00:39:39.661660 Couldn't find partition mmc 0
588 00:39:39.669358 Card did not respond to voltage select! : -110
589 00:39:39.674829 ** Bad device specification mmc 0 **
590 00:39:39.675309 Couldn't find partition mmc 0
591 00:39:39.679929 Error: could not access storage.
592 00:39:40.022639 Net: eth0: ethernet@ff3f0000
593 00:39:40.023224 starting USB...
594 00:39:40.274390 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 00:39:40.274961 Starting the controller
596 00:39:40.281306 USB XHCI 1.10
597 00:39:41.996811 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 00:39:41.997469 bl2_stage_init 0x01
599 00:39:41.997942 bl2_stage_init 0x81
600 00:39:42.002406 hw id: 0x0000 - pwm id 0x01
601 00:39:42.002893 bl2_stage_init 0xc1
602 00:39:42.003349 bl2_stage_init 0x02
603 00:39:42.003795
604 00:39:42.007851 L0:00000000
605 00:39:42.008358 L1:20000703
606 00:39:42.008808 L2:00008067
607 00:39:42.009248 L3:14000000
608 00:39:42.013524 B2:00402000
609 00:39:42.013992 B1:e0f83180
610 00:39:42.014437
611 00:39:42.014883 TE: 58167
612 00:39:42.015325
613 00:39:42.019085 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 00:39:42.019571
615 00:39:42.020047 Board ID = 1
616 00:39:42.024874 Set A53 clk to 24M
617 00:39:42.025352 Set A73 clk to 24M
618 00:39:42.025795 Set clk81 to 24M
619 00:39:42.030469 A53 clk: 1200 MHz
620 00:39:42.030950 A73 clk: 1200 MHz
621 00:39:42.031393 CLK81: 166.6M
622 00:39:42.031834 smccc: 00012abe
623 00:39:42.035937 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 00:39:42.041670 board id: 1
625 00:39:42.047624 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 00:39:42.057998 fw parse done
627 00:39:42.063909 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 00:39:42.106537 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 00:39:42.117467 PIEI prepare done
630 00:39:42.117942 fastboot data load
631 00:39:42.118393 fastboot data verify
632 00:39:42.123028 verify result: 266
633 00:39:42.128640 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 00:39:42.129118 LPDDR4 probe
635 00:39:42.129562 ddr clk to 1584MHz
636 00:39:42.136640 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 00:39:42.174045
638 00:39:42.174609 dmc_version 0001
639 00:39:42.180602 Check phy result
640 00:39:42.186480 INFO : End of CA training
641 00:39:42.186952 INFO : End of initialization
642 00:39:42.192043 INFO : Training has run successfully!
643 00:39:42.192515 Check phy result
644 00:39:42.197708 INFO : End of initialization
645 00:39:42.198189 INFO : End of read enable training
646 00:39:42.201021 INFO : End of fine write leveling
647 00:39:42.206593 INFO : End of Write leveling coarse delay
648 00:39:42.212216 INFO : Training has run successfully!
649 00:39:42.212682 Check phy result
650 00:39:42.213124 INFO : End of initialization
651 00:39:42.217775 INFO : End of read dq deskew training
652 00:39:42.221157 INFO : End of MPR read delay center optimization
653 00:39:42.226753 INFO : End of write delay center optimization
654 00:39:42.232375 INFO : End of read delay center optimization
655 00:39:42.232843 INFO : End of max read latency training
656 00:39:42.237965 INFO : Training has run successfully!
657 00:39:42.238437 1D training succeed
658 00:39:42.246108 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 00:39:42.293690 Check phy result
660 00:39:42.294237 INFO : End of initialization
661 00:39:42.316120 INFO : End of 2D read delay Voltage center optimization
662 00:39:42.336194 INFO : End of 2D read delay Voltage center optimization
663 00:39:42.388215 INFO : End of 2D write delay Voltage center optimization
664 00:39:42.437362 INFO : End of 2D write delay Voltage center optimization
665 00:39:42.442836 INFO : Training has run successfully!
666 00:39:42.443323
667 00:39:42.443785 channel==0
668 00:39:42.448520 RxClkDly_Margin_A0==88 ps 9
669 00:39:42.448999 TxDqDly_Margin_A0==98 ps 10
670 00:39:42.454133 RxClkDly_Margin_A1==88 ps 9
671 00:39:42.454610 TxDqDly_Margin_A1==88 ps 9
672 00:39:42.455069 TrainedVREFDQ_A0==74
673 00:39:42.459793 TrainedVREFDQ_A1==74
674 00:39:42.460290 VrefDac_Margin_A0==25
675 00:39:42.460738 DeviceVref_Margin_A0==40
676 00:39:42.465320 VrefDac_Margin_A1==24
677 00:39:42.465817 DeviceVref_Margin_A1==40
678 00:39:42.466265
679 00:39:42.466708
680 00:39:42.467145 channel==1
681 00:39:42.470946 RxClkDly_Margin_A0==98 ps 10
682 00:39:42.471424 TxDqDly_Margin_A0==98 ps 10
683 00:39:42.476451 RxClkDly_Margin_A1==98 ps 10
684 00:39:42.476926 TxDqDly_Margin_A1==88 ps 9
685 00:39:42.482067 TrainedVREFDQ_A0==77
686 00:39:42.482544 TrainedVREFDQ_A1==77
687 00:39:42.482992 VrefDac_Margin_A0==22
688 00:39:42.487638 DeviceVref_Margin_A0==37
689 00:39:42.488134 VrefDac_Margin_A1==24
690 00:39:42.493213 DeviceVref_Margin_A1==37
691 00:39:42.493680
692 00:39:42.494127 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 00:39:42.494562
694 00:39:42.526882 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000018 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
695 00:39:42.527465 2D training succeed
696 00:39:42.532496 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 00:39:42.538045 auto size-- 65535DDR cs0 size: 2048MB
698 00:39:42.538534 DDR cs1 size: 2048MB
699 00:39:42.543648 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 00:39:42.544176 cs0 DataBus test pass
701 00:39:42.549226 cs1 DataBus test pass
702 00:39:42.549707 cs0 AddrBus test pass
703 00:39:42.550152 cs1 AddrBus test pass
704 00:39:42.550592
705 00:39:42.554932 100bdlr_step_size ps== 420
706 00:39:42.555422 result report
707 00:39:42.560449 boot times 0Enable ddr reg access
708 00:39:42.565814 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 00:39:42.579274 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 00:39:43.151338 0.0;M3 CHK:0;cm4_sp_mode 0
711 00:39:43.152055 MVN_1=0x00000000
712 00:39:43.158541 MVN_2=0x00000000
713 00:39:43.162552 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 00:39:43.163147 OPS=0x10
715 00:39:43.163669 ring efuse init
716 00:39:43.164235 chipver efuse init
717 00:39:43.168163 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 00:39:43.173720 [0.018960 Inits done]
719 00:39:43.174277 secure task start!
720 00:39:43.174780 high task start!
721 00:39:43.178258 low task start!
722 00:39:43.178806 run into bl31
723 00:39:43.184946 NOTICE: BL31: v1.3(release):4fc40b1
724 00:39:43.192747 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 00:39:43.193318 NOTICE: BL31: G12A normal boot!
726 00:39:43.218116 NOTICE: BL31: BL33 decompress pass
727 00:39:43.223805 ERROR: Error initializing runtime service opteed_fast
728 00:39:44.456900
729 00:39:44.457689
730 00:39:44.465153 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 00:39:44.465759
732 00:39:44.466306 Model: Libre Computer AML-A311D-CC Alta
733 00:39:44.673763 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 00:39:44.696974 DRAM: 2 GiB (effective 3.8 GiB)
735 00:39:44.840039 Core: 408 devices, 31 uclasses, devicetree: separate
736 00:39:44.845810 WDT: Not starting watchdog@f0d0
737 00:39:44.878153 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 00:39:44.890642 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 00:39:44.895470 ** Bad device specification mmc 0 **
740 00:39:44.905933 Card did not respond to voltage select! : -110
741 00:39:44.914638 ** Bad device specification mmc 0 **
742 00:39:44.915229 Couldn't find partition mmc 0
743 00:39:44.921842 Card did not respond to voltage select! : -110
744 00:39:44.927367 ** Bad device specification mmc 0 **
745 00:39:44.927953 Couldn't find partition mmc 0
746 00:39:44.932405 Error: could not access storage.
747 00:39:45.274949 Net: eth0: ethernet@ff3f0000
748 00:39:45.275469 starting USB...
749 00:39:45.526879 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 00:39:45.527384 Starting the controller
751 00:39:45.533651 USB XHCI 1.10
752 00:39:47.695477 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 00:39:47.696299 bl2_stage_init 0x01
754 00:39:47.696868 bl2_stage_init 0x81
755 00:39:47.700912 hw id: 0x0000 - pwm id 0x01
756 00:39:47.701495 bl2_stage_init 0xc1
757 00:39:47.702018 bl2_stage_init 0x02
758 00:39:47.702536
759 00:39:47.706656 L0:00000000
760 00:39:47.707248 L1:20000703
761 00:39:47.707790 L2:00008067
762 00:39:47.708362 L3:14000000
763 00:39:47.709495 B2:00402000
764 00:39:47.710044 B1:e0f83180
765 00:39:47.710566
766 00:39:47.711082 TE: 58167
767 00:39:47.711608
768 00:39:47.720592 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 00:39:47.721185
770 00:39:47.721710 Board ID = 1
771 00:39:47.722225 Set A53 clk to 24M
772 00:39:47.722744 Set A73 clk to 24M
773 00:39:47.726256 Set clk81 to 24M
774 00:39:47.726819 A53 clk: 1200 MHz
775 00:39:47.727352 A73 clk: 1200 MHz
776 00:39:47.729687 CLK81: 166.6M
777 00:39:47.730250 smccc: 00012abe
778 00:39:47.735386 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 00:39:47.740978 board id: 1
780 00:39:47.746159 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 00:39:47.756705 fw parse done
782 00:39:47.762691 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 00:39:47.805346 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 00:39:47.816289 PIEI prepare done
785 00:39:47.816881 fastboot data load
786 00:39:47.817421 fastboot data verify
787 00:39:47.821761 verify result: 266
788 00:39:47.827446 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 00:39:47.828054 LPDDR4 probe
790 00:39:47.828581 ddr clk to 1584MHz
791 00:39:47.835312 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 00:39:47.872689
793 00:39:47.873394 dmc_version 0001
794 00:39:47.879339 Check phy result
795 00:39:47.885223 INFO : End of CA training
796 00:39:47.885848 INFO : End of initialization
797 00:39:47.890881 INFO : Training has run successfully!
798 00:39:47.891441 Check phy result
799 00:39:47.896329 INFO : End of initialization
800 00:39:47.896918 INFO : End of read enable training
801 00:39:47.901963 INFO : End of fine write leveling
802 00:39:47.907596 INFO : End of Write leveling coarse delay
803 00:39:47.908189 INFO : Training has run successfully!
804 00:39:47.908725 Check phy result
805 00:39:47.913195 INFO : End of initialization
806 00:39:47.913752 INFO : End of read dq deskew training
807 00:39:47.918874 INFO : End of MPR read delay center optimization
808 00:39:47.924307 INFO : End of write delay center optimization
809 00:39:47.929999 INFO : End of read delay center optimization
810 00:39:47.930553 INFO : End of max read latency training
811 00:39:47.935549 INFO : Training has run successfully!
812 00:39:47.936140 1D training succeed
813 00:39:47.944770 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 00:39:47.992424 Check phy result
815 00:39:47.993046 INFO : End of initialization
816 00:39:48.014037 INFO : End of 2D read delay Voltage center optimization
817 00:39:48.034167 INFO : End of 2D read delay Voltage center optimization
818 00:39:48.086037 INFO : End of 2D write delay Voltage center optimization
819 00:39:48.135320 INFO : End of 2D write delay Voltage center optimization
820 00:39:48.140847 INFO : Training has run successfully!
821 00:39:48.141460
822 00:39:48.141992 channel==0
823 00:39:48.146443 RxClkDly_Margin_A0==88 ps 9
824 00:39:48.147045 TxDqDly_Margin_A0==98 ps 10
825 00:39:48.152095 RxClkDly_Margin_A1==88 ps 9
826 00:39:48.152694 TxDqDly_Margin_A1==98 ps 10
827 00:39:48.153267 TrainedVREFDQ_A0==74
828 00:39:48.157665 TrainedVREFDQ_A1==74
829 00:39:48.158298 VrefDac_Margin_A0==25
830 00:39:48.158829 DeviceVref_Margin_A0==40
831 00:39:48.163404 VrefDac_Margin_A1==25
832 00:39:48.164070 DeviceVref_Margin_A1==40
833 00:39:48.164593
834 00:39:48.165111
835 00:39:48.168727 channel==1
836 00:39:48.169300 RxClkDly_Margin_A0==98 ps 10
837 00:39:48.169807 TxDqDly_Margin_A0==88 ps 9
838 00:39:48.174345 RxClkDly_Margin_A1==98 ps 10
839 00:39:48.174918 TxDqDly_Margin_A1==88 ps 9
840 00:39:48.180048 TrainedVREFDQ_A0==77
841 00:39:48.180618 TrainedVREFDQ_A1==77
842 00:39:48.181136 VrefDac_Margin_A0==22
843 00:39:48.185547 DeviceVref_Margin_A0==37
844 00:39:48.186121 VrefDac_Margin_A1==22
845 00:39:48.191311 DeviceVref_Margin_A1==37
846 00:39:48.191896
847 00:39:48.192448 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 00:39:48.192954
849 00:39:48.224623 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
850 00:39:48.225256 2D training succeed
851 00:39:48.230259 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 00:39:48.235895 auto size-- 65535DDR cs0 size: 2048MB
853 00:39:48.236485 DDR cs1 size: 2048MB
854 00:39:48.241535 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 00:39:48.242086 cs0 DataBus test pass
856 00:39:48.247144 cs1 DataBus test pass
857 00:39:48.247692 cs0 AddrBus test pass
858 00:39:48.248235 cs1 AddrBus test pass
859 00:39:48.248731
860 00:39:48.252744 100bdlr_step_size ps== 420
861 00:39:48.253320 result report
862 00:39:48.258246 boot times 0Enable ddr reg access
863 00:39:48.262651 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 00:39:48.277141 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 00:39:48.849281 0.0;M3 CHK:0;cm4_sp_mode 0
866 00:39:48.850101 MVN_1=0x00000000
867 00:39:48.854612 MVN_2=0x00000000
868 00:39:48.860336 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 00:39:48.860986 OPS=0x10
870 00:39:48.861543 ring efuse init
871 00:39:48.862074 chipver efuse init
872 00:39:48.865991 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 00:39:48.871610 [0.018960 Inits done]
874 00:39:48.872218 secure task start!
875 00:39:48.872650 high task start!
876 00:39:48.876202 low task start!
877 00:39:48.876694 run into bl31
878 00:39:48.882928 NOTICE: BL31: v1.3(release):4fc40b1
879 00:39:48.890585 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 00:39:48.891074 NOTICE: BL31: G12A normal boot!
881 00:39:48.915958 NOTICE: BL31: BL33 decompress pass
882 00:39:48.924179 ERROR: Error initializing runtime service opteed_fast
883 00:39:50.154566
884 00:39:50.155197
885 00:39:50.162634 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 00:39:50.163178
887 00:39:50.163634 Model: Libre Computer AML-A311D-CC Alta
888 00:39:50.370982 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 00:39:50.394220 DRAM: 2 GiB (effective 3.8 GiB)
890 00:39:50.537754 Core: 408 devices, 31 uclasses, devicetree: separate
891 00:39:50.543212 WDT: Not starting watchdog@f0d0
892 00:39:50.575930 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 00:39:50.588441 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 00:39:50.592396 ** Bad device specification mmc 0 **
895 00:39:50.603692 Card did not respond to voltage select! : -110
896 00:39:50.611246 ** Bad device specification mmc 0 **
897 00:39:50.611814 Couldn't find partition mmc 0
898 00:39:50.619697 Card did not respond to voltage select! : -110
899 00:39:50.625169 ** Bad device specification mmc 0 **
900 00:39:50.625730 Couldn't find partition mmc 0
901 00:39:50.630081 Error: could not access storage.
902 00:39:50.972404 Net: eth0: ethernet@ff3f0000
903 00:39:50.973073 starting USB...
904 00:39:51.224483 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 00:39:51.225144 Starting the controller
906 00:39:51.230452 USB XHCI 1.10
907 00:39:53.095003 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 00:39:53.095656 bl2_stage_init 0x01
909 00:39:53.096182 bl2_stage_init 0x81
910 00:39:53.100644 hw id: 0x0000 - pwm id 0x01
911 00:39:53.101171 bl2_stage_init 0xc1
912 00:39:53.101633 bl2_stage_init 0x02
913 00:39:53.102082
914 00:39:53.106244 L0:00000000
915 00:39:53.106757 L1:20000703
916 00:39:53.107209 L2:00008067
917 00:39:53.107648 L3:14000000
918 00:39:53.111848 B2:00402000
919 00:39:53.112393 B1:e0f83180
920 00:39:53.112847
921 00:39:53.113295 TE: 58167
922 00:39:53.113738
923 00:39:53.117459 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 00:39:53.117981
925 00:39:53.118436 Board ID = 1
926 00:39:53.123039 Set A53 clk to 24M
927 00:39:53.123553 Set A73 clk to 24M
928 00:39:53.124034 Set clk81 to 24M
929 00:39:53.128644 A53 clk: 1200 MHz
930 00:39:53.129151 A73 clk: 1200 MHz
931 00:39:53.129606 CLK81: 166.6M
932 00:39:53.130045 smccc: 00012abe
933 00:39:53.134203 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 00:39:53.139823 board id: 1
935 00:39:53.145354 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 00:39:53.156369 fw parse done
937 00:39:53.162380 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 00:39:53.204931 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 00:39:53.215944 PIEI prepare done
940 00:39:53.216498 fastboot data load
941 00:39:53.216933 fastboot data verify
942 00:39:53.221673 verify result: 266
943 00:39:53.227277 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 00:39:53.227781 LPDDR4 probe
945 00:39:53.228251 ddr clk to 1584MHz
946 00:39:53.235231 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 00:39:53.271714
948 00:39:53.272290 dmc_version 0001
949 00:39:53.278381 Check phy result
950 00:39:53.285065 INFO : End of CA training
951 00:39:53.285561 INFO : End of initialization
952 00:39:53.290664 INFO : Training has run successfully!
953 00:39:53.291160 Check phy result
954 00:39:53.296279 INFO : End of initialization
955 00:39:53.296848 INFO : End of read enable training
956 00:39:53.299696 INFO : End of fine write leveling
957 00:39:53.305050 INFO : End of Write leveling coarse delay
958 00:39:53.310723 INFO : Training has run successfully!
959 00:39:53.311235 Check phy result
960 00:39:53.311688 INFO : End of initialization
961 00:39:53.316270 INFO : End of read dq deskew training
962 00:39:53.321795 INFO : End of MPR read delay center optimization
963 00:39:53.322314 INFO : End of write delay center optimization
964 00:39:53.327411 INFO : End of read delay center optimization
965 00:39:53.333033 INFO : End of max read latency training
966 00:39:53.333554 INFO : Training has run successfully!
967 00:39:53.338598 1D training succeed
968 00:39:53.344603 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 00:39:53.392257 Check phy result
970 00:39:53.392876 INFO : End of initialization
971 00:39:53.414635 INFO : End of 2D read delay Voltage center optimization
972 00:39:53.434829 INFO : End of 2D read delay Voltage center optimization
973 00:39:53.486662 INFO : End of 2D write delay Voltage center optimization
974 00:39:53.535952 INFO : End of 2D write delay Voltage center optimization
975 00:39:53.541450 INFO : Training has run successfully!
976 00:39:53.541997
977 00:39:53.542465 channel==0
978 00:39:53.547108 RxClkDly_Margin_A0==88 ps 9
979 00:39:53.547648 TxDqDly_Margin_A0==98 ps 10
980 00:39:53.552731 RxClkDly_Margin_A1==88 ps 9
981 00:39:53.553266 TxDqDly_Margin_A1==98 ps 10
982 00:39:53.553725 TrainedVREFDQ_A0==74
983 00:39:53.558317 TrainedVREFDQ_A1==74
984 00:39:53.558848 VrefDac_Margin_A0==25
985 00:39:53.559300 DeviceVref_Margin_A0==40
986 00:39:53.563852 VrefDac_Margin_A1==24
987 00:39:53.564407 DeviceVref_Margin_A1==40
988 00:39:53.564860
989 00:39:53.565310
990 00:39:53.569515 channel==1
991 00:39:53.570062 RxClkDly_Margin_A0==98 ps 10
992 00:39:53.570514 TxDqDly_Margin_A0==98 ps 10
993 00:39:53.575132 RxClkDly_Margin_A1==98 ps 10
994 00:39:53.575654 TxDqDly_Margin_A1==88 ps 9
995 00:39:53.580724 TrainedVREFDQ_A0==77
996 00:39:53.581248 TrainedVREFDQ_A1==77
997 00:39:53.581702 VrefDac_Margin_A0==22
998 00:39:53.586292 DeviceVref_Margin_A0==37
999 00:39:53.586808 VrefDac_Margin_A1==24
1000 00:39:53.591907 DeviceVref_Margin_A1==37
1001 00:39:53.592453
1002 00:39:53.592904 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 00:39:53.597497
1004 00:39:53.625311 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1005 00:39:53.625937 2D training succeed
1006 00:39:53.631024 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 00:39:53.636624 auto size-- 65535DDR cs0 size: 2048MB
1008 00:39:53.637142 DDR cs1 size: 2048MB
1009 00:39:53.642158 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 00:39:53.642670 cs0 DataBus test pass
1011 00:39:53.647745 cs1 DataBus test pass
1012 00:39:53.648298 cs0 AddrBus test pass
1013 00:39:53.648748 cs1 AddrBus test pass
1014 00:39:53.649188
1015 00:39:53.653319 100bdlr_step_size ps== 420
1016 00:39:53.653842 result report
1017 00:39:53.658992 boot times 0Enable ddr reg access
1018 00:39:53.664370 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 00:39:53.677759 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 00:39:54.249819 0.0;M3 CHK:0;cm4_sp_mode 0
1021 00:39:54.250507 MVN_1=0x00000000
1022 00:39:54.255264 MVN_2=0x00000000
1023 00:39:54.261037 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 00:39:54.261555 OPS=0x10
1025 00:39:54.262012 ring efuse init
1026 00:39:54.262458 chipver efuse init
1027 00:39:54.266658 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 00:39:54.272262 [0.018960 Inits done]
1029 00:39:54.272792 secure task start!
1030 00:39:54.273248 high task start!
1031 00:39:54.276813 low task start!
1032 00:39:54.277329 run into bl31
1033 00:39:54.283479 NOTICE: BL31: v1.3(release):4fc40b1
1034 00:39:54.291277 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 00:39:54.291819 NOTICE: BL31: G12A normal boot!
1036 00:39:54.316653 NOTICE: BL31: BL33 decompress pass
1037 00:39:54.322316 ERROR: Error initializing runtime service opteed_fast
1038 00:39:55.555151
1039 00:39:55.555784
1040 00:39:55.563817 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 00:39:55.564900
1042 00:39:55.566566 Model: Libre Computer AML-A311D-CC Alta
1043 00:39:55.772126 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 00:39:55.795577 DRAM: 2 GiB (effective 3.8 GiB)
1045 00:39:55.938582 Core: 408 devices, 31 uclasses, devicetree: separate
1046 00:39:55.944586 WDT: Not starting watchdog@f0d0
1047 00:39:55.976580 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 00:39:55.989134 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 00:39:55.994645 ** Bad device specification mmc 0 **
1050 00:39:56.004286 Card did not respond to voltage select! : -110
1051 00:39:56.011931 ** Bad device specification mmc 0 **
1052 00:39:56.012502 Couldn't find partition mmc 0
1053 00:39:56.020830 Card did not respond to voltage select! : -110
1054 00:39:56.025774 ** Bad device specification mmc 0 **
1055 00:39:56.026382 Couldn't find partition mmc 0
1056 00:39:56.030909 Error: could not access storage.
1057 00:39:56.373393 Net: eth0: ethernet@ff3f0000
1058 00:39:56.373814 starting USB...
1059 00:39:56.626219 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 00:39:56.626902 Starting the controller
1061 00:39:56.633112 USB XHCI 1.10
1062 00:39:58.187224 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 00:39:58.195580 scanning usb for storage devices... 0 Storage Device(s) found
1065 00:39:58.246724 Hit any key to stop autoboot: 1
1066 00:39:58.247391 end: 2.4.2 bootloader-interrupt (duration 00:00:36) [common]
1067 00:39:58.247706 start: 2.4.3 bootloader-commands (timeout 00:04:24) [common]
1068 00:39:58.247951 Setting prompt string to ['=>']
1069 00:39:58.248228 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:24)
1070 00:39:58.252879 0
1071 00:39:58.253435 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 00:39:58.253711 Sending with 10 millisecond of delay
1074 00:39:59.388947 => setenv autoload no
1075 00:39:59.399818 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1076 00:39:59.405290 setenv autoload no
1077 00:39:59.406106 Sending with 10 millisecond of delay
1079 00:40:01.204272 => setenv initrd_high 0xffffffff
1080 00:40:01.215028 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1081 00:40:01.215601 setenv initrd_high 0xffffffff
1082 00:40:01.216113 Sending with 10 millisecond of delay
1084 00:40:02.833075 => setenv fdt_high 0xffffffff
1085 00:40:02.843913 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1086 00:40:02.844852 setenv fdt_high 0xffffffff
1087 00:40:02.845614 Sending with 10 millisecond of delay
1089 00:40:03.137528 => dhcp
1090 00:40:03.148158 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1091 00:40:03.148675 dhcp
1092 00:40:03.148917 Speed: 1000, full duplex
1093 00:40:03.149130 BOOTP broadcast 1
1094 00:40:03.157280 DHCP client bound to address 192.168.6.27 (9 ms)
1095 00:40:03.157853 Sending with 10 millisecond of delay
1097 00:40:04.834340 => setenv serverip 192.168.6.2
1098 00:40:04.844867 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1099 00:40:04.845380 setenv serverip 192.168.6.2
1100 00:40:04.845905 Sending with 10 millisecond of delay
1102 00:40:08.568837 => tftpboot 0x01080000 973335/tftp-deploy-_xtyjg5m/kernel/uImage
1103 00:40:08.579601 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1104 00:40:08.580160 tftpboot 0x01080000 973335/tftp-deploy-_xtyjg5m/kernel/uImage
1105 00:40:08.580419 Speed: 1000, full duplex
1106 00:40:08.580630 Using ethernet@ff3f0000 device
1107 00:40:08.582116 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1108 00:40:08.587923 Filename '973335/tftp-deploy-_xtyjg5m/kernel/uImage'.
1109 00:40:08.591200 Load address: 0x1080000
1110 00:40:11.635682 Loading: *################################################## 43.6 MiB
1111 00:40:11.636391 14.3 MiB/s
1112 00:40:11.636845 done
1113 00:40:11.640299 Bytes transferred = 45716032 (2b99240 hex)
1114 00:40:11.641136 Sending with 10 millisecond of delay
1116 00:40:16.329079 => tftpboot 0x08000000 973335/tftp-deploy-_xtyjg5m/ramdisk/ramdisk.cpio.gz.uboot
1117 00:40:16.339909 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1118 00:40:16.340852 tftpboot 0x08000000 973335/tftp-deploy-_xtyjg5m/ramdisk/ramdisk.cpio.gz.uboot
1119 00:40:16.341340 Speed: 1000, full duplex
1120 00:40:16.341795 Using ethernet@ff3f0000 device
1121 00:40:16.342858 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1122 00:40:16.351416 Filename '973335/tftp-deploy-_xtyjg5m/ramdisk/ramdisk.cpio.gz.uboot'.
1123 00:40:16.351958 Load address: 0x8000000
1124 00:40:23.480735 Loading: *##############T ################################### UDP wrong checksum 00000005 0000f3e6
1125 00:40:28.481143 T UDP wrong checksum 00000005 0000f3e6
1126 00:40:33.058962 UDP wrong checksum 000000ff 000029a6
1127 00:40:33.108510 UDP wrong checksum 000000ff 0000c398
1128 00:40:38.484358 T T UDP wrong checksum 00000005 0000f3e6
1129 00:40:58.488284 T T T T UDP wrong checksum 00000005 0000f3e6
1130 00:41:08.887507 T T UDP wrong checksum 000000ff 000075c9
1131 00:41:08.897500 UDP wrong checksum 000000ff 00000abc
1132 00:41:13.492517
1133 00:41:13.493190 Retry count exceeded; starting again
1135 00:41:13.494757 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1138 00:41:13.496901 end: 2.4 uboot-commands (duration 00:01:52) [common]
1140 00:41:13.498662 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1142 00:41:13.499887 end: 2 uboot-action (duration 00:01:52) [common]
1144 00:41:13.501716 Cleaning after the job
1145 00:41:13.502364 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973335/tftp-deploy-_xtyjg5m/ramdisk
1146 00:41:13.503972 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973335/tftp-deploy-_xtyjg5m/kernel
1147 00:41:13.556888 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973335/tftp-deploy-_xtyjg5m/dtb
1148 00:41:13.558246 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973335/tftp-deploy-_xtyjg5m/modules
1149 00:41:13.587831 start: 4.1 power-off (timeout 00:00:30) [common]
1150 00:41:13.588534 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1151 00:41:13.622215 >> OK - accepted request
1152 00:41:13.624604 Returned 0 in 0 seconds
1153 00:41:13.725696 end: 4.1 power-off (duration 00:00:00) [common]
1155 00:41:13.726670 start: 4.2 read-feedback (timeout 00:10:00) [common]
1156 00:41:13.727345 Listened to connection for namespace 'common' for up to 1s
1157 00:41:14.727420 Finalising connection for namespace 'common'
1158 00:41:14.728236 Disconnecting from shell: Finalise
1159 00:41:14.728833 =>
1160 00:41:14.830003 end: 4.2 read-feedback (duration 00:00:01) [common]
1161 00:41:14.830764 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/973335
1162 00:41:15.155011 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/973335
1163 00:41:15.155611 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.