Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:40:26.180785 lava-dispatcher, installed at version: 2024.01
2 01:40:26.181538 start: 0 validate
3 01:40:26.182016 Start time: 2024-11-11 01:40:26.181987+00:00 (UTC)
4 01:40:26.182557 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:40:26.183076 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 01:40:26.228616 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:40:26.229174 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-415-g0e90fad093db9%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 01:40:26.262802 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:40:26.263761 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-415-g0e90fad093db9%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 01:40:26.294658 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:40:26.295120 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-415-g0e90fad093db9%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 01:40:26.333938 validate duration: 0.15
14 01:40:26.334784 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 01:40:26.335113 start: 1.1 download-retry (timeout 00:10:00) [common]
16 01:40:26.335418 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 01:40:26.336017 Not decompressing ramdisk as can be used compressed.
18 01:40:26.336445 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 01:40:26.336717 saving as /var/lib/lava/dispatcher/tmp/973331/tftp-deploy-ub16foy5/ramdisk/rootfs.cpio.gz
20 01:40:26.336989 total size: 47897469 (45 MB)
21 01:40:26.386974 progress 0 % (0 MB)
22 01:40:26.424329 progress 5 % (2 MB)
23 01:40:26.460442 progress 10 % (4 MB)
24 01:40:26.496438 progress 15 % (6 MB)
25 01:40:26.532514 progress 20 % (9 MB)
26 01:40:26.569900 progress 25 % (11 MB)
27 01:40:26.599952 progress 30 % (13 MB)
28 01:40:26.629834 progress 35 % (16 MB)
29 01:40:26.659720 progress 40 % (18 MB)
30 01:40:26.689835 progress 45 % (20 MB)
31 01:40:26.719666 progress 50 % (22 MB)
32 01:40:26.749447 progress 55 % (25 MB)
33 01:40:26.779835 progress 60 % (27 MB)
34 01:40:26.809695 progress 65 % (29 MB)
35 01:40:26.839474 progress 70 % (32 MB)
36 01:40:26.869334 progress 75 % (34 MB)
37 01:40:26.899181 progress 80 % (36 MB)
38 01:40:26.929001 progress 85 % (38 MB)
39 01:40:26.959015 progress 90 % (41 MB)
40 01:40:26.989003 progress 95 % (43 MB)
41 01:40:27.018214 progress 100 % (45 MB)
42 01:40:27.018954 45 MB downloaded in 0.68 s (66.98 MB/s)
43 01:40:27.019536 end: 1.1.1 http-download (duration 00:00:01) [common]
45 01:40:27.020503 end: 1.1 download-retry (duration 00:00:01) [common]
46 01:40:27.020824 start: 1.2 download-retry (timeout 00:09:59) [common]
47 01:40:27.021113 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 01:40:27.021599 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-415-g0e90fad093db9/arm64/defconfig/gcc-12/kernel/Image
49 01:40:27.021856 saving as /var/lib/lava/dispatcher/tmp/973331/tftp-deploy-ub16foy5/kernel/Image
50 01:40:27.022075 total size: 45715968 (43 MB)
51 01:40:27.022295 No compression specified
52 01:40:27.073989 progress 0 % (0 MB)
53 01:40:27.101598 progress 5 % (2 MB)
54 01:40:27.129337 progress 10 % (4 MB)
55 01:40:27.157159 progress 15 % (6 MB)
56 01:40:27.184728 progress 20 % (8 MB)
57 01:40:27.211955 progress 25 % (10 MB)
58 01:40:27.239693 progress 30 % (13 MB)
59 01:40:27.267477 progress 35 % (15 MB)
60 01:40:27.295190 progress 40 % (17 MB)
61 01:40:27.322589 progress 45 % (19 MB)
62 01:40:27.350543 progress 50 % (21 MB)
63 01:40:27.378527 progress 55 % (24 MB)
64 01:40:27.406467 progress 60 % (26 MB)
65 01:40:27.433928 progress 65 % (28 MB)
66 01:40:27.462198 progress 70 % (30 MB)
67 01:40:27.490136 progress 75 % (32 MB)
68 01:40:27.518075 progress 80 % (34 MB)
69 01:40:27.545795 progress 85 % (37 MB)
70 01:40:27.573894 progress 90 % (39 MB)
71 01:40:27.601745 progress 95 % (41 MB)
72 01:40:27.628965 progress 100 % (43 MB)
73 01:40:27.629499 43 MB downloaded in 0.61 s (71.78 MB/s)
74 01:40:27.630006 end: 1.2.1 http-download (duration 00:00:01) [common]
76 01:40:27.630846 end: 1.2 download-retry (duration 00:00:01) [common]
77 01:40:27.631138 start: 1.3 download-retry (timeout 00:09:59) [common]
78 01:40:27.631419 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 01:40:27.632022 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-415-g0e90fad093db9/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 01:40:27.632320 saving as /var/lib/lava/dispatcher/tmp/973331/tftp-deploy-ub16foy5/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 01:40:27.632540 total size: 53209 (0 MB)
82 01:40:27.632758 No compression specified
83 01:40:27.682198 progress 61 % (0 MB)
84 01:40:27.683030 progress 100 % (0 MB)
85 01:40:27.683594 0 MB downloaded in 0.05 s (0.99 MB/s)
86 01:40:27.684090 end: 1.3.1 http-download (duration 00:00:00) [common]
88 01:40:27.684935 end: 1.3 download-retry (duration 00:00:00) [common]
89 01:40:27.685207 start: 1.4 download-retry (timeout 00:09:59) [common]
90 01:40:27.685480 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 01:40:27.685938 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-415-g0e90fad093db9/arm64/defconfig/gcc-12/modules.tar.xz
92 01:40:27.686187 saving as /var/lib/lava/dispatcher/tmp/973331/tftp-deploy-ub16foy5/modules/modules.tar
93 01:40:27.686397 total size: 11620588 (11 MB)
94 01:40:27.686612 Using unxz to decompress xz
95 01:40:27.722669 progress 0 % (0 MB)
96 01:40:27.799941 progress 5 % (0 MB)
97 01:40:27.886430 progress 10 % (1 MB)
98 01:40:27.999422 progress 15 % (1 MB)
99 01:40:28.107866 progress 20 % (2 MB)
100 01:40:28.201672 progress 25 % (2 MB)
101 01:40:28.290186 progress 30 % (3 MB)
102 01:40:28.373934 progress 35 % (3 MB)
103 01:40:28.446166 progress 40 % (4 MB)
104 01:40:28.521122 progress 45 % (5 MB)
105 01:40:28.605755 progress 50 % (5 MB)
106 01:40:28.686295 progress 55 % (6 MB)
107 01:40:28.765882 progress 60 % (6 MB)
108 01:40:28.845127 progress 65 % (7 MB)
109 01:40:28.924744 progress 70 % (7 MB)
110 01:40:29.002760 progress 75 % (8 MB)
111 01:40:29.087065 progress 80 % (8 MB)
112 01:40:29.167589 progress 85 % (9 MB)
113 01:40:29.250376 progress 90 % (10 MB)
114 01:40:29.326004 progress 95 % (10 MB)
115 01:40:29.401996 progress 100 % (11 MB)
116 01:40:29.415029 11 MB downloaded in 1.73 s (6.41 MB/s)
117 01:40:29.415670 end: 1.4.1 http-download (duration 00:00:02) [common]
119 01:40:29.417222 end: 1.4 download-retry (duration 00:00:02) [common]
120 01:40:29.417808 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 01:40:29.418380 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 01:40:29.418922 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 01:40:29.419470 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 01:40:29.420755 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz
125 01:40:29.421685 makedir: /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin
126 01:40:29.422377 makedir: /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/tests
127 01:40:29.423048 makedir: /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/results
128 01:40:29.423709 Creating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin/lava-add-keys
129 01:40:29.424762 Creating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin/lava-add-sources
130 01:40:29.425753 Creating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin/lava-background-process-start
131 01:40:29.426777 Creating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin/lava-background-process-stop
132 01:40:29.427831 Creating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin/lava-common-functions
133 01:40:29.428862 Creating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin/lava-echo-ipv4
134 01:40:29.429833 Creating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin/lava-install-packages
135 01:40:29.430873 Creating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin/lava-installed-packages
136 01:40:29.431833 Creating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin/lava-os-build
137 01:40:29.432842 Creating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin/lava-probe-channel
138 01:40:29.433810 Creating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin/lava-probe-ip
139 01:40:29.434769 Creating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin/lava-target-ip
140 01:40:29.435721 Creating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin/lava-target-mac
141 01:40:29.436817 Creating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin/lava-target-storage
142 01:40:29.437809 Creating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin/lava-test-case
143 01:40:29.438772 Creating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin/lava-test-event
144 01:40:29.439719 Creating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin/lava-test-feedback
145 01:40:29.440723 Creating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin/lava-test-raise
146 01:40:29.441628 Creating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin/lava-test-reference
147 01:40:29.442506 Creating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin/lava-test-runner
148 01:40:29.443380 Creating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin/lava-test-set
149 01:40:29.444277 Creating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin/lava-test-shell
150 01:40:29.445169 Updating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin/lava-install-packages (oe)
151 01:40:29.446127 Updating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/bin/lava-installed-packages (oe)
152 01:40:29.446936 Creating /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/environment
153 01:40:29.447620 LAVA metadata
154 01:40:29.448124 - LAVA_JOB_ID=973331
155 01:40:29.448353 - LAVA_DISPATCHER_IP=192.168.6.2
156 01:40:29.448713 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 01:40:29.449711 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 01:40:29.450051 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 01:40:29.450266 skipped lava-vland-overlay
160 01:40:29.450515 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 01:40:29.450776 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 01:40:29.450999 skipped lava-multinode-overlay
163 01:40:29.451246 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 01:40:29.451502 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 01:40:29.451750 Loading test definitions
166 01:40:29.452063 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 01:40:29.452301 Using /lava-973331 at stage 0
168 01:40:29.453445 uuid=973331_1.5.2.4.1 testdef=None
169 01:40:29.453767 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 01:40:29.454041 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 01:40:29.455751 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 01:40:29.456596 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 01:40:29.458736 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 01:40:29.459577 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 01:40:29.461676 runner path: /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/0/tests/0_igt-gpu-panfrost test_uuid 973331_1.5.2.4.1
178 01:40:29.462253 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 01:40:29.463074 Creating lava-test-runner.conf files
181 01:40:29.463283 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/973331/lava-overlay-310uprsz/lava-973331/0 for stage 0
182 01:40:29.463614 - 0_igt-gpu-panfrost
183 01:40:29.463965 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 01:40:29.464290 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 01:40:29.487493 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 01:40:29.487869 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 01:40:29.488164 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 01:40:29.488435 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 01:40:29.488702 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 01:40:36.614805 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 01:40:36.615280 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 01:40:36.615525 extracting modules file /var/lib/lava/dispatcher/tmp/973331/tftp-deploy-ub16foy5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/973331/extract-overlay-ramdisk-c494z5uf/ramdisk
193 01:40:38.056678 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 01:40:38.057168 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 01:40:38.057463 [common] Applying overlay /var/lib/lava/dispatcher/tmp/973331/compress-overlay-1nbnvglr/overlay-1.5.2.5.tar.gz to ramdisk
196 01:40:38.057690 [common] Applying overlay /var/lib/lava/dispatcher/tmp/973331/compress-overlay-1nbnvglr/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/973331/extract-overlay-ramdisk-c494z5uf/ramdisk
197 01:40:38.087860 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 01:40:38.088270 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 01:40:38.088562 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 01:40:38.088799 Converting downloaded kernel to a uImage
201 01:40:38.089113 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/973331/tftp-deploy-ub16foy5/kernel/Image /var/lib/lava/dispatcher/tmp/973331/tftp-deploy-ub16foy5/kernel/uImage
202 01:40:38.568144 output: Image Name:
203 01:40:38.568564 output: Created: Mon Nov 11 01:40:38 2024
204 01:40:38.568773 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 01:40:38.568977 output: Data Size: 45715968 Bytes = 44644.50 KiB = 43.60 MiB
206 01:40:38.569180 output: Load Address: 01080000
207 01:40:38.569378 output: Entry Point: 01080000
208 01:40:38.569577 output:
209 01:40:38.569910 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 01:40:38.570173 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 01:40:38.570443 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 01:40:38.570697 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 01:40:38.570954 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 01:40:38.571208 Building ramdisk /var/lib/lava/dispatcher/tmp/973331/extract-overlay-ramdisk-c494z5uf/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/973331/extract-overlay-ramdisk-c494z5uf/ramdisk
215 01:40:45.198164 >> 502418 blocks
216 01:41:05.823781 Adding RAMdisk u-boot header.
217 01:41:05.824617 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/973331/extract-overlay-ramdisk-c494z5uf/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/973331/extract-overlay-ramdisk-c494z5uf/ramdisk.cpio.gz.uboot
218 01:41:06.555103 output: Image Name:
219 01:41:06.555533 output: Created: Mon Nov 11 01:41:05 2024
220 01:41:06.555744 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 01:41:06.555947 output: Data Size: 65714059 Bytes = 64173.89 KiB = 62.67 MiB
222 01:41:06.556438 output: Load Address: 00000000
223 01:41:06.556882 output: Entry Point: 00000000
224 01:41:06.557336 output:
225 01:41:06.558366 rename /var/lib/lava/dispatcher/tmp/973331/extract-overlay-ramdisk-c494z5uf/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/973331/tftp-deploy-ub16foy5/ramdisk/ramdisk.cpio.gz.uboot
226 01:41:06.559127 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 01:41:06.559717 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 01:41:06.560342 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 01:41:06.560842 No LXC device requested
230 01:41:06.561391 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 01:41:06.561950 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 01:41:06.562488 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 01:41:06.562937 Checking files for TFTP limit of 4294967296 bytes.
234 01:41:06.565913 end: 1 tftp-deploy (duration 00:00:40) [common]
235 01:41:06.566566 start: 2 uboot-action (timeout 00:05:00) [common]
236 01:41:06.567136 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 01:41:06.567682 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 01:41:06.568288 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 01:41:06.568861 Using kernel file from prepare-kernel: 973331/tftp-deploy-ub16foy5/kernel/uImage
240 01:41:06.569520 substitutions:
241 01:41:06.569965 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 01:41:06.570404 - {DTB_ADDR}: 0x01070000
243 01:41:06.570843 - {DTB}: 973331/tftp-deploy-ub16foy5/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 01:41:06.571281 - {INITRD}: 973331/tftp-deploy-ub16foy5/ramdisk/ramdisk.cpio.gz.uboot
245 01:41:06.571713 - {KERNEL_ADDR}: 0x01080000
246 01:41:06.572185 - {KERNEL}: 973331/tftp-deploy-ub16foy5/kernel/uImage
247 01:41:06.572619 - {LAVA_MAC}: None
248 01:41:06.573091 - {PRESEED_CONFIG}: None
249 01:41:06.573524 - {PRESEED_LOCAL}: None
250 01:41:06.573949 - {RAMDISK_ADDR}: 0x08000000
251 01:41:06.574371 - {RAMDISK}: 973331/tftp-deploy-ub16foy5/ramdisk/ramdisk.cpio.gz.uboot
252 01:41:06.574800 - {ROOT_PART}: None
253 01:41:06.575222 - {ROOT}: None
254 01:41:06.575648 - {SERVER_IP}: 192.168.6.2
255 01:41:06.576107 - {TEE_ADDR}: 0x83000000
256 01:41:06.576539 - {TEE}: None
257 01:41:06.576966 Parsed boot commands:
258 01:41:06.577381 - setenv autoload no
259 01:41:06.577803 - setenv initrd_high 0xffffffff
260 01:41:06.578226 - setenv fdt_high 0xffffffff
261 01:41:06.578647 - dhcp
262 01:41:06.579068 - setenv serverip 192.168.6.2
263 01:41:06.579491 - tftpboot 0x01080000 973331/tftp-deploy-ub16foy5/kernel/uImage
264 01:41:06.579914 - tftpboot 0x08000000 973331/tftp-deploy-ub16foy5/ramdisk/ramdisk.cpio.gz.uboot
265 01:41:06.580367 - tftpboot 0x01070000 973331/tftp-deploy-ub16foy5/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 01:41:06.580789 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 01:41:06.581218 - bootm 0x01080000 0x08000000 0x01070000
268 01:41:06.581754 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 01:41:06.583359 start: 2.3 connect-device (timeout 00:05:00) [common]
271 01:41:06.583841 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 01:41:06.600025 Setting prompt string to ['lava-test: # ']
273 01:41:06.601653 end: 2.3 connect-device (duration 00:00:00) [common]
274 01:41:06.602333 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 01:41:06.602928 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 01:41:06.603484 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 01:41:06.605000 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 01:41:06.646220 >> OK - accepted request
279 01:41:06.648451 Returned 0 in 0 seconds
280 01:41:06.749716 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 01:41:06.751492 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 01:41:06.752147 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 01:41:06.752717 Setting prompt string to ['Hit any key to stop autoboot']
285 01:41:06.753218 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 01:41:06.754953 Trying 192.168.56.21...
287 01:41:06.755461 Connected to conserv1.
288 01:41:06.755912 Escape character is '^]'.
289 01:41:06.756393
290 01:41:06.756845 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 01:41:06.757309
292 01:41:14.264051 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 01:41:14.264688 bl2_stage_init 0x01
294 01:41:14.265108 bl2_stage_init 0x81
295 01:41:14.269707 hw id: 0x0000 - pwm id 0x01
296 01:41:14.270179 bl2_stage_init 0xc1
297 01:41:14.275188 bl2_stage_init 0x02
298 01:41:14.275712
299 01:41:14.276203 L0:00000000
300 01:41:14.276642 L1:00000703
301 01:41:14.277069 L2:00008067
302 01:41:14.277503 L3:15000000
303 01:41:14.280816 S1:00000000
304 01:41:14.281272 B2:20282000
305 01:41:14.281685 B1:a0f83180
306 01:41:14.282074
307 01:41:14.282463 TE: 69733
308 01:41:14.282849
309 01:41:14.286289 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 01:41:14.286753
311 01:41:14.291936 Board ID = 1
312 01:41:14.292423 Set cpu clk to 24M
313 01:41:14.292819 Set clk81 to 24M
314 01:41:14.297543 Use GP1_pll as DSU clk.
315 01:41:14.297987 DSU clk: 1200 Mhz
316 01:41:14.298379 CPU clk: 1200 MHz
317 01:41:14.303184 Set clk81 to 166.6M
318 01:41:14.308759 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 01:41:14.309220 board id: 1
320 01:41:14.316148 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 01:41:14.326928 fw parse done
322 01:41:14.332893 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 01:41:14.375914 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 01:41:14.386994 PIEI prepare done
325 01:41:14.387427 fastboot data load
326 01:41:14.387822 fastboot data verify
327 01:41:14.392562 verify result: 266
328 01:41:14.398164 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 01:41:14.398598 LPDDR4 probe
330 01:41:14.398988 ddr clk to 1584MHz
331 01:41:14.406142 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 01:41:14.443896
333 01:41:14.444371 dmc_version 0001
334 01:41:14.450997 Check phy result
335 01:41:14.456919 INFO : End of CA training
336 01:41:14.457341 INFO : End of initialization
337 01:41:14.462497 INFO : Training has run successfully!
338 01:41:14.462919 Check phy result
339 01:41:14.468127 INFO : End of initialization
340 01:41:14.468542 INFO : End of read enable training
341 01:41:14.473702 INFO : End of fine write leveling
342 01:41:14.479299 INFO : End of Write leveling coarse delay
343 01:41:14.479723 INFO : Training has run successfully!
344 01:41:14.480145 Check phy result
345 01:41:14.484895 INFO : End of initialization
346 01:41:14.485311 INFO : End of read dq deskew training
347 01:41:14.490475 INFO : End of MPR read delay center optimization
348 01:41:14.496084 INFO : End of write delay center optimization
349 01:41:14.501721 INFO : End of read delay center optimization
350 01:41:14.502160 INFO : End of max read latency training
351 01:41:14.507302 INFO : Training has run successfully!
352 01:41:14.507725 1D training succeed
353 01:41:14.516499 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 01:41:14.564797 Check phy result
355 01:41:14.565233 INFO : End of initialization
356 01:41:14.592154 INFO : End of 2D read delay Voltage center optimization
357 01:41:14.616299 INFO : End of 2D read delay Voltage center optimization
358 01:41:14.672928 INFO : End of 2D write delay Voltage center optimization
359 01:41:14.726842 INFO : End of 2D write delay Voltage center optimization
360 01:41:14.732393 INFO : Training has run successfully!
361 01:41:14.732818
362 01:41:14.733228 channel==0
363 01:41:14.738001 RxClkDly_Margin_A0==78 ps 8
364 01:41:14.738430 TxDqDly_Margin_A0==98 ps 10
365 01:41:14.743597 RxClkDly_Margin_A1==69 ps 7
366 01:41:14.744053 TxDqDly_Margin_A1==98 ps 10
367 01:41:14.744460 TrainedVREFDQ_A0==74
368 01:41:14.749195 TrainedVREFDQ_A1==74
369 01:41:14.749618 VrefDac_Margin_A0==23
370 01:41:14.750013 DeviceVref_Margin_A0==40
371 01:41:14.754833 VrefDac_Margin_A1==23
372 01:41:14.755253 DeviceVref_Margin_A1==40
373 01:41:14.755646
374 01:41:14.756066
375 01:41:14.760390 channel==1
376 01:41:14.760810 RxClkDly_Margin_A0==78 ps 8
377 01:41:14.761213 TxDqDly_Margin_A0==98 ps 10
378 01:41:14.765984 RxClkDly_Margin_A1==78 ps 8
379 01:41:14.766402 TxDqDly_Margin_A1==88 ps 9
380 01:41:14.771575 TrainedVREFDQ_A0==78
381 01:41:14.772026 TrainedVREFDQ_A1==75
382 01:41:14.772427 VrefDac_Margin_A0==22
383 01:41:14.777167 DeviceVref_Margin_A0==36
384 01:41:14.777584 VrefDac_Margin_A1==22
385 01:41:14.782832 DeviceVref_Margin_A1==38
386 01:41:14.783252
387 01:41:14.783650 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 01:41:14.784072
389 01:41:14.816388 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000019 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
390 01:41:14.816881 2D training succeed
391 01:41:14.822014 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 01:41:14.827591 auto size-- 65535DDR cs0 size: 2048MB
393 01:41:14.828034 DDR cs1 size: 2048MB
394 01:41:14.833189 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 01:41:14.833606 cs0 DataBus test pass
396 01:41:14.838844 cs1 DataBus test pass
397 01:41:14.839256 cs0 AddrBus test pass
398 01:41:14.839650 cs1 AddrBus test pass
399 01:41:14.840069
400 01:41:14.844377 100bdlr_step_size ps== 478
401 01:41:14.844796 result report
402 01:41:14.850016 boot times 0Enable ddr reg access
403 01:41:14.855254 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 01:41:14.869102 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 01:41:15.527497 bl2z: ptr: 05129330, size: 00001e40
406 01:41:15.535210 0.0;M3 CHK:0;cm4_sp_mode 0
407 01:41:15.535684 MVN_1=0x00000000
408 01:41:15.536125 MVN_2=0x00000000
409 01:41:15.546704 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 01:41:15.547152 OPS=0x04
411 01:41:15.547557 ring efuse init
412 01:41:15.549615 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 01:41:15.555249 [0.017354 Inits done]
414 01:41:15.555674 secure task start!
415 01:41:15.556099 high task start!
416 01:41:15.556498 low task start!
417 01:41:15.559563 run into bl31
418 01:41:15.568194 NOTICE: BL31: v1.3(release):4fc40b1
419 01:41:15.576096 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 01:41:15.576532 NOTICE: BL31: G12A normal boot!
421 01:41:15.591519 NOTICE: BL31: BL33 decompress pass
422 01:41:15.597199 ERROR: Error initializing runtime service opteed_fast
423 01:41:18.315519 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 01:41:18.316180 bl2_stage_init 0x01
425 01:41:18.316602 bl2_stage_init 0x81
426 01:41:18.321082 hw id: 0x0000 - pwm id 0x01
427 01:41:18.321563 bl2_stage_init 0xc1
428 01:41:18.326726 bl2_stage_init 0x02
429 01:41:18.327216
430 01:41:18.327609 L0:00000000
431 01:41:18.328025 L1:00000703
432 01:41:18.328416 L2:00008067
433 01:41:18.328795 L3:15000000
434 01:41:18.332262 S1:00000000
435 01:41:18.332675 B2:20282000
436 01:41:18.333057 B1:a0f83180
437 01:41:18.333436
438 01:41:18.333814 TE: 71086
439 01:41:18.334194
440 01:41:18.337886 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 01:41:18.338316
442 01:41:18.343465 Board ID = 1
443 01:41:18.343870 Set cpu clk to 24M
444 01:41:18.344290 Set clk81 to 24M
445 01:41:18.349083 Use GP1_pll as DSU clk.
446 01:41:18.349488 DSU clk: 1200 Mhz
447 01:41:18.349873 CPU clk: 1200 MHz
448 01:41:18.354682 Set clk81 to 166.6M
449 01:41:18.360263 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 01:41:18.360671 board id: 1
451 01:41:18.367461 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 01:41:18.378155 fw parse done
453 01:41:18.384093 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 01:41:18.426729 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 01:41:18.437712 PIEI prepare done
456 01:41:18.438120 fastboot data load
457 01:41:18.438502 fastboot data verify
458 01:41:18.443340 verify result: 266
459 01:41:18.448897 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 01:41:18.449320 LPDDR4 probe
461 01:41:18.449700 ddr clk to 1584MHz
462 01:41:18.456871 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 01:41:18.494093
464 01:41:18.494504 dmc_version 0001
465 01:41:18.500800 Check phy result
466 01:41:18.506729 INFO : End of CA training
467 01:41:18.507139 INFO : End of initialization
468 01:41:18.512349 INFO : Training has run successfully!
469 01:41:18.512763 Check phy result
470 01:41:18.517895 INFO : End of initialization
471 01:41:18.518336 INFO : End of read enable training
472 01:41:18.523520 INFO : End of fine write leveling
473 01:41:18.529129 INFO : End of Write leveling coarse delay
474 01:41:18.529562 INFO : Training has run successfully!
475 01:41:18.529962 Check phy result
476 01:41:18.534740 INFO : End of initialization
477 01:41:18.535179 INFO : End of read dq deskew training
478 01:41:18.540339 INFO : End of MPR read delay center optimization
479 01:41:18.545922 INFO : End of write delay center optimization
480 01:41:18.551563 INFO : End of read delay center optimization
481 01:41:18.552032 INFO : End of max read latency training
482 01:41:18.557104 INFO : Training has run successfully!
483 01:41:18.557527 1D training succeed
484 01:41:18.566308 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 01:41:18.613863 Check phy result
486 01:41:18.614310 INFO : End of initialization
487 01:41:18.636231 INFO : End of 2D read delay Voltage center optimization
488 01:41:18.655450 INFO : End of 2D read delay Voltage center optimization
489 01:41:18.707254 INFO : End of 2D write delay Voltage center optimization
490 01:41:18.756554 INFO : End of 2D write delay Voltage center optimization
491 01:41:18.762038 INFO : Training has run successfully!
492 01:41:18.762459
493 01:41:18.762859 channel==0
494 01:41:18.767642 RxClkDly_Margin_A0==88 ps 9
495 01:41:18.768105 TxDqDly_Margin_A0==88 ps 9
496 01:41:18.773239 RxClkDly_Margin_A1==88 ps 9
497 01:41:18.773658 TxDqDly_Margin_A1==98 ps 10
498 01:41:18.774059 TrainedVREFDQ_A0==74
499 01:41:18.778844 TrainedVREFDQ_A1==75
500 01:41:18.779266 VrefDac_Margin_A0==24
501 01:41:18.779661 DeviceVref_Margin_A0==40
502 01:41:18.784542 VrefDac_Margin_A1==23
503 01:41:18.784971 DeviceVref_Margin_A1==39
504 01:41:18.785375
505 01:41:18.785769
506 01:41:18.786160 channel==1
507 01:41:18.790048 RxClkDly_Margin_A0==78 ps 8
508 01:41:18.790469 TxDqDly_Margin_A0==88 ps 9
509 01:41:18.795648 RxClkDly_Margin_A1==78 ps 8
510 01:41:18.796105 TxDqDly_Margin_A1==88 ps 9
511 01:41:18.801240 TrainedVREFDQ_A0==75
512 01:41:18.801684 TrainedVREFDQ_A1==77
513 01:41:18.802086 VrefDac_Margin_A0==22
514 01:41:18.806840 DeviceVref_Margin_A0==39
515 01:41:18.807256 VrefDac_Margin_A1==22
516 01:41:18.807652 DeviceVref_Margin_A1==37
517 01:41:18.812504
518 01:41:18.812927 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 01:41:18.813330
520 01:41:18.846048 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
521 01:41:18.846502 2D training succeed
522 01:41:18.851658 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 01:41:18.857243 auto size-- 65535DDR cs0 size: 2048MB
524 01:41:18.857659 DDR cs1 size: 2048MB
525 01:41:18.862819 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 01:41:18.863235 cs0 DataBus test pass
527 01:41:18.868535 cs1 DataBus test pass
528 01:41:18.868955 cs0 AddrBus test pass
529 01:41:18.869349 cs1 AddrBus test pass
530 01:41:18.869741
531 01:41:18.874032 100bdlr_step_size ps== 478
532 01:41:18.874461 result report
533 01:41:18.879651 boot times 0Enable ddr reg access
534 01:41:18.884748 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 01:41:18.898607 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 01:41:19.553321 bl2z: ptr: 05129330, size: 00001e40
537 01:41:19.560991 0.0;M3 CHK:0;cm4_sp_mode 0
538 01:41:19.561438 MVN_1=0x00000000
539 01:41:19.561687 MVN_2=0x00000000
540 01:41:19.572484 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 01:41:19.572834 OPS=0x04
542 01:41:19.573053 ring efuse init
543 01:41:19.578161 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 01:41:19.578559 [0.017310 Inits done]
545 01:41:19.578889 secure task start!
546 01:41:19.585399 high task start!
547 01:41:19.585795 low task start!
548 01:41:19.586036 run into bl31
549 01:41:19.593918 NOTICE: BL31: v1.3(release):4fc40b1
550 01:41:19.601860 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 01:41:19.602145 NOTICE: BL31: G12A normal boot!
552 01:41:19.617235 NOTICE: BL31: BL33 decompress pass
553 01:41:19.622994 ERROR: Error initializing runtime service opteed_fast
554 01:41:21.010380 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 01:41:21.010984 bl2_stage_init 0x01
556 01:41:21.011405 bl2_stage_init 0x81
557 01:41:21.016026 hw id: 0x0000 - pwm id 0x01
558 01:41:21.016482 bl2_stage_init 0xc1
559 01:41:21.021431 bl2_stage_init 0x02
560 01:41:21.021880
561 01:41:21.022291 L0:00000000
562 01:41:21.022690 L1:00000703
563 01:41:21.023088 L2:00008067
564 01:41:21.023481 L3:15000000
565 01:41:21.027645 S1:00000000
566 01:41:21.028130 B2:20282000
567 01:41:21.028546 B1:a0f83180
568 01:41:21.028944
569 01:41:21.029337 TE: 66593
570 01:41:21.029730
571 01:41:21.033258 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 01:41:21.033696
573 01:41:21.038907 Board ID = 1
574 01:41:21.039340 Set cpu clk to 24M
575 01:41:21.039741 Set clk81 to 24M
576 01:41:21.042405 Use GP1_pll as DSU clk.
577 01:41:21.042840 DSU clk: 1200 Mhz
578 01:41:21.048054 CPU clk: 1200 MHz
579 01:41:21.048489 Set clk81 to 166.6M
580 01:41:21.053601 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 01:41:21.054038 board id: 1
582 01:41:21.059144 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 01:41:21.073030 fw parse done
584 01:41:21.078977 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 01:41:21.122131 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 01:41:21.133218 PIEI prepare done
587 01:41:21.133658 fastboot data load
588 01:41:21.134074 fastboot data verify
589 01:41:21.138834 verify result: 266
590 01:41:21.144397 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 01:41:21.144835 LPDDR4 probe
592 01:41:21.145242 ddr clk to 1584MHz
593 01:41:21.152380 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 01:41:21.190099
595 01:41:21.190555 dmc_version 0001
596 01:41:21.197152 Check phy result
597 01:41:21.203124 INFO : End of CA training
598 01:41:21.203552 INFO : End of initialization
599 01:41:21.208846 INFO : Training has run successfully!
600 01:41:21.209275 Check phy result
601 01:41:21.214303 INFO : End of initialization
602 01:41:21.214726 INFO : End of read enable training
603 01:41:21.219929 INFO : End of fine write leveling
604 01:41:21.225525 INFO : End of Write leveling coarse delay
605 01:41:21.225949 INFO : Training has run successfully!
606 01:41:21.226346 Check phy result
607 01:41:21.231098 INFO : End of initialization
608 01:41:21.231527 INFO : End of read dq deskew training
609 01:41:21.236720 INFO : End of MPR read delay center optimization
610 01:41:21.242334 INFO : End of write delay center optimization
611 01:41:21.248078 INFO : End of read delay center optimization
612 01:41:21.248509 INFO : End of max read latency training
613 01:41:21.253537 INFO : Training has run successfully!
614 01:41:21.253974 1D training succeed
615 01:41:21.262814 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 01:41:21.311132 Check phy result
617 01:41:21.311612 INFO : End of initialization
618 01:41:21.338377 INFO : End of 2D read delay Voltage center optimization
619 01:41:21.362541 INFO : End of 2D read delay Voltage center optimization
620 01:41:21.419285 INFO : End of 2D write delay Voltage center optimization
621 01:41:21.473224 INFO : End of 2D write delay Voltage center optimization
622 01:41:21.478900 INFO : Training has run successfully!
623 01:41:21.479321
624 01:41:21.479726 channel==0
625 01:41:21.484417 RxClkDly_Margin_A0==88 ps 9
626 01:41:21.484841 TxDqDly_Margin_A0==88 ps 9
627 01:41:21.487767 RxClkDly_Margin_A1==88 ps 9
628 01:41:21.488214 TxDqDly_Margin_A1==98 ps 10
629 01:41:21.493339 TrainedVREFDQ_A0==74
630 01:41:21.493772 TrainedVREFDQ_A1==75
631 01:41:21.494174 VrefDac_Margin_A0==24
632 01:41:21.498937 DeviceVref_Margin_A0==40
633 01:41:21.499364 VrefDac_Margin_A1==22
634 01:41:21.504535 DeviceVref_Margin_A1==39
635 01:41:21.504963
636 01:41:21.505363
637 01:41:21.505754 channel==1
638 01:41:21.506146 RxClkDly_Margin_A0==78 ps 8
639 01:41:21.510131 TxDqDly_Margin_A0==98 ps 10
640 01:41:21.510574 RxClkDly_Margin_A1==78 ps 8
641 01:41:21.515763 TxDqDly_Margin_A1==88 ps 9
642 01:41:21.516225 TrainedVREFDQ_A0==78
643 01:41:21.516633 TrainedVREFDQ_A1==75
644 01:41:21.521336 VrefDac_Margin_A0==22
645 01:41:21.521761 DeviceVref_Margin_A0==36
646 01:41:21.526930 VrefDac_Margin_A1==22
647 01:41:21.527352 DeviceVref_Margin_A1==39
648 01:41:21.527751
649 01:41:21.532537 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 01:41:21.532975
651 01:41:21.560531 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000015 00000015 00000016 00000018 00000019 00000017 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
652 01:41:21.566154 2D training succeed
653 01:41:21.571787 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 01:41:21.572252 auto size-- 65535DDR cs0 size: 2048MB
655 01:41:21.577348 DDR cs1 size: 2048MB
656 01:41:21.577776 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 01:41:21.582947 cs0 DataBus test pass
658 01:41:21.583388 cs1 DataBus test pass
659 01:41:21.583791 cs0 AddrBus test pass
660 01:41:21.588541 cs1 AddrBus test pass
661 01:41:21.588969
662 01:41:21.589372 100bdlr_step_size ps== 471
663 01:41:21.589778 result report
664 01:41:21.594149 boot times 0Enable ddr reg access
665 01:41:21.601612 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 01:41:21.615463 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 01:41:22.274975 bl2z: ptr: 05129330, size: 00001e40
668 01:41:22.281776 0.0;M3 CHK:0;cm4_sp_mode 0
669 01:41:22.282238 MVN_1=0x00000000
670 01:41:22.282640 MVN_2=0x00000000
671 01:41:22.293145 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 01:41:22.293601 OPS=0x04
673 01:41:22.294009 ring efuse init
674 01:41:22.296104 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 01:41:22.301791 [0.017354 Inits done]
676 01:41:22.302235 secure task start!
677 01:41:22.302639 high task start!
678 01:41:22.303030 low task start!
679 01:41:22.306113 run into bl31
680 01:41:22.314708 NOTICE: BL31: v1.3(release):4fc40b1
681 01:41:22.322506 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 01:41:22.322960 NOTICE: BL31: G12A normal boot!
683 01:41:22.338050 NOTICE: BL31: BL33 decompress pass
684 01:41:22.343746 ERROR: Error initializing runtime service opteed_fast
685 01:41:23.139353
686 01:41:23.139904
687 01:41:23.144579 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 01:41:23.145057
689 01:41:23.148082 Model: Libre Computer AML-S905D3-CC Solitude
690 01:41:23.295022 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 01:41:23.310517 DRAM: 2 GiB (effective 3.8 GiB)
692 01:41:23.411576 Core: 406 devices, 33 uclasses, devicetree: separate
693 01:41:23.417370 WDT: Not starting watchdog@f0d0
694 01:41:23.442379 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 01:41:23.454604 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 01:41:23.459626 ** Bad device specification mmc 0 **
697 01:41:23.469629 Card did not respond to voltage select! : -110
698 01:41:23.477256 ** Bad device specification mmc 0 **
699 01:41:23.477670 Couldn't find partition mmc 0
700 01:41:23.485564 Card did not respond to voltage select! : -110
701 01:41:23.491104 ** Bad device specification mmc 0 **
702 01:41:23.491521 Couldn't find partition mmc 0
703 01:41:23.496161 Error: could not access storage.
704 01:41:23.792609 Net: eth0: ethernet@ff3f0000
705 01:41:23.793188 starting USB...
706 01:41:24.037377 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 01:41:24.037884 Starting the controller
708 01:41:24.044264 USB XHCI 1.10
709 01:41:25.598760 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 01:41:25.607043 scanning usb for storage devices... 0 Storage Device(s) found
712 01:41:25.658516 Hit any key to stop autoboot: 1
713 01:41:25.659292 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 01:41:25.659880 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 01:41:25.660395 Setting prompt string to ['=>']
716 01:41:25.660873 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 01:41:25.673054 0
718 01:41:25.673937 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 01:41:25.775123 => setenv autoload no
721 01:41:25.775785 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 01:41:25.780608 setenv autoload no
724 01:41:25.882120 => setenv initrd_high 0xffffffff
725 01:41:25.882879 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 01:41:25.887469 setenv initrd_high 0xffffffff
728 01:41:25.989007 => setenv fdt_high 0xffffffff
729 01:41:25.990009 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 01:41:25.994300 setenv fdt_high 0xffffffff
732 01:41:26.095778 => dhcp
733 01:41:26.096702 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
734 01:41:26.100990 dhcp
735 01:41:27.056808 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
736 01:41:27.057370 Speed: 1000, full duplex
737 01:41:27.057783 BOOTP broadcast 1
738 01:41:27.066798 DHCP client bound to address 192.168.6.21 (9 ms)
740 01:41:27.168292 => setenv serverip 192.168.6.2
741 01:41:27.169252 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
742 01:41:27.173685 setenv serverip 192.168.6.2
744 01:41:27.275091 => tftpboot 0x01080000 973331/tftp-deploy-ub16foy5/kernel/uImage
745 01:41:27.276078 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
746 01:41:27.282542 tftpboot 0x01080000 973331/tftp-deploy-ub16foy5/kernel/uImage
747 01:41:27.283010 Speed: 1000, full duplex
748 01:41:27.283413 Using ethernet@ff3f0000 device
749 01:41:27.288075 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
750 01:41:27.293627 Filename '973331/tftp-deploy-ub16foy5/kernel/uImage'.
751 01:41:27.296913 Load address: 0x1080000
752 01:41:27.301953 Loading: * UDP wrong checksum 00000005 000070b8
753 01:41:35.085757 T ################################################## 43.6 MiB
754 01:41:35.086428 5.6 MiB/s
755 01:41:35.086895 done
756 01:41:35.090176 Bytes transferred = 45716032 (2b99240 hex)
758 01:41:35.191802 => tftpboot 0x08000000 973331/tftp-deploy-ub16foy5/ramdisk/ramdisk.cpio.gz.uboot
759 01:41:35.192857 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:31)
760 01:41:35.199678 tftpboot 0x08000000 973331/tftp-deploy-ub16foy5/ramdisk/ramdisk.cpio.gz.uboot
761 01:41:35.200281 Speed: 1000, full duplex
762 01:41:35.200739 Using ethernet@ff3f0000 device
763 01:41:35.205066 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
764 01:41:35.214839 Filename '973331/tftp-deploy-ub16foy5/ramdisk/ramdisk.cpio.gz.uboot'.
765 01:41:35.215392 Load address: 0x8000000
766 01:41:39.248616 Loading: *################################################# UDP wrong checksum 0000000f 0000c7e8
767 01:41:44.249348 T UDP wrong checksum 0000000f 0000c7e8
768 01:41:54.250463 T T UDP wrong checksum 0000000f 0000c7e8
769 01:42:14.255411 T T T T UDP wrong checksum 0000000f 0000c7e8
770 01:42:34.260169 T T T
771 01:42:34.260834 Retry count exceeded; starting again
773 01:42:34.262384 end: 2.4.3 bootloader-commands (duration 00:01:09) [common]
776 01:42:34.264489 end: 2.4 uboot-commands (duration 00:01:28) [common]
778 01:42:34.266004 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
780 01:42:34.267111 end: 2 uboot-action (duration 00:01:28) [common]
782 01:42:34.268799 Cleaning after the job
783 01:42:34.269380 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973331/tftp-deploy-ub16foy5/ramdisk
784 01:42:34.271795 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973331/tftp-deploy-ub16foy5/kernel
785 01:42:34.324298 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973331/tftp-deploy-ub16foy5/dtb
786 01:42:34.325527 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973331/tftp-deploy-ub16foy5/modules
787 01:42:34.347629 start: 4.1 power-off (timeout 00:00:30) [common]
788 01:42:34.348285 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
789 01:42:34.381129 >> OK - accepted request
790 01:42:34.383171 Returned 0 in 0 seconds
791 01:42:34.483945 end: 4.1 power-off (duration 00:00:00) [common]
793 01:42:34.484967 start: 4.2 read-feedback (timeout 00:10:00) [common]
794 01:42:34.485632 Listened to connection for namespace 'common' for up to 1s
795 01:42:35.486633 Finalising connection for namespace 'common'
796 01:42:35.487376 Disconnecting from shell: Finalise
797 01:42:35.487894 =>
798 01:42:35.589178 end: 4.2 read-feedback (duration 00:00:01) [common]
799 01:42:35.589874 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/973331
800 01:42:36.202306 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/973331
801 01:42:36.202918 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.