Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:44:46.310049 lava-dispatcher, installed at version: 2024.01
2 01:44:46.310824 start: 0 validate
3 01:44:46.311308 Start time: 2024-11-11 01:44:46.311279+00:00 (UTC)
4 01:44:46.311830 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:44:46.312409 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:44:46.356319 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:44:46.356981 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-415-g0e90fad093db9%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 01:44:46.385127 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:44:46.386054 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-415-g0e90fad093db9%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:44:46.413974 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:44:46.414486 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:44:46.445652 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 01:44:46.446372 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-415-g0e90fad093db9%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 01:44:46.483486 validate duration: 0.17
16 01:44:46.484394 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:44:46.484743 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:44:46.485074 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:44:46.485670 Not decompressing ramdisk as can be used compressed.
20 01:44:46.486137 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 01:44:46.486437 saving as /var/lib/lava/dispatcher/tmp/973310/tftp-deploy-qej_e1ie/ramdisk/initrd.cpio.gz
22 01:44:46.486715 total size: 5628140 (5 MB)
23 01:44:46.524756 progress 0 % (0 MB)
24 01:44:46.528976 progress 5 % (0 MB)
25 01:44:46.533392 progress 10 % (0 MB)
26 01:44:46.537247 progress 15 % (0 MB)
27 01:44:46.541517 progress 20 % (1 MB)
28 01:44:46.545345 progress 25 % (1 MB)
29 01:44:46.551227 progress 30 % (1 MB)
30 01:44:46.555672 progress 35 % (1 MB)
31 01:44:46.559471 progress 40 % (2 MB)
32 01:44:46.563635 progress 45 % (2 MB)
33 01:44:46.567440 progress 50 % (2 MB)
34 01:44:46.571637 progress 55 % (2 MB)
35 01:44:46.575832 progress 60 % (3 MB)
36 01:44:46.579630 progress 65 % (3 MB)
37 01:44:46.583792 progress 70 % (3 MB)
38 01:44:46.587498 progress 75 % (4 MB)
39 01:44:46.591560 progress 80 % (4 MB)
40 01:44:46.595263 progress 85 % (4 MB)
41 01:44:46.599343 progress 90 % (4 MB)
42 01:44:46.603311 progress 95 % (5 MB)
43 01:44:46.606693 progress 100 % (5 MB)
44 01:44:46.607341 5 MB downloaded in 0.12 s (44.50 MB/s)
45 01:44:46.607902 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:44:46.608842 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:44:46.609143 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:44:46.609420 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:44:46.609888 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-415-g0e90fad093db9/arm64/defconfig/gcc-12/kernel/Image
51 01:44:46.610139 saving as /var/lib/lava/dispatcher/tmp/973310/tftp-deploy-qej_e1ie/kernel/Image
52 01:44:46.610352 total size: 45715968 (43 MB)
53 01:44:46.610564 No compression specified
54 01:44:46.644052 progress 0 % (0 MB)
55 01:44:46.672877 progress 5 % (2 MB)
56 01:44:46.701899 progress 10 % (4 MB)
57 01:44:46.730769 progress 15 % (6 MB)
58 01:44:46.762058 progress 20 % (8 MB)
59 01:44:46.790779 progress 25 % (10 MB)
60 01:44:46.819924 progress 30 % (13 MB)
61 01:44:46.849608 progress 35 % (15 MB)
62 01:44:46.878867 progress 40 % (17 MB)
63 01:44:46.907869 progress 45 % (19 MB)
64 01:44:46.937199 progress 50 % (21 MB)
65 01:44:46.966868 progress 55 % (24 MB)
66 01:44:46.996272 progress 60 % (26 MB)
67 01:44:47.025286 progress 65 % (28 MB)
68 01:44:47.054714 progress 70 % (30 MB)
69 01:44:47.083882 progress 75 % (32 MB)
70 01:44:47.113527 progress 80 % (34 MB)
71 01:44:47.142269 progress 85 % (37 MB)
72 01:44:47.171597 progress 90 % (39 MB)
73 01:44:47.200684 progress 95 % (41 MB)
74 01:44:47.229435 progress 100 % (43 MB)
75 01:44:47.229997 43 MB downloaded in 0.62 s (70.36 MB/s)
76 01:44:47.230532 end: 1.2.1 http-download (duration 00:00:01) [common]
78 01:44:47.231429 end: 1.2 download-retry (duration 00:00:01) [common]
79 01:44:47.231745 start: 1.3 download-retry (timeout 00:09:59) [common]
80 01:44:47.232074 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 01:44:47.232583 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-415-g0e90fad093db9/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 01:44:47.232897 saving as /var/lib/lava/dispatcher/tmp/973310/tftp-deploy-qej_e1ie/dtb/meson-g12b-a311d-libretech-cc.dtb
83 01:44:47.233134 total size: 54703 (0 MB)
84 01:44:47.233368 No compression specified
85 01:44:47.266923 progress 59 % (0 MB)
86 01:44:47.267787 progress 100 % (0 MB)
87 01:44:47.268427 0 MB downloaded in 0.04 s (1.48 MB/s)
88 01:44:47.268957 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:44:47.269827 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:44:47.270118 start: 1.4 download-retry (timeout 00:09:59) [common]
92 01:44:47.270406 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 01:44:47.270878 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 01:44:47.271152 saving as /var/lib/lava/dispatcher/tmp/973310/tftp-deploy-qej_e1ie/nfsrootfs/full.rootfs.tar
95 01:44:47.271375 total size: 474398908 (452 MB)
96 01:44:47.271601 Using unxz to decompress xz
97 01:44:47.307267 progress 0 % (0 MB)
98 01:44:48.405238 progress 5 % (22 MB)
99 01:44:49.861047 progress 10 % (45 MB)
100 01:44:50.293356 progress 15 % (67 MB)
101 01:44:51.119597 progress 20 % (90 MB)
102 01:44:51.651556 progress 25 % (113 MB)
103 01:44:52.006327 progress 30 % (135 MB)
104 01:44:52.606183 progress 35 % (158 MB)
105 01:44:53.518942 progress 40 % (181 MB)
106 01:44:54.359750 progress 45 % (203 MB)
107 01:44:55.077903 progress 50 % (226 MB)
108 01:44:55.782253 progress 55 % (248 MB)
109 01:44:57.005345 progress 60 % (271 MB)
110 01:44:58.482875 progress 65 % (294 MB)
111 01:45:00.124032 progress 70 % (316 MB)
112 01:45:03.234155 progress 75 % (339 MB)
113 01:45:05.690704 progress 80 % (361 MB)
114 01:45:08.580846 progress 85 % (384 MB)
115 01:45:11.746020 progress 90 % (407 MB)
116 01:45:14.911357 progress 95 % (429 MB)
117 01:45:18.075867 progress 100 % (452 MB)
118 01:45:18.089810 452 MB downloaded in 30.82 s (14.68 MB/s)
119 01:45:18.090696 end: 1.4.1 http-download (duration 00:00:31) [common]
121 01:45:18.092375 end: 1.4 download-retry (duration 00:00:31) [common]
122 01:45:18.092911 start: 1.5 download-retry (timeout 00:09:28) [common]
123 01:45:18.093437 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 01:45:18.094922 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-415-g0e90fad093db9/arm64/defconfig/gcc-12/modules.tar.xz
125 01:45:18.095436 saving as /var/lib/lava/dispatcher/tmp/973310/tftp-deploy-qej_e1ie/modules/modules.tar
126 01:45:18.095866 total size: 11620588 (11 MB)
127 01:45:18.096346 Using unxz to decompress xz
128 01:45:18.140697 progress 0 % (0 MB)
129 01:45:18.209126 progress 5 % (0 MB)
130 01:45:18.284014 progress 10 % (1 MB)
131 01:45:18.383211 progress 15 % (1 MB)
132 01:45:18.476559 progress 20 % (2 MB)
133 01:45:18.558034 progress 25 % (2 MB)
134 01:45:18.634732 progress 30 % (3 MB)
135 01:45:18.714103 progress 35 % (3 MB)
136 01:45:18.786622 progress 40 % (4 MB)
137 01:45:18.861774 progress 45 % (5 MB)
138 01:45:18.947410 progress 50 % (5 MB)
139 01:45:19.031048 progress 55 % (6 MB)
140 01:45:19.112736 progress 60 % (6 MB)
141 01:45:19.193920 progress 65 % (7 MB)
142 01:45:19.275383 progress 70 % (7 MB)
143 01:45:19.353687 progress 75 % (8 MB)
144 01:45:19.437801 progress 80 % (8 MB)
145 01:45:19.519934 progress 85 % (9 MB)
146 01:45:19.603775 progress 90 % (10 MB)
147 01:45:19.677177 progress 95 % (10 MB)
148 01:45:19.753516 progress 100 % (11 MB)
149 01:45:19.767281 11 MB downloaded in 1.67 s (6.63 MB/s)
150 01:45:19.767881 end: 1.5.1 http-download (duration 00:00:02) [common]
152 01:45:19.769456 end: 1.5 download-retry (duration 00:00:02) [common]
153 01:45:19.769978 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 01:45:19.770493 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 01:45:35.158750 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/973310/extract-nfsrootfs-4km1l4_b
156 01:45:35.159366 end: 1.6.1 extract-nfsrootfs (duration 00:00:15) [common]
157 01:45:35.159655 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 01:45:35.160379 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z
159 01:45:35.160846 makedir: /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin
160 01:45:35.161170 makedir: /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/tests
161 01:45:35.161480 makedir: /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/results
162 01:45:35.161811 Creating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin/lava-add-keys
163 01:45:35.162332 Creating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin/lava-add-sources
164 01:45:35.162828 Creating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin/lava-background-process-start
165 01:45:35.163318 Creating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin/lava-background-process-stop
166 01:45:35.163840 Creating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin/lava-common-functions
167 01:45:35.164380 Creating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin/lava-echo-ipv4
168 01:45:35.164860 Creating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin/lava-install-packages
169 01:45:35.165341 Creating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin/lava-installed-packages
170 01:45:35.165809 Creating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin/lava-os-build
171 01:45:35.166273 Creating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin/lava-probe-channel
172 01:45:35.166739 Creating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin/lava-probe-ip
173 01:45:35.167277 Creating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin/lava-target-ip
174 01:45:35.167769 Creating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin/lava-target-mac
175 01:45:35.168288 Creating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin/lava-target-storage
176 01:45:35.168774 Creating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin/lava-test-case
177 01:45:35.169267 Creating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin/lava-test-event
178 01:45:35.169735 Creating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin/lava-test-feedback
179 01:45:35.170198 Creating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin/lava-test-raise
180 01:45:35.170663 Creating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin/lava-test-reference
181 01:45:35.171126 Creating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin/lava-test-runner
182 01:45:35.171633 Creating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin/lava-test-set
183 01:45:35.172163 Creating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin/lava-test-shell
184 01:45:35.172658 Updating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin/lava-install-packages (oe)
185 01:45:35.173184 Updating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/bin/lava-installed-packages (oe)
186 01:45:35.173620 Creating /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/environment
187 01:45:35.173980 LAVA metadata
188 01:45:35.174236 - LAVA_JOB_ID=973310
189 01:45:35.174450 - LAVA_DISPATCHER_IP=192.168.6.2
190 01:45:35.174795 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 01:45:35.175718 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 01:45:35.176044 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 01:45:35.176261 skipped lava-vland-overlay
194 01:45:35.176504 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 01:45:35.176757 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 01:45:35.176975 skipped lava-multinode-overlay
197 01:45:35.177219 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 01:45:35.177469 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 01:45:35.177717 Loading test definitions
200 01:45:35.177994 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 01:45:35.178213 Using /lava-973310 at stage 0
202 01:45:35.179347 uuid=973310_1.6.2.4.1 testdef=None
203 01:45:35.179649 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 01:45:35.179911 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 01:45:35.181637 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 01:45:35.182421 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 01:45:35.184579 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 01:45:35.185407 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 01:45:35.187434 runner path: /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/0/tests/0_v4l2-decoder-conformance-h264 test_uuid 973310_1.6.2.4.1
212 01:45:35.188036 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 01:45:35.188800 Creating lava-test-runner.conf files
215 01:45:35.189003 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/973310/lava-overlay-gfswax8z/lava-973310/0 for stage 0
216 01:45:35.189332 - 0_v4l2-decoder-conformance-h264
217 01:45:35.189673 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 01:45:35.189946 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 01:45:35.211105 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 01:45:35.211440 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 01:45:35.211697 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 01:45:35.211961 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 01:45:35.212289 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 01:45:35.857531 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 01:45:35.858007 start: 1.6.4 extract-modules (timeout 00:09:11) [common]
226 01:45:35.858259 extracting modules file /var/lib/lava/dispatcher/tmp/973310/tftp-deploy-qej_e1ie/modules/modules.tar to /var/lib/lava/dispatcher/tmp/973310/extract-nfsrootfs-4km1l4_b
227 01:45:37.206488 extracting modules file /var/lib/lava/dispatcher/tmp/973310/tftp-deploy-qej_e1ie/modules/modules.tar to /var/lib/lava/dispatcher/tmp/973310/extract-overlay-ramdisk-bo1p6ui7/ramdisk
228 01:45:38.585901 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 01:45:38.586384 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
230 01:45:38.586666 [common] Applying overlay to NFS
231 01:45:38.586882 [common] Applying overlay /var/lib/lava/dispatcher/tmp/973310/compress-overlay-99_qqeww/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/973310/extract-nfsrootfs-4km1l4_b
232 01:45:38.615746 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 01:45:38.616147 start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
234 01:45:38.616424 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
235 01:45:38.616652 Converting downloaded kernel to a uImage
236 01:45:38.616960 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/973310/tftp-deploy-qej_e1ie/kernel/Image /var/lib/lava/dispatcher/tmp/973310/tftp-deploy-qej_e1ie/kernel/uImage
237 01:45:39.092552 output: Image Name:
238 01:45:39.092979 output: Created: Mon Nov 11 01:45:38 2024
239 01:45:39.093191 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 01:45:39.093398 output: Data Size: 45715968 Bytes = 44644.50 KiB = 43.60 MiB
241 01:45:39.093601 output: Load Address: 01080000
242 01:45:39.093804 output: Entry Point: 01080000
243 01:45:39.094003 output:
244 01:45:39.094345 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 01:45:39.094615 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 01:45:39.094886 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 01:45:39.095142 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 01:45:39.095402 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 01:45:39.095658 Building ramdisk /var/lib/lava/dispatcher/tmp/973310/extract-overlay-ramdisk-bo1p6ui7/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/973310/extract-overlay-ramdisk-bo1p6ui7/ramdisk
250 01:45:41.217863 >> 166831 blocks
251 01:45:48.972479 Adding RAMdisk u-boot header.
252 01:45:48.972924 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/973310/extract-overlay-ramdisk-bo1p6ui7/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/973310/extract-overlay-ramdisk-bo1p6ui7/ramdisk.cpio.gz.uboot
253 01:45:49.226766 output: Image Name:
254 01:45:49.227184 output: Created: Mon Nov 11 01:45:48 2024
255 01:45:49.227400 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 01:45:49.227607 output: Data Size: 23435073 Bytes = 22885.81 KiB = 22.35 MiB
257 01:45:49.227810 output: Load Address: 00000000
258 01:45:49.228195 output: Entry Point: 00000000
259 01:45:49.228719 output:
260 01:45:49.229745 rename /var/lib/lava/dispatcher/tmp/973310/extract-overlay-ramdisk-bo1p6ui7/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/973310/tftp-deploy-qej_e1ie/ramdisk/ramdisk.cpio.gz.uboot
261 01:45:49.230470 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 01:45:49.231022 end: 1.6 prepare-tftp-overlay (duration 00:00:29) [common]
263 01:45:49.231554 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:57) [common]
264 01:45:49.232044 No LXC device requested
265 01:45:49.232562 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 01:45:49.233078 start: 1.8 deploy-device-env (timeout 00:08:57) [common]
267 01:45:49.233574 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 01:45:49.233988 Checking files for TFTP limit of 4294967296 bytes.
269 01:45:49.236673 end: 1 tftp-deploy (duration 00:01:03) [common]
270 01:45:49.237258 start: 2 uboot-action (timeout 00:05:00) [common]
271 01:45:49.237786 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 01:45:49.238280 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 01:45:49.238781 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 01:45:49.239308 Using kernel file from prepare-kernel: 973310/tftp-deploy-qej_e1ie/kernel/uImage
275 01:45:49.239940 substitutions:
276 01:45:49.240383 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 01:45:49.240785 - {DTB_ADDR}: 0x01070000
278 01:45:49.241184 - {DTB}: 973310/tftp-deploy-qej_e1ie/dtb/meson-g12b-a311d-libretech-cc.dtb
279 01:45:49.241581 - {INITRD}: 973310/tftp-deploy-qej_e1ie/ramdisk/ramdisk.cpio.gz.uboot
280 01:45:49.241981 - {KERNEL_ADDR}: 0x01080000
281 01:45:49.242373 - {KERNEL}: 973310/tftp-deploy-qej_e1ie/kernel/uImage
282 01:45:49.242766 - {LAVA_MAC}: None
283 01:45:49.243196 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/973310/extract-nfsrootfs-4km1l4_b
284 01:45:49.243593 - {NFS_SERVER_IP}: 192.168.6.2
285 01:45:49.244004 - {PRESEED_CONFIG}: None
286 01:45:49.244401 - {PRESEED_LOCAL}: None
287 01:45:49.244792 - {RAMDISK_ADDR}: 0x08000000
288 01:45:49.245177 - {RAMDISK}: 973310/tftp-deploy-qej_e1ie/ramdisk/ramdisk.cpio.gz.uboot
289 01:45:49.245564 - {ROOT_PART}: None
290 01:45:49.245954 - {ROOT}: None
291 01:45:49.246339 - {SERVER_IP}: 192.168.6.2
292 01:45:49.246728 - {TEE_ADDR}: 0x83000000
293 01:45:49.247114 - {TEE}: None
294 01:45:49.247500 Parsed boot commands:
295 01:45:49.247875 - setenv autoload no
296 01:45:49.248292 - setenv initrd_high 0xffffffff
297 01:45:49.248677 - setenv fdt_high 0xffffffff
298 01:45:49.249063 - dhcp
299 01:45:49.249447 - setenv serverip 192.168.6.2
300 01:45:49.249831 - tftpboot 0x01080000 973310/tftp-deploy-qej_e1ie/kernel/uImage
301 01:45:49.250217 - tftpboot 0x08000000 973310/tftp-deploy-qej_e1ie/ramdisk/ramdisk.cpio.gz.uboot
302 01:45:49.250600 - tftpboot 0x01070000 973310/tftp-deploy-qej_e1ie/dtb/meson-g12b-a311d-libretech-cc.dtb
303 01:45:49.250983 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/973310/extract-nfsrootfs-4km1l4_b,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 01:45:49.251383 - bootm 0x01080000 0x08000000 0x01070000
305 01:45:49.251874 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 01:45:49.253388 start: 2.3 connect-device (timeout 00:05:00) [common]
308 01:45:49.253805 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 01:45:49.268917 Setting prompt string to ['lava-test: # ']
310 01:45:49.270405 end: 2.3 connect-device (duration 00:00:00) [common]
311 01:45:49.271003 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 01:45:49.271545 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 01:45:49.272115 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 01:45:49.273262 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 01:45:49.308034 >> OK - accepted request
316 01:45:49.309796 Returned 0 in 0 seconds
317 01:45:49.410940 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 01:45:49.412685 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 01:45:49.413295 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 01:45:49.413829 Setting prompt string to ['Hit any key to stop autoboot']
322 01:45:49.414295 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 01:45:49.415883 Trying 192.168.56.21...
324 01:45:49.416432 Connected to conserv1.
325 01:45:49.416858 Escape character is '^]'.
326 01:45:49.417279
327 01:45:49.417694 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 01:45:49.418116
329 01:46:00.969929 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 01:46:00.970555 bl2_stage_init 0x01
331 01:46:00.970968 bl2_stage_init 0x81
332 01:46:00.975453 hw id: 0x0000 - pwm id 0x01
333 01:46:00.975909 bl2_stage_init 0xc1
334 01:46:00.976358 bl2_stage_init 0x02
335 01:46:00.976754
336 01:46:00.980860 L0:00000000
337 01:46:00.981302 L1:20000703
338 01:46:00.981695 L2:00008067
339 01:46:00.982083 L3:14000000
340 01:46:00.983963 B2:00402000
341 01:46:00.984437 B1:e0f83180
342 01:46:00.984832
343 01:46:00.985228 TE: 58167
344 01:46:00.985621
345 01:46:00.995017 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 01:46:00.995457
347 01:46:00.995853 Board ID = 1
348 01:46:00.996272 Set A53 clk to 24M
349 01:46:00.996659 Set A73 clk to 24M
350 01:46:01.000650 Set clk81 to 24M
351 01:46:01.001072 A53 clk: 1200 MHz
352 01:46:01.001463 A73 clk: 1200 MHz
353 01:46:01.006321 CLK81: 166.6M
354 01:46:01.006743 smccc: 00012abe
355 01:46:01.011899 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 01:46:01.012359 board id: 1
357 01:46:01.020665 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 01:46:01.031057 fw parse done
359 01:46:01.037012 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 01:46:01.079547 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 01:46:01.090454 PIEI prepare done
362 01:46:01.090931 fastboot data load
363 01:46:01.091335 fastboot data verify
364 01:46:01.096042 verify result: 266
365 01:46:01.101628 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 01:46:01.102065 LPDDR4 probe
367 01:46:01.102480 ddr clk to 1584MHz
368 01:46:01.114635 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 01:46:01.146988
370 01:46:01.147514 dmc_version 0001
371 01:46:01.153542 Check phy result
372 01:46:01.159398 INFO : End of CA training
373 01:46:01.159840 INFO : End of initialization
374 01:46:01.165012 INFO : Training has run successfully!
375 01:46:01.165768 Check phy result
376 01:46:01.170650 INFO : End of initialization
377 01:46:01.171141 INFO : End of read enable training
378 01:46:01.176191 INFO : End of fine write leveling
379 01:46:01.181799 INFO : End of Write leveling coarse delay
380 01:46:01.182234 INFO : Training has run successfully!
381 01:46:01.182640 Check phy result
382 01:46:01.187376 INFO : End of initialization
383 01:46:01.187801 INFO : End of read dq deskew training
384 01:46:01.193012 INFO : End of MPR read delay center optimization
385 01:46:01.198594 INFO : End of write delay center optimization
386 01:46:01.204215 INFO : End of read delay center optimization
387 01:46:01.204650 INFO : End of max read latency training
388 01:46:01.209809 INFO : Training has run successfully!
389 01:46:01.210237 1D training succeed
390 01:46:01.218998 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 01:46:01.266658 Check phy result
392 01:46:01.267211 INFO : End of initialization
393 01:46:01.288304 INFO : End of 2D read delay Voltage center optimization
394 01:46:01.308562 INFO : End of 2D read delay Voltage center optimization
395 01:46:01.360709 INFO : End of 2D write delay Voltage center optimization
396 01:46:01.410125 INFO : End of 2D write delay Voltage center optimization
397 01:46:01.415697 INFO : Training has run successfully!
398 01:46:01.416240
399 01:46:01.416682 channel==0
400 01:46:01.421194 RxClkDly_Margin_A0==88 ps 9
401 01:46:01.421662 TxDqDly_Margin_A0==98 ps 10
402 01:46:01.426751 RxClkDly_Margin_A1==88 ps 9
403 01:46:01.427175 TxDqDly_Margin_A1==98 ps 10
404 01:46:01.427586 TrainedVREFDQ_A0==74
405 01:46:01.432369 TrainedVREFDQ_A1==74
406 01:46:01.432959 VrefDac_Margin_A0==25
407 01:46:01.433446 DeviceVref_Margin_A0==40
408 01:46:01.438037 VrefDac_Margin_A1==25
409 01:46:01.438535 DeviceVref_Margin_A1==40
410 01:46:01.438931
411 01:46:01.439324
412 01:46:01.443715 channel==1
413 01:46:01.444225 RxClkDly_Margin_A0==98 ps 10
414 01:46:01.444626 TxDqDly_Margin_A0==98 ps 10
415 01:46:01.449241 RxClkDly_Margin_A1==98 ps 10
416 01:46:01.449669 TxDqDly_Margin_A1==88 ps 9
417 01:46:01.454772 TrainedVREFDQ_A0==77
418 01:46:01.455202 TrainedVREFDQ_A1==77
419 01:46:01.455601 VrefDac_Margin_A0==22
420 01:46:01.460390 DeviceVref_Margin_A0==37
421 01:46:01.460812 VrefDac_Margin_A1==22
422 01:46:01.465979 DeviceVref_Margin_A1==37
423 01:46:01.466398
424 01:46:01.466794 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 01:46:01.471548
426 01:46:01.499582 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
427 01:46:01.500119 2D training succeed
428 01:46:01.505286 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 01:46:01.510840 auto size-- 65535DDR cs0 size: 2048MB
430 01:46:01.511363 DDR cs1 size: 2048MB
431 01:46:01.516458 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 01:46:01.516920 cs0 DataBus test pass
433 01:46:01.521966 cs1 DataBus test pass
434 01:46:01.522424 cs0 AddrBus test pass
435 01:46:01.522821 cs1 AddrBus test pass
436 01:46:01.523214
437 01:46:01.527645 100bdlr_step_size ps== 420
438 01:46:01.528272 result report
439 01:46:01.533223 boot times 0Enable ddr reg access
440 01:46:01.538727 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 01:46:01.552105 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 01:46:02.125729 0.0;M3 CHK:0;cm4_sp_mode 0
443 01:46:02.126334 MVN_1=0x00000000
444 01:46:02.131181 MVN_2=0x00000000
445 01:46:02.136928 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 01:46:02.137364 OPS=0x10
447 01:46:02.137768 ring efuse init
448 01:46:02.138164 chipver efuse init
449 01:46:02.142548 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 01:46:02.148221 [0.018961 Inits done]
451 01:46:02.148670 secure task start!
452 01:46:02.149076 high task start!
453 01:46:02.152677 low task start!
454 01:46:02.153100 run into bl31
455 01:46:02.159464 NOTICE: BL31: v1.3(release):4fc40b1
456 01:46:02.167213 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 01:46:02.167658 NOTICE: BL31: G12A normal boot!
458 01:46:02.192616 NOTICE: BL31: BL33 decompress pass
459 01:46:02.198322 ERROR: Error initializing runtime service opteed_fast
460 01:46:03.431183
461 01:46:03.431802
462 01:46:03.439670 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 01:46:03.440250
464 01:46:03.440716 Model: Libre Computer AML-A311D-CC Alta
465 01:46:03.648156 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 01:46:03.671507 DRAM: 2 GiB (effective 3.8 GiB)
467 01:46:03.814658 Core: 408 devices, 31 uclasses, devicetree: separate
468 01:46:03.819376 WDT: Not starting watchdog@f0d0
469 01:46:03.852567 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 01:46:03.865051 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 01:46:03.870016 ** Bad device specification mmc 0 **
472 01:46:03.880510 Card did not respond to voltage select! : -110
473 01:46:03.887956 ** Bad device specification mmc 0 **
474 01:46:03.888659 Couldn't find partition mmc 0
475 01:46:03.896298 Card did not respond to voltage select! : -110
476 01:46:03.901766 ** Bad device specification mmc 0 **
477 01:46:03.902356 Couldn't find partition mmc 0
478 01:46:03.906814 Error: could not access storage.
479 01:46:05.170923 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 01:46:05.171599 bl2_stage_init 0x01
481 01:46:05.172161 bl2_stage_init 0x81
482 01:46:05.176356 hw id: 0x0000 - pwm id 0x01
483 01:46:05.176885 bl2_stage_init 0xc1
484 01:46:05.177357 bl2_stage_init 0x02
485 01:46:05.177818
486 01:46:05.181959 L0:00000000
487 01:46:05.182480 L1:20000703
488 01:46:05.182941 L2:00008067
489 01:46:05.183395 L3:14000000
490 01:46:05.184854 B2:00402000
491 01:46:05.185352 B1:e0f83180
492 01:46:05.185807
493 01:46:05.186258 TE: 58124
494 01:46:05.186706
495 01:46:05.196057 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 01:46:05.196565
497 01:46:05.197028 Board ID = 1
498 01:46:05.197475 Set A53 clk to 24M
499 01:46:05.197921 Set A73 clk to 24M
500 01:46:05.201646 Set clk81 to 24M
501 01:46:05.202144 A53 clk: 1200 MHz
502 01:46:05.202601 A73 clk: 1200 MHz
503 01:46:05.207255 CLK81: 166.6M
504 01:46:05.207752 smccc: 00012a92
505 01:46:05.212873 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 01:46:05.213370 board id: 1
507 01:46:05.221500 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 01:46:05.232090 fw parse done
509 01:46:05.238056 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 01:46:05.280688 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 01:46:05.291606 PIEI prepare done
512 01:46:05.292138 fastboot data load
513 01:46:05.292606 fastboot data verify
514 01:46:05.297470 verify result: 266
515 01:46:05.303003 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 01:46:05.303521 LPDDR4 probe
517 01:46:05.304020 ddr clk to 1584MHz
518 01:46:05.310944 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 01:46:05.348182
520 01:46:05.348720 dmc_version 0001
521 01:46:05.354818 Check phy result
522 01:46:05.360697 INFO : End of CA training
523 01:46:05.361210 INFO : End of initialization
524 01:46:05.366328 INFO : Training has run successfully!
525 01:46:05.366867 Check phy result
526 01:46:05.372110 INFO : End of initialization
527 01:46:05.372675 INFO : End of read enable training
528 01:46:05.377527 INFO : End of fine write leveling
529 01:46:05.383116 INFO : End of Write leveling coarse delay
530 01:46:05.383667 INFO : Training has run successfully!
531 01:46:05.384189 Check phy result
532 01:46:05.388693 INFO : End of initialization
533 01:46:05.389222 INFO : End of read dq deskew training
534 01:46:05.394293 INFO : End of MPR read delay center optimization
535 01:46:05.400019 INFO : End of write delay center optimization
536 01:46:05.405504 INFO : End of read delay center optimization
537 01:46:05.406025 INFO : End of max read latency training
538 01:46:05.411137 INFO : Training has run successfully!
539 01:46:05.411670 1D training succeed
540 01:46:05.420279 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 01:46:05.467920 Check phy result
542 01:46:05.468480 INFO : End of initialization
543 01:46:05.489613 INFO : End of 2D read delay Voltage center optimization
544 01:46:05.509293 INFO : End of 2D read delay Voltage center optimization
545 01:46:05.561163 INFO : End of 2D write delay Voltage center optimization
546 01:46:05.611289 INFO : End of 2D write delay Voltage center optimization
547 01:46:05.616919 INFO : Training has run successfully!
548 01:46:05.617435
549 01:46:05.617902 channel==0
550 01:46:05.622460 RxClkDly_Margin_A0==88 ps 9
551 01:46:05.623004 TxDqDly_Margin_A0==98 ps 10
552 01:46:05.625746 RxClkDly_Margin_A1==88 ps 9
553 01:46:05.626262 TxDqDly_Margin_A1==98 ps 10
554 01:46:05.631296 TrainedVREFDQ_A0==74
555 01:46:05.631823 TrainedVREFDQ_A1==74
556 01:46:05.636912 VrefDac_Margin_A0==25
557 01:46:05.637420 DeviceVref_Margin_A0==40
558 01:46:05.637882 VrefDac_Margin_A1==25
559 01:46:05.642453 DeviceVref_Margin_A1==40
560 01:46:05.642960
561 01:46:05.643427
562 01:46:05.643879 channel==1
563 01:46:05.644374 RxClkDly_Margin_A0==98 ps 10
564 01:46:05.648089 TxDqDly_Margin_A0==98 ps 10
565 01:46:05.648606 RxClkDly_Margin_A1==98 ps 10
566 01:46:05.653694 TxDqDly_Margin_A1==88 ps 9
567 01:46:05.654210 TrainedVREFDQ_A0==77
568 01:46:05.654672 TrainedVREFDQ_A1==77
569 01:46:05.659280 VrefDac_Margin_A0==22
570 01:46:05.659787 DeviceVref_Margin_A0==37
571 01:46:05.664931 VrefDac_Margin_A1==22
572 01:46:05.665449 DeviceVref_Margin_A1==37
573 01:46:05.665909
574 01:46:05.670496 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 01:46:05.671015
576 01:46:05.698461 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
577 01:46:05.704201 2D training succeed
578 01:46:05.709658 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 01:46:05.710183 auto size-- 65535DDR cs0 size: 2048MB
580 01:46:05.715266 DDR cs1 size: 2048MB
581 01:46:05.715773 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 01:46:05.720908 cs0 DataBus test pass
583 01:46:05.721417 cs1 DataBus test pass
584 01:46:05.721850 cs0 AddrBus test pass
585 01:46:05.726471 cs1 AddrBus test pass
586 01:46:05.726966
587 01:46:05.727399 100bdlr_step_size ps== 420
588 01:46:05.727836 result report
589 01:46:05.732094 boot times 0Enable ddr reg access
590 01:46:05.739884 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 01:46:05.753323 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 01:46:06.327101 0.0;M3 CHK:0;cm4_sp_mode 0
593 01:46:06.327742 MVN_1=0x00000000
594 01:46:06.332542 MVN_2=0x00000000
595 01:46:06.338386 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 01:46:06.338929 OPS=0x10
597 01:46:06.339403 ring efuse init
598 01:46:06.339832 chipver efuse init
599 01:46:06.344016 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 01:46:06.349610 [0.018961 Inits done]
601 01:46:06.350084 secure task start!
602 01:46:06.350486 high task start!
603 01:46:06.354145 low task start!
604 01:46:06.354618 run into bl31
605 01:46:06.360726 NOTICE: BL31: v1.3(release):4fc40b1
606 01:46:06.368661 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 01:46:06.369238 NOTICE: BL31: G12A normal boot!
608 01:46:06.393952 NOTICE: BL31: BL33 decompress pass
609 01:46:06.399621 ERROR: Error initializing runtime service opteed_fast
610 01:46:07.632414
611 01:46:07.632850
612 01:46:07.640860 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 01:46:07.641288
614 01:46:07.641625 Model: Libre Computer AML-A311D-CC Alta
615 01:46:07.849447 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 01:46:07.872935 DRAM: 2 GiB (effective 3.8 GiB)
617 01:46:08.015693 Core: 408 devices, 31 uclasses, devicetree: separate
618 01:46:08.021687 WDT: Not starting watchdog@f0d0
619 01:46:08.053854 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 01:46:08.066341 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 01:46:08.071385 ** Bad device specification mmc 0 **
622 01:46:08.081737 Card did not respond to voltage select! : -110
623 01:46:08.089402 ** Bad device specification mmc 0 **
624 01:46:08.089881 Couldn't find partition mmc 0
625 01:46:08.097582 Card did not respond to voltage select! : -110
626 01:46:08.103088 ** Bad device specification mmc 0 **
627 01:46:08.103561 Couldn't find partition mmc 0
628 01:46:08.108208 Error: could not access storage.
629 01:46:08.451686 Net: eth0: ethernet@ff3f0000
630 01:46:08.452139 starting USB...
631 01:46:08.703391 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 01:46:08.704011 Starting the controller
633 01:46:08.710460 USB XHCI 1.10
634 01:46:10.310278 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 01:46:10.310710 bl2_stage_init 0x01
636 01:46:10.310937 bl2_stage_init 0x81
637 01:46:10.315793 hw id: 0x0000 - pwm id 0x01
638 01:46:10.316090 bl2_stage_init 0xc1
639 01:46:10.316310 bl2_stage_init 0x02
640 01:46:10.316522
641 01:46:10.321372 L0:00000000
642 01:46:10.321642 L1:20000703
643 01:46:10.321860 L2:00008067
644 01:46:10.322069 L3:14000000
645 01:46:10.324345 B2:00402000
646 01:46:10.324606 B1:e0f83180
647 01:46:10.324820
648 01:46:10.325030 TE: 58167
649 01:46:10.325239
650 01:46:10.335501 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 01:46:10.336066
652 01:46:10.336497 Board ID = 1
653 01:46:10.336910 Set A53 clk to 24M
654 01:46:10.337317 Set A73 clk to 24M
655 01:46:10.341024 Set clk81 to 24M
656 01:46:10.341497 A53 clk: 1200 MHz
657 01:46:10.341910 A73 clk: 1200 MHz
658 01:46:10.346690 CLK81: 166.6M
659 01:46:10.347163 smccc: 00012abd
660 01:46:10.352285 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 01:46:10.352762 board id: 1
662 01:46:10.357819 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 01:46:10.371623 fw parse done
664 01:46:10.377670 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 01:46:10.420154 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 01:46:10.431003 PIEI prepare done
667 01:46:10.431500 fastboot data load
668 01:46:10.431923 fastboot data verify
669 01:46:10.436602 verify result: 266
670 01:46:10.442210 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 01:46:10.442689 LPDDR4 probe
672 01:46:10.443113 ddr clk to 1584MHz
673 01:46:10.450211 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 01:46:10.487487
675 01:46:10.488064 dmc_version 0001
676 01:46:10.494134 Check phy result
677 01:46:10.500044 INFO : End of CA training
678 01:46:10.500534 INFO : End of initialization
679 01:46:10.505633 INFO : Training has run successfully!
680 01:46:10.506116 Check phy result
681 01:46:10.511225 INFO : End of initialization
682 01:46:10.511729 INFO : End of read enable training
683 01:46:10.516860 INFO : End of fine write leveling
684 01:46:10.522438 INFO : End of Write leveling coarse delay
685 01:46:10.522918 INFO : Training has run successfully!
686 01:46:10.523336 Check phy result
687 01:46:10.528067 INFO : End of initialization
688 01:46:10.528550 INFO : End of read dq deskew training
689 01:46:10.533669 INFO : End of MPR read delay center optimization
690 01:46:10.539282 INFO : End of write delay center optimization
691 01:46:10.544848 INFO : End of read delay center optimization
692 01:46:10.545337 INFO : End of max read latency training
693 01:46:10.550456 INFO : Training has run successfully!
694 01:46:10.550939 1D training succeed
695 01:46:10.559594 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 01:46:10.607307 Check phy result
697 01:46:10.607891 INFO : End of initialization
698 01:46:10.628959 INFO : End of 2D read delay Voltage center optimization
699 01:46:10.649248 INFO : End of 2D read delay Voltage center optimization
700 01:46:10.701308 INFO : End of 2D write delay Voltage center optimization
701 01:46:10.750674 INFO : End of 2D write delay Voltage center optimization
702 01:46:10.756296 INFO : Training has run successfully!
703 01:46:10.756789
704 01:46:10.757209 channel==0
705 01:46:10.761912 RxClkDly_Margin_A0==88 ps 9
706 01:46:10.762407 TxDqDly_Margin_A0==98 ps 10
707 01:46:10.767486 RxClkDly_Margin_A1==88 ps 9
708 01:46:10.767961 TxDqDly_Margin_A1==98 ps 10
709 01:46:10.768434 TrainedVREFDQ_A0==74
710 01:46:10.773048 TrainedVREFDQ_A1==74
711 01:46:10.773521 VrefDac_Margin_A0==25
712 01:46:10.773934 DeviceVref_Margin_A0==40
713 01:46:10.778869 VrefDac_Margin_A1==25
714 01:46:10.779339 DeviceVref_Margin_A1==40
715 01:46:10.779748
716 01:46:10.780190
717 01:46:10.784278 channel==1
718 01:46:10.784740 RxClkDly_Margin_A0==98 ps 10
719 01:46:10.785223 TxDqDly_Margin_A0==98 ps 10
720 01:46:10.790004 RxClkDly_Margin_A1==88 ps 9
721 01:46:10.790477 TxDqDly_Margin_A1==88 ps 9
722 01:46:10.795413 TrainedVREFDQ_A0==77
723 01:46:10.795874 TrainedVREFDQ_A1==77
724 01:46:10.796328 VrefDac_Margin_A0==22
725 01:46:10.801048 DeviceVref_Margin_A0==37
726 01:46:10.801503 VrefDac_Margin_A1==24
727 01:46:10.806636 DeviceVref_Margin_A1==37
728 01:46:10.807092
729 01:46:10.807500 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 01:46:10.807899
731 01:46:10.840103 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
732 01:46:10.840631 2D training succeed
733 01:46:10.845762 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 01:46:10.851329 auto size-- 65535DDR cs0 size: 2048MB
735 01:46:10.851799 DDR cs1 size: 2048MB
736 01:46:10.856935 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 01:46:10.857396 cs0 DataBus test pass
738 01:46:10.862537 cs1 DataBus test pass
739 01:46:10.862994 cs0 AddrBus test pass
740 01:46:10.863405 cs1 AddrBus test pass
741 01:46:10.863808
742 01:46:10.868127 100bdlr_step_size ps== 420
743 01:46:10.868600 result report
744 01:46:10.873757 boot times 0Enable ddr reg access
745 01:46:10.879082 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 01:46:10.892528 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 01:46:11.465639 0.0;M3 CHK:0;cm4_sp_mode 0
748 01:46:11.466302 MVN_1=0x00000000
749 01:46:11.471104 MVN_2=0x00000000
750 01:46:11.476872 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 01:46:11.477358 OPS=0x10
752 01:46:11.477764 ring efuse init
753 01:46:11.478159 chipver efuse init
754 01:46:11.482380 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 01:46:11.488027 [0.018961 Inits done]
756 01:46:11.488500 secure task start!
757 01:46:11.488899 high task start!
758 01:46:11.492653 low task start!
759 01:46:11.493152 run into bl31
760 01:46:11.499285 NOTICE: BL31: v1.3(release):4fc40b1
761 01:46:11.507099 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 01:46:11.507577 NOTICE: BL31: G12A normal boot!
763 01:46:11.532480 NOTICE: BL31: BL33 decompress pass
764 01:46:11.538152 ERROR: Error initializing runtime service opteed_fast
765 01:46:12.771064
766 01:46:12.771715
767 01:46:12.779446 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 01:46:12.779954
769 01:46:12.780443 Model: Libre Computer AML-A311D-CC Alta
770 01:46:12.987967 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 01:46:13.011315 DRAM: 2 GiB (effective 3.8 GiB)
772 01:46:13.154304 Core: 408 devices, 31 uclasses, devicetree: separate
773 01:46:13.160181 WDT: Not starting watchdog@f0d0
774 01:46:13.192387 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 01:46:13.204905 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 01:46:13.209842 ** Bad device specification mmc 0 **
777 01:46:13.220183 Card did not respond to voltage select! : -110
778 01:46:13.227825 ** Bad device specification mmc 0 **
779 01:46:13.228343 Couldn't find partition mmc 0
780 01:46:13.236185 Card did not respond to voltage select! : -110
781 01:46:13.241686 ** Bad device specification mmc 0 **
782 01:46:13.242158 Couldn't find partition mmc 0
783 01:46:13.246750 Error: could not access storage.
784 01:46:13.590237 Net: eth0: ethernet@ff3f0000
785 01:46:13.590828 starting USB...
786 01:46:13.842224 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 01:46:13.842825 Starting the controller
788 01:46:13.849056 USB XHCI 1.10
789 01:46:16.010511 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 01:46:16.010931 bl2_stage_init 0x01
791 01:46:16.011153 bl2_stage_init 0x81
792 01:46:16.015910 hw id: 0x0000 - pwm id 0x01
793 01:46:16.016377 bl2_stage_init 0xc1
794 01:46:16.016709 bl2_stage_init 0x02
795 01:46:16.017026
796 01:46:16.021614 L0:00000000
797 01:46:16.022050 L1:20000703
798 01:46:16.022300 L2:00008067
799 01:46:16.022511 L3:14000000
800 01:46:16.024470 B2:00402000
801 01:46:16.024865 B1:e0f83180
802 01:46:16.025184
803 01:46:16.025507 TE: 58124
804 01:46:16.025820
805 01:46:16.035500 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 01:46:16.035796
807 01:46:16.036040 Board ID = 1
808 01:46:16.036434 Set A53 clk to 24M
809 01:46:16.036850 Set A73 clk to 24M
810 01:46:16.041187 Set clk81 to 24M
811 01:46:16.041674 A53 clk: 1200 MHz
812 01:46:16.042110 A73 clk: 1200 MHz
813 01:46:16.046774 CLK81: 166.6M
814 01:46:16.047241 smccc: 00012a92
815 01:46:16.052362 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 01:46:16.052834 board id: 1
817 01:46:16.060981 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 01:46:16.071644 fw parse done
819 01:46:16.077622 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 01:46:16.120226 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 01:46:16.131118 PIEI prepare done
822 01:46:16.131599 fastboot data load
823 01:46:16.132076 fastboot data verify
824 01:46:16.136813 verify result: 266
825 01:46:16.142424 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 01:46:16.142889 LPDDR4 probe
827 01:46:16.143305 ddr clk to 1584MHz
828 01:46:16.150379 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 01:46:16.187656
830 01:46:16.188179 dmc_version 0001
831 01:46:16.194276 Check phy result
832 01:46:16.200120 INFO : End of CA training
833 01:46:16.200592 INFO : End of initialization
834 01:46:16.205725 INFO : Training has run successfully!
835 01:46:16.206199 Check phy result
836 01:46:16.211442 INFO : End of initialization
837 01:46:16.211934 INFO : End of read enable training
838 01:46:16.216968 INFO : End of fine write leveling
839 01:46:16.222548 INFO : End of Write leveling coarse delay
840 01:46:16.223014 INFO : Training has run successfully!
841 01:46:16.223430 Check phy result
842 01:46:16.228189 INFO : End of initialization
843 01:46:16.228650 INFO : End of read dq deskew training
844 01:46:16.233736 INFO : End of MPR read delay center optimization
845 01:46:16.239417 INFO : End of write delay center optimization
846 01:46:16.244911 INFO : End of read delay center optimization
847 01:46:16.245380 INFO : End of max read latency training
848 01:46:16.250556 INFO : Training has run successfully!
849 01:46:16.251014 1D training succeed
850 01:46:16.259671 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 01:46:16.306355 Check phy result
852 01:46:16.306870 INFO : End of initialization
853 01:46:16.329111 INFO : End of 2D read delay Voltage center optimization
854 01:46:16.349363 INFO : End of 2D read delay Voltage center optimization
855 01:46:16.401388 INFO : End of 2D write delay Voltage center optimization
856 01:46:16.450812 INFO : End of 2D write delay Voltage center optimization
857 01:46:16.456328 INFO : Training has run successfully!
858 01:46:16.456815
859 01:46:16.457251 channel==0
860 01:46:16.461908 RxClkDly_Margin_A0==88 ps 9
861 01:46:16.462385 TxDqDly_Margin_A0==98 ps 10
862 01:46:16.465277 RxClkDly_Margin_A1==88 ps 9
863 01:46:16.465767 TxDqDly_Margin_A1==98 ps 10
864 01:46:16.470754 TrainedVREFDQ_A0==74
865 01:46:16.471233 TrainedVREFDQ_A1==74
866 01:46:16.471658 VrefDac_Margin_A0==25
867 01:46:16.476488 DeviceVref_Margin_A0==40
868 01:46:16.476982 VrefDac_Margin_A1==23
869 01:46:16.482036 DeviceVref_Margin_A1==40
870 01:46:16.482517
871 01:46:16.482915
872 01:46:16.483304 channel==1
873 01:46:16.483689 RxClkDly_Margin_A0==98 ps 10
874 01:46:16.487664 TxDqDly_Margin_A0==98 ps 10
875 01:46:16.488189 RxClkDly_Margin_A1==98 ps 10
876 01:46:16.493226 TxDqDly_Margin_A1==88 ps 9
877 01:46:16.493699 TrainedVREFDQ_A0==77
878 01:46:16.494095 TrainedVREFDQ_A1==77
879 01:46:16.498807 VrefDac_Margin_A0==22
880 01:46:16.499276 DeviceVref_Margin_A0==37
881 01:46:16.504425 VrefDac_Margin_A1==24
882 01:46:16.504895 DeviceVref_Margin_A1==37
883 01:46:16.505288
884 01:46:16.510044 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 01:46:16.510506
886 01:46:16.537999 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
887 01:46:16.543685 2D training succeed
888 01:46:16.549142 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 01:46:16.549624 auto size-- 65535DDR cs0 size: 2048MB
890 01:46:16.554735 DDR cs1 size: 2048MB
891 01:46:16.555208 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 01:46:16.560341 cs0 DataBus test pass
893 01:46:16.560806 cs1 DataBus test pass
894 01:46:16.561199 cs0 AddrBus test pass
895 01:46:16.565950 cs1 AddrBus test pass
896 01:46:16.566430
897 01:46:16.566824 100bdlr_step_size ps== 420
898 01:46:16.567222 result report
899 01:46:16.571556 boot times 0Enable ddr reg access
900 01:46:16.579226 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 01:46:16.592694 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 01:46:17.166476 0.0;M3 CHK:0;cm4_sp_mode 0
903 01:46:17.167141 MVN_1=0x00000000
904 01:46:17.171919 MVN_2=0x00000000
905 01:46:17.177715 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 01:46:17.178242 OPS=0x10
907 01:46:17.178698 ring efuse init
908 01:46:17.179153 chipver efuse init
909 01:46:17.185999 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 01:46:17.186522 [0.018961 Inits done]
911 01:46:17.186950 secure task start!
912 01:46:17.193429 high task start!
913 01:46:17.193960 low task start!
914 01:46:17.194390 run into bl31
915 01:46:17.200064 NOTICE: BL31: v1.3(release):4fc40b1
916 01:46:17.207883 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 01:46:17.208431 NOTICE: BL31: G12A normal boot!
918 01:46:17.233754 NOTICE: BL31: BL33 decompress pass
919 01:46:17.239537 ERROR: Error initializing runtime service opteed_fast
920 01:46:18.472268
921 01:46:18.472900
922 01:46:18.480697 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 01:46:18.481215
924 01:46:18.481654 Model: Libre Computer AML-A311D-CC Alta
925 01:46:18.689093 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 01:46:18.712485 DRAM: 2 GiB (effective 3.8 GiB)
927 01:46:18.855507 Core: 408 devices, 31 uclasses, devicetree: separate
928 01:46:18.861362 WDT: Not starting watchdog@f0d0
929 01:46:18.893588 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 01:46:18.906019 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 01:46:18.911031 ** Bad device specification mmc 0 **
932 01:46:18.921375 Card did not respond to voltage select! : -110
933 01:46:18.929077 ** Bad device specification mmc 0 **
934 01:46:18.929610 Couldn't find partition mmc 0
935 01:46:18.937378 Card did not respond to voltage select! : -110
936 01:46:18.942871 ** Bad device specification mmc 0 **
937 01:46:18.943364 Couldn't find partition mmc 0
938 01:46:18.947919 Error: could not access storage.
939 01:46:19.290393 Net: eth0: ethernet@ff3f0000
940 01:46:19.291000 starting USB...
941 01:46:19.542278 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 01:46:19.542913 Starting the controller
943 01:46:19.549219 USB XHCI 1.10
944 01:46:21.409917 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 01:46:21.410543 bl2_stage_init 0x01
946 01:46:21.410977 bl2_stage_init 0x81
947 01:46:21.415530 hw id: 0x0000 - pwm id 0x01
948 01:46:21.416086 bl2_stage_init 0xc1
949 01:46:21.416519 bl2_stage_init 0x02
950 01:46:21.416931
951 01:46:21.421105 L0:00000000
952 01:46:21.421592 L1:20000703
953 01:46:21.422010 L2:00008067
954 01:46:21.422417 L3:14000000
955 01:46:21.424048 B2:00402000
956 01:46:21.424534 B1:e0f83180
957 01:46:21.424950
958 01:46:21.425360 TE: 58124
959 01:46:21.425770
960 01:46:21.435197 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 01:46:21.435736
962 01:46:21.436202 Board ID = 1
963 01:46:21.436620 Set A53 clk to 24M
964 01:46:21.437024 Set A73 clk to 24M
965 01:46:21.440804 Set clk81 to 24M
966 01:46:21.441288 A53 clk: 1200 MHz
967 01:46:21.441702 A73 clk: 1200 MHz
968 01:46:21.446374 CLK81: 166.6M
969 01:46:21.446852 smccc: 00012a91
970 01:46:21.452007 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 01:46:21.452510 board id: 1
972 01:46:21.460561 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 01:46:21.471240 fw parse done
974 01:46:21.477264 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 01:46:21.519835 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 01:46:21.530724 PIEI prepare done
977 01:46:21.531217 fastboot data load
978 01:46:21.531618 fastboot data verify
979 01:46:21.536494 verify result: 266
980 01:46:21.542044 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 01:46:21.542533 LPDDR4 probe
982 01:46:21.542926 ddr clk to 1584MHz
983 01:46:21.550100 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 01:46:21.587616
985 01:46:21.588183 dmc_version 0001
986 01:46:21.594149 Check phy result
987 01:46:21.599883 INFO : End of CA training
988 01:46:21.600392 INFO : End of initialization
989 01:46:21.605482 INFO : Training has run successfully!
990 01:46:21.605804 Check phy result
991 01:46:21.611184 INFO : End of initialization
992 01:46:21.611509 INFO : End of read enable training
993 01:46:21.614470 INFO : End of fine write leveling
994 01:46:21.620612 INFO : End of Write leveling coarse delay
995 01:46:21.625519 INFO : Training has run successfully!
996 01:46:21.625830 Check phy result
997 01:46:21.626069 INFO : End of initialization
998 01:46:21.631291 INFO : End of read dq deskew training
999 01:46:21.634785 INFO : End of MPR read delay center optimization
1000 01:46:21.640391 INFO : End of write delay center optimization
1001 01:46:21.645804 INFO : End of read delay center optimization
1002 01:46:21.646112 INFO : End of max read latency training
1003 01:46:21.651410 INFO : Training has run successfully!
1004 01:46:21.651730 1D training succeed
1005 01:46:21.659383 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 01:46:21.707055 Check phy result
1007 01:46:21.707660 INFO : End of initialization
1008 01:46:21.728668 INFO : End of 2D read delay Voltage center optimization
1009 01:46:21.748795 INFO : End of 2D read delay Voltage center optimization
1010 01:46:21.800953 INFO : End of 2D write delay Voltage center optimization
1011 01:46:21.849879 INFO : End of 2D write delay Voltage center optimization
1012 01:46:21.855450 INFO : Training has run successfully!
1013 01:46:21.855920
1014 01:46:21.856396 channel==0
1015 01:46:21.861163 RxClkDly_Margin_A0==88 ps 9
1016 01:46:21.861635 TxDqDly_Margin_A0==98 ps 10
1017 01:46:21.864364 RxClkDly_Margin_A1==88 ps 9
1018 01:46:21.864828 TxDqDly_Margin_A1==98 ps 10
1019 01:46:21.870032 TrainedVREFDQ_A0==74
1020 01:46:21.870536 TrainedVREFDQ_A1==75
1021 01:46:21.870967 VrefDac_Margin_A0==25
1022 01:46:21.875659 DeviceVref_Margin_A0==40
1023 01:46:21.876199 VrefDac_Margin_A1==25
1024 01:46:21.881238 DeviceVref_Margin_A1==39
1025 01:46:21.881712
1026 01:46:21.882130
1027 01:46:21.882539 channel==1
1028 01:46:21.882941 RxClkDly_Margin_A0==98 ps 10
1029 01:46:21.884591 TxDqDly_Margin_A0==88 ps 9
1030 01:46:21.890214 RxClkDly_Margin_A1==88 ps 9
1031 01:46:21.890679 TxDqDly_Margin_A1==88 ps 9
1032 01:46:21.891098 TrainedVREFDQ_A0==76
1033 01:46:21.895689 TrainedVREFDQ_A1==77
1034 01:46:21.896190 VrefDac_Margin_A0==22
1035 01:46:21.901361 DeviceVref_Margin_A0==38
1036 01:46:21.901822 VrefDac_Margin_A1==24
1037 01:46:21.902238 DeviceVref_Margin_A1==37
1038 01:46:21.902639
1039 01:46:21.910453 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 01:46:21.910941
1041 01:46:21.938356 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1042 01:46:21.938917 2D training succeed
1043 01:46:21.944006 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 01:46:21.949662 auto size-- 65535DDR cs0 size: 2048MB
1045 01:46:21.950132 DDR cs1 size: 2048MB
1046 01:46:21.955235 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 01:46:21.955701 cs0 DataBus test pass
1048 01:46:21.960746 cs1 DataBus test pass
1049 01:46:21.961241 cs0 AddrBus test pass
1050 01:46:21.966322 cs1 AddrBus test pass
1051 01:46:21.966790
1052 01:46:21.967204 100bdlr_step_size ps== 420
1053 01:46:21.967616 result report
1054 01:46:21.971892 boot times 0Enable ddr reg access
1055 01:46:21.978325 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 01:46:21.991720 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 01:46:22.563706 0.0;M3 CHK:0;cm4_sp_mode 0
1058 01:46:22.564332 MVN_1=0x00000000
1059 01:46:22.569299 MVN_2=0x00000000
1060 01:46:22.575013 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 01:46:22.575550 OPS=0x10
1062 01:46:22.575973 ring efuse init
1063 01:46:22.576423 chipver efuse init
1064 01:46:22.580536 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 01:46:22.586149 [0.018960 Inits done]
1066 01:46:22.586633 secure task start!
1067 01:46:22.587052 high task start!
1068 01:46:22.590702 low task start!
1069 01:46:22.591191 run into bl31
1070 01:46:22.597381 NOTICE: BL31: v1.3(release):4fc40b1
1071 01:46:22.605258 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 01:46:22.605757 NOTICE: BL31: G12A normal boot!
1073 01:46:22.630548 NOTICE: BL31: BL33 decompress pass
1074 01:46:22.636220 ERROR: Error initializing runtime service opteed_fast
1075 01:46:23.869082
1076 01:46:23.869716
1077 01:46:23.877542 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 01:46:23.878033
1079 01:46:23.878461 Model: Libre Computer AML-A311D-CC Alta
1080 01:46:24.085935 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 01:46:24.109304 DRAM: 2 GiB (effective 3.8 GiB)
1082 01:46:24.252316 Core: 408 devices, 31 uclasses, devicetree: separate
1083 01:46:24.258088 WDT: Not starting watchdog@f0d0
1084 01:46:24.290373 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 01:46:24.302771 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 01:46:24.307849 ** Bad device specification mmc 0 **
1087 01:46:24.318119 Card did not respond to voltage select! : -110
1088 01:46:24.325774 ** Bad device specification mmc 0 **
1089 01:46:24.326258 Couldn't find partition mmc 0
1090 01:46:24.334120 Card did not respond to voltage select! : -110
1091 01:46:24.339610 ** Bad device specification mmc 0 **
1092 01:46:24.340108 Couldn't find partition mmc 0
1093 01:46:24.344710 Error: could not access storage.
1094 01:46:24.687127 Net: eth0: ethernet@ff3f0000
1095 01:46:24.687717 starting USB...
1096 01:46:24.938961 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 01:46:24.939515 Starting the controller
1098 01:46:24.945913 USB XHCI 1.10
1099 01:46:26.502275 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 01:46:26.510526 scanning usb for storage devices... 0 Storage Device(s) found
1102 01:46:26.562072 Hit any key to stop autoboot: 1
1103 01:46:26.562860 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 01:46:26.563592 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 01:46:26.564102 Setting prompt string to ['=>']
1106 01:46:26.564587 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 01:46:26.578044 0
1108 01:46:26.578986 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 01:46:26.579470 Sending with 10 millisecond of delay
1111 01:46:27.714114 => setenv autoload no
1112 01:46:27.724950 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1113 01:46:27.730152 setenv autoload no
1114 01:46:27.730987 Sending with 10 millisecond of delay
1116 01:46:29.528702 => setenv initrd_high 0xffffffff
1117 01:46:29.539738 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 01:46:29.540965 setenv initrd_high 0xffffffff
1119 01:46:29.541876 Sending with 10 millisecond of delay
1121 01:46:31.159500 => setenv fdt_high 0xffffffff
1122 01:46:31.170497 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 01:46:31.171537 setenv fdt_high 0xffffffff
1124 01:46:31.172450 Sending with 10 millisecond of delay
1126 01:46:31.464581 => dhcp
1127 01:46:31.475564 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 01:46:31.476698 dhcp
1129 01:46:31.477284 Speed: 1000, full duplex
1130 01:46:31.477867 BOOTP broadcast 1
1131 01:46:31.483909 DHCP client bound to address 192.168.6.27 (9 ms)
1132 01:46:31.484782 Sending with 10 millisecond of delay
1134 01:46:33.162607 => setenv serverip 192.168.6.2
1135 01:46:33.173670 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1136 01:46:33.174826 setenv serverip 192.168.6.2
1137 01:46:33.175724 Sending with 10 millisecond of delay
1139 01:46:36.899333 => tftpboot 0x01080000 973310/tftp-deploy-qej_e1ie/kernel/uImage
1140 01:46:36.910170 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1141 01:46:36.911044 tftpboot 0x01080000 973310/tftp-deploy-qej_e1ie/kernel/uImage
1142 01:46:36.911493 Speed: 1000, full duplex
1143 01:46:36.911921 Using ethernet@ff3f0000 device
1144 01:46:36.913062 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1145 01:46:36.918561 Filename '973310/tftp-deploy-qej_e1ie/kernel/uImage'.
1146 01:46:36.922606 Load address: 0x1080000
1147 01:46:39.904271 Loading: *################################################## 43.6 MiB
1148 01:46:39.904889 14.6 MiB/s
1149 01:46:39.905301 done
1150 01:46:39.907770 Bytes transferred = 45716032 (2b99240 hex)
1151 01:46:39.908571 Sending with 10 millisecond of delay
1153 01:46:44.596315 => tftpboot 0x08000000 973310/tftp-deploy-qej_e1ie/ramdisk/ramdisk.cpio.gz.uboot
1154 01:46:44.607171 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1155 01:46:44.608118 tftpboot 0x08000000 973310/tftp-deploy-qej_e1ie/ramdisk/ramdisk.cpio.gz.uboot
1156 01:46:44.608612 Speed: 1000, full duplex
1157 01:46:44.609071 Using ethernet@ff3f0000 device
1158 01:46:44.609973 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1159 01:46:44.618558 Filename '973310/tftp-deploy-qej_e1ie/ramdisk/ramdisk.cpio.gz.uboot'.
1160 01:46:44.619129 Load address: 0x8000000
1161 01:46:51.609770 Loading: *#############T #################################### UDP wrong checksum 00000005 00001ad6
1162 01:46:56.611282 T UDP wrong checksum 00000005 00001ad6
1163 01:47:06.613197 T T UDP wrong checksum 00000005 00001ad6
1164 01:47:26.618219 T T T T UDP wrong checksum 00000005 00001ad6
1165 01:47:41.622145 T T
1166 01:47:41.622827 Retry count exceeded; starting again
1168 01:47:41.624451 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1171 01:47:41.626583 end: 2.4 uboot-commands (duration 00:01:52) [common]
1173 01:47:41.628286 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1175 01:47:41.629441 end: 2 uboot-action (duration 00:01:52) [common]
1177 01:47:41.631104 Cleaning after the job
1178 01:47:41.631701 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973310/tftp-deploy-qej_e1ie/ramdisk
1179 01:47:41.633265 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973310/tftp-deploy-qej_e1ie/kernel
1180 01:47:41.682543 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973310/tftp-deploy-qej_e1ie/dtb
1181 01:47:41.683354 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973310/tftp-deploy-qej_e1ie/nfsrootfs
1182 01:47:42.001233 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973310/tftp-deploy-qej_e1ie/modules
1183 01:47:42.023580 start: 4.1 power-off (timeout 00:00:30) [common]
1184 01:47:42.024306 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1185 01:47:42.055900 >> OK - accepted request
1186 01:47:42.057805 Returned 0 in 0 seconds
1187 01:47:42.158574 end: 4.1 power-off (duration 00:00:00) [common]
1189 01:47:42.159659 start: 4.2 read-feedback (timeout 00:10:00) [common]
1190 01:47:42.160383 Listened to connection for namespace 'common' for up to 1s
1191 01:47:43.161281 Finalising connection for namespace 'common'
1192 01:47:43.161770 Disconnecting from shell: Finalise
1193 01:47:43.162038 =>
1194 01:47:43.262987 end: 4.2 read-feedback (duration 00:00:01) [common]
1195 01:47:43.263459 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/973310
1196 01:47:45.813260 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/973310
1197 01:47:45.813858 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.