Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:48:26.434294 lava-dispatcher, installed at version: 2024.01
2 01:48:26.435086 start: 0 validate
3 01:48:26.435598 Start time: 2024-11-11 01:48:26.435567+00:00 (UTC)
4 01:48:26.436166 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:48:26.436719 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:48:26.475919 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:48:26.476691 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-415-g0e90fad093db9%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 01:48:26.506803 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:48:26.507475 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-415-g0e90fad093db9%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:48:26.536982 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:48:26.537529 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:48:26.566176 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 01:48:26.566728 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-415-g0e90fad093db9%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 01:48:26.602522 validate duration: 0.17
16 01:48:26.603392 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:48:26.603720 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:48:26.604057 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:48:26.604647 Not decompressing ramdisk as can be used compressed.
20 01:48:26.605099 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 01:48:26.605388 saving as /var/lib/lava/dispatcher/tmp/973315/tftp-deploy-eaofl1o7/ramdisk/initrd.cpio.gz
22 01:48:26.605663 total size: 5628140 (5 MB)
23 01:48:26.638978 progress 0 % (0 MB)
24 01:48:26.642894 progress 5 % (0 MB)
25 01:48:26.646909 progress 10 % (0 MB)
26 01:48:26.650512 progress 15 % (0 MB)
27 01:48:26.654502 progress 20 % (1 MB)
28 01:48:26.658099 progress 25 % (1 MB)
29 01:48:26.662057 progress 30 % (1 MB)
30 01:48:26.666190 progress 35 % (1 MB)
31 01:48:26.669764 progress 40 % (2 MB)
32 01:48:26.673712 progress 45 % (2 MB)
33 01:48:26.677289 progress 50 % (2 MB)
34 01:48:26.681168 progress 55 % (2 MB)
35 01:48:26.685115 progress 60 % (3 MB)
36 01:48:26.688690 progress 65 % (3 MB)
37 01:48:26.692759 progress 70 % (3 MB)
38 01:48:26.696356 progress 75 % (4 MB)
39 01:48:26.700271 progress 80 % (4 MB)
40 01:48:26.703785 progress 85 % (4 MB)
41 01:48:26.707672 progress 90 % (4 MB)
42 01:48:26.711497 progress 95 % (5 MB)
43 01:48:26.714769 progress 100 % (5 MB)
44 01:48:26.715421 5 MB downloaded in 0.11 s (48.91 MB/s)
45 01:48:26.716007 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:48:26.716954 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:48:26.717276 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:48:26.717567 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:48:26.718057 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-415-g0e90fad093db9/arm64/defconfig/gcc-12/kernel/Image
51 01:48:26.718313 saving as /var/lib/lava/dispatcher/tmp/973315/tftp-deploy-eaofl1o7/kernel/Image
52 01:48:26.718534 total size: 45715968 (43 MB)
53 01:48:26.718755 No compression specified
54 01:48:26.751821 progress 0 % (0 MB)
55 01:48:26.780134 progress 5 % (2 MB)
56 01:48:26.808091 progress 10 % (4 MB)
57 01:48:26.835806 progress 15 % (6 MB)
58 01:48:26.863668 progress 20 % (8 MB)
59 01:48:26.891224 progress 25 % (10 MB)
60 01:48:26.919128 progress 30 % (13 MB)
61 01:48:26.947060 progress 35 % (15 MB)
62 01:48:26.974884 progress 40 % (17 MB)
63 01:48:27.004485 progress 45 % (19 MB)
64 01:48:27.032650 progress 50 % (21 MB)
65 01:48:27.060692 progress 55 % (24 MB)
66 01:48:27.088677 progress 60 % (26 MB)
67 01:48:27.116071 progress 65 % (28 MB)
68 01:48:27.143858 progress 70 % (30 MB)
69 01:48:27.171699 progress 75 % (32 MB)
70 01:48:27.199587 progress 80 % (34 MB)
71 01:48:27.227364 progress 85 % (37 MB)
72 01:48:27.255290 progress 90 % (39 MB)
73 01:48:27.283171 progress 95 % (41 MB)
74 01:48:27.310625 progress 100 % (43 MB)
75 01:48:27.311187 43 MB downloaded in 0.59 s (73.57 MB/s)
76 01:48:27.311699 end: 1.2.1 http-download (duration 00:00:01) [common]
78 01:48:27.312595 end: 1.2 download-retry (duration 00:00:01) [common]
79 01:48:27.312899 start: 1.3 download-retry (timeout 00:09:59) [common]
80 01:48:27.313183 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 01:48:27.313674 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-415-g0e90fad093db9/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 01:48:27.313967 saving as /var/lib/lava/dispatcher/tmp/973315/tftp-deploy-eaofl1o7/dtb/meson-g12b-a311d-libretech-cc.dtb
83 01:48:27.314191 total size: 54703 (0 MB)
84 01:48:27.314412 No compression specified
85 01:48:27.356691 progress 59 % (0 MB)
86 01:48:27.357546 progress 100 % (0 MB)
87 01:48:27.358129 0 MB downloaded in 0.04 s (1.19 MB/s)
88 01:48:27.358642 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:48:27.359482 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:48:27.359758 start: 1.4 download-retry (timeout 00:09:59) [common]
92 01:48:27.360055 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 01:48:27.360530 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 01:48:27.360791 saving as /var/lib/lava/dispatcher/tmp/973315/tftp-deploy-eaofl1o7/nfsrootfs/full.rootfs.tar
95 01:48:27.361007 total size: 474398908 (452 MB)
96 01:48:27.361225 Using unxz to decompress xz
97 01:48:27.406953 progress 0 % (0 MB)
98 01:48:28.509612 progress 5 % (22 MB)
99 01:48:29.964623 progress 10 % (45 MB)
100 01:48:30.406681 progress 15 % (67 MB)
101 01:48:31.184191 progress 20 % (90 MB)
102 01:48:31.711433 progress 25 % (113 MB)
103 01:48:32.085607 progress 30 % (135 MB)
104 01:48:32.685107 progress 35 % (158 MB)
105 01:48:33.586172 progress 40 % (181 MB)
106 01:48:34.464552 progress 45 % (203 MB)
107 01:48:35.036594 progress 50 % (226 MB)
108 01:48:35.674732 progress 55 % (248 MB)
109 01:48:36.888705 progress 60 % (271 MB)
110 01:48:38.345019 progress 65 % (294 MB)
111 01:48:39.952245 progress 70 % (316 MB)
112 01:48:43.146140 progress 75 % (339 MB)
113 01:48:45.667127 progress 80 % (361 MB)
114 01:48:48.575376 progress 85 % (384 MB)
115 01:48:52.002794 progress 90 % (407 MB)
116 01:48:55.200678 progress 95 % (429 MB)
117 01:48:58.384883 progress 100 % (452 MB)
118 01:48:58.397965 452 MB downloaded in 31.04 s (14.58 MB/s)
119 01:48:58.398555 end: 1.4.1 http-download (duration 00:00:31) [common]
121 01:48:58.399369 end: 1.4 download-retry (duration 00:00:31) [common]
122 01:48:58.399632 start: 1.5 download-retry (timeout 00:09:28) [common]
123 01:48:58.399891 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 01:48:58.400702 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-415-g0e90fad093db9/arm64/defconfig/gcc-12/modules.tar.xz
125 01:48:58.401178 saving as /var/lib/lava/dispatcher/tmp/973315/tftp-deploy-eaofl1o7/modules/modules.tar
126 01:48:58.401578 total size: 11620588 (11 MB)
127 01:48:58.401990 Using unxz to decompress xz
128 01:48:58.445366 progress 0 % (0 MB)
129 01:48:58.512118 progress 5 % (0 MB)
130 01:48:58.588167 progress 10 % (1 MB)
131 01:48:58.683773 progress 15 % (1 MB)
132 01:48:58.776103 progress 20 % (2 MB)
133 01:48:58.856246 progress 25 % (2 MB)
134 01:48:58.932264 progress 30 % (3 MB)
135 01:48:59.011442 progress 35 % (3 MB)
136 01:48:59.084710 progress 40 % (4 MB)
137 01:48:59.160834 progress 45 % (5 MB)
138 01:48:59.245937 progress 50 % (5 MB)
139 01:48:59.332946 progress 55 % (6 MB)
140 01:48:59.416507 progress 60 % (6 MB)
141 01:48:59.500346 progress 65 % (7 MB)
142 01:48:59.582130 progress 70 % (7 MB)
143 01:48:59.660984 progress 75 % (8 MB)
144 01:48:59.744954 progress 80 % (8 MB)
145 01:48:59.825404 progress 85 % (9 MB)
146 01:48:59.908854 progress 90 % (10 MB)
147 01:48:59.982424 progress 95 % (10 MB)
148 01:49:00.059411 progress 100 % (11 MB)
149 01:49:00.072350 11 MB downloaded in 1.67 s (6.63 MB/s)
150 01:49:00.072947 end: 1.5.1 http-download (duration 00:00:02) [common]
152 01:49:00.073767 end: 1.5 download-retry (duration 00:00:02) [common]
153 01:49:00.074033 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 01:49:00.074297 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 01:49:15.615192 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/973315/extract-nfsrootfs-wualqlh2
156 01:49:15.615811 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 01:49:15.616138 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 01:49:15.616901 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q
159 01:49:15.617395 makedir: /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin
160 01:49:15.617833 makedir: /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/tests
161 01:49:15.618282 makedir: /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/results
162 01:49:15.618658 Creating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin/lava-add-keys
163 01:49:15.619247 Creating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin/lava-add-sources
164 01:49:15.619803 Creating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin/lava-background-process-start
165 01:49:15.620395 Creating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin/lava-background-process-stop
166 01:49:15.620986 Creating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin/lava-common-functions
167 01:49:15.621523 Creating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin/lava-echo-ipv4
168 01:49:15.622051 Creating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin/lava-install-packages
169 01:49:15.622591 Creating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin/lava-installed-packages
170 01:49:15.623134 Creating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin/lava-os-build
171 01:49:15.623688 Creating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin/lava-probe-channel
172 01:49:15.624298 Creating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin/lava-probe-ip
173 01:49:15.625001 Creating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin/lava-target-ip
174 01:49:15.625574 Creating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin/lava-target-mac
175 01:49:15.626132 Creating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin/lava-target-storage
176 01:49:15.626706 Creating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin/lava-test-case
177 01:49:15.627282 Creating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin/lava-test-event
178 01:49:15.627938 Creating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin/lava-test-feedback
179 01:49:15.628774 Creating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin/lava-test-raise
180 01:49:15.629400 Creating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin/lava-test-reference
181 01:49:15.630102 Creating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin/lava-test-runner
182 01:49:15.630749 Creating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin/lava-test-set
183 01:49:15.631496 Creating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin/lava-test-shell
184 01:49:15.632207 Updating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin/lava-install-packages (oe)
185 01:49:15.632873 Updating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/bin/lava-installed-packages (oe)
186 01:49:15.633361 Creating /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/environment
187 01:49:15.633759 LAVA metadata
188 01:49:15.634054 - LAVA_JOB_ID=973315
189 01:49:15.634276 - LAVA_DISPATCHER_IP=192.168.6.2
190 01:49:15.634671 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 01:49:15.635724 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 01:49:15.636086 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 01:49:15.636307 skipped lava-vland-overlay
194 01:49:15.636551 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 01:49:15.636806 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 01:49:15.637028 skipped lava-multinode-overlay
197 01:49:15.637269 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 01:49:15.637520 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 01:49:15.637777 Loading test definitions
200 01:49:15.638067 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 01:49:15.638291 Using /lava-973315 at stage 0
202 01:49:15.639616 uuid=973315_1.6.2.4.1 testdef=None
203 01:49:15.639974 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 01:49:15.640300 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 01:49:15.642160 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 01:49:15.642972 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 01:49:15.645357 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 01:49:15.646239 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 01:49:15.648509 runner path: /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/0/tests/0_v4l2-decoder-conformance-h265 test_uuid 973315_1.6.2.4.1
212 01:49:15.649157 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 01:49:15.649928 Creating lava-test-runner.conf files
215 01:49:15.650131 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/973315/lava-overlay-7a67ha1q/lava-973315/0 for stage 0
216 01:49:15.650645 - 0_v4l2-decoder-conformance-h265
217 01:49:15.651071 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 01:49:15.651352 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 01:49:15.675763 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 01:49:15.676250 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 01:49:15.676519 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 01:49:15.676788 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 01:49:15.677051 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 01:49:16.305664 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 01:49:16.306137 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 01:49:16.306381 extracting modules file /var/lib/lava/dispatcher/tmp/973315/tftp-deploy-eaofl1o7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/973315/extract-nfsrootfs-wualqlh2
227 01:49:17.675608 extracting modules file /var/lib/lava/dispatcher/tmp/973315/tftp-deploy-eaofl1o7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/973315/extract-overlay-ramdisk-b9cacr2m/ramdisk
228 01:49:19.086587 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 01:49:19.087070 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
230 01:49:19.087348 [common] Applying overlay to NFS
231 01:49:19.087563 [common] Applying overlay /var/lib/lava/dispatcher/tmp/973315/compress-overlay-kdh63kmr/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/973315/extract-nfsrootfs-wualqlh2
232 01:49:19.116500 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 01:49:19.116863 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 01:49:19.117138 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 01:49:19.117364 Converting downloaded kernel to a uImage
236 01:49:19.117666 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/973315/tftp-deploy-eaofl1o7/kernel/Image /var/lib/lava/dispatcher/tmp/973315/tftp-deploy-eaofl1o7/kernel/uImage
237 01:49:19.594538 output: Image Name:
238 01:49:19.594960 output: Created: Mon Nov 11 01:49:19 2024
239 01:49:19.595169 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 01:49:19.595372 output: Data Size: 45715968 Bytes = 44644.50 KiB = 43.60 MiB
241 01:49:19.595573 output: Load Address: 01080000
242 01:49:19.595774 output: Entry Point: 01080000
243 01:49:19.595970 output:
244 01:49:19.596353 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 01:49:19.596620 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 01:49:19.596888 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 01:49:19.597138 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 01:49:19.597393 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 01:49:19.597656 Building ramdisk /var/lib/lava/dispatcher/tmp/973315/extract-overlay-ramdisk-b9cacr2m/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/973315/extract-overlay-ramdisk-b9cacr2m/ramdisk
250 01:49:21.752323 >> 166831 blocks
251 01:49:29.581954 Adding RAMdisk u-boot header.
252 01:49:29.582394 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/973315/extract-overlay-ramdisk-b9cacr2m/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/973315/extract-overlay-ramdisk-b9cacr2m/ramdisk.cpio.gz.uboot
253 01:49:29.886350 output: Image Name:
254 01:49:29.886773 output: Created: Mon Nov 11 01:49:29 2024
255 01:49:29.886990 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 01:49:29.887197 output: Data Size: 23435849 Bytes = 22886.57 KiB = 22.35 MiB
257 01:49:29.887399 output: Load Address: 00000000
258 01:49:29.887599 output: Entry Point: 00000000
259 01:49:29.887796 output:
260 01:49:29.888584 rename /var/lib/lava/dispatcher/tmp/973315/extract-overlay-ramdisk-b9cacr2m/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/973315/tftp-deploy-eaofl1o7/ramdisk/ramdisk.cpio.gz.uboot
261 01:49:29.889306 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 01:49:29.889846 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 01:49:29.890369 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:57) [common]
264 01:49:29.890823 No LXC device requested
265 01:49:29.891320 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 01:49:29.891827 start: 1.8 deploy-device-env (timeout 00:08:57) [common]
267 01:49:29.892362 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 01:49:29.892775 Checking files for TFTP limit of 4294967296 bytes.
269 01:49:29.895404 end: 1 tftp-deploy (duration 00:01:03) [common]
270 01:49:29.895968 start: 2 uboot-action (timeout 00:05:00) [common]
271 01:49:29.896525 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 01:49:29.897016 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 01:49:29.897512 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 01:49:29.898032 Using kernel file from prepare-kernel: 973315/tftp-deploy-eaofl1o7/kernel/uImage
275 01:49:29.898649 substitutions:
276 01:49:29.899053 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 01:49:29.899449 - {DTB_ADDR}: 0x01070000
278 01:49:29.899844 - {DTB}: 973315/tftp-deploy-eaofl1o7/dtb/meson-g12b-a311d-libretech-cc.dtb
279 01:49:29.900268 - {INITRD}: 973315/tftp-deploy-eaofl1o7/ramdisk/ramdisk.cpio.gz.uboot
280 01:49:29.900663 - {KERNEL_ADDR}: 0x01080000
281 01:49:29.901050 - {KERNEL}: 973315/tftp-deploy-eaofl1o7/kernel/uImage
282 01:49:29.901441 - {LAVA_MAC}: None
283 01:49:29.901866 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/973315/extract-nfsrootfs-wualqlh2
284 01:49:29.902258 - {NFS_SERVER_IP}: 192.168.6.2
285 01:49:29.902644 - {PRESEED_CONFIG}: None
286 01:49:29.903030 - {PRESEED_LOCAL}: None
287 01:49:29.903418 - {RAMDISK_ADDR}: 0x08000000
288 01:49:29.903799 - {RAMDISK}: 973315/tftp-deploy-eaofl1o7/ramdisk/ramdisk.cpio.gz.uboot
289 01:49:29.904216 - {ROOT_PART}: None
290 01:49:29.904604 - {ROOT}: None
291 01:49:29.904990 - {SERVER_IP}: 192.168.6.2
292 01:49:29.905380 - {TEE_ADDR}: 0x83000000
293 01:49:29.905763 - {TEE}: None
294 01:49:29.906144 Parsed boot commands:
295 01:49:29.906518 - setenv autoload no
296 01:49:29.906899 - setenv initrd_high 0xffffffff
297 01:49:29.907278 - setenv fdt_high 0xffffffff
298 01:49:29.907657 - dhcp
299 01:49:29.908062 - setenv serverip 192.168.6.2
300 01:49:29.908446 - tftpboot 0x01080000 973315/tftp-deploy-eaofl1o7/kernel/uImage
301 01:49:29.908830 - tftpboot 0x08000000 973315/tftp-deploy-eaofl1o7/ramdisk/ramdisk.cpio.gz.uboot
302 01:49:29.909212 - tftpboot 0x01070000 973315/tftp-deploy-eaofl1o7/dtb/meson-g12b-a311d-libretech-cc.dtb
303 01:49:29.909594 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/973315/extract-nfsrootfs-wualqlh2,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 01:49:29.909988 - bootm 0x01080000 0x08000000 0x01070000
305 01:49:29.910473 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 01:49:29.911938 start: 2.3 connect-device (timeout 00:05:00) [common]
308 01:49:29.912377 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 01:49:29.926933 Setting prompt string to ['lava-test: # ']
310 01:49:29.928448 end: 2.3 connect-device (duration 00:00:00) [common]
311 01:49:29.929034 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 01:49:29.929563 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 01:49:29.930082 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 01:49:29.931198 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 01:49:29.968515 >> OK - accepted request
316 01:49:29.970633 Returned 0 in 0 seconds
317 01:49:30.071696 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 01:49:30.073294 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 01:49:30.073866 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 01:49:30.074375 Setting prompt string to ['Hit any key to stop autoboot']
322 01:49:30.074828 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 01:49:30.076373 Trying 192.168.56.21...
324 01:49:30.076857 Connected to conserv1.
325 01:49:30.077268 Escape character is '^]'.
326 01:49:30.077680
327 01:49:30.078090 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 01:49:30.078500
329 01:49:41.160878 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 01:49:41.161504 bl2_stage_init 0x01
331 01:49:41.161932 bl2_stage_init 0x81
332 01:49:41.166442 hw id: 0x0000 - pwm id 0x01
333 01:49:41.166944 bl2_stage_init 0xc1
334 01:49:41.167341 bl2_stage_init 0x02
335 01:49:41.167729
336 01:49:41.172020 L0:00000000
337 01:49:41.172469 L1:20000703
338 01:49:41.172859 L2:00008067
339 01:49:41.173245 L3:14000000
340 01:49:41.174898 B2:00402000
341 01:49:41.175329 B1:e0f83180
342 01:49:41.175715
343 01:49:41.176142 TE: 58124
344 01:49:41.176533
345 01:49:41.186051 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 01:49:41.186484
347 01:49:41.186880 Board ID = 1
348 01:49:41.187262 Set A53 clk to 24M
349 01:49:41.187644 Set A73 clk to 24M
350 01:49:41.191737 Set clk81 to 24M
351 01:49:41.192174 A53 clk: 1200 MHz
352 01:49:41.192560 A73 clk: 1200 MHz
353 01:49:41.197218 CLK81: 166.6M
354 01:49:41.197659 smccc: 00012a92
355 01:49:41.202819 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 01:49:41.203230 board id: 1
357 01:49:41.211480 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 01:49:41.222020 fw parse done
359 01:49:41.228050 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 01:49:41.270613 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 01:49:41.281498 PIEI prepare done
362 01:49:41.281916 fastboot data load
363 01:49:41.282306 fastboot data verify
364 01:49:41.287174 verify result: 266
365 01:49:41.292735 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 01:49:41.293159 LPDDR4 probe
367 01:49:41.293547 ddr clk to 1584MHz
368 01:49:41.300850 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 01:49:41.338013
370 01:49:41.338469 dmc_version 0001
371 01:49:41.344680 Check phy result
372 01:49:41.350547 INFO : End of CA training
373 01:49:41.350966 INFO : End of initialization
374 01:49:41.356171 INFO : Training has run successfully!
375 01:49:41.356592 Check phy result
376 01:49:41.361740 INFO : End of initialization
377 01:49:41.362161 INFO : End of read enable training
378 01:49:41.367336 INFO : End of fine write leveling
379 01:49:41.373165 INFO : End of Write leveling coarse delay
380 01:49:41.373589 INFO : Training has run successfully!
381 01:49:41.373978 Check phy result
382 01:49:41.378641 INFO : End of initialization
383 01:49:41.379059 INFO : End of read dq deskew training
384 01:49:41.384342 INFO : End of MPR read delay center optimization
385 01:49:41.389886 INFO : End of write delay center optimization
386 01:49:41.395396 INFO : End of read delay center optimization
387 01:49:41.395811 INFO : End of max read latency training
388 01:49:41.401034 INFO : Training has run successfully!
389 01:49:41.401533 1D training succeed
390 01:49:41.410386 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 01:49:41.457906 Check phy result
392 01:49:41.458359 INFO : End of initialization
393 01:49:41.479554 INFO : End of 2D read delay Voltage center optimization
394 01:49:41.499926 INFO : End of 2D read delay Voltage center optimization
395 01:49:41.551998 INFO : End of 2D write delay Voltage center optimization
396 01:49:41.601344 INFO : End of 2D write delay Voltage center optimization
397 01:49:41.606889 INFO : Training has run successfully!
398 01:49:41.607308
399 01:49:41.607715 channel==0
400 01:49:41.612475 RxClkDly_Margin_A0==88 ps 9
401 01:49:41.612895 TxDqDly_Margin_A0==98 ps 10
402 01:49:41.618057 RxClkDly_Margin_A1==88 ps 9
403 01:49:41.618488 TxDqDly_Margin_A1==98 ps 10
404 01:49:41.618884 TrainedVREFDQ_A0==74
405 01:49:41.623679 TrainedVREFDQ_A1==75
406 01:49:41.624128 VrefDac_Margin_A0==25
407 01:49:41.624525 DeviceVref_Margin_A0==40
408 01:49:41.629271 VrefDac_Margin_A1==25
409 01:49:41.629683 DeviceVref_Margin_A1==39
410 01:49:41.630068
411 01:49:41.630453
412 01:49:41.634870 channel==1
413 01:49:41.635292 RxClkDly_Margin_A0==98 ps 10
414 01:49:41.635683 TxDqDly_Margin_A0==88 ps 9
415 01:49:41.640434 RxClkDly_Margin_A1==98 ps 10
416 01:49:41.640856 TxDqDly_Margin_A1==88 ps 9
417 01:49:41.646029 TrainedVREFDQ_A0==76
418 01:49:41.646448 TrainedVREFDQ_A1==77
419 01:49:41.646839 VrefDac_Margin_A0==22
420 01:49:41.651636 DeviceVref_Margin_A0==38
421 01:49:41.652083 VrefDac_Margin_A1==22
422 01:49:41.657268 DeviceVref_Margin_A1==37
423 01:49:41.657685
424 01:49:41.658077 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 01:49:41.658462
426 01:49:41.690960 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 01:49:41.691484 2D training succeed
428 01:49:41.698509 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 01:49:41.701426 auto size-- 65535DDR cs0 size: 2048MB
430 01:49:41.701846 DDR cs1 size: 2048MB
431 01:49:41.706999 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 01:49:41.707418 cs0 DataBus test pass
433 01:49:41.712600 cs1 DataBus test pass
434 01:49:41.713021 cs0 AddrBus test pass
435 01:49:41.713408 cs1 AddrBus test pass
436 01:49:41.713791
437 01:49:41.718192 100bdlr_step_size ps== 420
438 01:49:41.718617 result report
439 01:49:41.723793 boot times 0Enable ddr reg access
440 01:49:41.729678 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 01:49:41.743176 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 01:49:42.316945 0.0;M3 CHK:0;cm4_sp_mode 0
443 01:49:42.317582 MVN_1=0x00000000
444 01:49:42.322309 MVN_2=0x00000000
445 01:49:42.328083 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 01:49:42.328535 OPS=0x10
447 01:49:42.328943 ring efuse init
448 01:49:42.329339 chipver efuse init
449 01:49:42.333693 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 01:49:42.339258 [0.018961 Inits done]
451 01:49:42.339707 secure task start!
452 01:49:42.340143 high task start!
453 01:49:42.343955 low task start!
454 01:49:42.344409 run into bl31
455 01:49:42.350499 NOTICE: BL31: v1.3(release):4fc40b1
456 01:49:42.358291 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 01:49:42.358726 NOTICE: BL31: G12A normal boot!
458 01:49:42.383801 NOTICE: BL31: BL33 decompress pass
459 01:49:42.389374 ERROR: Error initializing runtime service opteed_fast
460 01:49:43.622293
461 01:49:43.622891
462 01:49:43.630585 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 01:49:43.631039
464 01:49:43.631451 Model: Libre Computer AML-A311D-CC Alta
465 01:49:43.839081 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 01:49:43.862407 DRAM: 2 GiB (effective 3.8 GiB)
467 01:49:44.005387 Core: 408 devices, 31 uclasses, devicetree: separate
468 01:49:44.011259 WDT: Not starting watchdog@f0d0
469 01:49:44.043600 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 01:49:44.056080 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 01:49:44.060986 ** Bad device specification mmc 0 **
472 01:49:44.071335 Card did not respond to voltage select! : -110
473 01:49:44.078962 ** Bad device specification mmc 0 **
474 01:49:44.079541 Couldn't find partition mmc 0
475 01:49:44.087311 Card did not respond to voltage select! : -110
476 01:49:44.092816 ** Bad device specification mmc 0 **
477 01:49:44.093372 Couldn't find partition mmc 0
478 01:49:44.097883 Error: could not access storage.
479 01:49:45.361308 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 01:49:45.362100 bl2_stage_init 0x01
481 01:49:45.362667 bl2_stage_init 0x81
482 01:49:45.366723 hw id: 0x0000 - pwm id 0x01
483 01:49:45.367324 bl2_stage_init 0xc1
484 01:49:45.367869 bl2_stage_init 0x02
485 01:49:45.368445
486 01:49:45.376191 L0:00000000
487 01:49:45.376770 L1:20000703
488 01:49:45.377298 L2:00008067
489 01:49:45.377825 L3:14000000
490 01:49:45.378339 B2:00402000
491 01:49:45.378848 B1:e0f83180
492 01:49:45.379353
493 01:49:45.379862 TE: 58124
494 01:49:45.380421
495 01:49:45.386395 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 01:49:45.386961
497 01:49:45.387490 Board ID = 1
498 01:49:45.388025 Set A53 clk to 24M
499 01:49:45.388550 Set A73 clk to 24M
500 01:49:45.392069 Set clk81 to 24M
501 01:49:45.392615 A53 clk: 1200 MHz
502 01:49:45.393133 A73 clk: 1200 MHz
503 01:49:45.397583 CLK81: 166.6M
504 01:49:45.398136 smccc: 00012a92
505 01:49:45.403267 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 01:49:45.403907 board id: 1
507 01:49:45.411936 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 01:49:45.422500 fw parse done
509 01:49:45.428402 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 01:49:45.471059 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 01:49:45.482001 PIEI prepare done
512 01:49:45.482576 fastboot data load
513 01:49:45.483100 fastboot data verify
514 01:49:45.487564 verify result: 266
515 01:49:45.493375 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 01:49:45.494031 LPDDR4 probe
517 01:49:45.494571 ddr clk to 1584MHz
518 01:49:45.501180 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 01:49:45.538529
520 01:49:45.539203 dmc_version 0001
521 01:49:45.545171 Check phy result
522 01:49:45.551104 INFO : End of CA training
523 01:49:45.551753 INFO : End of initialization
524 01:49:45.556591 INFO : Training has run successfully!
525 01:49:45.557165 Check phy result
526 01:49:45.562329 INFO : End of initialization
527 01:49:45.562888 INFO : End of read enable training
528 01:49:45.567768 INFO : End of fine write leveling
529 01:49:45.573379 INFO : End of Write leveling coarse delay
530 01:49:45.573959 INFO : Training has run successfully!
531 01:49:45.574482 Check phy result
532 01:49:45.578954 INFO : End of initialization
533 01:49:45.579510 INFO : End of read dq deskew training
534 01:49:45.584542 INFO : End of MPR read delay center optimization
535 01:49:45.590347 INFO : End of write delay center optimization
536 01:49:45.595762 INFO : End of read delay center optimization
537 01:49:45.596358 INFO : End of max read latency training
538 01:49:45.601365 INFO : Training has run successfully!
539 01:49:45.601925 1D training succeed
540 01:49:45.610518 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 01:49:45.658270 Check phy result
542 01:49:45.658955 INFO : End of initialization
543 01:49:45.680776 INFO : End of 2D read delay Voltage center optimization
544 01:49:45.701011 INFO : End of 2D read delay Voltage center optimization
545 01:49:45.753097 INFO : End of 2D write delay Voltage center optimization
546 01:49:45.802541 INFO : End of 2D write delay Voltage center optimization
547 01:49:45.807973 INFO : Training has run successfully!
548 01:49:45.808592
549 01:49:45.809120 channel==0
550 01:49:45.813569 RxClkDly_Margin_A0==88 ps 9
551 01:49:45.814151 TxDqDly_Margin_A0==98 ps 10
552 01:49:45.819174 RxClkDly_Margin_A1==88 ps 9
553 01:49:45.819758 TxDqDly_Margin_A1==98 ps 10
554 01:49:45.820327 TrainedVREFDQ_A0==74
555 01:49:45.824742 TrainedVREFDQ_A1==75
556 01:49:45.825304 VrefDac_Margin_A0==24
557 01:49:45.825818 DeviceVref_Margin_A0==40
558 01:49:45.830348 VrefDac_Margin_A1==25
559 01:49:45.830895 DeviceVref_Margin_A1==39
560 01:49:45.831412
561 01:49:45.831928
562 01:49:45.835921 channel==1
563 01:49:45.836513 RxClkDly_Margin_A0==98 ps 10
564 01:49:45.837049 TxDqDly_Margin_A0==98 ps 10
565 01:49:45.841552 RxClkDly_Margin_A1==98 ps 10
566 01:49:45.842085 TxDqDly_Margin_A1==88 ps 9
567 01:49:45.847132 TrainedVREFDQ_A0==77
568 01:49:45.847676 TrainedVREFDQ_A1==77
569 01:49:45.848235 VrefDac_Margin_A0==22
570 01:49:45.852742 DeviceVref_Margin_A0==37
571 01:49:45.853289 VrefDac_Margin_A1==22
572 01:49:45.858347 DeviceVref_Margin_A1==37
573 01:49:45.858890
574 01:49:45.859405 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 01:49:45.863946
576 01:49:45.891973 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
577 01:49:45.892609 2D training succeed
578 01:49:45.897651 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 01:49:45.903159 auto size-- 65535DDR cs0 size: 2048MB
580 01:49:45.903710 DDR cs1 size: 2048MB
581 01:49:45.908744 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 01:49:45.909294 cs0 DataBus test pass
583 01:49:45.914392 cs1 DataBus test pass
584 01:49:45.914930 cs0 AddrBus test pass
585 01:49:45.915457 cs1 AddrBus test pass
586 01:49:45.915970
587 01:49:45.919976 100bdlr_step_size ps== 420
588 01:49:45.920573 result report
589 01:49:45.925551 boot times 0Enable ddr reg access
590 01:49:45.930981 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 01:49:45.943564 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 01:49:46.517542 0.0;M3 CHK:0;cm4_sp_mode 0
593 01:49:46.518322 MVN_1=0x00000000
594 01:49:46.523008 MVN_2=0x00000000
595 01:49:46.528751 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 01:49:46.529401 OPS=0x10
597 01:49:46.529970 ring efuse init
598 01:49:46.530485 chipver efuse init
599 01:49:46.534385 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 01:49:46.539939 [0.018961 Inits done]
601 01:49:46.540545 secure task start!
602 01:49:46.541066 high task start!
603 01:49:46.544500 low task start!
604 01:49:46.545051 run into bl31
605 01:49:46.551174 NOTICE: BL31: v1.3(release):4fc40b1
606 01:49:46.558967 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 01:49:46.559541 NOTICE: BL31: G12A normal boot!
608 01:49:46.584442 NOTICE: BL31: BL33 decompress pass
609 01:49:46.590003 ERROR: Error initializing runtime service opteed_fast
610 01:49:47.823138
611 01:49:47.823934
612 01:49:47.831521 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 01:49:47.832124
614 01:49:47.832677 Model: Libre Computer AML-A311D-CC Alta
615 01:49:48.039965 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 01:49:48.063353 DRAM: 2 GiB (effective 3.8 GiB)
617 01:49:48.206181 Core: 408 devices, 31 uclasses, devicetree: separate
618 01:49:48.212138 WDT: Not starting watchdog@f0d0
619 01:49:48.244438 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 01:49:48.256810 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 01:49:48.261832 ** Bad device specification mmc 0 **
622 01:49:48.272078 Card did not respond to voltage select! : -110
623 01:49:48.279829 ** Bad device specification mmc 0 **
624 01:49:48.280315 Couldn't find partition mmc 0
625 01:49:48.288068 Card did not respond to voltage select! : -110
626 01:49:48.293648 ** Bad device specification mmc 0 **
627 01:49:48.294082 Couldn't find partition mmc 0
628 01:49:48.298762 Error: could not access storage.
629 01:49:48.642547 Net: eth0: ethernet@ff3f0000
630 01:49:48.643080 starting USB...
631 01:49:48.894529 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 01:49:48.895043 Starting the controller
633 01:49:48.901195 USB XHCI 1.10
634 01:49:50.611630 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 01:49:50.612480 bl2_stage_init 0x01
636 01:49:50.613036 bl2_stage_init 0x81
637 01:49:50.617122 hw id: 0x0000 - pwm id 0x01
638 01:49:50.617705 bl2_stage_init 0xc1
639 01:49:50.618230 bl2_stage_init 0x02
640 01:49:50.618756
641 01:49:50.622757 L0:00000000
642 01:49:50.623306 L1:20000703
643 01:49:50.623835 L2:00008067
644 01:49:50.624390 L3:14000000
645 01:49:50.628364 B2:00402000
646 01:49:50.628937 B1:e0f83180
647 01:49:50.629457
648 01:49:50.629977 TE: 58124
649 01:49:50.630493
650 01:49:50.633944 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 01:49:50.634507
652 01:49:50.635027 Board ID = 1
653 01:49:50.639488 Set A53 clk to 24M
654 01:49:50.640072 Set A73 clk to 24M
655 01:49:50.640607 Set clk81 to 24M
656 01:49:50.645165 A53 clk: 1200 MHz
657 01:49:50.645716 A73 clk: 1200 MHz
658 01:49:50.646232 CLK81: 166.6M
659 01:49:50.646753 smccc: 00012a92
660 01:49:50.650798 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 01:49:50.656315 board id: 1
662 01:49:50.662316 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 01:49:50.672944 fw parse done
664 01:49:50.678959 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 01:49:50.721377 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 01:49:50.732253 PIEI prepare done
667 01:49:50.732805 fastboot data load
668 01:49:50.733329 fastboot data verify
669 01:49:50.737851 verify result: 266
670 01:49:50.743442 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 01:49:50.744029 LPDDR4 probe
672 01:49:50.744565 ddr clk to 1584MHz
673 01:49:50.751439 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 01:49:50.788690
675 01:49:50.789291 dmc_version 0001
676 01:49:50.795363 Check phy result
677 01:49:50.801255 INFO : End of CA training
678 01:49:50.801828 INFO : End of initialization
679 01:49:50.806842 INFO : Training has run successfully!
680 01:49:50.807403 Check phy result
681 01:49:50.812453 INFO : End of initialization
682 01:49:50.813016 INFO : End of read enable training
683 01:49:50.818066 INFO : End of fine write leveling
684 01:49:50.823640 INFO : End of Write leveling coarse delay
685 01:49:50.824231 INFO : Training has run successfully!
686 01:49:50.824766 Check phy result
687 01:49:50.829225 INFO : End of initialization
688 01:49:50.829798 INFO : End of read dq deskew training
689 01:49:50.834842 INFO : End of MPR read delay center optimization
690 01:49:50.840436 INFO : End of write delay center optimization
691 01:49:50.846054 INFO : End of read delay center optimization
692 01:49:50.846605 INFO : End of max read latency training
693 01:49:50.851664 INFO : Training has run successfully!
694 01:49:50.852258 1D training succeed
695 01:49:50.860882 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 01:49:50.908412 Check phy result
697 01:49:50.909001 INFO : End of initialization
698 01:49:50.930188 INFO : End of 2D read delay Voltage center optimization
699 01:49:50.950498 INFO : End of 2D read delay Voltage center optimization
700 01:49:51.002466 INFO : End of 2D write delay Voltage center optimization
701 01:49:51.051873 INFO : End of 2D write delay Voltage center optimization
702 01:49:51.057424 INFO : Training has run successfully!
703 01:49:51.057998
704 01:49:51.058548 channel==0
705 01:49:51.063088 RxClkDly_Margin_A0==88 ps 9
706 01:49:51.063638 TxDqDly_Margin_A0==98 ps 10
707 01:49:51.068620 RxClkDly_Margin_A1==88 ps 9
708 01:49:51.069170 TxDqDly_Margin_A1==98 ps 10
709 01:49:51.069701 TrainedVREFDQ_A0==74
710 01:49:51.074231 TrainedVREFDQ_A1==74
711 01:49:51.074791 VrefDac_Margin_A0==25
712 01:49:51.075320 DeviceVref_Margin_A0==40
713 01:49:51.079861 VrefDac_Margin_A1==24
714 01:49:51.080457 DeviceVref_Margin_A1==40
715 01:49:51.080981
716 01:49:51.081508
717 01:49:51.085454 channel==1
718 01:49:51.086010 RxClkDly_Margin_A0==98 ps 10
719 01:49:51.086537 TxDqDly_Margin_A0==98 ps 10
720 01:49:51.091075 RxClkDly_Margin_A1==88 ps 9
721 01:49:51.091626 TxDqDly_Margin_A1==88 ps 9
722 01:49:51.096625 TrainedVREFDQ_A0==77
723 01:49:51.097171 TrainedVREFDQ_A1==77
724 01:49:51.097690 VrefDac_Margin_A0==22
725 01:49:51.102226 DeviceVref_Margin_A0==37
726 01:49:51.102766 VrefDac_Margin_A1==24
727 01:49:51.107839 DeviceVref_Margin_A1==37
728 01:49:51.108407
729 01:49:51.108939 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 01:49:51.109453
731 01:49:51.141418 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
732 01:49:51.142032 2D training succeed
733 01:49:51.147090 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 01:49:51.152617 auto size-- 65535DDR cs0 size: 2048MB
735 01:49:51.153174 DDR cs1 size: 2048MB
736 01:49:51.158218 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 01:49:51.158778 cs0 DataBus test pass
738 01:49:51.163909 cs1 DataBus test pass
739 01:49:51.164495 cs0 AddrBus test pass
740 01:49:51.165011 cs1 AddrBus test pass
741 01:49:51.165522
742 01:49:51.169396 100bdlr_step_size ps== 420
743 01:49:51.169966 result report
744 01:49:51.175108 boot times 0Enable ddr reg access
745 01:49:51.180313 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 01:49:51.193918 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 01:49:51.767691 0.0;M3 CHK:0;cm4_sp_mode 0
748 01:49:51.768543 MVN_1=0x00000000
749 01:49:51.773040 MVN_2=0x00000000
750 01:49:51.778850 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 01:49:51.779521 OPS=0x10
752 01:49:51.780098 ring efuse init
753 01:49:51.780620 chipver efuse init
754 01:49:51.784378 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 01:49:51.789981 [0.018960 Inits done]
756 01:49:51.790525 secure task start!
757 01:49:51.791031 high task start!
758 01:49:51.794537 low task start!
759 01:49:51.795061 run into bl31
760 01:49:51.801175 NOTICE: BL31: v1.3(release):4fc40b1
761 01:49:51.809000 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 01:49:51.809543 NOTICE: BL31: G12A normal boot!
763 01:49:51.834348 NOTICE: BL31: BL33 decompress pass
764 01:49:51.840024 ERROR: Error initializing runtime service opteed_fast
765 01:49:53.073003
766 01:49:53.073795
767 01:49:53.080395 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 01:49:53.080994
769 01:49:53.081514 Model: Libre Computer AML-A311D-CC Alta
770 01:49:53.289778 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 01:49:53.313067 DRAM: 2 GiB (effective 3.8 GiB)
772 01:49:53.456301 Core: 408 devices, 31 uclasses, devicetree: separate
773 01:49:53.461958 WDT: Not starting watchdog@f0d0
774 01:49:53.494204 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 01:49:53.506702 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 01:49:53.510732 ** Bad device specification mmc 0 **
777 01:49:53.521965 Card did not respond to voltage select! : -110
778 01:49:53.529632 ** Bad device specification mmc 0 **
779 01:49:53.530211 Couldn't find partition mmc 0
780 01:49:53.537963 Card did not respond to voltage select! : -110
781 01:49:53.543478 ** Bad device specification mmc 0 **
782 01:49:53.544098 Couldn't find partition mmc 0
783 01:49:53.548543 Error: could not access storage.
784 01:49:53.891024 Net: eth0: ethernet@ff3f0000
785 01:49:53.891801 starting USB...
786 01:49:54.142879 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 01:49:54.143639 Starting the controller
788 01:49:54.148780 USB XHCI 1.10
789 01:49:56.311782 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 01:49:56.312623 bl2_stage_init 0x01
791 01:49:56.313218 bl2_stage_init 0x81
792 01:49:56.317364 hw id: 0x0000 - pwm id 0x01
793 01:49:56.317976 bl2_stage_init 0xc1
794 01:49:56.318526 bl2_stage_init 0x02
795 01:49:56.319091
796 01:49:56.322927 L0:00000000
797 01:49:56.323423 L1:20000703
798 01:49:56.323843 L2:00008067
799 01:49:56.324376 L3:14000000
800 01:49:56.325927 B2:00402000
801 01:49:56.326352 B1:e0f83180
802 01:49:56.326755
803 01:49:56.327155 TE: 58159
804 01:49:56.327553
805 01:49:56.337015 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 01:49:56.337459
807 01:49:56.337864 Board ID = 1
808 01:49:56.338260 Set A53 clk to 24M
809 01:49:56.338652 Set A73 clk to 24M
810 01:49:56.342634 Set clk81 to 24M
811 01:49:56.343054 A53 clk: 1200 MHz
812 01:49:56.343453 A73 clk: 1200 MHz
813 01:49:56.348319 CLK81: 166.6M
814 01:49:56.348757 smccc: 00012ab5
815 01:49:56.353902 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 01:49:56.354340 board id: 1
817 01:49:56.362450 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 01:49:56.373026 fw parse done
819 01:49:56.379028 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 01:49:56.421623 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 01:49:56.432493 PIEI prepare done
822 01:49:56.432953 fastboot data load
823 01:49:56.433367 fastboot data verify
824 01:49:56.438059 verify result: 266
825 01:49:56.443752 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 01:49:56.444236 LPDDR4 probe
827 01:49:56.444641 ddr clk to 1584MHz
828 01:49:56.451709 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 01:49:56.488072
830 01:49:56.488535 dmc_version 0001
831 01:49:56.494747 Check phy result
832 01:49:56.501513 INFO : End of CA training
833 01:49:56.501958 INFO : End of initialization
834 01:49:56.507130 INFO : Training has run successfully!
835 01:49:56.507569 Check phy result
836 01:49:56.512649 INFO : End of initialization
837 01:49:56.513099 INFO : End of read enable training
838 01:49:56.516074 INFO : End of fine write leveling
839 01:49:56.521620 INFO : End of Write leveling coarse delay
840 01:49:56.527210 INFO : Training has run successfully!
841 01:49:56.527652 Check phy result
842 01:49:56.528083 INFO : End of initialization
843 01:49:56.533147 INFO : End of read dq deskew training
844 01:49:56.538569 INFO : End of MPR read delay center optimization
845 01:49:56.539283 INFO : End of write delay center optimization
846 01:49:56.544064 INFO : End of read delay center optimization
847 01:49:56.549700 INFO : End of max read latency training
848 01:49:56.550414 INFO : Training has run successfully!
849 01:49:56.555322 1D training succeed
850 01:49:56.560321 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 01:49:56.608589 Check phy result
852 01:49:56.609072 INFO : End of initialization
853 01:49:56.630355 INFO : End of 2D read delay Voltage center optimization
854 01:49:56.649709 INFO : End of 2D read delay Voltage center optimization
855 01:49:56.701679 INFO : End of 2D write delay Voltage center optimization
856 01:49:56.752043 INFO : End of 2D write delay Voltage center optimization
857 01:49:56.757624 INFO : Training has run successfully!
858 01:49:56.758059
859 01:49:56.758462 channel==0
860 01:49:56.763181 RxClkDly_Margin_A0==88 ps 9
861 01:49:56.763633 TxDqDly_Margin_A0==98 ps 10
862 01:49:56.768861 RxClkDly_Margin_A1==88 ps 9
863 01:49:56.769290 TxDqDly_Margin_A1==98 ps 10
864 01:49:56.769702 TrainedVREFDQ_A0==74
865 01:49:56.774394 TrainedVREFDQ_A1==74
866 01:49:56.774858 VrefDac_Margin_A0==25
867 01:49:56.775254 DeviceVref_Margin_A0==40
868 01:49:56.780021 VrefDac_Margin_A1==25
869 01:49:56.780506 DeviceVref_Margin_A1==40
870 01:49:56.780914
871 01:49:56.781301
872 01:49:56.785624 channel==1
873 01:49:56.786045 RxClkDly_Margin_A0==88 ps 9
874 01:49:56.786431 TxDqDly_Margin_A0==98 ps 10
875 01:49:56.791168 RxClkDly_Margin_A1==88 ps 9
876 01:49:56.791585 TxDqDly_Margin_A1==88 ps 9
877 01:49:56.796869 TrainedVREFDQ_A0==77
878 01:49:56.797289 TrainedVREFDQ_A1==77
879 01:49:56.797678 VrefDac_Margin_A0==22
880 01:49:56.802375 DeviceVref_Margin_A0==37
881 01:49:56.802791 VrefDac_Margin_A1==24
882 01:49:56.808031 DeviceVref_Margin_A1==37
883 01:49:56.808447
884 01:49:56.808834 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 01:49:56.809215
886 01:49:56.841627 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000016 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
887 01:49:56.842094 2D training succeed
888 01:49:56.847163 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 01:49:56.852873 auto size-- 65535DDR cs0 size: 2048MB
890 01:49:56.853288 DDR cs1 size: 2048MB
891 01:49:56.858379 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 01:49:56.858798 cs0 DataBus test pass
893 01:49:56.864017 cs1 DataBus test pass
894 01:49:56.864439 cs0 AddrBus test pass
895 01:49:56.864825 cs1 AddrBus test pass
896 01:49:56.865203
897 01:49:56.869630 100bdlr_step_size ps== 420
898 01:49:56.870056 result report
899 01:49:56.875181 boot times 0Enable ddr reg access
900 01:49:56.880450 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 01:49:56.893965 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 01:49:57.467658 0.0;M3 CHK:0;cm4_sp_mode 0
903 01:49:57.468362 MVN_1=0x00000000
904 01:49:57.473001 MVN_2=0x00000000
905 01:49:57.478785 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 01:49:57.479254 OPS=0x10
907 01:49:57.479664 ring efuse init
908 01:49:57.480096 chipver efuse init
909 01:49:57.486964 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 01:49:57.487416 [0.018961 Inits done]
911 01:49:57.494552 secure task start!
912 01:49:57.494994 high task start!
913 01:49:57.495394 low task start!
914 01:49:57.495785 run into bl31
915 01:49:57.501210 NOTICE: BL31: v1.3(release):4fc40b1
916 01:49:57.509058 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 01:49:57.509525 NOTICE: BL31: G12A normal boot!
918 01:49:57.534328 NOTICE: BL31: BL33 decompress pass
919 01:49:57.540053 ERROR: Error initializing runtime service opteed_fast
920 01:49:58.773062
921 01:49:58.773687
922 01:49:58.781332 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 01:49:58.781827
924 01:49:58.782244 Model: Libre Computer AML-A311D-CC Alta
925 01:49:58.989689 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 01:49:59.012293 DRAM: 2 GiB (effective 3.8 GiB)
927 01:49:59.156359 Core: 408 devices, 31 uclasses, devicetree: separate
928 01:49:59.162041 WDT: Not starting watchdog@f0d0
929 01:49:59.194314 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 01:49:59.207000 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 01:49:59.211479 ** Bad device specification mmc 0 **
932 01:49:59.222271 Card did not respond to voltage select! : -110
933 01:49:59.229709 ** Bad device specification mmc 0 **
934 01:49:59.230240 Couldn't find partition mmc 0
935 01:49:59.238127 Card did not respond to voltage select! : -110
936 01:49:59.243579 ** Bad device specification mmc 0 **
937 01:49:59.244116 Couldn't find partition mmc 0
938 01:49:59.248597 Error: could not access storage.
939 01:49:59.590187 Net: eth0: ethernet@ff3f0000
940 01:49:59.590578 starting USB...
941 01:49:59.842869 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 01:49:59.843483 Starting the controller
943 01:49:59.849846 USB XHCI 1.10
944 01:50:01.711599 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 01:50:01.712266 bl2_stage_init 0x01
946 01:50:01.712693 bl2_stage_init 0x81
947 01:50:01.716985 hw id: 0x0000 - pwm id 0x01
948 01:50:01.717446 bl2_stage_init 0xc1
949 01:50:01.717856 bl2_stage_init 0x02
950 01:50:01.718256
951 01:50:01.722643 L0:00000000
952 01:50:01.723091 L1:20000703
953 01:50:01.723496 L2:00008067
954 01:50:01.723892 L3:14000000
955 01:50:01.725686 B2:00402000
956 01:50:01.726118 B1:e0f83180
957 01:50:01.726518
958 01:50:01.726918 TE: 58159
959 01:50:01.727318
960 01:50:01.737276 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 01:50:01.737742
962 01:50:01.738150 Board ID = 1
963 01:50:01.738548 Set A53 clk to 24M
964 01:50:01.738943 Set A73 clk to 24M
965 01:50:01.742552 Set clk81 to 24M
966 01:50:01.743001 A53 clk: 1200 MHz
967 01:50:01.743408 A73 clk: 1200 MHz
968 01:50:01.746168 CLK81: 166.6M
969 01:50:01.746605 smccc: 00012ab4
970 01:50:01.751041 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 01:50:01.756102 board id: 1
972 01:50:01.762075 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 01:50:01.773047 fw parse done
974 01:50:01.779254 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 01:50:01.821514 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 01:50:01.832311 PIEI prepare done
977 01:50:01.832754 fastboot data load
978 01:50:01.833146 fastboot data verify
979 01:50:01.837904 verify result: 266
980 01:50:01.843564 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 01:50:01.844029 LPDDR4 probe
982 01:50:01.844426 ddr clk to 1584MHz
983 01:50:01.851221 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 01:50:01.888711
985 01:50:01.889176 dmc_version 0001
986 01:50:01.895250 Check phy result
987 01:50:01.901706 INFO : End of CA training
988 01:50:01.902152 INFO : End of initialization
989 01:50:01.906707 INFO : Training has run successfully!
990 01:50:01.907133 Check phy result
991 01:50:01.912349 INFO : End of initialization
992 01:50:01.912815 INFO : End of read enable training
993 01:50:01.918537 INFO : End of fine write leveling
994 01:50:01.923563 INFO : End of Write leveling coarse delay
995 01:50:01.924036 INFO : Training has run successfully!
996 01:50:01.924443 Check phy result
997 01:50:01.929871 INFO : End of initialization
998 01:50:01.930320 INFO : End of read dq deskew training
999 01:50:01.935016 INFO : End of MPR read delay center optimization
1000 01:50:01.940547 INFO : End of write delay center optimization
1001 01:50:01.946202 INFO : End of read delay center optimization
1002 01:50:01.946793 INFO : End of max read latency training
1003 01:50:01.951908 INFO : Training has run successfully!
1004 01:50:01.952533 1D training succeed
1005 01:50:01.960774 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 01:50:02.008393 Check phy result
1007 01:50:02.008907 INFO : End of initialization
1008 01:50:02.029799 INFO : End of 2D read delay Voltage center optimization
1009 01:50:02.050462 INFO : End of 2D read delay Voltage center optimization
1010 01:50:02.101998 INFO : End of 2D write delay Voltage center optimization
1011 01:50:02.151348 INFO : End of 2D write delay Voltage center optimization
1012 01:50:02.157095 INFO : Training has run successfully!
1013 01:50:02.157661
1014 01:50:02.159415 channel==0
1015 01:50:02.162521 RxClkDly_Margin_A0==88 ps 9
1016 01:50:02.163077 TxDqDly_Margin_A0==98 ps 10
1017 01:50:02.168389 RxClkDly_Margin_A1==88 ps 9
1018 01:50:02.168967 TxDqDly_Margin_A1==98 ps 10
1019 01:50:02.169467 TrainedVREFDQ_A0==74
1020 01:50:02.174686 TrainedVREFDQ_A1==74
1021 01:50:02.174997 VrefDac_Margin_A0==25
1022 01:50:02.175227 DeviceVref_Margin_A0==40
1023 01:50:02.181027 VrefDac_Margin_A1==25
1024 01:50:02.183010 DeviceVref_Margin_A1==40
1025 01:50:02.183504
1026 01:50:02.183971
1027 01:50:02.185534 channel==1
1028 01:50:02.185863 RxClkDly_Margin_A0==98 ps 10
1029 01:50:02.186863 TxDqDly_Margin_A0==98 ps 10
1030 01:50:02.190399 RxClkDly_Margin_A1==98 ps 10
1031 01:50:02.190710 TxDqDly_Margin_A1==98 ps 10
1032 01:50:02.196486 TrainedVREFDQ_A0==77
1033 01:50:02.197073 TrainedVREFDQ_A1==77
1034 01:50:02.197553 VrefDac_Margin_A0==22
1035 01:50:02.201551 DeviceVref_Margin_A0==37
1036 01:50:02.201916 VrefDac_Margin_A1==22
1037 01:50:02.207739 DeviceVref_Margin_A1==37
1038 01:50:02.208370
1039 01:50:02.208877 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 01:50:02.213184
1041 01:50:02.241146 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
1042 01:50:02.241962 2D training succeed
1043 01:50:02.246677 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 01:50:02.252273 auto size-- 65535DDR cs0 size: 2048MB
1045 01:50:02.253277 DDR cs1 size: 2048MB
1046 01:50:02.257742 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 01:50:02.258322 cs0 DataBus test pass
1048 01:50:02.263297 cs1 DataBus test pass
1049 01:50:02.264640 cs0 AddrBus test pass
1050 01:50:02.265294 cs1 AddrBus test pass
1051 01:50:02.265771
1052 01:50:02.269274 100bdlr_step_size ps== 420
1053 01:50:02.269863 result report
1054 01:50:02.274495 boot times 0Enable ddr reg access
1055 01:50:02.280388 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 01:50:02.294266 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 01:50:02.865598 0.0;M3 CHK:0;cm4_sp_mode 0
1058 01:50:02.866288 MVN_1=0x00000000
1059 01:50:02.871062 MVN_2=0x00000000
1060 01:50:02.876860 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 01:50:02.877416 OPS=0x10
1062 01:50:02.877886 ring efuse init
1063 01:50:02.878340 chipver efuse init
1064 01:50:02.882456 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 01:50:02.888093 [0.018961 Inits done]
1066 01:50:02.888640 secure task start!
1067 01:50:02.889103 high task start!
1068 01:50:02.892688 low task start!
1069 01:50:02.893244 run into bl31
1070 01:50:02.899335 NOTICE: BL31: v1.3(release):4fc40b1
1071 01:50:02.907094 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 01:50:02.907647 NOTICE: BL31: G12A normal boot!
1073 01:50:02.932289 NOTICE: BL31: BL33 decompress pass
1074 01:50:02.937894 ERROR: Error initializing runtime service opteed_fast
1075 01:50:04.171022
1076 01:50:04.171617
1077 01:50:04.179220 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 01:50:04.179682
1079 01:50:04.180129 Model: Libre Computer AML-A311D-CC Alta
1080 01:50:04.387766 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 01:50:04.411219 DRAM: 2 GiB (effective 3.8 GiB)
1082 01:50:04.554209 Core: 408 devices, 31 uclasses, devicetree: separate
1083 01:50:04.560055 WDT: Not starting watchdog@f0d0
1084 01:50:04.592190 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 01:50:04.604682 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 01:50:04.609645 ** Bad device specification mmc 0 **
1087 01:50:04.619967 Card did not respond to voltage select! : -110
1088 01:50:04.627644 ** Bad device specification mmc 0 **
1089 01:50:04.628101 Couldn't find partition mmc 0
1090 01:50:04.636003 Card did not respond to voltage select! : -110
1091 01:50:04.641484 ** Bad device specification mmc 0 **
1092 01:50:04.641919 Couldn't find partition mmc 0
1093 01:50:04.646530 Error: could not access storage.
1094 01:50:04.989077 Net: eth0: ethernet@ff3f0000
1095 01:50:04.989585 starting USB...
1096 01:50:05.240935 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 01:50:05.241438 Starting the controller
1098 01:50:05.247853 USB XHCI 1.10
1099 01:50:06.804249 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 01:50:06.812476 scanning usb for storage devices... 0 Storage Device(s) found
1102 01:50:06.863469 Hit any key to stop autoboot: 1
1103 01:50:06.864078 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 01:50:06.864414 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 01:50:06.864668 Setting prompt string to ['=>']
1106 01:50:06.864923 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 01:50:06.869896 0
1108 01:50:06.870482 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 01:50:06.870748 Sending with 10 millisecond of delay
1111 01:50:08.004477 => setenv autoload no
1112 01:50:08.015217 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1113 01:50:08.017789 setenv autoload no
1114 01:50:08.018293 Sending with 10 millisecond of delay
1116 01:50:09.813989 => setenv initrd_high 0xffffffff
1117 01:50:09.824713 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 01:50:09.825197 setenv initrd_high 0xffffffff
1119 01:50:09.825660 Sending with 10 millisecond of delay
1121 01:50:11.440879 => setenv fdt_high 0xffffffff
1122 01:50:11.451631 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 01:50:11.452190 setenv fdt_high 0xffffffff
1124 01:50:11.452669 Sending with 10 millisecond of delay
1126 01:50:11.743968 => dhcp
1127 01:50:11.754702 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 01:50:11.755232 dhcp
1129 01:50:11.755458 Speed: 1000, full duplex
1130 01:50:11.755665 BOOTP broadcast 1
1131 01:50:11.763004 DHCP client bound to address 192.168.6.27 (8 ms)
1132 01:50:11.763508 Sending with 10 millisecond of delay
1134 01:50:13.438776 => setenv serverip 192.168.6.2
1135 01:50:13.450125 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1136 01:50:13.451584 setenv serverip 192.168.6.2
1137 01:50:13.452804 Sending with 10 millisecond of delay
1139 01:50:17.178289 => tftpboot 0x01080000 973315/tftp-deploy-eaofl1o7/kernel/uImage
1140 01:50:17.189096 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1141 01:50:17.190371 tftpboot 0x01080000 973315/tftp-deploy-eaofl1o7/kernel/uImage
1142 01:50:17.191083 Speed: 1000, full duplex
1143 01:50:17.191787 Using ethernet@ff3f0000 device
1144 01:50:17.192338 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1145 01:50:17.197374 Filename '973315/tftp-deploy-eaofl1o7/kernel/uImage'.
1146 01:50:17.201250 Load address: 0x1080000
1147 01:50:19.997021 Loading: *################################################## 43.6 MiB
1148 01:50:19.997692 15.6 MiB/s
1149 01:50:19.998139 done
1150 01:50:20.001482 Bytes transferred = 45716032 (2b99240 hex)
1151 01:50:20.002331 Sending with 10 millisecond of delay
1153 01:50:24.689549 => tftpboot 0x08000000 973315/tftp-deploy-eaofl1o7/ramdisk/ramdisk.cpio.gz.uboot
1154 01:50:24.700389 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1155 01:50:24.701280 tftpboot 0x08000000 973315/tftp-deploy-eaofl1o7/ramdisk/ramdisk.cpio.gz.uboot
1156 01:50:24.701760 Speed: 1000, full duplex
1157 01:50:24.702212 Using ethernet@ff3f0000 device
1158 01:50:24.703751 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1159 01:50:24.711965 Filename '973315/tftp-deploy-eaofl1o7/ramdisk/ramdisk.cpio.gz.uboot'.
1160 01:50:24.712542 Load address: 0x8000000
1161 01:50:31.462574 Loading: *######################T ########################### UDP wrong checksum 00000005 000032bb
1162 01:50:36.463851 T UDP wrong checksum 00000005 000032bb
1163 01:50:46.467309 T T UDP wrong checksum 00000005 000032bb
1164 01:51:06.469334 T T T UDP wrong checksum 00000005 000032bb
1165 01:51:21.475124 T T T
1166 01:51:21.475758 Retry count exceeded; starting again
1168 01:51:21.477247 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1171 01:51:21.479122 end: 2.4 uboot-commands (duration 00:01:52) [common]
1173 01:51:21.480549 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1175 01:51:21.481544 end: 2 uboot-action (duration 00:01:52) [common]
1177 01:51:21.483014 Cleaning after the job
1178 01:51:21.483549 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973315/tftp-deploy-eaofl1o7/ramdisk
1179 01:51:21.484828 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973315/tftp-deploy-eaofl1o7/kernel
1180 01:51:21.514864 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973315/tftp-deploy-eaofl1o7/dtb
1181 01:51:21.515714 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973315/tftp-deploy-eaofl1o7/nfsrootfs
1182 01:51:21.814614 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973315/tftp-deploy-eaofl1o7/modules
1183 01:51:21.836676 start: 4.1 power-off (timeout 00:00:30) [common]
1184 01:51:21.837346 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1185 01:51:21.870825 >> OK - accepted request
1186 01:51:21.872924 Returned 0 in 0 seconds
1187 01:51:21.973650 end: 4.1 power-off (duration 00:00:00) [common]
1189 01:51:21.974620 start: 4.2 read-feedback (timeout 00:10:00) [common]
1190 01:51:21.975262 Listened to connection for namespace 'common' for up to 1s
1191 01:51:22.975886 Finalising connection for namespace 'common'
1192 01:51:22.976733 Disconnecting from shell: Finalise
1193 01:51:22.977304 =>
1194 01:51:23.078379 end: 4.2 read-feedback (duration 00:00:01) [common]
1195 01:51:23.079044 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/973315
1196 01:51:25.608373 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/973315
1197 01:51:25.608985 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.