Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 01:34:05.930832 lava-dispatcher, installed at version: 2024.01
2 01:34:05.931598 start: 0 validate
3 01:34:05.932100 Start time: 2024-11-11 01:34:05.932069+00:00 (UTC)
4 01:34:05.932635 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 01:34:05.933183 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 01:34:05.973626 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 01:34:05.974168 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-415-g0e90fad093db9%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 01:34:05.999801 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 01:34:06.000439 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-415-g0e90fad093db9%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 01:34:06.028861 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 01:34:06.029367 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 01:34:06.058435 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 01:34:06.058953 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc6-415-g0e90fad093db9%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 01:34:06.095081 validate duration: 0.16
16 01:34:06.095951 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 01:34:06.096311 start: 1.1 download-retry (timeout 00:10:00) [common]
18 01:34:06.096636 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 01:34:06.097232 Not decompressing ramdisk as can be used compressed.
20 01:34:06.097683 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 01:34:06.097972 saving as /var/lib/lava/dispatcher/tmp/973280/tftp-deploy-ienrcya0/ramdisk/initrd.cpio.gz
22 01:34:06.098254 total size: 5628140 (5 MB)
23 01:34:06.131021 progress 0 % (0 MB)
24 01:34:06.135392 progress 5 % (0 MB)
25 01:34:06.139618 progress 10 % (0 MB)
26 01:34:06.143554 progress 15 % (0 MB)
27 01:34:06.147943 progress 20 % (1 MB)
28 01:34:06.151917 progress 25 % (1 MB)
29 01:34:06.156150 progress 30 % (1 MB)
30 01:34:06.160264 progress 35 % (1 MB)
31 01:34:06.163881 progress 40 % (2 MB)
32 01:34:06.167904 progress 45 % (2 MB)
33 01:34:06.171558 progress 50 % (2 MB)
34 01:34:06.175643 progress 55 % (2 MB)
35 01:34:06.179701 progress 60 % (3 MB)
36 01:34:06.183479 progress 65 % (3 MB)
37 01:34:06.187649 progress 70 % (3 MB)
38 01:34:06.191346 progress 75 % (4 MB)
39 01:34:06.195408 progress 80 % (4 MB)
40 01:34:06.199074 progress 85 % (4 MB)
41 01:34:06.203089 progress 90 % (4 MB)
42 01:34:06.207104 progress 95 % (5 MB)
43 01:34:06.210448 progress 100 % (5 MB)
44 01:34:06.211105 5 MB downloaded in 0.11 s (47.57 MB/s)
45 01:34:06.211665 end: 1.1.1 http-download (duration 00:00:00) [common]
47 01:34:06.212583 end: 1.1 download-retry (duration 00:00:00) [common]
48 01:34:06.212884 start: 1.2 download-retry (timeout 00:10:00) [common]
49 01:34:06.213163 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 01:34:06.213637 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-415-g0e90fad093db9/arm64/defconfig/gcc-12/kernel/Image
51 01:34:06.213887 saving as /var/lib/lava/dispatcher/tmp/973280/tftp-deploy-ienrcya0/kernel/Image
52 01:34:06.214097 total size: 45715968 (43 MB)
53 01:34:06.214308 No compression specified
54 01:34:06.248094 progress 0 % (0 MB)
55 01:34:06.277188 progress 5 % (2 MB)
56 01:34:06.306777 progress 10 % (4 MB)
57 01:34:06.336111 progress 15 % (6 MB)
58 01:34:06.365353 progress 20 % (8 MB)
59 01:34:06.394411 progress 25 % (10 MB)
60 01:34:06.423841 progress 30 % (13 MB)
61 01:34:06.453322 progress 35 % (15 MB)
62 01:34:06.482415 progress 40 % (17 MB)
63 01:34:06.511742 progress 45 % (19 MB)
64 01:34:06.541490 progress 50 % (21 MB)
65 01:34:06.571027 progress 55 % (24 MB)
66 01:34:06.600816 progress 60 % (26 MB)
67 01:34:06.629590 progress 65 % (28 MB)
68 01:34:06.658907 progress 70 % (30 MB)
69 01:34:06.688120 progress 75 % (32 MB)
70 01:34:06.717588 progress 80 % (34 MB)
71 01:34:06.746610 progress 85 % (37 MB)
72 01:34:06.776079 progress 90 % (39 MB)
73 01:34:06.805451 progress 95 % (41 MB)
74 01:34:06.834241 progress 100 % (43 MB)
75 01:34:06.834791 43 MB downloaded in 0.62 s (70.24 MB/s)
76 01:34:06.835284 end: 1.2.1 http-download (duration 00:00:01) [common]
78 01:34:06.836139 end: 1.2 download-retry (duration 00:00:01) [common]
79 01:34:06.836425 start: 1.3 download-retry (timeout 00:09:59) [common]
80 01:34:06.836701 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 01:34:06.837179 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-415-g0e90fad093db9/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 01:34:06.837465 saving as /var/lib/lava/dispatcher/tmp/973280/tftp-deploy-ienrcya0/dtb/meson-g12b-a311d-libretech-cc.dtb
83 01:34:06.837675 total size: 54703 (0 MB)
84 01:34:06.837884 No compression specified
85 01:34:06.873493 progress 59 % (0 MB)
86 01:34:06.874330 progress 100 % (0 MB)
87 01:34:06.874886 0 MB downloaded in 0.04 s (1.40 MB/s)
88 01:34:06.875374 end: 1.3.1 http-download (duration 00:00:00) [common]
90 01:34:06.876244 end: 1.3 download-retry (duration 00:00:00) [common]
91 01:34:06.876517 start: 1.4 download-retry (timeout 00:09:59) [common]
92 01:34:06.876785 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 01:34:06.877236 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 01:34:06.877489 saving as /var/lib/lava/dispatcher/tmp/973280/tftp-deploy-ienrcya0/nfsrootfs/full.rootfs.tar
95 01:34:06.877694 total size: 474398908 (452 MB)
96 01:34:06.877906 Using unxz to decompress xz
97 01:34:06.911769 progress 0 % (0 MB)
98 01:34:08.014440 progress 5 % (22 MB)
99 01:34:09.510400 progress 10 % (45 MB)
100 01:34:09.957655 progress 15 % (67 MB)
101 01:34:10.800142 progress 20 % (90 MB)
102 01:34:11.340791 progress 25 % (113 MB)
103 01:34:11.705765 progress 30 % (135 MB)
104 01:34:12.316017 progress 35 % (158 MB)
105 01:34:13.186718 progress 40 % (181 MB)
106 01:34:14.072400 progress 45 % (203 MB)
107 01:34:14.738552 progress 50 % (226 MB)
108 01:34:15.391801 progress 55 % (248 MB)
109 01:34:16.621641 progress 60 % (271 MB)
110 01:34:18.131814 progress 65 % (294 MB)
111 01:34:19.851146 progress 70 % (316 MB)
112 01:34:23.050265 progress 75 % (339 MB)
113 01:34:25.479209 progress 80 % (361 MB)
114 01:34:28.364468 progress 85 % (384 MB)
115 01:34:31.514648 progress 90 % (407 MB)
116 01:34:34.701348 progress 95 % (429 MB)
117 01:34:37.871382 progress 100 % (452 MB)
118 01:34:37.884290 452 MB downloaded in 31.01 s (14.59 MB/s)
119 01:34:37.885147 end: 1.4.1 http-download (duration 00:00:31) [common]
121 01:34:37.886714 end: 1.4 download-retry (duration 00:00:31) [common]
122 01:34:37.887220 start: 1.5 download-retry (timeout 00:09:28) [common]
123 01:34:37.887723 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 01:34:37.888871 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc6-415-g0e90fad093db9/arm64/defconfig/gcc-12/modules.tar.xz
125 01:34:37.889349 saving as /var/lib/lava/dispatcher/tmp/973280/tftp-deploy-ienrcya0/modules/modules.tar
126 01:34:37.889750 total size: 11620588 (11 MB)
127 01:34:37.890160 Using unxz to decompress xz
128 01:34:37.936087 progress 0 % (0 MB)
129 01:34:38.002608 progress 5 % (0 MB)
130 01:34:38.076347 progress 10 % (1 MB)
131 01:34:38.173663 progress 15 % (1 MB)
132 01:34:38.265364 progress 20 % (2 MB)
133 01:34:38.346493 progress 25 % (2 MB)
134 01:34:38.423275 progress 30 % (3 MB)
135 01:34:38.503789 progress 35 % (3 MB)
136 01:34:38.576710 progress 40 % (4 MB)
137 01:34:38.651928 progress 45 % (5 MB)
138 01:34:38.736219 progress 50 % (5 MB)
139 01:34:38.817178 progress 55 % (6 MB)
140 01:34:38.899753 progress 60 % (6 MB)
141 01:34:38.982411 progress 65 % (7 MB)
142 01:34:39.064577 progress 70 % (7 MB)
143 01:34:39.145528 progress 75 % (8 MB)
144 01:34:39.229839 progress 80 % (8 MB)
145 01:34:39.309921 progress 85 % (9 MB)
146 01:34:39.392823 progress 90 % (10 MB)
147 01:34:39.466713 progress 95 % (10 MB)
148 01:34:39.544315 progress 100 % (11 MB)
149 01:34:39.557631 11 MB downloaded in 1.67 s (6.64 MB/s)
150 01:34:39.558249 end: 1.5.1 http-download (duration 00:00:02) [common]
152 01:34:39.559105 end: 1.5 download-retry (duration 00:00:02) [common]
153 01:34:39.559375 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 01:34:39.559644 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 01:34:55.360291 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/973280/extract-nfsrootfs-cqaq2udu
156 01:34:55.360887 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 01:34:55.361174 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 01:34:55.361778 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5
159 01:34:55.362206 makedir: /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin
160 01:34:55.362529 makedir: /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/tests
161 01:34:55.362837 makedir: /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/results
162 01:34:55.363157 Creating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin/lava-add-keys
163 01:34:55.363676 Creating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin/lava-add-sources
164 01:34:55.364220 Creating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin/lava-background-process-start
165 01:34:55.364731 Creating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin/lava-background-process-stop
166 01:34:55.365259 Creating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin/lava-common-functions
167 01:34:55.365761 Creating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin/lava-echo-ipv4
168 01:34:55.366266 Creating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin/lava-install-packages
169 01:34:55.366760 Creating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin/lava-installed-packages
170 01:34:55.367234 Creating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin/lava-os-build
171 01:34:55.367712 Creating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin/lava-probe-channel
172 01:34:55.368222 Creating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin/lava-probe-ip
173 01:34:55.368788 Creating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin/lava-target-ip
174 01:34:55.369286 Creating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin/lava-target-mac
175 01:34:55.369793 Creating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin/lava-target-storage
176 01:34:55.370468 Creating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin/lava-test-case
177 01:34:55.371131 Creating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin/lava-test-event
178 01:34:55.371808 Creating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin/lava-test-feedback
179 01:34:55.372988 Creating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin/lava-test-raise
180 01:34:55.373603 Creating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin/lava-test-reference
181 01:34:55.374142 Creating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin/lava-test-runner
182 01:34:55.374721 Creating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin/lava-test-set
183 01:34:55.375322 Creating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin/lava-test-shell
184 01:34:55.375937 Updating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin/lava-install-packages (oe)
185 01:34:55.376704 Updating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/bin/lava-installed-packages (oe)
186 01:34:55.377221 Creating /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/environment
187 01:34:55.377650 LAVA metadata
188 01:34:55.377946 - LAVA_JOB_ID=973280
189 01:34:55.378177 - LAVA_DISPATCHER_IP=192.168.6.2
190 01:34:55.378585 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 01:34:55.379830 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 01:34:55.380280 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 01:34:55.380506 skipped lava-vland-overlay
194 01:34:55.380771 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 01:34:55.381051 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 01:34:55.381300 skipped lava-multinode-overlay
197 01:34:55.381562 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 01:34:55.381820 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 01:34:55.382095 Loading test definitions
200 01:34:55.382394 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 01:34:55.382623 Using /lava-973280 at stage 0
202 01:34:55.383950 uuid=973280_1.6.2.4.1 testdef=None
203 01:34:55.384402 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 01:34:55.384723 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 01:34:55.386803 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 01:34:55.387794 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 01:34:55.390929 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 01:34:55.391900 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 01:34:55.395020 runner path: /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 973280_1.6.2.4.1
212 01:34:55.395805 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 01:34:55.398164 Creating lava-test-runner.conf files
215 01:34:55.398393 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/973280/lava-overlay-p3bo2oz5/lava-973280/0 for stage 0
216 01:34:55.398958 - 0_v4l2-decoder-conformance-vp9
217 01:34:55.399391 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 01:34:55.399688 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 01:34:55.426030 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 01:34:55.426486 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 01:34:55.426746 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 01:34:55.427015 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 01:34:55.427283 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 01:34:56.270513 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 01:34:56.271181 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 01:34:56.271474 extracting modules file /var/lib/lava/dispatcher/tmp/973280/tftp-deploy-ienrcya0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/973280/extract-nfsrootfs-cqaq2udu
227 01:34:57.816000 extracting modules file /var/lib/lava/dispatcher/tmp/973280/tftp-deploy-ienrcya0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/973280/extract-overlay-ramdisk-0mvzcggn/ramdisk
228 01:34:59.203144 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 01:34:59.203632 start: 1.6.5 apply-overlay-tftp (timeout 00:09:07) [common]
230 01:34:59.203908 [common] Applying overlay to NFS
231 01:34:59.204167 [common] Applying overlay /var/lib/lava/dispatcher/tmp/973280/compress-overlay-xq3wlq1q/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/973280/extract-nfsrootfs-cqaq2udu
232 01:34:59.233612 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 01:34:59.234012 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 01:34:59.234280 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 01:34:59.234505 Converting downloaded kernel to a uImage
236 01:34:59.234811 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/973280/tftp-deploy-ienrcya0/kernel/Image /var/lib/lava/dispatcher/tmp/973280/tftp-deploy-ienrcya0/kernel/uImage
237 01:34:59.852590 output: Image Name:
238 01:34:59.853025 output: Created: Mon Nov 11 01:34:59 2024
239 01:34:59.853257 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 01:34:59.853471 output: Data Size: 45715968 Bytes = 44644.50 KiB = 43.60 MiB
241 01:34:59.853673 output: Load Address: 01080000
242 01:34:59.853878 output: Entry Point: 01080000
243 01:34:59.854084 output:
244 01:34:59.854424 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 01:34:59.854703 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 01:34:59.854978 start: 1.6.7 configure-preseed-file (timeout 00:09:06) [common]
247 01:34:59.855263 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 01:34:59.855529 start: 1.6.8 compress-ramdisk (timeout 00:09:06) [common]
249 01:34:59.855785 Building ramdisk /var/lib/lava/dispatcher/tmp/973280/extract-overlay-ramdisk-0mvzcggn/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/973280/extract-overlay-ramdisk-0mvzcggn/ramdisk
250 01:35:02.083042 >> 166831 blocks
251 01:35:09.813710 Adding RAMdisk u-boot header.
252 01:35:09.814428 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/973280/extract-overlay-ramdisk-0mvzcggn/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/973280/extract-overlay-ramdisk-0mvzcggn/ramdisk.cpio.gz.uboot
253 01:35:10.106269 output: Image Name:
254 01:35:10.106692 output: Created: Mon Nov 11 01:35:09 2024
255 01:35:10.106901 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 01:35:10.107106 output: Data Size: 23436585 Bytes = 22887.29 KiB = 22.35 MiB
257 01:35:10.107308 output: Load Address: 00000000
258 01:35:10.107505 output: Entry Point: 00000000
259 01:35:10.107701 output:
260 01:35:10.108591 rename /var/lib/lava/dispatcher/tmp/973280/extract-overlay-ramdisk-0mvzcggn/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/973280/tftp-deploy-ienrcya0/ramdisk/ramdisk.cpio.gz.uboot
261 01:35:10.109313 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 01:35:10.109852 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
263 01:35:10.110373 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:56) [common]
264 01:35:10.110825 No LXC device requested
265 01:35:10.111319 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 01:35:10.111825 start: 1.8 deploy-device-env (timeout 00:08:56) [common]
267 01:35:10.112360 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 01:35:10.112773 Checking files for TFTP limit of 4294967296 bytes.
269 01:35:10.115395 end: 1 tftp-deploy (duration 00:01:04) [common]
270 01:35:10.115947 start: 2 uboot-action (timeout 00:05:00) [common]
271 01:35:10.116513 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 01:35:10.117006 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 01:35:10.117501 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 01:35:10.118018 Using kernel file from prepare-kernel: 973280/tftp-deploy-ienrcya0/kernel/uImage
275 01:35:10.118636 substitutions:
276 01:35:10.119036 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 01:35:10.119430 - {DTB_ADDR}: 0x01070000
278 01:35:10.119821 - {DTB}: 973280/tftp-deploy-ienrcya0/dtb/meson-g12b-a311d-libretech-cc.dtb
279 01:35:10.120244 - {INITRD}: 973280/tftp-deploy-ienrcya0/ramdisk/ramdisk.cpio.gz.uboot
280 01:35:10.120637 - {KERNEL_ADDR}: 0x01080000
281 01:35:10.121026 - {KERNEL}: 973280/tftp-deploy-ienrcya0/kernel/uImage
282 01:35:10.121409 - {LAVA_MAC}: None
283 01:35:10.121830 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/973280/extract-nfsrootfs-cqaq2udu
284 01:35:10.122223 - {NFS_SERVER_IP}: 192.168.6.2
285 01:35:10.122607 - {PRESEED_CONFIG}: None
286 01:35:10.122991 - {PRESEED_LOCAL}: None
287 01:35:10.123374 - {RAMDISK_ADDR}: 0x08000000
288 01:35:10.123755 - {RAMDISK}: 973280/tftp-deploy-ienrcya0/ramdisk/ramdisk.cpio.gz.uboot
289 01:35:10.124169 - {ROOT_PART}: None
290 01:35:10.124554 - {ROOT}: None
291 01:35:10.124934 - {SERVER_IP}: 192.168.6.2
292 01:35:10.125314 - {TEE_ADDR}: 0x83000000
293 01:35:10.125691 - {TEE}: None
294 01:35:10.126069 Parsed boot commands:
295 01:35:10.126442 - setenv autoload no
296 01:35:10.126819 - setenv initrd_high 0xffffffff
297 01:35:10.127195 - setenv fdt_high 0xffffffff
298 01:35:10.127576 - dhcp
299 01:35:10.127955 - setenv serverip 192.168.6.2
300 01:35:10.128362 - tftpboot 0x01080000 973280/tftp-deploy-ienrcya0/kernel/uImage
301 01:35:10.128747 - tftpboot 0x08000000 973280/tftp-deploy-ienrcya0/ramdisk/ramdisk.cpio.gz.uboot
302 01:35:10.129127 - tftpboot 0x01070000 973280/tftp-deploy-ienrcya0/dtb/meson-g12b-a311d-libretech-cc.dtb
303 01:35:10.129508 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/973280/extract-nfsrootfs-cqaq2udu,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 01:35:10.129901 - bootm 0x01080000 0x08000000 0x01070000
305 01:35:10.130381 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 01:35:10.131819 start: 2.3 connect-device (timeout 00:05:00) [common]
308 01:35:10.132257 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 01:35:10.146931 Setting prompt string to ['lava-test: # ']
310 01:35:10.148410 end: 2.3 connect-device (duration 00:00:00) [common]
311 01:35:10.148998 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 01:35:10.149532 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 01:35:10.150050 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 01:35:10.151170 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 01:35:10.188307 >> OK - accepted request
316 01:35:10.190422 Returned 0 in 0 seconds
317 01:35:10.291504 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 01:35:10.293093 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 01:35:10.293646 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 01:35:10.294143 Setting prompt string to ['Hit any key to stop autoboot']
322 01:35:10.294601 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 01:35:10.296185 Trying 192.168.56.21...
324 01:35:10.296660 Connected to conserv1.
325 01:35:10.297078 Escape character is '^]'.
326 01:35:10.297494
327 01:35:10.297913 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 01:35:10.298326
329 01:35:21.496702 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 01:35:21.497320 bl2_stage_init 0x01
331 01:35:21.497726 bl2_stage_init 0x81
332 01:35:21.502285 hw id: 0x0000 - pwm id 0x01
333 01:35:21.502726 bl2_stage_init 0xc1
334 01:35:21.503115 bl2_stage_init 0x02
335 01:35:21.503499
336 01:35:21.507785 L0:00000000
337 01:35:21.508247 L1:20000703
338 01:35:21.508637 L2:00008067
339 01:35:21.509029 L3:14000000
340 01:35:21.513448 B2:00402000
341 01:35:21.513893 B1:e0f83180
342 01:35:21.514296
343 01:35:21.514689 TE: 58167
344 01:35:21.515077
345 01:35:21.518990 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 01:35:21.519401
347 01:35:21.519792 Board ID = 1
348 01:35:21.524618 Set A53 clk to 24M
349 01:35:21.525070 Set A73 clk to 24M
350 01:35:21.525459 Set clk81 to 24M
351 01:35:21.530284 A53 clk: 1200 MHz
352 01:35:21.530705 A73 clk: 1200 MHz
353 01:35:21.531089 CLK81: 166.6M
354 01:35:21.531469 smccc: 00012abd
355 01:35:21.535785 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 01:35:21.541400 board id: 1
357 01:35:21.547351 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 01:35:21.557934 fw parse done
359 01:35:21.563919 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 01:35:21.606527 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 01:35:21.617441 PIEI prepare done
362 01:35:21.617864 fastboot data load
363 01:35:21.618254 fastboot data verify
364 01:35:21.623143 verify result: 266
365 01:35:21.628687 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 01:35:21.629112 LPDDR4 probe
367 01:35:21.629515 ddr clk to 1584MHz
368 01:35:21.635749 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 01:35:21.672959
370 01:35:21.673396 dmc_version 0001
371 01:35:21.680500 Check phy result
372 01:35:21.686480 INFO : End of CA training
373 01:35:21.686903 INFO : End of initialization
374 01:35:21.692067 INFO : Training has run successfully!
375 01:35:21.692489 Check phy result
376 01:35:21.697668 INFO : End of initialization
377 01:35:21.698088 INFO : End of read enable training
378 01:35:21.703388 INFO : End of fine write leveling
379 01:35:21.708947 INFO : End of Write leveling coarse delay
380 01:35:21.709370 INFO : Training has run successfully!
381 01:35:21.709769 Check phy result
382 01:35:21.714541 INFO : End of initialization
383 01:35:21.714963 INFO : End of read dq deskew training
384 01:35:21.720066 INFO : End of MPR read delay center optimization
385 01:35:21.725653 INFO : End of write delay center optimization
386 01:35:21.731357 INFO : End of read delay center optimization
387 01:35:21.731782 INFO : End of max read latency training
388 01:35:21.736863 INFO : Training has run successfully!
389 01:35:21.737283 1D training succeed
390 01:35:21.746073 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 01:35:21.793664 Check phy result
392 01:35:21.794128 INFO : End of initialization
393 01:35:21.815590 INFO : End of 2D read delay Voltage center optimization
394 01:35:21.835751 INFO : End of 2D read delay Voltage center optimization
395 01:35:21.887715 INFO : End of 2D write delay Voltage center optimization
396 01:35:21.937039 INFO : End of 2D write delay Voltage center optimization
397 01:35:21.942613 INFO : Training has run successfully!
398 01:35:21.943043
399 01:35:21.943449 channel==0
400 01:35:21.948230 RxClkDly_Margin_A0==88 ps 9
401 01:35:21.948659 TxDqDly_Margin_A0==98 ps 10
402 01:35:21.953814 RxClkDly_Margin_A1==88 ps 9
403 01:35:21.954249 TxDqDly_Margin_A1==98 ps 10
404 01:35:21.954653 TrainedVREFDQ_A0==74
405 01:35:21.959410 TrainedVREFDQ_A1==74
406 01:35:21.959842 VrefDac_Margin_A0==25
407 01:35:21.960290 DeviceVref_Margin_A0==40
408 01:35:21.965134 VrefDac_Margin_A1==25
409 01:35:21.965562 DeviceVref_Margin_A1==40
410 01:35:21.965957
411 01:35:21.966349
412 01:35:21.970675 channel==1
413 01:35:21.971097 RxClkDly_Margin_A0==98 ps 10
414 01:35:21.971494 TxDqDly_Margin_A0==98 ps 10
415 01:35:21.976222 RxClkDly_Margin_A1==88 ps 9
416 01:35:21.976644 TxDqDly_Margin_A1==88 ps 9
417 01:35:21.981804 TrainedVREFDQ_A0==77
418 01:35:21.982225 TrainedVREFDQ_A1==77
419 01:35:21.982625 VrefDac_Margin_A0==22
420 01:35:21.987415 DeviceVref_Margin_A0==37
421 01:35:21.987832 VrefDac_Margin_A1==24
422 01:35:21.993005 DeviceVref_Margin_A1==37
423 01:35:21.993423
424 01:35:21.993819 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 01:35:21.994209
426 01:35:22.026589 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 01:35:22.027107 2D training succeed
428 01:35:22.032231 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 01:35:22.037872 auto size-- 65535DDR cs0 size: 2048MB
430 01:35:22.038311 DDR cs1 size: 2048MB
431 01:35:22.043430 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 01:35:22.043853 cs0 DataBus test pass
433 01:35:22.049015 cs1 DataBus test pass
434 01:35:22.049436 cs0 AddrBus test pass
435 01:35:22.049845 cs1 AddrBus test pass
436 01:35:22.050242
437 01:35:22.054612 100bdlr_step_size ps== 420
438 01:35:22.055047 result report
439 01:35:22.060223 boot times 0Enable ddr reg access
440 01:35:22.065625 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 01:35:22.079066 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 01:35:22.652802 0.0;M3 CHK:0;cm4_sp_mode 0
443 01:35:22.653420 MVN_1=0x00000000
444 01:35:22.658273 MVN_2=0x00000000
445 01:35:22.664022 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 01:35:22.664527 OPS=0x10
447 01:35:22.664941 ring efuse init
448 01:35:22.665339 chipver efuse init
449 01:35:22.669597 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 01:35:22.675158 [0.018961 Inits done]
451 01:35:22.675581 secure task start!
452 01:35:22.675975 high task start!
453 01:35:22.679750 low task start!
454 01:35:22.680204 run into bl31
455 01:35:22.686477 NOTICE: BL31: v1.3(release):4fc40b1
456 01:35:22.694204 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 01:35:22.694637 NOTICE: BL31: G12A normal boot!
458 01:35:22.720077 NOTICE: BL31: BL33 decompress pass
459 01:35:22.725779 ERROR: Error initializing runtime service opteed_fast
460 01:35:23.958811
461 01:35:23.959385
462 01:35:23.967051 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 01:35:23.967501
464 01:35:23.967927 Model: Libre Computer AML-A311D-CC Alta
465 01:35:24.175559 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 01:35:24.198878 DRAM: 2 GiB (effective 3.8 GiB)
467 01:35:24.341849 Core: 408 devices, 31 uclasses, devicetree: separate
468 01:35:24.347751 WDT: Not starting watchdog@f0d0
469 01:35:24.380018 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 01:35:24.392446 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 01:35:24.397417 ** Bad device specification mmc 0 **
472 01:35:24.407765 Card did not respond to voltage select! : -110
473 01:35:24.415426 ** Bad device specification mmc 0 **
474 01:35:24.415876 Couldn't find partition mmc 0
475 01:35:24.423752 Card did not respond to voltage select! : -110
476 01:35:24.429280 ** Bad device specification mmc 0 **
477 01:35:24.429710 Couldn't find partition mmc 0
478 01:35:24.434310 Error: could not access storage.
479 01:35:25.697427 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 01:35:25.698024 bl2_stage_init 0x01
481 01:35:25.698442 bl2_stage_init 0x81
482 01:35:25.703016 hw id: 0x0000 - pwm id 0x01
483 01:35:25.703456 bl2_stage_init 0xc1
484 01:35:25.703858 bl2_stage_init 0x02
485 01:35:25.704309
486 01:35:25.708573 L0:00000000
487 01:35:25.709004 L1:20000703
488 01:35:25.709400 L2:00008067
489 01:35:25.709787 L3:14000000
490 01:35:25.714211 B2:00402000
491 01:35:25.714641 B1:e0f83180
492 01:35:25.715037
493 01:35:25.715429 TE: 58167
494 01:35:25.715819
495 01:35:25.719734 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 01:35:25.720197
497 01:35:25.720605 Board ID = 1
498 01:35:25.725307 Set A53 clk to 24M
499 01:35:25.725738 Set A73 clk to 24M
500 01:35:25.726133 Set clk81 to 24M
501 01:35:25.730931 A53 clk: 1200 MHz
502 01:35:25.731355 A73 clk: 1200 MHz
503 01:35:25.731753 CLK81: 166.6M
504 01:35:25.732180 smccc: 00012abe
505 01:35:25.736487 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 01:35:25.742083 board id: 1
507 01:35:25.748056 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 01:35:25.758609 fw parse done
509 01:35:25.764591 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 01:35:25.807270 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 01:35:25.818074 PIEI prepare done
512 01:35:25.818505 fastboot data load
513 01:35:25.818906 fastboot data verify
514 01:35:25.823774 verify result: 266
515 01:35:25.829459 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 01:35:25.829887 LPDDR4 probe
517 01:35:25.830289 ddr clk to 1584MHz
518 01:35:25.837488 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 01:35:25.874597
520 01:35:25.875049 dmc_version 0001
521 01:35:25.881326 Check phy result
522 01:35:25.887139 INFO : End of CA training
523 01:35:25.887561 INFO : End of initialization
524 01:35:25.892723 INFO : Training has run successfully!
525 01:35:25.893147 Check phy result
526 01:35:25.898371 INFO : End of initialization
527 01:35:25.898791 INFO : End of read enable training
528 01:35:25.904024 INFO : End of fine write leveling
529 01:35:25.909534 INFO : End of Write leveling coarse delay
530 01:35:25.909973 INFO : Training has run successfully!
531 01:35:25.910371 Check phy result
532 01:35:25.915115 INFO : End of initialization
533 01:35:25.915550 INFO : End of read dq deskew training
534 01:35:25.920705 INFO : End of MPR read delay center optimization
535 01:35:25.926320 INFO : End of write delay center optimization
536 01:35:25.932016 INFO : End of read delay center optimization
537 01:35:25.932444 INFO : End of max read latency training
538 01:35:25.937566 INFO : Training has run successfully!
539 01:35:25.938010 1D training succeed
540 01:35:25.946739 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 01:35:25.994405 Check phy result
542 01:35:25.994876 INFO : End of initialization
543 01:35:26.016162 INFO : End of 2D read delay Voltage center optimization
544 01:35:26.036355 INFO : End of 2D read delay Voltage center optimization
545 01:35:26.088434 INFO : End of 2D write delay Voltage center optimization
546 01:35:26.137842 INFO : End of 2D write delay Voltage center optimization
547 01:35:26.143376 INFO : Training has run successfully!
548 01:35:26.143830
549 01:35:26.144297 channel==0
550 01:35:26.148986 RxClkDly_Margin_A0==88 ps 9
551 01:35:26.149445 TxDqDly_Margin_A0==98 ps 10
552 01:35:26.152333 RxClkDly_Margin_A1==88 ps 9
553 01:35:26.152784 TxDqDly_Margin_A1==88 ps 9
554 01:35:26.157927 TrainedVREFDQ_A0==74
555 01:35:26.158374 TrainedVREFDQ_A1==74
556 01:35:26.158800 VrefDac_Margin_A0==25
557 01:35:26.163452 DeviceVref_Margin_A0==40
558 01:35:26.164114 VrefDac_Margin_A1==25
559 01:35:26.169215 DeviceVref_Margin_A1==40
560 01:35:26.169827
561 01:35:26.170378
562 01:35:26.170908 channel==1
563 01:35:26.171432 RxClkDly_Margin_A0==88 ps 9
564 01:35:26.172549 TxDqDly_Margin_A0==98 ps 10
565 01:35:26.178152 RxClkDly_Margin_A1==98 ps 10
566 01:35:26.178762 TxDqDly_Margin_A1==88 ps 9
567 01:35:26.179349 TrainedVREFDQ_A0==77
568 01:35:26.183857 TrainedVREFDQ_A1==77
569 01:35:26.184532 VrefDac_Margin_A0==22
570 01:35:26.189388 DeviceVref_Margin_A0==37
571 01:35:26.190009 VrefDac_Margin_A1==22
572 01:35:26.190534 DeviceVref_Margin_A1==37
573 01:35:26.191050
574 01:35:26.195014 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 01:35:26.195621
576 01:35:26.228591 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
577 01:35:26.229256 2D training succeed
578 01:35:26.234220 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 01:35:26.239619 auto size-- 65535DDR cs0 size: 2048MB
580 01:35:26.240238 DDR cs1 size: 2048MB
581 01:35:26.245253 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 01:35:26.245810 cs0 DataBus test pass
583 01:35:26.246342 cs1 DataBus test pass
584 01:35:26.250896 cs0 AddrBus test pass
585 01:35:26.251470 cs1 AddrBus test pass
586 01:35:26.252034
587 01:35:26.256457 100bdlr_step_size ps== 420
588 01:35:26.257062 result report
589 01:35:26.257599 boot times 0Enable ddr reg access
590 01:35:26.266079 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 01:35:26.279531 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 01:35:26.852668 0.0;M3 CHK:0;cm4_sp_mode 0
593 01:35:26.853481 MVN_1=0x00000000
594 01:35:26.858104 MVN_2=0x00000000
595 01:35:26.863859 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 01:35:26.864572 OPS=0x10
597 01:35:26.865151 ring efuse init
598 01:35:26.865662 chipver efuse init
599 01:35:26.869423 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 01:35:26.875033 [0.018960 Inits done]
601 01:35:26.875609 secure task start!
602 01:35:26.876164 high task start!
603 01:35:26.879607 low task start!
604 01:35:26.880200 run into bl31
605 01:35:26.886312 NOTICE: BL31: v1.3(release):4fc40b1
606 01:35:26.894133 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 01:35:26.894702 NOTICE: BL31: G12A normal boot!
608 01:35:26.919466 NOTICE: BL31: BL33 decompress pass
609 01:35:26.925111 ERROR: Error initializing runtime service opteed_fast
610 01:35:28.157991
611 01:35:28.158808
612 01:35:28.166591 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 01:35:28.167352
614 01:35:28.167928 Model: Libre Computer AML-A311D-CC Alta
615 01:35:28.374835 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 01:35:28.398226 DRAM: 2 GiB (effective 3.8 GiB)
617 01:35:28.541285 Core: 408 devices, 31 uclasses, devicetree: separate
618 01:35:28.547028 WDT: Not starting watchdog@f0d0
619 01:35:28.579318 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 01:35:28.591765 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 01:35:28.596745 ** Bad device specification mmc 0 **
622 01:35:28.607049 Card did not respond to voltage select! : -110
623 01:35:28.614707 ** Bad device specification mmc 0 **
624 01:35:28.615297 Couldn't find partition mmc 0
625 01:35:28.623048 Card did not respond to voltage select! : -110
626 01:35:28.628542 ** Bad device specification mmc 0 **
627 01:35:28.629136 Couldn't find partition mmc 0
628 01:35:28.633597 Error: could not access storage.
629 01:35:28.976250 Net: eth0: ethernet@ff3f0000
630 01:35:28.976954 starting USB...
631 01:35:29.228965 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 01:35:29.229698 Starting the controller
633 01:35:29.235015 USB XHCI 1.10
634 01:35:30.945860 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 01:35:30.946685 bl2_stage_init 0x01
636 01:35:30.947249 bl2_stage_init 0x81
637 01:35:30.951391 hw id: 0x0000 - pwm id 0x01
638 01:35:30.951959 bl2_stage_init 0xc1
639 01:35:30.952525 bl2_stage_init 0x02
640 01:35:30.953041
641 01:35:30.956994 L0:00000000
642 01:35:30.957568 L1:20000703
643 01:35:30.958087 L2:00008067
644 01:35:30.958597 L3:14000000
645 01:35:30.962599 B2:00402000
646 01:35:30.963160 B1:e0f83180
647 01:35:30.963683
648 01:35:30.964258 TE: 58167
649 01:35:30.964771
650 01:35:30.968193 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 01:35:30.968750
652 01:35:30.969270 Board ID = 1
653 01:35:30.973802 Set A53 clk to 24M
654 01:35:30.974368 Set A73 clk to 24M
655 01:35:30.974890 Set clk81 to 24M
656 01:35:30.979381 A53 clk: 1200 MHz
657 01:35:30.979937 A73 clk: 1200 MHz
658 01:35:30.980492 CLK81: 166.6M
659 01:35:30.981003 smccc: 00012abe
660 01:35:30.985001 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 01:35:30.990577 board id: 1
662 01:35:30.996472 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 01:35:31.007203 fw parse done
664 01:35:31.013101 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 01:35:31.055751 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 01:35:31.066644 PIEI prepare done
667 01:35:31.067236 fastboot data load
668 01:35:31.067761 fastboot data verify
669 01:35:31.072314 verify result: 266
670 01:35:31.077914 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 01:35:31.078492 LPDDR4 probe
672 01:35:31.079016 ddr clk to 1584MHz
673 01:35:31.085885 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 01:35:31.123177
675 01:35:31.123777 dmc_version 0001
676 01:35:31.129835 Check phy result
677 01:35:31.135694 INFO : End of CA training
678 01:35:31.136271 INFO : End of initialization
679 01:35:31.141279 INFO : Training has run successfully!
680 01:35:31.141839 Check phy result
681 01:35:31.146877 INFO : End of initialization
682 01:35:31.147434 INFO : End of read enable training
683 01:35:31.152478 INFO : End of fine write leveling
684 01:35:31.158081 INFO : End of Write leveling coarse delay
685 01:35:31.158633 INFO : Training has run successfully!
686 01:35:31.159151 Check phy result
687 01:35:31.163671 INFO : End of initialization
688 01:35:31.164243 INFO : End of read dq deskew training
689 01:35:31.169272 INFO : End of MPR read delay center optimization
690 01:35:31.174871 INFO : End of write delay center optimization
691 01:35:31.180488 INFO : End of read delay center optimization
692 01:35:31.181080 INFO : End of max read latency training
693 01:35:31.186080 INFO : Training has run successfully!
694 01:35:31.186641 1D training succeed
695 01:35:31.195237 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 01:35:31.243148 Check phy result
697 01:35:31.243807 INFO : End of initialization
698 01:35:31.264711 INFO : End of 2D read delay Voltage center optimization
699 01:35:31.284711 INFO : End of 2D read delay Voltage center optimization
700 01:35:31.336759 INFO : End of 2D write delay Voltage center optimization
701 01:35:31.385950 INFO : End of 2D write delay Voltage center optimization
702 01:35:31.391402 INFO : Training has run successfully!
703 01:35:31.392018
704 01:35:31.392685 channel==0
705 01:35:31.396970 RxClkDly_Margin_A0==88 ps 9
706 01:35:31.397423 TxDqDly_Margin_A0==98 ps 10
707 01:35:31.400271 RxClkDly_Margin_A1==88 ps 9
708 01:35:31.400720 TxDqDly_Margin_A1==88 ps 9
709 01:35:31.405898 TrainedVREFDQ_A0==74
710 01:35:31.406348 TrainedVREFDQ_A1==74
711 01:35:31.406762 VrefDac_Margin_A0==25
712 01:35:31.411444 DeviceVref_Margin_A0==40
713 01:35:31.411894 VrefDac_Margin_A1==25
714 01:35:31.417029 DeviceVref_Margin_A1==40
715 01:35:31.417584
716 01:35:31.418003
717 01:35:31.418407 channel==1
718 01:35:31.418804 RxClkDly_Margin_A0==98 ps 10
719 01:35:31.422623 TxDqDly_Margin_A0==98 ps 10
720 01:35:31.423085 RxClkDly_Margin_A1==88 ps 9
721 01:35:31.428218 TxDqDly_Margin_A1==88 ps 9
722 01:35:31.428686 TrainedVREFDQ_A0==77
723 01:35:31.429105 TrainedVREFDQ_A1==77
724 01:35:31.433832 VrefDac_Margin_A0==22
725 01:35:31.434289 DeviceVref_Margin_A0==37
726 01:35:31.439396 VrefDac_Margin_A1==24
727 01:35:31.439844 DeviceVref_Margin_A1==37
728 01:35:31.440285
729 01:35:31.444937 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 01:35:31.445389
731 01:35:31.472946 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000018 dram_vref_reg_value 0x 00000060
732 01:35:31.478544 2D training succeed
733 01:35:31.484176 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 01:35:31.484639 auto size-- 65535DDR cs0 size: 2048MB
735 01:35:31.489773 DDR cs1 size: 2048MB
736 01:35:31.490230 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 01:35:31.495304 cs0 DataBus test pass
738 01:35:31.495756 cs1 DataBus test pass
739 01:35:31.496207 cs0 AddrBus test pass
740 01:35:31.500940 cs1 AddrBus test pass
741 01:35:31.501318
742 01:35:31.501576 100bdlr_step_size ps== 420
743 01:35:31.501811 result report
744 01:35:31.506572 boot times 0Enable ddr reg access
745 01:35:31.514201 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 01:35:31.527655 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 01:35:32.099839 0.0;M3 CHK:0;cm4_sp_mode 0
748 01:35:32.100514 MVN_1=0x00000000
749 01:35:32.105219 MVN_2=0x00000000
750 01:35:32.110994 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 01:35:32.111544 OPS=0x10
752 01:35:32.111946 ring efuse init
753 01:35:32.112375 chipver efuse init
754 01:35:32.116576 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 01:35:32.122135 [0.018960 Inits done]
756 01:35:32.122569 secure task start!
757 01:35:32.122960 high task start!
758 01:35:32.126786 low task start!
759 01:35:32.127214 run into bl31
760 01:35:32.133348 NOTICE: BL31: v1.3(release):4fc40b1
761 01:35:32.141166 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 01:35:32.141605 NOTICE: BL31: G12A normal boot!
763 01:35:32.166496 NOTICE: BL31: BL33 decompress pass
764 01:35:32.172190 ERROR: Error initializing runtime service opteed_fast
765 01:35:33.405480
766 01:35:33.406202
767 01:35:33.413913 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 01:35:33.414618
769 01:35:33.415134 Model: Libre Computer AML-A311D-CC Alta
770 01:35:33.622063 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 01:35:33.645419 DRAM: 2 GiB (effective 3.8 GiB)
772 01:35:33.788249 Core: 408 devices, 31 uclasses, devicetree: separate
773 01:35:33.794205 WDT: Not starting watchdog@f0d0
774 01:35:33.826479 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 01:35:33.838896 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 01:35:33.843925 ** Bad device specification mmc 0 **
777 01:35:33.854251 Card did not respond to voltage select! : -110
778 01:35:33.861829 ** Bad device specification mmc 0 **
779 01:35:33.862119 Couldn't find partition mmc 0
780 01:35:33.870222 Card did not respond to voltage select! : -110
781 01:35:33.875689 ** Bad device specification mmc 0 **
782 01:35:33.876128 Couldn't find partition mmc 0
783 01:35:33.880793 Error: could not access storage.
784 01:35:34.223500 Net: eth0: ethernet@ff3f0000
785 01:35:34.224209 starting USB...
786 01:35:34.475413 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 01:35:34.476133 Starting the controller
788 01:35:34.482247 USB XHCI 1.10
789 01:35:36.646193 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 01:35:36.646864 bl2_stage_init 0x01
791 01:35:36.647338 bl2_stage_init 0x81
792 01:35:36.651772 hw id: 0x0000 - pwm id 0x01
793 01:35:36.652327 bl2_stage_init 0xc1
794 01:35:36.652796 bl2_stage_init 0x02
795 01:35:36.653247
796 01:35:36.657275 L0:00000000
797 01:35:36.657790 L1:20000703
798 01:35:36.658251 L2:00008067
799 01:35:36.658700 L3:14000000
800 01:35:36.660417 B2:00402000
801 01:35:36.660923 B1:e0f83180
802 01:35:36.661380
803 01:35:36.661831 TE: 58150
804 01:35:36.662278
805 01:35:36.671641 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 01:35:36.672187
807 01:35:36.672649 Board ID = 1
808 01:35:36.673097 Set A53 clk to 24M
809 01:35:36.673543 Set A73 clk to 24M
810 01:35:36.677249 Set clk81 to 24M
811 01:35:36.677757 A53 clk: 1200 MHz
812 01:35:36.678216 A73 clk: 1200 MHz
813 01:35:36.680598 CLK81: 166.6M
814 01:35:36.681104 smccc: 00012aac
815 01:35:36.686191 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 01:35:36.691700 board id: 1
817 01:35:36.696847 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 01:35:36.707435 fw parse done
819 01:35:36.713522 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 01:35:36.755892 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 01:35:36.766893 PIEI prepare done
822 01:35:36.767410 fastboot data load
823 01:35:36.767870 fastboot data verify
824 01:35:36.772577 verify result: 266
825 01:35:36.778080 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 01:35:36.778594 LPDDR4 probe
827 01:35:36.779047 ddr clk to 1584MHz
828 01:35:36.785998 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 01:35:36.823293
830 01:35:36.823820 dmc_version 0001
831 01:35:36.830043 Check phy result
832 01:35:36.835867 INFO : End of CA training
833 01:35:36.836406 INFO : End of initialization
834 01:35:36.841566 INFO : Training has run successfully!
835 01:35:36.842072 Check phy result
836 01:35:36.847068 INFO : End of initialization
837 01:35:36.847576 INFO : End of read enable training
838 01:35:36.852696 INFO : End of fine write leveling
839 01:35:36.858295 INFO : End of Write leveling coarse delay
840 01:35:36.858809 INFO : Training has run successfully!
841 01:35:36.859267 Check phy result
842 01:35:36.863854 INFO : End of initialization
843 01:35:36.864388 INFO : End of read dq deskew training
844 01:35:36.869558 INFO : End of MPR read delay center optimization
845 01:35:36.875075 INFO : End of write delay center optimization
846 01:35:36.880685 INFO : End of read delay center optimization
847 01:35:36.881195 INFO : End of max read latency training
848 01:35:36.886266 INFO : Training has run successfully!
849 01:35:36.886770 1D training succeed
850 01:35:36.895455 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 01:35:36.943086 Check phy result
852 01:35:36.943634 INFO : End of initialization
853 01:35:36.964803 INFO : End of 2D read delay Voltage center optimization
854 01:35:36.985014 INFO : End of 2D read delay Voltage center optimization
855 01:35:37.037103 INFO : End of 2D write delay Voltage center optimization
856 01:35:37.086459 INFO : End of 2D write delay Voltage center optimization
857 01:35:37.092038 INFO : Training has run successfully!
858 01:35:37.092558
859 01:35:37.093018 channel==0
860 01:35:37.097607 RxClkDly_Margin_A0==88 ps 9
861 01:35:37.098120 TxDqDly_Margin_A0==98 ps 10
862 01:35:37.103192 RxClkDly_Margin_A1==88 ps 9
863 01:35:37.103705 TxDqDly_Margin_A1==88 ps 9
864 01:35:37.104229 TrainedVREFDQ_A0==74
865 01:35:37.108812 TrainedVREFDQ_A1==74
866 01:35:37.109346 VrefDac_Margin_A0==25
867 01:35:37.109803 DeviceVref_Margin_A0==40
868 01:35:37.114388 VrefDac_Margin_A1==25
869 01:35:37.114913 DeviceVref_Margin_A1==40
870 01:35:37.115347
871 01:35:37.115781
872 01:35:37.116254 channel==1
873 01:35:37.119959 RxClkDly_Margin_A0==98 ps 10
874 01:35:37.120491 TxDqDly_Margin_A0==98 ps 10
875 01:35:37.125579 RxClkDly_Margin_A1==88 ps 9
876 01:35:37.126077 TxDqDly_Margin_A1==88 ps 9
877 01:35:37.131234 TrainedVREFDQ_A0==77
878 01:35:37.131786 TrainedVREFDQ_A1==77
879 01:35:37.132280 VrefDac_Margin_A0==22
880 01:35:37.136773 DeviceVref_Margin_A0==37
881 01:35:37.137289 VrefDac_Margin_A1==24
882 01:35:37.142393 DeviceVref_Margin_A1==37
883 01:35:37.142903
884 01:35:37.143347 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 01:35:37.143784
886 01:35:37.175933 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 0000005f
887 01:35:37.176512 2D training succeed
888 01:35:37.181586 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 01:35:37.187173 auto size-- 65535DDR cs0 size: 2048MB
890 01:35:37.187681 DDR cs1 size: 2048MB
891 01:35:37.192773 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 01:35:37.193277 cs0 DataBus test pass
893 01:35:37.198377 cs1 DataBus test pass
894 01:35:37.198872 cs0 AddrBus test pass
895 01:35:37.199314 cs1 AddrBus test pass
896 01:35:37.199745
897 01:35:37.203972 100bdlr_step_size ps== 420
898 01:35:37.204512 result report
899 01:35:37.209629 boot times 0Enable ddr reg access
900 01:35:37.214853 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 01:35:37.228298 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 01:35:37.802117 0.0;M3 CHK:0;cm4_sp_mode 0
903 01:35:37.802812 MVN_1=0x00000000
904 01:35:37.807595 MVN_2=0x00000000
905 01:35:37.813323 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 01:35:37.813846 OPS=0x10
907 01:35:37.814312 ring efuse init
908 01:35:37.814767 chipver efuse init
909 01:35:37.818879 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 01:35:37.824545 [0.018960 Inits done]
911 01:35:37.825064 secure task start!
912 01:35:37.825524 high task start!
913 01:35:37.829089 low task start!
914 01:35:37.829605 run into bl31
915 01:35:37.835783 NOTICE: BL31: v1.3(release):4fc40b1
916 01:35:37.843550 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 01:35:37.844103 NOTICE: BL31: G12A normal boot!
918 01:35:37.869012 NOTICE: BL31: BL33 decompress pass
919 01:35:37.874661 ERROR: Error initializing runtime service opteed_fast
920 01:35:39.107555
921 01:35:39.108280
922 01:35:39.116007 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 01:35:39.116542
924 01:35:39.117014 Model: Libre Computer AML-A311D-CC Alta
925 01:35:39.324332 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 01:35:39.347714 DRAM: 2 GiB (effective 3.8 GiB)
927 01:35:39.490745 Core: 408 devices, 31 uclasses, devicetree: separate
928 01:35:39.496569 WDT: Not starting watchdog@f0d0
929 01:35:39.528862 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 01:35:39.541310 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 01:35:39.546333 ** Bad device specification mmc 0 **
932 01:35:39.556619 Card did not respond to voltage select! : -110
933 01:35:39.564355 ** Bad device specification mmc 0 **
934 01:35:39.564917 Couldn't find partition mmc 0
935 01:35:39.572617 Card did not respond to voltage select! : -110
936 01:35:39.578046 ** Bad device specification mmc 0 **
937 01:35:39.578587 Couldn't find partition mmc 0
938 01:35:39.583175 Error: could not access storage.
939 01:35:39.926633 Net: eth0: ethernet@ff3f0000
940 01:35:39.927262 starting USB...
941 01:35:40.178551 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 01:35:40.179180 Starting the controller
943 01:35:40.185458 USB XHCI 1.10
944 01:35:42.046263 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 01:35:42.046945 bl2_stage_init 0x01
946 01:35:42.047421 bl2_stage_init 0x81
947 01:35:42.051687 hw id: 0x0000 - pwm id 0x01
948 01:35:42.052259 bl2_stage_init 0xc1
949 01:35:42.052723 bl2_stage_init 0x02
950 01:35:42.053175
951 01:35:42.057454 L0:00000000
952 01:35:42.057985 L1:20000703
953 01:35:42.058446 L2:00008067
954 01:35:42.058894 L3:14000000
955 01:35:42.060406 B2:00402000
956 01:35:42.060917 B1:e0f83180
957 01:35:42.061369
958 01:35:42.061821 TE: 58159
959 01:35:42.062272
960 01:35:42.071358 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 01:35:42.071873
962 01:35:42.072383 Board ID = 1
963 01:35:42.072836 Set A53 clk to 24M
964 01:35:42.073281 Set A73 clk to 24M
965 01:35:42.077113 Set clk81 to 24M
966 01:35:42.077621 A53 clk: 1200 MHz
967 01:35:42.078074 A73 clk: 1200 MHz
968 01:35:42.082643 CLK81: 166.6M
969 01:35:42.083150 smccc: 00012ab5
970 01:35:42.088365 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 01:35:42.088876 board id: 1
972 01:35:42.096826 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 01:35:42.107449 fw parse done
974 01:35:42.113805 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 01:35:42.156278 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 01:35:42.166851 PIEI prepare done
977 01:35:42.167344 fastboot data load
978 01:35:42.167781 fastboot data verify
979 01:35:42.172450 verify result: 266
980 01:35:42.178039 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 01:35:42.178533 LPDDR4 probe
982 01:35:42.178963 ddr clk to 1584MHz
983 01:35:42.186454 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 01:35:42.223282
985 01:35:42.223776 dmc_version 0001
986 01:35:42.229948 Check phy result
987 01:35:42.235825 INFO : End of CA training
988 01:35:42.236349 INFO : End of initialization
989 01:35:42.241460 INFO : Training has run successfully!
990 01:35:42.241952 Check phy result
991 01:35:42.247090 INFO : End of initialization
992 01:35:42.247611 INFO : End of read enable training
993 01:35:42.252614 INFO : End of fine write leveling
994 01:35:42.258333 INFO : End of Write leveling coarse delay
995 01:35:42.258851 INFO : Training has run successfully!
996 01:35:42.259309 Check phy result
997 01:35:42.263833 INFO : End of initialization
998 01:35:42.264366 INFO : End of read dq deskew training
999 01:35:42.269455 INFO : End of MPR read delay center optimization
1000 01:35:42.275029 INFO : End of write delay center optimization
1001 01:35:42.280681 INFO : End of read delay center optimization
1002 01:35:42.281182 INFO : End of max read latency training
1003 01:35:42.286434 INFO : Training has run successfully!
1004 01:35:42.286942 1D training succeed
1005 01:35:42.295370 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 01:35:42.342979 Check phy result
1007 01:35:42.343497 INFO : End of initialization
1008 01:35:42.364635 INFO : End of 2D read delay Voltage center optimization
1009 01:35:42.384737 INFO : End of 2D read delay Voltage center optimization
1010 01:35:42.436643 INFO : End of 2D write delay Voltage center optimization
1011 01:35:42.485882 INFO : End of 2D write delay Voltage center optimization
1012 01:35:42.491430 INFO : Training has run successfully!
1013 01:35:42.491945
1014 01:35:42.492453 channel==0
1015 01:35:42.497022 RxClkDly_Margin_A0==88 ps 9
1016 01:35:42.497533 TxDqDly_Margin_A0==98 ps 10
1017 01:35:42.500430 RxClkDly_Margin_A1==88 ps 9
1018 01:35:42.500980 TxDqDly_Margin_A1==98 ps 10
1019 01:35:42.505894 TrainedVREFDQ_A0==74
1020 01:35:42.506427 TrainedVREFDQ_A1==74
1021 01:35:42.511510 VrefDac_Margin_A0==24
1022 01:35:42.512073 DeviceVref_Margin_A0==40
1023 01:35:42.512539 VrefDac_Margin_A1==25
1024 01:35:42.517098 DeviceVref_Margin_A1==40
1025 01:35:42.517619
1026 01:35:42.518078
1027 01:35:42.518529 channel==1
1028 01:35:42.518970 RxClkDly_Margin_A0==98 ps 10
1029 01:35:42.522693 TxDqDly_Margin_A0==88 ps 9
1030 01:35:42.523224 RxClkDly_Margin_A1==98 ps 10
1031 01:35:42.528359 TxDqDly_Margin_A1==88 ps 9
1032 01:35:42.528890 TrainedVREFDQ_A0==76
1033 01:35:42.529357 TrainedVREFDQ_A1==77
1034 01:35:42.533903 VrefDac_Margin_A0==22
1035 01:35:42.534430 DeviceVref_Margin_A0==38
1036 01:35:42.539500 VrefDac_Margin_A1==22
1037 01:35:42.540056 DeviceVref_Margin_A1==37
1038 01:35:42.540522
1039 01:35:42.545063 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 01:35:42.545595
1041 01:35:42.573035 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1042 01:35:42.578686 2D training succeed
1043 01:35:42.584362 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 01:35:42.584873 auto size-- 65535DDR cs0 size: 2048MB
1045 01:35:42.589865 DDR cs1 size: 2048MB
1046 01:35:42.590373 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 01:35:42.595479 cs0 DataBus test pass
1048 01:35:42.596096 cs1 DataBus test pass
1049 01:35:42.596676 cs0 AddrBus test pass
1050 01:35:42.601060 cs1 AddrBus test pass
1051 01:35:42.601514
1052 01:35:42.601938 100bdlr_step_size ps== 420
1053 01:35:42.602359 result report
1054 01:35:42.606556 boot times 0Enable ddr reg access
1055 01:35:42.614356 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 01:35:42.627738 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 01:35:43.199860 0.0;M3 CHK:0;cm4_sp_mode 0
1058 01:35:43.200509 MVN_1=0x00000000
1059 01:35:43.205274 MVN_2=0x00000000
1060 01:35:43.210985 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 01:35:43.211452 OPS=0x10
1062 01:35:43.211881 ring efuse init
1063 01:35:43.212353 chipver efuse init
1064 01:35:43.216582 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 01:35:43.222265 [0.018961 Inits done]
1066 01:35:43.222723 secure task start!
1067 01:35:43.223142 high task start!
1068 01:35:43.226776 low task start!
1069 01:35:43.227226 run into bl31
1070 01:35:43.233357 NOTICE: BL31: v1.3(release):4fc40b1
1071 01:35:43.241232 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 01:35:43.241686 NOTICE: BL31: G12A normal boot!
1073 01:35:43.266562 NOTICE: BL31: BL33 decompress pass
1074 01:35:43.272228 ERROR: Error initializing runtime service opteed_fast
1075 01:35:44.505280
1076 01:35:44.505921
1077 01:35:44.513579 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 01:35:44.514060
1079 01:35:44.514493 Model: Libre Computer AML-A311D-CC Alta
1080 01:35:44.721918 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 01:35:44.745278 DRAM: 2 GiB (effective 3.8 GiB)
1082 01:35:44.888429 Core: 408 devices, 31 uclasses, devicetree: separate
1083 01:35:44.894156 WDT: Not starting watchdog@f0d0
1084 01:35:44.926537 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 01:35:44.938902 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 01:35:44.943849 ** Bad device specification mmc 0 **
1087 01:35:44.954191 Card did not respond to voltage select! : -110
1088 01:35:44.961837 ** Bad device specification mmc 0 **
1089 01:35:44.962294 Couldn't find partition mmc 0
1090 01:35:44.970295 Card did not respond to voltage select! : -110
1091 01:35:44.975712 ** Bad device specification mmc 0 **
1092 01:35:44.976224 Couldn't find partition mmc 0
1093 01:35:44.980763 Error: could not access storage.
1094 01:35:45.324304 Net: eth0: ethernet@ff3f0000
1095 01:35:45.324899 starting USB...
1096 01:35:45.576215 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 01:35:45.576878 Starting the controller
1098 01:35:45.583186 USB XHCI 1.10
1099 01:35:47.139412 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 01:35:47.147931 scanning usb for storage devices... 0 Storage Device(s) found
1102 01:35:47.199277 Hit any key to stop autoboot: 1
1103 01:35:47.200040 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 01:35:47.200490 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 01:35:47.200833 Setting prompt string to ['=>']
1106 01:35:47.201175 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 01:35:47.215415 0
1108 01:35:47.216696 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 01:35:47.217100 Sending with 10 millisecond of delay
1111 01:35:48.351949 => setenv autoload no
1112 01:35:48.363026 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1113 01:35:48.369408 setenv autoload no
1114 01:35:48.370368 Sending with 10 millisecond of delay
1116 01:35:50.167026 => setenv initrd_high 0xffffffff
1117 01:35:50.177808 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 01:35:50.178642 setenv initrd_high 0xffffffff
1119 01:35:50.179357 Sending with 10 millisecond of delay
1121 01:35:51.795449 => setenv fdt_high 0xffffffff
1122 01:35:51.806272 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 01:35:51.807097 setenv fdt_high 0xffffffff
1124 01:35:51.807809 Sending with 10 millisecond of delay
1126 01:35:52.099687 => dhcp
1127 01:35:52.110701 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 01:35:52.111775 dhcp
1129 01:35:52.112383 Speed: 1000, full duplex
1130 01:35:52.112934 BOOTP broadcast 1
1131 01:35:52.121029 DHCP client bound to address 192.168.6.27 (10 ms)
1132 01:35:52.121910 Sending with 10 millisecond of delay
1134 01:35:53.798756 => setenv serverip 192.168.6.2
1135 01:35:53.809762 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1136 01:35:53.810914 setenv serverip 192.168.6.2
1137 01:35:53.811776 Sending with 10 millisecond of delay
1139 01:35:57.535435 => tftpboot 0x01080000 973280/tftp-deploy-ienrcya0/kernel/uImage
1140 01:35:57.546301 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1141 01:35:57.547169 tftpboot 0x01080000 973280/tftp-deploy-ienrcya0/kernel/uImage
1142 01:35:57.547620 Speed: 1000, full duplex
1143 01:35:57.548071 Using ethernet@ff3f0000 device
1144 01:35:57.548967 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1145 01:35:57.554558 Filename '973280/tftp-deploy-ienrcya0/kernel/uImage'.
1146 01:35:57.558585 Load address: 0x1080000
1147 01:36:00.523724 Loading: *################################################## 43.6 MiB
1148 01:36:00.524396 14.7 MiB/s
1149 01:36:00.524831 done
1150 01:36:00.528239 Bytes transferred = 45716032 (2b99240 hex)
1151 01:36:00.529033 Sending with 10 millisecond of delay
1153 01:36:05.216743 => tftpboot 0x08000000 973280/tftp-deploy-ienrcya0/ramdisk/ramdisk.cpio.gz.uboot
1154 01:36:05.227520 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1155 01:36:05.228372 tftpboot 0x08000000 973280/tftp-deploy-ienrcya0/ramdisk/ramdisk.cpio.gz.uboot
1156 01:36:05.228825 Speed: 1000, full duplex
1157 01:36:05.229240 Using ethernet@ff3f0000 device
1158 01:36:05.230404 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1159 01:36:05.242093 Filename '973280/tftp-deploy-ienrcya0/ramdisk/ramdisk.cpio.gz.uboot'.
1160 01:36:05.242568 Load address: 0x8000000
1161 01:36:12.224053 Loading: *####################T ############################# UDP wrong checksum 00000005 0000bc2a
1162 01:36:17.225420 T UDP wrong checksum 00000005 0000bc2a
1163 01:36:27.228440 T T UDP wrong checksum 00000005 0000bc2a
1164 01:36:47.232588 T T T T UDP wrong checksum 00000005 0000bc2a
1165 01:37:02.236334 T T
1166 01:37:02.236794 Retry count exceeded; starting again
1168 01:37:02.238568 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1171 01:37:02.239931 end: 2.4 uboot-commands (duration 00:01:52) [common]
1173 01:37:02.241044 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1175 01:37:02.241879 end: 2 uboot-action (duration 00:01:52) [common]
1177 01:37:02.243053 Cleaning after the job
1178 01:37:02.243509 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973280/tftp-deploy-ienrcya0/ramdisk
1179 01:37:02.244646 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973280/tftp-deploy-ienrcya0/kernel
1180 01:37:02.261903 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973280/tftp-deploy-ienrcya0/dtb
1181 01:37:02.263036 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973280/tftp-deploy-ienrcya0/nfsrootfs
1182 01:37:02.451543 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/973280/tftp-deploy-ienrcya0/modules
1183 01:37:02.468633 start: 4.1 power-off (timeout 00:00:30) [common]
1184 01:37:02.469434 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1185 01:37:02.503645 >> OK - accepted request
1186 01:37:02.505735 Returned 0 in 0 seconds
1187 01:37:02.606703 end: 4.1 power-off (duration 00:00:00) [common]
1189 01:37:02.607966 start: 4.2 read-feedback (timeout 00:10:00) [common]
1190 01:37:02.608807 Listened to connection for namespace 'common' for up to 1s
1191 01:37:03.609763 Finalising connection for namespace 'common'
1192 01:37:03.610358 Disconnecting from shell: Finalise
1193 01:37:03.610694 =>
1194 01:37:03.711517 end: 4.2 read-feedback (duration 00:00:01) [common]
1195 01:37:03.712103 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/973280
1196 01:37:07.250551 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/973280
1197 01:37:07.251425 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.