Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 03:01:24.326778 lava-dispatcher, installed at version: 2024.01
2 03:01:24.327556 start: 0 validate
3 03:01:24.328046 Start time: 2024-11-12 03:01:24.328016+00:00 (UTC)
4 03:01:24.328610 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 03:01:24.329157 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 03:01:24.366818 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 03:01:24.367573 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc7-95-g96203094619a7%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 03:01:25.402161 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 03:01:25.402916 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc7-95-g96203094619a7%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 03:01:28.449959 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 03:01:28.450562 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 03:01:28.480352 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 03:01:28.481139 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fnext%2Fpending-fixes%2Fv6.12-rc7-95-g96203094619a7%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 03:01:29.523811 validate duration: 5.20
16 03:01:29.525383 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 03:01:29.526011 start: 1.1 download-retry (timeout 00:10:00) [common]
18 03:01:29.526600 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 03:01:29.527608 Not decompressing ramdisk as can be used compressed.
20 03:01:29.528305 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 03:01:29.528803 saving as /var/lib/lava/dispatcher/tmp/978069/tftp-deploy-lm_nm_7r/ramdisk/initrd.cpio.gz
22 03:01:29.529337 total size: 4775763 (4 MB)
23 03:01:29.565811 progress 0 % (0 MB)
24 03:01:29.573532 progress 5 % (0 MB)
25 03:01:29.579741 progress 10 % (0 MB)
26 03:01:29.585910 progress 15 % (0 MB)
27 03:01:29.592822 progress 20 % (0 MB)
28 03:01:29.597507 progress 25 % (1 MB)
29 03:01:29.600721 progress 30 % (1 MB)
30 03:01:29.604281 progress 35 % (1 MB)
31 03:01:29.607400 progress 40 % (1 MB)
32 03:01:29.610487 progress 45 % (2 MB)
33 03:01:29.613635 progress 50 % (2 MB)
34 03:01:29.617091 progress 55 % (2 MB)
35 03:01:29.620257 progress 60 % (2 MB)
36 03:01:29.623316 progress 65 % (2 MB)
37 03:01:29.626818 progress 70 % (3 MB)
38 03:01:29.629849 progress 75 % (3 MB)
39 03:01:29.632848 progress 80 % (3 MB)
40 03:01:29.635761 progress 85 % (3 MB)
41 03:01:29.639001 progress 90 % (4 MB)
42 03:01:29.641891 progress 95 % (4 MB)
43 03:01:29.644807 progress 100 % (4 MB)
44 03:01:29.645439 4 MB downloaded in 0.12 s (39.23 MB/s)
45 03:01:29.645961 end: 1.1.1 http-download (duration 00:00:00) [common]
47 03:01:29.646833 end: 1.1 download-retry (duration 00:00:00) [common]
48 03:01:29.647104 start: 1.2 download-retry (timeout 00:10:00) [common]
49 03:01:29.647365 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 03:01:29.647844 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc7-95-g96203094619a7/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 03:01:29.648117 saving as /var/lib/lava/dispatcher/tmp/978069/tftp-deploy-lm_nm_7r/kernel/zImage
52 03:01:29.648326 total size: 11448832 (10 MB)
53 03:01:29.648535 No compression specified
54 03:01:29.687491 progress 0 % (0 MB)
55 03:01:29.694473 progress 5 % (0 MB)
56 03:01:29.701226 progress 10 % (1 MB)
57 03:01:29.708336 progress 15 % (1 MB)
58 03:01:29.715132 progress 20 % (2 MB)
59 03:01:29.722215 progress 25 % (2 MB)
60 03:01:29.729026 progress 30 % (3 MB)
61 03:01:29.736141 progress 35 % (3 MB)
62 03:01:29.742857 progress 40 % (4 MB)
63 03:01:29.750016 progress 45 % (4 MB)
64 03:01:29.756848 progress 50 % (5 MB)
65 03:01:29.763892 progress 55 % (6 MB)
66 03:01:29.770603 progress 60 % (6 MB)
67 03:01:29.777778 progress 65 % (7 MB)
68 03:01:29.784517 progress 70 % (7 MB)
69 03:01:29.791531 progress 75 % (8 MB)
70 03:01:29.798207 progress 80 % (8 MB)
71 03:01:29.804924 progress 85 % (9 MB)
72 03:01:29.811899 progress 90 % (9 MB)
73 03:01:29.818252 progress 95 % (10 MB)
74 03:01:29.825041 progress 100 % (10 MB)
75 03:01:29.825609 10 MB downloaded in 0.18 s (61.59 MB/s)
76 03:01:29.826095 end: 1.2.1 http-download (duration 00:00:00) [common]
78 03:01:29.826927 end: 1.2 download-retry (duration 00:00:00) [common]
79 03:01:29.827214 start: 1.3 download-retry (timeout 00:10:00) [common]
80 03:01:29.827489 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 03:01:29.827975 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc7-95-g96203094619a7/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 03:01:29.828283 saving as /var/lib/lava/dispatcher/tmp/978069/tftp-deploy-lm_nm_7r/dtb/am335x-boneblack.dtb
83 03:01:29.828498 total size: 70568 (0 MB)
84 03:01:29.828713 No compression specified
85 03:01:29.861481 progress 46 % (0 MB)
86 03:01:29.862463 progress 92 % (0 MB)
87 03:01:29.863274 progress 100 % (0 MB)
88 03:01:29.863770 0 MB downloaded in 0.04 s (1.91 MB/s)
89 03:01:29.864384 end: 1.3.1 http-download (duration 00:00:00) [common]
91 03:01:29.865395 end: 1.3 download-retry (duration 00:00:00) [common]
92 03:01:29.865732 start: 1.4 download-retry (timeout 00:10:00) [common]
93 03:01:29.866062 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 03:01:29.866643 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 03:01:29.866943 saving as /var/lib/lava/dispatcher/tmp/978069/tftp-deploy-lm_nm_7r/nfsrootfs/full.rootfs.tar
96 03:01:29.867207 total size: 117747780 (112 MB)
97 03:01:29.867467 Using unxz to decompress xz
98 03:01:29.907036 progress 0 % (0 MB)
99 03:01:30.638231 progress 5 % (5 MB)
100 03:01:31.381345 progress 10 % (11 MB)
101 03:01:32.152599 progress 15 % (16 MB)
102 03:01:32.868751 progress 20 % (22 MB)
103 03:01:33.442084 progress 25 % (28 MB)
104 03:01:34.238322 progress 30 % (33 MB)
105 03:01:35.038082 progress 35 % (39 MB)
106 03:01:35.383492 progress 40 % (44 MB)
107 03:01:35.735073 progress 45 % (50 MB)
108 03:01:36.393393 progress 50 % (56 MB)
109 03:01:37.207220 progress 55 % (61 MB)
110 03:01:37.932463 progress 60 % (67 MB)
111 03:01:38.640743 progress 65 % (73 MB)
112 03:01:39.393305 progress 70 % (78 MB)
113 03:01:40.143999 progress 75 % (84 MB)
114 03:01:40.867218 progress 80 % (89 MB)
115 03:01:41.569261 progress 85 % (95 MB)
116 03:01:42.350103 progress 90 % (101 MB)
117 03:01:43.109553 progress 95 % (106 MB)
118 03:01:43.925062 progress 100 % (112 MB)
119 03:01:43.936985 112 MB downloaded in 14.07 s (7.98 MB/s)
120 03:01:43.937654 end: 1.4.1 http-download (duration 00:00:14) [common]
122 03:01:43.938608 end: 1.4 download-retry (duration 00:00:14) [common]
123 03:01:43.938936 start: 1.5 download-retry (timeout 00:09:46) [common]
124 03:01:43.939249 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 03:01:43.939797 downloading http://storage.kernelci.org/next/pending-fixes/v6.12-rc7-95-g96203094619a7/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 03:01:43.940135 saving as /var/lib/lava/dispatcher/tmp/978069/tftp-deploy-lm_nm_7r/modules/modules.tar
127 03:01:43.940392 total size: 6609492 (6 MB)
128 03:01:43.940658 Using unxz to decompress xz
129 03:01:43.980676 progress 0 % (0 MB)
130 03:01:44.021936 progress 5 % (0 MB)
131 03:01:44.073240 progress 10 % (0 MB)
132 03:01:44.125180 progress 15 % (0 MB)
133 03:01:44.169514 progress 20 % (1 MB)
134 03:01:44.216226 progress 25 % (1 MB)
135 03:01:44.259220 progress 30 % (1 MB)
136 03:01:44.302107 progress 35 % (2 MB)
137 03:01:44.346085 progress 40 % (2 MB)
138 03:01:44.389611 progress 45 % (2 MB)
139 03:01:44.433090 progress 50 % (3 MB)
140 03:01:44.475622 progress 55 % (3 MB)
141 03:01:44.525932 progress 60 % (3 MB)
142 03:01:44.568883 progress 65 % (4 MB)
143 03:01:44.612341 progress 70 % (4 MB)
144 03:01:44.659207 progress 75 % (4 MB)
145 03:01:44.703120 progress 80 % (5 MB)
146 03:01:44.747449 progress 85 % (5 MB)
147 03:01:44.796281 progress 90 % (5 MB)
148 03:01:44.842507 progress 95 % (6 MB)
149 03:01:44.888547 progress 100 % (6 MB)
150 03:01:44.901937 6 MB downloaded in 0.96 s (6.56 MB/s)
151 03:01:44.903008 end: 1.5.1 http-download (duration 00:00:01) [common]
153 03:01:44.904950 end: 1.5 download-retry (duration 00:00:01) [common]
154 03:01:44.905616 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 03:01:44.906231 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 03:02:02.611362 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/978069/extract-nfsrootfs-hd0p7fiu
157 03:02:02.611944 end: 1.6.1 extract-nfsrootfs (duration 00:00:18) [common]
158 03:02:02.612265 start: 1.6.2 lava-overlay (timeout 00:09:27) [common]
159 03:02:02.612877 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35
160 03:02:02.613326 makedir: /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin
161 03:02:02.613664 makedir: /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/tests
162 03:02:02.614035 makedir: /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/results
163 03:02:02.614385 Creating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-add-keys
164 03:02:02.614912 Creating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-add-sources
165 03:02:02.615416 Creating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-background-process-start
166 03:02:02.615911 Creating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-background-process-stop
167 03:02:02.616492 Creating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-common-functions
168 03:02:02.616993 Creating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-echo-ipv4
169 03:02:02.617475 Creating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-install-packages
170 03:02:02.617967 Creating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-installed-packages
171 03:02:02.618499 Creating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-os-build
172 03:02:02.618979 Creating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-probe-channel
173 03:02:02.619448 Creating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-probe-ip
174 03:02:02.619915 Creating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-target-ip
175 03:02:02.620422 Creating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-target-mac
176 03:02:02.620897 Creating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-target-storage
177 03:02:02.621397 Creating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-test-case
178 03:02:02.621914 Creating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-test-event
179 03:02:02.622396 Creating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-test-feedback
180 03:02:02.622867 Creating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-test-raise
181 03:02:02.623331 Creating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-test-reference
182 03:02:02.623801 Creating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-test-runner
183 03:02:02.624313 Creating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-test-set
184 03:02:02.624883 Creating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-test-shell
185 03:02:02.625397 Updating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-add-keys (debian)
186 03:02:02.625935 Updating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-add-sources (debian)
187 03:02:02.626435 Updating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-install-packages (debian)
188 03:02:02.626924 Updating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-installed-packages (debian)
189 03:02:02.627409 Updating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/bin/lava-os-build (debian)
190 03:02:02.627836 Creating /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/environment
191 03:02:02.628228 LAVA metadata
192 03:02:02.628491 - LAVA_JOB_ID=978069
193 03:02:02.628707 - LAVA_DISPATCHER_IP=192.168.6.2
194 03:02:02.629063 start: 1.6.2.1 ssh-authorize (timeout 00:09:27) [common]
195 03:02:02.630016 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 03:02:02.630321 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:27) [common]
197 03:02:02.630525 skipped lava-vland-overlay
198 03:02:02.630764 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 03:02:02.631014 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:27) [common]
200 03:02:02.631229 skipped lava-multinode-overlay
201 03:02:02.631469 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 03:02:02.631717 start: 1.6.2.4 test-definition (timeout 00:09:27) [common]
203 03:02:02.631958 Loading test definitions
204 03:02:02.632261 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:27) [common]
205 03:02:02.632477 Using /lava-978069 at stage 0
206 03:02:02.633608 uuid=978069_1.6.2.4.1 testdef=None
207 03:02:02.633911 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 03:02:02.634173 start: 1.6.2.4.2 test-overlay (timeout 00:09:27) [common]
209 03:02:02.635706 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 03:02:02.636507 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:27) [common]
212 03:02:02.638404 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 03:02:02.639211 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:27) [common]
215 03:02:02.641071 runner path: /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/0/tests/0_timesync-off test_uuid 978069_1.6.2.4.1
216 03:02:02.641624 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 03:02:02.642427 start: 1.6.2.4.5 git-repo-action (timeout 00:09:27) [common]
219 03:02:02.642647 Using /lava-978069 at stage 0
220 03:02:02.642993 Fetching tests from https://github.com/kernelci/test-definitions.git
221 03:02:02.643283 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/0/tests/1_kselftest-dt'
222 03:02:05.973734 Running '/usr/bin/git checkout kernelci.org
223 03:02:06.423599 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 03:02:06.426123 uuid=978069_1.6.2.4.5 testdef=None
225 03:02:06.426786 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 03:02:06.428426 start: 1.6.2.4.6 test-overlay (timeout 00:09:23) [common]
228 03:02:06.434407 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 03:02:06.436192 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:23) [common]
231 03:02:06.444177 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 03:02:06.446013 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:23) [common]
234 03:02:06.453715 runner path: /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/0/tests/1_kselftest-dt test_uuid 978069_1.6.2.4.5
235 03:02:06.454305 BOARD='beaglebone-black'
236 03:02:06.454746 BRANCH='next'
237 03:02:06.455177 SKIPFILE='/dev/null'
238 03:02:06.455604 SKIP_INSTALL='True'
239 03:02:06.456091 TESTPROG_URL='http://storage.kernelci.org/next/pending-fixes/v6.12-rc7-95-g96203094619a7/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 03:02:06.456548 TST_CASENAME=''
241 03:02:06.456979 TST_CMDFILES='dt'
242 03:02:06.458129 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 03:02:06.459824 Creating lava-test-runner.conf files
245 03:02:06.460311 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/978069/lava-overlay-5rgmqq35/lava-978069/0 for stage 0
246 03:02:06.461025 - 0_timesync-off
247 03:02:06.461523 - 1_kselftest-dt
248 03:02:06.462216 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 03:02:06.462804 start: 1.6.2.5 compress-overlay (timeout 00:09:23) [common]
250 03:02:29.731054 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 03:02:29.731504 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:00) [common]
252 03:02:29.731766 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 03:02:29.732060 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 03:02:29.732330 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:00) [common]
255 03:02:30.125525 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 03:02:30.126013 start: 1.6.4 extract-modules (timeout 00:08:59) [common]
257 03:02:30.126267 extracting modules file /var/lib/lava/dispatcher/tmp/978069/tftp-deploy-lm_nm_7r/modules/modules.tar to /var/lib/lava/dispatcher/tmp/978069/extract-nfsrootfs-hd0p7fiu
258 03:02:31.016661 extracting modules file /var/lib/lava/dispatcher/tmp/978069/tftp-deploy-lm_nm_7r/modules/modules.tar to /var/lib/lava/dispatcher/tmp/978069/extract-overlay-ramdisk-frx4ej2_/ramdisk
259 03:02:31.953749 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 03:02:31.954229 start: 1.6.5 apply-overlay-tftp (timeout 00:08:58) [common]
261 03:02:31.954508 [common] Applying overlay to NFS
262 03:02:31.954726 [common] Applying overlay /var/lib/lava/dispatcher/tmp/978069/compress-overlay-aaxh4g7q/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/978069/extract-nfsrootfs-hd0p7fiu
263 03:02:34.720118 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 03:02:34.720605 start: 1.6.6 prepare-kernel (timeout 00:08:55) [common]
265 03:02:34.720906 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:55) [common]
266 03:02:34.721203 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 03:02:34.721476 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 03:02:34.721751 start: 1.6.7 configure-preseed-file (timeout 00:08:55) [common]
269 03:02:34.722013 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 03:02:34.722279 start: 1.6.8 compress-ramdisk (timeout 00:08:55) [common]
271 03:02:34.722539 Building ramdisk /var/lib/lava/dispatcher/tmp/978069/extract-overlay-ramdisk-frx4ej2_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/978069/extract-overlay-ramdisk-frx4ej2_/ramdisk
272 03:02:35.716786 >> 74903 blocks
273 03:02:40.296982 Adding RAMdisk u-boot header.
274 03:02:40.297430 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/978069/extract-overlay-ramdisk-frx4ej2_/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/978069/extract-overlay-ramdisk-frx4ej2_/ramdisk.cpio.gz.uboot
275 03:02:40.457668 output: Image Name:
276 03:02:40.458082 output: Created: Tue Nov 12 03:02:40 2024
277 03:02:40.458293 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 03:02:40.458497 output: Data Size: 14792941 Bytes = 14446.23 KiB = 14.11 MiB
279 03:02:40.458697 output: Load Address: 00000000
280 03:02:40.458894 output: Entry Point: 00000000
281 03:02:40.459089 output:
282 03:02:40.459774 rename /var/lib/lava/dispatcher/tmp/978069/extract-overlay-ramdisk-frx4ej2_/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/978069/tftp-deploy-lm_nm_7r/ramdisk/ramdisk.cpio.gz.uboot
283 03:02:40.460376 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 03:02:40.460983 end: 1.6 prepare-tftp-overlay (duration 00:00:56) [common]
285 03:02:40.461559 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:49) [common]
286 03:02:40.462056 No LXC device requested
287 03:02:40.462600 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 03:02:40.463149 start: 1.8 deploy-device-env (timeout 00:08:49) [common]
289 03:02:40.463693 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 03:02:40.464183 Checking files for TFTP limit of 4294967296 bytes.
291 03:02:40.467080 end: 1 tftp-deploy (duration 00:01:11) [common]
292 03:02:40.467704 start: 2 uboot-action (timeout 00:05:00) [common]
293 03:02:40.468329 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 03:02:40.468876 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 03:02:40.469426 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 03:02:40.470245 substitutions:
297 03:02:40.470705 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 03:02:40.471154 - {DTB_ADDR}: 0x88000000
299 03:02:40.471595 - {DTB}: 978069/tftp-deploy-lm_nm_7r/dtb/am335x-boneblack.dtb
300 03:02:40.472068 - {INITRD}: 978069/tftp-deploy-lm_nm_7r/ramdisk/ramdisk.cpio.gz.uboot
301 03:02:40.472511 - {KERNEL_ADDR}: 0x82000000
302 03:02:40.472942 - {KERNEL}: 978069/tftp-deploy-lm_nm_7r/kernel/zImage
303 03:02:40.473376 - {LAVA_MAC}: None
304 03:02:40.473850 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/978069/extract-nfsrootfs-hd0p7fiu
305 03:02:40.474287 - {NFS_SERVER_IP}: 192.168.6.2
306 03:02:40.474720 - {PRESEED_CONFIG}: None
307 03:02:40.475151 - {PRESEED_LOCAL}: None
308 03:02:40.475586 - {RAMDISK_ADDR}: 0x83000000
309 03:02:40.476045 - {RAMDISK}: 978069/tftp-deploy-lm_nm_7r/ramdisk/ramdisk.cpio.gz.uboot
310 03:02:40.476489 - {ROOT_PART}: None
311 03:02:40.476923 - {ROOT}: None
312 03:02:40.477352 - {SERVER_IP}: 192.168.6.2
313 03:02:40.477775 - {TEE_ADDR}: 0x83000000
314 03:02:40.478199 - {TEE}: None
315 03:02:40.478624 Parsed boot commands:
316 03:02:40.479038 - setenv autoload no
317 03:02:40.479462 - setenv initrd_high 0xffffffff
318 03:02:40.479890 - setenv fdt_high 0xffffffff
319 03:02:40.480342 - dhcp
320 03:02:40.480761 - setenv serverip 192.168.6.2
321 03:02:40.481186 - tftp 0x82000000 978069/tftp-deploy-lm_nm_7r/kernel/zImage
322 03:02:40.481612 - tftp 0x83000000 978069/tftp-deploy-lm_nm_7r/ramdisk/ramdisk.cpio.gz.uboot
323 03:02:40.482035 - setenv initrd_size ${filesize}
324 03:02:40.482457 - tftp 0x88000000 978069/tftp-deploy-lm_nm_7r/dtb/am335x-boneblack.dtb
325 03:02:40.482883 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/978069/extract-nfsrootfs-hd0p7fiu,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 03:02:40.483319 - bootz 0x82000000 0x83000000 0x88000000
327 03:02:40.483865 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 03:02:40.485653 start: 2.3 connect-device (timeout 00:05:00) [common]
330 03:02:40.486177 [common] connect-device Connecting to device using 'telnet conserv1 3003'
331 03:02:40.500942 Setting prompt string to ['lava-test: # ']
332 03:02:40.502614 end: 2.3 connect-device (duration 00:00:00) [common]
333 03:02:40.503280 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 03:02:40.503912 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 03:02:40.504602 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 03:02:40.505368 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-01'
337 03:02:40.540944 >> OK - accepted request
338 03:02:40.542887 Returned 0 in 0 seconds
339 03:02:40.643808 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 03:02:40.645687 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 03:02:40.646289 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 03:02:40.646852 Setting prompt string to ['Hit any key to stop autoboot']
344 03:02:40.647351 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 03:02:40.649087 Trying 192.168.56.21...
346 03:02:40.649614 Connected to conserv1.
347 03:02:40.650068 Escape character is '^]'.
348 03:02:40.650520
349 03:02:40.650972 ser2net port telnet,3003 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 03:02:40.651422
351 03:02:48.664271
352 03:02:48.664896 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
353 03:02:48.669358 Trying to boot from MMC1
354 03:02:49.242406
355 03:02:49.243093
356 03:02:49.243565 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
357 03:02:49.244064
358 03:02:49.247945 CPU : AM335X-GP rev 2.1
359 03:02:49.248515 Model: TI AM335x BeagleBone Black
360 03:02:49.251971 DRAM: 512 MiB
361 03:02:49.334698 Core: 160 devices, 18 uclasses, devicetree: separate
362 03:02:49.344458 WDT: Started wdt@44e35000 with servicing (60s timeout)
363 03:02:52.713316 7[r[999;999H[6n8NAND:
364 03:02:52.714010 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
365 03:02:52.718502 Trying to boot from MMC1
366 03:02:53.290889
367 03:02:53.291546
368 03:02:53.292092 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
369 03:02:53.292611
370 03:02:53.296443 CPU : AM335X-GP rev 2.1
371 03:02:53.297003 Model: TI AM335x BeagleBone Black
372 03:02:53.300524 DRAM: 512 MiB
373 03:02:53.383254 Core: 160 devices, 18 uclasses, devicetree: separate
374 03:02:53.393054 WDT: Started wdt@44e35000 with servicing (60s timeout)
375 03:02:55.415350 7[r[999;999H[6n8NAND:
376 03:02:55.415800 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
377 03:02:55.420325 Trying to boot from MMC1
378 03:02:55.992691
379 03:02:55.993333
380 03:02:55.993762 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
381 03:02:55.994182
382 03:02:55.998093 CPU : AM335X-GP rev 2.1
383 03:02:55.998589 Model: TI AM335x BeagleBone Black
384 03:02:56.002229 DRAM: 512 MiB
385 03:02:56.085136 Core: 160 devices, 18 uclasses, devicetree: separate
386 03:02:56.094556 WDT: Started wdt@44e35000 with servicing (60s timeout)
387 03:02:56.599976 7[r[999;999H[6n8NAND: 0 MiB
388 03:02:56.610006 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
389 03:02:56.682837 Loading Environment from FAT... Unable to use mmc 0:1...
390 03:02:56.704183 <ethaddr> not set. Validating first E-fuse MAC
391 03:02:56.734535 Net: eth2: ethernet@4a100000, eth3: usb_ether
393 03:02:56.792883 Hit any key to stop autoboot: 2
394 03:02:56.793738 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
395 03:02:56.794141 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
396 03:02:56.794444 Setting prompt string to ['=>']
397 03:02:56.794723 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
398 03:02:56.802958 0
399 03:02:56.803619 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
400 03:02:56.803923 Sending with 10 millisecond of delay
402 03:02:57.938908 => setenv autoload no
403 03:02:57.949828 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
404 03:02:57.955323 setenv autoload no
405 03:02:57.956149 Sending with 10 millisecond of delay
407 03:02:59.754555 => setenv initrd_high 0xffffffff
408 03:02:59.765431 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
409 03:02:59.766483 setenv initrd_high 0xffffffff
410 03:02:59.767273 Sending with 10 millisecond of delay
412 03:03:01.384099 => setenv fdt_high 0xffffffff
413 03:03:01.394680 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
414 03:03:01.395217 setenv fdt_high 0xffffffff
415 03:03:01.395674 Sending with 10 millisecond of delay
417 03:03:01.687181 => dhcp
418 03:03:01.698028 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
419 03:03:01.698975 dhcp
420 03:03:01.699457 link up on port 0, speed 100, full duplex
421 03:03:01.699909 BOOTP broadcast 1
422 03:03:01.725159 DHCP client bound to address 192.168.6.12 (21 ms)
423 03:03:01.725951 Sending with 10 millisecond of delay
425 03:03:03.403062 => setenv serverip 192.168.6.2
426 03:03:03.413824 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
427 03:03:03.414660 setenv serverip 192.168.6.2
428 03:03:03.415383 Sending with 10 millisecond of delay
430 03:03:06.899706 => tftp 0x82000000 978069/tftp-deploy-lm_nm_7r/kernel/zImage
431 03:03:06.910415 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
432 03:03:06.911133 tftp 0x82000000 978069/tftp-deploy-lm_nm_7r/kernel/zImage
433 03:03:06.911499 link up on port 0, speed 100, full duplex
434 03:03:06.915089 Using ethernet@4a100000 device
435 03:03:06.920720 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
436 03:03:06.921073 Filename '978069/tftp-deploy-lm_nm_7r/kernel/zImage'.
437 03:03:06.924188 Load address: 0x82000000
438 03:03:09.160653 Loading: *################################################## 10.9 MiB
439 03:03:09.161068 4.9 MiB/s
440 03:03:09.161316 done
441 03:03:09.164310 Bytes transferred = 11448832 (aeb200 hex)
442 03:03:09.164886 Sending with 10 millisecond of delay
444 03:03:13.613296 => tftp 0x83000000 978069/tftp-deploy-lm_nm_7r/ramdisk/ramdisk.cpio.gz.uboot
445 03:03:13.624122 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
446 03:03:13.625341 tftp 0x83000000 978069/tftp-deploy-lm_nm_7r/ramdisk/ramdisk.cpio.gz.uboot
447 03:03:13.626063 link up on port 0, speed 100, full duplex
448 03:03:13.629182 Using ethernet@4a100000 device
449 03:03:13.634626 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
450 03:03:13.643612 Filename '978069/tftp-deploy-lm_nm_7r/ramdisk/ramdisk.cpio.gz.uboot'.
451 03:03:13.644431 Load address: 0x83000000
452 03:03:16.624501 Loading: *################################################## 14.1 MiB
453 03:03:16.625106 4.7 MiB/s
454 03:03:16.625510 done
455 03:03:16.628118 Bytes transferred = 14793005 (e1b92d hex)
456 03:03:16.628931 Sending with 10 millisecond of delay
458 03:03:18.486218 => setenv initrd_size ${filesize}
459 03:03:18.497006 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
460 03:03:18.497826 setenv initrd_size ${filesize}
461 03:03:18.498506 Sending with 10 millisecond of delay
463 03:03:22.643905 => tftp 0x88000000 978069/tftp-deploy-lm_nm_7r/dtb/am335x-boneblack.dtb
464 03:03:22.654693 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
465 03:03:22.655534 tftp 0x88000000 978069/tftp-deploy-lm_nm_7r/dtb/am335x-boneblack.dtb
466 03:03:22.655956 link up on port 0, speed 100, full duplex
467 03:03:22.659398 Using ethernet@4a100000 device
468 03:03:22.664972 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
469 03:03:22.672399 Filename '978069/tftp-deploy-lm_nm_7r/dtb/am335x-boneblack.dtb'.
470 03:03:22.672884 Load address: 0x88000000
471 03:03:22.686390 Loading: *################################################## 68.9 KiB
472 03:03:22.696262 4.2 MiB/s
473 03:03:22.696719 done
474 03:03:22.697112 Bytes transferred = 70568 (113a8 hex)
475 03:03:22.697771 Sending with 10 millisecond of delay
477 03:03:35.879837 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/978069/extract-nfsrootfs-hd0p7fiu,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 03:03:35.890979 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
479 03:03:35.892211 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/978069/extract-nfsrootfs-hd0p7fiu,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 03:03:35.893208 Sending with 10 millisecond of delay
482 03:03:38.233254 => bootz 0x82000000 0x83000000 0x88000000
483 03:03:38.244103 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 03:03:38.244697 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
485 03:03:38.245794 bootz 0x82000000 0x83000000 0x88000000
486 03:03:38.246285 Kernel image @ 0x82000000 [ 0x000000 - 0xaeb200 ]
487 03:03:38.246828 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 03:03:38.251432 Image Name:
489 03:03:38.251915 Created: 2024-11-12 3:02:40 UTC
490 03:03:38.257045 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 03:03:38.262588 Data Size: 14792941 Bytes = 14.1 MiB
492 03:03:38.263061 Load Address: 00000000
493 03:03:38.268781 Entry Point: 00000000
494 03:03:38.437254 Verifying Checksum ... OK
495 03:03:38.437913 ## Flattened Device Tree blob at 88000000
496 03:03:38.443769 Booting using the fdt blob at 0x88000000
497 03:03:38.448655 Using Device Tree in place at 88000000, end 880143a7
498 03:03:38.462279
499 03:03:38.462774 Starting kernel ...
500 03:03:38.463226
501 03:03:38.464178 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 03:03:38.464803 start: 2.4.4 auto-login-action (timeout 00:04:02) [common]
503 03:03:38.465308 Setting prompt string to ['Linux version [0-9]']
504 03:03:38.465837 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
505 03:03:38.466350 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
506 03:03:39.309761 [ 0.000000] Booting Linux on physical CPU 0x0
507 03:03:39.315728 start: 2.4.4.1 login-action (timeout 00:04:01) [common]
508 03:03:39.316556 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 03:03:39.317133 Setting prompt string to []
510 03:03:39.317708 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 03:03:39.318260 Using line separator: #'\n'#
512 03:03:39.318840 No login prompt set.
513 03:03:39.319373 Parsing kernel messages
514 03:03:39.319859 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 03:03:39.320715 [login-action] Waiting for messages, (timeout 00:04:01)
516 03:03:39.321253 Waiting using forced prompt support (timeout 00:02:01)
517 03:03:39.329719 [ 0.000000] Linux version 6.12.0-rc7 (KernelCI@build-j373521-arm-gcc-12-multi-v7-defconfig-5ktlm) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Tue Nov 12 02:45:50 UTC 2024
518 03:03:39.340953 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
519 03:03:39.346796 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
520 03:03:39.352646 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
521 03:03:39.358189 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
522 03:03:39.363924 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
523 03:03:39.370560 [ 0.000000] Memory policy: Data cache writeback
524 03:03:39.370971 [ 0.000000] efi: UEFI not found.
525 03:03:39.378848 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
526 03:03:39.384586 [ 0.000000] Zone ranges:
527 03:03:39.390261 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
528 03:03:39.396032 [ 0.000000] Normal empty
529 03:03:39.396726 [ 0.000000] HighMem empty
530 03:03:39.401840 [ 0.000000] Movable zone start for each node
531 03:03:39.402555 [ 0.000000] Early memory node ranges
532 03:03:39.413307 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
533 03:03:39.418788 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
534 03:03:39.444129 [ 0.000000] CPU: All CPU(s) started in SVC mode.
535 03:03:39.449774 [ 0.000000] AM335X ES2.1 (sgx neon)
536 03:03:39.461327 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
537 03:03:39.481878 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/978069/extract-nfsrootfs-hd0p7fiu,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
538 03:03:39.487687 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
539 03:03:39.499088 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
540 03:03:39.504725 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
541 03:03:39.511995 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
542 03:03:39.541112 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
543 03:03:39.547220 <6>[ 0.000000] trace event string verifier disabled
544 03:03:39.547875 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
545 03:03:39.554961 <6>[ 0.000000] rcu: RCU event tracing is enabled.
546 03:03:39.561077 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
547 03:03:39.572310 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
548 03:03:39.577165 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
549 03:03:39.592064 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
550 03:03:39.609308 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
551 03:03:39.616103 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
552 03:03:39.708844 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
553 03:03:39.720240 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
554 03:03:39.727153 <6>[ 0.008337] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
555 03:03:39.740076 <6>[ 0.019142] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
556 03:03:39.747429 <6>[ 0.033959] Console: colour dummy device 80x30
557 03:03:39.753550 Matched prompt #6: WARNING:
558 03:03:39.754160 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
559 03:03:39.758906 <3>[ 0.038854] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
560 03:03:39.764616 <3>[ 0.045922] This ensures that you still see kernel messages. Please
561 03:03:39.766907 <3>[ 0.052646] update your kernel commandline.
562 03:03:39.808611 <6>[ 0.057255] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
563 03:03:39.814180 <6>[ 0.096146] CPU: Testing write buffer coherency: ok
564 03:03:39.820108 <6>[ 0.101509] CPU0: Spectre v2: using BPIALL workaround
565 03:03:39.820600 <6>[ 0.106975] pid_max: default: 32768 minimum: 301
566 03:03:39.831563 <6>[ 0.112163] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 03:03:39.838508 <6>[ 0.119985] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 03:03:39.844723 <6>[ 0.129343] CPU0: thread -1, cpu 0, socket -1, mpidr 0
569 03:03:39.911101 <6>[ 0.189531] Setting up static identity map for 0x80300000 - 0x803000ac
570 03:03:39.916862 <6>[ 0.199100] rcu: Hierarchical SRCU implementation.
571 03:03:39.920607 <6>[ 0.204389] rcu: Max phase no-delay instances is 1000.
572 03:03:39.929019 <6>[ 0.215407] EFI services will not be available.
573 03:03:39.934817 <6>[ 0.220760] smp: Bringing up secondary CPUs ...
574 03:03:39.940668 <6>[ 0.225728] smp: Brought up 1 node, 1 CPU
575 03:03:39.946382 <6>[ 0.230213] SMP: Total of 1 processors activated (996.14 BogoMIPS).
576 03:03:39.952354 <6>[ 0.236933] CPU: All CPU(s) started in SVC mode.
577 03:03:39.972675 <6>[ 0.242141] Memory: 405996K/522240K available (16384K kernel code, 2543K rwdata, 6788K rodata, 2048K init, 430K bss, 49052K reserved, 65536K cma-reserved, 0K highmem)
578 03:03:39.973252 <6>[ 0.258428] devtmpfs: initialized
579 03:03:39.995108 <6>[ 0.275724] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
580 03:03:40.003408 <6>[ 0.284325] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
581 03:03:40.012604 <6>[ 0.294766] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
582 03:03:40.023251 <6>[ 0.307035] pinctrl core: initialized pinctrl subsystem
583 03:03:40.032576 <6>[ 0.317701] DMI not present or invalid.
584 03:03:40.040945 <6>[ 0.323552] NET: Registered PF_NETLINK/PF_ROUTE protocol family
585 03:03:40.050483 <6>[ 0.332548] DMA: preallocated 256 KiB pool for atomic coherent allocations
586 03:03:40.065620 <6>[ 0.344030] thermal_sys: Registered thermal governor 'step_wise'
587 03:03:40.066120 <6>[ 0.344203] cpuidle: using governor menu
588 03:03:40.093407 <6>[ 0.380128] No ATAGs?
589 03:03:40.098708 <6>[ 0.382767] hw-breakpoint: debug architecture 0x4 unsupported.
590 03:03:40.108776 <6>[ 0.394686] Serial: AMBA PL011 UART driver
591 03:03:40.138885 <6>[ 0.425501] iommu: Default domain type: Translated
592 03:03:40.147041 <6>[ 0.430842] iommu: DMA domain TLB invalidation policy: strict mode
593 03:03:40.174825 <5>[ 0.460762] SCSI subsystem initialized
594 03:03:40.180590 <6>[ 0.465660] usbcore: registered new interface driver usbfs
595 03:03:40.186383 <6>[ 0.471682] usbcore: registered new interface driver hub
596 03:03:40.193172 <6>[ 0.477468] usbcore: registered new device driver usb
597 03:03:40.198889 <6>[ 0.483981] pps_core: LinuxPPS API ver. 1 registered
598 03:03:40.210458 <6>[ 0.489366] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
599 03:03:40.216773 <6>[ 0.499092] PTP clock support registered
600 03:03:40.217257 <6>[ 0.503568] EDAC MC: Ver: 3.0.0
601 03:03:40.269130 <6>[ 0.553271] scmi_core: SCMI protocol bus registered
602 03:03:40.293761 <6>[ 0.579773] vgaarb: loaded
603 03:03:40.299807 <6>[ 0.583546] clocksource: Switched to clocksource dmtimer
604 03:03:40.324312 <6>[ 0.610668] NET: Registered PF_INET protocol family
605 03:03:40.336859 <6>[ 0.616364] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
606 03:03:40.342620 <6>[ 0.625210] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
607 03:03:40.354088 <6>[ 0.634136] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
608 03:03:40.359924 <6>[ 0.642377] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
609 03:03:40.371466 <6>[ 0.650660] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
610 03:03:40.377314 <6>[ 0.658378] TCP: Hash tables configured (established 4096 bind 4096)
611 03:03:40.383126 <6>[ 0.665307] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
612 03:03:40.388971 <6>[ 0.672316] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
613 03:03:40.396576 <6>[ 0.679922] NET: Registered PF_UNIX/PF_LOCAL protocol family
614 03:03:40.482638 <6>[ 0.763596] RPC: Registered named UNIX socket transport module.
615 03:03:40.483290 <6>[ 0.769982] RPC: Registered udp transport module.
616 03:03:40.488318 <6>[ 0.775123] RPC: Registered tcp transport module.
617 03:03:40.494051 <6>[ 0.780228] RPC: Registered tcp-with-tls transport module.
618 03:03:40.507015 <6>[ 0.786149] RPC: Registered tcp NFSv4.1 backchannel transport module.
619 03:03:40.507538 <6>[ 0.793055] PCI: CLS 0 bytes, default 64
620 03:03:40.514228 <5>[ 0.798853] Initialise system trusted keyrings
621 03:03:40.535325 <6>[ 0.818966] Trying to unpack rootfs image as initramfs...
622 03:03:40.613647 <6>[ 0.894036] workingset: timestamp_bits=30 max_order=17 bucket_order=0
623 03:03:40.618326 <6>[ 0.901539] squashfs: version 4.0 (2009/01/31) Phillip Lougher
624 03:03:40.670851 <5>[ 0.957515] NFS: Registering the id_resolver key type
625 03:03:40.676641 <5>[ 0.963098] Key type id_resolver registered
626 03:03:40.682404 <5>[ 0.967747] Key type id_legacy registered
627 03:03:40.688166 <6>[ 0.972182] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
628 03:03:40.697747 <6>[ 0.979374] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
629 03:03:40.769545 <5>[ 1.056335] Key type asymmetric registered
630 03:03:40.775528 <5>[ 1.060858] Asymmetric key parser 'x509' registered
631 03:03:40.786965 <6>[ 1.066357] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
632 03:03:40.787529 <6>[ 1.074279] io scheduler mq-deadline registered
633 03:03:40.792792 <6>[ 1.079211] io scheduler kyber registered
634 03:03:40.797445 <6>[ 1.083680] io scheduler bfq registered
635 03:03:40.901374 <6>[ 1.184449] ledtrig-cpu: registered to indicate activity on CPUs
636 03:03:41.190105 <6>[ 1.472756] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
637 03:03:41.232781 <6>[ 1.519024] msm_serial: driver initialized
638 03:03:41.238603 <6>[ 1.524031] SuperH (H)SCI(F) driver initialized
639 03:03:41.244584 <6>[ 1.529144] STMicroelectronics ASC driver initialized
640 03:03:41.249867 <6>[ 1.534813] STM32 USART driver initialized
641 03:03:41.353201 <6>[ 1.639119] brd: module loaded
642 03:03:41.388762 <6>[ 1.674574] loop: module loaded
643 03:03:41.429067 <6>[ 1.714953] CAN device driver interface
644 03:03:41.435823 <6>[ 1.719942] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
645 03:03:41.441472 <6>[ 1.727103] e1000e: Intel(R) PRO/1000 Network Driver
646 03:03:41.447278 <6>[ 1.732491] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
647 03:03:41.453003 <6>[ 1.738956] igb: Intel(R) Gigabit Ethernet Network Driver
648 03:03:41.461345 <6>[ 1.744804] igb: Copyright (c) 2007-2014 Intel Corporation.
649 03:03:41.473124 <6>[ 1.754197] pegasus: Pegasus/Pegasus II USB Ethernet driver
650 03:03:41.479075 <6>[ 1.760263] usbcore: registered new interface driver pegasus
651 03:03:41.481861 <6>[ 1.766437] usbcore: registered new interface driver asix
652 03:03:41.487695 <6>[ 1.772290] usbcore: registered new interface driver ax88179_178a
653 03:03:41.493437 <6>[ 1.778894] usbcore: registered new interface driver cdc_ether
654 03:03:41.499149 <6>[ 1.785216] usbcore: registered new interface driver smsc75xx
655 03:03:41.507779 <6>[ 1.791427] usbcore: registered new interface driver smsc95xx
656 03:03:41.513569 <6>[ 1.797668] usbcore: registered new interface driver net1080
657 03:03:41.519574 <6>[ 1.803806] usbcore: registered new interface driver cdc_subset
658 03:03:41.527937 <6>[ 1.810191] usbcore: registered new interface driver zaurus
659 03:03:41.532905 <6>[ 1.816255] usbcore: registered new interface driver cdc_ncm
660 03:03:41.541891 <6>[ 1.825856] usbcore: registered new interface driver usb-storage
661 03:03:41.551154 <6>[ 1.836981] i2c_dev: i2c /dev entries driver
662 03:03:41.571885 <5>[ 1.855163] cpuidle: enable-method property 'ti,am3352' found operations
663 03:03:41.585266 <6>[ 1.864621] sdhci: Secure Digital Host Controller Interface driver
664 03:03:41.585855 <6>[ 1.871277] sdhci: Copyright(c) Pierre Ossman
665 03:03:41.592135 <6>[ 1.877717] Synopsys Designware Multimedia Card Interface Driver
666 03:03:41.601222 <6>[ 1.885632] sdhci-pltfm: SDHCI platform and OF driver helper
667 03:03:41.615127 <6>[ 1.895442] usbcore: registered new interface driver usbhid
668 03:03:41.615619 <6>[ 1.901471] usbhid: USB HID core driver
669 03:03:41.627833 <6>[ 1.912866] NET: Registered PF_INET6 protocol family
670 03:03:42.088353 <6>[ 2.374973] Segment Routing with IPv6
671 03:03:42.094051 <6>[ 2.379121] In-situ OAM (IOAM) with IPv6
672 03:03:42.100752 <6>[ 2.383640] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
673 03:03:42.108260 <6>[ 2.390893] NET: Registered PF_PACKET protocol family
674 03:03:42.113965 <6>[ 2.396463] can: controller area network core
675 03:03:42.114446 <6>[ 2.401287] NET: Registered PF_CAN protocol family
676 03:03:42.119788 <6>[ 2.406515] can: raw protocol
677 03:03:42.125526 <6>[ 2.409840] can: broadcast manager protocol
678 03:03:42.132402 <6>[ 2.414447] can: netlink gateway - max_hops=1
679 03:03:42.132888 <5>[ 2.419937] Key type dns_resolver registered
680 03:03:42.138172 <6>[ 2.425015] ThumbEE CPU extension supported.
681 03:03:42.144393 <5>[ 2.429708] Registering SWP/SWPB emulation handler
682 03:03:42.152548 <3>[ 2.435400] omap_voltage_late_init: Voltage driver support not added
683 03:03:42.362319 <5>[ 2.636371] Loading compiled-in X.509 certificates
684 03:03:42.479163 <6>[ 2.753070] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
685 03:03:42.485510 <6>[ 2.769720] pinctrl-single 44e10800.pinmux: 142 pins, size 568
686 03:03:42.512630 <3>[ 2.793351] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
687 03:03:42.722367 <3>[ 3.003018] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
688 03:03:42.918437 <6>[ 3.204312] OMAP GPIO hardware version 0.1
689 03:03:42.939875 <6>[ 3.222915] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
690 03:03:43.042426 <4>[ 3.325225] at24 2-0054: supply vcc not found, using dummy regulator
691 03:03:43.079527 <4>[ 3.362303] at24 2-0055: supply vcc not found, using dummy regulator
692 03:03:43.120256 <4>[ 3.403049] at24 2-0056: supply vcc not found, using dummy regulator
693 03:03:43.156595 <4>[ 3.439404] at24 2-0057: supply vcc not found, using dummy regulator
694 03:03:43.193711 <6>[ 3.477296] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
695 03:03:43.270577 <3>[ 3.550150] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
696 03:03:43.295076 <6>[ 3.570941] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
697 03:03:43.316987 <4>[ 3.596999] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
698 03:03:43.324600 <4>[ 3.606191] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
699 03:03:43.461162 <6>[ 3.744145] omap_rng 48310000.rng: Random Number Generator ver. 20
700 03:03:43.484541 <5>[ 3.770313] random: crng init done
701 03:03:43.532595 <6>[ 3.814027] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
702 03:03:43.560334 <6>[ 3.845657] Freeing initrd memory: 14448K
703 03:03:43.615418 <6>[ 3.895983] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
704 03:03:43.621200 <6>[ 3.906309] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
705 03:03:43.633090 <6>[ 3.913644] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
706 03:03:43.638756 <6>[ 3.921099] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
707 03:03:43.650390 <6>[ 3.929231] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
708 03:03:43.657682 <6>[ 3.940873] cpsw-switch 4a100000.switch: Detected MACID = 78:a5:04:e2:4c:3d
709 03:03:43.669925 <5>[ 3.949906] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
710 03:03:43.698517 <3>[ 3.979581] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
711 03:03:43.704261 <6>[ 3.988170] edma 49000000.dma: TI EDMA DMA engine driver
712 03:03:43.774413 <3>[ 4.055727] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
713 03:03:43.790079 <6>[ 4.070058] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
714 03:03:43.802906 <3>[ 4.087120] l3-aon-clkctrl:0000:0: failed to disable
715 03:03:43.853676 <6>[ 4.134658] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
716 03:03:43.859260 <6>[ 4.144132] printk: legacy console [ttyS0] enabled
717 03:03:43.865113 <6>[ 4.144132] printk: legacy console [ttyS0] enabled
718 03:03:43.870670 <6>[ 4.154472] printk: legacy bootconsole [omap8250] disabled
719 03:03:43.876487 <6>[ 4.154472] printk: legacy bootconsole [omap8250] disabled
720 03:03:43.914269 <4>[ 4.194313] tps65217-pmic: Failed to locate of_node [id: -1]
721 03:03:43.917755 <4>[ 4.201716] tps65217-bl: Failed to locate of_node [id: -1]
722 03:03:43.934299 <6>[ 4.221341] tps65217 0-0024: TPS65217 ID 0xe version 1.2
723 03:03:43.952723 <6>[ 4.228295] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
724 03:03:43.964453 <6>[ 4.241980] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
725 03:03:43.970204 <6>[ 4.253890] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
726 03:03:43.992519 <6>[ 4.273991] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
727 03:03:43.998459 <6>[ 4.283047] sdhci-omap 48060000.mmc: Got CD GPIO
728 03:03:44.006482 <4>[ 4.288248] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
729 03:03:44.021081 <4>[ 4.301654] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
730 03:03:44.027323 <4>[ 4.310417] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
731 03:03:44.036825 <4>[ 4.319018] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
732 03:03:44.136261 <6>[ 4.418705] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
733 03:03:44.164054 <6>[ 4.446443] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
734 03:03:44.201585 <6>[ 4.481701] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
735 03:03:44.208206 <6>[ 4.491051] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
736 03:03:44.250174 <6>[ 4.535017] mmc1: new high speed MMC card at address 0001
737 03:03:44.259404 <6>[ 4.544167] mmcblk1: mmc1:0001 MMC04G 3.60 GiB
738 03:03:44.272443 <6>[ 4.557201] mmcblk1boot0: mmc1:0001 MMC04G 2.00 MiB
739 03:03:44.283051 <6>[ 4.568338] mmcblk1boot1: mmc1:0001 MMC04G 2.00 MiB
740 03:03:44.291850 <6>[ 4.575668] mmc0: new high speed SDHC card at address 1234
741 03:03:44.300230 <6>[ 4.585569] mmcblk0: mmc0:1234 SA32G 29.1 GiB
742 03:03:44.312249 <6>[ 4.591829] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
743 03:03:44.321938 <6>[ 4.609645] mmcblk0: p1
744 03:03:44.335680 <6>[ 4.618775] mmcblk1rpmb: mmc1:0001 MMC04G 128 KiB, chardev (236:0)
745 03:03:46.473369 <6>[ 6.754583] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
746 03:03:46.536522 <5>[ 6.783575] Sending DHCP requests ., OK
747 03:03:46.547901 <6>[ 6.827868] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.12
748 03:03:46.548421 <6>[ 6.835933] IP-Config: Complete:
749 03:03:46.559128 <6>[ 6.839450] device=eth0, hwaddr=78:a5:04:e2:4c:3d, ipaddr=192.168.6.12, mask=255.255.255.0, gw=192.168.6.1
750 03:03:46.564909 <6>[ 6.849903] host=192.168.6.12, domain=, nis-domain=(none)
751 03:03:46.576852 <6>[ 6.856066] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
752 03:03:46.577365 <6>[ 6.856083] nameserver0=10.255.253.1
753 03:03:46.582642 <6>[ 6.868212] clk: Disabling unused clocks
754 03:03:46.588282 <6>[ 6.872666] PM: genpd: Disabling unused power domains
755 03:03:46.606935 <6>[ 6.884777] Freeing unused kernel image (initmem) memory: 2048K
756 03:03:46.607389 <6>[ 6.892719] Run /init as init process
757 03:03:46.630076 Loading, please wait...
758 03:03:46.705650 Starting systemd-udevd version 252.22-1~deb12u1
759 03:03:49.790054 <4>[ 10.070643] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
760 03:03:49.935766 <4>[ 10.215933] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
761 03:03:50.076816 <6>[ 10.364102] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
762 03:03:50.087118 <6>[ 10.369777] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
763 03:03:50.339166 <6>[ 10.625069] hub 1-0:1.0: USB hub found
764 03:03:50.384583 <6>[ 10.670349] hub 1-0:1.0: 1 port detected
765 03:03:50.582063 <6>[ 10.866971] tda998x 0-0070: found TDA19988
766 03:03:53.694720 Begin: Loading essential drivers ... done.
767 03:03:53.701159 Begin: Running /scripts/init-premount ... done.
768 03:03:53.712196 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
769 03:03:53.717743 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
770 03:03:53.722151 Device /sys/class/net/eth0 found
771 03:03:53.722448 done.
772 03:03:53.801015 Begin: Waiting up to 180 secs for any network device to become available ... done.
773 03:03:53.899484 IP-Config: eth0 hardware address 78:a5:04:e2:4c:3d mtu 1500 DHCP
774 03:03:53.923092 IP-Config: eth0 guessed broadcast address 192.168.6.255
775 03:03:53.928675 IP-Config: eth0 complete (dhcp from 192.168.6.1):
776 03:03:53.934311 address: 192.168.6.12 broadcast: 192.168.6.255 netmask: 255.255.255.0
777 03:03:53.945488 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
778 03:03:53.945834 rootserver: 192.168.6.1 rootpath:
779 03:03:53.949001 filename :
780 03:03:54.060057 done.
781 03:03:54.072176 Begin: Running /scripts/nfs-bottom ... done.
782 03:03:54.137515 Begin: Running /scripts/init-bottom ... done.
783 03:03:55.590112 <30>[ 15.873457] systemd[1]: System time before build time, advancing clock.
784 03:03:55.804902 <30>[ 16.060391] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
785 03:03:55.808368 <30>[ 16.094359] systemd[1]: Detected architecture arm.
786 03:03:55.824064
787 03:03:55.824438 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
788 03:03:55.824655
789 03:03:55.849485 <30>[ 16.133270] systemd[1]: Hostname set to <debian-bookworm-armhf>.
790 03:03:58.015214 <30>[ 18.297963] systemd[1]: Queued start job for default target graphical.target.
791 03:03:58.031810 <30>[ 18.312470] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
792 03:03:58.038631 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
793 03:03:58.066132 <30>[ 18.345973] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
794 03:03:58.073616 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
795 03:03:58.098197 <30>[ 18.379750] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
796 03:03:58.111305 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
797 03:03:58.133964 <30>[ 18.415445] systemd[1]: Created slice user.slice - User and Session Slice.
798 03:03:58.140612 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
799 03:03:58.169447 <30>[ 18.444935] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
800 03:03:58.175621 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
801 03:03:58.193363 <30>[ 18.474742] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
802 03:03:58.202390 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
803 03:03:58.234184 <30>[ 18.504594] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
804 03:03:58.240562 <30>[ 18.525043] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
805 03:03:58.249138 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
806 03:03:58.272451 <30>[ 18.554063] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
807 03:03:58.280459 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
808 03:03:58.303102 <30>[ 18.584400] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
809 03:03:58.311916 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
810 03:03:58.332997 <30>[ 18.614554] systemd[1]: Reached target paths.target - Path Units.
811 03:03:58.338049 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
812 03:03:58.362646 <30>[ 18.644230] systemd[1]: Reached target remote-fs.target - Remote File Systems.
813 03:03:58.370007 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
814 03:03:58.392744 <30>[ 18.674123] systemd[1]: Reached target slices.target - Slice Units.
815 03:03:58.398052 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
816 03:03:58.422774 <30>[ 18.704329] systemd[1]: Reached target swap.target - Swaps.
817 03:03:58.426823 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
818 03:03:58.453030 <30>[ 18.734380] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
819 03:03:58.461092 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
820 03:03:58.485192 <30>[ 18.766780] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
821 03:03:58.498138 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
822 03:03:58.582668 <30>[ 18.859886] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
823 03:03:58.596219 <30>[ 18.877277] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
824 03:03:58.604551 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
825 03:03:58.623734 <30>[ 18.905219] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
826 03:03:58.631142 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
827 03:03:58.656281 <30>[ 18.937213] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
828 03:03:58.664397 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
829 03:03:58.692684 <30>[ 18.974552] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
830 03:03:58.703486 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
831 03:03:58.724386 <30>[ 19.005007] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
832 03:03:58.731926 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
833 03:03:58.760080 <30>[ 19.035367] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
834 03:03:58.778750 <30>[ 19.053951] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
835 03:03:58.826869 <30>[ 19.109302] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
836 03:03:58.852962 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
837 03:03:58.905028 <30>[ 19.187070] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
838 03:03:58.932757 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
839 03:03:59.026031 <30>[ 19.307089] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
840 03:03:59.052395 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
841 03:03:59.113466 <30>[ 19.395173] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
842 03:03:59.141642 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
843 03:03:59.193291 <30>[ 19.475387] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
844 03:03:59.212211 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
845 03:03:59.235101 <30>[ 19.517677] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
846 03:03:59.259500 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
847 03:03:59.316070 <30>[ 19.597158] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
848 03:03:59.342098 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
849 03:03:59.392886 <30>[ 19.674834] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
850 03:03:59.413654 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
851 03:03:59.471714 <30>[ 19.754748] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
852 03:03:59.493173 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
853 03:03:59.521482 <28>[ 19.795978] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
854 03:03:59.530093 <28>[ 19.811550] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
855 03:03:59.573343 <30>[ 19.857119] systemd[1]: Starting systemd-journald.service - Journal Service...
856 03:03:59.590445 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
857 03:03:59.662948 <30>[ 19.945066] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
858 03:03:59.676856 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
859 03:03:59.703271 <30>[ 19.985537] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
860 03:03:59.752622 Starting [0;1;39msystemd-network-g… units from Kernel command line...
861 03:03:59.819008 <30>[ 20.099798] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
862 03:03:59.872910 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
863 03:03:59.946682 <30>[ 20.228286] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
864 03:04:00.014675 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
865 03:04:00.082566 <30>[ 20.365069] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
866 03:04:00.131836 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
867 03:04:00.155692 <30>[ 20.438048] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
868 03:04:00.203166 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
869 03:04:00.227159 <30>[ 20.508295] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
870 03:04:00.254296 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
871 03:04:00.363535 <30>[ 20.646553] systemd[1]: modprobe@configfs.service: Deactivated successfully.
872 03:04:00.412492 <30>[ 20.694160] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
873 03:04:00.421449 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
874 03:04:00.443051 <30>[ 20.726338] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
875 03:04:00.472731 <30>[ 20.755082] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
876 03:04:00.497840 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
877 03:04:00.523588 <30>[ 20.805295] systemd[1]: Started systemd-journald.service - Journal Service.
878 03:04:00.530452 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
879 03:04:00.573584 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
880 03:04:00.604887 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
881 03:04:00.633853 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
882 03:04:00.657311 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
883 03:04:00.692551 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
884 03:04:00.722518 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
885 03:04:00.745827 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
886 03:04:00.777009 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
887 03:04:00.841987 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
888 03:04:00.888403 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
889 03:04:00.943795 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
890 03:04:01.004196 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
891 03:04:01.056894 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
892 03:04:01.243810 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
893 03:04:01.335635 <46>[ 21.618214] systemd-journald[163]: Received client request to flush runtime journal.
894 03:04:01.382526 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
895 03:04:01.523300 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
896 03:04:02.291138 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
897 03:04:02.345125 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
898 03:04:03.064834 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
899 03:04:03.184678 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
900 03:04:03.204473 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
901 03:04:03.222167 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
902 03:04:03.292856 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
903 03:04:03.341702 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
904 03:04:04.267060 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
905 03:04:04.333433 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
906 03:04:04.602517 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
907 03:04:04.693723 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
908 03:04:04.771752 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
909 03:04:06.753062 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
910 03:04:06.998341 <5>[ 27.281124] cfg80211: Loading compiled-in X.509 certificates for regulatory database
911 03:04:07.232466 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
912 03:04:08.207104 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
913 03:04:08.422216 <5>[ 28.707122] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
914 03:04:08.503054 <5>[ 28.787250] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
915 03:04:08.539401 <4>[ 28.821934] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
916 03:04:08.545305 <6>[ 28.831057] cfg80211: failed to load regulatory.db
917 03:04:09.617238 <46>[ 29.890800] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
918 03:04:09.717592 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
919 03:04:09.788872 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0<46>[ 30.060931] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
920 03:04:09.792336 m - Network Configuration.
921 03:04:18.726982 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
922 03:04:18.751202 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
923 03:04:18.776667 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
924 03:04:18.809209 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
925 03:04:18.872641 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
926 03:04:18.920542 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
927 03:04:18.984930 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
928 03:04:19.034462 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
929 03:04:19.082617 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
930 03:04:19.111503 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
931 03:04:19.136583 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
932 03:04:19.177483 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
933 03:04:19.205764 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
934 03:04:19.254668 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
935 03:04:19.292912 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
936 03:04:19.306082 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
937 03:04:19.339277 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
938 03:04:19.367568 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
939 03:04:19.398747 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
940 03:04:19.422309 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
941 03:04:19.452151 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
942 03:04:19.472302 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
943 03:04:19.498814 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
944 03:04:19.572494 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
945 03:04:19.621596 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
946 03:04:19.742272 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
947 03:04:19.807233 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
948 03:04:19.883617 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
949 03:04:19.937789 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
950 03:04:19.961516 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
951 03:04:20.118578 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
952 03:04:20.172882 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
953 03:04:20.236167 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
954 03:04:20.260948 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
955 03:04:20.291786 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
956 03:04:20.533908 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
957 03:04:20.889092 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
958 03:04:20.941839 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
959 03:04:20.966211 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
960 03:04:21.056120 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
961 03:04:21.249363 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
962 03:04:21.428832
963 03:04:21.432741 Debian GNU/Linux 12 debian-worm-armhf login: root (automatic login)
964 03:04:21.433285
965 03:04:21.776823 Linux debian-bookworm-armhf 6.12.0-rc7 #1 SMP Tue Nov 12 02:45:50 UTC 2024 armv7l
966 03:04:21.777449
967 03:04:21.782484 The programs included with the Debian GNU/Linux system are free software;
968 03:04:21.788041 the exact distribution terms for each program are described in the
969 03:04:21.793578 individual files in /usr/share/doc/*/copyright.
970 03:04:21.793889
971 03:04:21.801753 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
972 03:04:21.802303 permitted by applicable law.
973 03:04:26.418679 Unable to match end of the kernel message
975 03:04:26.420313 Setting prompt string to ['/ #']
976 03:04:26.420899 end: 2.4.4.1 login-action (duration 00:00:47) [common]
978 03:04:26.422292 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
979 03:04:26.422856 start: 2.4.5 expect-shell-connection (timeout 00:03:14) [common]
980 03:04:26.423338 Setting prompt string to ['/ #']
981 03:04:26.423780 Forcing a shell prompt, looking for ['/ #']
983 03:04:26.474814 / #
984 03:04:26.475484 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
985 03:04:26.476034 Waiting using forced prompt support (timeout 00:02:30)
986 03:04:26.480435
987 03:04:26.489269 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
988 03:04:26.489894 start: 2.4.6 export-device-env (timeout 00:03:14) [common]
989 03:04:26.490346 Sending with 10 millisecond of delay
991 03:04:31.479430 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/978069/extract-nfsrootfs-hd0p7fiu'
992 03:04:31.490517 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/978069/extract-nfsrootfs-hd0p7fiu'
993 03:04:31.491428 Sending with 10 millisecond of delay
995 03:04:33.590871 / # export NFS_SERVER_IP='192.168.6.2'
996 03:04:33.601700 export NFS_SERVER_IP='192.168.6.2'
997 03:04:33.602752 end: 2.4.6 export-device-env (duration 00:00:07) [common]
998 03:04:33.603123 end: 2.4 uboot-commands (duration 00:01:53) [common]
999 03:04:33.603497 end: 2 uboot-action (duration 00:01:53) [common]
1000 03:04:33.603854 start: 3 lava-test-retry (timeout 00:06:56) [common]
1001 03:04:33.604248 start: 3.1 lava-test-shell (timeout 00:06:56) [common]
1002 03:04:33.604530 Using namespace: common
1004 03:04:33.705368 / # #
1005 03:04:33.706082 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1006 03:04:33.710798 #
1007 03:04:33.717256 Using /lava-978069
1009 03:04:33.818082 / # export SHELL=/bin/bash
1010 03:04:33.823329 export SHELL=/bin/bash
1012 03:04:33.930214 / # . /lava-978069/environment
1013 03:04:33.935659 . /lava-978069/environment
1015 03:04:34.051737 / # /lava-978069/bin/lava-test-runner /lava-978069/0
1016 03:04:34.052336 Test shell timeout: 10s (minimum of the action and connection timeout)
1017 03:04:34.057074 /lava-978069/bin/lava-test-runner /lava-978069/0
1018 03:04:34.472576 + export TESTRUN_ID=0_timesync-off
1019 03:04:34.480437 + TESTRUN_ID=0_timesync-off
1020 03:04:34.481022 + cd /lava-978069/0/tests/0_timesync-off
1021 03:04:34.481534 ++ cat uuid
1022 03:04:34.497162 + UUID=978069_1.6.2.4.1
1023 03:04:34.497781 + set +x
1024 03:04:34.505660 <LAVA_SIGNAL_STARTRUN 0_timesync-off 978069_1.6.2.4.1>
1025 03:04:34.506216 + systemctl stop systemd-timesyncd
1026 03:04:34.507021 Received signal: <STARTRUN> 0_timesync-off 978069_1.6.2.4.1
1027 03:04:34.507555 Starting test lava.0_timesync-off (978069_1.6.2.4.1)
1028 03:04:34.508198 Skipping test definition patterns.
1029 03:04:34.806621 + set +x
1030 03:04:34.807277 <LAVA_SIGNAL_ENDRUN 0_timesync-off 978069_1.6.2.4.1>
1031 03:04:34.808074 Received signal: <ENDRUN> 0_timesync-off 978069_1.6.2.4.1
1032 03:04:34.808634 Ending use of test pattern.
1033 03:04:34.809100 Ending test lava.0_timesync-off (978069_1.6.2.4.1), duration 0.30
1035 03:04:34.975783 + export TESTRUN_ID=1_kselftest-dt
1036 03:04:34.983647 + TESTRUN_ID=1_kselftest-dt
1037 03:04:34.984211 + cd /lava-978069/0/tests/1_kselftest-dt
1038 03:04:34.984690 ++ cat uuid
1039 03:04:34.999574 + UUID=978069_1.6.2.4.5
1040 03:04:35.000147 + set +x
1041 03:04:35.005173 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 978069_1.6.2.4.5>
1042 03:04:35.005702 + cd ./automated/linux/kselftest/
1043 03:04:35.006470 Received signal: <STARTRUN> 1_kselftest-dt 978069_1.6.2.4.5
1044 03:04:35.006958 Starting test lava.1_kselftest-dt (978069_1.6.2.4.5)
1045 03:04:35.007505 Skipping test definition patterns.
1046 03:04:35.033407 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/next/pending-fixes/v6.12-rc7-95-g96203094619a7/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g next -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1047 03:04:35.134226 INFO: install_deps skipped
1048 03:04:35.733971 --2024-11-12 03:04:35-- http://storage.kernelci.org/next/pending-fixes/v6.12-rc7-95-g96203094619a7/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1049 03:04:35.769682 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1050 03:04:35.908328 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1051 03:04:36.048455 HTTP request sent, awaiting response... 200 OK
1052 03:04:36.049081 Length: 4107484 (3.9M) [application/octet-stream]
1053 03:04:36.053937 Saving to: 'kselftest_armhf.tar.gz'
1054 03:04:36.054435
1055 03:04:37.690936
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 44.73K 166KB/s
kselftest_armhf.tar 5%[> ] 203.20K 375KB/s
kselftest_armhf.tar 20%[===> ] 828.01K 1019KB/s
kselftest_armhf.tar 32%[=====> ] 1.28M 1.27MB/s
kselftest_armhf.tar 66%[============> ] 2.61M 2.13MB/s
kselftest_armhf.tar 76%[==============> ] 2.99M 2.07MB/s
kselftest_armhf.tar 100%[===================>] 3.92M 2.39MB/s in 1.6s
1056 03:04:37.691643
1057 03:04:38.196733 2024-11-12 03:04:37 (2.39 MB/s) - 'kselftest_armhf.tar.gz' saved [4107484/4107484]
1058 03:04:38.197421
1059 03:04:51.029179 skiplist:
1060 03:04:51.029614 ========================================
1061 03:04:51.034942 ========================================
1062 03:04:51.130590 dt:test_unprobed_devices.sh
1063 03:04:51.158688 ============== Tests to run ===============
1064 03:04:51.167910 dt:test_unprobed_devices.sh
1065 03:04:51.171956 ===========End Tests to run ===============
1066 03:04:51.179974 shardfile-dt pass
1067 03:04:51.398264 <12>[ 71.686908] kselftest: Running tests in dt
1068 03:04:51.428993 TAP version 13
1069 03:04:51.450440 1..1
1070 03:04:51.503956 # timeout set to 45
1071 03:04:51.504593 # selftests: dt: test_unprobed_devices.sh
1072 03:04:52.261310 # TAP version 13
1073 03:05:17.158262 # 1..257
1074 03:05:17.321963 # ok 1 / # SKIP
1075 03:05:17.343317 # ok 2 /clk_mcasp0
1076 03:05:17.414988 # ok 3 /clk_mcasp0_fixed # SKIP
1077 03:05:17.486638 # ok 4 /cpus/cpu@0 # SKIP
1078 03:05:17.558682 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1079 03:05:17.578624 # ok 6 /fixedregulator0
1080 03:05:17.600404 # ok 7 /leds
1081 03:05:17.625304 # ok 8 /ocp
1082 03:05:17.649702 # ok 9 /ocp/interconnect@44c00000
1083 03:05:17.672997 # ok 10 /ocp/interconnect@44c00000/segment@0
1084 03:05:17.691378 # ok 11 /ocp/interconnect@44c00000/segment@100000
1085 03:05:17.716224 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1086 03:05:17.786562 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1087 03:05:17.811102 # ok 14 /ocp/interconnect@44c00000/segment@200000
1088 03:05:17.835206 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1089 03:05:17.941911 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1090 03:05:18.015076 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1091 03:05:18.087504 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1092 03:05:18.155850 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1093 03:05:18.228053 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1094 03:05:18.298524 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1095 03:05:18.375723 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1096 03:05:18.447713 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1097 03:05:18.517794 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1098 03:05:18.586324 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1099 03:05:18.661141 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1100 03:05:18.733078 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1101 03:05:18.804538 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1102 03:05:18.876770 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1103 03:05:18.945906 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1104 03:05:19.014875 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1105 03:05:19.084554 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1106 03:05:19.156776 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1107 03:05:19.228844 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1108 03:05:19.304893 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1109 03:05:19.375401 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1110 03:05:19.447378 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1111 03:05:19.516204 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1112 03:05:19.588641 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1113 03:05:19.657954 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1114 03:05:19.729650 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1115 03:05:19.801569 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1116 03:05:19.872165 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1117 03:05:19.944990 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1118 03:05:20.016565 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1119 03:05:20.090300 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1120 03:05:20.160919 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1121 03:05:20.231644 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1122 03:05:20.302957 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1123 03:05:20.374238 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1124 03:05:20.445810 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1125 03:05:20.519146 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1126 03:05:20.589375 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1127 03:05:20.665793 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1128 03:05:20.736824 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1129 03:05:20.809335 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1130 03:05:20.878610 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1131 03:05:20.953428 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1132 03:05:21.024462 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1133 03:05:21.097081 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1134 03:05:21.167782 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1135 03:05:21.236388 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1136 03:05:21.307634 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1137 03:05:21.382426 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1138 03:05:21.453583 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1139 03:05:21.525861 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1140 03:05:21.597612 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1141 03:05:21.664496 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1142 03:05:21.735472 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1143 03:05:21.807506 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1144 03:05:21.883750 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1145 03:05:21.953597 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1146 03:05:22.028226 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1147 03:05:22.098369 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1148 03:05:22.171204 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1149 03:05:22.247122 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1150 03:05:22.314613 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1151 03:05:22.386164 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1152 03:05:22.458148 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1153 03:05:22.532272 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1154 03:05:22.606647 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1155 03:05:22.677932 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1156 03:05:22.745316 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1157 03:05:22.816545 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1158 03:05:22.891909 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1159 03:05:22.964531 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1160 03:05:23.035621 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1161 03:05:23.107111 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1162 03:05:23.174682 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1163 03:05:23.246796 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1164 03:05:23.318198 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1165 03:05:23.391445 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1166 03:05:23.466895 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1167 03:05:23.535137 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1168 03:05:23.557483 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1169 03:05:23.578917 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1170 03:05:23.603168 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1171 03:05:23.626764 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1172 03:05:23.650574 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1173 03:05:23.674332 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1174 03:05:23.698266 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1175 03:05:23.720214 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1176 03:05:23.825242 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1177 03:05:23.854385 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1178 03:05:23.876770 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1179 03:05:23.902275 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1180 03:05:24.006983 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1181 03:05:24.078511 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1182 03:05:24.153934 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1183 03:05:24.221723 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1184 03:05:24.293218 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1185 03:05:24.365140 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1186 03:05:24.437579 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1187 03:05:24.510659 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1188 03:05:24.584878 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1189 03:05:24.658981 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1190 03:05:24.729621 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1191 03:05:24.798366 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1192 03:05:24.874020 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1193 03:05:24.944012 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1194 03:05:25.015705 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1195 03:05:25.087526 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1196 03:05:25.116192 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1197 03:05:25.185887 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1198 03:05:25.255294 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1199 03:05:25.326218 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1200 03:05:25.347565 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1201 03:05:25.416630 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1202 03:05:25.439287 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1203 03:05:25.513909 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1204 03:05:25.534776 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1205 03:05:25.560568 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1206 03:05:25.578809 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1207 03:05:25.602925 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1208 03:05:25.625152 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1209 03:05:25.649786 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1210 03:05:25.675662 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1211 03:05:25.750219 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1212 03:05:25.770485 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1213 03:05:25.794382 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1214 03:05:25.866256 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1215 03:05:25.937150 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1216 03:05:25.957568 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1217 03:05:26.058081 # not ok 144 /ocp/interconnect@47c00000
1218 03:05:26.128882 # not ok 145 /ocp/interconnect@47c00000/segment@0
1219 03:05:26.152145 # ok 146 /ocp/interconnect@48000000
1220 03:05:26.179527 # ok 147 /ocp/interconnect@48000000/segment@0
1221 03:05:26.197606 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1222 03:05:26.221522 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1223 03:05:26.246456 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1224 03:05:26.266760 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1225 03:05:26.290676 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1226 03:05:26.317546 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1227 03:05:26.337138 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1228 03:05:26.409491 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1229 03:05:26.481424 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1230 03:05:26.502659 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1231 03:05:26.527559 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1232 03:05:26.549498 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1233 03:05:26.575220 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1234 03:05:26.600403 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1235 03:05:26.624495 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1236 03:05:26.644602 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1237 03:05:26.671312 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1238 03:05:26.693667 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1239 03:05:26.715318 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1240 03:05:26.740362 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1241 03:05:26.764815 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1242 03:05:26.782569 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1243 03:05:26.811288 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1244 03:05:26.833823 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1245 03:05:26.855408 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1246 03:05:26.881798 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1247 03:05:26.904287 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1248 03:05:26.922300 # ok 175 /ocp/interconnect@48000000/segment@100000
1249 03:05:26.947676 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1250 03:05:26.971630 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1251 03:05:27.044820 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1252 03:05:27.118538 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1253 03:05:27.194520 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1254 03:05:27.266501 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1255 03:05:27.337191 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1256 03:05:27.405832 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1257 03:05:27.476205 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1258 03:05:27.554234 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1259 03:05:27.569451 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1260 03:05:27.592795 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1261 03:05:27.616655 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1262 03:05:27.640048 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1263 03:05:27.663193 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1264 03:05:27.687841 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1265 03:05:27.710143 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1266 03:05:27.734289 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1267 03:05:27.762111 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1268 03:05:27.784739 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1269 03:05:27.806778 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1270 03:05:27.828457 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1271 03:05:27.852071 # ok 198 /ocp/interconnect@48000000/segment@200000
1272 03:05:27.880308 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1273 03:05:27.953915 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1274 03:05:27.973035 # ok 201 /ocp/interconnect@48000000/segment@300000
1275 03:05:27.995420 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1276 03:05:28.023331 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1277 03:05:28.045499 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1278 03:05:28.071951 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1279 03:05:28.094671 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1280 03:05:28.122383 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1281 03:05:28.185774 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1282 03:05:28.205472 # ok 209 /ocp/interconnect@4a000000
1283 03:05:28.232673 # ok 210 /ocp/interconnect@4a000000/segment@0
1284 03:05:28.257759 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1285 03:05:28.283807 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1286 03:05:28.306165 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1287 03:05:28.326379 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1288 03:05:28.401926 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1289 03:05:28.506819 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1290 03:05:28.575955 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1291 03:05:28.679670 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1292 03:05:28.748606 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1293 03:05:28.819269 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1294 03:05:28.917866 # not ok 221 /ocp/interconnect@4b140000
1295 03:05:28.989799 # not ok 222 /ocp/interconnect@4b140000/segment@0
1296 03:05:29.060447 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1297 03:05:29.083436 # ok 224 /ocp/target-module@40300000
1298 03:05:29.104348 # ok 225 /ocp/target-module@40300000/sram@0
1299 03:05:29.177720 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1300 03:05:29.253151 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1301 03:05:29.271908 # ok 228 /ocp/target-module@47400000
1302 03:05:29.298426 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1303 03:05:29.321822 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1304 03:05:29.343113 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1305 03:05:29.366753 # ok 232 /ocp/target-module@47400000/usb@1400
1306 03:05:29.390354 # ok 233 /ocp/target-module@47400000/usb@1800
1307 03:05:29.411781 # ok 234 /ocp/target-module@47810000
1308 03:05:29.431294 # ok 235 /ocp/target-module@49000000
1309 03:05:29.454424 # ok 236 /ocp/target-module@49000000/dma@0
1310 03:05:29.475724 # ok 237 /ocp/target-module@49800000
1311 03:05:29.498649 # ok 238 /ocp/target-module@49800000/dma@0
1312 03:05:29.520722 # ok 239 /ocp/target-module@49900000
1313 03:05:29.544340 # ok 240 /ocp/target-module@49900000/dma@0
1314 03:05:29.569840 # ok 241 /ocp/target-module@49a00000
1315 03:05:29.594028 # ok 242 /ocp/target-module@49a00000/dma@0
1316 03:05:29.609657 # ok 243 /ocp/target-module@4c000000
1317 03:05:29.683339 # not ok 244 /ocp/target-module@4c000000/emif@0
1318 03:05:29.708944 # ok 245 /ocp/target-module@50000000
1319 03:05:29.731357 # ok 246 /ocp/target-module@53100000
1320 03:05:29.802178 # not ok 247 /ocp/target-module@53100000/sham@0
1321 03:05:29.819084 # ok 248 /ocp/target-module@53500000
1322 03:05:29.892796 # not ok 249 /ocp/target-module@53500000/aes@0
1323 03:05:29.912459 # ok 250 /ocp/target-module@56000000
1324 03:05:30.021230 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1325 03:05:30.089601 # ok 252 /opp-table # SKIP
1326 03:05:30.154595 # ok 253 /soc # SKIP
1327 03:05:30.180226 # ok 254 /sound
1328 03:05:30.207569 # ok 255 /target-module@4b000000
1329 03:05:30.226882 # ok 256 /target-module@4b000000/target-module@140000
1330 03:05:30.247632 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1331 03:05:30.255890 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1332 03:05:30.264846 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1333 03:05:32.575449 dt_test_unprobed_devices_sh_ skip
1334 03:05:32.580916 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1335 03:05:32.586525 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1336 03:05:32.587018 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1337 03:05:32.595410 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1338 03:05:32.595912 dt_test_unprobed_devices_sh_fixedregulator0 pass
1339 03:05:32.601058 dt_test_unprobed_devices_sh_leds pass
1340 03:05:32.606657 dt_test_unprobed_devices_sh_ocp pass
1341 03:05:32.610218 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1342 03:05:32.615750 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1343 03:05:32.621359 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1344 03:05:32.630616 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1345 03:05:32.636198 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1346 03:05:32.647268 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1347 03:05:32.650884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1348 03:05:32.662291 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1349 03:05:32.673659 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1350 03:05:32.679027 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1351 03:05:32.690202 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1352 03:05:32.701426 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1353 03:05:32.712645 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1354 03:05:32.723932 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1355 03:05:32.729476 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1356 03:05:32.740665 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1357 03:05:32.751831 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1358 03:05:32.763118 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1359 03:05:32.768804 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1360 03:05:32.779926 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1361 03:05:32.791122 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1362 03:05:32.802306 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1363 03:05:32.813469 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1364 03:05:32.819137 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1365 03:05:32.830295 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1366 03:05:32.841447 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1367 03:05:32.852633 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1368 03:05:32.858314 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1369 03:05:32.869432 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1370 03:05:32.880616 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1371 03:05:32.891747 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1372 03:05:32.902929 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1373 03:05:32.914092 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1374 03:05:32.925297 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1375 03:05:32.936480 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1376 03:05:32.947693 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1377 03:05:32.958956 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1378 03:05:32.970086 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1379 03:05:32.981282 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1380 03:05:32.992472 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1381 03:05:33.003651 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1382 03:05:33.014846 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1383 03:05:33.026076 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1384 03:05:33.037234 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1385 03:05:33.048439 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1386 03:05:33.059636 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1387 03:05:33.070837 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1388 03:05:33.082077 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1389 03:05:33.093266 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1390 03:05:33.104458 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1391 03:05:33.115648 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1392 03:05:33.121301 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1393 03:05:33.132452 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1394 03:05:33.143645 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1395 03:05:33.154842 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1396 03:05:33.166062 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1397 03:05:33.177248 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1398 03:05:33.188443 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1399 03:05:33.199623 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1400 03:05:33.210829 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1401 03:05:33.222054 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1402 03:05:33.233215 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1403 03:05:33.244380 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1404 03:05:33.255598 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1405 03:05:33.261231 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1406 03:05:33.272365 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1407 03:05:33.283577 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1408 03:05:33.294741 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1409 03:05:33.305990 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1410 03:05:33.317095 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1411 03:05:33.328289 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1412 03:05:33.339526 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1413 03:05:33.350692 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1414 03:05:33.361850 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1415 03:05:33.373074 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1416 03:05:33.384153 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1417 03:05:33.395312 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1418 03:05:33.400983 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1419 03:05:33.412203 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1420 03:05:33.423428 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1421 03:05:33.434636 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1422 03:05:33.445823 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1423 03:05:33.457778 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1424 03:05:33.468276 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1425 03:05:33.479412 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1426 03:05:33.490574 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1427 03:05:33.501769 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1428 03:05:33.513030 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1429 03:05:33.518582 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1430 03:05:33.529700 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1431 03:05:33.540897 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1432 03:05:33.546551 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1433 03:05:33.557684 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1434 03:05:33.563333 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1435 03:05:33.574461 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1436 03:05:33.585669 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1437 03:05:33.596857 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1438 03:05:33.602514 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1439 03:05:33.613683 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1440 03:05:33.624853 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1441 03:05:33.636049 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1442 03:05:33.647225 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1443 03:05:33.664040 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1444 03:05:33.675206 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1445 03:05:33.686412 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1446 03:05:33.697598 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1447 03:05:33.708801 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1448 03:05:33.720071 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1449 03:05:33.731167 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1450 03:05:33.747958 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1451 03:05:33.759160 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1452 03:05:33.770343 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1453 03:05:33.781534 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1454 03:05:33.798310 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1455 03:05:33.809511 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1456 03:05:33.815350 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1457 03:05:33.826497 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1458 03:05:33.838105 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1459 03:05:33.843430 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1460 03:05:33.854234 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1461 03:05:33.859864 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1462 03:05:33.871046 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1463 03:05:33.876615 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1464 03:05:33.887798 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1465 03:05:33.893352 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1466 03:05:33.904562 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1467 03:05:33.910117 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1468 03:05:33.921323 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1469 03:05:33.932515 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1470 03:05:33.943764 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1471 03:05:33.954918 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1472 03:05:33.960551 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1473 03:05:33.971732 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1474 03:05:33.982865 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1475 03:05:33.988505 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1476 03:05:33.994098 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1477 03:05:33.999685 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1478 03:05:34.005286 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1479 03:05:34.010891 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1480 03:05:34.022082 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1481 03:05:34.027702 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1482 03:05:34.038887 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1483 03:05:34.044457 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1484 03:05:34.050092 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1485 03:05:34.061223 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1486 03:05:34.066836 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1487 03:05:34.078011 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1488 03:05:34.083646 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1489 03:05:34.094768 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1490 03:05:34.100396 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1491 03:05:34.111580 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1492 03:05:34.117182 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1493 03:05:34.128387 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1494 03:05:34.134068 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1495 03:05:34.145149 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1496 03:05:34.150762 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1497 03:05:34.156347 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1498 03:05:34.167521 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1499 03:05:34.173149 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1500 03:05:34.184301 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1501 03:05:34.189936 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1502 03:05:34.201120 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1503 03:05:34.206699 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1504 03:05:34.217939 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1505 03:05:34.223501 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1506 03:05:34.234682 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1507 03:05:34.240281 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1508 03:05:34.245865 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1509 03:05:34.257031 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1510 03:05:34.268288 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1511 03:05:34.279414 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1512 03:05:34.290605 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1513 03:05:34.301786 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1514 03:05:34.313056 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1515 03:05:34.324197 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1516 03:05:34.329805 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1517 03:05:34.340984 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1518 03:05:34.352186 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1519 03:05:34.357774 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1520 03:05:34.368938 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1521 03:05:34.374562 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1522 03:05:34.385708 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1523 03:05:34.391332 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1524 03:05:34.402506 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1525 03:05:34.413700 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1526 03:05:34.419310 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1527 03:05:34.424905 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1528 03:05:34.436182 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1529 03:05:34.447285 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1530 03:05:34.452830 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1531 03:05:34.458435 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1532 03:05:34.469608 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1533 03:05:34.475257 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1534 03:05:34.480847 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1535 03:05:34.492296 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1536 03:05:34.497585 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1537 03:05:34.508808 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1538 03:05:34.514382 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1539 03:05:34.525540 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1540 03:05:34.531198 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1541 03:05:34.536888 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1542 03:05:34.542369 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1543 03:05:34.553547 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1544 03:05:34.559174 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1545 03:05:34.570329 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1546 03:05:34.576116 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1547 03:05:34.587131 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1548 03:05:34.598319 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1549 03:05:34.609498 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1550 03:05:34.615124 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1551 03:05:34.626388 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1552 03:05:34.637673 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1553 03:05:34.643286 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1554 03:05:34.648866 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1555 03:05:34.654421 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1556 03:05:34.660098 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1557 03:05:34.665766 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1558 03:05:34.671404 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1559 03:05:34.682507 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1560 03:05:34.688123 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1561 03:05:34.693887 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1562 03:05:34.699493 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1563 03:05:34.705094 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1564 03:05:34.710695 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1565 03:05:34.716372 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1566 03:05:34.721861 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1567 03:05:34.727423 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1568 03:05:34.733059 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1569 03:05:34.738654 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1570 03:05:34.744514 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1571 03:05:34.749717 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1572 03:05:34.755332 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1573 03:05:34.760975 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1574 03:05:34.766615 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1575 03:05:34.772987 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1576 03:05:34.777751 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1577 03:05:34.784669 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1578 03:05:34.789247 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1579 03:05:34.794544 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1580 03:05:34.800281 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1581 03:05:34.805766 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1582 03:05:34.811320 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1583 03:05:34.816953 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1584 03:05:34.822454 dt_test_unprobed_devices_sh_opp-table skip
1585 03:05:34.828194 dt_test_unprobed_devices_sh_soc skip
1586 03:05:34.828526 dt_test_unprobed_devices_sh_sound pass
1587 03:05:34.833690 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1588 03:05:34.839270 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1589 03:05:34.850475 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1590 03:05:34.850869 dt_test_unprobed_devices_sh fail
1591 03:05:34.856178 + ../../utils/send-to-lava.sh ./output/result.txt
1592 03:05:34.861781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1593 03:05:34.862799 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1595 03:05:34.897571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1596 03:05:34.898440 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1598 03:05:35.004024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1599 03:05:35.004684 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1601 03:05:35.106595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1602 03:05:35.107240 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1604 03:05:35.204649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1605 03:05:35.205390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1607 03:05:35.301152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1608 03:05:35.301922 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1610 03:05:35.392151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1611 03:05:35.392910 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1613 03:05:35.491022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1614 03:05:35.491822 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1616 03:05:35.628518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1617 03:05:35.629218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1619 03:05:35.761776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1620 03:05:35.762501 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1622 03:05:35.863067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1623 03:05:35.863807 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1625 03:05:35.959644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1626 03:05:35.960360 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1628 03:05:36.054041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1629 03:05:36.054767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1631 03:05:36.151441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1632 03:05:36.152666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1634 03:05:36.243448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1635 03:05:36.244078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1637 03:05:36.334139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1638 03:05:36.334805 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1640 03:05:36.431806 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1641 03:05:36.432513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1643 03:05:36.540428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1644 03:05:36.541039 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1646 03:05:36.636911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1647 03:05:36.637474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1649 03:05:36.724729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1650 03:05:36.725299 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1652 03:05:36.813906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1653 03:05:36.814469 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1655 03:05:36.905146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1656 03:05:36.905683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1658 03:05:36.990736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1659 03:05:36.991284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1661 03:05:37.081183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1662 03:05:37.081753 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1664 03:05:37.172905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1665 03:05:37.173453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1667 03:05:37.265901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1668 03:05:37.266681 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1670 03:05:37.349932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1671 03:05:37.351010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1673 03:05:37.433150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1674 03:05:37.434040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1676 03:05:37.517229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1677 03:05:37.518145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1679 03:05:37.599781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1680 03:05:37.600695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1682 03:05:37.681003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1683 03:05:37.681890 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1685 03:05:37.764251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1686 03:05:37.765115 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1688 03:05:37.846029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1689 03:05:37.846935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1691 03:05:37.930383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1692 03:05:37.931306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1694 03:05:38.012638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1695 03:05:38.013543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1697 03:05:38.098519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1698 03:05:38.100614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1700 03:05:38.182928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1701 03:05:38.183533 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1703 03:05:38.273906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1704 03:05:38.274653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1706 03:05:38.360484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1707 03:05:38.361542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1709 03:05:38.451176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1710 03:05:38.452197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1712 03:05:38.535209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1713 03:05:38.536073 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1715 03:05:38.619480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1716 03:05:38.620312 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1718 03:05:38.703778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1719 03:05:38.704545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1721 03:05:38.788043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1722 03:05:38.788857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1724 03:05:38.878170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1725 03:05:38.878998 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1727 03:05:38.966689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1728 03:05:38.967481 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1730 03:05:39.049708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1731 03:05:39.050523 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1733 03:05:39.133274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1734 03:05:39.134010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1736 03:05:39.216225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1737 03:05:39.216967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1739 03:05:39.300230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1740 03:05:39.300960 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1742 03:05:39.383941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1743 03:05:39.384814 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1745 03:05:39.467674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1746 03:05:39.468437 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1748 03:05:39.551078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1749 03:05:39.551842 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1751 03:05:39.634100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1752 03:05:39.634836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1754 03:05:39.717710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1755 03:05:39.718471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1757 03:05:39.801687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1758 03:05:39.802411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1760 03:05:39.890950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1761 03:05:39.891706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1763 03:05:39.976698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1764 03:05:39.977512 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1766 03:05:40.059571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1767 03:05:40.060447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1769 03:05:40.149519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1770 03:05:40.150122 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1772 03:05:40.234632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1773 03:05:40.235528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1775 03:05:40.319167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1776 03:05:40.320070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1778 03:05:40.404445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1779 03:05:40.405387 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1781 03:05:40.495208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1782 03:05:40.496112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1784 03:05:40.583238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1785 03:05:40.584143 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1787 03:05:40.668072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1788 03:05:40.668923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1790 03:05:40.754880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1791 03:05:40.755760 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1793 03:05:40.845387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1794 03:05:40.846248 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1796 03:05:40.934516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1797 03:05:40.935401 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1799 03:05:41.018435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1800 03:05:41.019889 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1802 03:05:41.103555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1803 03:05:41.104548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1805 03:05:41.187730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1806 03:05:41.188628 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1808 03:05:41.276895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1809 03:05:41.277791 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1811 03:05:41.364709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1812 03:05:41.365620 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1814 03:05:41.453779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1815 03:05:41.454768 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1817 03:05:41.544142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1818 03:05:41.545063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1820 03:05:41.635127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1821 03:05:41.636119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1823 03:05:41.723011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1824 03:05:41.723950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1826 03:05:41.808205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1827 03:05:41.809195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1829 03:05:41.896992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1830 03:05:41.897699 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1832 03:05:41.993242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1833 03:05:41.993847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1835 03:05:42.084556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1836 03:05:42.085119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1838 03:05:42.174382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1839 03:05:42.175238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1841 03:05:42.263053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1842 03:05:42.263822 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1844 03:05:42.348210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1845 03:05:42.349045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1847 03:05:42.434627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1848 03:05:42.435421 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1850 03:05:42.521196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1851 03:05:42.521967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1853 03:05:42.613149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1854 03:05:42.613922 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1856 03:05:42.704819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1857 03:05:42.705588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1859 03:05:42.792371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1860 03:05:42.793153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1862 03:05:42.894710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1863 03:05:42.895494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1865 03:05:42.985192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1866 03:05:42.985946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1868 03:05:43.078797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1869 03:05:43.079586 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1871 03:05:43.165671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1872 03:05:43.166435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1874 03:05:43.257751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1875 03:05:43.258539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1877 03:05:43.346137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1878 03:05:43.346980 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1880 03:05:43.433352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1881 03:05:43.434159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1883 03:05:43.524400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1884 03:05:43.525194 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1886 03:05:43.615624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1887 03:05:43.616323 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1889 03:05:43.703956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1890 03:05:43.704644 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1892 03:05:43.793746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1893 03:05:43.794362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1895 03:05:43.889230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1896 03:05:43.889843 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1898 03:05:43.980624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1899 03:05:43.981241 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1901 03:05:44.067281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1902 03:05:44.068160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1904 03:05:44.159586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1905 03:05:44.160455 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1907 03:05:44.247115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1908 03:05:44.247894 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1910 03:05:44.337706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1911 03:05:44.338538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1913 03:05:44.431811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1914 03:05:44.432715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1916 03:05:44.527494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1917 03:05:44.528167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1919 03:05:44.619000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1920 03:05:44.619836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1922 03:05:44.705363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1923 03:05:44.706223 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1925 03:05:44.796242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1926 03:05:44.797041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1928 03:05:44.888394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1929 03:05:44.889147 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1931 03:05:44.977719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1932 03:05:44.978427 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1934 03:05:45.068780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1935 03:05:45.069625 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1937 03:05:45.161644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1938 03:05:45.162475 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1940 03:05:45.254497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1941 03:05:45.255313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1943 03:05:45.346586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1944 03:05:45.347418 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1946 03:05:45.438406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1947 03:05:45.439271 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1949 03:05:45.528004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1950 03:05:45.528840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1952 03:05:45.612956 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1954 03:05:45.616130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1955 03:05:45.705120 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1957 03:05:45.708318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1958 03:05:45.796329 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1960 03:05:45.799575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1961 03:05:45.885551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1962 03:05:45.886472 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1964 03:05:45.974570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1965 03:05:45.975453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1967 03:05:46.064374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1968 03:05:46.065203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1970 03:05:46.152441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1971 03:05:46.153251 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1973 03:05:46.242195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1974 03:05:46.243008 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1976 03:05:46.334045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1977 03:05:46.334903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1979 03:05:46.419011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1980 03:05:46.419824 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1982 03:05:46.511480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1983 03:05:46.512295 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1985 03:05:46.605101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1986 03:05:46.605904 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1988 03:05:46.694025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1989 03:05:46.694833 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1991 03:05:46.785121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1992 03:05:46.785912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1994 03:05:46.877205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1995 03:05:46.878038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1997 03:05:46.963642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1998 03:05:46.964490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2000 03:05:47.055507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2001 03:05:47.056335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2003 03:05:47.143320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2004 03:05:47.144129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2006 03:05:47.237189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2007 03:05:47.238028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2009 03:05:47.326939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2010 03:05:47.327772 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2012 03:05:47.417749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2013 03:05:47.418607 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2015 03:05:47.514282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2016 03:05:47.515148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2018 03:05:47.605490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2019 03:05:47.606404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2021 03:05:47.697435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2022 03:05:47.698329 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2024 03:05:47.786853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2025 03:05:47.787751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2027 03:05:47.881640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2028 03:05:47.882474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2030 03:05:47.968119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2031 03:05:47.968979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2033 03:05:48.059588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2034 03:05:48.060508 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2036 03:05:48.152960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2037 03:05:48.153792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2039 03:05:48.239079 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2040 03:05:48.239938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2042 03:05:48.331467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2043 03:05:48.332340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2045 03:05:48.424761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2046 03:05:48.425418 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2048 03:05:48.511461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2049 03:05:48.512102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2051 03:05:48.603971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2052 03:05:48.604599 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2054 03:05:48.695340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2055 03:05:48.695946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2057 03:05:48.781697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2058 03:05:48.782301 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2060 03:05:48.871232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2061 03:05:48.872114 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2063 03:05:48.965595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2064 03:05:48.966513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2066 03:05:49.059358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2067 03:05:49.060317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2069 03:05:49.151908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2070 03:05:49.153036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2072 03:05:49.238897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2073 03:05:49.239820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2075 03:05:49.330294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2076 03:05:49.331218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2078 03:05:49.415941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2079 03:05:49.416888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2081 03:05:49.509766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2082 03:05:49.510660 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2084 03:05:49.606412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2085 03:05:49.607359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2087 03:05:49.696553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2088 03:05:49.697463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2090 03:05:49.791976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2091 03:05:49.792986 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2093 03:05:49.881181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2094 03:05:49.882167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2096 03:05:49.974711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2097 03:05:49.975717 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2099 03:05:50.060418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2100 03:05:50.061616 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2102 03:05:50.154658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2103 03:05:50.155703 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2105 03:05:50.246372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2106 03:05:50.246979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2108 03:05:50.334932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2109 03:05:50.335615 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2111 03:05:50.439086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2112 03:05:50.439783 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2114 03:05:50.536247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2115 03:05:50.536906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2117 03:05:50.619099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2118 03:05:50.619951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2120 03:05:50.706889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2121 03:05:50.707545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2123 03:05:50.799300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2124 03:05:50.799935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2126 03:05:50.891912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2127 03:05:50.892566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2129 03:05:50.984539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2130 03:05:50.985187 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2132 03:05:51.074235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2133 03:05:51.074837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2135 03:05:51.164669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2136 03:05:51.165291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2138 03:05:51.249770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2139 03:05:51.250385 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2141 03:05:51.345854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2142 03:05:51.346485 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2144 03:05:51.439209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2145 03:05:51.439847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2147 03:05:51.533659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2148 03:05:51.534269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2150 03:05:51.624524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2151 03:05:51.625147 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2153 03:05:51.710124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2154 03:05:51.710854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2156 03:05:51.800425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2157 03:05:51.801171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2159 03:05:51.892347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2160 03:05:51.893527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2162 03:05:51.977970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2163 03:05:51.979118 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2165 03:05:52.070459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2166 03:05:52.071476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2168 03:05:52.161429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2169 03:05:52.162457 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2171 03:05:52.252827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2172 03:05:52.253833 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2174 03:05:52.339066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2175 03:05:52.339839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2177 03:05:52.424573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2178 03:05:52.425453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2180 03:05:52.515084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2181 03:05:52.516121 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2183 03:05:52.601722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2184 03:05:52.602608 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2186 03:05:52.689373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2187 03:05:52.690438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2189 03:05:52.780742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2190 03:05:52.781845 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2192 03:05:52.866158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2193 03:05:52.866785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2195 03:05:52.956156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2196 03:05:52.956763 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2198 03:05:53.044647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2199 03:05:53.045274 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2201 03:05:53.136602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2202 03:05:53.137219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2204 03:05:53.526535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2205 03:05:53.527169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2207 03:05:53.633123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2208 03:05:53.633745 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2210 03:05:53.726640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2211 03:05:53.727229 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2213 03:05:53.824116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2214 03:05:53.824715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2216 03:05:53.929980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2217 03:05:53.930636 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2219 03:05:54.027230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2220 03:05:54.027865 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2222 03:05:54.122058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2223 03:05:54.122702 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2225 03:05:54.216097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2226 03:05:54.216715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2228 03:05:54.313305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2229 03:05:54.313938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2231 03:05:54.402627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2232 03:05:54.403254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2234 03:05:54.487811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2235 03:05:54.488504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2237 03:05:54.587736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2238 03:05:54.588380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2240 03:05:54.681326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2241 03:05:54.681941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2243 03:05:54.777437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2244 03:05:54.778078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2246 03:05:54.873295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2247 03:05:54.873906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2249 03:05:54.965068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2250 03:05:54.965682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2252 03:05:55.053693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2253 03:05:55.054333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2255 03:05:55.139533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2256 03:05:55.140212 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2258 03:05:55.232694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2259 03:05:55.233554 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2261 03:05:55.325091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2262 03:05:55.325881 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2264 03:05:55.411864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2265 03:05:55.412510 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2267 03:05:55.506770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2268 03:05:55.508101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2270 03:05:55.602156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2271 03:05:55.602792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2273 03:05:55.690837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2275 03:05:55.694013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2276 03:05:55.784975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2277 03:05:55.785604 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2279 03:05:55.881162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2280 03:05:55.882167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2282 03:05:55.970677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2283 03:05:55.971299 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2285 03:05:56.063531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2286 03:05:56.064455 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2288 03:05:56.155701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2289 03:05:56.156326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2291 03:05:56.249322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2292 03:05:56.250186 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2294 03:05:56.341428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2295 03:05:56.342265 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2297 03:05:56.433999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2298 03:05:56.434836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2300 03:05:56.528233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2301 03:05:56.529070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2303 03:05:56.620427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2304 03:05:56.621227 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2306 03:05:56.713827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2307 03:05:56.714602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2309 03:05:56.804791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2310 03:05:56.805631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2312 03:05:56.896583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2313 03:05:56.897482 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2315 03:05:56.989266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2316 03:05:56.990116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2318 03:05:57.082685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2319 03:05:57.083817 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2321 03:05:57.173941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2322 03:05:57.174796 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2324 03:05:57.261782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2325 03:05:57.262651 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2327 03:05:57.357641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2328 03:05:57.358611 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2330 03:05:57.454640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2331 03:05:57.455500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2333 03:05:57.548112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2334 03:05:57.548962 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2336 03:05:57.641054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2337 03:05:57.641936 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2339 03:05:57.733435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2340 03:05:57.734073 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2342 03:05:57.828250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2343 03:05:57.829100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2345 03:05:57.921609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2346 03:05:57.922423 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2348 03:05:58.022777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2349 03:05:58.023537 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2351 03:05:58.116662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2352 03:05:58.117514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2354 03:05:58.207946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2355 03:05:58.208760 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2357 03:05:58.301480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2358 03:05:58.302264 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2360 03:05:58.390691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2361 03:05:58.391301 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2363 03:05:58.485018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2364 03:05:58.485853 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2366 03:05:58.574562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2367 03:05:58.575139 + set +x
2368 03:05:58.575804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2370 03:05:58.577904 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 978069_1.6.2.4.5>
2371 03:05:58.578615 Received signal: <ENDRUN> 1_kselftest-dt 978069_1.6.2.4.5
2372 03:05:58.579055 Ending use of test pattern.
2373 03:05:58.579448 Ending test lava.1_kselftest-dt (978069_1.6.2.4.5), duration 83.57
2375 03:05:58.583026 <LAVA_TEST_RUNNER EXIT>
2376 03:05:58.583730 ok: lava_test_shell seems to have completed
2377 03:05:58.596622 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2378 03:05:58.598535 end: 3.1 lava-test-shell (duration 00:01:25) [common]
2379 03:05:58.599083 end: 3 lava-test-retry (duration 00:01:25) [common]
2380 03:05:58.599620 start: 4 finalize (timeout 00:05:31) [common]
2381 03:05:58.600190 start: 4.1 power-off (timeout 00:00:30) [common]
2382 03:05:58.601163 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-01'
2383 03:05:58.636495 >> OK - accepted request
2384 03:05:58.638986 Returned 0 in 0 seconds
2385 03:05:58.740276 end: 4.1 power-off (duration 00:00:00) [common]
2387 03:05:58.741970 start: 4.2 read-feedback (timeout 00:05:31) [common]
2388 03:05:58.743059 Listened to connection for namespace 'common' for up to 1s
2389 03:05:58.743908 Listened to connection for namespace 'common' for up to 1s
2390 03:05:59.743854 Finalising connection for namespace 'common'
2391 03:05:59.744658 Disconnecting from shell: Finalise
2392 03:05:59.745149 / #
2393 03:05:59.846155 end: 4.2 read-feedback (duration 00:00:01) [common]
2394 03:05:59.846924 end: 4 finalize (duration 00:00:01) [common]
2395 03:05:59.847550 Cleaning after the job
2396 03:05:59.848206 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978069/tftp-deploy-lm_nm_7r/ramdisk
2397 03:05:59.853313 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978069/tftp-deploy-lm_nm_7r/kernel
2398 03:05:59.856546 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978069/tftp-deploy-lm_nm_7r/dtb
2399 03:05:59.857812 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978069/tftp-deploy-lm_nm_7r/nfsrootfs
2400 03:05:59.939182 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/978069/tftp-deploy-lm_nm_7r/modules
2401 03:05:59.944862 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/978069
2402 03:06:02.885116 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/978069
2403 03:06:02.885746 Job finished correctly