Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 17:13:44.416681 lava-dispatcher, installed at version: 2024.01
2 17:13:44.417519 start: 0 validate
3 17:13:44.418014 Start time: 2024-11-06 17:13:44.417984+00:00 (UTC)
4 17:13:44.418564 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 17:13:44.419130 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 17:13:44.460272 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 17:13:44.460844 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-116-g471463faceb56%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 17:13:44.491824 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 17:13:44.492544 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-116-g471463faceb56%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 17:13:44.524573 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 17:13:44.525116 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 17:13:44.562362 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 17:13:44.563144 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-116-g471463faceb56%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 17:13:44.604300 validate duration: 0.19
16 17:13:44.605218 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 17:13:44.605551 start: 1.1 download-retry (timeout 00:10:00) [common]
18 17:13:44.605857 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 17:13:44.606452 Not decompressing ramdisk as can be used compressed.
20 17:13:44.606874 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 17:13:44.607140 saving as /var/lib/lava/dispatcher/tmp/948111/tftp-deploy-9d1q109r/ramdisk/initrd.cpio.gz
22 17:13:44.607417 total size: 4775763 (4 MB)
23 17:13:44.644806 progress 0 % (0 MB)
24 17:13:44.648662 progress 5 % (0 MB)
25 17:13:44.654558 progress 10 % (0 MB)
26 17:13:44.660859 progress 15 % (0 MB)
27 17:13:44.667700 progress 20 % (0 MB)
28 17:13:44.671162 progress 25 % (1 MB)
29 17:13:44.674421 progress 30 % (1 MB)
30 17:13:44.678037 progress 35 % (1 MB)
31 17:13:44.681285 progress 40 % (1 MB)
32 17:13:44.684517 progress 45 % (2 MB)
33 17:13:44.687732 progress 50 % (2 MB)
34 17:13:44.691312 progress 55 % (2 MB)
35 17:13:44.694523 progress 60 % (2 MB)
36 17:13:44.697713 progress 65 % (2 MB)
37 17:13:44.701285 progress 70 % (3 MB)
38 17:13:44.704470 progress 75 % (3 MB)
39 17:13:44.707591 progress 80 % (3 MB)
40 17:13:44.710735 progress 85 % (3 MB)
41 17:13:44.714029 progress 90 % (4 MB)
42 17:13:44.716945 progress 95 % (4 MB)
43 17:13:44.719824 progress 100 % (4 MB)
44 17:13:44.720540 4 MB downloaded in 0.11 s (40.27 MB/s)
45 17:13:44.721153 end: 1.1.1 http-download (duration 00:00:00) [common]
47 17:13:44.722187 end: 1.1 download-retry (duration 00:00:00) [common]
48 17:13:44.722533 start: 1.2 download-retry (timeout 00:10:00) [common]
49 17:13:44.722861 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 17:13:44.723382 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-116-g471463faceb56/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 17:13:44.723643 saving as /var/lib/lava/dispatcher/tmp/948111/tftp-deploy-9d1q109r/kernel/zImage
52 17:13:44.724269 total size: 11444736 (10 MB)
53 17:13:44.724512 No compression specified
54 17:13:44.756575 progress 0 % (0 MB)
55 17:13:44.764002 progress 5 % (0 MB)
56 17:13:44.771091 progress 10 % (1 MB)
57 17:13:44.778660 progress 15 % (1 MB)
58 17:13:44.785778 progress 20 % (2 MB)
59 17:13:44.793279 progress 25 % (2 MB)
60 17:13:44.800430 progress 30 % (3 MB)
61 17:13:44.807787 progress 35 % (3 MB)
62 17:13:44.814728 progress 40 % (4 MB)
63 17:13:44.822131 progress 45 % (4 MB)
64 17:13:44.829061 progress 50 % (5 MB)
65 17:13:44.836513 progress 55 % (6 MB)
66 17:13:44.843582 progress 60 % (6 MB)
67 17:13:44.851123 progress 65 % (7 MB)
68 17:13:44.858435 progress 70 % (7 MB)
69 17:13:44.865451 progress 75 % (8 MB)
70 17:13:44.872864 progress 80 % (8 MB)
71 17:13:44.879845 progress 85 % (9 MB)
72 17:13:44.887254 progress 90 % (9 MB)
73 17:13:44.894179 progress 95 % (10 MB)
74 17:13:44.900966 progress 100 % (10 MB)
75 17:13:44.901483 10 MB downloaded in 0.18 s (61.59 MB/s)
76 17:13:44.901962 end: 1.2.1 http-download (duration 00:00:00) [common]
78 17:13:44.902795 end: 1.2 download-retry (duration 00:00:00) [common]
79 17:13:44.903081 start: 1.3 download-retry (timeout 00:10:00) [common]
80 17:13:44.903356 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 17:13:44.903832 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-116-g471463faceb56/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 17:13:44.904117 saving as /var/lib/lava/dispatcher/tmp/948111/tftp-deploy-9d1q109r/dtb/am335x-boneblack.dtb
83 17:13:44.904334 total size: 70568 (0 MB)
84 17:13:44.904551 No compression specified
85 17:13:44.937564 progress 46 % (0 MB)
86 17:13:44.938431 progress 92 % (0 MB)
87 17:13:44.939167 progress 100 % (0 MB)
88 17:13:44.939596 0 MB downloaded in 0.04 s (1.91 MB/s)
89 17:13:44.940113 end: 1.3.1 http-download (duration 00:00:00) [common]
91 17:13:44.940993 end: 1.3 download-retry (duration 00:00:00) [common]
92 17:13:44.941280 start: 1.4 download-retry (timeout 00:10:00) [common]
93 17:13:44.941573 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 17:13:44.942061 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 17:13:44.942327 saving as /var/lib/lava/dispatcher/tmp/948111/tftp-deploy-9d1q109r/nfsrootfs/full.rootfs.tar
96 17:13:44.942544 total size: 117747780 (112 MB)
97 17:13:44.942771 Using unxz to decompress xz
98 17:13:44.979906 progress 0 % (0 MB)
99 17:13:45.719977 progress 5 % (5 MB)
100 17:13:46.472418 progress 10 % (11 MB)
101 17:13:47.250104 progress 15 % (16 MB)
102 17:13:47.967273 progress 20 % (22 MB)
103 17:13:48.543315 progress 25 % (28 MB)
104 17:13:49.343077 progress 30 % (33 MB)
105 17:13:50.142046 progress 35 % (39 MB)
106 17:13:50.489764 progress 40 % (44 MB)
107 17:13:50.841712 progress 45 % (50 MB)
108 17:13:51.500671 progress 50 % (56 MB)
109 17:13:52.304545 progress 55 % (61 MB)
110 17:13:53.024161 progress 60 % (67 MB)
111 17:13:53.731758 progress 65 % (73 MB)
112 17:13:54.495823 progress 70 % (78 MB)
113 17:13:55.263776 progress 75 % (84 MB)
114 17:13:55.996620 progress 80 % (89 MB)
115 17:13:56.705386 progress 85 % (95 MB)
116 17:13:57.494863 progress 90 % (101 MB)
117 17:13:58.264117 progress 95 % (106 MB)
118 17:13:59.081452 progress 100 % (112 MB)
119 17:13:59.094996 112 MB downloaded in 14.15 s (7.93 MB/s)
120 17:13:59.095774 end: 1.4.1 http-download (duration 00:00:14) [common]
122 17:13:59.097678 end: 1.4 download-retry (duration 00:00:14) [common]
123 17:13:59.098266 start: 1.5 download-retry (timeout 00:09:46) [common]
124 17:13:59.098848 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 17:13:59.099805 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-116-g471463faceb56/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 17:13:59.100371 saving as /var/lib/lava/dispatcher/tmp/948111/tftp-deploy-9d1q109r/modules/modules.tar
127 17:13:59.100839 total size: 6611252 (6 MB)
128 17:13:59.101308 Using unxz to decompress xz
129 17:13:59.143629 progress 0 % (0 MB)
130 17:13:59.184299 progress 5 % (0 MB)
131 17:13:59.242634 progress 10 % (0 MB)
132 17:13:59.297001 progress 15 % (0 MB)
133 17:13:59.351548 progress 20 % (1 MB)
134 17:13:59.409559 progress 25 % (1 MB)
135 17:13:59.463293 progress 30 % (1 MB)
136 17:13:59.514659 progress 35 % (2 MB)
137 17:13:59.567868 progress 40 % (2 MB)
138 17:13:59.620329 progress 45 % (2 MB)
139 17:13:59.670625 progress 50 % (3 MB)
140 17:13:59.713718 progress 55 % (3 MB)
141 17:13:59.764054 progress 60 % (3 MB)
142 17:13:59.806706 progress 65 % (4 MB)
143 17:13:59.850196 progress 70 % (4 MB)
144 17:13:59.896570 progress 75 % (4 MB)
145 17:13:59.939700 progress 80 % (5 MB)
146 17:13:59.982550 progress 85 % (5 MB)
147 17:14:00.027113 progress 90 % (5 MB)
148 17:14:00.071067 progress 95 % (6 MB)
149 17:14:00.116857 progress 100 % (6 MB)
150 17:14:00.131657 6 MB downloaded in 1.03 s (6.12 MB/s)
151 17:14:00.132441 end: 1.5.1 http-download (duration 00:00:01) [common]
153 17:14:00.134231 end: 1.5 download-retry (duration 00:00:01) [common]
154 17:14:00.134801 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 17:14:00.135374 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 17:14:16.702315 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/948111/extract-nfsrootfs-_iigzxnu
157 17:14:16.702915 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 17:14:16.703199 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 17:14:16.703897 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb
160 17:14:16.704376 makedir: /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin
161 17:14:16.704693 makedir: /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/tests
162 17:14:16.705000 makedir: /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/results
163 17:14:16.705325 Creating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-add-keys
164 17:14:16.705842 Creating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-add-sources
165 17:14:16.706338 Creating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-background-process-start
166 17:14:16.706824 Creating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-background-process-stop
167 17:14:16.707336 Creating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-common-functions
168 17:14:16.707810 Creating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-echo-ipv4
169 17:14:16.708317 Creating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-install-packages
170 17:14:16.708781 Creating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-installed-packages
171 17:14:16.709234 Creating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-os-build
172 17:14:16.709684 Creating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-probe-channel
173 17:14:16.710137 Creating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-probe-ip
174 17:14:16.710587 Creating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-target-ip
175 17:14:16.711034 Creating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-target-mac
176 17:14:16.711486 Creating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-target-storage
177 17:14:16.711942 Creating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-test-case
178 17:14:16.712506 Creating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-test-event
179 17:14:16.712976 Creating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-test-feedback
180 17:14:16.713446 Creating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-test-raise
181 17:14:16.713922 Creating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-test-reference
182 17:14:16.714385 Creating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-test-runner
183 17:14:16.714847 Creating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-test-set
184 17:14:16.715303 Creating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-test-shell
185 17:14:16.715764 Updating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-add-keys (debian)
186 17:14:16.716303 Updating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-add-sources (debian)
187 17:14:16.716792 Updating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-install-packages (debian)
188 17:14:16.717272 Updating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-installed-packages (debian)
189 17:14:16.717745 Updating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/bin/lava-os-build (debian)
190 17:14:16.718163 Creating /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/environment
191 17:14:16.718516 LAVA metadata
192 17:14:16.718771 - LAVA_JOB_ID=948111
193 17:14:16.718985 - LAVA_DISPATCHER_IP=192.168.6.2
194 17:14:16.719337 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 17:14:16.720303 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 17:14:16.720613 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 17:14:16.720819 skipped lava-vland-overlay
198 17:14:16.721059 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 17:14:16.721314 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 17:14:16.721532 skipped lava-multinode-overlay
201 17:14:16.721774 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 17:14:16.722025 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 17:14:16.722264 Loading test definitions
204 17:14:16.722537 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 17:14:16.722754 Using /lava-948111 at stage 0
206 17:14:16.723798 uuid=948111_1.6.2.4.1 testdef=None
207 17:14:16.724115 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 17:14:16.724381 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 17:14:16.725895 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 17:14:16.726673 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 17:14:16.728565 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 17:14:16.729382 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 17:14:16.731146 runner path: /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/0/tests/0_timesync-off test_uuid 948111_1.6.2.4.1
216 17:14:16.731662 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 17:14:16.732490 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 17:14:16.732711 Using /lava-948111 at stage 0
220 17:14:16.733051 Fetching tests from https://github.com/kernelci/test-definitions.git
221 17:14:16.733338 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/0/tests/1_kselftest-dt'
222 17:14:20.149541 Running '/usr/bin/git checkout kernelci.org
223 17:14:20.342418 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 17:14:20.343857 uuid=948111_1.6.2.4.5 testdef=None
225 17:14:20.344252 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 17:14:20.345000 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 17:14:20.347870 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 17:14:20.348740 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 17:14:20.352454 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 17:14:20.353311 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 17:14:20.356888 runner path: /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/0/tests/1_kselftest-dt test_uuid 948111_1.6.2.4.5
235 17:14:20.357176 BOARD='beaglebone-black'
236 17:14:20.357381 BRANCH='pm'
237 17:14:20.357578 SKIPFILE='/dev/null'
238 17:14:20.357776 SKIP_INSTALL='True'
239 17:14:20.357971 TESTPROG_URL='http://storage.kernelci.org/pm/testing/v6.12-rc6-116-g471463faceb56/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 17:14:20.358173 TST_CASENAME=''
241 17:14:20.358368 TST_CMDFILES='dt'
242 17:14:20.358919 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 17:14:20.359709 Creating lava-test-runner.conf files
245 17:14:20.359913 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/948111/lava-overlay-uxbm7feb/lava-948111/0 for stage 0
246 17:14:20.360290 - 0_timesync-off
247 17:14:20.360534 - 1_kselftest-dt
248 17:14:20.360862 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 17:14:20.361146 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 17:14:43.960548 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 17:14:43.960990 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:01) [common]
252 17:14:43.961283 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 17:14:43.961588 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 17:14:43.961883 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:01) [common]
255 17:14:44.324505 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 17:14:44.325027 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 17:14:44.325327 extracting modules file /var/lib/lava/dispatcher/tmp/948111/tftp-deploy-9d1q109r/modules/modules.tar to /var/lib/lava/dispatcher/tmp/948111/extract-nfsrootfs-_iigzxnu
258 17:14:45.207095 extracting modules file /var/lib/lava/dispatcher/tmp/948111/tftp-deploy-9d1q109r/modules/modules.tar to /var/lib/lava/dispatcher/tmp/948111/extract-overlay-ramdisk-z30hg1n2/ramdisk
259 17:14:46.119770 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 17:14:46.120275 start: 1.6.5 apply-overlay-tftp (timeout 00:08:58) [common]
261 17:14:46.120561 [common] Applying overlay to NFS
262 17:14:46.120779 [common] Applying overlay /var/lib/lava/dispatcher/tmp/948111/compress-overlay-ezbyjnm6/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/948111/extract-nfsrootfs-_iigzxnu
263 17:14:48.882258 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 17:14:48.882743 start: 1.6.6 prepare-kernel (timeout 00:08:56) [common]
265 17:14:48.883021 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:56) [common]
266 17:14:48.883301 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 17:14:48.883554 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 17:14:48.883815 start: 1.6.7 configure-preseed-file (timeout 00:08:56) [common]
269 17:14:48.884100 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 17:14:48.884375 start: 1.6.8 compress-ramdisk (timeout 00:08:56) [common]
271 17:14:48.884634 Building ramdisk /var/lib/lava/dispatcher/tmp/948111/extract-overlay-ramdisk-z30hg1n2/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/948111/extract-overlay-ramdisk-z30hg1n2/ramdisk
272 17:14:49.935732 >> 74900 blocks
273 17:14:54.519712 Adding RAMdisk u-boot header.
274 17:14:54.520590 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/948111/extract-overlay-ramdisk-z30hg1n2/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/948111/extract-overlay-ramdisk-z30hg1n2/ramdisk.cpio.gz.uboot
275 17:14:54.706531 output: Image Name:
276 17:14:54.706943 output: Created: Wed Nov 6 17:14:54 2024
277 17:14:54.707158 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 17:14:54.707365 output: Data Size: 14790417 Bytes = 14443.77 KiB = 14.11 MiB
279 17:14:54.707568 output: Load Address: 00000000
280 17:14:54.707768 output: Entry Point: 00000000
281 17:14:54.707968 output:
282 17:14:54.709016 rename /var/lib/lava/dispatcher/tmp/948111/extract-overlay-ramdisk-z30hg1n2/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/948111/tftp-deploy-9d1q109r/ramdisk/ramdisk.cpio.gz.uboot
283 17:14:54.709730 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 17:14:54.710270 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 17:14:54.710796 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:50) [common]
286 17:14:54.711247 No LXC device requested
287 17:14:54.711743 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 17:14:54.712296 start: 1.8 deploy-device-env (timeout 00:08:50) [common]
289 17:14:54.712789 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 17:14:54.713202 Checking files for TFTP limit of 4294967296 bytes.
291 17:14:54.715910 end: 1 tftp-deploy (duration 00:01:10) [common]
292 17:14:54.716543 start: 2 uboot-action (timeout 00:05:00) [common]
293 17:14:54.717068 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 17:14:54.717566 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 17:14:54.718063 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 17:14:54.718807 substitutions:
297 17:14:54.719227 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 17:14:54.719633 - {DTB_ADDR}: 0x88000000
299 17:14:54.720058 - {DTB}: 948111/tftp-deploy-9d1q109r/dtb/am335x-boneblack.dtb
300 17:14:54.720460 - {INITRD}: 948111/tftp-deploy-9d1q109r/ramdisk/ramdisk.cpio.gz.uboot
301 17:14:54.720854 - {KERNEL_ADDR}: 0x82000000
302 17:14:54.721244 - {KERNEL}: 948111/tftp-deploy-9d1q109r/kernel/zImage
303 17:14:54.721633 - {LAVA_MAC}: None
304 17:14:54.722062 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/948111/extract-nfsrootfs-_iigzxnu
305 17:14:54.722459 - {NFS_SERVER_IP}: 192.168.6.2
306 17:14:54.722847 - {PRESEED_CONFIG}: None
307 17:14:54.723235 - {PRESEED_LOCAL}: None
308 17:14:54.723620 - {RAMDISK_ADDR}: 0x83000000
309 17:14:54.724029 - {RAMDISK}: 948111/tftp-deploy-9d1q109r/ramdisk/ramdisk.cpio.gz.uboot
310 17:14:54.724426 - {ROOT_PART}: None
311 17:14:54.724817 - {ROOT}: None
312 17:14:54.725204 - {SERVER_IP}: 192.168.6.2
313 17:14:54.725586 - {TEE_ADDR}: 0x83000000
314 17:14:54.725967 - {TEE}: None
315 17:14:54.726348 Parsed boot commands:
316 17:14:54.726719 - setenv autoload no
317 17:14:54.727104 - setenv initrd_high 0xffffffff
318 17:14:54.727486 - setenv fdt_high 0xffffffff
319 17:14:54.727863 - dhcp
320 17:14:54.728301 - setenv serverip 192.168.6.2
321 17:14:54.728687 - tftp 0x82000000 948111/tftp-deploy-9d1q109r/kernel/zImage
322 17:14:54.729071 - tftp 0x83000000 948111/tftp-deploy-9d1q109r/ramdisk/ramdisk.cpio.gz.uboot
323 17:14:54.729455 - setenv initrd_size ${filesize}
324 17:14:54.729836 - tftp 0x88000000 948111/tftp-deploy-9d1q109r/dtb/am335x-boneblack.dtb
325 17:14:54.730220 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/948111/extract-nfsrootfs-_iigzxnu,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 17:14:54.730617 - bootz 0x82000000 0x83000000 0x88000000
327 17:14:54.731104 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 17:14:54.732613 start: 2.3 connect-device (timeout 00:05:00) [common]
330 17:14:54.733030 [common] connect-device Connecting to device using 'telnet conserv1 3003'
331 17:14:54.748374 Setting prompt string to ['lava-test: # ']
332 17:14:54.749878 end: 2.3 connect-device (duration 00:00:00) [common]
333 17:14:54.750486 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 17:14:54.751039 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 17:14:54.751606 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 17:14:54.752846 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-01'
337 17:14:54.788235 >> OK - accepted request
338 17:14:54.790120 Returned 0 in 0 seconds
339 17:14:54.891560 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 17:14:54.893866 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 17:14:54.894635 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 17:14:54.895311 Setting prompt string to ['Hit any key to stop autoboot']
344 17:14:54.895936 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 17:14:54.898012 Trying 192.168.56.21...
346 17:14:54.898649 Connected to conserv1.
347 17:14:54.899211 Escape character is '^]'.
348 17:14:54.899754
349 17:14:54.900434 ser2net port telnet,3003 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 17:14:54.901056
351 17:15:03.028580
352 17:15:03.029194 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
353 17:15:03.033759 Trying to boot from MMC1
354 17:15:03.606419
355 17:15:03.607078
356 17:15:03.607557 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
357 17:15:03.608069
358 17:15:03.611920 CPU : AM335X-GP rev 2.1
359 17:15:03.612486 Model: TI AM335x BeagleBone Black
360 17:15:03.616051 DRAM: 512 MiB
361 17:15:03.698822 Core: 160 devices, 18 uclasses, devicetree: separate
362 17:15:03.708486 WDT: Started wdt@44e35000 with servicing (60s timeout)
363 17:15:07.081998 7[r[999;999H[6n8NAND:
364 17:15:07.082485 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
365 17:15:07.087173 Trying to boot from MMC1
366 17:15:07.661534
367 17:15:07.662199
368 17:15:07.662682 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
369 17:15:07.663147
370 17:15:07.666977 CPU : AM335X-GP rev 2.1
371 17:15:07.667524 Model: TI AM335x BeagleBone Black
372 17:15:07.671082 DRAM: 512 MiB
373 17:15:07.753167 Core: 160 devices, 18 uclasses, devicetree: separate
374 17:15:07.763873 WDT: Started wdt@44e35000 with servicing (60s timeout)
375 17:15:09.782121 7[r[999;999H[6n8NAND:
376 17:15:09.782523 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
377 17:15:09.786678 Trying to boot from MMC1
378 17:15:10.359904
379 17:15:10.360607
380 17:15:10.361088 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
381 17:15:10.361551
382 17:15:10.365215 CPU : AM335X-GP rev 2.1
383 17:15:10.365710 Model: TI AM335x BeagleBone Black
384 17:15:10.368842 DRAM: 512 MiB
385 17:15:10.451482 Core: 160 devices, 18 uclasses, devicetree: separate
386 17:15:10.461880 WDT: Started wdt@44e35000 with servicing (60s timeout)
387 17:15:10.966080 7[r[999;999H[6n8NAND: 0 MiB
388 17:15:10.977190 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
389 17:15:11.049030 Loading Environment from FAT... Unable to use mmc 0:1...
390 17:15:11.070856 <ethaddr> not set. Validating first E-fuse MAC
391 17:15:11.100886 Net: eth2: ethernet@4a100000, eth3: usb_ether
393 17:15:11.159801 Hit any key to stop autoboot: 2
394 17:15:11.160851 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
395 17:15:11.161527 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
396 17:15:11.162127 Setting prompt string to ['=>']
397 17:15:11.162701 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
398 17:15:11.170103 0
399 17:15:11.171084 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
400 17:15:11.171646 Sending with 10 millisecond of delay
402 17:15:12.307093 => setenv autoload no
403 17:15:12.317931 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
404 17:15:12.323342 setenv autoload no
405 17:15:12.324124 Sending with 10 millisecond of delay
407 17:15:14.121058 => setenv initrd_high 0xffffffff
408 17:15:14.131846 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
409 17:15:14.132784 setenv initrd_high 0xffffffff
410 17:15:14.133554 Sending with 10 millisecond of delay
412 17:15:15.749818 => setenv fdt_high 0xffffffff
413 17:15:15.760610 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
414 17:15:15.761500 setenv fdt_high 0xffffffff
415 17:15:15.762266 Sending with 10 millisecond of delay
417 17:15:16.054174 => dhcp
418 17:15:16.064928 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
419 17:15:16.065814 dhcp
420 17:15:16.067625 link up on port 0, speed 100, full duplex
421 17:15:16.068168 BOOTP broadcast 1
422 17:15:16.088939 DHCP client bound to address 192.168.6.12 (18 ms)
423 17:15:16.089715 Sending with 10 millisecond of delay
425 17:15:17.766104 => setenv serverip 192.168.6.2
426 17:15:17.776893 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
427 17:15:17.777819 setenv serverip 192.168.6.2
428 17:15:17.778587 Sending with 10 millisecond of delay
430 17:15:21.261376 => tftp 0x82000000 948111/tftp-deploy-9d1q109r/kernel/zImage
431 17:15:21.272145 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
432 17:15:21.272977 tftp 0x82000000 948111/tftp-deploy-9d1q109r/kernel/zImage
433 17:15:21.273427 link up on port 0, speed 100, full duplex
434 17:15:21.276740 Using ethernet@4a100000 device
435 17:15:21.282499 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
436 17:15:21.289663 Filename '948111/tftp-deploy-9d1q109r/kernel/zImage'.
437 17:15:21.290126 Load address: 0x82000000
438 17:15:23.667480 Loading: *################################################## 10.9 MiB
439 17:15:23.668142 4.6 MiB/s
440 17:15:23.668589 done
441 17:15:23.671447 Bytes transferred = 11444736 (aea200 hex)
442 17:15:23.672251 Sending with 10 millisecond of delay
444 17:15:28.119700 => tftp 0x83000000 948111/tftp-deploy-9d1q109r/ramdisk/ramdisk.cpio.gz.uboot
445 17:15:28.130625 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
446 17:15:28.131127 tftp 0x83000000 948111/tftp-deploy-9d1q109r/ramdisk/ramdisk.cpio.gz.uboot
447 17:15:28.131373 link up on port 0, speed 100, full duplex
448 17:15:28.135726 Using ethernet@4a100000 device
449 17:15:28.140976 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
450 17:15:28.149489 Filename '948111/tftp-deploy-9d1q109r/ramdisk/ramdisk.cpio.gz.uboot'.
451 17:15:28.150008 Load address: 0x83000000
452 17:15:31.183033 Loading: *################################################## 14.1 MiB
453 17:15:31.183625 4.7 MiB/s
454 17:15:31.183878 done
455 17:15:31.186903 Bytes transferred = 14790481 (e1af51 hex)
456 17:15:31.188233 Sending with 10 millisecond of delay
458 17:15:33.046367 => setenv initrd_size ${filesize}
459 17:15:33.057181 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
460 17:15:33.057841 setenv initrd_size ${filesize}
461 17:15:33.058322 Sending with 10 millisecond of delay
463 17:15:37.204080 => tftp 0x88000000 948111/tftp-deploy-9d1q109r/dtb/am335x-boneblack.dtb
464 17:15:37.214916 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
465 17:15:37.215861 tftp 0x88000000 948111/tftp-deploy-9d1q109r/dtb/am335x-boneblack.dtb
466 17:15:37.216443 link up on port 0, speed 100, full duplex
467 17:15:37.219707 Using ethernet@4a100000 device
468 17:15:37.225295 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
469 17:15:37.236486 Filename '948111/tftp-deploy-9d1q109r/dtb/am335x-boneblack.dtb'.
470 17:15:37.236974 Load address: 0x88000000
471 17:15:37.247604 Loading: *################################################## 68.9 KiB
472 17:15:37.248115 4.5 MiB/s
473 17:15:37.256049 done
474 17:15:37.256518 Bytes transferred = 70568 (113a8 hex)
475 17:15:37.257232 Sending with 10 millisecond of delay
477 17:15:50.439076 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/948111/extract-nfsrootfs-_iigzxnu,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 17:15:50.450463 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
479 17:15:50.451071 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/948111/extract-nfsrootfs-_iigzxnu,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 17:15:50.451581 Sending with 10 millisecond of delay
482 17:15:52.789712 => bootz 0x82000000 0x83000000 0x88000000
483 17:15:52.800314 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 17:15:52.800658 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
485 17:15:52.801234 bootz 0x82000000 0x83000000 0x88000000
486 17:15:52.801496 Kernel image @ 0x82000000 [ 0x000000 - 0xaea200 ]
487 17:15:52.802320 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 17:15:52.807897 Image Name:
489 17:15:52.808216 Created: 2024-11-06 17:14:54 UTC
490 17:15:52.813412 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 17:15:52.819049 Data Size: 14790417 Bytes = 14.1 MiB
492 17:15:52.819335 Load Address: 00000000
493 17:15:52.825201 Entry Point: 00000000
494 17:15:52.993845 Verifying Checksum ... OK
495 17:15:52.994278 ## Flattened Device Tree blob at 88000000
496 17:15:53.000181 Booting using the fdt blob at 0x88000000
497 17:15:53.005057 Using Device Tree in place at 88000000, end 880143a7
498 17:15:53.018723
499 17:15:53.019050 Starting kernel ...
500 17:15:53.019270
501 17:15:53.019921 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 17:15:53.020424 start: 2.4.4 auto-login-action (timeout 00:04:02) [common]
503 17:15:53.020817 Setting prompt string to ['Linux version [0-9]']
504 17:15:53.021182 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
505 17:15:53.021558 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
506 17:15:53.859653 [ 0.000000] Booting Linux on physical CPU 0x0
507 17:15:53.865530 start: 2.4.4.1 login-action (timeout 00:04:01) [common]
508 17:15:53.866011 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 17:15:53.866291 Setting prompt string to []
510 17:15:53.866558 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 17:15:53.866808 Using line separator: #'\n'#
512 17:15:53.867019 No login prompt set.
513 17:15:53.867258 Parsing kernel messages
514 17:15:53.867475 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 17:15:53.867894 [login-action] Waiting for messages, (timeout 00:04:01)
516 17:15:53.868179 Waiting using forced prompt support (timeout 00:02:00)
517 17:15:53.879524 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j365228-arm-gcc-12-multi-v7-defconfig-x7vmt) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Wed Nov 6 16:59:24 UTC 2024
518 17:15:53.890994 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
519 17:15:53.896954 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
520 17:15:53.902662 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
521 17:15:53.908169 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
522 17:15:53.913940 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
523 17:15:53.920484 [ 0.000000] Memory policy: Data cache writeback
524 17:15:53.920777 [ 0.000000] efi: UEFI not found.
525 17:15:53.929298 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
526 17:15:53.935034 [ 0.000000] Zone ranges:
527 17:15:53.940754 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
528 17:15:53.941045 [ 0.000000] Normal empty
529 17:15:53.946391 [ 0.000000] HighMem empty
530 17:15:53.952072 [ 0.000000] Movable zone start for each node
531 17:15:53.952363 [ 0.000000] Early memory node ranges
532 17:15:53.963669 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
533 17:15:53.967303 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
534 17:15:53.993711 [ 0.000000] CPU: All CPU(s) started in SVC mode.
535 17:15:53.999375 [ 0.000000] AM335X ES2.1 (sgx neon)
536 17:15:54.011090 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
537 17:15:54.028811 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/948111/extract-nfsrootfs-_iigzxnu,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
538 17:15:54.040338 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
539 17:15:54.046046 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
540 17:15:54.051801 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
541 17:15:54.061814 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
542 17:15:54.090931 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
543 17:15:54.096881 <6>[ 0.000000] trace event string verifier disabled
544 17:15:54.097352 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
545 17:15:54.102672 <6>[ 0.000000] rcu: RCU event tracing is enabled.
546 17:15:54.114071 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
547 17:15:54.119799 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
548 17:15:54.127061 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
549 17:15:54.142178 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
550 17:15:54.159768 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
551 17:15:54.166384 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
552 17:15:54.260157 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
553 17:15:54.271263 <6>[ 0.000003] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
554 17:15:54.278095 <6>[ 0.008336] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
555 17:15:54.291018 <6>[ 0.019161] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
556 17:15:54.298601 <6>[ 0.034067] Console: colour dummy device 80x30
557 17:15:54.304778 Matched prompt #6: WARNING:
558 17:15:54.305397 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
559 17:15:54.310087 <3>[ 0.038965] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
560 17:15:54.315872 <3>[ 0.046033] This ensures that you still see kernel messages. Please
561 17:15:54.318999 <3>[ 0.052762] update your kernel commandline.
562 17:15:54.359584 <6>[ 0.057375] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
563 17:15:54.365389 <6>[ 0.096163] CPU: Testing write buffer coherency: ok
564 17:15:54.371303 <6>[ 0.101525] CPU0: Spectre v2: using BPIALL workaround
565 17:15:54.371919 <6>[ 0.106993] pid_max: default: 32768 minimum: 301
566 17:15:54.382819 <6>[ 0.112182] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 17:15:54.389863 <6>[ 0.120006] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 17:15:54.396855 <6>[ 0.129367] CPU0: thread -1, cpu 0, socket -1, mpidr 0
569 17:15:54.405256 <6>[ 0.136364] Setting up static identity map for 0x80300000 - 0x803000ac
570 17:15:54.411017 <6>[ 0.145994] rcu: Hierarchical SRCU implementation.
571 17:15:54.418733 <6>[ 0.151274] rcu: Max phase no-delay instances is 1000.
572 17:15:54.427196 <6>[ 0.162450] EFI services will not be available.
573 17:15:54.433104 <6>[ 0.167729] smp: Bringing up secondary CPUs ...
574 17:15:54.438878 <6>[ 0.172777] smp: Brought up 1 node, 1 CPU
575 17:15:54.444571 <6>[ 0.177177] SMP: Total of 1 processors activated (996.14 BogoMIPS).
576 17:15:54.450454 <6>[ 0.183945] CPU: All CPU(s) started in SVC mode.
577 17:15:54.470854 <6>[ 0.189130] Memory: 406000K/522240K available (16384K kernel code, 2543K rwdata, 6788K rodata, 2048K init, 430K bss, 49048K reserved, 65536K cma-reserved, 0K highmem)
578 17:15:54.471449 <6>[ 0.205412] devtmpfs: initialized
579 17:15:54.492976 <6>[ 0.222561] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
580 17:15:54.504547 <6>[ 0.231137] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
581 17:15:54.510598 <6>[ 0.241596] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
582 17:15:54.521413 <6>[ 0.253885] pinctrl core: initialized pinctrl subsystem
583 17:15:54.533199 <6>[ 0.264578] DMI not present or invalid.
584 17:15:54.538977 <6>[ 0.270438] NET: Registered PF_NETLINK/PF_ROUTE protocol family
585 17:15:54.548348 <6>[ 0.279365] DMA: preallocated 256 KiB pool for atomic coherent allocations
586 17:15:54.563610 <6>[ 0.290968] thermal_sys: Registered thermal governor 'step_wise'
587 17:15:54.564454 <6>[ 0.291125] cpuidle: using governor menu
588 17:15:54.591064 <6>[ 0.326714] No ATAGs?
589 17:15:54.597252 <6>[ 0.329357] hw-breakpoint: debug architecture 0x4 unsupported.
590 17:15:54.607478 <6>[ 0.341374] Serial: AMBA PL011 UART driver
591 17:15:54.639566 <6>[ 0.375072] iommu: Default domain type: Translated
592 17:15:54.648638 <6>[ 0.380412] iommu: DMA domain TLB invalidation policy: strict mode
593 17:15:54.985153 <5>[ 0.411039] SCSI subsystem initialized
594 17:15:54.985663 <6>[ 0.415921] usbcore: registered new interface driver usbfs
595 17:15:54.985991 <6>[ 0.421953] usbcore: registered new interface driver hub
596 17:15:54.986311 <6>[ 0.427743] usbcore: registered new device driver usb
597 17:15:54.986616 <6>[ 0.434251] pps_core: LinuxPPS API ver. 1 registered
598 17:15:54.986925 <6>[ 0.439686] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
599 17:15:54.987233 <6>[ 0.449369] PTP clock support registered
600 17:15:54.987549 <6>[ 0.453827] EDAC MC: Ver: 3.0.0
601 17:15:54.987853 <6>[ 0.499864] scmi_core: SCMI protocol bus registered
602 17:15:54.988226 <6>[ 0.517177] vgaarb: loaded
603 17:15:54.988534 <6>[ 0.521019] clocksource: Switched to clocksource dmtimer
604 17:15:54.988820 <6>[ 0.566324] NET: Registered PF_INET protocol family
605 17:15:54.989113 <6>[ 0.571991] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
606 17:15:54.989439 <6>[ 0.580793] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
607 17:15:54.989737 <6>[ 0.589717] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
608 17:15:54.990471 <6>[ 0.597979] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
609 17:15:54.991002 <6>[ 0.606260] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
610 17:15:54.991478 <6>[ 0.613976] TCP: Hash tables configured (established 4096 bind 4096)
611 17:15:54.991961 <6>[ 0.620877] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
612 17:15:54.992485 <6>[ 0.627921] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
613 17:15:54.992949 <6>[ 0.635524] NET: Registered PF_UNIX/PF_LOCAL protocol family
614 17:15:54.993281 <6>[ 0.709984] RPC: Registered named UNIX socket transport module.
615 17:15:54.993580 <6>[ 0.716413] RPC: Registered udp transport module.
616 17:15:54.993862 <6>[ 0.721537] RPC: Registered tcp transport module.
617 17:15:54.994820 <6>[ 0.726641] RPC: Registered tcp-with-tls transport module.
618 17:15:55.000560 <6>[ 0.732569] RPC: Registered tcp NFSv4.1 backchannel transport module.
619 17:15:55.007784 <6>[ 0.739475] PCI: CLS 0 bytes, default 64
620 17:15:55.011742 <5>[ 0.745261] Initialise system trusted keyrings
621 17:15:55.032774 <6>[ 0.765295] Trying to unpack rootfs image as initramfs...
622 17:15:55.112089 <6>[ 0.841471] workingset: timestamp_bits=30 max_order=17 bucket_order=0
623 17:15:55.116857 <6>[ 0.848975] squashfs: version 4.0 (2009/01/31) Phillip Lougher
624 17:15:55.155947 <5>[ 0.891511] NFS: Registering the id_resolver key type
625 17:15:55.161735 <5>[ 0.897109] Key type id_resolver registered
626 17:15:55.167508 <5>[ 0.901778] Key type id_legacy registered
627 17:15:55.175913 <6>[ 0.906216] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
628 17:15:55.182863 <6>[ 0.913411] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
629 17:15:55.252183 <5>[ 0.987630] Key type asymmetric registered
630 17:15:55.257877 <5>[ 0.992219] Asymmetric key parser 'x509' registered
631 17:15:55.269352 <6>[ 0.997643] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
632 17:15:55.270005 <6>[ 1.005557] io scheduler mq-deadline registered
633 17:15:55.275173 <6>[ 1.010487] io scheduler kyber registered
634 17:15:55.280992 <6>[ 1.014975] io scheduler bfq registered
635 17:15:55.389887 <6>[ 1.121814] ledtrig-cpu: registered to indicate activity on CPUs
636 17:15:55.681612 <6>[ 1.413313] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
637 17:15:55.710981 <6>[ 1.446187] msm_serial: driver initialized
638 17:15:55.716949 <6>[ 1.451170] SuperH (H)SCI(F) driver initialized
639 17:15:55.722773 <6>[ 1.456342] STMicroelectronics ASC driver initialized
640 17:15:55.727959 <6>[ 1.462020] STM32 USART driver initialized
641 17:15:55.837571 <6>[ 1.572899] brd: module loaded
642 17:15:55.868559 <6>[ 1.604375] loop: module loaded
643 17:15:55.914271 <6>[ 1.648980] CAN device driver interface
644 17:15:55.920910 <6>[ 1.654267] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
645 17:15:55.926667 <6>[ 1.661359] e1000e: Intel(R) PRO/1000 Network Driver
646 17:15:55.932827 <6>[ 1.666746] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
647 17:15:55.938303 <6>[ 1.673221] igb: Intel(R) Gigabit Ethernet Network Driver
648 17:15:55.946538 <6>[ 1.679046] igb: Copyright (c) 2007-2014 Intel Corporation.
649 17:15:55.958821 <6>[ 1.688305] pegasus: Pegasus/Pegasus II USB Ethernet driver
650 17:15:55.964400 <6>[ 1.694464] usbcore: registered new interface driver pegasus
651 17:15:55.969962 <6>[ 1.700590] usbcore: registered new interface driver asix
652 17:15:55.975780 <6>[ 1.706475] usbcore: registered new interface driver ax88179_178a
653 17:15:55.982006 <6>[ 1.713065] usbcore: registered new interface driver cdc_ether
654 17:15:55.987284 <6>[ 1.719363] usbcore: registered new interface driver smsc75xx
655 17:15:55.993050 <6>[ 1.725599] usbcore: registered new interface driver smsc95xx
656 17:15:55.998926 <6>[ 1.731842] usbcore: registered new interface driver net1080
657 17:15:56.004993 <6>[ 1.737962] usbcore: registered new interface driver cdc_subset
658 17:15:56.010433 <6>[ 1.744373] usbcore: registered new interface driver zaurus
659 17:15:56.018016 <6>[ 1.750417] usbcore: registered new interface driver cdc_ncm
660 17:15:56.027921 <6>[ 1.759887] usbcore: registered new interface driver usb-storage
661 17:15:56.037080 <6>[ 1.770878] i2c_dev: i2c /dev entries driver
662 17:15:56.061242 <5>[ 1.788921] cpuidle: enable-method property 'ti,am3352' found operations
663 17:15:56.067540 <6>[ 1.798389] sdhci: Secure Digital Host Controller Interface driver
664 17:15:56.074459 <6>[ 1.805141] sdhci: Copyright(c) Pierre Ossman
665 17:15:56.081376 <6>[ 1.811635] Synopsys Designware Multimedia Card Interface Driver
666 17:15:56.086874 <6>[ 1.819402] sdhci-pltfm: SDHCI platform and OF driver helper
667 17:15:56.100891 <6>[ 1.829162] usbcore: registered new interface driver usbhid
668 17:15:56.101446 <6>[ 1.835280] usbhid: USB HID core driver
669 17:15:56.113572 <6>[ 1.846706] NET: Registered PF_INET6 protocol family
670 17:15:56.576656 <6>[ 2.312233] Segment Routing with IPv6
671 17:15:56.582239 <6>[ 2.316388] In-situ OAM (IOAM) with IPv6
672 17:15:56.589010 <6>[ 2.320788] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
673 17:15:56.594822 <6>[ 2.328151] NET: Registered PF_PACKET protocol family
674 17:15:56.600611 <6>[ 2.333724] can: controller area network core
675 17:15:56.606418 <6>[ 2.338546] NET: Registered PF_CAN protocol family
676 17:15:56.606928 <6>[ 2.343772] can: raw protocol
677 17:15:56.612199 <6>[ 2.347100] can: broadcast manager protocol
678 17:15:56.618833 <6>[ 2.351700] can: netlink gateway - max_hops=1
679 17:15:56.624853 <5>[ 2.357195] Key type dns_resolver registered
680 17:15:56.631112 <6>[ 2.362272] ThumbEE CPU extension supported.
681 17:15:56.631594 <5>[ 2.366962] Registering SWP/SWPB emulation handler
682 17:15:56.640953 <3>[ 2.372653] omap_voltage_late_init: Voltage driver support not added
683 17:15:56.838494 <5>[ 2.571730] Loading compiled-in X.509 certificates
684 17:15:56.977624 <6>[ 2.700428] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
685 17:15:56.984875 <6>[ 2.717086] pinctrl-single 44e10800.pinmux: 142 pins, size 568
686 17:15:57.010138 <3>[ 2.740776] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
687 17:15:57.221034 <3>[ 2.950753] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
688 17:15:57.418016 <6>[ 3.152052] OMAP GPIO hardware version 0.1
689 17:15:57.438876 <6>[ 3.170719] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
690 17:15:57.531295 <4>[ 3.262970] at24 2-0054: supply vcc not found, using dummy regulator
691 17:15:57.576085 <4>[ 3.307692] at24 2-0055: supply vcc not found, using dummy regulator
692 17:15:57.620318 <4>[ 3.351924] at24 2-0056: supply vcc not found, using dummy regulator
693 17:15:57.655448 <4>[ 3.387106] at24 2-0057: supply vcc not found, using dummy regulator
694 17:15:57.702285 <6>[ 3.434734] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
695 17:15:57.775392 <3>[ 3.503787] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
696 17:15:57.799951 <6>[ 3.524759] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
697 17:15:57.822114 <4>[ 3.551301] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
698 17:15:57.829762 <4>[ 3.560272] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
699 17:15:57.969837 <6>[ 3.701772] omap_rng 48310000.rng: Random Number Generator ver. 20
700 17:15:57.993339 <5>[ 3.728146] random: crng init done
701 17:15:58.050515 <6>[ 3.786170] Freeing initrd memory: 14444K
702 17:15:58.060314 <6>[ 3.790806] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
703 17:15:58.113885 <6>[ 3.843436] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
704 17:15:58.119680 <6>[ 3.853768] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
705 17:15:58.131416 <6>[ 3.861106] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
706 17:15:58.137252 <6>[ 3.868553] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
707 17:15:58.148765 <6>[ 3.876689] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
708 17:15:58.156107 <6>[ 3.888316] cpsw-switch 4a100000.switch: Detected MACID = 78:a5:04:e2:4c:3d
709 17:15:58.169314 <5>[ 3.897341] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
710 17:15:58.197100 <3>[ 3.927163] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
711 17:15:58.202839 <6>[ 3.935752] edma 49000000.dma: TI EDMA DMA engine driver
712 17:15:58.272619 <3>[ 4.002020] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
713 17:15:58.289536 <6>[ 4.018570] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
714 17:15:58.302907 <3>[ 4.036146] l3-aon-clkctrl:0000:0: failed to disable
715 17:15:58.352147 <6>[ 4.082124] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
716 17:15:58.357753 <6>[ 4.091583] printk: legacy console [ttyS0] enabled
717 17:15:58.360552 <6>[ 4.091583] printk: legacy console [ttyS0] enabled
718 17:15:58.366152 <6>[ 4.101909] printk: legacy bootconsole [omap8250] disabled
719 17:15:58.371852 <6>[ 4.101909] printk: legacy bootconsole [omap8250] disabled
720 17:15:58.412701 <4>[ 4.141783] tps65217-pmic: Failed to locate of_node [id: -1]
721 17:15:58.416286 <4>[ 4.149155] tps65217-bl: Failed to locate of_node [id: -1]
722 17:15:58.432635 <6>[ 4.168711] tps65217 0-0024: TPS65217 ID 0xe version 1.2
723 17:15:58.451129 <6>[ 4.175667] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
724 17:15:58.462767 <6>[ 4.189353] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
725 17:15:58.468473 <6>[ 4.201252] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
726 17:15:58.490447 <6>[ 4.220810] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
727 17:15:58.496359 <6>[ 4.230003] sdhci-omap 48060000.mmc: Got CD GPIO
728 17:15:58.504366 <4>[ 4.235160] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
729 17:15:58.519020 <4>[ 4.248750] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
730 17:15:58.525430 <4>[ 4.257407] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
731 17:15:58.535304 <4>[ 4.266100] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
732 17:15:58.658932 <6>[ 4.390305] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
733 17:15:58.704801 <6>[ 4.434007] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
734 17:15:58.711333 <6>[ 4.443339] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
735 17:15:58.720458 <6>[ 4.452305] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
736 17:15:58.779763 <6>[ 4.505167] mmc0: new high speed SDHC card at address 1234
737 17:15:58.780294 <6>[ 4.513700] mmcblk0: mmc0:1234 SA32G 29.1 GiB
738 17:15:58.788846 <6>[ 4.524634] mmcblk0: p1
739 17:15:58.805398 <6>[ 4.533183] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
740 17:15:58.828709 <6>[ 4.555018] mmc1: new high speed MMC card at address 0001
741 17:15:58.829175 <6>[ 4.562020] mmcblk1: mmc1:0001 MMC04G 3.60 GiB
742 17:15:58.834127 <6>[ 4.569640] mmcblk1boot0: mmc1:0001 MMC04G 2.00 MiB
743 17:15:58.842533 <6>[ 4.576776] mmcblk1boot1: mmc1:0001 MMC04G 2.00 MiB
744 17:15:58.851604 <6>[ 4.583801] mmcblk1rpmb: mmc1:0001 MMC04G 128 KiB, chardev (236:0)
745 17:16:00.952168 <6>[ 6.682072] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
746 17:16:01.025412 <5>[ 6.721106] Sending DHCP requests ., OK
747 17:16:01.036755 <6>[ 6.765549] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.12
748 17:16:01.037257 <6>[ 6.773672] IP-Config: Complete:
749 17:16:01.050932 <6>[ 6.777207] device=eth0, hwaddr=78:a5:04:e2:4c:3d, ipaddr=192.168.6.12, mask=255.255.255.0, gw=192.168.6.1
750 17:16:01.056607 <6>[ 6.787744] host=192.168.6.12, domain=, nis-domain=(none)
751 17:16:01.062342 <6>[ 6.793957] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
752 17:16:01.068904 <6>[ 6.793991] nameserver0=10.255.253.1
753 17:16:01.078073 <6>[ 6.806530] clk: Disabling unused clocks
754 17:16:01.078556 <6>[ 6.811295] PM: genpd: Disabling unused power domains
755 17:16:01.097334 <6>[ 6.829735] Freeing unused kernel image (initmem) memory: 2048K
756 17:16:01.104749 <6>[ 6.839476] Run /init as init process
757 17:16:01.127688 Loading, please wait...
758 17:16:01.203418 Starting systemd-udevd version 252.22-1~deb12u1
759 17:16:04.273908 <4>[ 10.002548] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
760 17:16:04.443695 <4>[ 10.172574] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
761 17:16:04.567295 <6>[ 10.303597] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
762 17:16:04.577222 <6>[ 10.309271] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
763 17:16:04.777323 <6>[ 10.511839] hub 1-0:1.0: USB hub found
764 17:16:04.846846 <6>[ 10.581246] hub 1-0:1.0: 1 port detected
765 17:16:04.862799 <6>[ 10.597087] tda998x 0-0070: found TDA19988
766 17:16:08.228409 Begin: Loading essential drivers ... done.
767 17:16:08.234070 Begin: Running /scripts/init-premount ... done.
768 17:16:08.239468 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
769 17:16:08.249593 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
770 17:16:08.258771 Device /sys/class/net/eth0 found
771 17:16:08.259283 done.
772 17:16:08.339583 Begin: Waiting up to 180 secs for any network device to become available ... done.
773 17:16:08.428100 IP-Config: eth0 hardware address 78:a5:04:e2:4c:3d mtu 1500 DHCP
774 17:16:08.453507 IP-Config: eth0 guessed broadcast address 192.168.6.255
775 17:16:08.459164 IP-Config: eth0 complete (dhcp from 192.168.6.1):
776 17:16:08.465020 address: 192.168.6.12 broadcast: 192.168.6.255 netmask: 255.255.255.0
777 17:16:08.475867 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
778 17:16:08.476423 rootserver: 192.168.6.1 rootpath:
779 17:16:08.478425 filename :
780 17:16:08.591523 done.
781 17:16:08.602384 Begin: Running /scripts/nfs-bottom ... done.
782 17:16:08.679673 Begin: Running /scripts/init-bottom ... done.
783 17:16:10.105191 <30>[ 15.837594] systemd[1]: System time before build time, advancing clock.
784 17:16:10.301318 <30>[ 16.007827] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
785 17:16:10.311223 <30>[ 16.045132] systemd[1]: Detected architecture arm.
786 17:16:10.324129
787 17:16:10.324719 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
788 17:16:10.325194
789 17:16:10.348415 <30>[ 16.081265] systemd[1]: Hostname set to <debian-bookworm-armhf>.
790 17:16:12.587327 <30>[ 18.318866] systemd[1]: Queued start job for default target graphical.target.
791 17:16:12.604380 <30>[ 18.333779] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
792 17:16:12.611850 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
793 17:16:12.634376 <30>[ 18.363979] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
794 17:16:12.642913 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
795 17:16:12.664620 <30>[ 18.394360] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
796 17:16:12.672942 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
797 17:16:12.692907 <30>[ 18.423021] systemd[1]: Created slice user.slice - User and Session Slice.
798 17:16:12.699690 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
799 17:16:12.729076 <30>[ 18.452443] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
800 17:16:12.734997 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
801 17:16:12.762968 <30>[ 18.492207] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
802 17:16:12.773952 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
803 17:16:12.800476 <30>[ 18.522174] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
804 17:16:12.814197 <30>[ 18.544240] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
805 17:16:12.818816 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
806 17:16:12.841196 <30>[ 18.571541] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
807 17:16:12.849538 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
808 17:16:12.871853 <30>[ 18.601829] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
809 17:16:12.880580 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
810 17:16:12.901591 <30>[ 18.632084] systemd[1]: Reached target paths.target - Path Units.
811 17:16:12.905875 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
812 17:16:12.931109 <30>[ 18.661645] systemd[1]: Reached target remote-fs.target - Remote File Systems.
813 17:16:12.938236 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
814 17:16:12.961241 <30>[ 18.691557] systemd[1]: Reached target slices.target - Slice Units.
815 17:16:12.966704 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
816 17:16:12.991363 <30>[ 18.721756] systemd[1]: Reached target swap.target - Swaps.
817 17:16:12.994469 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
818 17:16:13.021674 <30>[ 18.751826] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
819 17:16:13.029749 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
820 17:16:13.052719 <30>[ 18.782759] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
821 17:16:13.061058 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
822 17:16:13.154354 <30>[ 18.879460] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
823 17:16:13.167156 <30>[ 18.897114] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
824 17:16:13.175585 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
825 17:16:13.203691 <30>[ 18.935401] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
826 17:16:13.216226 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
827 17:16:13.245196 <30>[ 18.974155] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
828 17:16:13.252460 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
829 17:16:13.288156 <30>[ 19.018848] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
830 17:16:13.301478 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
831 17:16:13.323121 <30>[ 19.052955] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
832 17:16:13.331692 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
833 17:16:13.358711 <30>[ 19.082760] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
834 17:16:13.375356 <30>[ 19.099424] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
835 17:16:13.425247 <30>[ 19.156244] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
836 17:16:13.451668 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
837 17:16:13.503381 <30>[ 19.234277] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
838 17:16:13.526636 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
839 17:16:13.602271 <30>[ 19.332254] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
840 17:16:13.620918 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
841 17:16:13.681878 <30>[ 19.412449] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
842 17:16:13.703380 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
843 17:16:13.771436 <30>[ 19.502285] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
844 17:16:13.794237 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
845 17:16:13.850493 <30>[ 19.582828] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
846 17:16:13.871431 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
847 17:16:13.902117 <30>[ 19.633312] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
848 17:16:13.934276 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
849 17:16:13.980938 <30>[ 19.712266] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
850 17:16:13.996914 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
851 17:16:14.063113 <30>[ 19.794431] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
852 17:16:14.090519 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
853 17:16:14.119086 <28>[ 19.843355] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
854 17:16:14.127178 <28>[ 19.858016] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
855 17:16:14.170758 <30>[ 19.902519] systemd[1]: Starting systemd-journald.service - Journal Service...
856 17:16:14.181979 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
857 17:16:14.263025 <30>[ 19.994103] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
858 17:16:14.281695 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
859 17:16:14.315395 <30>[ 20.046622] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
860 17:16:14.361960 Starting [0;1;39msystemd-network-g… units from Kernel command line...
861 17:16:14.405909 <30>[ 20.135678] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
862 17:16:14.470069 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
863 17:16:14.526916 <30>[ 20.257428] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
864 17:16:14.591842 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
865 17:16:14.647614 <30>[ 20.379031] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
866 17:16:14.715295 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
867 17:16:14.731960 <30>[ 20.463239] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
868 17:16:14.761951 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
869 17:16:14.786030 <30>[ 20.516211] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
870 17:16:14.818947 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
871 17:16:14.971623 <30>[ 20.703580] systemd[1]: modprobe@configfs.service: Deactivated successfully.
872 17:16:15.002219 <30>[ 20.733045] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
873 17:16:15.031085 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
874 17:16:15.051651 <30>[ 20.783805] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
875 17:16:15.090954 <30>[ 20.821454] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
876 17:16:15.099418 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
877 17:16:15.112190 <30>[ 20.842760] systemd[1]: Started systemd-journald.service - Journal Service.
878 17:16:15.119057 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
879 17:16:15.162266 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
880 17:16:15.192577 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
881 17:16:15.225662 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
882 17:16:15.262202 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
883 17:16:15.291214 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
884 17:16:15.314488 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
885 17:16:15.343631 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
886 17:16:15.371165 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
887 17:16:15.430788 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
888 17:16:15.501524 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
889 17:16:15.572146 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
890 17:16:15.647786 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
891 17:16:15.733996 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
892 17:16:15.870930 <46>[ 21.603003] systemd-journald[168]: Received client request to flush runtime journal.
893 17:16:15.890578 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
894 17:16:15.953611 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
895 17:16:16.593872 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
896 17:16:17.232917 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
897 17:16:17.303177 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
898 17:16:17.642832 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
899 17:16:17.834410 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
900 17:16:17.852908 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
901 17:16:17.870091 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
902 17:16:17.931312 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
903 17:16:17.970785 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
904 17:16:18.959171 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
905 17:16:19.020109 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
906 17:16:19.097405 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
907 17:16:19.209806 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
908 17:16:19.241372 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
909 17:16:20.970210 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
910 17:16:21.973192 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
911 17:16:22.060100 <5>[ 27.791761] cfg80211: Loading compiled-in X.509 certificates for regulatory database
912 17:16:22.885573 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
913 17:16:23.435860 <5>[ 29.170599] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
914 17:16:23.455342 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
915 17:16:23.517411 <5>[ 29.250725] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
916 17:16:23.542834 <4>[ 29.274474] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
917 17:16:23.547803 <6>[ 29.283598] cfg80211: failed to load regulatory.db
918 17:16:23.830823 <46>[ 29.553125] systemd-journald[168]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
919 17:16:24.026472 <46>[ 29.752233] systemd-journald[168]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
920 17:16:24.777999 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
921 17:16:33.298335 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
922 17:16:33.327329 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
923 17:16:33.352427 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
924 17:16:33.371798 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
925 17:16:33.439954 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
926 17:16:33.490628 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
927 17:16:33.539683 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
928 17:16:33.613857 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
929 17:16:33.657265 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
930 17:16:33.685948 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
931 17:16:33.718142 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
932 17:16:33.746052 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
933 17:16:33.786374 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
934 17:16:33.817676 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
935 17:16:33.850370 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
936 17:16:33.881202 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
937 17:16:33.907139 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
938 17:16:33.937773 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
939 17:16:33.961348 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
940 17:16:33.982696 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
941 17:16:34.018482 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
942 17:16:34.043814 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
943 17:16:34.073183 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
944 17:16:34.140401 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
945 17:16:34.179261 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
946 17:16:34.281744 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
947 17:16:34.365470 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
948 17:16:34.436561 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
949 17:16:34.468291 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
950 17:16:34.504666 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
951 17:16:34.704876 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
952 17:16:34.750940 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
953 17:16:34.790805 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
954 17:16:34.814523 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
955 17:16:34.843121 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
956 17:16:35.090195 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
957 17:16:35.502283 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
958 17:16:35.547214 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
959 17:16:35.576167 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
960 17:16:35.654801 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
961 17:16:35.846663 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
962 17:16:35.995781
963 17:16:35.996451 Debian GNU/Linux 1worm-armhf login: root (automatic login)
964 17:16:35.998704
965 17:16:36.324299 Linux debian-bookworm-armhf 6.12.0-rc6 #1 SMP Wed Nov 6 16:59:24 UTC 2024 armv7l
966 17:16:36.324959
967 17:16:36.329844 The programs included with the Debian GNU/Linux system are free software;
968 17:16:36.333288 the exact distribution terms for each program are described in the
969 17:16:36.338844 individual files in /usr/share/doc/*/copyright.
970 17:16:36.339374
971 17:16:36.344336 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
972 17:16:36.348876 permitted by applicable law.
973 17:16:41.064275 Unable to match end of the kernel message
975 17:16:41.065963 Setting prompt string to ['/ #']
976 17:16:41.066597 end: 2.4.4.1 login-action (duration 00:00:47) [common]
978 17:16:41.068220 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
979 17:16:41.068844 start: 2.4.5 expect-shell-connection (timeout 00:03:14) [common]
980 17:16:41.069382 Setting prompt string to ['/ #']
981 17:16:41.069884 Forcing a shell prompt, looking for ['/ #']
983 17:16:41.120996 / #
984 17:16:41.121794 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
985 17:16:41.122300 Waiting using forced prompt support (timeout 00:02:30)
986 17:16:41.125329
987 17:16:41.134258 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
988 17:16:41.134940 start: 2.4.6 export-device-env (timeout 00:03:14) [common]
989 17:16:41.135460 Sending with 10 millisecond of delay
991 17:16:46.124858 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/948111/extract-nfsrootfs-_iigzxnu'
992 17:16:46.135890 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/948111/extract-nfsrootfs-_iigzxnu'
993 17:16:46.136834 Sending with 10 millisecond of delay
995 17:16:48.235398 / # export NFS_SERVER_IP='192.168.6.2'
996 17:16:48.246439 export NFS_SERVER_IP='192.168.6.2'
997 17:16:48.247417 end: 2.4.6 export-device-env (duration 00:00:07) [common]
998 17:16:48.248091 end: 2.4 uboot-commands (duration 00:01:53) [common]
999 17:16:48.248746 end: 2 uboot-action (duration 00:01:54) [common]
1000 17:16:48.249376 start: 3 lava-test-retry (timeout 00:06:56) [common]
1001 17:16:48.250009 start: 3.1 lava-test-shell (timeout 00:06:56) [common]
1002 17:16:48.250520 Using namespace: common
1004 17:16:48.351761 / # #
1005 17:16:48.352431 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1006 17:16:48.357245 #
1007 17:16:48.364121 Using /lava-948111
1009 17:16:48.465313 / # export SHELL=/bin/bash
1010 17:16:48.470695 export SHELL=/bin/bash
1012 17:16:48.577172 / # . /lava-948111/environment
1013 17:16:48.582570 . /lava-948111/environment
1015 17:16:48.695874 / # /lava-948111/bin/lava-test-runner /lava-948111/0
1016 17:16:48.696622 Test shell timeout: 10s (minimum of the action and connection timeout)
1017 17:16:48.700340 /lava-948111/bin/lava-test-runner /lava-948111/0
1018 17:16:49.088922 + export TESTRUN_ID=0_timesync-off
1019 17:16:49.096751 + TESTRUN_ID=0_timesync-off
1020 17:16:49.097248 + cd /lava-948111/0/tests/0_timesync-off
1021 17:16:49.097719 ++ cat uuid
1022 17:16:49.112672 + UUID=948111_1.6.2.4.1
1023 17:16:49.113159 + set +x
1024 17:16:49.121282 <LAVA_SIGNAL_STARTRUN 0_timesync-off 948111_1.6.2.4.1>
1025 17:16:49.121765 + systemctl stop systemd-timesyncd
1026 17:16:49.122519 Received signal: <STARTRUN> 0_timesync-off 948111_1.6.2.4.1
1027 17:16:49.122997 Starting test lava.0_timesync-off (948111_1.6.2.4.1)
1028 17:16:49.123567 Skipping test definition patterns.
1029 17:16:49.450704 + set +x
1030 17:16:49.451239 <LAVA_SIGNAL_ENDRUN 0_timesync-off 948111_1.6.2.4.1>
1031 17:16:49.451962 Received signal: <ENDRUN> 0_timesync-off 948111_1.6.2.4.1
1032 17:16:49.452582 Ending use of test pattern.
1033 17:16:49.453040 Ending test lava.0_timesync-off (948111_1.6.2.4.1), duration 0.33
1035 17:16:49.627891 + export TESTRUN_ID=1_kselftest-dt
1036 17:16:49.636011 + TESTRUN_ID=1_kselftest-dt
1037 17:16:49.636510 + cd /lava-948111/0/tests/1_kselftest-dt
1038 17:16:49.636976 ++ cat uuid
1039 17:16:49.654378 + UUID=948111_1.6.2.4.5
1040 17:16:49.654859 + set +x
1041 17:16:49.657076 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 948111_1.6.2.4.5>
1042 17:16:49.657559 + cd ./automated/linux/kselftest/
1043 17:16:49.658287 Received signal: <STARTRUN> 1_kselftest-dt 948111_1.6.2.4.5
1044 17:16:49.658751 Starting test lava.1_kselftest-dt (948111_1.6.2.4.5)
1045 17:16:49.659277 Skipping test definition patterns.
1046 17:16:49.684369 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/pm/testing/v6.12-rc6-116-g471463faceb56/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g pm -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1047 17:16:49.822814 INFO: install_deps skipped
1048 17:16:50.405250 --2024-11-06 17:16:50-- http://storage.kernelci.org/pm/testing/v6.12-rc6-116-g471463faceb56/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1049 17:16:50.673887 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1050 17:16:50.816120 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1051 17:16:50.956890 HTTP request sent, awaiting response... 200 OK
1052 17:16:50.957367 Length: 4107232 (3.9M) [application/octet-stream]
1053 17:16:50.962519 Saving to: 'kselftest_armhf.tar.gz'
1054 17:16:50.962988
1055 17:16:53.033711
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 44.73K 162KB/s
kselftest_armhf.tar 5%[> ] 208.82K 376KB/s
kselftest_armhf.tar 16%[==> ] 656.01K 736KB/s
kselftest_armhf.tar 30%[=====> ] 1.19M 1.07MB/s
kselftest_armhf.tar 43%[=======> ] 1.70M 1.30MB/s
kselftest_armhf.tar 58%[==========> ] 2.29M 1.50MB/s
kselftest_armhf.tar 72%[=============> ] 2.84M 1.64MB/s
kselftest_armhf.tar 90%[=================> ] 3.53M 1.81MB/s
kselftest_armhf.tar 100%[===================>] 3.92M 1.89MB/s in 2.1s
1056 17:16:53.034340
1057 17:16:53.544469 2024-11-06 17:16:53 (1.89 MB/s) - 'kselftest_armhf.tar.gz' saved [4107232/4107232]
1058 17:16:53.545121
1059 17:17:05.919939 skiplist:
1060 17:17:05.920363 ========================================
1061 17:17:05.925652 ========================================
1062 17:17:06.031272 dt:test_unprobed_devices.sh
1063 17:17:06.059244 ============== Tests to run ===============
1064 17:17:06.068586 dt:test_unprobed_devices.sh
1065 17:17:06.072536 ===========End Tests to run ===============
1066 17:17:06.082686 shardfile-dt pass
1067 17:17:06.322207 <12>[ 72.059827] kselftest: Running tests in dt
1068 17:17:06.350500 TAP version 13
1069 17:17:06.373636 1..1
1070 17:17:06.427395 # timeout set to 45
1071 17:17:06.427947 # selftests: dt: test_unprobed_devices.sh
1072 17:17:07.251044 # TAP version 13
1073 17:17:32.063621 # 1..257
1074 17:17:32.237779 # ok 1 / # SKIP
1075 17:17:32.254266 # ok 2 /clk_mcasp0
1076 17:17:32.325754 # ok 3 /clk_mcasp0_fixed # SKIP
1077 17:17:32.398775 # ok 4 /cpus/cpu@0 # SKIP
1078 17:17:32.465108 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1079 17:17:32.485780 # ok 6 /fixedregulator0
1080 17:17:32.508740 # ok 7 /leds
1081 17:17:32.526994 # ok 8 /ocp
1082 17:17:32.551172 # ok 9 /ocp/interconnect@44c00000
1083 17:17:32.578618 # ok 10 /ocp/interconnect@44c00000/segment@0
1084 17:17:32.601353 # ok 11 /ocp/interconnect@44c00000/segment@100000
1085 17:17:32.621285 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1086 17:17:32.694488 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1087 17:17:32.719060 # ok 14 /ocp/interconnect@44c00000/segment@200000
1088 17:17:32.738793 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1089 17:17:32.841659 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1090 17:17:32.914087 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1091 17:17:32.990802 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1092 17:17:33.058036 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1093 17:17:33.129476 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1094 17:17:33.200353 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1095 17:17:33.271006 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1096 17:17:33.341773 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1097 17:17:33.413242 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1098 17:17:33.485020 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1099 17:17:33.561282 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1100 17:17:33.631808 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1101 17:17:33.703317 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1102 17:17:33.775426 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1103 17:17:33.844655 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1104 17:17:33.911578 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1105 17:17:33.984668 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1106 17:17:34.054373 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1107 17:17:34.125012 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1108 17:17:34.198517 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1109 17:17:34.266572 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1110 17:17:34.341439 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1111 17:17:34.414407 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1112 17:17:34.485401 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1113 17:17:34.555894 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1114 17:17:34.626767 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1115 17:17:34.693002 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1116 17:17:34.764781 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1117 17:17:34.834905 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1118 17:17:34.908050 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1119 17:17:34.976401 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1120 17:17:35.052797 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1121 17:17:35.123208 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1122 17:17:35.194565 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1123 17:17:35.266697 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1124 17:17:35.337148 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1125 17:17:35.405752 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1126 17:17:35.476815 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1127 17:17:35.553201 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1128 17:17:35.623581 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1129 17:17:35.694657 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1130 17:17:35.767174 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1131 17:17:35.836338 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1132 17:17:35.904266 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1133 17:17:35.976397 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1134 17:17:36.047789 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1135 17:17:36.117993 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1136 17:17:36.191689 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1137 17:17:36.263042 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1138 17:17:36.333010 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1139 17:17:36.408538 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1140 17:17:36.483781 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1141 17:17:36.555834 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1142 17:17:36.623133 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1143 17:17:36.700369 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1144 17:17:36.771667 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1145 17:17:36.844026 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1146 17:17:36.917116 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1147 17:17:36.989694 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1148 17:17:37.061097 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1149 17:17:37.132158 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1150 17:17:37.204256 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1151 17:17:37.276405 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1152 17:17:37.347075 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1153 17:17:37.441994 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1154 17:17:37.518689 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1155 17:17:37.590503 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1156 17:17:37.661609 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1157 17:17:37.733209 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1158 17:17:37.804104 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1159 17:17:37.885174 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1160 17:17:37.954032 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1161 17:17:38.024964 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1162 17:17:38.094196 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1163 17:17:38.169239 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1164 17:17:38.237021 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1165 17:17:38.310255 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1166 17:17:38.381691 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1167 17:17:38.453056 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1168 17:17:38.476217 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1169 17:17:38.497625 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1170 17:17:38.520803 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1171 17:17:38.549547 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1172 17:17:38.574448 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1173 17:17:38.599417 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1174 17:17:38.622641 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1175 17:17:38.645348 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1176 17:17:38.746483 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1177 17:17:38.771833 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1178 17:17:38.795699 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1179 17:17:38.818926 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1180 17:17:38.926202 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1181 17:17:39.004573 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1182 17:17:39.076189 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1183 17:17:39.147672 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1184 17:17:39.215594 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1185 17:17:39.287770 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1186 17:17:39.358724 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1187 17:17:39.435533 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1188 17:17:39.503385 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1189 17:17:39.575354 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1190 17:17:39.651243 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1191 17:17:39.725723 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1192 17:17:39.797063 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1193 17:17:39.871948 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1194 17:17:39.941986 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1195 17:17:40.013456 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1196 17:17:40.033568 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1197 17:17:40.105387 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1198 17:17:40.179034 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1199 17:17:40.251455 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1200 17:17:40.273620 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1201 17:17:40.340975 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1202 17:17:40.365996 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1203 17:17:40.433681 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1204 17:17:40.456292 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1205 17:17:40.481157 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1206 17:17:40.508545 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1207 17:17:40.533104 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1208 17:17:40.553507 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1209 17:17:40.580089 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1210 17:17:40.605785 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1211 17:17:40.675373 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1212 17:17:40.697263 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1213 17:17:40.720503 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1214 17:17:40.790356 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1215 17:17:40.861633 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1216 17:17:40.882238 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1217 17:17:40.983601 # not ok 144 /ocp/interconnect@47c00000
1218 17:17:41.059159 # not ok 145 /ocp/interconnect@47c00000/segment@0
1219 17:17:41.080180 # ok 146 /ocp/interconnect@48000000
1220 17:17:41.098954 # ok 147 /ocp/interconnect@48000000/segment@0
1221 17:17:41.123487 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1222 17:17:41.151418 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1223 17:17:41.172936 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1224 17:17:41.193483 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1225 17:17:41.221714 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1226 17:17:41.243833 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1227 17:17:41.263876 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1228 17:17:41.341005 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1229 17:17:41.413248 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1230 17:17:41.432976 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1231 17:17:41.459688 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1232 17:17:41.482196 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1233 17:17:41.503743 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1234 17:17:41.524859 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1235 17:17:41.547540 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1236 17:17:41.572640 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1237 17:17:41.595713 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1238 17:17:41.617871 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1239 17:17:41.641748 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1240 17:17:41.670410 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1241 17:17:41.690615 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1242 17:17:41.719069 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1243 17:17:41.742944 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1244 17:17:41.763024 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1245 17:17:41.784879 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1246 17:17:41.806734 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1247 17:17:41.833990 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1248 17:17:41.853117 # ok 175 /ocp/interconnect@48000000/segment@100000
1249 17:17:41.880910 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1250 17:17:41.903953 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1251 17:17:41.974740 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1252 17:17:42.051903 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1253 17:17:42.118499 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1254 17:17:42.197623 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1255 17:17:42.260672 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1256 17:17:42.332977 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1257 17:17:42.402027 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1258 17:17:42.474946 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1259 17:17:42.496177 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1260 17:17:42.522850 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1261 17:17:42.543543 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1262 17:17:42.565326 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1263 17:17:42.592369 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1264 17:17:42.614101 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1265 17:17:42.636422 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1266 17:17:42.663291 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1267 17:17:42.691224 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1268 17:17:42.706666 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1269 17:17:42.730295 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1270 17:17:42.754920 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1271 17:17:42.774845 # ok 198 /ocp/interconnect@48000000/segment@200000
1272 17:17:42.799515 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1273 17:17:42.878561 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1274 17:17:42.895290 # ok 201 /ocp/interconnect@48000000/segment@300000
1275 17:17:42.918621 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1276 17:17:42.948594 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1277 17:17:42.967917 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1278 17:17:42.989741 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1279 17:17:43.014009 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1280 17:17:43.041282 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1281 17:17:43.113614 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1282 17:17:43.129299 # ok 209 /ocp/interconnect@4a000000
1283 17:17:43.155240 # ok 210 /ocp/interconnect@4a000000/segment@0
1284 17:17:43.179505 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1285 17:17:43.203730 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1286 17:17:43.225637 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1287 17:17:43.247750 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1288 17:17:43.318933 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1289 17:17:43.423594 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1290 17:17:43.495232 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1291 17:17:43.597777 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1292 17:17:43.667307 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1293 17:17:43.737764 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1294 17:17:43.835453 # not ok 221 /ocp/interconnect@4b140000
1295 17:17:43.910943 # not ok 222 /ocp/interconnect@4b140000/segment@0
1296 17:17:43.981712 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1297 17:17:43.998264 # ok 224 /ocp/target-module@40300000
1298 17:17:44.024548 # ok 225 /ocp/target-module@40300000/sram@0
1299 17:17:44.094424 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1300 17:17:44.164935 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1301 17:17:44.188491 # ok 228 /ocp/target-module@47400000
1302 17:17:44.213730 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1303 17:17:44.229819 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1304 17:17:44.252389 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1305 17:17:44.274212 # ok 232 /ocp/target-module@47400000/usb@1400
1306 17:17:44.296467 # ok 233 /ocp/target-module@47400000/usb@1800
1307 17:17:44.317847 # ok 234 /ocp/target-module@47810000
1308 17:17:44.339800 # ok 235 /ocp/target-module@49000000
1309 17:17:44.367028 # ok 236 /ocp/target-module@49000000/dma@0
1310 17:17:44.388575 # ok 237 /ocp/target-module@49800000
1311 17:17:44.410900 # ok 238 /ocp/target-module@49800000/dma@0
1312 17:17:44.430406 # ok 239 /ocp/target-module@49900000
1313 17:17:44.457107 # ok 240 /ocp/target-module@49900000/dma@0
1314 17:17:44.478298 # ok 241 /ocp/target-module@49a00000
1315 17:17:44.500865 # ok 242 /ocp/target-module@49a00000/dma@0
1316 17:17:44.520364 # ok 243 /ocp/target-module@4c000000
1317 17:17:44.590079 # not ok 244 /ocp/target-module@4c000000/emif@0
1318 17:17:44.615849 # ok 245 /ocp/target-module@50000000
1319 17:17:44.637826 # ok 246 /ocp/target-module@53100000
1320 17:17:44.706099 # not ok 247 /ocp/target-module@53100000/sham@0
1321 17:17:44.730297 # ok 248 /ocp/target-module@53500000
1322 17:17:44.800258 # not ok 249 /ocp/target-module@53500000/aes@0
1323 17:17:44.818127 # ok 250 /ocp/target-module@56000000
1324 17:17:44.925074 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1325 17:17:44.998089 # ok 252 /opp-table # SKIP
1326 17:17:45.067676 # ok 253 /soc # SKIP
1327 17:17:45.084604 # ok 254 /sound
1328 17:17:45.110122 # ok 255 /target-module@4b000000
1329 17:17:45.137411 # ok 256 /target-module@4b000000/target-module@140000
1330 17:17:45.154347 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1331 17:17:45.162860 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1332 17:17:45.170769 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1333 17:17:47.462361 dt_test_unprobed_devices_sh_ skip
1334 17:17:47.467881 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1335 17:17:47.473439 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1336 17:17:47.473996 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1337 17:17:47.482426 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1338 17:17:47.482902 dt_test_unprobed_devices_sh_fixedregulator0 pass
1339 17:17:47.487814 dt_test_unprobed_devices_sh_leds pass
1340 17:17:47.493445 dt_test_unprobed_devices_sh_ocp pass
1341 17:17:47.499056 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1342 17:17:47.504656 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1343 17:17:47.510255 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1344 17:17:47.515865 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1345 17:17:47.527078 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1346 17:17:47.532695 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1347 17:17:47.538291 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1348 17:17:47.549551 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1349 17:17:47.555225 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1350 17:17:47.566380 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1351 17:17:47.577612 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1352 17:17:47.588786 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1353 17:17:47.600072 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1354 17:17:47.605629 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1355 17:17:47.616931 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1356 17:17:47.628155 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1357 17:17:47.639307 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1358 17:17:47.650540 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1359 17:17:47.656192 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1360 17:17:47.667337 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1361 17:17:47.678510 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1362 17:17:47.689684 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1363 17:17:47.700913 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1364 17:17:47.706486 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1365 17:17:47.717690 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1366 17:17:47.728892 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1367 17:17:47.740214 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1368 17:17:47.745701 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1369 17:17:47.756937 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1370 17:17:47.768223 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1371 17:17:47.779366 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1372 17:17:47.790494 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1373 17:17:47.801685 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1374 17:17:47.812898 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1375 17:17:47.824107 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1376 17:17:47.835286 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1377 17:17:47.846491 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1378 17:17:47.857666 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1379 17:17:47.868875 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1380 17:17:47.880106 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1381 17:17:47.891252 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1382 17:17:47.902441 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1383 17:17:47.913626 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1384 17:17:47.924854 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1385 17:17:47.936077 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1386 17:17:47.947249 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1387 17:17:47.958369 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1388 17:17:47.969579 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1389 17:17:47.980715 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1390 17:17:47.991947 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1391 17:17:47.997506 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1392 17:17:48.008708 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1393 17:17:48.019889 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1394 17:17:48.031127 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1395 17:17:48.042329 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1396 17:17:48.053496 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1397 17:17:48.064770 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1398 17:17:48.075833 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1399 17:17:48.087070 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1400 17:17:48.098347 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1401 17:17:48.103964 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1402 17:17:48.115140 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1403 17:17:48.126310 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1404 17:17:48.137408 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1405 17:17:48.148607 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1406 17:17:48.159808 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1407 17:17:48.171041 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1408 17:17:48.182186 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1409 17:17:48.193362 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1410 17:17:48.204569 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1411 17:17:48.215802 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1412 17:17:48.227007 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1413 17:17:48.238182 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1414 17:17:48.249458 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1415 17:17:48.260575 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1416 17:17:48.271729 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1417 17:17:48.277356 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1418 17:17:48.288549 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1419 17:17:48.299692 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1420 17:17:48.310888 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1421 17:17:48.322187 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1422 17:17:48.333278 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1423 17:17:48.344466 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1424 17:17:48.355646 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1425 17:17:48.366864 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1426 17:17:48.378140 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1427 17:17:48.389244 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1428 17:17:48.400415 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1429 17:17:48.406037 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1430 17:17:48.417225 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1431 17:17:48.428411 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1432 17:17:48.434010 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1433 17:17:48.445238 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1434 17:17:48.450807 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1435 17:17:48.462020 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1436 17:17:48.473244 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1437 17:17:48.478798 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1438 17:17:48.489985 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1439 17:17:48.501182 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1440 17:17:48.512391 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1441 17:17:48.523601 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1442 17:17:48.534897 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1443 17:17:48.545971 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1444 17:17:48.562775 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1445 17:17:48.573952 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1446 17:17:48.585205 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1447 17:17:48.596328 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1448 17:17:48.607498 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1449 17:17:48.618716 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1450 17:17:48.629901 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1451 17:17:48.641118 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1452 17:17:48.657921 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1453 17:17:48.669131 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1454 17:17:48.685861 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1455 17:17:48.697064 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1456 17:17:48.702647 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1457 17:17:48.713784 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1458 17:17:48.719371 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1459 17:17:48.730538 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1460 17:17:48.741806 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1461 17:17:48.747340 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1462 17:17:48.758571 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1463 17:17:48.764211 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1464 17:17:48.775376 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1465 17:17:48.780939 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1466 17:17:48.792172 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1467 17:17:48.797731 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1468 17:17:48.808920 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1469 17:17:48.820185 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1470 17:17:48.831290 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1471 17:17:48.836957 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1472 17:17:48.848140 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1473 17:17:48.859311 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1474 17:17:48.870474 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1475 17:17:48.876091 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1476 17:17:48.881654 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1477 17:17:48.887277 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1478 17:17:48.892869 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1479 17:17:48.898439 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1480 17:17:48.909653 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1481 17:17:48.915282 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1482 17:17:48.920838 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1483 17:17:48.932016 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1484 17:17:48.937665 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1485 17:17:48.948804 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1486 17:17:48.954424 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1487 17:17:48.965661 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1488 17:17:48.971193 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1489 17:17:48.982408 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1490 17:17:48.987974 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1491 17:17:48.999188 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1492 17:17:49.004791 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1493 17:17:49.010353 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1494 17:17:49.021604 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1495 17:17:49.027180 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1496 17:17:49.038331 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1497 17:17:49.043939 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1498 17:17:49.055253 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1499 17:17:49.060771 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1500 17:17:49.071924 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1501 17:17:49.077502 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1502 17:17:49.088695 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1503 17:17:49.094363 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1504 17:17:49.105485 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1505 17:17:49.111072 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1506 17:17:49.122454 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1507 17:17:49.128032 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1508 17:17:49.133578 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1509 17:17:49.144797 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1510 17:17:49.155918 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1511 17:17:49.167043 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1512 17:17:49.178237 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1513 17:17:49.189438 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1514 17:17:49.195031 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1515 17:17:49.206210 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1516 17:17:49.217431 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1517 17:17:49.228612 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1518 17:17:49.239791 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1519 17:17:49.245445 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1520 17:17:49.256718 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1521 17:17:49.262266 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1522 17:17:49.273425 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1523 17:17:49.278980 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1524 17:17:49.290251 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1525 17:17:49.295879 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1526 17:17:49.306931 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1527 17:17:49.312537 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1528 17:17:49.323767 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1529 17:17:49.329370 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1530 17:17:49.340589 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1531 17:17:49.346310 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1532 17:17:49.357501 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1533 17:17:49.363088 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1534 17:17:49.368647 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1535 17:17:49.379861 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1536 17:17:49.385495 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1537 17:17:49.396720 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1538 17:17:49.402352 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1539 17:17:49.413535 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1540 17:17:49.419148 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1541 17:17:49.424781 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1542 17:17:49.430369 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1543 17:17:49.441538 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1544 17:17:49.447190 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1545 17:17:49.458422 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1546 17:17:49.463953 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1547 17:17:49.475140 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1548 17:17:49.486318 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1549 17:17:49.497525 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1550 17:17:49.503191 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1551 17:17:49.514295 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1552 17:17:49.525590 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1553 17:17:49.531206 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1554 17:17:49.536797 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1555 17:17:49.542425 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1556 17:17:49.548000 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1557 17:17:49.553606 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1558 17:17:49.559270 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1559 17:17:49.564792 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1560 17:17:49.570445 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1561 17:17:49.581596 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1562 17:17:49.587175 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1563 17:17:49.592791 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1564 17:17:49.598406 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1565 17:17:49.604042 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1566 17:17:49.609576 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1567 17:17:49.615167 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1568 17:17:49.620805 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1569 17:17:49.626381 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1570 17:17:49.632002 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1571 17:17:49.637573 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1572 17:17:49.643263 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1573 17:17:49.648780 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1574 17:17:49.654371 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1575 17:17:49.660037 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1576 17:17:49.665663 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1577 17:17:49.671309 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1578 17:17:49.676839 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1579 17:17:49.682455 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1580 17:17:49.688056 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1581 17:17:49.693653 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1582 17:17:49.699327 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1583 17:17:49.704850 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1584 17:17:49.710478 dt_test_unprobed_devices_sh_opp-table skip
1585 17:17:49.711015 dt_test_unprobed_devices_sh_soc skip
1586 17:17:49.716086 dt_test_unprobed_devices_sh_sound pass
1587 17:17:49.721644 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1588 17:17:49.727294 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1589 17:17:49.732845 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1590 17:17:49.738446 dt_test_unprobed_devices_sh fail
1591 17:17:49.744067 + ../../utils/send-to-lava.sh ./output/result.txt
1592 17:17:49.749772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1593 17:17:49.750657 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1595 17:17:49.754491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1596 17:17:49.755218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1598 17:17:49.835125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1599 17:17:49.835926 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1601 17:17:49.924817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1602 17:17:49.925627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1604 17:17:50.013499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1605 17:17:50.014263 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1607 17:17:50.104080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1608 17:17:50.104866 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1610 17:17:50.187717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1611 17:17:50.188562 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1613 17:17:50.270468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1614 17:17:50.271100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1616 17:17:50.354839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1617 17:17:50.355456 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1619 17:17:50.447085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1620 17:17:50.447682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1622 17:17:50.539462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1623 17:17:50.540101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1625 17:17:50.628218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1626 17:17:50.628927 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1628 17:17:50.713036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1629 17:17:50.713723 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1631 17:17:50.797476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1632 17:17:50.798097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1634 17:17:50.880320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1635 17:17:50.880920 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1637 17:17:50.966066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1638 17:17:50.966866 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1640 17:17:51.051102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1641 17:17:51.051858 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1643 17:17:51.141149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1644 17:17:51.141906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1646 17:17:51.233223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1647 17:17:51.233961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1649 17:17:51.317627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1650 17:17:51.318380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1652 17:17:51.407963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1653 17:17:51.408742 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1655 17:17:51.492291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1656 17:17:51.493045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1658 17:17:51.582312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1659 17:17:51.583054 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1661 17:17:51.673452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1662 17:17:51.674203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1664 17:17:51.756752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1665 17:17:51.757478 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1667 17:17:51.848274 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1668 17:17:51.849041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1670 17:17:51.931681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1671 17:17:51.932473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1673 17:17:52.022805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1674 17:17:52.023528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1676 17:17:52.114738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1677 17:17:52.115491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1679 17:17:52.203881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1680 17:17:52.204644 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1682 17:17:52.293478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1683 17:17:52.294216 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1685 17:17:52.383426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1686 17:17:52.384168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1688 17:17:52.467380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1689 17:17:52.468129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1691 17:17:52.558603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1692 17:17:52.559381 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1694 17:17:52.642986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1695 17:17:52.643701 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1697 17:17:52.733221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1698 17:17:52.733998 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1700 17:17:52.817851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1701 17:17:52.818616 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1703 17:17:52.907920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1704 17:17:52.908751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1706 17:17:52.993003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1707 17:17:52.993738 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1709 17:17:53.084606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1710 17:17:53.085358 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1712 17:17:53.168843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1713 17:17:53.169577 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1715 17:17:53.258359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1716 17:17:53.259094 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1718 17:17:53.342890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1719 17:17:53.343644 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1721 17:17:53.434210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1722 17:17:53.434940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1724 17:17:53.522823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1725 17:17:53.523574 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1727 17:17:53.607556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1728 17:17:53.608349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1730 17:17:53.692600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1731 17:17:53.693429 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1733 17:17:53.783139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1734 17:17:53.783949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1736 17:17:53.874160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1737 17:17:53.874970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1739 17:17:53.963132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1740 17:17:53.963925 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1742 17:17:54.047111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1743 17:17:54.047923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1745 17:17:54.134244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1746 17:17:54.135062 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1748 17:17:54.224456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1749 17:17:54.225247 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1751 17:17:54.313571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1752 17:17:54.314369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1754 17:17:54.397678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1755 17:17:54.398471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1757 17:17:54.484075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1758 17:17:54.484846 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1760 17:17:54.572531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1761 17:17:54.573318 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1763 17:17:54.660474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1764 17:17:54.661285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1766 17:17:54.749617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1767 17:17:54.750416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1769 17:17:54.839234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1770 17:17:54.840061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1772 17:17:54.934167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1773 17:17:54.934956 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1775 17:17:55.023928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1776 17:17:55.024756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1778 17:17:55.115315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1779 17:17:55.116137 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1781 17:17:55.205730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1782 17:17:55.206524 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1784 17:17:55.292751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1785 17:17:55.293600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1787 17:17:55.381652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1788 17:17:55.382541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1790 17:17:55.472902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1791 17:17:55.473745 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1793 17:17:55.564503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1794 17:17:55.565409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1796 17:17:55.649718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1797 17:17:55.650835 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1799 17:17:55.740148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1800 17:17:55.741244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1802 17:17:55.826747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1803 17:17:55.827822 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1805 17:17:55.916402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1806 17:17:55.917364 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1808 17:17:56.006904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1809 17:17:56.007843 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1811 17:17:56.092204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1812 17:17:56.093115 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1814 17:17:56.181865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1815 17:17:56.182712 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1817 17:17:56.272047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1818 17:17:56.272942 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1820 17:17:56.361970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1821 17:17:56.362877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1823 17:17:56.453482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1824 17:17:56.454334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1826 17:17:56.543144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1827 17:17:56.544015 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1829 17:17:56.633745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1830 17:17:56.634355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1832 17:17:56.722027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1833 17:17:56.722696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1835 17:17:56.807132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1836 17:17:56.807857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1838 17:17:56.899050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1839 17:17:56.899769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1841 17:17:56.989290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1842 17:17:56.990043 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1844 17:17:57.079280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1845 17:17:57.079959 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1847 17:17:57.169270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1848 17:17:57.169955 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1850 17:17:57.259631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1851 17:17:57.260350 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1853 17:17:57.343955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1854 17:17:57.344680 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1856 17:17:57.433268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1857 17:17:57.433961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1859 17:17:57.519392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1860 17:17:57.520219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1862 17:17:57.610233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1863 17:17:57.610935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1865 17:17:57.692705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1866 17:17:57.693330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1868 17:17:57.783964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1869 17:17:57.784737 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1871 17:17:57.873645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1872 17:17:57.874338 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1874 17:17:57.963714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1875 17:17:57.964457 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1877 17:17:58.051406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1878 17:17:58.052058 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1880 17:17:58.140862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1881 17:17:58.141507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1883 17:17:58.230879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1884 17:17:58.231556 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1886 17:17:58.315877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1887 17:17:58.316730 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1889 17:17:58.401816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1890 17:17:58.402579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1892 17:17:58.493557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1893 17:17:58.494233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1895 17:17:58.601281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1896 17:17:58.601969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1898 17:17:58.704040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1899 17:17:58.704716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1901 17:17:58.802284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1902 17:17:58.802991 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1904 17:17:58.897000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1905 17:17:58.898187 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1907 17:17:58.998410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1908 17:17:58.999399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1910 17:17:59.092878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1911 17:17:59.093588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1913 17:17:59.184094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1914 17:17:59.184789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1916 17:17:59.278621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1917 17:17:59.279280 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1919 17:17:59.364525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1920 17:17:59.365431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1922 17:17:59.453201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1923 17:17:59.454108 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1925 17:17:59.543287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1926 17:17:59.544184 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1928 17:17:59.633952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1929 17:17:59.634817 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1931 17:17:59.722214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1932 17:17:59.723159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1934 17:17:59.812835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1935 17:17:59.813694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1937 17:17:59.903176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1938 17:17:59.904077 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1940 17:17:59.993060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1941 17:17:59.993658 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1943 17:18:00.083899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1944 17:18:00.084513 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1946 17:18:00.174007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1947 17:18:00.174888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1949 17:18:00.262906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1950 17:18:00.263819 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1952 17:18:00.347579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1954 17:18:00.349745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1955 17:18:00.433002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1957 17:18:00.435276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1958 17:18:00.523152 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1960 17:18:00.525342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1961 17:18:00.612374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1962 17:18:00.613214 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1964 17:18:00.703234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1965 17:18:00.704087 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1967 17:18:00.790703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1968 17:18:00.791546 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1970 17:18:00.881048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1971 17:18:00.881899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1973 17:18:00.964652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1974 17:18:00.965496 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1976 17:18:01.050104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1977 17:18:01.050964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1979 17:18:01.140270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1980 17:18:01.141118 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1982 17:18:01.230833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1983 17:18:01.231789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1985 17:18:01.322448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1986 17:18:01.323313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1988 17:18:01.413576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1989 17:18:01.414466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1991 17:18:01.496536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1992 17:18:01.497397 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1994 17:18:01.589748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1995 17:18:01.590686 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1997 17:18:01.679554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1998 17:18:01.680514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2000 17:18:01.770367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2001 17:18:01.771355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2003 17:18:01.866687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2004 17:18:01.867641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2006 17:18:01.966092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2007 17:18:01.966716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2009 17:18:02.058268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2010 17:18:02.059124 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2012 17:18:02.149801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2013 17:18:02.150748 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2015 17:18:02.244153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2016 17:18:02.245108 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2018 17:18:02.331022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2019 17:18:02.332034 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2021 17:18:02.435434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2022 17:18:02.436398 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2024 17:18:02.533397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2025 17:18:02.534348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2027 17:18:02.625299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2028 17:18:02.626203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2030 17:18:02.719328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2031 17:18:02.720207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2033 17:18:02.811142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2034 17:18:02.812821 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2036 17:18:02.912527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2037 17:18:02.913398 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2039 17:18:03.018102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2040 17:18:03.018957 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2042 17:18:03.121062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2043 17:18:03.121940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2045 17:18:03.210505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2046 17:18:03.211336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2048 17:18:03.294654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2049 17:18:03.295412 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2051 17:18:03.386406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2052 17:18:03.387203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2054 17:18:03.470178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2055 17:18:03.470946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2057 17:18:03.554887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2058 17:18:03.555720 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2060 17:18:03.640371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2061 17:18:03.641124 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2063 17:18:03.730364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2064 17:18:03.731142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2066 17:18:03.815881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2067 17:18:03.816719 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2069 17:18:03.906296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2070 17:18:03.907089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2072 17:18:03.991195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2073 17:18:03.991951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2075 17:18:04.079762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2076 17:18:04.080564 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2078 17:18:04.165333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2079 17:18:04.166090 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2081 17:18:04.254263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2082 17:18:04.255085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2084 17:18:04.339704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2085 17:18:04.340546 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2087 17:18:04.423529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2088 17:18:04.424376 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2090 17:18:04.508845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2091 17:18:04.509651 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2093 17:18:04.593150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2094 17:18:04.593755 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2096 17:18:04.679273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2097 17:18:04.680092 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2099 17:18:04.762577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2100 17:18:04.763436 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2102 17:18:04.848596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2103 17:18:04.849509 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2105 17:18:04.938653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2106 17:18:04.939637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2108 17:18:05.029448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2109 17:18:05.030450 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2111 17:18:05.118876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2112 17:18:05.119909 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2114 17:18:05.211309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2115 17:18:05.212330 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2117 17:18:05.297302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2118 17:18:05.298321 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2120 17:18:05.382920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2121 17:18:05.383964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2123 17:18:05.467202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2124 17:18:05.468178 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2126 17:18:05.553045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2127 17:18:05.554134 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2129 17:18:05.638832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2130 17:18:05.639824 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2132 17:18:05.722139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2133 17:18:05.723156 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2135 17:18:05.814170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2136 17:18:05.815195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2138 17:18:06.147419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2139 17:18:06.147865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2140 17:18:06.148417 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2142 17:18:06.149213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2144 17:18:06.150362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2145 17:18:06.150833 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2147 17:18:06.173873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2148 17:18:06.174746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2150 17:18:06.255057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2151 17:18:06.255900 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2153 17:18:06.341499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2154 17:18:06.342357 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2156 17:18:06.439666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2157 17:18:06.440584 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2159 17:18:06.529495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2160 17:18:06.530376 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2162 17:18:06.619127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2163 17:18:06.619975 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2165 17:18:06.708251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2166 17:18:06.709101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2168 17:18:06.797779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2169 17:18:06.798768 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2171 17:18:06.883008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2172 17:18:06.883880 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2174 17:18:06.972089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2175 17:18:06.972921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2177 17:18:07.056944 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2178 17:18:07.057778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2180 17:18:07.147234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2181 17:18:07.148098 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2183 17:18:07.237320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2184 17:18:07.238268 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2186 17:18:07.319834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2187 17:18:07.320919 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2189 17:18:07.410750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2190 17:18:07.411818 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2192 17:18:07.496658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2193 17:18:07.497711 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2195 17:18:07.586599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2196 17:18:07.587674 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2198 17:18:07.681071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2199 17:18:07.682106 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2201 17:18:07.765777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2202 17:18:07.766738 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2204 17:18:07.856051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2205 17:18:07.857108 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2207 17:18:07.941047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2208 17:18:07.942109 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2210 17:18:08.032282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2211 17:18:08.033349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2213 17:18:08.116167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2214 17:18:08.117189 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2216 17:18:08.206174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2217 17:18:08.207212 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2219 17:18:08.287195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2220 17:18:08.288405 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2222 17:18:08.372411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2223 17:18:08.373468 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2225 17:18:08.458433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2226 17:18:08.459451 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2228 17:18:08.542307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2229 17:18:08.543385 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2231 17:18:08.627709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2232 17:18:08.628770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2234 17:18:08.715524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2235 17:18:08.716682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2237 17:18:08.807068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2238 17:18:08.808152 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2240 17:18:08.898370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2241 17:18:08.899429 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2243 17:18:08.990030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2244 17:18:08.990659 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2246 17:18:09.081787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2247 17:18:09.082447 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2249 17:18:09.170995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2250 17:18:09.171649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2252 17:18:09.261398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2253 17:18:09.262028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2255 17:18:09.348809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2256 17:18:09.349446 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2258 17:18:09.434032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2259 17:18:09.434680 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2261 17:18:09.518588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2262 17:18:09.519267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2264 17:18:09.771644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2265 17:18:09.772290 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2267 17:18:09.878388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2268 17:18:09.879024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2270 17:18:09.967352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2271 17:18:09.968190 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2273 17:18:10.049740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2275 17:18:10.052736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2276 17:18:10.134377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2277 17:18:10.135276 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2279 17:18:10.226834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2280 17:18:10.227780 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2282 17:18:10.317693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2283 17:18:10.318610 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2285 17:18:10.407240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2286 17:18:10.407875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2288 17:18:10.498354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2289 17:18:10.498977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2291 17:18:10.588498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2292 17:18:10.589402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2294 17:18:10.672708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2295 17:18:10.673589 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2297 17:18:10.763419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2298 17:18:10.764360 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2300 17:18:10.853717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2301 17:18:10.854609 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2303 17:18:10.943717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2304 17:18:10.944663 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2306 17:18:11.029374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2307 17:18:11.030293 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2309 17:18:11.113743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2310 17:18:11.114666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2312 17:18:11.197989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2313 17:18:11.198896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2315 17:18:11.287300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2316 17:18:11.288170 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2318 17:18:11.378297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2319 17:18:11.379201 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2321 17:18:11.462825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2322 17:18:11.463734 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2324 17:18:11.553252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2325 17:18:11.554140 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2327 17:18:11.636646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2328 17:18:11.637542 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2330 17:18:11.727016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2331 17:18:11.727910 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2333 17:18:11.818835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2334 17:18:11.819714 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2336 17:18:11.906721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2337 17:18:11.907587 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2339 17:18:11.992766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2340 17:18:11.993611 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2342 17:18:12.083486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2343 17:18:12.084558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2345 17:18:12.176593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2346 17:18:12.177495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2348 17:18:12.263829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2349 17:18:12.264732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2351 17:18:12.351545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2352 17:18:12.352477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2354 17:18:12.441441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2355 17:18:12.442324 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2357 17:18:12.532741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2358 17:18:12.533599 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2360 17:18:12.624846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2361 17:18:12.625731 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2363 17:18:12.717656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2364 17:18:12.718526 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2366 17:18:12.805185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2367 17:18:12.805727 + set +x
2368 17:18:12.806427 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2370 17:18:12.813788 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 948111_1.6.2.4.5>
2371 17:18:12.814307 <LAVA_TEST_RUNNER EXIT>
2372 17:18:12.815001 Received signal: <ENDRUN> 1_kselftest-dt 948111_1.6.2.4.5
2373 17:18:12.815477 Ending use of test pattern.
2374 17:18:12.815908 Ending test lava.1_kselftest-dt (948111_1.6.2.4.5), duration 83.16
2376 17:18:12.817739 ok: lava_test_shell seems to have completed
2377 17:18:12.831733 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2378 17:18:12.833813 end: 3.1 lava-test-shell (duration 00:01:25) [common]
2379 17:18:12.834403 end: 3 lava-test-retry (duration 00:01:25) [common]
2380 17:18:12.834990 start: 4 finalize (timeout 00:05:32) [common]
2381 17:18:12.835568 start: 4.1 power-off (timeout 00:00:30) [common]
2382 17:18:12.836599 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-01'
2383 17:18:12.871365 >> OK - accepted request
2384 17:18:12.873679 Returned 0 in 0 seconds
2385 17:18:12.975171 end: 4.1 power-off (duration 00:00:00) [common]
2387 17:18:12.977288 start: 4.2 read-feedback (timeout 00:05:32) [common]
2388 17:18:12.978914 Listened to connection for namespace 'common' for up to 1s
2389 17:18:12.980061 Listened to connection for namespace 'common' for up to 1s
2390 17:18:13.979385 Finalising connection for namespace 'common'
2391 17:18:13.980238 Disconnecting from shell: Finalise
2392 17:18:13.980839 / #
2393 17:18:14.081971 end: 4.2 read-feedback (duration 00:00:01) [common]
2394 17:18:14.082799 end: 4 finalize (duration 00:00:01) [common]
2395 17:18:14.083552 Cleaning after the job
2396 17:18:14.084349 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948111/tftp-deploy-9d1q109r/ramdisk
2397 17:18:14.087197 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948111/tftp-deploy-9d1q109r/kernel
2398 17:18:14.089304 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948111/tftp-deploy-9d1q109r/dtb
2399 17:18:14.090687 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948111/tftp-deploy-9d1q109r/nfsrootfs
2400 17:18:14.129134 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/948111/tftp-deploy-9d1q109r/modules
2401 17:18:14.136920 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/948111
2402 17:18:17.151046 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/948111
2403 17:18:17.151713 Job finished correctly