Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 13:54:40.621811 lava-dispatcher, installed at version: 2024.01
2 13:54:40.622599 start: 0 validate
3 13:54:40.623087 Start time: 2024-11-04 13:54:40.623058+00:00 (UTC)
4 13:54:40.623639 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 13:54:40.624207 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 13:54:40.660579 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 13:54:40.661108 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-84-ge231ee35020e%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 13:54:40.694252 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 13:54:40.694880 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-84-ge231ee35020e%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 13:54:40.734336 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 13:54:40.734834 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 13:54:40.768423 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 13:54:40.768905 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-84-ge231ee35020e%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 13:54:40.807937 validate duration: 0.19
16 13:54:40.809107 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:54:40.809574 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:54:40.809986 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:54:40.810921 Not decompressing ramdisk as can be used compressed.
20 13:54:40.811481 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 13:54:40.811837 saving as /var/lib/lava/dispatcher/tmp/934132/tftp-deploy-abofgn5v/ramdisk/initrd.cpio.gz
22 13:54:40.812233 total size: 4775763 (4 MB)
23 13:54:40.851476 progress 0 % (0 MB)
24 13:54:40.855372 progress 5 % (0 MB)
25 13:54:40.858823 progress 10 % (0 MB)
26 13:54:40.862300 progress 15 % (0 MB)
27 13:54:40.866203 progress 20 % (0 MB)
28 13:54:40.869478 progress 25 % (1 MB)
29 13:54:40.872949 progress 30 % (1 MB)
30 13:54:40.876937 progress 35 % (1 MB)
31 13:54:40.880248 progress 40 % (1 MB)
32 13:54:40.883445 progress 45 % (2 MB)
33 13:54:40.886686 progress 50 % (2 MB)
34 13:54:40.890319 progress 55 % (2 MB)
35 13:54:40.893536 progress 60 % (2 MB)
36 13:54:40.896838 progress 65 % (2 MB)
37 13:54:40.900512 progress 70 % (3 MB)
38 13:54:40.903755 progress 75 % (3 MB)
39 13:54:40.906992 progress 80 % (3 MB)
40 13:54:40.910303 progress 85 % (3 MB)
41 13:54:40.913969 progress 90 % (4 MB)
42 13:54:40.917035 progress 95 % (4 MB)
43 13:54:40.919927 progress 100 % (4 MB)
44 13:54:40.920601 4 MB downloaded in 0.11 s (42.03 MB/s)
45 13:54:40.921165 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:54:40.922069 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:54:40.922365 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:54:40.922637 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:54:40.923104 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-84-ge231ee35020e/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 13:54:40.923358 saving as /var/lib/lava/dispatcher/tmp/934132/tftp-deploy-abofgn5v/kernel/zImage
52 13:54:40.923566 total size: 11444736 (10 MB)
53 13:54:40.923778 No compression specified
54 13:54:40.964887 progress 0 % (0 MB)
55 13:54:40.972191 progress 5 % (0 MB)
56 13:54:40.979376 progress 10 % (1 MB)
57 13:54:40.986925 progress 15 % (1 MB)
58 13:54:40.993844 progress 20 % (2 MB)
59 13:54:41.001381 progress 25 % (2 MB)
60 13:54:41.008451 progress 30 % (3 MB)
61 13:54:41.015822 progress 35 % (3 MB)
62 13:54:41.022851 progress 40 % (4 MB)
63 13:54:41.030226 progress 45 % (4 MB)
64 13:54:41.037135 progress 50 % (5 MB)
65 13:54:41.044466 progress 55 % (6 MB)
66 13:54:41.051525 progress 60 % (6 MB)
67 13:54:41.058925 progress 65 % (7 MB)
68 13:54:41.065857 progress 70 % (7 MB)
69 13:54:41.072882 progress 75 % (8 MB)
70 13:54:41.080507 progress 80 % (8 MB)
71 13:54:41.087472 progress 85 % (9 MB)
72 13:54:41.094819 progress 90 % (9 MB)
73 13:54:41.101908 progress 95 % (10 MB)
74 13:54:41.109209 progress 100 % (10 MB)
75 13:54:41.109744 10 MB downloaded in 0.19 s (58.63 MB/s)
76 13:54:41.110220 end: 1.2.1 http-download (duration 00:00:00) [common]
78 13:54:41.111052 end: 1.2 download-retry (duration 00:00:00) [common]
79 13:54:41.111332 start: 1.3 download-retry (timeout 00:10:00) [common]
80 13:54:41.111597 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 13:54:41.112085 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-84-ge231ee35020e/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 13:54:41.112372 saving as /var/lib/lava/dispatcher/tmp/934132/tftp-deploy-abofgn5v/dtb/am335x-boneblack.dtb
83 13:54:41.112582 total size: 70568 (0 MB)
84 13:54:41.112791 No compression specified
85 13:54:41.151893 progress 46 % (0 MB)
86 13:54:41.152727 progress 92 % (0 MB)
87 13:54:41.153430 progress 100 % (0 MB)
88 13:54:41.153824 0 MB downloaded in 0.04 s (1.63 MB/s)
89 13:54:41.154276 end: 1.3.1 http-download (duration 00:00:00) [common]
91 13:54:41.155089 end: 1.3 download-retry (duration 00:00:00) [common]
92 13:54:41.155353 start: 1.4 download-retry (timeout 00:10:00) [common]
93 13:54:41.155615 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 13:54:41.156068 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 13:54:41.156322 saving as /var/lib/lava/dispatcher/tmp/934132/tftp-deploy-abofgn5v/nfsrootfs/full.rootfs.tar
96 13:54:41.156526 total size: 117747780 (112 MB)
97 13:54:41.156736 Using unxz to decompress xz
98 13:54:41.198011 progress 0 % (0 MB)
99 13:54:41.918029 progress 5 % (5 MB)
100 13:54:42.653704 progress 10 % (11 MB)
101 13:54:43.417809 progress 15 % (16 MB)
102 13:54:44.123772 progress 20 % (22 MB)
103 13:54:44.698188 progress 25 % (28 MB)
104 13:54:45.491904 progress 30 % (33 MB)
105 13:54:46.286571 progress 35 % (39 MB)
106 13:54:46.639467 progress 40 % (44 MB)
107 13:54:46.999303 progress 45 % (50 MB)
108 13:54:47.649308 progress 50 % (56 MB)
109 13:54:48.446970 progress 55 % (61 MB)
110 13:54:49.164634 progress 60 % (67 MB)
111 13:54:49.870840 progress 65 % (73 MB)
112 13:54:50.619949 progress 70 % (78 MB)
113 13:54:51.368226 progress 75 % (84 MB)
114 13:54:52.093589 progress 80 % (89 MB)
115 13:54:52.796076 progress 85 % (95 MB)
116 13:54:53.569780 progress 90 % (101 MB)
117 13:54:54.316201 progress 95 % (106 MB)
118 13:54:55.114381 progress 100 % (112 MB)
119 13:54:55.126563 112 MB downloaded in 13.97 s (8.04 MB/s)
120 13:54:55.127485 end: 1.4.1 http-download (duration 00:00:14) [common]
122 13:54:55.129301 end: 1.4 download-retry (duration 00:00:14) [common]
123 13:54:55.129870 start: 1.5 download-retry (timeout 00:09:46) [common]
124 13:54:55.130432 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 13:54:55.131391 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-84-ge231ee35020e/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 13:54:55.131901 saving as /var/lib/lava/dispatcher/tmp/934132/tftp-deploy-abofgn5v/modules/modules.tar
127 13:54:55.132394 total size: 6610168 (6 MB)
128 13:54:55.132853 Using unxz to decompress xz
129 13:54:55.181759 progress 0 % (0 MB)
130 13:54:55.216565 progress 5 % (0 MB)
131 13:54:55.259194 progress 10 % (0 MB)
132 13:54:55.301636 progress 15 % (0 MB)
133 13:54:55.344860 progress 20 % (1 MB)
134 13:54:55.390248 progress 25 % (1 MB)
135 13:54:55.432029 progress 30 % (1 MB)
136 13:54:55.473445 progress 35 % (2 MB)
137 13:54:55.515778 progress 40 % (2 MB)
138 13:54:55.557990 progress 45 % (2 MB)
139 13:54:55.600358 progress 50 % (3 MB)
140 13:54:55.641996 progress 55 % (3 MB)
141 13:54:55.690693 progress 60 % (3 MB)
142 13:54:55.732093 progress 65 % (4 MB)
143 13:54:55.774544 progress 70 % (4 MB)
144 13:54:55.819845 progress 75 % (4 MB)
145 13:54:55.861652 progress 80 % (5 MB)
146 13:54:55.903370 progress 85 % (5 MB)
147 13:54:55.945365 progress 90 % (5 MB)
148 13:54:55.987867 progress 95 % (6 MB)
149 13:54:56.030835 progress 100 % (6 MB)
150 13:54:56.043890 6 MB downloaded in 0.91 s (6.92 MB/s)
151 13:54:56.044908 end: 1.5.1 http-download (duration 00:00:01) [common]
153 13:54:56.046715 end: 1.5 download-retry (duration 00:00:01) [common]
154 13:54:56.047289 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 13:54:56.047859 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 13:55:11.926895 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/934132/extract-nfsrootfs-2jrv9trt
157 13:55:11.927514 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 13:55:11.927802 start: 1.6.2 lava-overlay (timeout 00:09:29) [common]
159 13:55:11.928472 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq
160 13:55:11.929010 makedir: /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin
161 13:55:11.929357 makedir: /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/tests
162 13:55:11.929672 makedir: /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/results
163 13:55:11.930003 Creating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-add-keys
164 13:55:11.930528 Creating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-add-sources
165 13:55:11.931034 Creating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-background-process-start
166 13:55:11.931531 Creating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-background-process-stop
167 13:55:11.932093 Creating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-common-functions
168 13:55:11.932619 Creating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-echo-ipv4
169 13:55:11.933124 Creating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-install-packages
170 13:55:11.933748 Creating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-installed-packages
171 13:55:11.934252 Creating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-os-build
172 13:55:11.934735 Creating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-probe-channel
173 13:55:11.935235 Creating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-probe-ip
174 13:55:11.935746 Creating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-target-ip
175 13:55:11.936268 Creating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-target-mac
176 13:55:11.936767 Creating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-target-storage
177 13:55:11.937260 Creating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-test-case
178 13:55:11.937741 Creating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-test-event
179 13:55:11.938214 Creating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-test-feedback
180 13:55:11.938718 Creating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-test-raise
181 13:55:11.939223 Creating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-test-reference
182 13:55:11.939702 Creating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-test-runner
183 13:55:11.940212 Creating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-test-set
184 13:55:11.940698 Creating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-test-shell
185 13:55:11.941188 Updating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-add-keys (debian)
186 13:55:11.941729 Updating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-add-sources (debian)
187 13:55:11.942234 Updating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-install-packages (debian)
188 13:55:11.942733 Updating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-installed-packages (debian)
189 13:55:11.943222 Updating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/bin/lava-os-build (debian)
190 13:55:11.943653 Creating /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/environment
191 13:55:11.944082 LAVA metadata
192 13:55:11.944357 - LAVA_JOB_ID=934132
193 13:55:11.944576 - LAVA_DISPATCHER_IP=192.168.6.2
194 13:55:11.944932 start: 1.6.2.1 ssh-authorize (timeout 00:09:29) [common]
195 13:55:11.945911 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 13:55:11.946228 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:29) [common]
197 13:55:11.946436 skipped lava-vland-overlay
198 13:55:11.946677 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 13:55:11.946930 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:29) [common]
200 13:55:11.947148 skipped lava-multinode-overlay
201 13:55:11.947392 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 13:55:11.947641 start: 1.6.2.4 test-definition (timeout 00:09:29) [common]
203 13:55:11.947886 Loading test definitions
204 13:55:11.948217 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:29) [common]
205 13:55:11.948442 Using /lava-934132 at stage 0
206 13:55:11.949528 uuid=934132_1.6.2.4.1 testdef=None
207 13:55:11.949830 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 13:55:11.950094 start: 1.6.2.4.2 test-overlay (timeout 00:09:29) [common]
209 13:55:11.951633 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 13:55:11.952457 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:29) [common]
212 13:55:11.954386 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 13:55:11.955210 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:29) [common]
215 13:55:11.957090 runner path: /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/0/tests/0_timesync-off test_uuid 934132_1.6.2.4.1
216 13:55:11.957635 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 13:55:11.958452 start: 1.6.2.4.5 git-repo-action (timeout 00:09:29) [common]
219 13:55:11.958675 Using /lava-934132 at stage 0
220 13:55:11.959027 Fetching tests from https://github.com/kernelci/test-definitions.git
221 13:55:11.959317 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/0/tests/1_kselftest-dt'
222 13:55:15.254958 Running '/usr/bin/git checkout kernelci.org
223 13:55:15.503156 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 13:55:15.504673 uuid=934132_1.6.2.4.5 testdef=None
225 13:55:15.505041 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 13:55:15.505802 start: 1.6.2.4.6 test-overlay (timeout 00:09:25) [common]
228 13:55:15.508722 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 13:55:15.509559 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:25) [common]
231 13:55:15.513388 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 13:55:15.514277 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:25) [common]
234 13:55:15.519423 runner path: /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/0/tests/1_kselftest-dt test_uuid 934132_1.6.2.4.5
235 13:55:15.519954 BOARD='beaglebone-black'
236 13:55:15.520401 BRANCH='pm'
237 13:55:15.520793 SKIPFILE='/dev/null'
238 13:55:15.521184 SKIP_INSTALL='True'
239 13:55:15.521571 TESTPROG_URL='http://storage.kernelci.org/pm/testing/v6.12-rc6-84-ge231ee35020e/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 13:55:15.521973 TST_CASENAME=''
241 13:55:15.522364 TST_CMDFILES='dt'
242 13:55:15.523361 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 13:55:15.524949 Creating lava-test-runner.conf files
245 13:55:15.525359 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/934132/lava-overlay-xf1bhbcq/lava-934132/0 for stage 0
246 13:55:15.526002 - 0_timesync-off
247 13:55:15.526464 - 1_kselftest-dt
248 13:55:15.527100 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 13:55:15.527634 start: 1.6.2.5 compress-overlay (timeout 00:09:25) [common]
250 13:55:38.826280 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 13:55:38.826713 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:02) [common]
252 13:55:38.826981 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 13:55:38.827254 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 13:55:38.827520 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:02) [common]
255 13:55:39.197566 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 13:55:39.198022 start: 1.6.4 extract-modules (timeout 00:09:02) [common]
257 13:55:39.198291 extracting modules file /var/lib/lava/dispatcher/tmp/934132/tftp-deploy-abofgn5v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/934132/extract-nfsrootfs-2jrv9trt
258 13:55:40.065634 extracting modules file /var/lib/lava/dispatcher/tmp/934132/tftp-deploy-abofgn5v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/934132/extract-overlay-ramdisk-njnb8jw_/ramdisk
259 13:55:40.960323 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 13:55:40.960781 start: 1.6.5 apply-overlay-tftp (timeout 00:09:00) [common]
261 13:55:40.961068 [common] Applying overlay to NFS
262 13:55:40.961287 [common] Applying overlay /var/lib/lava/dispatcher/tmp/934132/compress-overlay-i97mba_x/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/934132/extract-nfsrootfs-2jrv9trt
263 13:55:43.693688 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 13:55:43.694125 start: 1.6.6 prepare-kernel (timeout 00:08:57) [common]
265 13:55:43.694402 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:57) [common]
266 13:55:43.694677 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 13:55:43.694931 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 13:55:43.695189 start: 1.6.7 configure-preseed-file (timeout 00:08:57) [common]
269 13:55:43.695439 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 13:55:43.695694 start: 1.6.8 compress-ramdisk (timeout 00:08:57) [common]
271 13:55:43.695943 Building ramdisk /var/lib/lava/dispatcher/tmp/934132/extract-overlay-ramdisk-njnb8jw_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/934132/extract-overlay-ramdisk-njnb8jw_/ramdisk
272 13:55:44.696929 >> 74900 blocks
273 13:55:49.246808 Adding RAMdisk u-boot header.
274 13:55:49.247304 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/934132/extract-overlay-ramdisk-njnb8jw_/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/934132/extract-overlay-ramdisk-njnb8jw_/ramdisk.cpio.gz.uboot
275 13:55:49.403307 output: Image Name:
276 13:55:49.403730 output: Created: Mon Nov 4 13:55:49 2024
277 13:55:49.403943 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 13:55:49.404341 output: Data Size: 14789978 Bytes = 14443.34 KiB = 14.10 MiB
279 13:55:49.404752 output: Load Address: 00000000
280 13:55:49.405150 output: Entry Point: 00000000
281 13:55:49.405545 output:
282 13:55:49.406620 rename /var/lib/lava/dispatcher/tmp/934132/extract-overlay-ramdisk-njnb8jw_/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/934132/tftp-deploy-abofgn5v/ramdisk/ramdisk.cpio.gz.uboot
283 13:55:49.407348 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 13:55:49.407893 end: 1.6 prepare-tftp-overlay (duration 00:00:53) [common]
285 13:55:49.408509 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:51) [common]
286 13:55:49.408962 No LXC device requested
287 13:55:49.409457 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 13:55:49.409962 start: 1.8 deploy-device-env (timeout 00:08:51) [common]
289 13:55:49.410450 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 13:55:49.410863 Checking files for TFTP limit of 4294967296 bytes.
291 13:55:49.413556 end: 1 tftp-deploy (duration 00:01:09) [common]
292 13:55:49.414143 start: 2 uboot-action (timeout 00:05:00) [common]
293 13:55:49.414674 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 13:55:49.415172 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 13:55:49.415670 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 13:55:49.416452 substitutions:
297 13:55:49.416878 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 13:55:49.417284 - {DTB_ADDR}: 0x88000000
299 13:55:49.417682 - {DTB}: 934132/tftp-deploy-abofgn5v/dtb/am335x-boneblack.dtb
300 13:55:49.418080 - {INITRD}: 934132/tftp-deploy-abofgn5v/ramdisk/ramdisk.cpio.gz.uboot
301 13:55:49.418474 - {KERNEL_ADDR}: 0x82000000
302 13:55:49.418866 - {KERNEL}: 934132/tftp-deploy-abofgn5v/kernel/zImage
303 13:55:49.419257 - {LAVA_MAC}: None
304 13:55:49.419687 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/934132/extract-nfsrootfs-2jrv9trt
305 13:55:49.420118 - {NFS_SERVER_IP}: 192.168.6.2
306 13:55:49.420516 - {PRESEED_CONFIG}: None
307 13:55:49.420907 - {PRESEED_LOCAL}: None
308 13:55:49.421299 - {RAMDISK_ADDR}: 0x83000000
309 13:55:49.421687 - {RAMDISK}: 934132/tftp-deploy-abofgn5v/ramdisk/ramdisk.cpio.gz.uboot
310 13:55:49.422080 - {ROOT_PART}: None
311 13:55:49.422465 - {ROOT}: None
312 13:55:49.422855 - {SERVER_IP}: 192.168.6.2
313 13:55:49.423241 - {TEE_ADDR}: 0x83000000
314 13:55:49.423627 - {TEE}: None
315 13:55:49.424037 Parsed boot commands:
316 13:55:49.424416 - setenv autoload no
317 13:55:49.424805 - setenv initrd_high 0xffffffff
318 13:55:49.425188 - setenv fdt_high 0xffffffff
319 13:55:49.425570 - dhcp
320 13:55:49.425948 - setenv serverip 192.168.6.2
321 13:55:49.426334 - tftp 0x82000000 934132/tftp-deploy-abofgn5v/kernel/zImage
322 13:55:49.426719 - tftp 0x83000000 934132/tftp-deploy-abofgn5v/ramdisk/ramdisk.cpio.gz.uboot
323 13:55:49.427104 - setenv initrd_size ${filesize}
324 13:55:49.427484 - tftp 0x88000000 934132/tftp-deploy-abofgn5v/dtb/am335x-boneblack.dtb
325 13:55:49.427867 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/934132/extract-nfsrootfs-2jrv9trt,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 13:55:49.428292 - bootz 0x82000000 0x83000000 0x88000000
327 13:55:49.428789 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 13:55:49.430268 start: 2.3 connect-device (timeout 00:05:00) [common]
330 13:55:49.430684 [common] connect-device Connecting to device using 'telnet conserv1 3003'
331 13:55:49.445591 Setting prompt string to ['lava-test: # ']
332 13:55:49.447097 end: 2.3 connect-device (duration 00:00:00) [common]
333 13:55:49.447713 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 13:55:49.448325 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 13:55:49.448887 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 13:55:49.450303 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-01'
337 13:55:49.493038 >> OK - accepted request
338 13:55:49.495184 Returned 0 in 0 seconds
339 13:55:49.596394 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 13:55:49.598074 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 13:55:49.598634 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 13:55:49.599154 Setting prompt string to ['Hit any key to stop autoboot']
344 13:55:49.599615 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 13:55:49.601195 Trying 192.168.56.21...
346 13:55:49.601677 Connected to conserv1.
347 13:55:49.602099 Escape character is '^]'.
348 13:55:49.602515
349 13:55:49.602924 ser2net port telnet,3003 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 13:55:49.603343
351 13:55:57.139793
352 13:55:57.140473 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
353 13:55:57.144871 Trying to boot from MMC1
354 13:55:57.717264
355 13:55:57.717821
356 13:55:57.718236 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
357 13:55:57.718641
358 13:55:57.722726 CPU : AM335X-GP rev 2.1
359 13:55:57.723194 Model: TI AM335x BeagleBone Black
360 13:55:57.726936 DRAM: 512 MiB
361 13:55:57.809562 Core: 160 devices, 18 uclasses, devicetree: separate
362 13:55:57.819214 WDT: Started wdt@44e35000 with servicing (60s timeout)
363 13:56:01.189300 7[r[999;999H[6n8NAND:
364 13:56:01.189982 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
365 13:56:01.194445 Trying to boot from MMC1
366 13:56:01.766529
367 13:56:01.767144
368 13:56:01.767583 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
369 13:56:01.768048
370 13:56:01.772107 CPU : AM335X-GP rev 2.1
371 13:56:01.772573 Model: TI AM335x BeagleBone Black
372 13:56:01.776122 DRAM: 512 MiB
373 13:56:01.858863 Core: 160 devices, 18 uclasses, devicetree: separate
374 13:56:01.868514 WDT: Started wdt@44e35000 with servicing (60s timeout)
375 13:56:03.889596 7[r[999;999H[6n8NAND:
376 13:56:03.890174 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
377 13:56:03.894786 Trying to boot from MMC1
378 13:56:04.467135
379 13:56:04.467622
380 13:56:04.468105 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
381 13:56:04.468532
382 13:56:04.472662 CPU : AM335X-GP rev 2.1
383 13:56:04.473125 Model: TI AM335x BeagleBone Black
384 13:56:04.476849 DRAM: 512 MiB
385 13:56:04.559541 Core: 160 devices, 18 uclasses, devicetree: separate
386 13:56:04.569194 WDT: Started wdt@44e35000 with servicing (60s timeout)
387 13:56:05.074207 7[r[999;999H[6n8NAND: 0 MiB
388 13:56:05.084565 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
389 13:56:05.157357 Loading Environment from FAT... Unable to use mmc 0:1...
390 13:56:05.178701 <ethaddr> not set. Validating first E-fuse MAC
391 13:56:05.208991 Net: eth2: ethernet@4a100000, eth3: usb_ether
393 13:56:05.267606 Hit any key to stop autoboot: 2
394 13:56:05.268512 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
395 13:56:05.269257 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
396 13:56:05.269747 Setting prompt string to ['=>']
397 13:56:05.270239 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
398 13:56:05.277632 0
399 13:56:05.278496 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
400 13:56:05.278986 Sending with 10 millisecond of delay
402 13:56:06.413405 => setenv autoload no
403 13:56:06.424158 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
404 13:56:06.429020 setenv autoload no
405 13:56:06.429733 Sending with 10 millisecond of delay
407 13:56:08.226292 => setenv initrd_high 0xffffffff
408 13:56:08.237057 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
409 13:56:08.237882 setenv initrd_high 0xffffffff
410 13:56:08.238603 Sending with 10 millisecond of delay
412 13:56:09.854432 => setenv fdt_high 0xffffffff
413 13:56:09.865144 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
414 13:56:09.865928 setenv fdt_high 0xffffffff
415 13:56:09.866630 Sending with 10 millisecond of delay
417 13:56:10.158346 => dhcp
418 13:56:10.168967 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
419 13:56:10.169727 dhcp
420 13:56:10.170150 link up on port 0, speed 100, full duplex
421 13:56:10.170559 BOOTP broadcast 1
422 13:56:10.193711 DHCP client bound to address 192.168.6.12 (19 ms)
423 13:56:10.194412 Sending with 10 millisecond of delay
425 13:56:11.870525 => setenv serverip 192.168.6.2
426 13:56:11.881322 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
427 13:56:11.882193 setenv serverip 192.168.6.2
428 13:56:11.882901 Sending with 10 millisecond of delay
430 13:56:15.364626 => tftp 0x82000000 934132/tftp-deploy-abofgn5v/kernel/zImage
431 13:56:15.375418 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
432 13:56:15.376287 tftp 0x82000000 934132/tftp-deploy-abofgn5v/kernel/zImage
433 13:56:15.376741 link up on port 0, speed 100, full duplex
434 13:56:15.380246 Using ethernet@4a100000 device
435 13:56:15.385758 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
436 13:56:15.393143 Filename '934132/tftp-deploy-abofgn5v/kernel/zImage'.
437 13:56:15.393625 Load address: 0x82000000
438 13:56:17.795640 Loading: *################################################## 10.9 MiB
439 13:56:17.796292 4.5 MiB/s
440 13:56:17.796727 done
441 13:56:17.800185 Bytes transferred = 11444736 (aea200 hex)
442 13:56:17.800985 Sending with 10 millisecond of delay
444 13:56:22.247395 => tftp 0x83000000 934132/tftp-deploy-abofgn5v/ramdisk/ramdisk.cpio.gz.uboot
445 13:56:22.258322 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
446 13:56:22.259230 tftp 0x83000000 934132/tftp-deploy-abofgn5v/ramdisk/ramdisk.cpio.gz.uboot
447 13:56:22.259733 link up on port 0, speed 100, full duplex
448 13:56:22.263039 Using ethernet@4a100000 device
449 13:56:22.268651 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
450 13:56:22.277281 Filename '934132/tftp-deploy-abofgn5v/ramdisk/ramdisk.cpio.gz.uboot'.
451 13:56:22.277984 Load address: 0x83000000
452 13:56:25.298485 Loading: *################################################## 14.1 MiB
453 13:56:25.299122 4.7 MiB/s
454 13:56:25.299557 done
455 13:56:25.302967 Bytes transferred = 14790042 (e1ad9a hex)
456 13:56:25.303792 Sending with 10 millisecond of delay
458 13:56:27.160404 => setenv initrd_size ${filesize}
459 13:56:27.171172 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
460 13:56:27.172034 setenv initrd_size ${filesize}
461 13:56:27.172750 Sending with 10 millisecond of delay
463 13:56:31.316451 => tftp 0x88000000 934132/tftp-deploy-abofgn5v/dtb/am335x-boneblack.dtb
464 13:56:31.327227 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
465 13:56:31.328108 tftp 0x88000000 934132/tftp-deploy-abofgn5v/dtb/am335x-boneblack.dtb
466 13:56:31.328544 link up on port 0, speed 100, full duplex
467 13:56:31.332026 Using ethernet@4a100000 device
468 13:56:31.337580 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
469 13:56:31.348748 Filename '934132/tftp-deploy-abofgn5v/dtb/am335x-boneblack.dtb'.
470 13:56:31.349221 Load address: 0x88000000
471 13:56:31.360382 Loading: *################################################## 68.9 KiB
472 13:56:31.360832 4.2 MiB/s
473 13:56:31.369064 done
474 13:56:31.369511 Bytes transferred = 70568 (113a8 hex)
475 13:56:31.370177 Sending with 10 millisecond of delay
477 13:56:44.542916 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/934132/extract-nfsrootfs-2jrv9trt,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 13:56:44.553701 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
479 13:56:44.554225 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/934132/extract-nfsrootfs-2jrv9trt,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 13:56:44.554694 Sending with 10 millisecond of delay
482 13:56:46.894195 => bootz 0x82000000 0x83000000 0x88000000
483 13:56:46.905068 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 13:56:46.905655 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
485 13:56:46.906739 bootz 0x82000000 0x83000000 0x88000000
486 13:56:46.907231 Kernel image @ 0x82000000 [ 0x000000 - 0xaea200 ]
487 13:56:46.907781 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 13:56:46.912570 Image Name:
489 13:56:46.913060 Created: 2024-11-04 13:55:49 UTC
490 13:56:46.918285 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 13:56:46.923779 Data Size: 14789978 Bytes = 14.1 MiB
492 13:56:46.924296 Load Address: 00000000
493 13:56:46.929876 Entry Point: 00000000
494 13:56:47.098482 Verifying Checksum ... OK
495 13:56:47.099141 ## Flattened Device Tree blob at 88000000
496 13:56:47.104831 Booting using the fdt blob at 0x88000000
497 13:56:47.109832 Using Device Tree in place at 88000000, end 880143a7
498 13:56:47.123548
499 13:56:47.124137 Starting kernel ...
500 13:56:47.124611
501 13:56:47.125561 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 13:56:47.126181 start: 2.4.4 auto-login-action (timeout 00:04:02) [common]
503 13:56:47.126694 Setting prompt string to ['Linux version [0-9]']
504 13:56:47.127199 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
505 13:56:47.127707 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
506 13:56:47.964313 [ 0.000000] Booting Linux on physical CPU 0x0
507 13:56:47.970219 start: 2.4.4.1 login-action (timeout 00:04:01) [common]
508 13:56:47.970837 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 13:56:47.971360 Setting prompt string to []
510 13:56:47.971900 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 13:56:47.972468 Using line separator: #'\n'#
512 13:56:47.972928 No login prompt set.
513 13:56:47.973416 Parsing kernel messages
514 13:56:47.973858 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 13:56:47.974714 [login-action] Waiting for messages, (timeout 00:04:01)
516 13:56:47.975214 Waiting using forced prompt support (timeout 00:02:01)
517 13:56:47.986902 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j361698-arm-gcc-12-multi-v7-defconfig-mdcg5) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Mon Nov 4 13:39:27 UTC 2024
518 13:56:47.992646 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
519 13:56:47.998458 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
520 13:56:48.009807 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
521 13:56:48.015512 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
522 13:56:48.021459 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
523 13:56:48.021945 [ 0.000000] Memory policy: Data cache writeback
524 13:56:48.028033 [ 0.000000] efi: UEFI not found.
525 13:56:48.036740 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
526 13:56:48.037228 [ 0.000000] Zone ranges:
527 13:56:48.042589 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
528 13:56:48.048359 [ 0.000000] Normal empty
529 13:56:48.053984 [ 0.000000] HighMem empty
530 13:56:48.054484 [ 0.000000] Movable zone start for each node
531 13:56:48.059676 [ 0.000000] Early memory node ranges
532 13:56:48.065304 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
533 13:56:48.072985 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
534 13:56:48.098400 [ 0.000000] CPU: All CPU(s) started in SVC mode.
535 13:56:48.104054 [ 0.000000] AM335X ES2.1 (sgx neon)
536 13:56:48.115690 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
537 13:56:48.133367 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/934132/extract-nfsrootfs-2jrv9trt,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
538 13:56:48.144902 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
539 13:56:48.150642 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
540 13:56:48.156374 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
541 13:56:48.166431 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
542 13:56:48.195453 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
543 13:56:48.201422 <6>[ 0.000000] trace event string verifier disabled
544 13:56:48.201911 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
545 13:56:48.209465 <6>[ 0.000000] rcu: RCU event tracing is enabled.
546 13:56:48.215190 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
547 13:56:48.226651 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
548 13:56:48.231597 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
549 13:56:48.246645 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
550 13:56:48.263866 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
551 13:56:48.270577 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
552 13:56:48.363168 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
553 13:56:48.374564 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
554 13:56:48.381318 <6>[ 0.008336] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
555 13:56:48.394398 <6>[ 0.019137] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
556 13:56:48.401697 <6>[ 0.033960] Console: colour dummy device 80x30
557 13:56:48.407833 Matched prompt #6: WARNING:
558 13:56:48.408385 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
559 13:56:48.413241 <3>[ 0.038855] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
560 13:56:48.418977 <3>[ 0.045922] This ensures that you still see kernel messages. Please
561 13:56:48.422226 <3>[ 0.052651] update your kernel commandline.
562 13:56:48.462921 <6>[ 0.057262] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
563 13:56:48.468635 <6>[ 0.096142] CPU: Testing write buffer coherency: ok
564 13:56:48.474573 <6>[ 0.101509] CPU0: Spectre v2: using BPIALL workaround
565 13:56:48.475056 <6>[ 0.106974] pid_max: default: 32768 minimum: 301
566 13:56:48.486039 <6>[ 0.112165] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 13:56:48.492996 <6>[ 0.119987] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 13:56:48.500078 <6>[ 0.129350] CPU0: thread -1, cpu 0, socket -1, mpidr 0
569 13:56:48.508463 <6>[ 0.136342] Setting up static identity map for 0x80300000 - 0x803000ac
570 13:56:48.514254 <6>[ 0.145955] rcu: Hierarchical SRCU implementation.
571 13:56:48.521890 <6>[ 0.151239] rcu: Max phase no-delay instances is 1000.
572 13:56:48.530392 <6>[ 0.162343] EFI services will not be available.
573 13:56:48.536221 <6>[ 0.167629] smp: Bringing up secondary CPUs ...
574 13:56:48.541946 <6>[ 0.172676] smp: Brought up 1 node, 1 CPU
575 13:56:48.550143 <6>[ 0.177078] SMP: Total of 1 processors activated (996.14 BogoMIPS).
576 13:56:48.556100 <6>[ 0.183847] CPU: All CPU(s) started in SVC mode.
577 13:56:48.568266 <6>[ 0.189033] Memory: 406000K/522240K available (16384K kernel code, 2543K rwdata, 6788K rodata, 2048K init, 430K bss, 49048K reserved, 65536K cma-reserved, 0K highmem)
578 13:56:48.573999 <6>[ 0.205292] devtmpfs: initialized
579 13:56:48.596423 <6>[ 0.222602] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
580 13:56:48.607939 <6>[ 0.231179] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
581 13:56:48.613879 <6>[ 0.241631] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
582 13:56:48.624813 <6>[ 0.253905] pinctrl core: initialized pinctrl subsystem
583 13:56:48.633868 <6>[ 0.264522] DMI not present or invalid.
584 13:56:48.642135 <6>[ 0.270381] NET: Registered PF_NETLINK/PF_ROUTE protocol family
585 13:56:48.651631 <6>[ 0.279285] DMA: preallocated 256 KiB pool for atomic coherent allocations
586 13:56:48.666766 <6>[ 0.290817] thermal_sys: Registered thermal governor 'step_wise'
587 13:56:48.667310 <6>[ 0.290979] cpuidle: using governor menu
588 13:56:48.694632 <6>[ 0.326818] No ATAGs?
589 13:56:48.700824 <6>[ 0.329551] hw-breakpoint: debug architecture 0x4 unsupported.
590 13:56:48.710945 <6>[ 0.341445] Serial: AMBA PL011 UART driver
591 13:56:48.742709 <6>[ 0.374890] iommu: Default domain type: Translated
592 13:56:48.751819 <6>[ 0.380238] iommu: DMA domain TLB invalidation policy: strict mode
593 13:56:48.778818 <5>[ 0.410353] SCSI subsystem initialized
594 13:56:48.784589 <6>[ 0.415235] usbcore: registered new interface driver usbfs
595 13:56:48.790395 <6>[ 0.421261] usbcore: registered new interface driver hub
596 13:56:48.797136 <6>[ 0.427046] usbcore: registered new device driver usb
597 13:56:48.802873 <6>[ 0.433544] pps_core: LinuxPPS API ver. 1 registered
598 13:56:48.814547 <6>[ 0.438934] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
599 13:56:48.821612 <6>[ 0.448657] PTP clock support registered
600 13:56:48.822096 <6>[ 0.453115] EDAC MC: Ver: 3.0.0
601 13:56:48.870229 <6>[ 0.499889] scmi_core: SCMI protocol bus registered
602 13:56:48.885645 <6>[ 0.517195] vgaarb: loaded
603 13:56:48.891735 <6>[ 0.521035] clocksource: Switched to clocksource dmtimer
604 13:56:48.934397 <6>[ 0.566348] NET: Registered PF_INET protocol family
605 13:56:48.946920 <6>[ 0.572011] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
606 13:56:48.954119 <6>[ 0.580820] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
607 13:56:48.959852 <6>[ 0.589753] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
608 13:56:48.971457 <6>[ 0.598013] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
609 13:56:48.977258 <6>[ 0.606294] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
610 13:56:48.983226 <6>[ 0.614016] TCP: Hash tables configured (established 4096 bind 4096)
611 13:56:48.994581 <6>[ 0.620921] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
612 13:56:49.000485 <6>[ 0.627957] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
613 13:56:49.006593 <6>[ 0.635555] NET: Registered PF_UNIX/PF_LOCAL protocol family
614 13:56:49.083462 <6>[ 0.710002] RPC: Registered named UNIX socket transport module.
615 13:56:49.084068 <6>[ 0.716435] RPC: Registered udp transport module.
616 13:56:49.089176 <6>[ 0.721563] RPC: Registered tcp transport module.
617 13:56:49.094905 <6>[ 0.726667] RPC: Registered tcp-with-tls transport module.
618 13:56:49.107921 <6>[ 0.732590] RPC: Registered tcp NFSv4.1 backchannel transport module.
619 13:56:49.108450 <6>[ 0.739494] PCI: CLS 0 bytes, default 64
620 13:56:49.115198 <5>[ 0.745284] Initialise system trusted keyrings
621 13:56:49.136182 <6>[ 0.765340] Trying to unpack rootfs image as initramfs...
622 13:56:49.215514 <6>[ 0.841489] workingset: timestamp_bits=30 max_order=17 bucket_order=0
623 13:56:49.220279 <6>[ 0.849002] squashfs: version 4.0 (2009/01/31) Phillip Lougher
624 13:56:49.259279 <5>[ 0.891518] NFS: Registering the id_resolver key type
625 13:56:49.265087 <5>[ 0.897106] Key type id_resolver registered
626 13:56:49.270928 <5>[ 0.901776] Key type id_legacy registered
627 13:56:49.276662 <6>[ 0.906216] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
628 13:56:49.286232 <6>[ 0.913416] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
629 13:56:49.355639 <5>[ 0.987690] Key type asymmetric registered
630 13:56:49.361294 <5>[ 0.992263] Asymmetric key parser 'x509' registered
631 13:56:49.372810 <6>[ 0.997693] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
632 13:56:49.373389 <6>[ 1.005607] io scheduler mq-deadline registered
633 13:56:49.378637 <6>[ 1.010541] io scheduler kyber registered
634 13:56:49.384220 <6>[ 1.015028] io scheduler bfq registered
635 13:56:49.493083 <6>[ 1.121642] ledtrig-cpu: registered to indicate activity on CPUs
636 13:56:49.777245 <6>[ 1.405556] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
637 13:56:49.813291 <6>[ 1.445339] msm_serial: driver initialized
638 13:56:49.819388 <6>[ 1.450116] SuperH (H)SCI(F) driver initialized
639 13:56:49.825356 <6>[ 1.455488] STMicroelectronics ASC driver initialized
640 13:56:49.830596 <6>[ 1.461184] STM32 USART driver initialized
641 13:56:49.933395 <6>[ 1.564904] brd: module loaded
642 13:56:49.974397 <6>[ 1.605861] loop: module loaded
643 13:56:50.017717 <6>[ 1.649084] CAN device driver interface
644 13:56:50.024446 <6>[ 1.654315] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
645 13:56:50.030116 <6>[ 1.661370] e1000e: Intel(R) PRO/1000 Network Driver
646 13:56:50.035936 <6>[ 1.666759] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
647 13:56:50.041658 <6>[ 1.673241] igb: Intel(R) Gigabit Ethernet Network Driver
648 13:56:50.049946 <6>[ 1.679062] igb: Copyright (c) 2007-2014 Intel Corporation.
649 13:56:50.061651 <6>[ 1.688236] pegasus: Pegasus/Pegasus II USB Ethernet driver
650 13:56:50.067416 <6>[ 1.694395] usbcore: registered new interface driver pegasus
651 13:56:50.073284 <6>[ 1.700522] usbcore: registered new interface driver asix
652 13:56:50.079148 <6>[ 1.706402] usbcore: registered new interface driver ax88179_178a
653 13:56:50.084794 <6>[ 1.712990] usbcore: registered new interface driver cdc_ether
654 13:56:50.090613 <6>[ 1.719290] usbcore: registered new interface driver smsc75xx
655 13:56:50.096379 <6>[ 1.725529] usbcore: registered new interface driver smsc95xx
656 13:56:50.102153 <6>[ 1.731772] usbcore: registered new interface driver net1080
657 13:56:50.107910 <6>[ 1.737891] usbcore: registered new interface driver cdc_subset
658 13:56:50.113712 <6>[ 1.744298] usbcore: registered new interface driver zaurus
659 13:56:50.121376 <6>[ 1.750341] usbcore: registered new interface driver cdc_ncm
660 13:56:50.131586 <6>[ 1.759713] usbcore: registered new interface driver usb-storage
661 13:56:50.140167 <6>[ 1.770528] i2c_dev: i2c /dev entries driver
662 13:56:50.163871 <5>[ 1.788204] cpuidle: enable-method property 'ti,am3352' found operations
663 13:56:50.169715 <6>[ 1.797706] sdhci: Secure Digital Host Controller Interface driver
664 13:56:50.177809 <6>[ 1.804480] sdhci: Copyright(c) Pierre Ossman
665 13:56:50.184865 <6>[ 1.810853] Synopsys Designware Multimedia Card Interface Driver
666 13:56:50.189790 <6>[ 1.818745] sdhci-pltfm: SDHCI platform and OF driver helper
667 13:56:50.203780 <6>[ 1.828485] usbcore: registered new interface driver usbhid
668 13:56:50.204301 <6>[ 1.834622] usbhid: USB HID core driver
669 13:56:50.216426 <6>[ 1.846060] NET: Registered PF_INET6 protocol family
670 13:56:50.660785 <6>[ 2.292896] Segment Routing with IPv6
671 13:56:50.666639 <6>[ 2.297045] In-situ OAM (IOAM) with IPv6
672 13:56:50.673222 <6>[ 2.301599] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
673 13:56:50.679037 <6>[ 2.308875] NET: Registered PF_PACKET protocol family
674 13:56:50.684839 <6>[ 2.314444] can: controller area network core
675 13:56:50.690622 <6>[ 2.319272] NET: Registered PF_CAN protocol family
676 13:56:50.691105 <6>[ 2.324499] can: raw protocol
677 13:56:50.696369 <6>[ 2.327824] can: broadcast manager protocol
678 13:56:50.702866 <6>[ 2.332426] can: netlink gateway - max_hops=1
679 13:56:50.708993 <5>[ 2.337912] Key type dns_resolver registered
680 13:56:50.715270 <6>[ 2.342975] ThumbEE CPU extension supported.
681 13:56:50.715749 <5>[ 2.347662] Registering SWP/SWPB emulation handler
682 13:56:50.725045 <3>[ 2.353366] omap_voltage_late_init: Voltage driver support not added
683 13:56:50.942348 <5>[ 2.572024] Loading compiled-in X.509 certificates
684 13:56:51.060743 <6>[ 2.680052] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
685 13:56:51.067889 <6>[ 2.696727] pinctrl-single 44e10800.pinmux: 142 pins, size 568
686 13:56:51.094142 <3>[ 2.720381] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
687 13:56:51.299653 <3>[ 2.925853] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
688 13:56:51.503045 <6>[ 3.133451] OMAP GPIO hardware version 0.1
689 13:56:51.523817 <6>[ 3.152336] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
690 13:56:51.614473 <4>[ 3.242780] at24 2-0054: supply vcc not found, using dummy regulator
691 13:56:51.648755 <4>[ 3.277082] at24 2-0055: supply vcc not found, using dummy regulator
692 13:56:51.688870 <4>[ 3.317102] at24 2-0056: supply vcc not found, using dummy regulator
693 13:56:51.729429 <4>[ 3.357754] at24 2-0057: supply vcc not found, using dummy regulator
694 13:56:51.770496 <6>[ 3.399636] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
695 13:56:51.848716 <3>[ 3.473813] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
696 13:56:51.873329 <6>[ 3.494763] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
697 13:56:51.895588 <4>[ 3.520895] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
698 13:56:51.903291 <4>[ 3.530386] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
699 13:56:52.052940 <6>[ 3.681424] omap_rng 48310000.rng: Random Number Generator ver. 20
700 13:56:52.076226 <5>[ 3.707602] random: crng init done
701 13:56:52.124813 <6>[ 3.751799] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
702 13:56:52.160385 <6>[ 3.791113] Freeing initrd memory: 14444K
703 13:56:52.217358 <6>[ 3.843457] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
704 13:56:52.223137 <6>[ 3.853782] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
705 13:56:52.234887 <6>[ 3.861120] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
706 13:56:52.240713 <6>[ 3.868581] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
707 13:56:52.252246 <6>[ 3.876722] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
708 13:56:52.259600 <6>[ 3.888358] cpsw-switch 4a100000.switch: Detected MACID = 78:a5:04:e2:4c:3d
709 13:56:52.272787 <5>[ 3.897398] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
710 13:56:52.300535 <3>[ 3.927152] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
711 13:56:52.306269 <6>[ 3.935739] edma 49000000.dma: TI EDMA DMA engine driver
712 13:56:52.377415 <3>[ 4.003362] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
713 13:56:52.392121 <6>[ 4.017697] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
714 13:56:52.405004 <3>[ 4.034763] l3-aon-clkctrl:0000:0: failed to disable
715 13:56:52.458232 <6>[ 4.084797] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
716 13:56:52.463876 <6>[ 4.094305] printk: legacy console [ttyS0] enabled
717 13:56:52.469590 <6>[ 4.094305] printk: legacy console [ttyS0] enabled
718 13:56:52.475253 <6>[ 4.104633] printk: legacy bootconsole [omap8250] disabled
719 13:56:52.481096 <6>[ 4.104633] printk: legacy bootconsole [omap8250] disabled
720 13:56:52.516212 <4>[ 4.141778] tps65217-pmic: Failed to locate of_node [id: -1]
721 13:56:52.519745 <4>[ 4.149173] tps65217-bl: Failed to locate of_node [id: -1]
722 13:56:52.536088 <6>[ 4.168738] tps65217 0-0024: TPS65217 ID 0xe version 1.2
723 13:56:52.554501 <6>[ 4.175676] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
724 13:56:52.566463 <6>[ 4.189364] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
725 13:56:52.571975 <6>[ 4.201267] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
726 13:56:52.594113 <6>[ 4.220970] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
727 13:56:52.600032 <6>[ 4.230202] sdhci-omap 48060000.mmc: Got CD GPIO
728 13:56:52.608073 <4>[ 4.235390] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
729 13:56:52.622907 <4>[ 4.249048] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
730 13:56:52.629162 <4>[ 4.257793] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
731 13:56:52.639054 <4>[ 4.266380] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
732 13:56:52.737578 <6>[ 4.365579] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
733 13:56:52.783925 <6>[ 4.408079] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
734 13:56:52.789952 <6>[ 4.418961] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
735 13:56:52.799446 <6>[ 4.427839] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
736 13:56:52.850022 <6>[ 4.472301] mmc0: new high speed SDHC card at address 1234
737 13:56:52.850597 <6>[ 4.480536] mmcblk0: mmc0:1234 SA32G 29.1 GiB
738 13:56:52.860336 <6>[ 4.492691] mmcblk0: p1
739 13:56:52.878398 <6>[ 4.502296] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
740 13:56:52.902010 <6>[ 4.525057] mmc1: new high speed MMC card at address 0001
741 13:56:52.902556 <6>[ 4.532018] mmcblk1: mmc1:0001 MMC04G 3.60 GiB
742 13:56:52.907457 <6>[ 4.539494] mmcblk1boot0: mmc1:0001 MMC04G 2.00 MiB
743 13:56:52.916349 <6>[ 4.546583] mmcblk1boot1: mmc1:0001 MMC04G 2.00 MiB
744 13:56:52.925033 <6>[ 4.553747] mmcblk1rpmb: mmc1:0001 MMC04G 128 KiB, chardev (236:0)
745 13:56:54.975673 <6>[ 6.602090] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
746 13:56:55.038945 <5>[ 6.631056] Sending DHCP requests ., OK
747 13:56:55.050272 <6>[ 6.675588] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.12
748 13:56:55.050812 <6>[ 6.683735] IP-Config: Complete:
749 13:56:55.061595 <6>[ 6.687272] device=eth0, hwaddr=78:a5:04:e2:4c:3d, ipaddr=192.168.6.12, mask=255.255.255.0, gw=192.168.6.1
750 13:56:55.067344 <6>[ 6.697811] host=192.168.6.12, domain=, nis-domain=(none)
751 13:56:55.079605 <6>[ 6.704035] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
752 13:56:55.080196 <6>[ 6.704070] nameserver0=10.255.253.1
753 13:56:55.085806 <6>[ 6.716626] clk: Disabling unused clocks
754 13:56:55.091637 <6>[ 6.721403] PM: genpd: Disabling unused power domains
755 13:56:55.111519 <6>[ 6.740383] Freeing unused kernel image (initmem) memory: 2048K
756 13:56:55.119048 <6>[ 6.750214] Run /init as init process
757 13:56:55.141219 Loading, please wait...
758 13:56:55.216616 Starting systemd-udevd version 252.22-1~deb12u1
759 13:56:58.292191 <4>[ 9.917570] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
760 13:56:58.476568 <4>[ 10.101779] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
761 13:56:58.619135 <6>[ 10.251905] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
762 13:56:58.629798 <6>[ 10.257579] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
763 13:56:58.867086 <6>[ 10.498513] hub 1-0:1.0: USB hub found
764 13:56:58.940007 <6>[ 10.571274] hub 1-0:1.0: 1 port detected
765 13:56:59.140927 <6>[ 10.771953] tda998x 0-0070: found TDA19988
766 13:57:01.893871 Begin: Loading essential drivers ... done.
767 13:57:01.899181 Begin: Running /scripts/init-premount ... done.
768 13:57:01.904814 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
769 13:57:01.915064 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
770 13:57:01.923892 Device /sys/class/net/eth0 found
771 13:57:01.924397 done.
772 13:57:01.982371 Begin: Waiting up to 180 secs for any network device to become available ... done.
773 13:57:02.051618 IP-Config: eth0 hardware address 78:a5:04:e2:4c:3d mtu 1500 DHCP
774 13:57:02.073899 IP-Config: eth0 guessed broadcast address 192.168.6.255
775 13:57:02.079491 IP-Config: eth0 complete (dhcp from 192.168.6.1):
776 13:57:02.085076 address: 192.168.6.12 broadcast: 192.168.6.255 netmask: 255.255.255.0
777 13:57:02.096317 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
778 13:57:02.096824 rootserver: 192.168.6.1 rootpath:
779 13:57:02.099758 filename :
780 13:57:02.208022 done.
781 13:57:02.224708 Begin: Running /scripts/nfs-bottom ... done.
782 13:57:02.300571 Begin: Running /scripts/init-bottom ... done.
783 13:57:03.896098 <30>[ 15.524702] systemd[1]: System time before build time, advancing clock.
784 13:57:04.083967 <30>[ 15.686344] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
785 13:57:04.093469 <30>[ 15.723977] systemd[1]: Detected architecture arm.
786 13:57:04.105921
787 13:57:04.106504 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
788 13:57:04.106982
789 13:57:04.131937 <30>[ 15.760855] systemd[1]: Hostname set to <debian-bookworm-armhf>.
790 13:57:06.327267 <30>[ 17.955403] systemd[1]: Queued start job for default target graphical.target.
791 13:57:06.344016 <30>[ 17.970065] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
792 13:57:06.351580 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
793 13:57:06.378358 <30>[ 18.003463] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
794 13:57:06.385757 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
795 13:57:06.410698 <30>[ 18.037267] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
796 13:57:06.423785 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
797 13:57:06.446112 <30>[ 18.072961] systemd[1]: Created slice user.slice - User and Session Slice.
798 13:57:06.452832 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
799 13:57:06.481553 <30>[ 18.102419] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
800 13:57:06.487552 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
801 13:57:06.505418 <30>[ 18.132182] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
802 13:57:06.514436 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
803 13:57:06.546382 <30>[ 18.162233] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
804 13:57:06.552873 <30>[ 18.182737] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
805 13:57:06.561397 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
806 13:57:06.584524 <30>[ 18.211538] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
807 13:57:06.592779 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
808 13:57:06.615250 <30>[ 18.241886] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
809 13:57:06.623664 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
810 13:57:06.644997 <30>[ 18.271897] systemd[1]: Reached target paths.target - Path Units.
811 13:57:06.650096 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
812 13:57:06.674781 <30>[ 18.301678] systemd[1]: Reached target remote-fs.target - Remote File Systems.
813 13:57:06.682152 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
814 13:57:06.706185 <30>[ 18.332506] systemd[1]: Reached target slices.target - Slice Units.
815 13:57:06.711660 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
816 13:57:06.734973 <30>[ 18.361827] systemd[1]: Reached target swap.target - Swaps.
817 13:57:06.738938 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
818 13:57:06.765485 <30>[ 18.391794] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
819 13:57:06.773389 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
820 13:57:06.796134 <30>[ 18.422683] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
821 13:57:06.804422 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
822 13:57:06.892028 <30>[ 18.513924] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
823 13:57:06.904817 <30>[ 18.531708] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
824 13:57:06.913239 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
825 13:57:06.936507 <30>[ 18.562777] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
826 13:57:06.943839 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
827 13:57:06.969591 <30>[ 18.594380] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
828 13:57:06.976062 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
829 13:57:07.011479 <30>[ 18.638893] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
830 13:57:07.024968 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
831 13:57:07.046575 <30>[ 18.673045] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
832 13:57:07.055119 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
833 13:57:07.082321 <30>[ 18.702878] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
834 13:57:07.098805 <30>[ 18.719569] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
835 13:57:07.149089 <30>[ 18.776519] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
836 13:57:07.176502 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
837 13:57:07.238135 <30>[ 18.865646] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
838 13:57:07.256547 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
839 13:57:07.315836 <30>[ 18.942422] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
840 13:57:07.334029 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
841 13:57:07.395264 <30>[ 19.022451] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
842 13:57:07.417206 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
843 13:57:07.446688 <30>[ 19.074251] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
844 13:57:07.473438 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
845 13:57:07.525278 <30>[ 19.152320] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
846 13:57:07.532251 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
847 13:57:07.575112 <30>[ 19.201963] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
848 13:57:07.603666 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
849 13:57:07.646564 <30>[ 19.274482] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
850 13:57:07.673569 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
851 13:57:07.725458 <30>[ 19.353302] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
852 13:57:07.749497 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
853 13:57:07.782189 <28>[ 19.403318] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
854 13:57:07.790675 <28>[ 19.417731] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
855 13:57:07.835284 <30>[ 19.462271] systemd[1]: Starting systemd-journald.service - Journal Service...
856 13:57:07.841774 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
857 13:57:07.904828 <30>[ 19.532451] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
858 13:57:07.923887 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
859 13:57:07.966336 <30>[ 19.594163] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
860 13:57:08.017291 Starting [0;1;39msystemd-network-g… units from Kernel command line...
861 13:57:08.087939 <30>[ 19.714251] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
862 13:57:08.143811 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
863 13:57:08.213637 <30>[ 19.840751] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
864 13:57:08.268803 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
865 13:57:08.311917 <30>[ 19.939915] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
866 13:57:08.370762 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
867 13:57:08.377155 <30>[ 20.006912] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
868 13:57:08.422739 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
869 13:57:08.449300 <30>[ 20.076075] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
870 13:57:08.483038 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
871 13:57:08.618815 <30>[ 20.247351] systemd[1]: modprobe@configfs.service: Deactivated successfully.
872 13:57:08.655565 <30>[ 20.282957] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
873 13:57:08.684471 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
874 13:57:08.715099 <30>[ 20.343814] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
875 13:57:08.745080 <30>[ 20.372831] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
876 13:57:08.774501 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
877 13:57:08.795691 <30>[ 20.422849] systemd[1]: Started systemd-journald.service - Journal Service.
878 13:57:08.802598 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
879 13:57:08.834426 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
880 13:57:08.860239 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
881 13:57:08.896666 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
882 13:57:08.925651 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
883 13:57:08.947377 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
884 13:57:08.974731 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
885 13:57:08.997664 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
886 13:57:09.034593 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
887 13:57:09.084338 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
888 13:57:09.133565 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
889 13:57:09.198423 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
890 13:57:09.261849 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
891 13:57:09.328536 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
892 13:57:09.466631 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
893 13:57:09.532987 <46>[ 21.160831] systemd-journald[163]: Received client request to flush runtime journal.
894 13:57:09.646957 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
895 13:57:09.734268 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
896 13:57:10.534731 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
897 13:57:10.587836 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
898 13:57:11.287602 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
899 13:57:11.456611 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
900 13:57:11.476391 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
901 13:57:11.494001 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
902 13:57:11.574294 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
903 13:57:11.634140 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
904 13:57:12.572808 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
905 13:57:12.626525 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
906 13:57:12.889931 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
907 13:57:13.005994 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
908 13:57:13.076639 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
909 13:57:15.076968 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
910 13:57:15.108327 <5>[ 26.736450] cfg80211: Loading compiled-in X.509 certificates for regulatory database
911 13:57:15.440561 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
912 13:57:16.535829 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
913 13:57:16.666255 <5>[ 28.296594] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
914 13:57:16.762866 <5>[ 28.389873] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
915 13:57:16.768626 <4>[ 28.398667] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
916 13:57:16.776373 <6>[ 28.407763] cfg80211: failed to load regulatory.db
917 13:57:17.725871 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
918 13:57:18.093581 <46>[ 29.712725] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
919 13:57:18.162408 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0<46>[ 29.776459] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
920 13:57:18.163119 m - Network Configuration.
921 13:57:26.985938 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
922 13:57:27.014965 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
923 13:57:27.035912 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
924 13:57:27.058848 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
925 13:57:27.124183 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
926 13:57:27.174574 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
927 13:57:27.246074 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
928 13:57:27.292593 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
929 13:57:27.345919 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
930 13:57:27.370246 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
931 13:57:27.399415 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
932 13:57:27.439114 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
933 13:57:27.473145 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
934 13:57:27.503688 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
935 13:57:27.535085 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
936 13:57:27.557558 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
937 13:57:27.589989 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
938 13:57:27.619733 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
939 13:57:27.650769 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
940 13:57:27.674457 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
941 13:57:27.704284 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
942 13:57:27.724424 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
943 13:57:27.751202 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
944 13:57:27.824565 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
945 13:57:27.877655 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
946 13:57:27.977172 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
947 13:57:28.060088 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
948 13:57:28.125820 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
949 13:57:28.163490 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
950 13:57:28.198066 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
951 13:57:28.380464 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
952 13:57:28.463522 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
953 13:57:28.524984 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
954 13:57:28.553224 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
955 13:57:28.574815 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
956 13:57:28.766608 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
957 13:57:29.112266 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
958 13:57:29.165536 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
959 13:57:29.188322 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
960 13:57:29.280541 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
961 13:57:29.491089 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
962 13:57:29.638412
963 13:57:29.642274 Debian GNU/Linux 12 debian-krm-armhf login: root (automatic login)
964 13:57:29.642798
965 13:57:29.937000 Linux debian-bookworm-armhf 6.12.0-rc6 #1 SMP Mon Nov 4 13:39:27 UTC 2024 armv7l
966 13:57:29.937575
967 13:57:29.942576 The programs included with the Debian GNU/Linux system are free software;
968 13:57:29.948183 the exact distribution terms for each program are described in the
969 13:57:29.953749 individual files in /usr/share/doc/*/copyright.
970 13:57:29.954246
971 13:57:29.961718 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
972 13:57:29.962221 permitted by applicable law.
973 13:57:34.611261 Unable to match end of the kernel message
975 13:57:34.613019 Setting prompt string to ['/ #']
976 13:57:34.613648 end: 2.4.4.1 login-action (duration 00:00:47) [common]
978 13:57:34.615197 end: 2.4.4 auto-login-action (duration 00:00:47) [common]
979 13:57:34.615830 start: 2.4.5 expect-shell-connection (timeout 00:03:15) [common]
980 13:57:34.616412 Setting prompt string to ['/ #']
981 13:57:34.616905 Forcing a shell prompt, looking for ['/ #']
983 13:57:34.668083 / #
984 13:57:34.668705 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
985 13:57:34.669187 Waiting using forced prompt support (timeout 00:02:30)
986 13:57:34.673503
987 13:57:34.682224 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
988 13:57:34.682834 start: 2.4.6 export-device-env (timeout 00:03:15) [common]
989 13:57:34.683333 Sending with 10 millisecond of delay
991 13:57:39.672397 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/934132/extract-nfsrootfs-2jrv9trt'
992 13:57:39.683405 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/934132/extract-nfsrootfs-2jrv9trt'
993 13:57:39.684340 Sending with 10 millisecond of delay
995 13:57:41.782093 / # export NFS_SERVER_IP='192.168.6.2'
996 13:57:41.793069 export NFS_SERVER_IP='192.168.6.2'
997 13:57:41.794042 end: 2.4.6 export-device-env (duration 00:00:07) [common]
998 13:57:41.794675 end: 2.4 uboot-commands (duration 00:01:52) [common]
999 13:57:41.795313 end: 2 uboot-action (duration 00:01:52) [common]
1000 13:57:41.795952 start: 3 lava-test-retry (timeout 00:06:59) [common]
1001 13:57:41.796654 start: 3.1 lava-test-shell (timeout 00:06:59) [common]
1002 13:57:41.797172 Using namespace: common
1004 13:57:41.898419 / # #
1005 13:57:41.899119 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1006 13:57:41.903876 #
1007 13:57:41.909656 Using /lava-934132
1009 13:57:42.010893 / # export SHELL=/bin/bash
1010 13:57:42.016259 export SHELL=/bin/bash
1012 13:57:42.122860 / # . /lava-934132/environment
1013 13:57:42.128228 . /lava-934132/environment
1015 13:57:42.241128 / # /lava-934132/bin/lava-test-runner /lava-934132/0
1016 13:57:42.241836 Test shell timeout: 10s (minimum of the action and connection timeout)
1017 13:57:42.246491 /lava-934132/bin/lava-test-runner /lava-934132/0
1018 13:57:42.663952 + export TESTRUN_ID=0_timesync-off
1019 13:57:42.671819 + TESTRUN_ID=0_timesync-off
1020 13:57:42.672368 + cd /lava-934132/0/tests/0_timesync-off
1021 13:57:42.672842 ++ cat uuid
1022 13:57:42.688088 + UUID=934132_1.6.2.4.1
1023 13:57:42.688598 + set +x
1024 13:57:42.696633 <LAVA_SIGNAL_STARTRUN 0_timesync-off 934132_1.6.2.4.1>
1025 13:57:42.697138 + systemctl stop systemd-timesyncd
1026 13:57:42.697892 Received signal: <STARTRUN> 0_timesync-off 934132_1.6.2.4.1
1027 13:57:42.698379 Starting test lava.0_timesync-off (934132_1.6.2.4.1)
1028 13:57:42.698966 Skipping test definition patterns.
1029 13:57:43.019835 + set +x
1030 13:57:43.020499 <LAVA_SIGNAL_ENDRUN 0_timesync-off 934132_1.6.2.4.1>
1031 13:57:43.021248 Received signal: <ENDRUN> 0_timesync-off 934132_1.6.2.4.1
1032 13:57:43.021800 Ending use of test pattern.
1033 13:57:43.022258 Ending test lava.0_timesync-off (934132_1.6.2.4.1), duration 0.32
1035 13:57:43.185403 + export TESTRUN_ID=1_kselftest-dt
1036 13:57:43.193365 + TESTRUN_ID=1_kselftest-dt
1037 13:57:43.193869 + cd /lava-934132/0/tests/1_kselftest-dt
1038 13:57:43.194339 ++ cat uuid
1039 13:57:43.209641 + UUID=934132_1.6.2.4.5
1040 13:57:43.210138 + set +x
1041 13:57:43.215253 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 934132_1.6.2.4.5>
1042 13:57:43.215743 + cd ./automated/linux/kselftest/
1043 13:57:43.216787 Received signal: <STARTRUN> 1_kselftest-dt 934132_1.6.2.4.5
1044 13:57:43.217322 Starting test lava.1_kselftest-dt (934132_1.6.2.4.5)
1045 13:57:43.217897 Skipping test definition patterns.
1046 13:57:43.242287 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/pm/testing/v6.12-rc6-84-ge231ee35020e/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g pm -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1047 13:57:43.355600 INFO: install_deps skipped
1048 13:57:44.076141 --2024-11-04 13:57:44-- http://storage.kernelci.org/pm/testing/v6.12-rc6-84-ge231ee35020e/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1049 13:57:44.111645 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1050 13:57:44.249541 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1051 13:57:44.386274 HTTP request sent, awaiting response... 200 OK
1052 13:57:44.386861 Length: 4106200 (3.9M) [application/octet-stream]
1053 13:57:44.391737 Saving to: 'kselftest_armhf.tar.gz'
1054 13:57:44.392313
1055 13:57:45.717932
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 185KB/s
kselftest_armhf.tar 4%[ ] 194.76K 353KB/s
kselftest_armhf.tar 19%[==> ] 798.04K 944KB/s
kselftest_armhf.tar 68%[============> ] 2.70M 2.58MB/s
kselftest_armhf.tar 86%[================> ] 3.40M 2.65MB/s
kselftest_armhf.tar 100%[===================>] 3.92M 2.95MB/s in 1.3s
1056 13:57:45.718664
1057 13:57:46.309563 2024-11-04 13:57:45 (2.95 MB/s) - 'kselftest_armhf.tar.gz' saved [4106200/4106200]
1058 13:57:46.310260
1059 13:57:58.558058 skiplist:
1060 13:57:58.558851 ========================================
1061 13:57:58.563751 ========================================
1062 13:57:58.664146 dt:test_unprobed_devices.sh
1063 13:57:58.695038 ============== Tests to run ===============
1064 13:57:58.702871 dt:test_unprobed_devices.sh
1065 13:57:58.706889 ===========End Tests to run ===============
1066 13:57:58.717646 shardfile-dt pass
1067 13:57:58.938456 <12>[ 70.572414] kselftest: Running tests in dt
1068 13:57:58.966463 TAP version 13
1069 13:57:58.990147 1..1
1070 13:57:59.043496 # timeout set to 45
1071 13:57:59.044105 # selftests: dt: test_unprobed_devices.sh
1072 13:57:59.794681 # TAP version 13
1073 13:58:24.762724 �# 1..257
1074 13:58:24.928916 # ok 1 / # SKIP
1075 13:58:24.951215 # ok 2 /clk_mcasp0
1076 13:58:25.022188 # ok 3 /clk_mcasp0_fixed # SKIP
1077 13:58:25.100511 # ok 4 /cpus/cpu@0 # SKIP
1078 13:58:25.170408 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1079 13:58:25.187103 # ok 6 /fixedregulator0
1080 13:58:25.213730 # ok 7 /leds
1081 13:58:25.230976 # ok 8 /ocp
1082 13:58:25.256778 # ok 9 /ocp/interconnect@44c00000
1083 13:58:25.284071 # ok 10 /ocp/interconnect@44c00000/segment@0
1084 13:58:25.305746 # ok 11 /ocp/interconnect@44c00000/segment@100000
1085 13:58:25.327897 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1086 13:58:25.398678 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1087 13:58:25.419112 # ok 14 /ocp/interconnect@44c00000/segment@200000
1088 13:58:25.447156 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1089 13:58:25.549031 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1090 13:58:25.620832 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1091 13:58:25.693625 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1092 13:58:25.765571 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1093 13:58:25.836896 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1094 13:58:25.910370 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1095 13:58:25.983699 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1096 13:58:26.055543 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1097 13:58:26.139242 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1098 13:58:26.211103 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1099 13:58:26.282532 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1100 13:58:26.355483 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1101 13:58:26.427175 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1102 13:58:26.501184 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1103 13:58:26.571341 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1104 13:58:26.644292 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1105 13:58:26.714142 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1106 13:58:26.788261 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1107 13:58:26.860065 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1108 13:58:26.932475 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1109 13:58:27.006776 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1110 13:58:27.079917 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1111 13:58:27.147849 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1112 13:58:27.222175 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1113 13:58:27.294624 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1114 13:58:27.369198 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1115 13:58:27.440909 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1116 13:58:27.509597 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1117 13:58:27.586439 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1118 13:58:27.658294 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1119 13:58:27.725911 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1120 13:58:27.797937 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1121 13:58:27.869966 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1122 13:58:27.942022 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1123 13:58:28.018223 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1124 13:58:28.090433 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1125 13:58:28.156907 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1126 13:58:28.230884 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1127 13:58:28.303815 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1128 13:58:28.374526 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1129 13:58:28.446101 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1130 13:58:28.518944 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1131 13:58:28.593303 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1132 13:58:28.663769 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1133 13:58:28.736308 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1134 13:58:28.808376 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1135 13:58:28.881521 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1136 13:58:28.951894 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1137 13:58:29.024709 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1138 13:58:29.095807 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1139 13:58:29.168508 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1140 13:58:29.247886 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1141 13:58:29.313776 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1142 13:58:29.385926 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1143 13:58:29.458882 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1144 13:58:29.533361 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1145 13:58:29.604682 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1146 13:58:29.676307 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1147 13:58:29.748020 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1148 13:58:29.820003 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1149 13:58:29.891793 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1150 13:58:29.964203 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1151 13:58:30.035580 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1152 13:58:30.106148 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1153 13:58:30.178910 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1154 13:58:30.260621 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1155 13:58:30.326453 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1156 13:58:30.397700 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1157 13:58:30.470815 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1158 13:58:30.542232 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1159 13:58:30.614113 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1160 13:58:30.692705 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1161 13:58:30.778762 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1162 13:58:30.851975 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1163 13:58:30.925974 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1164 13:58:31.016689 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1165 13:58:31.081372 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1166 13:58:31.152376 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1167 13:58:31.224979 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1168 13:58:31.245273 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1169 13:58:31.269426 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1170 13:58:31.293838 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1171 13:58:31.317469 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1172 13:58:31.341584 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1173 13:58:31.364811 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1174 13:58:31.389233 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1175 13:58:31.411712 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1176 13:58:31.518075 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1177 13:58:31.546614 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1178 13:58:31.569000 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1179 13:58:31.591087 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1180 13:58:31.695157 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1181 13:58:31.771441 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1182 13:58:31.847797 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1183 13:58:31.919975 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1184 13:58:31.991387 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1185 13:58:32.061418 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1186 13:58:32.140117 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1187 13:58:32.206277 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1188 13:58:32.278323 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1189 13:58:32.351336 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1190 13:58:32.425301 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1191 13:58:32.497458 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1192 13:58:32.569773 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1193 13:58:32.648379 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1194 13:58:32.720665 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1195 13:58:32.789036 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1196 13:58:32.810810 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1197 13:58:32.880568 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1198 13:58:32.949778 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1199 13:58:33.022321 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1200 13:58:33.047276 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1201 13:58:33.116647 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1202 13:58:33.139414 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1203 13:58:33.210204 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1204 13:58:33.237099 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1205 13:58:33.257588 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1206 13:58:33.284179 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1207 13:58:33.307862 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1208 13:58:33.328831 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1209 13:58:33.351747 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1210 13:58:33.377607 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1211 13:58:33.453359 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1212 13:58:33.472204 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1213 13:58:33.496216 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1214 13:58:33.568317 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1215 13:58:33.640984 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1216 13:58:33.659735 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1217 13:58:33.760069 # not ok 144 /ocp/interconnect@47c00000
1218 13:58:33.831606 # not ok 145 /ocp/interconnect@47c00000/segment@0
1219 13:58:33.852659 # ok 146 /ocp/interconnect@48000000
1220 13:58:33.880684 # ok 147 /ocp/interconnect@48000000/segment@0
1221 13:58:33.905898 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1222 13:58:33.926899 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1223 13:58:33.952690 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1224 13:58:33.976023 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1225 13:58:33.996829 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1226 13:58:34.019370 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1227 13:58:34.041518 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1228 13:58:34.116959 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1229 13:58:34.185899 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1230 13:58:34.208468 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1231 13:58:34.236937 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1232 13:58:34.256684 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1233 13:58:34.279723 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1234 13:58:34.305952 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1235 13:58:34.327463 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1236 13:58:34.352670 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1237 13:58:34.376818 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1238 13:58:34.394991 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1239 13:58:34.423452 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1240 13:58:34.446017 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1241 13:58:34.467336 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1242 13:58:34.488565 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1243 13:58:34.516589 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1244 13:58:34.536805 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1245 13:58:34.559685 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1246 13:58:34.580962 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1247 13:58:34.606390 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1248 13:58:34.627153 # ok 175 /ocp/interconnect@48000000/segment@100000
1249 13:58:34.651908 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1250 13:58:34.677596 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1251 13:58:34.753572 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1252 13:58:34.827874 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1253 13:58:34.897460 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1254 13:58:34.970725 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1255 13:58:35.037191 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1256 13:58:35.112393 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1257 13:58:35.182055 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1258 13:58:35.256944 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1259 13:58:35.276646 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1260 13:58:35.305986 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1261 13:58:35.327020 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1262 13:58:35.349001 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1263 13:58:35.372153 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1264 13:58:35.396468 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1265 13:58:35.424048 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1266 13:58:35.447648 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1267 13:58:35.474743 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1268 13:58:35.493441 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1269 13:58:35.521597 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1270 13:58:35.540891 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1271 13:58:35.562010 # ok 198 /ocp/interconnect@48000000/segment@200000
1272 13:58:35.593399 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1273 13:58:35.659260 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1274 13:58:35.680091 # ok 201 /ocp/interconnect@48000000/segment@300000
1275 13:58:35.704638 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1276 13:58:35.732991 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1277 13:58:35.757640 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1278 13:58:35.776934 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1279 13:58:35.804166 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1280 13:58:35.826881 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1281 13:58:35.895744 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1282 13:58:35.914532 # ok 209 /ocp/interconnect@4a000000
1283 13:58:35.938120 # ok 210 /ocp/interconnect@4a000000/segment@0
1284 13:58:35.966837 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1285 13:58:35.992401 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1286 13:58:36.013019 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1287 13:58:36.034141 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1288 13:58:36.106726 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1289 13:58:36.212094 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1290 13:58:36.284434 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1291 13:58:36.387113 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1292 13:58:36.458032 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1293 13:58:36.528327 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1294 13:58:36.631247 # not ok 221 /ocp/interconnect@4b140000
1295 13:58:36.702912 # not ok 222 /ocp/interconnect@4b140000/segment@0
1296 13:58:36.768707 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1297 13:58:36.794038 # ok 224 /ocp/target-module@40300000
1298 13:58:36.813444 # ok 225 /ocp/target-module@40300000/sram@0
1299 13:58:36.894955 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1300 13:58:36.959512 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1301 13:58:36.979746 # ok 228 /ocp/target-module@47400000
1302 13:58:37.003081 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1303 13:58:37.025814 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1304 13:58:37.052928 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1305 13:58:37.074740 # ok 232 /ocp/target-module@47400000/usb@1400
1306 13:58:37.094835 # ok 233 /ocp/target-module@47400000/usb@1800
1307 13:58:37.119665 # ok 234 /ocp/target-module@47810000
1308 13:58:37.141849 # ok 235 /ocp/target-module@49000000
1309 13:58:37.160702 # ok 236 /ocp/target-module@49000000/dma@0
1310 13:58:37.184138 # ok 237 /ocp/target-module@49800000
1311 13:58:37.210070 # ok 238 /ocp/target-module@49800000/dma@0
1312 13:58:37.227310 # ok 239 /ocp/target-module@49900000
1313 13:58:37.254577 # ok 240 /ocp/target-module@49900000/dma@0
1314 13:58:37.272828 # ok 241 /ocp/target-module@49a00000
1315 13:58:37.296248 # ok 242 /ocp/target-module@49a00000/dma@0
1316 13:58:37.321836 # ok 243 /ocp/target-module@4c000000
1317 13:58:37.393886 # not ok 244 /ocp/target-module@4c000000/emif@0
1318 13:58:37.410967 # ok 245 /ocp/target-module@50000000
1319 13:58:37.434026 # ok 246 /ocp/target-module@53100000
1320 13:58:37.509617 # not ok 247 /ocp/target-module@53100000/sham@0
1321 13:58:37.531247 # ok 248 /ocp/target-module@53500000
1322 13:58:37.599215 # not ok 249 /ocp/target-module@53500000/aes@0
1323 13:58:37.624011 # ok 250 /ocp/target-module@56000000
1324 13:58:37.730393 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1325 13:58:37.795054 # ok 252 /opp-table # SKIP
1326 13:58:37.866231 # ok 253 /soc # SKIP
1327 13:58:37.891049 # ok 254 /sound
1328 13:58:37.909425 # ok 255 /target-module@4b000000
1329 13:58:37.935368 # ok 256 /target-module@4b000000/target-module@140000
1330 13:58:37.955863 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1331 13:58:37.963846 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1332 13:58:37.970794 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1333 13:58:40.221552 dt_test_unprobed_devices_sh_ skip
1334 13:58:40.227088 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1335 13:58:40.232900 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1336 13:58:40.233391 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1337 13:58:40.241576 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1338 13:58:40.242010 dt_test_unprobed_devices_sh_fixedregulator0 pass
1339 13:58:40.247135 dt_test_unprobed_devices_sh_leds pass
1340 13:58:40.252814 dt_test_unprobed_devices_sh_ocp pass
1341 13:58:40.258518 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1342 13:58:40.264069 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1343 13:58:40.269607 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1344 13:58:40.275124 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1345 13:58:40.286406 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1346 13:58:40.292024 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1347 13:58:40.297651 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1348 13:58:40.308909 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1349 13:58:40.320147 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1350 13:58:40.325820 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1351 13:58:40.336966 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1352 13:58:40.348085 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1353 13:58:40.359257 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1354 13:58:40.370478 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1355 13:58:40.376117 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1356 13:58:40.387260 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1357 13:58:40.398505 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1358 13:58:40.409635 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1359 13:58:40.415195 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1360 13:58:40.426408 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1361 13:58:40.437609 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1362 13:58:40.448794 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1363 13:58:40.460127 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1364 13:58:40.465612 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1365 13:58:40.476787 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1366 13:58:40.488053 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1367 13:58:40.499184 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1368 13:58:40.504760 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1369 13:58:40.515954 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1370 13:58:40.527144 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1371 13:58:40.538350 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1372 13:58:40.549518 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1373 13:58:40.560763 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1374 13:58:40.571953 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1375 13:58:40.583142 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1376 13:58:40.594314 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1377 13:58:40.605505 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1378 13:58:40.616788 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1379 13:58:40.627911 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1380 13:58:40.639100 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1381 13:58:40.650315 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1382 13:58:40.661515 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1383 13:58:40.672689 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1384 13:58:40.683858 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1385 13:58:40.695074 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1386 13:58:40.706234 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1387 13:58:40.717442 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1388 13:58:40.728608 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1389 13:58:40.739863 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1390 13:58:40.750981 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1391 13:58:40.756580 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1392 13:58:40.767754 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1393 13:58:40.778960 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1394 13:58:40.790137 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1395 13:58:40.801345 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1396 13:58:40.812560 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1397 13:58:40.823811 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1398 13:58:40.834950 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1399 13:58:40.846132 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1400 13:58:40.857416 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1401 13:58:40.868527 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1402 13:58:40.874143 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1403 13:58:40.885314 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1404 13:58:40.896486 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1405 13:58:40.907700 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1406 13:58:40.918908 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1407 13:58:40.930091 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1408 13:58:40.941276 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1409 13:58:40.952474 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1410 13:58:40.963648 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1411 13:58:40.974962 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1412 13:58:40.986045 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1413 13:58:40.997223 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1414 13:58:41.008428 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1415 13:58:41.019609 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1416 13:58:41.030808 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1417 13:58:41.036399 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1418 13:58:41.047669 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1419 13:58:41.058847 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1420 13:58:41.069985 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1421 13:58:41.081169 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1422 13:58:41.092361 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1423 13:58:41.103552 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1424 13:58:41.114736 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1425 13:58:41.125928 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1426 13:58:41.137134 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1427 13:58:41.148333 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1428 13:58:41.159519 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1429 13:58:41.165162 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1430 13:58:41.176303 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1431 13:58:41.187540 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1432 13:58:41.193123 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1433 13:58:41.204320 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1434 13:58:41.209920 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1435 13:58:41.221047 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1436 13:58:41.232280 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1437 13:58:41.237851 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1438 13:58:41.249020 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1439 13:58:41.260305 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1440 13:58:41.271440 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1441 13:58:41.282624 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1442 13:58:41.293837 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1443 13:58:41.305021 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1444 13:58:41.321782 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1445 13:58:41.332954 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1446 13:58:41.344176 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1447 13:58:41.355343 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1448 13:58:41.366564 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1449 13:58:41.377769 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1450 13:58:41.394547 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1451 13:58:41.405759 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1452 13:58:41.416934 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1453 13:58:41.428155 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1454 13:58:41.444945 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1455 13:58:41.456136 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1456 13:58:41.461692 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1457 13:58:41.472871 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1458 13:58:41.478480 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1459 13:58:41.489660 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1460 13:58:41.500901 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1461 13:58:41.506476 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1462 13:58:41.517668 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1463 13:58:41.523252 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1464 13:58:41.534453 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1465 13:58:41.540063 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1466 13:58:41.551244 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1467 13:58:41.556941 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1468 13:58:41.568051 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1469 13:58:41.579231 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1470 13:58:41.590430 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1471 13:58:41.596053 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1472 13:58:41.607179 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1473 13:58:41.618387 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1474 13:58:41.629572 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1475 13:58:41.635176 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1476 13:58:41.640787 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1477 13:58:41.646353 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1478 13:58:41.651943 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1479 13:58:41.657618 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1480 13:58:41.668763 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1481 13:58:41.674427 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1482 13:58:41.685547 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1483 13:58:41.691173 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1484 13:58:41.696745 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1485 13:58:41.707925 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1486 13:58:41.713548 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1487 13:58:41.724709 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1488 13:58:41.730309 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1489 13:58:41.741530 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1490 13:58:41.747140 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1491 13:58:41.758325 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1492 13:58:41.763947 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1493 13:58:41.769500 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1494 13:58:41.780696 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1495 13:58:41.786276 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1496 13:58:41.797442 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1497 13:58:41.803043 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1498 13:58:41.814262 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1499 13:58:41.819897 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1500 13:58:41.831043 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1501 13:58:41.836653 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1502 13:58:41.847844 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1503 13:58:41.853431 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1504 13:58:41.864627 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1505 13:58:41.870201 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1506 13:58:41.881491 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1507 13:58:41.887013 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1508 13:58:41.892595 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1509 13:58:41.903768 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1510 13:58:41.914988 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1511 13:58:41.926180 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1512 13:58:41.937349 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1513 13:58:41.948577 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1514 13:58:41.954168 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1515 13:58:41.965379 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1516 13:58:41.976503 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1517 13:58:41.987718 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1518 13:58:41.998963 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1519 13:58:42.004541 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1520 13:58:42.015720 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1521 13:58:42.021330 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1522 13:58:42.032499 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1523 13:58:42.038132 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1524 13:58:42.049295 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1525 13:58:42.054919 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1526 13:58:42.066060 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1527 13:58:42.071673 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1528 13:58:42.082852 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1529 13:58:42.088498 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1530 13:58:42.099649 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1531 13:58:42.105256 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1532 13:58:42.116423 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1533 13:58:42.122033 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1534 13:58:42.127619 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1535 13:58:42.138809 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1536 13:58:42.144433 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1537 13:58:42.155592 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1538 13:58:42.161206 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1539 13:58:42.172388 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1540 13:58:42.178006 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1541 13:58:42.183599 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1542 13:58:42.189221 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1543 13:58:42.200396 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1544 13:58:42.206040 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1545 13:58:42.217159 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1546 13:58:42.222785 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1547 13:58:42.234014 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1548 13:58:42.245146 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1549 13:58:42.256333 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1550 13:58:42.261947 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1551 13:58:42.273200 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1552 13:58:42.284368 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1553 13:58:42.290044 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1554 13:58:42.295566 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1555 13:58:42.301152 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1556 13:58:42.306789 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1557 13:58:42.312376 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1558 13:58:42.318038 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1559 13:58:42.329169 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1560 13:58:42.329625 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1561 13:58:42.340367 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1562 13:58:42.346049 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1563 13:58:42.351598 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1564 13:58:42.357170 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1565 13:58:42.362794 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1566 13:58:42.368383 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1567 13:58:42.374037 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1568 13:58:42.379649 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1569 13:58:42.385180 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1570 13:58:42.390784 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1571 13:58:42.396421 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1572 13:58:42.402079 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1573 13:58:42.407572 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1574 13:58:42.413198 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1575 13:58:42.418779 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1576 13:58:42.424356 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1577 13:58:42.430074 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1578 13:58:42.435589 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1579 13:58:42.441221 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1580 13:58:42.446803 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1581 13:58:42.452450 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1582 13:58:42.458049 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1583 13:58:42.463630 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1584 13:58:42.469237 dt_test_unprobed_devices_sh_opp-table skip
1585 13:58:42.469714 dt_test_unprobed_devices_sh_soc skip
1586 13:58:42.474821 dt_test_unprobed_devices_sh_sound pass
1587 13:58:42.480385 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1588 13:58:42.486068 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1589 13:58:42.491619 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1590 13:58:42.497219 dt_test_unprobed_devices_sh fail
1591 13:58:42.502881 + ../../utils/send-to-lava.sh ./output/result.txt
1592 13:58:42.507560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1593 13:58:42.508497 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1595 13:58:42.521095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1596 13:58:42.521783 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1598 13:58:42.607157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1599 13:58:42.607937 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1601 13:58:42.700390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1602 13:58:42.701167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1604 13:58:42.789375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1605 13:58:42.790161 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1607 13:58:42.883046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1608 13:58:42.883812 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1610 13:58:42.967817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1611 13:58:42.968551 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1613 13:58:43.057613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1614 13:58:43.058302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1616 13:58:43.142258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1617 13:58:43.142949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1619 13:58:43.234502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1620 13:58:43.235245 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1622 13:58:43.322834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1623 13:58:43.323555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1625 13:58:43.412625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1626 13:58:43.413317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1628 13:58:43.508088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1629 13:58:43.508778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1631 13:58:43.594780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1632 13:58:43.595475 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1634 13:58:43.684208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1635 13:58:43.684951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1637 13:58:43.777098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1638 13:58:43.777879 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1640 13:58:43.865491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1641 13:58:43.866241 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1643 13:58:43.955112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1644 13:58:43.955840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1646 13:58:44.046511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1647 13:58:44.047209 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1649 13:58:44.132102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1650 13:58:44.132867 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1652 13:58:44.223189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1653 13:58:44.224036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1655 13:58:44.314193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1656 13:58:44.314981 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1658 13:58:44.400173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1659 13:58:44.400915 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1661 13:58:44.490668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1662 13:58:44.491378 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1664 13:58:44.577599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1665 13:58:44.578299 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1667 13:58:44.668058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1668 13:58:44.668786 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1670 13:58:44.752739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1671 13:58:44.753428 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1673 13:58:44.844438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1674 13:58:44.845130 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1676 13:58:44.935662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1677 13:58:44.936507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1679 13:58:45.027197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1680 13:58:45.027912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1682 13:58:45.111857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1683 13:58:45.112602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1685 13:58:45.198998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1686 13:58:45.199697 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1688 13:58:45.289138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1689 13:58:45.289849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1691 13:58:45.375644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1692 13:58:45.376462 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1694 13:58:45.465163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1695 13:58:45.465903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1697 13:58:45.558063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1698 13:58:45.558847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1700 13:58:45.648308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1701 13:58:45.649022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1703 13:58:45.736223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1704 13:58:45.736960 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1706 13:58:45.826752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1707 13:58:45.827514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1709 13:58:45.917617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1710 13:58:45.918351 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1712 13:58:46.003226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1713 13:58:46.003939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1715 13:58:46.094082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1716 13:58:46.094789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1718 13:58:46.187092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1719 13:58:46.187789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1721 13:58:46.278821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1722 13:58:46.279514 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1724 13:58:46.364828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1725 13:58:46.365536 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1727 13:58:46.456655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1728 13:58:46.457369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1730 13:58:46.545712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1731 13:58:46.546419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1733 13:58:46.639130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1734 13:58:46.639883 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1736 13:58:46.729695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1737 13:58:46.730509 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1739 13:58:46.816607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1740 13:58:46.817349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1742 13:58:46.906426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1743 13:58:46.907160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1745 13:58:46.997214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1746 13:58:46.997948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1748 13:58:47.087411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1749 13:58:47.088156 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1751 13:58:47.178303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1752 13:58:47.179025 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1754 13:58:47.270592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1755 13:58:47.271326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1757 13:58:47.357932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1758 13:58:47.358726 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1760 13:58:47.447949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1761 13:58:47.448730 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1763 13:58:47.538029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1764 13:58:47.538759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1766 13:58:47.622544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1767 13:58:47.623289 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1769 13:58:47.713676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1770 13:58:47.714448 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1772 13:58:47.804277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1773 13:58:47.805020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1775 13:58:47.894680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1776 13:58:47.895434 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1778 13:58:47.984579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1779 13:58:47.985325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1781 13:58:48.070403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1782 13:58:48.071141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1784 13:58:48.163446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1785 13:58:48.164179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1787 13:58:48.255500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1788 13:58:48.256258 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1790 13:58:48.346870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1791 13:58:48.347641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1793 13:58:48.433308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1794 13:58:48.434056 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1796 13:58:48.519177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1797 13:58:48.519912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1799 13:58:48.611132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1800 13:58:48.611885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1802 13:58:48.698066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1803 13:58:48.698854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1805 13:58:48.784431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1806 13:58:48.785179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1808 13:58:48.876759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1809 13:58:48.877498 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1811 13:58:48.967155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1812 13:58:48.967899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1814 13:58:49.058258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1815 13:58:49.058989 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1817 13:58:49.144215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1818 13:58:49.144940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1820 13:58:49.237913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1821 13:58:49.238619 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1823 13:58:49.328354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1824 13:58:49.329135 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1826 13:58:49.419627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1827 13:58:49.420418 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1829 13:58:49.506599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1830 13:58:49.507296 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1832 13:58:49.597634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1833 13:58:49.598335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1835 13:58:49.688927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1836 13:58:49.689663 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1838 13:58:49.776124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1839 13:58:49.776816 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1841 13:58:49.865875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1842 13:58:49.866578 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1844 13:58:49.959367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1845 13:58:49.960103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1847 13:58:50.045870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1848 13:58:50.046570 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1850 13:58:50.137404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1851 13:58:50.138089 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1853 13:58:50.228556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1854 13:58:50.229245 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1856 13:58:50.314535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1857 13:58:50.315235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1859 13:58:50.406911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1860 13:58:50.407664 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1862 13:58:50.498443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1863 13:58:50.499137 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1865 13:58:50.581747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1866 13:58:50.582474 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1868 13:58:50.675019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1869 13:58:50.675740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1871 13:58:50.761162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1872 13:58:50.761851 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1874 13:58:50.854934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1875 13:58:50.855628 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1877 13:58:50.944030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1878 13:58:50.944735 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1880 13:58:51.037338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1881 13:58:51.038030 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1883 13:58:51.127952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1884 13:58:51.128688 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1886 13:58:51.225509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1887 13:58:51.226208 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1889 13:58:51.315884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1890 13:58:51.316628 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1892 13:58:51.407791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1893 13:58:51.408526 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1895 13:58:51.499314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1896 13:58:51.500039 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1898 13:58:51.584873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1899 13:58:51.585567 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1901 13:58:51.676561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1902 13:58:51.677277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1904 13:58:51.765571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1905 13:58:51.766275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1907 13:58:51.856729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1908 13:58:51.857416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1910 13:58:51.947144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1911 13:58:51.947843 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1913 13:58:52.035952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1914 13:58:52.036672 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1916 13:58:52.129904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1917 13:58:52.130606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1919 13:58:52.221384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1920 13:58:52.222076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1922 13:58:52.307704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1923 13:58:52.308462 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1925 13:58:52.399045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1926 13:58:52.399739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1928 13:58:52.490422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1929 13:58:52.491185 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1931 13:58:52.578606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1932 13:58:52.579325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1934 13:58:52.667887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1935 13:58:52.668636 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1937 13:58:52.759694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1938 13:58:52.760495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1940 13:58:52.848729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1941 13:58:52.849421 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1943 13:58:52.938854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1944 13:58:52.939549 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1946 13:58:53.030075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1947 13:58:53.030769 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1949 13:58:53.115969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1950 13:58:53.116705 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1952 13:58:53.206873 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1954 13:58:53.209948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1955 13:58:53.300988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1957 13:58:53.304135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1958 13:58:53.387361 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1960 13:58:53.390387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1961 13:58:53.473500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1962 13:58:53.474190 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1964 13:58:53.565103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1965 13:58:53.565811 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1967 13:58:53.654764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1968 13:58:53.655450 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1970 13:58:53.746490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1971 13:58:53.747213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1973 13:58:53.830831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1974 13:58:53.831521 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1976 13:58:53.923772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1977 13:58:53.924504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1979 13:58:54.014369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1980 13:58:54.015051 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1982 13:58:54.105518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1983 13:58:54.106213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1985 13:58:54.190441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1986 13:58:54.191132 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1988 13:58:54.277568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1989 13:58:54.278256 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1991 13:58:54.368529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1992 13:58:54.369227 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1994 13:58:54.455365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1995 13:58:54.456060 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1997 13:58:54.544966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1998 13:58:54.545660 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2000 13:58:54.636588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2001 13:58:54.637273 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2003 13:58:54.725491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2004 13:58:54.726220 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2006 13:58:54.818873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2007 13:58:54.819564 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2009 13:58:54.908384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2010 13:58:54.909078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2012 13:58:54.995294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2013 13:58:54.996031 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2015 13:58:55.087151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2016 13:58:55.087850 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2018 13:58:55.178011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2019 13:58:55.178706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2021 13:58:55.263547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2022 13:58:55.264266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2024 13:58:55.350240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2025 13:58:55.350934 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2027 13:58:55.442263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2028 13:58:55.443008 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2030 13:58:55.527265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2031 13:58:55.527946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2033 13:58:55.621707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2034 13:58:55.622439 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2036 13:58:55.716106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2037 13:58:55.716824 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2039 13:58:55.803906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2040 13:58:55.804641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2042 13:58:55.892378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2043 13:58:55.893063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2045 13:58:55.983837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2046 13:58:55.984577 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2048 13:58:56.074181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2049 13:58:56.074867 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2051 13:58:56.160502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2052 13:58:56.161191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2054 13:58:56.253401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2055 13:58:56.254084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2057 13:58:56.344320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2058 13:58:56.345024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2060 13:58:56.430584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2061 13:58:56.431277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2063 13:58:56.515312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2064 13:58:56.516016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2066 13:58:56.606854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2067 13:58:56.607562 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2069 13:58:56.692452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2070 13:58:56.693180 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2072 13:58:56.784740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2073 13:58:56.785437 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2075 13:58:56.874930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2076 13:58:56.875620 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2078 13:58:56.966949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2079 13:58:56.967684 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2081 13:58:57.052368 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2082 13:58:57.053064 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2084 13:58:57.144417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2085 13:58:57.145103 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2087 13:58:57.234927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2088 13:58:57.235615 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2090 13:58:57.321179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2091 13:58:57.321881 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2093 13:58:57.411633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2094 13:58:57.412370 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2096 13:58:57.503974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2097 13:58:57.504685 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2099 13:58:57.594910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2100 13:58:57.595624 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2102 13:58:57.687676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2103 13:58:57.688443 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2105 13:58:57.773454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2106 13:58:57.774156 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2108 13:58:57.865919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2109 13:58:57.866616 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2111 13:58:57.955393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2112 13:58:57.956105 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2114 13:58:58.041614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2115 13:58:58.042306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2117 13:58:58.132561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2118 13:58:58.133255 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2120 13:58:58.225475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2121 13:58:58.226172 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2123 13:58:58.310730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2124 13:58:58.311418 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2126 13:58:58.403776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2127 13:58:58.404519 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2129 13:58:58.495930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2130 13:58:58.496696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2132 13:58:58.586013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2133 13:58:58.586715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2135 13:58:58.677703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2136 13:58:58.678446 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2138 13:58:58.761980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2139 13:58:58.762555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2141 13:58:58.848720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2142 13:58:58.849319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2144 13:58:58.938251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2145 13:58:58.938822 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2147 13:58:59.025269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2148 13:58:59.025865 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2150 13:58:59.115251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2151 13:58:59.115880 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2153 13:58:59.258014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2154 13:58:59.258649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2156 13:58:59.357022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2157 13:58:59.357543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2159 13:58:59.448409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2160 13:58:59.449141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2162 13:58:59.533847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2163 13:58:59.534555 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2165 13:58:59.624725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2166 13:58:59.625432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2168 13:58:59.714867 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2169 13:58:59.715598 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2171 13:58:59.800581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2172 13:58:59.801289 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2174 13:58:59.890679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2175 13:58:59.891374 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2177 13:58:59.981434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2178 13:58:59.982154 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2180 13:59:00.072380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2181 13:59:00.073076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2183 13:59:00.164496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2184 13:59:00.165209 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2186 13:59:00.252857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2187 13:59:00.253553 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2189 13:59:00.343525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2190 13:59:00.344251 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2192 13:59:00.435647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2193 13:59:00.436381 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2195 13:59:00.524589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2196 13:59:00.525332 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2198 13:59:00.614050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2199 13:59:00.614727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2201 13:59:00.704271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2202 13:59:00.704978 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2204 13:59:00.795372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2205 13:59:00.796100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2207 13:59:00.879815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2208 13:59:00.880548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2210 13:59:00.970846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2211 13:59:00.971612 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2213 13:59:01.064483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2214 13:59:01.065268 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2216 13:59:01.154123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2217 13:59:01.154862 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2219 13:59:01.243672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2220 13:59:01.244548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2222 13:59:01.328627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2223 13:59:01.329412 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2225 13:59:01.422357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2226 13:59:01.423071 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2228 13:59:01.514655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2229 13:59:01.515346 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2231 13:59:01.607752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2232 13:59:01.608518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2234 13:59:01.697201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2235 13:59:01.697933 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2237 13:59:01.784053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2238 13:59:01.784747 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2240 13:59:01.876211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2241 13:59:01.876903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2243 13:59:01.969022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2244 13:59:01.969721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2246 13:59:02.053047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2247 13:59:02.053749 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2249 13:59:02.145092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2250 13:59:02.145789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2252 13:59:02.237034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2253 13:59:02.237726 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2255 13:59:02.321043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2256 13:59:02.321730 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2258 13:59:02.413647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2259 13:59:02.414343 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2261 13:59:02.505889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2262 13:59:02.506586 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2264 13:59:02.591811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2265 13:59:02.592548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2267 13:59:02.678480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2268 13:59:02.679177 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2270 13:59:02.771767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2271 13:59:02.772527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2273 13:59:02.860472 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2275 13:59:02.863568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2276 13:59:02.950982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2277 13:59:02.951671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2279 13:59:03.038188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2280 13:59:03.038871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2282 13:59:03.123887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2283 13:59:03.124630 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2285 13:59:03.216842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2286 13:59:03.217548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2288 13:59:03.309146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2289 13:59:03.309838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2291 13:59:03.401750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2292 13:59:03.402448 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2294 13:59:03.490303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2295 13:59:03.491010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2297 13:59:03.582288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2298 13:59:03.582996 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2300 13:59:03.673904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2301 13:59:03.674595 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2303 13:59:03.760500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2304 13:59:03.761239 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2306 13:59:03.851134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2307 13:59:03.851826 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2309 13:59:03.941706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2310 13:59:03.942399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2312 13:59:04.027324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2313 13:59:04.028050 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2315 13:59:04.117369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2316 13:59:04.118062 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2318 13:59:04.203528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2319 13:59:04.204216 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2321 13:59:04.294153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2322 13:59:04.294839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2324 13:59:04.380408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2325 13:59:04.381098 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2327 13:59:04.470816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2328 13:59:04.471506 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2330 13:59:04.561332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2331 13:59:04.562017 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2333 13:59:04.648322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2334 13:59:04.649010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2336 13:59:04.733214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2337 13:59:04.733935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2339 13:59:04.820212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2340 13:59:04.820897 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2342 13:59:04.910073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2343 13:59:04.910765 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2345 13:59:05.001541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2346 13:59:05.002237 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2348 13:59:05.085394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2349 13:59:05.086079 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2351 13:59:05.170404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2352 13:59:05.171084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2354 13:59:05.255746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2355 13:59:05.256457 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2357 13:59:05.348416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2358 13:59:05.349099 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2360 13:59:05.435972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2361 13:59:05.436708 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2363 13:59:05.527820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2364 13:59:05.528584 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2366 13:59:05.611040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2367 13:59:05.611487 + set +x
2368 13:59:05.612123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2370 13:59:05.619809 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 934132_1.6.2.4.5>
2371 13:59:05.620279 <LAVA_TEST_RUNNER EXIT>
2372 13:59:05.620911 Received signal: <ENDRUN> 1_kselftest-dt 934132_1.6.2.4.5
2373 13:59:05.621341 Ending use of test pattern.
2374 13:59:05.621731 Ending test lava.1_kselftest-dt (934132_1.6.2.4.5), duration 82.40
2376 13:59:05.623189 ok: lava_test_shell seems to have completed
2377 13:59:05.635937 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2378 13:59:05.637816 end: 3.1 lava-test-shell (duration 00:01:24) [common]
2379 13:59:05.638351 end: 3 lava-test-retry (duration 00:01:24) [common]
2380 13:59:05.638885 start: 4 finalize (timeout 00:05:35) [common]
2381 13:59:05.639424 start: 4.1 power-off (timeout 00:00:30) [common]
2382 13:59:05.640444 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-01'
2383 13:59:05.675671 >> OK - accepted request
2384 13:59:05.677816 Returned 0 in 0 seconds
2385 13:59:05.778904 end: 4.1 power-off (duration 00:00:00) [common]
2387 13:59:05.780605 start: 4.2 read-feedback (timeout 00:05:35) [common]
2388 13:59:05.781707 Listened to connection for namespace 'common' for up to 1s
2389 13:59:05.782565 Listened to connection for namespace 'common' for up to 1s
2390 13:59:06.782429 Finalising connection for namespace 'common'
2391 13:59:06.783049 Disconnecting from shell: Finalise
2392 13:59:06.783555 / #
2393 13:59:06.884478 end: 4.2 read-feedback (duration 00:00:01) [common]
2394 13:59:06.885106 end: 4 finalize (duration 00:00:01) [common]
2395 13:59:06.885763 Cleaning after the job
2396 13:59:06.886352 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/934132/tftp-deploy-abofgn5v/ramdisk
2397 13:59:06.895776 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/934132/tftp-deploy-abofgn5v/kernel
2398 13:59:06.903019 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/934132/tftp-deploy-abofgn5v/dtb
2399 13:59:06.904249 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/934132/tftp-deploy-abofgn5v/nfsrootfs
2400 13:59:07.045107 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/934132/tftp-deploy-abofgn5v/modules
2401 13:59:07.053731 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/934132
2402 13:59:09.923275 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/934132
2403 13:59:09.923865 Job finished correctly