Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 14:00:42.730304 lava-dispatcher, installed at version: 2024.01
2 14:00:42.731083 start: 0 validate
3 14:00:42.731570 Start time: 2024-11-04 14:00:42.731540+00:00 (UTC)
4 14:00:42.732136 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 14:00:42.732705 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 14:00:42.771151 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 14:00:42.771682 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-84-ge231ee35020e%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 14:00:42.801572 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 14:00:42.802248 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-84-ge231ee35020e%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 14:00:43.854060 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 14:00:43.854708 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-84-ge231ee35020e%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 14:00:43.894927 validate duration: 1.16
14 14:00:43.895819 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 14:00:43.896191 start: 1.1 download-retry (timeout 00:10:00) [common]
16 14:00:43.896504 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 14:00:43.897101 Not decompressing ramdisk as can be used compressed.
18 14:00:43.897550 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 14:00:43.897795 saving as /var/lib/lava/dispatcher/tmp/934199/tftp-deploy-i29qaq55/ramdisk/rootfs.cpio.gz
20 14:00:43.898056 total size: 8181887 (7 MB)
21 14:00:43.936327 progress 0 % (0 MB)
22 14:00:43.943010 progress 5 % (0 MB)
23 14:00:43.950751 progress 10 % (0 MB)
24 14:00:43.958643 progress 15 % (1 MB)
25 14:00:43.965641 progress 20 % (1 MB)
26 14:00:43.972684 progress 25 % (1 MB)
27 14:00:43.979400 progress 30 % (2 MB)
28 14:00:43.985509 progress 35 % (2 MB)
29 14:00:43.991508 progress 40 % (3 MB)
30 14:00:43.997537 progress 45 % (3 MB)
31 14:00:44.003267 progress 50 % (3 MB)
32 14:00:44.009468 progress 55 % (4 MB)
33 14:00:44.015077 progress 60 % (4 MB)
34 14:00:44.021196 progress 65 % (5 MB)
35 14:00:44.026930 progress 70 % (5 MB)
36 14:00:44.033104 progress 75 % (5 MB)
37 14:00:44.038718 progress 80 % (6 MB)
38 14:00:44.044704 progress 85 % (6 MB)
39 14:00:44.050325 progress 90 % (7 MB)
40 14:00:44.056292 progress 95 % (7 MB)
41 14:00:44.061372 progress 100 % (7 MB)
42 14:00:44.062098 7 MB downloaded in 0.16 s (47.57 MB/s)
43 14:00:44.062695 end: 1.1.1 http-download (duration 00:00:00) [common]
45 14:00:44.063658 end: 1.1 download-retry (duration 00:00:00) [common]
46 14:00:44.064015 start: 1.2 download-retry (timeout 00:10:00) [common]
47 14:00:44.064333 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 14:00:44.064835 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-84-ge231ee35020e/arm64/defconfig/gcc-12/kernel/Image
49 14:00:44.065110 saving as /var/lib/lava/dispatcher/tmp/934199/tftp-deploy-i29qaq55/kernel/Image
50 14:00:44.065330 total size: 45713920 (43 MB)
51 14:00:44.065552 No compression specified
52 14:00:44.102937 progress 0 % (0 MB)
53 14:00:44.132846 progress 5 % (2 MB)
54 14:00:44.163159 progress 10 % (4 MB)
55 14:00:44.193079 progress 15 % (6 MB)
56 14:00:44.222115 progress 20 % (8 MB)
57 14:00:44.250711 progress 25 % (10 MB)
58 14:00:44.280904 progress 30 % (13 MB)
59 14:00:44.310482 progress 35 % (15 MB)
60 14:00:44.339561 progress 40 % (17 MB)
61 14:00:44.368276 progress 45 % (19 MB)
62 14:00:44.397224 progress 50 % (21 MB)
63 14:00:44.425910 progress 55 % (24 MB)
64 14:00:44.454847 progress 60 % (26 MB)
65 14:00:44.483580 progress 65 % (28 MB)
66 14:00:44.512588 progress 70 % (30 MB)
67 14:00:44.541642 progress 75 % (32 MB)
68 14:00:44.571527 progress 80 % (34 MB)
69 14:00:44.601451 progress 85 % (37 MB)
70 14:00:44.630690 progress 90 % (39 MB)
71 14:00:44.660298 progress 95 % (41 MB)
72 14:00:44.689374 progress 100 % (43 MB)
73 14:00:44.689944 43 MB downloaded in 0.62 s (69.80 MB/s)
74 14:00:44.690426 end: 1.2.1 http-download (duration 00:00:01) [common]
76 14:00:44.691243 end: 1.2 download-retry (duration 00:00:01) [common]
77 14:00:44.691516 start: 1.3 download-retry (timeout 00:09:59) [common]
78 14:00:44.691779 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 14:00:44.692260 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-84-ge231ee35020e/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 14:00:44.692536 saving as /var/lib/lava/dispatcher/tmp/934199/tftp-deploy-i29qaq55/dtb/meson-g12b-a311d-libretech-cc.dtb
81 14:00:44.692746 total size: 54703 (0 MB)
82 14:00:44.692957 No compression specified
83 14:00:44.727349 progress 59 % (0 MB)
84 14:00:44.729777 progress 100 % (0 MB)
85 14:00:44.730567 0 MB downloaded in 0.04 s (1.38 MB/s)
86 14:00:44.731202 end: 1.3.1 http-download (duration 00:00:00) [common]
88 14:00:44.732345 end: 1.3 download-retry (duration 00:00:00) [common]
89 14:00:44.732718 start: 1.4 download-retry (timeout 00:09:59) [common]
90 14:00:44.733093 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 14:00:44.733689 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-84-ge231ee35020e/arm64/defconfig/gcc-12/modules.tar.xz
92 14:00:44.734029 saving as /var/lib/lava/dispatcher/tmp/934199/tftp-deploy-i29qaq55/modules/modules.tar
93 14:00:44.734342 total size: 11613396 (11 MB)
94 14:00:44.734634 Using unxz to decompress xz
95 14:00:44.775225 progress 0 % (0 MB)
96 14:00:44.854235 progress 5 % (0 MB)
97 14:00:44.935294 progress 10 % (1 MB)
98 14:00:45.035591 progress 15 % (1 MB)
99 14:00:45.135697 progress 20 % (2 MB)
100 14:00:45.216418 progress 25 % (2 MB)
101 14:00:45.294075 progress 30 % (3 MB)
102 14:00:45.374454 progress 35 % (3 MB)
103 14:00:45.448740 progress 40 % (4 MB)
104 14:00:45.526707 progress 45 % (5 MB)
105 14:00:45.614798 progress 50 % (5 MB)
106 14:00:45.694841 progress 55 % (6 MB)
107 14:00:45.782784 progress 60 % (6 MB)
108 14:00:45.866214 progress 65 % (7 MB)
109 14:00:45.949733 progress 70 % (7 MB)
110 14:00:46.028924 progress 75 % (8 MB)
111 14:00:46.114676 progress 80 % (8 MB)
112 14:00:46.196309 progress 85 % (9 MB)
113 14:00:46.277461 progress 90 % (9 MB)
114 14:00:46.358485 progress 95 % (10 MB)
115 14:00:46.437286 progress 100 % (11 MB)
116 14:00:46.449249 11 MB downloaded in 1.71 s (6.46 MB/s)
117 14:00:46.449918 end: 1.4.1 http-download (duration 00:00:02) [common]
119 14:00:46.450742 end: 1.4 download-retry (duration 00:00:02) [common]
120 14:00:46.451015 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 14:00:46.451283 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 14:00:46.451533 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 14:00:46.451789 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 14:00:46.452804 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr
125 14:00:46.454430 makedir: /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin
126 14:00:46.455211 makedir: /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/tests
127 14:00:46.455923 makedir: /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/results
128 14:00:46.456670 Creating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin/lava-add-keys
129 14:00:46.457770 Creating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin/lava-add-sources
130 14:00:46.458861 Creating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin/lava-background-process-start
131 14:00:46.460022 Creating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin/lava-background-process-stop
132 14:00:46.461703 Creating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin/lava-common-functions
133 14:00:46.462875 Creating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin/lava-echo-ipv4
134 14:00:46.463567 Creating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin/lava-install-packages
135 14:00:46.464565 Creating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin/lava-installed-packages
136 14:00:46.466931 Creating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin/lava-os-build
137 14:00:46.467714 Creating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin/lava-probe-channel
138 14:00:46.468544 Creating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin/lava-probe-ip
139 14:00:46.469151 Creating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin/lava-target-ip
140 14:00:46.469740 Creating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin/lava-target-mac
141 14:00:46.470332 Creating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin/lava-target-storage
142 14:00:46.470928 Creating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin/lava-test-case
143 14:00:46.471520 Creating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin/lava-test-event
144 14:00:46.478740 Creating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin/lava-test-feedback
145 14:00:46.492408 Creating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin/lava-test-raise
146 14:00:46.493245 Creating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin/lava-test-reference
147 14:00:46.493885 Creating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin/lava-test-runner
148 14:00:46.494507 Creating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin/lava-test-set
149 14:00:46.495063 Creating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin/lava-test-shell
150 14:00:46.495661 Updating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin/lava-install-packages (oe)
151 14:00:46.500992 Updating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/bin/lava-installed-packages (oe)
152 14:00:46.502713 Creating /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/environment
153 14:00:46.503297 LAVA metadata
154 14:00:46.503591 - LAVA_JOB_ID=934199
155 14:00:46.503825 - LAVA_DISPATCHER_IP=192.168.6.2
156 14:00:46.504287 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 14:00:46.505458 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 14:00:46.505829 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 14:00:46.506063 skipped lava-vland-overlay
160 14:00:46.506381 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 14:00:46.506665 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 14:00:46.506891 skipped lava-multinode-overlay
163 14:00:46.507146 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 14:00:46.507420 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 14:00:46.507683 Loading test definitions
166 14:00:46.507970 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 14:00:46.508235 Using /lava-934199 at stage 0
168 14:00:46.509552 uuid=934199_1.5.2.4.1 testdef=None
169 14:00:46.509900 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 14:00:46.510171 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 14:00:46.512063 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 14:00:46.512957 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 14:00:46.515514 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 14:00:46.516534 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 14:00:46.519184 runner path: /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/0/tests/0_dmesg test_uuid 934199_1.5.2.4.1
178 14:00:46.519944 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 14:00:46.520858 Creating lava-test-runner.conf files
181 14:00:46.521100 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/934199/lava-overlay-b7sdchmr/lava-934199/0 for stage 0
182 14:00:46.521534 - 0_dmesg
183 14:00:46.521989 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 14:00:46.522327 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 14:00:46.553016 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 14:00:46.553505 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 14:00:46.553773 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 14:00:46.554041 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 14:00:46.554306 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 14:00:47.698655 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 14:00:47.699154 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 14:00:47.699425 extracting modules file /var/lib/lava/dispatcher/tmp/934199/tftp-deploy-i29qaq55/modules/modules.tar to /var/lib/lava/dispatcher/tmp/934199/extract-overlay-ramdisk-5kf10n_l/ramdisk
193 14:00:49.666453 end: 1.5.4 extract-modules (duration 00:00:02) [common]
194 14:00:49.666948 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
195 14:00:49.667239 [common] Applying overlay /var/lib/lava/dispatcher/tmp/934199/compress-overlay-tuemo19b/overlay-1.5.2.5.tar.gz to ramdisk
196 14:00:49.667463 [common] Applying overlay /var/lib/lava/dispatcher/tmp/934199/compress-overlay-tuemo19b/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/934199/extract-overlay-ramdisk-5kf10n_l/ramdisk
197 14:00:49.700761 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 14:00:49.701230 start: 1.5.6 prepare-kernel (timeout 00:09:54) [common]
199 14:00:49.701508 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:54) [common]
200 14:00:49.701744 Converting downloaded kernel to a uImage
201 14:00:49.702065 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/934199/tftp-deploy-i29qaq55/kernel/Image /var/lib/lava/dispatcher/tmp/934199/tftp-deploy-i29qaq55/kernel/uImage
202 14:00:50.201666 output: Image Name:
203 14:00:50.202089 output: Created: Mon Nov 4 14:00:49 2024
204 14:00:50.202299 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 14:00:50.202501 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 14:00:50.202700 output: Load Address: 01080000
207 14:00:50.202895 output: Entry Point: 01080000
208 14:00:50.203090 output:
209 14:00:50.203418 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
210 14:00:50.203685 end: 1.5.6 prepare-kernel (duration 00:00:01) [common]
211 14:00:50.203952 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 14:00:50.204253 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 14:00:50.204515 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 14:00:50.204772 Building ramdisk /var/lib/lava/dispatcher/tmp/934199/extract-overlay-ramdisk-5kf10n_l/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/934199/extract-overlay-ramdisk-5kf10n_l/ramdisk
215 14:00:52.653860 >> 181606 blocks
216 14:01:01.103835 Adding RAMdisk u-boot header.
217 14:01:01.104293 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/934199/extract-overlay-ramdisk-5kf10n_l/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/934199/extract-overlay-ramdisk-5kf10n_l/ramdisk.cpio.gz.uboot
218 14:01:01.441898 output: Image Name:
219 14:01:01.442308 output: Created: Mon Nov 4 14:01:01 2024
220 14:01:01.442517 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 14:01:01.442729 output: Data Size: 26061571 Bytes = 25450.75 KiB = 24.85 MiB
222 14:01:01.442931 output: Load Address: 00000000
223 14:01:01.443129 output: Entry Point: 00000000
224 14:01:01.443324 output:
225 14:01:01.444027 rename /var/lib/lava/dispatcher/tmp/934199/extract-overlay-ramdisk-5kf10n_l/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/934199/tftp-deploy-i29qaq55/ramdisk/ramdisk.cpio.gz.uboot
226 14:01:01.444752 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 14:01:01.445285 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 14:01:01.445802 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
229 14:01:01.446251 No LXC device requested
230 14:01:01.446746 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 14:01:01.447247 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
232 14:01:01.447731 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 14:01:01.448170 Checking files for TFTP limit of 4294967296 bytes.
234 14:01:01.450796 end: 1 tftp-deploy (duration 00:00:18) [common]
235 14:01:01.451359 start: 2 uboot-action (timeout 00:05:00) [common]
236 14:01:01.451871 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 14:01:01.452410 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 14:01:01.452908 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 14:01:01.453433 Using kernel file from prepare-kernel: 934199/tftp-deploy-i29qaq55/kernel/uImage
240 14:01:01.454052 substitutions:
241 14:01:01.454463 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 14:01:01.454864 - {DTB_ADDR}: 0x01070000
243 14:01:01.455257 - {DTB}: 934199/tftp-deploy-i29qaq55/dtb/meson-g12b-a311d-libretech-cc.dtb
244 14:01:01.455655 - {INITRD}: 934199/tftp-deploy-i29qaq55/ramdisk/ramdisk.cpio.gz.uboot
245 14:01:01.456080 - {KERNEL_ADDR}: 0x01080000
246 14:01:01.456478 - {KERNEL}: 934199/tftp-deploy-i29qaq55/kernel/uImage
247 14:01:01.456873 - {LAVA_MAC}: None
248 14:01:01.457302 - {PRESEED_CONFIG}: None
249 14:01:01.457693 - {PRESEED_LOCAL}: None
250 14:01:01.458079 - {RAMDISK_ADDR}: 0x08000000
251 14:01:01.458464 - {RAMDISK}: 934199/tftp-deploy-i29qaq55/ramdisk/ramdisk.cpio.gz.uboot
252 14:01:01.458857 - {ROOT_PART}: None
253 14:01:01.459245 - {ROOT}: None
254 14:01:01.459631 - {SERVER_IP}: 192.168.6.2
255 14:01:01.460050 - {TEE_ADDR}: 0x83000000
256 14:01:01.460447 - {TEE}: None
257 14:01:01.460835 Parsed boot commands:
258 14:01:01.461213 - setenv autoload no
259 14:01:01.461598 - setenv initrd_high 0xffffffff
260 14:01:01.461985 - setenv fdt_high 0xffffffff
261 14:01:01.462370 - dhcp
262 14:01:01.462757 - setenv serverip 192.168.6.2
263 14:01:01.463141 - tftpboot 0x01080000 934199/tftp-deploy-i29qaq55/kernel/uImage
264 14:01:01.463526 - tftpboot 0x08000000 934199/tftp-deploy-i29qaq55/ramdisk/ramdisk.cpio.gz.uboot
265 14:01:01.463911 - tftpboot 0x01070000 934199/tftp-deploy-i29qaq55/dtb/meson-g12b-a311d-libretech-cc.dtb
266 14:01:01.464322 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 14:01:01.464715 - bootm 0x01080000 0x08000000 0x01070000
268 14:01:01.465208 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 14:01:01.466674 start: 2.3 connect-device (timeout 00:05:00) [common]
271 14:01:01.467113 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 14:01:01.480739 Setting prompt string to ['lava-test: # ']
273 14:01:01.482181 end: 2.3 connect-device (duration 00:00:00) [common]
274 14:01:01.482768 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 14:01:01.483303 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 14:01:01.483816 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 14:01:01.485002 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 14:01:01.521106 >> OK - accepted request
279 14:01:01.523601 Returned 0 in 0 seconds
280 14:01:01.625161 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 14:01:01.627358 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 14:01:01.628160 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 14:01:01.628844 Setting prompt string to ['Hit any key to stop autoboot']
285 14:01:01.629441 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 14:01:01.631462 Trying 192.168.56.21...
287 14:01:01.632118 Connected to conserv1.
288 14:01:01.632668 Escape character is '^]'.
289 14:01:01.633224
290 14:01:01.633788 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 14:01:01.634349
292 14:01:13.250649 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
293 14:01:13.251502 bl2_stage_init 0x81
294 14:01:13.256206 hw id: 0x0000 - pwm id 0x01
295 14:01:13.256780 bl2_stage_init 0xc1
296 14:01:13.257239 bl2_stage_init 0x02
297 14:01:13.257632
298 14:01:13.261768 L0:00000000
299 14:01:13.262198 L1:20000703
300 14:01:13.262592 L2:00008067
301 14:01:13.262976 L3:14000000
302 14:01:13.263358 B2:00402000
303 14:01:13.267257 B1:e0f83180
304 14:01:13.267684
305 14:01:13.268106 TE: 58150
306 14:01:13.268498
307 14:01:13.273031 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
308 14:01:13.273457
309 14:01:13.273848 Board ID = 1
310 14:01:13.278458 Set A53 clk to 24M
311 14:01:13.278907 Set A73 clk to 24M
312 14:01:13.279296 Set clk81 to 24M
313 14:01:13.284201 A53 clk: 1200 MHz
314 14:01:13.284622 A73 clk: 1200 MHz
315 14:01:13.285007 CLK81: 166.6M
316 14:01:13.285387 smccc: 00012aab
317 14:01:13.289660 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
318 14:01:13.295256 board id: 1
319 14:01:13.301078 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
320 14:01:13.311901 fw parse done
321 14:01:13.317804 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
322 14:01:13.360405 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
323 14:01:13.371257 PIEI prepare done
324 14:01:13.371684 fastboot data load
325 14:01:13.372108 fastboot data verify
326 14:01:13.376902 verify result: 266
327 14:01:13.382494 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
328 14:01:13.382932 LPDDR4 probe
329 14:01:13.383321 ddr clk to 1584MHz
330 14:01:13.390464 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
331 14:01:13.427719
332 14:01:13.428281 dmc_version 0001
333 14:01:13.434399 Check phy result
334 14:01:13.440247 INFO : End of CA training
335 14:01:13.440674 INFO : End of initialization
336 14:01:13.445893 INFO : Training has run successfully!
337 14:01:13.446316 Check phy result
338 14:01:13.451479 INFO : End of initialization
339 14:01:13.451901 INFO : End of read enable training
340 14:01:13.457106 INFO : End of fine write leveling
341 14:01:13.462645 INFO : End of Write leveling coarse delay
342 14:01:13.463084 INFO : Training has run successfully!
343 14:01:13.463475 Check phy result
344 14:01:13.468243 INFO : End of initialization
345 14:01:13.468674 INFO : End of read dq deskew training
346 14:01:13.473865 INFO : End of MPR read delay center optimization
347 14:01:13.479467 INFO : End of write delay center optimization
348 14:01:13.485110 INFO : End of read delay center optimization
349 14:01:13.485541 INFO : End of max read latency training
350 14:01:13.490683 INFO : Training has run successfully!
351 14:01:13.491160 1D training succeed
352 14:01:13.499881 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
353 14:01:13.546750 Check phy result
354 14:01:13.547304 INFO : End of initialization
355 14:01:13.569989 INFO : End of 2D read delay Voltage center optimization
356 14:01:13.590014 INFO : End of 2D read delay Voltage center optimization
357 14:01:13.642059 INFO : End of 2D write delay Voltage center optimization
358 14:01:13.691435 INFO : End of 2D write delay Voltage center optimization
359 14:01:13.696764 INFO : Training has run successfully!
360 14:01:13.697241
361 14:01:13.697641 channel==0
362 14:01:13.702331 RxClkDly_Margin_A0==88 ps 9
363 14:01:13.702784 TxDqDly_Margin_A0==98 ps 10
364 14:01:13.707934 RxClkDly_Margin_A1==88 ps 9
365 14:01:13.708430 TxDqDly_Margin_A1==98 ps 10
366 14:01:13.708832 TrainedVREFDQ_A0==74
367 14:01:13.713580 TrainedVREFDQ_A1==74
368 14:01:13.714170 VrefDac_Margin_A0==25
369 14:01:13.714570 DeviceVref_Margin_A0==40
370 14:01:13.719147 VrefDac_Margin_A1==25
371 14:01:13.719612 DeviceVref_Margin_A1==40
372 14:01:13.720034
373 14:01:13.720438
374 14:01:13.724834 channel==1
375 14:01:13.725424 RxClkDly_Margin_A0==88 ps 9
376 14:01:13.725887 TxDqDly_Margin_A0==98 ps 10
377 14:01:13.730340 RxClkDly_Margin_A1==98 ps 10
378 14:01:13.730801 TxDqDly_Margin_A1==88 ps 9
379 14:01:13.735957 TrainedVREFDQ_A0==77
380 14:01:13.736462 TrainedVREFDQ_A1==77
381 14:01:13.736859 VrefDac_Margin_A0==23
382 14:01:13.741531 DeviceVref_Margin_A0==37
383 14:01:13.741980 VrefDac_Margin_A1==23
384 14:01:13.747124 DeviceVref_Margin_A1==37
385 14:01:13.747569
386 14:01:13.747961 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
387 14:01:13.748391
388 14:01:13.780879 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 0000001a 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
389 14:01:13.781493 2D training succeed
390 14:01:13.786482 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
391 14:01:13.792119 auto size-- 65535DDR cs0 size: 2048MB
392 14:01:13.792771 DDR cs1 size: 2048MB
393 14:01:13.797646 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
394 14:01:13.798241 cs0 DataBus test pass
395 14:01:13.803201 cs1 DataBus test pass
396 14:01:13.803795 cs0 AddrBus test pass
397 14:01:13.804345 cs1 AddrBus test pass
398 14:01:13.804859
399 14:01:13.808845 100bdlr_step_size ps== 420
400 14:01:13.809520 result report
401 14:01:13.814455 boot times 0Enable ddr reg access
402 14:01:13.819791 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
403 14:01:13.833819 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
404 14:01:14.405177 0.0;M3 CHK:0;cm4_sp_mode 0
405 14:01:14.405619 MVN_1=0x00000000
406 14:01:14.410695 MVN_2=0x00000000
407 14:01:14.416487 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
408 14:01:14.416878 OPS=0x10
409 14:01:14.417118 ring efuse init
410 14:01:14.417354 chipver efuse init
411 14:01:14.424868 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
412 14:01:14.425273 [0.018961 Inits done]
413 14:01:14.425518 secure task start!
414 14:01:14.431473 high task start!
415 14:01:14.431887 low task start!
416 14:01:14.432173 run into bl31
417 14:01:14.438973 NOTICE: BL31: v1.3(release):4fc40b1
418 14:01:14.446772 NOTICE: BL31: Built : 15:58:17, May 22 2019
419 14:01:14.447167 NOTICE: BL31: G12A normal boot!
420 14:01:14.472178 NOTICE: BL31: BL33 decompress pass
421 14:01:14.476777 ERROR: Error initializing runtime service opteed_fast
422 14:01:15.710701
423 14:01:15.711509
424 14:01:15.719095 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
425 14:01:15.719693
426 14:01:15.720283 Model: Libre Computer AML-A311D-CC Alta
427 14:01:15.927706 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
428 14:01:15.951050 DRAM: 2 GiB (effective 3.8 GiB)
429 14:01:16.094065 Core: 408 devices, 31 uclasses, devicetree: separate
430 14:01:16.099875 WDT: Not starting watchdog@f0d0
431 14:01:16.132140 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
432 14:01:16.144640 Loading Environment from FAT... Card did not respond to voltage select! : -110
433 14:01:16.149509 ** Bad device specification mmc 0 **
434 14:01:16.159955 Card did not respond to voltage select! : -110
435 14:01:16.167515 ** Bad device specification mmc 0 **
436 14:01:16.168152 Couldn't find partition mmc 0
437 14:01:16.175821 Card did not respond to voltage select! : -110
438 14:01:16.181362 ** Bad device specification mmc 0 **
439 14:01:16.181954 Couldn't find partition mmc 0
440 14:01:16.186301 Error: could not access storage.
441 14:01:17.450897 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
442 14:01:17.451709 bl2_stage_init 0x01
443 14:01:17.452333 bl2_stage_init 0x81
444 14:01:17.456413 hw id: 0x0000 - pwm id 0x01
445 14:01:17.456953 bl2_stage_init 0xc1
446 14:01:17.457377 bl2_stage_init 0x02
447 14:01:17.457785
448 14:01:17.461991 L0:00000000
449 14:01:17.462494 L1:20000703
450 14:01:17.462913 L2:00008067
451 14:01:17.463320 L3:14000000
452 14:01:17.467599 B2:00402000
453 14:01:17.468105 B1:e0f83180
454 14:01:17.468519
455 14:01:17.468922 TE: 58159
456 14:01:17.469322
457 14:01:17.473180 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 14:01:17.473680
459 14:01:17.474101 Board ID = 1
460 14:01:17.478731 Set A53 clk to 24M
461 14:01:17.479224 Set A73 clk to 24M
462 14:01:17.479633 Set clk81 to 24M
463 14:01:17.484369 A53 clk: 1200 MHz
464 14:01:17.484849 A73 clk: 1200 MHz
465 14:01:17.485253 CLK81: 166.6M
466 14:01:17.485649 smccc: 00012ab4
467 14:01:17.489999 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 14:01:17.495567 board id: 1
469 14:01:17.501425 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 14:01:17.512099 fw parse done
471 14:01:17.518041 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 14:01:17.560669 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 14:01:17.571559 PIEI prepare done
474 14:01:17.572086 fastboot data load
475 14:01:17.572503 fastboot data verify
476 14:01:17.577292 verify result: 266
477 14:01:17.582793 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 14:01:17.583254 LPDDR4 probe
479 14:01:17.583658 ddr clk to 1584MHz
480 14:01:17.590826 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 14:01:17.628172
482 14:01:17.628706 dmc_version 0001
483 14:01:17.634777 Check phy result
484 14:01:17.640646 INFO : End of CA training
485 14:01:17.641130 INFO : End of initialization
486 14:01:17.646184 INFO : Training has run successfully!
487 14:01:17.646641 Check phy result
488 14:01:17.651822 INFO : End of initialization
489 14:01:17.652346 INFO : End of read enable training
490 14:01:17.657448 INFO : End of fine write leveling
491 14:01:17.663103 INFO : End of Write leveling coarse delay
492 14:01:17.663594 INFO : Training has run successfully!
493 14:01:17.664027 Check phy result
494 14:01:17.668711 INFO : End of initialization
495 14:01:17.669169 INFO : End of read dq deskew training
496 14:01:17.674217 INFO : End of MPR read delay center optimization
497 14:01:17.679813 INFO : End of write delay center optimization
498 14:01:17.685441 INFO : End of read delay center optimization
499 14:01:17.685902 INFO : End of max read latency training
500 14:01:17.691029 INFO : Training has run successfully!
501 14:01:17.691492 1D training succeed
502 14:01:17.699684 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 14:01:17.747913 Check phy result
504 14:01:17.748555 INFO : End of initialization
505 14:01:17.770568 INFO : End of 2D read delay Voltage center optimization
506 14:01:17.790849 INFO : End of 2D read delay Voltage center optimization
507 14:01:17.842843 INFO : End of 2D write delay Voltage center optimization
508 14:01:17.892312 INFO : End of 2D write delay Voltage center optimization
509 14:01:17.897738 INFO : Training has run successfully!
510 14:01:17.898243
511 14:01:17.898658 channel==0
512 14:01:17.903261 RxClkDly_Margin_A0==78 ps 8
513 14:01:17.903807 TxDqDly_Margin_A0==98 ps 10
514 14:01:17.908859 RxClkDly_Margin_A1==88 ps 9
515 14:01:17.909337 TxDqDly_Margin_A1==98 ps 10
516 14:01:17.909746 TrainedVREFDQ_A0==74
517 14:01:17.914513 TrainedVREFDQ_A1==75
518 14:01:17.915009 VrefDac_Margin_A0==25
519 14:01:17.915338 DeviceVref_Margin_A0==40
520 14:01:17.920038 VrefDac_Margin_A1==25
521 14:01:17.920513 DeviceVref_Margin_A1==39
522 14:01:17.920922
523 14:01:17.921325
524 14:01:17.925725 channel==1
525 14:01:17.926199 RxClkDly_Margin_A0==98 ps 10
526 14:01:17.926604 TxDqDly_Margin_A0==98 ps 10
527 14:01:17.931262 RxClkDly_Margin_A1==98 ps 10
528 14:01:17.931721 TxDqDly_Margin_A1==88 ps 9
529 14:01:17.936852 TrainedVREFDQ_A0==77
530 14:01:17.937346 TrainedVREFDQ_A1==77
531 14:01:17.937751 VrefDac_Margin_A0==23
532 14:01:17.942447 DeviceVref_Margin_A0==37
533 14:01:17.942920 VrefDac_Margin_A1==23
534 14:01:17.948092 DeviceVref_Margin_A1==37
535 14:01:17.948614
536 14:01:17.949031 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 14:01:17.953746
538 14:01:17.981795 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
539 14:01:17.982355 2D training succeed
540 14:01:17.987204 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 14:01:17.992912 auto size-- 65535DDR cs0 size: 2048MB
542 14:01:17.993380 DDR cs1 size: 2048MB
543 14:01:17.998478 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 14:01:17.998929 cs0 DataBus test pass
545 14:01:18.004094 cs1 DataBus test pass
546 14:01:18.004545 cs0 AddrBus test pass
547 14:01:18.004949 cs1 AddrBus test pass
548 14:01:18.005344
549 14:01:18.009704 100bdlr_step_size ps== 420
550 14:01:18.010160 result report
551 14:01:18.015214 boot times 0Enable ddr reg access
552 14:01:18.020804 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 14:01:18.034213 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 14:01:18.607932 0.0;M3 CHK:0;cm4_sp_mode 0
555 14:01:18.608560 MVN_1=0x00000000
556 14:01:18.613598 MVN_2=0x00000000
557 14:01:18.619228 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 14:01:18.619754 OPS=0x10
559 14:01:18.620209 ring efuse init
560 14:01:18.620609 chipver efuse init
561 14:01:18.624900 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 14:01:18.630467 [0.018960 Inits done]
563 14:01:18.631037 secure task start!
564 14:01:18.631438 high task start!
565 14:01:18.634993 low task start!
566 14:01:18.635512 run into bl31
567 14:01:18.641645 NOTICE: BL31: v1.3(release):4fc40b1
568 14:01:18.648513 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 14:01:18.649032 NOTICE: BL31: G12A normal boot!
570 14:01:18.674856 NOTICE: BL31: BL33 decompress pass
571 14:01:18.680512 ERROR: Error initializing runtime service opteed_fast
572 14:01:19.913168
573 14:01:19.913602
574 14:01:19.921402 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 14:01:19.921760
576 14:01:19.921987 Model: Libre Computer AML-A311D-CC Alta
577 14:01:20.130197 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 14:01:20.153442 DRAM: 2 GiB (effective 3.8 GiB)
579 14:01:20.296412 Core: 408 devices, 31 uclasses, devicetree: separate
580 14:01:20.302229 WDT: Not starting watchdog@f0d0
581 14:01:20.334539 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 14:01:20.346952 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 14:01:20.352071 ** Bad device specification mmc 0 **
584 14:01:20.362301 Card did not respond to voltage select! : -110
585 14:01:20.370045 ** Bad device specification mmc 0 **
586 14:01:20.370379 Couldn't find partition mmc 0
587 14:01:20.378285 Card did not respond to voltage select! : -110
588 14:01:20.383798 ** Bad device specification mmc 0 **
589 14:01:20.384283 Couldn't find partition mmc 0
590 14:01:20.388838 Error: could not access storage.
591 14:01:20.732423 Net: eth0: ethernet@ff3f0000
592 14:01:20.732850 starting USB...
593 14:01:20.984206 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 14:01:20.984771 Starting the controller
595 14:01:20.991138 USB XHCI 1.10
596 14:01:22.702796 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 14:01:22.703274 bl2_stage_init 0x01
598 14:01:22.703557 bl2_stage_init 0x81
599 14:01:22.708202 hw id: 0x0000 - pwm id 0x01
600 14:01:22.708536 bl2_stage_init 0xc1
601 14:01:22.708754 bl2_stage_init 0x02
602 14:01:22.708963
603 14:01:22.713868 L0:00000000
604 14:01:22.714221 L1:20000703
605 14:01:22.714441 L2:00008067
606 14:01:22.714661 L3:14000000
607 14:01:22.716760 B2:00402000
608 14:01:22.717101 B1:e0f83180
609 14:01:22.717367
610 14:01:22.717606 TE: 58159
611 14:01:22.717852
612 14:01:22.727858 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 14:01:22.728260
614 14:01:22.728469 Board ID = 1
615 14:01:22.728679 Set A53 clk to 24M
616 14:01:22.728882 Set A73 clk to 24M
617 14:01:22.733532 Set clk81 to 24M
618 14:01:22.733900 A53 clk: 1200 MHz
619 14:01:22.734160 A73 clk: 1200 MHz
620 14:01:22.739179 CLK81: 166.6M
621 14:01:22.739543 smccc: 00012ab5
622 14:01:22.744627 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 14:01:22.745124 board id: 1
624 14:01:22.753323 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 14:01:22.764231 fw parse done
626 14:01:22.769982 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 14:01:22.812469 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 14:01:22.824243 PIEI prepare done
629 14:01:22.824632 fastboot data load
630 14:01:22.824847 fastboot data verify
631 14:01:22.829091 verify result: 266
632 14:01:22.834651 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 14:01:22.835196 LPDDR4 probe
634 14:01:22.835433 ddr clk to 1584MHz
635 14:01:22.842758 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 14:01:22.879903
637 14:01:22.880388 dmc_version 0001
638 14:01:22.885760 Check phy result
639 14:01:22.892508 INFO : End of CA training
640 14:01:22.892897 INFO : End of initialization
641 14:01:22.898004 INFO : Training has run successfully!
642 14:01:22.898383 Check phy result
643 14:01:22.903629 INFO : End of initialization
644 14:01:22.904018 INFO : End of read enable training
645 14:01:22.906941 INFO : End of fine write leveling
646 14:01:22.912485 INFO : End of Write leveling coarse delay
647 14:01:22.917984 INFO : Training has run successfully!
648 14:01:22.918348 Check phy result
649 14:01:22.918581 INFO : End of initialization
650 14:01:22.923605 INFO : End of read dq deskew training
651 14:01:22.929233 INFO : End of MPR read delay center optimization
652 14:01:22.929750 INFO : End of write delay center optimization
653 14:01:22.934909 INFO : End of read delay center optimization
654 14:01:22.940547 INFO : End of max read latency training
655 14:01:22.940915 INFO : Training has run successfully!
656 14:01:22.946125 1D training succeed
657 14:01:22.951110 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 14:01:22.999706 Check phy result
659 14:01:23.000159 INFO : End of initialization
660 14:01:23.022241 INFO : End of 2D read delay Voltage center optimization
661 14:01:23.042431 INFO : End of 2D read delay Voltage center optimization
662 14:01:23.094496 INFO : End of 2D write delay Voltage center optimization
663 14:01:23.143936 INFO : End of 2D write delay Voltage center optimization
664 14:01:23.149450 INFO : Training has run successfully!
665 14:01:23.149800
666 14:01:23.150011 channel==0
667 14:01:23.154988 RxClkDly_Margin_A0==88 ps 9
668 14:01:23.155333 TxDqDly_Margin_A0==98 ps 10
669 14:01:23.160656 RxClkDly_Margin_A1==88 ps 9
670 14:01:23.161299 TxDqDly_Margin_A1==98 ps 10
671 14:01:23.161608 TrainedVREFDQ_A0==74
672 14:01:23.166383 TrainedVREFDQ_A1==74
673 14:01:23.166746 VrefDac_Margin_A0==25
674 14:01:23.166969 DeviceVref_Margin_A0==40
675 14:01:23.172057 VrefDac_Margin_A1==25
676 14:01:23.172547 DeviceVref_Margin_A1==40
677 14:01:23.172870
678 14:01:23.173188
679 14:01:23.177566 channel==1
680 14:01:23.177921 RxClkDly_Margin_A0==98 ps 10
681 14:01:23.178453 TxDqDly_Margin_A0==98 ps 10
682 14:01:23.183078 RxClkDly_Margin_A1==98 ps 10
683 14:01:23.183549 TxDqDly_Margin_A1==88 ps 9
684 14:01:23.188549 TrainedVREFDQ_A0==77
685 14:01:23.188905 TrainedVREFDQ_A1==77
686 14:01:23.189131 VrefDac_Margin_A0==23
687 14:01:23.194267 DeviceVref_Margin_A0==37
688 14:01:23.194616 VrefDac_Margin_A1==24
689 14:01:23.199886 DeviceVref_Margin_A1==37
690 14:01:23.200250
691 14:01:23.200469 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 14:01:23.205397
693 14:01:23.233344 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
694 14:01:23.233765 2D training succeed
695 14:01:23.238999 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 14:01:23.244543 auto size-- 65535DDR cs0 size: 2048MB
697 14:01:23.244886 DDR cs1 size: 2048MB
698 14:01:23.250044 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 14:01:23.250371 cs0 DataBus test pass
700 14:01:23.255701 cs1 DataBus test pass
701 14:01:23.256067 cs0 AddrBus test pass
702 14:01:23.256281 cs1 AddrBus test pass
703 14:01:23.256489
704 14:01:23.261209 100bdlr_step_size ps== 420
705 14:01:23.261540 result report
706 14:01:23.266847 boot times 0Enable ddr reg access
707 14:01:23.272279 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 14:01:23.285772 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 14:01:23.859665 0.0;M3 CHK:0;cm4_sp_mode 0
710 14:01:23.860124 MVN_1=0x00000000
711 14:01:23.865062 MVN_2=0x00000000
712 14:01:23.870837 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 14:01:23.871159 OPS=0x10
714 14:01:23.871393 ring efuse init
715 14:01:23.871611 chipver efuse init
716 14:01:23.876570 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 14:01:23.882066 [0.018961 Inits done]
718 14:01:23.882397 secure task start!
719 14:01:23.882608 high task start!
720 14:01:23.886642 low task start!
721 14:01:23.886949 run into bl31
722 14:01:23.893310 NOTICE: BL31: v1.3(release):4fc40b1
723 14:01:23.901076 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 14:01:23.901408 NOTICE: BL31: G12A normal boot!
725 14:01:23.926652 NOTICE: BL31: BL33 decompress pass
726 14:01:23.932213 ERROR: Error initializing runtime service opteed_fast
727 14:01:25.165064
728 14:01:25.165487
729 14:01:25.172619 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 14:01:25.172994
731 14:01:25.173226 Model: Libre Computer AML-A311D-CC Alta
732 14:01:25.381943 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 14:01:25.404454 DRAM: 2 GiB (effective 3.8 GiB)
734 14:01:25.548316 Core: 408 devices, 31 uclasses, devicetree: separate
735 14:01:25.553980 WDT: Not starting watchdog@f0d0
736 14:01:25.586465 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 14:01:25.598955 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 14:01:25.603900 ** Bad device specification mmc 0 **
739 14:01:25.614381 Card did not respond to voltage select! : -110
740 14:01:25.620976 ** Bad device specification mmc 0 **
741 14:01:25.621618 Couldn't find partition mmc 0
742 14:01:25.630189 Card did not respond to voltage select! : -110
743 14:01:25.635816 ** Bad device specification mmc 0 **
744 14:01:25.636212 Couldn't find partition mmc 0
745 14:01:25.640880 Error: could not access storage.
746 14:01:25.982386 Net: eth0: ethernet@ff3f0000
747 14:01:25.982808 starting USB...
748 14:01:26.235108 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 14:01:26.235526 Starting the controller
750 14:01:26.241486 USB XHCI 1.10
751 14:01:28.401287 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 14:01:28.401673 bl2_stage_init 0x01
753 14:01:28.401881 bl2_stage_init 0x81
754 14:01:28.406829 hw id: 0x0000 - pwm id 0x01
755 14:01:28.407115 bl2_stage_init 0xc1
756 14:01:28.407325 bl2_stage_init 0x02
757 14:01:28.407532
758 14:01:28.412505 L0:00000000
759 14:01:28.412783 L1:20000703
760 14:01:28.412986 L2:00008067
761 14:01:28.413193 L3:14000000
762 14:01:28.418123 B2:00402000
763 14:01:28.418401 B1:e0f83180
764 14:01:28.418603
765 14:01:28.418813 TE: 58159
766 14:01:28.419012
767 14:01:28.423708 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 14:01:28.424004
769 14:01:28.424217 Board ID = 1
770 14:01:28.429236 Set A53 clk to 24M
771 14:01:28.429518 Set A73 clk to 24M
772 14:01:28.429722 Set clk81 to 24M
773 14:01:28.434960 A53 clk: 1200 MHz
774 14:01:28.435244 A73 clk: 1200 MHz
775 14:01:28.435445 CLK81: 166.6M
776 14:01:28.435638 smccc: 00012ab5
777 14:01:28.440579 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 14:01:28.446051 board id: 1
779 14:01:28.450961 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 14:01:28.462590 fw parse done
781 14:01:28.468517 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 14:01:28.511274 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 14:01:28.522079 PIEI prepare done
784 14:01:28.522393 fastboot data load
785 14:01:28.522607 fastboot data verify
786 14:01:28.527758 verify result: 266
787 14:01:28.533295 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 14:01:28.533588 LPDDR4 probe
789 14:01:28.533794 ddr clk to 1584MHz
790 14:01:28.541328 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 14:01:28.578531
792 14:01:28.578886 dmc_version 0001
793 14:01:28.585158 Check phy result
794 14:01:28.591042 INFO : End of CA training
795 14:01:28.591331 INFO : End of initialization
796 14:01:28.596634 INFO : Training has run successfully!
797 14:01:28.596901 Check phy result
798 14:01:28.602193 INFO : End of initialization
799 14:01:28.602468 INFO : End of read enable training
800 14:01:28.607821 INFO : End of fine write leveling
801 14:01:28.613416 INFO : End of Write leveling coarse delay
802 14:01:28.613694 INFO : Training has run successfully!
803 14:01:28.613904 Check phy result
804 14:01:28.619047 INFO : End of initialization
805 14:01:28.619314 INFO : End of read dq deskew training
806 14:01:28.624623 INFO : End of MPR read delay center optimization
807 14:01:28.630191 INFO : End of write delay center optimization
808 14:01:28.635818 INFO : End of read delay center optimization
809 14:01:28.636121 INFO : End of max read latency training
810 14:01:28.641474 INFO : Training has run successfully!
811 14:01:28.641749 1D training succeed
812 14:01:28.649673 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 14:01:28.698376 Check phy result
814 14:01:28.698747 INFO : End of initialization
815 14:01:28.720803 INFO : End of 2D read delay Voltage center optimization
816 14:01:28.741121 INFO : End of 2D read delay Voltage center optimization
817 14:01:28.792882 INFO : End of 2D write delay Voltage center optimization
818 14:01:28.842508 INFO : End of 2D write delay Voltage center optimization
819 14:01:28.848112 INFO : Training has run successfully!
820 14:01:28.848402
821 14:01:28.848631 channel==0
822 14:01:28.853661 RxClkDly_Margin_A0==88 ps 9
823 14:01:28.853961 TxDqDly_Margin_A0==98 ps 10
824 14:01:28.856994 RxClkDly_Margin_A1==88 ps 9
825 14:01:28.857263 TxDqDly_Margin_A1==98 ps 10
826 14:01:28.862741 TrainedVREFDQ_A0==74
827 14:01:28.863031 TrainedVREFDQ_A1==74
828 14:01:28.863242 VrefDac_Margin_A0==24
829 14:01:28.868202 DeviceVref_Margin_A0==40
830 14:01:28.868483 VrefDac_Margin_A1==25
831 14:01:28.873750 DeviceVref_Margin_A1==40
832 14:01:28.874047
833 14:01:28.874256
834 14:01:28.874458 channel==1
835 14:01:28.874656 RxClkDly_Margin_A0==98 ps 10
836 14:01:28.879298 TxDqDly_Margin_A0==88 ps 9
837 14:01:28.879568 RxClkDly_Margin_A1==88 ps 9
838 14:01:28.885164 TxDqDly_Margin_A1==88 ps 9
839 14:01:28.885433 TrainedVREFDQ_A0==75
840 14:01:28.885638 TrainedVREFDQ_A1==75
841 14:01:28.890574 VrefDac_Margin_A0==22
842 14:01:28.890846 DeviceVref_Margin_A0==38
843 14:01:28.896167 VrefDac_Margin_A1==24
844 14:01:28.896429 DeviceVref_Margin_A1==39
845 14:01:28.896628
846 14:01:28.901735 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 14:01:28.902004
848 14:01:28.929856 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
849 14:01:28.935577 2D training succeed
850 14:01:28.940864 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 14:01:28.941128 auto size-- 65535DDR cs0 size: 2048MB
852 14:01:28.946517 DDR cs1 size: 2048MB
853 14:01:28.946791 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 14:01:28.952052 cs0 DataBus test pass
855 14:01:28.952318 cs1 DataBus test pass
856 14:01:28.952518 cs0 AddrBus test pass
857 14:01:28.957646 cs1 AddrBus test pass
858 14:01:28.957899
859 14:01:28.958099 100bdlr_step_size ps== 420
860 14:01:28.958297 result report
861 14:01:28.963250 boot times 0Enable ddr reg access
862 14:01:28.969857 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 14:01:28.983314 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 14:01:29.558040 0.0;M3 CHK:0;cm4_sp_mode 0
865 14:01:29.558441 MVN_1=0x00000000
866 14:01:29.563507 MVN_2=0x00000000
867 14:01:29.569299 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 14:01:29.569698 OPS=0x10
869 14:01:29.570022 ring efuse init
870 14:01:29.570254 chipver efuse init
871 14:01:29.574891 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 14:01:29.580480 [0.018961 Inits done]
873 14:01:29.580763 secure task start!
874 14:01:29.580977 high task start!
875 14:01:29.584192 low task start!
876 14:01:29.584488 run into bl31
877 14:01:29.591765 NOTICE: BL31: v1.3(release):4fc40b1
878 14:01:29.598590 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 14:01:29.598885 NOTICE: BL31: G12A normal boot!
880 14:01:29.624912 NOTICE: BL31: BL33 decompress pass
881 14:01:29.629609 ERROR: Error initializing runtime service opteed_fast
882 14:01:30.863591
883 14:01:30.864078
884 14:01:30.871030 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 14:01:30.871327
886 14:01:30.871558 Model: Libre Computer AML-A311D-CC Alta
887 14:01:31.079497 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 14:01:31.103773 DRAM: 2 GiB (effective 3.8 GiB)
889 14:01:31.246787 Core: 408 devices, 31 uclasses, devicetree: separate
890 14:01:31.252619 WDT: Not starting watchdog@f0d0
891 14:01:31.284860 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 14:01:31.297321 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 14:01:31.302270 ** Bad device specification mmc 0 **
894 14:01:31.312648 Card did not respond to voltage select! : -110
895 14:01:31.320361 ** Bad device specification mmc 0 **
896 14:01:31.320648 Couldn't find partition mmc 0
897 14:01:31.328716 Card did not respond to voltage select! : -110
898 14:01:31.334157 ** Bad device specification mmc 0 **
899 14:01:31.334633 Couldn't find partition mmc 0
900 14:01:31.339208 Error: could not access storage.
901 14:01:31.681748 Net: eth0: ethernet@ff3f0000
902 14:01:31.682391 starting USB...
903 14:01:31.933583 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 14:01:31.934219 Starting the controller
905 14:01:31.940427 USB XHCI 1.10
906 14:01:33.494342 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
907 14:01:33.502676 scanning usb for storage devices... 0 Storage Device(s) found
909 14:01:33.554328 Hit any key to stop autoboot: 1
910 14:01:33.555280 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
911 14:01:33.555874 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
912 14:01:33.556396 Setting prompt string to ['=>']
913 14:01:33.556900 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
914 14:01:33.570113 0
915 14:01:33.571064 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
916 14:01:33.571588 Sending with 10 millisecond of delay
918 14:01:34.706665 => setenv autoload no
919 14:01:34.718163 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
920 14:01:34.723119 setenv autoload no
921 14:01:34.723870 Sending with 10 millisecond of delay
923 14:01:36.522626 => setenv initrd_high 0xffffffff
924 14:01:36.533234 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
925 14:01:36.533827 setenv initrd_high 0xffffffff
926 14:01:36.534368 Sending with 10 millisecond of delay
928 14:01:38.151070 => setenv fdt_high 0xffffffff
929 14:01:38.161795 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
930 14:01:38.162329 setenv fdt_high 0xffffffff
931 14:01:38.162800 Sending with 10 millisecond of delay
933 14:01:38.454051 => dhcp
934 14:01:38.464757 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
935 14:01:38.465275 dhcp
936 14:01:38.465502 Speed: 1000, full duplex
937 14:01:38.465702 BOOTP broadcast 1
938 14:01:38.475749 DHCP client bound to address 192.168.6.27 (11 ms)
939 14:01:38.476490 Sending with 10 millisecond of delay
941 14:01:40.153832 => setenv serverip 192.168.6.2
942 14:01:40.164711 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
943 14:01:40.165724 setenv serverip 192.168.6.2
944 14:01:40.166500 Sending with 10 millisecond of delay
946 14:01:43.891631 => tftpboot 0x01080000 934199/tftp-deploy-i29qaq55/kernel/uImage
947 14:01:43.902523 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
948 14:01:43.903405 tftpboot 0x01080000 934199/tftp-deploy-i29qaq55/kernel/uImage
949 14:01:43.903898 Speed: 1000, full duplex
950 14:01:43.904401 Using ethernet@ff3f0000 device
951 14:01:43.904940 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
952 14:01:43.910469 Filename '934199/tftp-deploy-i29qaq55/kernel/uImage'.
953 14:01:43.914364 Load address: 0x1080000
954 14:01:46.760090 Loading: *################################################## 43.6 MiB
955 14:01:46.760499 15.3 MiB/s
956 14:01:46.760715 done
957 14:01:46.764672 Bytes transferred = 45713984 (2b98a40 hex)
958 14:01:46.765680 Sending with 10 millisecond of delay
960 14:01:51.456649 => tftpboot 0x08000000 934199/tftp-deploy-i29qaq55/ramdisk/ramdisk.cpio.gz.uboot
961 14:01:51.467576 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
962 14:01:51.468571 tftpboot 0x08000000 934199/tftp-deploy-i29qaq55/ramdisk/ramdisk.cpio.gz.uboot
963 14:01:51.469066 Speed: 1000, full duplex
964 14:01:51.469512 Using ethernet@ff3f0000 device
965 14:01:51.470355 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
966 14:01:51.478865 Filename '934199/tftp-deploy-i29qaq55/ramdisk/ramdisk.cpio.gz.uboot'.
967 14:01:51.479447 Load address: 0x8000000
968 14:01:58.631024 Loading: *################################################# UDP wrong checksum 00000005 0000e5f3
969 14:02:03.631457 T UDP wrong checksum 00000005 0000e5f3
970 14:02:13.634293 T T UDP wrong checksum 00000005 0000e5f3
971 14:02:26.377486 T T UDP wrong checksum 000000ff 000056bc
972 14:02:26.401643 UDP wrong checksum 000000ff 0000edae
973 14:02:33.639436 T T UDP wrong checksum 00000005 0000e5f3
974 14:02:44.229114 T T UDP wrong checksum 000000ff 0000ca82
975 14:02:47.469538 UDP wrong checksum 000000ff 0000aca0
976 14:02:47.480416 UDP wrong checksum 000000ff 00003593
977 14:02:51.756178 T UDP wrong checksum 000000ff 00001579
978 14:02:51.766543 UDP wrong checksum 000000ff 0000a96b
979 14:02:53.644352
980 14:02:53.645131 Retry count exceeded; starting again
982 14:02:53.646989 end: 2.4.3 bootloader-commands (duration 00:01:20) [common]
985 14:02:53.649455 end: 2.4 uboot-commands (duration 00:01:52) [common]
987 14:02:53.651234 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
989 14:02:53.652644 end: 2 uboot-action (duration 00:01:52) [common]
991 14:02:53.654637 Cleaning after the job
992 14:02:53.655368 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/934199/tftp-deploy-i29qaq55/ramdisk
993 14:02:53.657066 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/934199/tftp-deploy-i29qaq55/kernel
994 14:02:53.690231 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/934199/tftp-deploy-i29qaq55/dtb
995 14:02:53.692263 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/934199/tftp-deploy-i29qaq55/modules
996 14:02:53.714013 start: 4.1 power-off (timeout 00:00:30) [common]
997 14:02:53.715419 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
998 14:02:53.746993 >> OK - accepted request
999 14:02:53.749127 Returned 0 in 0 seconds
1000 14:02:53.850091 end: 4.1 power-off (duration 00:00:00) [common]
1002 14:02:53.851825 start: 4.2 read-feedback (timeout 00:10:00) [common]
1003 14:02:53.853025 Listened to connection for namespace 'common' for up to 1s
1004 14:02:54.853295 Finalising connection for namespace 'common'
1005 14:02:54.853823 Disconnecting from shell: Finalise
1006 14:02:54.854110 =>
1007 14:02:54.954815 end: 4.2 read-feedback (duration 00:00:01) [common]
1008 14:02:54.955493 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/934199
1009 14:02:55.236150 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/934199
1010 14:02:55.236766 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.