Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 20:14:28.974449 lava-dispatcher, installed at version: 2024.01
2 20:14:28.975198 start: 0 validate
3 20:14:28.975671 Start time: 2024-11-04 20:14:28.975643+00:00 (UTC)
4 20:14:28.976214 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 20:14:28.976758 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 20:14:29.014302 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 20:14:29.014844 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-95-g6db936d4ac0f%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 20:14:29.042033 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 20:14:29.042628 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-95-g6db936d4ac0f%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 20:14:29.064289 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 20:14:29.064766 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 20:14:29.089663 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 20:14:29.090161 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-95-g6db936d4ac0f%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 20:14:29.119647 validate duration: 0.14
16 20:14:29.120542 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 20:14:29.120870 start: 1.1 download-retry (timeout 00:10:00) [common]
18 20:14:29.121402 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 20:14:29.122083 Not decompressing ramdisk as can be used compressed.
20 20:14:29.122513 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 20:14:29.122787 saving as /var/lib/lava/dispatcher/tmp/936513/tftp-deploy-zj58j50d/ramdisk/initrd.cpio.gz
22 20:14:29.123045 total size: 4775763 (4 MB)
23 20:14:29.155622 progress 0 % (0 MB)
24 20:14:29.159339 progress 5 % (0 MB)
25 20:14:29.162779 progress 10 % (0 MB)
26 20:14:29.166184 progress 15 % (0 MB)
27 20:14:29.170121 progress 20 % (0 MB)
28 20:14:29.173451 progress 25 % (1 MB)
29 20:14:29.176737 progress 30 % (1 MB)
30 20:14:29.180534 progress 35 % (1 MB)
31 20:14:29.183861 progress 40 % (1 MB)
32 20:14:29.187238 progress 45 % (2 MB)
33 20:14:29.190597 progress 50 % (2 MB)
34 20:14:29.194344 progress 55 % (2 MB)
35 20:14:29.197634 progress 60 % (2 MB)
36 20:14:29.200987 progress 65 % (2 MB)
37 20:14:29.204721 progress 70 % (3 MB)
38 20:14:29.208054 progress 75 % (3 MB)
39 20:14:29.211412 progress 80 % (3 MB)
40 20:14:29.214643 progress 85 % (3 MB)
41 20:14:29.218249 progress 90 % (4 MB)
42 20:14:29.221350 progress 95 % (4 MB)
43 20:14:29.224289 progress 100 % (4 MB)
44 20:14:29.224900 4 MB downloaded in 0.10 s (44.73 MB/s)
45 20:14:29.225417 end: 1.1.1 http-download (duration 00:00:00) [common]
47 20:14:29.226297 end: 1.1 download-retry (duration 00:00:00) [common]
48 20:14:29.226588 start: 1.2 download-retry (timeout 00:10:00) [common]
49 20:14:29.226856 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 20:14:29.227330 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-95-g6db936d4ac0f/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 20:14:29.227574 saving as /var/lib/lava/dispatcher/tmp/936513/tftp-deploy-zj58j50d/kernel/zImage
52 20:14:29.227802 total size: 11444736 (10 MB)
53 20:14:29.228012 No compression specified
54 20:14:29.266722 progress 0 % (0 MB)
55 20:14:29.274062 progress 5 % (0 MB)
56 20:14:29.281320 progress 10 % (1 MB)
57 20:14:29.288976 progress 15 % (1 MB)
58 20:14:29.296327 progress 20 % (2 MB)
59 20:14:29.303961 progress 25 % (2 MB)
60 20:14:29.311233 progress 30 % (3 MB)
61 20:14:29.318752 progress 35 % (3 MB)
62 20:14:29.325941 progress 40 % (4 MB)
63 20:14:29.333420 progress 45 % (4 MB)
64 20:14:29.340648 progress 50 % (5 MB)
65 20:14:29.348220 progress 55 % (6 MB)
66 20:14:29.355596 progress 60 % (6 MB)
67 20:14:29.363211 progress 65 % (7 MB)
68 20:14:29.370432 progress 70 % (7 MB)
69 20:14:29.377525 progress 75 % (8 MB)
70 20:14:29.385111 progress 80 % (8 MB)
71 20:14:29.392236 progress 85 % (9 MB)
72 20:14:29.399840 progress 90 % (9 MB)
73 20:14:29.406967 progress 95 % (10 MB)
74 20:14:29.414197 progress 100 % (10 MB)
75 20:14:29.414676 10 MB downloaded in 0.19 s (58.41 MB/s)
76 20:14:29.415138 end: 1.2.1 http-download (duration 00:00:00) [common]
78 20:14:29.415949 end: 1.2 download-retry (duration 00:00:00) [common]
79 20:14:29.416223 start: 1.3 download-retry (timeout 00:10:00) [common]
80 20:14:29.416484 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 20:14:29.416952 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-95-g6db936d4ac0f/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 20:14:29.417220 saving as /var/lib/lava/dispatcher/tmp/936513/tftp-deploy-zj58j50d/dtb/am335x-boneblack.dtb
83 20:14:29.417425 total size: 70568 (0 MB)
84 20:14:29.417631 No compression specified
85 20:14:29.454225 progress 46 % (0 MB)
86 20:14:29.455015 progress 92 % (0 MB)
87 20:14:29.455668 progress 100 % (0 MB)
88 20:14:29.456033 0 MB downloaded in 0.04 s (1.74 MB/s)
89 20:14:29.456467 end: 1.3.1 http-download (duration 00:00:00) [common]
91 20:14:29.457266 end: 1.3 download-retry (duration 00:00:00) [common]
92 20:14:29.457525 start: 1.4 download-retry (timeout 00:10:00) [common]
93 20:14:29.457785 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 20:14:29.458270 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 20:14:29.458507 saving as /var/lib/lava/dispatcher/tmp/936513/tftp-deploy-zj58j50d/nfsrootfs/full.rootfs.tar
96 20:14:29.458709 total size: 117747780 (112 MB)
97 20:14:29.458915 Using unxz to decompress xz
98 20:14:29.489016 progress 0 % (0 MB)
99 20:14:30.214614 progress 5 % (5 MB)
100 20:14:30.961908 progress 10 % (11 MB)
101 20:14:31.735043 progress 15 % (16 MB)
102 20:14:32.449764 progress 20 % (22 MB)
103 20:14:33.081902 progress 25 % (28 MB)
104 20:14:33.936560 progress 30 % (33 MB)
105 20:14:34.744442 progress 35 % (39 MB)
106 20:14:35.072897 progress 40 % (44 MB)
107 20:14:35.423593 progress 45 % (50 MB)
108 20:14:36.135892 progress 50 % (56 MB)
109 20:14:36.949658 progress 55 % (61 MB)
110 20:14:37.706657 progress 60 % (67 MB)
111 20:14:38.573774 progress 65 % (73 MB)
112 20:14:39.344441 progress 70 % (78 MB)
113 20:14:40.094901 progress 75 % (84 MB)
114 20:14:40.814825 progress 80 % (89 MB)
115 20:14:41.515377 progress 85 % (95 MB)
116 20:14:42.288434 progress 90 % (101 MB)
117 20:14:43.036543 progress 95 % (106 MB)
118 20:14:43.840784 progress 100 % (112 MB)
119 20:14:43.853115 112 MB downloaded in 14.39 s (7.80 MB/s)
120 20:14:43.854070 end: 1.4.1 http-download (duration 00:00:14) [common]
122 20:14:43.855700 end: 1.4 download-retry (duration 00:00:14) [common]
123 20:14:43.856223 start: 1.5 download-retry (timeout 00:09:45) [common]
124 20:14:43.856741 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 20:14:43.857626 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-95-g6db936d4ac0f/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 20:14:43.858129 saving as /var/lib/lava/dispatcher/tmp/936513/tftp-deploy-zj58j50d/modules/modules.tar
127 20:14:43.858546 total size: 6609744 (6 MB)
128 20:14:43.858967 Using unxz to decompress xz
129 20:14:43.892499 progress 0 % (0 MB)
130 20:14:43.927432 progress 5 % (0 MB)
131 20:14:43.969917 progress 10 % (0 MB)
132 20:14:44.012416 progress 15 % (0 MB)
133 20:14:44.055803 progress 20 % (1 MB)
134 20:14:44.101208 progress 25 % (1 MB)
135 20:14:44.143239 progress 30 % (1 MB)
136 20:14:44.184850 progress 35 % (2 MB)
137 20:14:44.227682 progress 40 % (2 MB)
138 20:14:44.270434 progress 45 % (2 MB)
139 20:14:44.313201 progress 50 % (3 MB)
140 20:14:44.355098 progress 55 % (3 MB)
141 20:14:44.404264 progress 60 % (3 MB)
142 20:14:44.446475 progress 65 % (4 MB)
143 20:14:44.489087 progress 70 % (4 MB)
144 20:14:44.534248 progress 75 % (4 MB)
145 20:14:44.576169 progress 80 % (5 MB)
146 20:14:44.617970 progress 85 % (5 MB)
147 20:14:44.660085 progress 90 % (5 MB)
148 20:14:44.702644 progress 95 % (6 MB)
149 20:14:44.745708 progress 100 % (6 MB)
150 20:14:44.758636 6 MB downloaded in 0.90 s (7.00 MB/s)
151 20:14:44.759357 end: 1.5.1 http-download (duration 00:00:01) [common]
153 20:14:44.760413 end: 1.5 download-retry (duration 00:00:01) [common]
154 20:14:44.760761 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 20:14:44.761103 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 20:15:02.635257 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/936513/extract-nfsrootfs-3d2g851a
157 20:15:02.635822 end: 1.6.1 extract-nfsrootfs (duration 00:00:18) [common]
158 20:15:02.636148 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
159 20:15:02.636820 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07
160 20:15:02.637322 makedir: /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin
161 20:15:02.637740 makedir: /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/tests
162 20:15:02.638183 makedir: /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/results
163 20:15:02.638574 Creating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-add-keys
164 20:15:02.639111 Creating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-add-sources
165 20:15:02.639693 Creating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-background-process-start
166 20:15:02.640218 Creating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-background-process-stop
167 20:15:02.640748 Creating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-common-functions
168 20:15:02.641246 Creating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-echo-ipv4
169 20:15:02.641730 Creating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-install-packages
170 20:15:02.642252 Creating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-installed-packages
171 20:15:02.642738 Creating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-os-build
172 20:15:02.643222 Creating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-probe-channel
173 20:15:02.643703 Creating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-probe-ip
174 20:15:02.644180 Creating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-target-ip
175 20:15:02.644687 Creating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-target-mac
176 20:15:02.645171 Creating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-target-storage
177 20:15:02.645660 Creating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-test-case
178 20:15:02.646202 Creating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-test-event
179 20:15:02.646681 Creating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-test-feedback
180 20:15:02.647161 Creating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-test-raise
181 20:15:02.647636 Creating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-test-reference
182 20:15:02.648109 Creating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-test-runner
183 20:15:02.648613 Creating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-test-set
184 20:15:02.649090 Creating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-test-shell
185 20:15:02.649582 Updating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-add-keys (debian)
186 20:15:02.650159 Updating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-add-sources (debian)
187 20:15:02.650675 Updating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-install-packages (debian)
188 20:15:02.651175 Updating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-installed-packages (debian)
189 20:15:02.651669 Updating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/bin/lava-os-build (debian)
190 20:15:02.652101 Creating /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/environment
191 20:15:02.652470 LAVA metadata
192 20:15:02.652729 - LAVA_JOB_ID=936513
193 20:15:02.652945 - LAVA_DISPATCHER_IP=192.168.6.3
194 20:15:02.653291 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
195 20:15:02.654245 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 20:15:02.654560 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
197 20:15:02.654764 skipped lava-vland-overlay
198 20:15:02.655004 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 20:15:02.655256 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
200 20:15:02.655471 skipped lava-multinode-overlay
201 20:15:02.655715 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 20:15:02.655965 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
203 20:15:02.656211 Loading test definitions
204 20:15:02.656485 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
205 20:15:02.656718 Using /lava-936513 at stage 0
206 20:15:02.657899 uuid=936513_1.6.2.4.1 testdef=None
207 20:15:02.658204 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 20:15:02.658468 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
209 20:15:02.660081 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 20:15:02.660874 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
212 20:15:02.662807 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 20:15:02.663627 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
215 20:15:02.665411 runner path: /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/0/tests/0_timesync-off test_uuid 936513_1.6.2.4.1
216 20:15:02.665970 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 20:15:02.666785 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
219 20:15:02.667024 Using /lava-936513 at stage 0
220 20:15:02.667379 Fetching tests from https://github.com/kernelci/test-definitions.git
221 20:15:02.667664 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/0/tests/1_kselftest-dt'
222 20:15:06.018160 Running '/usr/bin/git checkout kernelci.org
223 20:15:06.043769 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 20:15:06.045280 uuid=936513_1.6.2.4.5 testdef=None
225 20:15:06.045649 end: 1.6.2.4.5 git-repo-action (duration 00:00:03) [common]
227 20:15:06.046456 start: 1.6.2.4.6 test-overlay (timeout 00:09:23) [common]
228 20:15:06.049441 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 20:15:06.050336 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:23) [common]
231 20:15:06.054314 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 20:15:06.055245 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:23) [common]
234 20:15:06.059073 runner path: /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/0/tests/1_kselftest-dt test_uuid 936513_1.6.2.4.5
235 20:15:06.059418 BOARD='beaglebone-black'
236 20:15:06.059626 BRANCH='pm'
237 20:15:06.059824 SKIPFILE='/dev/null'
238 20:15:06.060022 SKIP_INSTALL='True'
239 20:15:06.060217 TESTPROG_URL='http://storage.kernelci.org/pm/testing/v6.12-rc6-95-g6db936d4ac0f/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 20:15:06.060416 TST_CASENAME=''
241 20:15:06.060611 TST_CMDFILES='dt'
242 20:15:06.061269 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 20:15:06.062145 Creating lava-test-runner.conf files
245 20:15:06.062359 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/936513/lava-overlay-g4eoty07/lava-936513/0 for stage 0
246 20:15:06.062748 - 0_timesync-off
247 20:15:06.063008 - 1_kselftest-dt
248 20:15:06.063374 end: 1.6.2.4 test-definition (duration 00:00:03) [common]
249 20:15:06.063671 start: 1.6.2.5 compress-overlay (timeout 00:09:23) [common]
250 20:15:30.074905 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 20:15:30.075381 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
252 20:15:30.075705 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 20:15:30.076035 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 20:15:30.076353 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
255 20:15:30.468907 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 20:15:30.469384 start: 1.6.4 extract-modules (timeout 00:08:59) [common]
257 20:15:30.469648 extracting modules file /var/lib/lava/dispatcher/tmp/936513/tftp-deploy-zj58j50d/modules/modules.tar to /var/lib/lava/dispatcher/tmp/936513/extract-nfsrootfs-3d2g851a
258 20:15:31.404352 extracting modules file /var/lib/lava/dispatcher/tmp/936513/tftp-deploy-zj58j50d/modules/modules.tar to /var/lib/lava/dispatcher/tmp/936513/extract-overlay-ramdisk-vlk0v_6f/ramdisk
259 20:15:32.388970 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 20:15:32.389464 start: 1.6.5 apply-overlay-tftp (timeout 00:08:57) [common]
261 20:15:32.389747 [common] Applying overlay to NFS
262 20:15:32.389991 [common] Applying overlay /var/lib/lava/dispatcher/tmp/936513/compress-overlay-6d_atze9/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/936513/extract-nfsrootfs-3d2g851a
263 20:15:35.257515 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 20:15:35.258045 start: 1.6.6 prepare-kernel (timeout 00:08:54) [common]
265 20:15:35.258353 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:54) [common]
266 20:15:35.258653 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 20:15:35.258919 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 20:15:35.259189 start: 1.6.7 configure-preseed-file (timeout 00:08:54) [common]
269 20:15:35.259449 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 20:15:35.259712 start: 1.6.8 compress-ramdisk (timeout 00:08:54) [common]
271 20:15:35.259973 Building ramdisk /var/lib/lava/dispatcher/tmp/936513/extract-overlay-ramdisk-vlk0v_6f/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/936513/extract-overlay-ramdisk-vlk0v_6f/ramdisk
272 20:15:36.392387 >> 74900 blocks
273 20:15:41.117542 Adding RAMdisk u-boot header.
274 20:15:41.118138 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/936513/extract-overlay-ramdisk-vlk0v_6f/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/936513/extract-overlay-ramdisk-vlk0v_6f/ramdisk.cpio.gz.uboot
275 20:15:41.280354 output: Image Name:
276 20:15:41.280781 output: Created: Mon Nov 4 20:15:41 2024
277 20:15:41.281211 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 20:15:41.281631 output: Data Size: 14791038 Bytes = 14444.37 KiB = 14.11 MiB
279 20:15:41.282100 output: Load Address: 00000000
280 20:15:41.282513 output: Entry Point: 00000000
281 20:15:41.282917 output:
282 20:15:41.283948 rename /var/lib/lava/dispatcher/tmp/936513/extract-overlay-ramdisk-vlk0v_6f/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/936513/tftp-deploy-zj58j50d/ramdisk/ramdisk.cpio.gz.uboot
283 20:15:41.284664 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 20:15:41.285221 end: 1.6 prepare-tftp-overlay (duration 00:00:57) [common]
285 20:15:41.285758 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:48) [common]
286 20:15:41.286259 No LXC device requested
287 20:15:41.286776 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 20:15:41.287295 start: 1.8 deploy-device-env (timeout 00:08:48) [common]
289 20:15:41.287797 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 20:15:41.288214 Checking files for TFTP limit of 4294967296 bytes.
291 20:15:41.290913 end: 1 tftp-deploy (duration 00:01:12) [common]
292 20:15:41.291495 start: 2 uboot-action (timeout 00:05:00) [common]
293 20:15:41.292030 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 20:15:41.292540 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 20:15:41.293051 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 20:15:41.293800 substitutions:
297 20:15:41.294259 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 20:15:41.294677 - {DTB_ADDR}: 0x88000000
299 20:15:41.295083 - {DTB}: 936513/tftp-deploy-zj58j50d/dtb/am335x-boneblack.dtb
300 20:15:41.295487 - {INITRD}: 936513/tftp-deploy-zj58j50d/ramdisk/ramdisk.cpio.gz.uboot
301 20:15:41.295886 - {KERNEL_ADDR}: 0x82000000
302 20:15:41.296283 - {KERNEL}: 936513/tftp-deploy-zj58j50d/kernel/zImage
303 20:15:41.296682 - {LAVA_MAC}: None
304 20:15:41.297121 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/936513/extract-nfsrootfs-3d2g851a
305 20:15:41.297525 - {NFS_SERVER_IP}: 192.168.6.3
306 20:15:41.297947 - {PRESEED_CONFIG}: None
307 20:15:41.298346 - {PRESEED_LOCAL}: None
308 20:15:41.298742 - {RAMDISK_ADDR}: 0x83000000
309 20:15:41.299136 - {RAMDISK}: 936513/tftp-deploy-zj58j50d/ramdisk/ramdisk.cpio.gz.uboot
310 20:15:41.299535 - {ROOT_PART}: None
311 20:15:41.299927 - {ROOT}: None
312 20:15:41.300317 - {SERVER_IP}: 192.168.6.3
313 20:15:41.300706 - {TEE_ADDR}: 0x83000000
314 20:15:41.301091 - {TEE}: None
315 20:15:41.301480 Parsed boot commands:
316 20:15:41.301884 - setenv autoload no
317 20:15:41.302284 - setenv initrd_high 0xffffffff
318 20:15:41.302674 - setenv fdt_high 0xffffffff
319 20:15:41.303060 - dhcp
320 20:15:41.303446 - setenv serverip 192.168.6.3
321 20:15:41.303828 - tftp 0x82000000 936513/tftp-deploy-zj58j50d/kernel/zImage
322 20:15:41.304216 - tftp 0x83000000 936513/tftp-deploy-zj58j50d/ramdisk/ramdisk.cpio.gz.uboot
323 20:15:41.304604 - setenv initrd_size ${filesize}
324 20:15:41.304990 - tftp 0x88000000 936513/tftp-deploy-zj58j50d/dtb/am335x-boneblack.dtb
325 20:15:41.305377 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/936513/extract-nfsrootfs-3d2g851a,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 20:15:41.305777 - bootz 0x82000000 0x83000000 0x88000000
327 20:15:41.306307 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 20:15:41.307794 start: 2.3 connect-device (timeout 00:05:00) [common]
330 20:15:41.308220 [common] connect-device Connecting to device using 'telnet conserv3 3002'
331 20:15:41.322607 Setting prompt string to ['lava-test: # ']
332 20:15:41.324053 end: 2.3 connect-device (duration 00:00:00) [common]
333 20:15:41.324672 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 20:15:41.325265 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 20:15:41.325923 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 20:15:41.327347 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-05'
337 20:15:41.361279 >> OK - accepted request
338 20:15:41.363241 Returned 0 in 0 seconds
339 20:15:41.464190 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 20:15:41.465908 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 20:15:41.466481 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 20:15:41.467003 Setting prompt string to ['Hit any key to stop autoboot']
344 20:15:41.467471 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 20:15:41.469026 Trying 192.168.56.22...
346 20:15:41.469510 Connected to conserv3.
347 20:15:41.469961 Escape character is '^]'.
348 20:15:41.470376
349 20:15:41.470796 ser2net port telnet,3002 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 20:15:41.471203
351 20:15:50.035795
352 20:15:50.041620 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
353 20:15:50.042125 Trying to boot from MMC1
354 20:15:54.088728
355 20:15:54.094820 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
356 20:15:54.095522 Trying to boot from MMC1
357 20:15:56.784111
358 20:15:56.791408 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
359 20:15:56.791980 Trying to boot from MMC1
360 20:15:57.374392
361 20:15:57.374991
362 20:15:57.379856 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
363 20:15:57.380331
364 20:15:57.380760 CPU : AM335X-GP rev 2.0
365 20:15:57.385049 Model: TI AM335x BeagleBone Black
366 20:15:57.385493 DRAM: 512 MiB
367 20:15:57.464750 Core: 160 devices, 18 uclasses, devicetree: separate
368 20:15:57.478842 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
369 20:15:57.879527 NAND: 0 MiB
370 20:15:57.890062 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
371 20:15:57.986914 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
372 20:15:58.008307 <ethaddr> not set. Validating first E-fuse MAC
373 20:15:58.038787 Net: eth2: ethernet@4a100000, eth3: usb_ether
375 20:15:58.096947 Hit any key to stop autoboot: 2
376 20:15:58.097989 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
377 20:15:58.098614 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
378 20:15:58.099102 Setting prompt string to ['=>']
379 20:15:58.099588 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
380 20:15:58.107228 0
381 20:15:58.108100 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
382 20:15:58.108603 Sending with 10 millisecond of delay
384 20:15:59.243197 => setenv autoload no
385 20:15:59.253970 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
386 20:15:59.258822 setenv autoload no
387 20:15:59.259534 Sending with 10 millisecond of delay
389 20:16:01.056296 => setenv initrd_high 0xffffffff
390 20:16:01.066802 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
391 20:16:01.067261 setenv initrd_high 0xffffffff
392 20:16:01.067705 Sending with 10 millisecond of delay
394 20:16:02.682518 => setenv fdt_high 0xffffffff
395 20:16:02.693266 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
396 20:16:02.694088 setenv fdt_high 0xffffffff
397 20:16:02.694789 Sending with 10 millisecond of delay
399 20:16:02.986500 => dhcp
400 20:16:02.997214 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
401 20:16:02.998054 dhcp
402 20:16:02.998484 link up on port 0, speed 100, full duplex
403 20:16:02.998891 BOOTP broadcast 1
404 20:16:03.251865 BOOTP broadcast 2
405 20:16:03.753904 BOOTP broadcast 3
406 20:16:04.755812 BOOTP broadcast 4
407 20:16:04.847478 DHCP client bound to address 192.168.6.8 (1845 ms)
408 20:16:04.848279 Sending with 10 millisecond of delay
410 20:16:06.525326 => setenv serverip 192.168.6.3
411 20:16:06.536189 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
412 20:16:06.537113 setenv serverip 192.168.6.3
413 20:16:06.537920 Sending with 10 millisecond of delay
415 20:16:10.023033 => tftp 0x82000000 936513/tftp-deploy-zj58j50d/kernel/zImage
416 20:16:10.033617 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:31)
417 20:16:10.034214 tftp 0x82000000 936513/tftp-deploy-zj58j50d/kernel/zImage
418 20:16:10.034450 link up on port 0, speed 100, full duplex
419 20:16:10.038286 Using ethernet@4a100000 device
420 20:16:10.044024 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
421 20:16:10.051211 Filename '936513/tftp-deploy-zj58j50d/kernel/zImage'.
422 20:16:10.051499 Load address: 0x82000000
423 20:16:12.151002 Loading: *################################################## 10.9 MiB
424 20:16:12.151642 5.2 MiB/s
425 20:16:12.152076 done
426 20:16:12.155300 Bytes transferred = 11444736 (aea200 hex)
427 20:16:12.156121 Sending with 10 millisecond of delay
429 20:16:16.607300 => tftp 0x83000000 936513/tftp-deploy-zj58j50d/ramdisk/ramdisk.cpio.gz.uboot
430 20:16:16.617875 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
431 20:16:16.618427 tftp 0x83000000 936513/tftp-deploy-zj58j50d/ramdisk/ramdisk.cpio.gz.uboot
432 20:16:16.618654 link up on port 0, speed 100, full duplex
433 20:16:16.622838 Using ethernet@4a100000 device
434 20:16:16.628475 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
435 20:16:16.636983 Filename '936513/tftp-deploy-zj58j50d/ramdisk/ramdisk.cpio.gz.uboot'.
436 20:16:16.638175 Load address: 0x83000000
437 20:16:19.353712 Loading: *################################################## 14.1 MiB
438 20:16:19.354166 5.2 MiB/s
439 20:16:19.354397 done
440 20:16:19.356996 Bytes transferred = 14791102 (e1b1be hex)
441 20:16:19.357619 Sending with 10 millisecond of delay
443 20:16:21.220391 => setenv initrd_size ${filesize}
444 20:16:21.231211 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
445 20:16:21.232094 setenv initrd_size ${filesize}
446 20:16:21.232853 Sending with 10 millisecond of delay
448 20:16:25.379088 => tftp 0x88000000 936513/tftp-deploy-zj58j50d/dtb/am335x-boneblack.dtb
449 20:16:25.390194 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
450 20:16:25.390768 tftp 0x88000000 936513/tftp-deploy-zj58j50d/dtb/am335x-boneblack.dtb
451 20:16:25.391004 link up on port 0, speed 100, full duplex
452 20:16:25.394518 Using ethernet@4a100000 device
453 20:16:25.400078 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
454 20:16:25.411764 Filename '936513/tftp-deploy-zj58j50d/dtb/am335x-boneblack.dtb'.
455 20:16:25.412104 Load address: 0x88000000
456 20:16:25.421926 Loading: *################################################## 68.9 KiB
457 20:16:25.422259 4.8 MiB/s
458 20:16:25.422486 done
459 20:16:25.429179 Bytes transferred = 70568 (113a8 hex)
460 20:16:25.429726 Sending with 10 millisecond of delay
462 20:16:38.605546 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/936513/extract-nfsrootfs-3d2g851a,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
463 20:16:38.616404 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
464 20:16:38.617299 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/936513/extract-nfsrootfs-3d2g851a,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
465 20:16:38.618003 Sending with 10 millisecond of delay
467 20:16:40.956961 => bootz 0x82000000 0x83000000 0x88000000
468 20:16:40.967733 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
469 20:16:40.968131 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
470 20:16:40.968704 bootz 0x82000000 0x83000000 0x88000000
471 20:16:40.968951 Kernel image @ 0x82000000 [ 0x000000 - 0xaea200 ]
472 20:16:40.969760 ## Loading init Ramdisk from Legacy Image at 83000000 ...
473 20:16:40.975290 Image Name:
474 20:16:40.975604 Created: 2024-11-04 20:15:41 UTC
475 20:16:40.980917 Image Type: ARM Linux RAMDisk Image (uncompressed)
476 20:16:40.986408 Data Size: 14791038 Bytes = 14.1 MiB
477 20:16:40.986740 Load Address: 00000000
478 20:16:40.992575 Entry Point: 00000000
479 20:16:41.161008 Verifying Checksum ... OK
480 20:16:41.161752 ## Flattened Device Tree blob at 88000000
481 20:16:41.167372 Booting using the fdt blob at 0x88000000
482 20:16:41.168047 Working FDT set to 88000000
483 20:16:41.173077 Using Device Tree in place at 88000000, end 880143a7
484 20:16:41.177708 Working FDT set to 88000000
485 20:16:41.191193
486 20:16:41.191949 Starting kernel ...
487 20:16:41.192613
488 20:16:41.193850 end: 2.4.3 bootloader-commands (duration 00:00:43) [common]
489 20:16:41.194737 start: 2.4.4 auto-login-action (timeout 00:04:00) [common]
490 20:16:41.195401 Setting prompt string to ['Linux version [0-9]']
491 20:16:41.196085 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
492 20:16:41.196998 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
493 20:16:42.032098 [ 0.000000] Booting Linux on physical CPU 0x0
494 20:16:42.038038 start: 2.4.4.1 login-action (timeout 00:03:59) [common]
495 20:16:42.038554 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
496 20:16:42.038906 Setting prompt string to []
497 20:16:42.039429 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
498 20:16:42.040095 Using line separator: #'\n'#
499 20:16:42.040733 No login prompt set.
500 20:16:42.041332 Parsing kernel messages
501 20:16:42.041668 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
502 20:16:42.042269 [login-action] Waiting for messages, (timeout 00:03:59)
503 20:16:42.042667 Waiting using forced prompt support (timeout 00:02:00)
504 20:16:42.055026 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j361850-arm-gcc-12-multi-v7-defconfig-cwt5f) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Mon Nov 4 16:50:05 UTC 2024
505 20:16:42.060482 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
506 20:16:42.066182 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
507 20:16:42.077548 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
508 20:16:42.083315 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
509 20:16:42.089040 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
510 20:16:42.089495 [ 0.000000] Memory policy: Data cache writeback
511 20:16:42.095888 [ 0.000000] efi: UEFI not found.
512 20:16:42.104385 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
513 20:16:42.105520 [ 0.000000] Zone ranges:
514 20:16:42.110346 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
515 20:16:42.115776 [ 0.000000] Normal empty
516 20:16:42.121549 [ 0.000000] HighMem empty
517 20:16:42.121927 [ 0.000000] Movable zone start for each node
518 20:16:42.127260 [ 0.000000] Early memory node ranges
519 20:16:42.133119 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
520 20:16:42.140831 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
521 20:16:42.166317 [ 0.000000] CPU: All CPU(s) started in SVC mode.
522 20:16:42.171924 [ 0.000000] AM335X ES2.0 (sgx neon)
523 20:16:42.183818 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
524 20:16:42.201311 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/936513/extract-nfsrootfs-3d2g851a,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
525 20:16:42.212852 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
526 20:16:42.218674 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
527 20:16:42.224356 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
528 20:16:42.234361 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
529 20:16:42.263409 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
530 20:16:42.269511 <6>[ 0.000000] trace event string verifier disabled
531 20:16:42.270104 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
532 20:16:42.277535 <6>[ 0.000000] rcu: RCU event tracing is enabled.
533 20:16:42.283203 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
534 20:16:42.294757 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
535 20:16:42.299678 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
536 20:16:42.314979 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
537 20:16:42.332098 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
538 20:16:42.338846 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
539 20:16:42.432166 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
540 20:16:42.443691 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
541 20:16:42.450348 <6>[ 0.008334] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
542 20:16:42.463424 <6>[ 0.019164] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
543 20:16:42.470987 <6>[ 0.034059] Console: colour dummy device 80x30
544 20:16:42.477072 Matched prompt #6: WARNING:
545 20:16:42.477634 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
546 20:16:42.482430 <3>[ 0.038957] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
547 20:16:42.488205 <3>[ 0.046025] This ensures that you still see kernel messages. Please
548 20:16:42.491461 <3>[ 0.052752] update your kernel commandline.
549 20:16:42.531941 <6>[ 0.057365] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
550 20:16:42.537727 <6>[ 0.096169] CPU: Testing write buffer coherency: ok
551 20:16:42.543718 <6>[ 0.101534] CPU0: Spectre v2: using BPIALL workaround
552 20:16:42.544173 <6>[ 0.107000] pid_max: default: 32768 minimum: 301
553 20:16:42.555098 <6>[ 0.112195] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
554 20:16:42.562127 <6>[ 0.120018] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
555 20:16:42.569209 <6>[ 0.129371] CPU0: thread -1, cpu 0, socket -1, mpidr 0
556 20:16:42.577542 <6>[ 0.136360] Setting up static identity map for 0x80300000 - 0x803000ac
557 20:16:42.583332 <6>[ 0.146003] rcu: Hierarchical SRCU implementation.
558 20:16:42.590997 <6>[ 0.151282] rcu: Max phase no-delay instances is 1000.
559 20:16:42.599557 <6>[ 0.162488] EFI services will not be available.
560 20:16:42.605470 <6>[ 0.167769] smp: Bringing up secondary CPUs ...
561 20:16:42.611147 <6>[ 0.172812] smp: Brought up 1 node, 1 CPU
562 20:16:42.616946 <6>[ 0.177212] SMP: Total of 1 processors activated (996.14 BogoMIPS).
563 20:16:42.622832 <6>[ 0.183980] CPU: All CPU(s) started in SVC mode.
564 20:16:42.643207 <6>[ 0.189162] Memory: 405996K/522240K available (16384K kernel code, 2543K rwdata, 6788K rodata, 2048K init, 430K bss, 49052K reserved, 65536K cma-reserved, 0K highmem)
565 20:16:42.643723 <6>[ 0.205440] devtmpfs: initialized
566 20:16:42.665514 <6>[ 0.222583] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
567 20:16:42.677008 <6>[ 0.231165] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
568 20:16:42.682957 <6>[ 0.241623] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
569 20:16:42.693666 <6>[ 0.253906] pinctrl core: initialized pinctrl subsystem
570 20:16:42.703076 <6>[ 0.264579] DMI not present or invalid.
571 20:16:42.711329 <6>[ 0.270434] NET: Registered PF_NETLINK/PF_ROUTE protocol family
572 20:16:42.720861 <6>[ 0.279371] DMA: preallocated 256 KiB pool for atomic coherent allocations
573 20:16:42.735972 <6>[ 0.290965] thermal_sys: Registered thermal governor 'step_wise'
574 20:16:42.736498 <6>[ 0.291130] cpuidle: using governor menu
575 20:16:42.763584 <6>[ 0.326716] No ATAGs?
576 20:16:42.769976 <6>[ 0.329357] hw-breakpoint: debug architecture 0x4 unsupported.
577 20:16:42.780004 <6>[ 0.341395] Serial: AMBA PL011 UART driver
578 20:16:42.811951 <6>[ 0.375061] iommu: Default domain type: Translated
579 20:16:42.821046 <6>[ 0.380406] iommu: DMA domain TLB invalidation policy: strict mode
580 20:16:42.848552 <5>[ 0.411035] SCSI subsystem initialized
581 20:16:42.854310 <6>[ 0.415916] usbcore: registered new interface driver usbfs
582 20:16:42.860105 <6>[ 0.421940] usbcore: registered new interface driver hub
583 20:16:42.866897 <6>[ 0.427721] usbcore: registered new device driver usb
584 20:16:42.872753 <6>[ 0.434224] pps_core: LinuxPPS API ver. 1 registered
585 20:16:42.884132 <6>[ 0.439654] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
586 20:16:42.891321 <6>[ 0.449337] PTP clock support registered
587 20:16:42.891898 <6>[ 0.453794] EDAC MC: Ver: 3.0.0
588 20:16:42.939170 <6>[ 0.499830] scmi_core: SCMI protocol bus registered
589 20:16:42.954700 <6>[ 0.517140] vgaarb: loaded
590 20:16:42.960831 <6>[ 0.520961] clocksource: Switched to clocksource dmtimer
591 20:16:43.003402 <6>[ 0.566300] NET: Registered PF_INET protocol family
592 20:16:43.016076 <6>[ 0.571963] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
593 20:16:43.021751 <6>[ 0.580767] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
594 20:16:43.033208 <6>[ 0.589701] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
595 20:16:43.039029 <6>[ 0.597962] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
596 20:16:43.050499 <6>[ 0.606249] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
597 20:16:43.056370 <6>[ 0.613974] TCP: Hash tables configured (established 4096 bind 4096)
598 20:16:43.062143 <6>[ 0.620874] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
599 20:16:43.067997 <6>[ 0.627911] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
600 20:16:43.075671 <6>[ 0.635514] NET: Registered PF_UNIX/PF_LOCAL protocol family
601 20:16:43.152408 <6>[ 0.709986] RPC: Registered named UNIX socket transport module.
602 20:16:43.152989 <6>[ 0.716418] RPC: Registered udp transport module.
603 20:16:43.158165 <6>[ 0.721547] RPC: Registered tcp transport module.
604 20:16:43.163885 <6>[ 0.726650] RPC: Registered tcp-with-tls transport module.
605 20:16:43.176866 <6>[ 0.732572] RPC: Registered tcp NFSv4.1 backchannel transport module.
606 20:16:43.177406 <6>[ 0.739477] PCI: CLS 0 bytes, default 64
607 20:16:43.184082 <5>[ 0.745248] Initialise system trusted keyrings
608 20:16:43.205066 <6>[ 0.765279] Trying to unpack rootfs image as initramfs...
609 20:16:43.284383 <6>[ 0.841381] workingset: timestamp_bits=30 max_order=17 bucket_order=0
610 20:16:43.289148 <6>[ 0.848889] squashfs: version 4.0 (2009/01/31) Phillip Lougher
611 20:16:43.328195 <5>[ 0.891421] NFS: Registering the id_resolver key type
612 20:16:43.334091 <5>[ 0.897010] Key type id_resolver registered
613 20:16:43.339788 <5>[ 0.901676] Key type id_legacy registered
614 20:16:43.348256 <6>[ 0.906113] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
615 20:16:43.355188 <6>[ 0.913310] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
616 20:16:43.424297 <5>[ 0.987535] Key type asymmetric registered
617 20:16:43.430135 <5>[ 0.992111] Asymmetric key parser 'x509' registered
618 20:16:43.438526 <6>[ 0.997537] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
619 20:16:43.444205 <6>[ 1.005453] io scheduler mq-deadline registered
620 20:16:43.452149 <6>[ 1.010385] io scheduler kyber registered
621 20:16:43.452508 <6>[ 1.014867] io scheduler bfq registered
622 20:16:43.557447 <6>[ 1.116953] ledtrig-cpu: registered to indicate activity on CPUs
623 20:16:43.832446 <6>[ 1.391696] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
624 20:16:43.862928 <6>[ 1.425887] msm_serial: driver initialized
625 20:16:43.869003 <6>[ 1.430666] SuperH (H)SCI(F) driver initialized
626 20:16:43.874932 <6>[ 1.436015] STMicroelectronics ASC driver initialized
627 20:16:43.880128 <6>[ 1.441687] STM32 USART driver initialized
628 20:16:43.981629 <6>[ 1.544099] brd: module loaded
629 20:16:44.025856 <6>[ 1.588146] loop: module loaded
630 20:16:44.066530 <6>[ 1.628840] CAN device driver interface
631 20:16:44.073125 <6>[ 1.634015] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
632 20:16:44.078949 <6>[ 1.640985] e1000e: Intel(R) PRO/1000 Network Driver
633 20:16:44.085735 <6>[ 1.646373] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
634 20:16:44.091477 <6>[ 1.652802] igb: Intel(R) Gigabit Ethernet Network Driver
635 20:16:44.098651 <6>[ 1.658625] igb: Copyright (c) 2007-2014 Intel Corporation.
636 20:16:44.110411 <6>[ 1.667811] pegasus: Pegasus/Pegasus II USB Ethernet driver
637 20:16:44.116219 <6>[ 1.673982] usbcore: registered new interface driver pegasus
638 20:16:44.119037 <6>[ 1.680109] usbcore: registered new interface driver asix
639 20:16:44.124743 <6>[ 1.685997] usbcore: registered new interface driver ax88179_178a
640 20:16:44.130498 <6>[ 1.692584] usbcore: registered new interface driver cdc_ether
641 20:16:44.136291 <6>[ 1.698877] usbcore: registered new interface driver smsc75xx
642 20:16:44.147780 <6>[ 1.705106] usbcore: registered new interface driver smsc95xx
643 20:16:44.153569 <6>[ 1.711346] usbcore: registered new interface driver net1080
644 20:16:44.159376 <6>[ 1.717465] usbcore: registered new interface driver cdc_subset
645 20:16:44.165133 <6>[ 1.723884] usbcore: registered new interface driver zaurus
646 20:16:44.170120 <6>[ 1.729927] usbcore: registered new interface driver cdc_ncm
647 20:16:44.179819 <6>[ 1.739349] usbcore: registered new interface driver usb-storage
648 20:16:44.189214 <6>[ 1.750392] i2c_dev: i2c /dev entries driver
649 20:16:44.213553 <5>[ 1.768737] cpuidle: enable-method property 'ti,am3352' found operations
650 20:16:44.219538 <6>[ 1.778303] sdhci: Secure Digital Host Controller Interface driver
651 20:16:44.227129 <6>[ 1.785081] sdhci: Copyright(c) Pierre Ossman
652 20:16:44.234341 <6>[ 1.791693] Synopsys Designware Multimedia Card Interface Driver
653 20:16:44.239875 <6>[ 1.799620] sdhci-pltfm: SDHCI platform and OF driver helper
654 20:16:44.253908 <6>[ 1.809538] usbcore: registered new interface driver usbhid
655 20:16:44.254449 <6>[ 1.815660] usbhid: USB HID core driver
656 20:16:44.266848 <6>[ 1.827383] NET: Registered PF_INET6 protocol family
657 20:16:44.730246 <6>[ 2.293268] Segment Routing with IPv6
658 20:16:44.735977 <6>[ 2.297415] In-situ OAM (IOAM) with IPv6
659 20:16:44.742659 <6>[ 2.301954] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
660 20:16:44.750083 <6>[ 2.309219] NET: Registered PF_PACKET protocol family
661 20:16:44.755981 <6>[ 2.314796] can: controller area network core
662 20:16:44.756633 <6>[ 2.319619] NET: Registered PF_CAN protocol family
663 20:16:44.761710 <6>[ 2.324846] can: raw protocol
664 20:16:44.764332 <6>[ 2.328173] can: broadcast manager protocol
665 20:16:44.770848 <6>[ 2.332775] can: netlink gateway - max_hops=1
666 20:16:44.776991 <5>[ 2.338253] Key type dns_resolver registered
667 20:16:44.782699 <6>[ 2.343326] ThumbEE CPU extension supported.
668 20:16:44.788972 <5>[ 2.348011] Registering SWP/SWPB emulation handler
669 20:16:44.794461 <3>[ 2.353703] omap_voltage_late_init: Voltage driver support not added
670 20:16:44.991258 <5>[ 2.551963] Loading compiled-in X.509 certificates
671 20:16:45.119442 <6>[ 2.669572] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
672 20:16:45.126539 <6>[ 2.686228] pinctrl-single 44e10800.pinmux: 142 pins, size 568
673 20:16:45.152855 <3>[ 2.709904] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
674 20:16:45.353293 <3>[ 2.910288] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
675 20:16:45.559992 <6>[ 3.121499] OMAP GPIO hardware version 0.1
676 20:16:45.580563 <6>[ 3.140084] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
677 20:16:45.674965 <4>[ 3.234130] at24 2-0054: supply vcc not found, using dummy regulator
678 20:16:45.743276 <4>[ 3.302475] at24 2-0055: supply vcc not found, using dummy regulator
679 20:16:45.777698 <4>[ 3.336892] at24 2-0056: supply vcc not found, using dummy regulator
680 20:16:45.820201 <4>[ 3.379513] at24 2-0057: supply vcc not found, using dummy regulator
681 20:16:45.855959 <6>[ 3.415937] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
682 20:16:45.931106 <3>[ 3.487112] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
683 20:16:45.955757 <6>[ 3.507963] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
684 20:16:45.976234 <4>[ 3.534080] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
685 20:16:45.994505 <4>[ 3.552405] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
686 20:16:46.131784 <6>[ 3.691163] omap_rng 48310000.rng: Random Number Generator ver. 20
687 20:16:46.155367 <5>[ 3.717460] random: crng init done
688 20:16:46.218075 <6>[ 3.780423] Freeing initrd memory: 14448K
689 20:16:46.227322 <6>[ 3.785122] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
690 20:16:46.276494 <6>[ 3.833436] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
691 20:16:46.282264 <6>[ 3.843786] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
692 20:16:46.293995 <6>[ 3.851153] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
693 20:16:46.299822 <6>[ 3.858614] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
694 20:16:46.311362 <6>[ 3.866759] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
695 20:16:46.318762 <6>[ 3.878396] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:00:92
696 20:16:46.331883 <5>[ 3.887408] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
697 20:16:46.359646 <3>[ 3.917175] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
698 20:16:46.365408 <6>[ 3.925770] edma 49000000.dma: TI EDMA DMA engine driver
699 20:16:46.436470 <3>[ 3.993310] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
700 20:16:46.451139 <6>[ 4.007625] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
701 20:16:46.464066 <3>[ 4.024712] l3-aon-clkctrl:0000:0: failed to disable
702 20:16:46.517334 <6>[ 4.074801] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
703 20:16:46.523009 <6>[ 4.084313] printk: legacy console [ttyS0] enabled
704 20:16:46.525734 <6>[ 4.084313] printk: legacy console [ttyS0] enabled
705 20:16:46.531328 <6>[ 4.094647] printk: legacy bootconsole [omap8250] disabled
706 20:16:46.540299 <6>[ 4.094647] printk: legacy bootconsole [omap8250] disabled
707 20:16:46.575308 <4>[ 4.131756] tps65217-pmic: Failed to locate of_node [id: -1]
708 20:16:46.578845 <4>[ 4.139163] tps65217-bl: Failed to locate of_node [id: -1]
709 20:16:46.595230 <6>[ 4.158676] tps65217 0-0024: TPS65217 ID 0xe version 1.2
710 20:16:46.613556 <6>[ 4.165626] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
711 20:16:46.625324 <6>[ 4.179313] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
712 20:16:46.631017 <6>[ 4.191209] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
713 20:16:46.653253 <6>[ 4.211131] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
714 20:16:46.659104 <6>[ 4.220189] sdhci-omap 48060000.mmc: Got CD GPIO
715 20:16:46.667129 <4>[ 4.225380] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
716 20:16:46.681904 <4>[ 4.238827] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
717 20:16:46.688440 <4>[ 4.247767] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
718 20:16:46.698308 <4>[ 4.256564] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
719 20:16:46.821702 <6>[ 4.380640] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
720 20:16:46.867335 <6>[ 4.423984] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
721 20:16:46.873845 <6>[ 4.433370] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
722 20:16:46.883096 <6>[ 4.442307] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
723 20:16:46.956026 <6>[ 4.508617] mmc1: new high speed MMC card at address 0001
724 20:16:46.956594 <6>[ 4.517325] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
725 20:16:46.973267 <6>[ 4.529521] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
726 20:16:46.981121 <6>[ 4.542061] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
727 20:16:46.996796 <6>[ 4.557731] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
728 20:16:47.013070 <6>[ 4.566450] mmc0: new high speed SDHC card at address aaaa
729 20:16:47.013535 <6>[ 4.574400] mmcblk0: mmc0:aaaa SU16G 14.8 GiB
730 20:16:47.021838 <6>[ 4.581469] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
731 20:16:47.030158 <6>[ 4.591436] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 >
732 20:16:49.124547 <6>[ 6.682015] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
733 20:16:49.228002 <5>[ 6.710984] Sending DHCP requests ., OK
734 20:16:49.239317 <6>[ 6.795451] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.8
735 20:16:49.239890 <6>[ 6.803535] IP-Config: Complete:
736 20:16:49.250557 <6>[ 6.807072] device=eth0, hwaddr=90:59:af:5b:00:92, ipaddr=192.168.6.8, mask=255.255.255.0, gw=192.168.6.1
737 20:16:49.256240 <6>[ 6.817503] host=192.168.6.8, domain=, nis-domain=(none)
738 20:16:49.261992 <6>[ 6.823627] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
739 20:16:49.268749 <6>[ 6.823661] nameserver0=10.255.253.1
740 20:16:49.274721 <6>[ 6.836231] clk: Disabling unused clocks
741 20:16:49.280187 <6>[ 6.840837] PM: genpd: Disabling unused power domains
742 20:16:49.299890 <6>[ 6.859632] Freeing unused kernel image (initmem) memory: 2048K
743 20:16:49.307293 <6>[ 6.869351] Run /init as init process
744 20:16:49.333005 Loading, please wait...
745 20:16:49.408509 Starting systemd-udevd version 252.22-1~deb12u1
746 20:16:52.502908 <4>[ 10.059032] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
747 20:16:52.678218 <4>[ 10.234423] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
748 20:16:52.831328 <6>[ 10.395018] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
749 20:16:52.842126 <6>[ 10.400692] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
750 20:16:53.032990 <6>[ 10.595159] hub 1-0:1.0: USB hub found
751 20:16:53.038694 <6>[ 10.600644] tda998x 0-0070: found TDA19988
752 20:16:53.060881 <6>[ 10.622903] hub 1-0:1.0: 1 port detected
753 20:16:56.232336 Begin: Loading essential drivers ... done.
754 20:16:56.237731 Begin: Running /scripts/init-premount ... done.
755 20:16:56.243492 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
756 20:16:56.253878 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
757 20:16:56.262637 Device /sys/class/net/eth0 found
758 20:16:56.263086 done.
759 20:16:56.321356 Begin: Waiting up to 180 secs for any network device to become available ... done.
760 20:16:56.401299 IP-Config: eth0 hardware address 90:59:af:5b:00:92 mtu 1500 DHCP
761 20:16:56.515577 IP-Config: eth0 guessed broadcast address 192.168.6.255
762 20:16:56.520967 IP-Config: eth0 complete (dhcp from 192.168.6.1):
763 20:16:56.526524 address: 192.168.6.8 broadcast: 192.168.6.255 netmask: 255.255.255.0
764 20:16:56.537763 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
765 20:16:56.538309 rootserver: 192.168.6.1 rootpath:
766 20:16:56.541355 filename :
767 20:16:56.631556 done.
768 20:16:56.641901 Begin: Running /scripts/nfs-bottom ... done.
769 20:16:56.717600 Begin: Running /scripts/init-bottom ... done.
770 20:16:58.201119 <30>[ 15.760399] systemd[1]: System time before build time, advancing clock.
771 20:16:58.362786 <30>[ 15.895826] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
772 20:16:58.371495 <30>[ 15.932527] systemd[1]: Detected architecture arm.
773 20:16:58.383487
774 20:16:58.383951 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
775 20:16:58.384368
776 20:16:58.411701 <30>[ 15.971522] systemd[1]: Hostname set to <debian-bookworm-armhf>.
777 20:17:00.553097 <30>[ 18.111804] systemd[1]: Queued start job for default target graphical.target.
778 20:17:00.570320 <30>[ 18.126809] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
779 20:17:00.577901 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
780 20:17:00.607976 <30>[ 18.163747] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
781 20:17:00.615451 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
782 20:17:00.640016 <30>[ 18.197105] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
783 20:17:00.652418 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
784 20:17:00.675240 <30>[ 18.232824] systemd[1]: Created slice user.slice - User and Session Slice.
785 20:17:00.681963 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
786 20:17:00.710833 <30>[ 18.262386] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
787 20:17:00.716919 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
788 20:17:00.734700 <30>[ 18.292093] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
789 20:17:00.742641 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
790 20:17:00.775681 <30>[ 18.322066] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
791 20:17:00.782241 <30>[ 18.342594] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
792 20:17:00.790654 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
793 20:17:00.813891 <30>[ 18.371448] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
794 20:17:00.822117 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
795 20:17:00.844505 <30>[ 18.401833] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
796 20:17:00.853081 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
797 20:17:00.874466 <30>[ 18.432026] systemd[1]: Reached target paths.target - Path Units.
798 20:17:00.879546 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
799 20:17:00.903981 <30>[ 18.461589] systemd[1]: Reached target remote-fs.target - Remote File Systems.
800 20:17:00.911390 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
801 20:17:00.933969 <30>[ 18.491504] systemd[1]: Reached target slices.target - Slice Units.
802 20:17:00.939323 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
803 20:17:00.964305 <30>[ 18.521691] systemd[1]: Reached target swap.target - Swaps.
804 20:17:00.968176 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
805 20:17:00.994433 <30>[ 18.551727] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
806 20:17:01.003373 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
807 20:17:01.025584 <30>[ 18.582701] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
808 20:17:01.033882 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
809 20:17:01.112471 <30>[ 18.664927] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
810 20:17:01.125313 <30>[ 18.682676] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
811 20:17:01.133735 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
812 20:17:01.157210 <30>[ 18.713645] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
813 20:17:01.164547 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
814 20:17:01.186672 <30>[ 18.743968] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
815 20:17:01.194868 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
816 20:17:01.219711 <30>[ 18.775888] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
817 20:17:01.225332 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
818 20:17:01.256649 <30>[ 18.812706] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
819 20:17:01.264196 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
820 20:17:01.291512 <30>[ 18.842734] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
821 20:17:01.310028 <30>[ 18.861341] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
822 20:17:01.354396 <30>[ 18.912514] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
823 20:17:01.376463 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
824 20:17:01.436405 <30>[ 18.994451] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
825 20:17:01.456454 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
826 20:17:01.535260 <30>[ 19.092343] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
827 20:17:01.562907 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
828 20:17:01.614920 <30>[ 19.172615] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
829 20:17:01.633051 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
830 20:17:01.664732 <30>[ 19.222803] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
831 20:17:01.694977 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
832 20:17:01.743685 <30>[ 19.302258] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
833 20:17:01.761247 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
834 20:17:01.827305 <30>[ 19.384272] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
835 20:17:01.854255 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
836 20:17:01.904526 <30>[ 19.462825] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
837 20:17:01.923689 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
838 20:17:01.951736 <30>[ 19.510147] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
839 20:17:01.983111 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
840 20:17:02.010858 <28>[ 19.563259] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
841 20:17:02.019357 <28>[ 19.576888] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
842 20:17:02.063601 <30>[ 19.622409] systemd[1]: Starting systemd-journald.service - Journal Service...
843 20:17:02.082553 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
844 20:17:02.157739 <30>[ 19.715838] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
845 20:17:02.184631 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
846 20:17:02.235815 <30>[ 19.794151] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
847 20:17:02.284017 Starting [0;1;39msystemd-network-g… units from Kernel command line...
848 20:17:02.349322 <30>[ 19.906134] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
849 20:17:02.400129 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
850 20:17:02.466609 <30>[ 20.024131] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
851 20:17:02.514161 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
852 20:17:02.585181 <30>[ 20.143638] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
853 20:17:02.634081 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
854 20:17:02.655941 <30>[ 20.214253] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
855 20:17:02.679681 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
856 20:17:02.699185 <30>[ 20.256421] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
857 20:17:02.726601 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
858 20:17:02.876383 <30>[ 20.435381] systemd[1]: modprobe@configfs.service: Deactivated successfully.
859 20:17:02.915000 <30>[ 20.472870] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
860 20:17:02.943814 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
861 20:17:02.964997 <30>[ 20.522626] systemd[1]: Started systemd-journald.service - Journal Service.
862 20:17:02.971822 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
863 20:17:03.015439 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
864 20:17:03.045202 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
865 20:17:03.075360 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
866 20:17:03.099671 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
867 20:17:03.135195 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
868 20:17:03.164335 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
869 20:17:03.186435 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
870 20:17:03.207308 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
871 20:17:03.239904 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
872 20:17:03.303535 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
873 20:17:03.346079 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
874 20:17:03.415736 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
875 20:17:03.503952 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
876 20:17:03.584146 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
877 20:17:03.737991 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kerne<46>[ 21.291923] systemd-journald[164]: Received client request to flush runtime journal.
878 20:17:03.738656 l Configuration File System.
879 20:17:03.829893 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
880 20:17:03.978896 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
881 20:17:05.025457 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
882 20:17:05.086221 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
883 20:17:05.469278 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
884 20:17:05.656384 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
885 20:17:05.685045 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
886 20:17:05.703813 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
887 20:17:05.775264 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
888 20:17:05.810495 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
889 20:17:06.734376 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
890 20:17:06.806531 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
891 20:17:07.004180 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
892 20:17:07.105244 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
893 20:17:07.233533 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
894 20:17:09.280853 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
895 20:17:09.703871 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
896 20:17:09.755578 <5>[ 27.314001] cfg80211: Loading compiled-in X.509 certificates for regulatory database
897 20:17:10.558228 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
898 20:17:10.792445 <5>[ 28.352890] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
899 20:17:10.863705 <5>[ 28.422718] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
900 20:17:10.883290 <4>[ 28.441259] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
901 20:17:10.889252 <6>[ 28.450720] cfg80211: failed to load regulatory.db
902 20:17:11.961689 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
903 20:17:11.988561 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
904 20:17:12.061927 <46>[ 29.610506] systemd-journald[164]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
905 20:17:12.229681 <46>[ 29.781261] systemd-journald[164]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
906 20:17:21.438609 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
907 20:17:21.470344 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
908 20:17:21.496027 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
909 20:17:21.516163 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
910 20:17:21.589310 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
911 20:17:21.635963 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
912 20:17:21.707655 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
913 20:17:21.743947 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
914 20:17:21.799775 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
915 20:17:21.830051 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
916 20:17:21.871506 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
917 20:17:21.898187 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
918 20:17:21.940296 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
919 20:17:21.971524 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
920 20:17:22.004838 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
921 20:17:22.035492 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
922 20:17:22.065258 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
923 20:17:22.089736 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
924 20:17:22.115786 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
925 20:17:22.134510 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
926 20:17:22.171277 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
927 20:17:22.194533 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
928 20:17:22.216663 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
929 20:17:22.293687 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
930 20:17:22.318587 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
931 20:17:22.403871 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
932 20:17:22.499564 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
933 20:17:22.575372 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
934 20:17:22.618863 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
935 20:17:22.634570 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
936 20:17:22.842664 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
937 20:17:22.914598 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
938 20:17:22.953943 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
939 20:17:22.972941 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
940 20:17:23.002609 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
941 20:17:23.230600 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
942 20:17:23.581151 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
943 20:17:23.634868 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
944 20:17:23.659787 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
945 20:17:23.743077 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
946 20:17:23.917182 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
947 20:17:24.060354
948 20:17:24.063714 Debian GNU/Linux 12 dworm-armhf login: root (automatic login)
949 20:17:24.064020
950 20:17:24.350011 Linux debian-bookworm-armhf 6.12.0-rc6 #1 SMP Mon Nov 4 16:50:05 UTC 2024 armv7l
951 20:17:24.350855
952 20:17:24.355664 The programs included with the Debian GNU/Linux system are free software;
953 20:17:24.361258 the exact distribution terms for each program are described in the
954 20:17:24.366906 individual files in /usr/share/doc/*/copyright.
955 20:17:24.367450
956 20:17:24.374805 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
957 20:17:24.375343 permitted by applicable law.
958 20:17:29.405291 Unable to match end of the kernel message
960 20:17:29.406203 Setting prompt string to ['/ #']
961 20:17:29.406518 end: 2.4.4.1 login-action (duration 00:00:47) [common]
963 20:17:29.407278 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
964 20:17:29.407583 start: 2.4.5 expect-shell-connection (timeout 00:03:12) [common]
965 20:17:29.407808 Setting prompt string to ['/ #']
966 20:17:29.408009 Forcing a shell prompt, looking for ['/ #']
968 20:17:29.458579 / #
969 20:17:29.459344 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
970 20:17:29.460024 Waiting using forced prompt support (timeout 00:02:30)
971 20:17:29.467190
972 20:17:29.468057 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
973 20:17:29.468619 start: 2.4.6 export-device-env (timeout 00:03:12) [common]
974 20:17:29.469105 Sending with 10 millisecond of delay
976 20:17:34.459897 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/936513/extract-nfsrootfs-3d2g851a'
977 20:17:34.470939 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/936513/extract-nfsrootfs-3d2g851a'
978 20:17:34.472050 Sending with 10 millisecond of delay
980 20:17:36.570518 / # export NFS_SERVER_IP='192.168.6.3'
981 20:17:36.581474 export NFS_SERVER_IP='192.168.6.3'
982 20:17:36.582502 end: 2.4.6 export-device-env (duration 00:00:07) [common]
983 20:17:36.583156 end: 2.4 uboot-commands (duration 00:01:55) [common]
984 20:17:36.583811 end: 2 uboot-action (duration 00:01:55) [common]
985 20:17:36.584440 start: 3 lava-test-retry (timeout 00:06:53) [common]
986 20:17:36.585079 start: 3.1 lava-test-shell (timeout 00:06:53) [common]
987 20:17:36.585587 Using namespace: common
989 20:17:36.686908 / # #
990 20:17:36.687683 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
991 20:17:36.691473 #
992 20:17:36.696108 Using /lava-936513
994 20:17:36.797342 / # export SHELL=/bin/bash
995 20:17:36.802997 export SHELL=/bin/bash
997 20:17:36.910400 / # . /lava-936513/environment
998 20:17:36.916081 . /lava-936513/environment
1000 20:17:37.029584 / # /lava-936513/bin/lava-test-runner /lava-936513/0
1001 20:17:37.030383 Test shell timeout: 10s (minimum of the action and connection timeout)
1002 20:17:37.035305 /lava-936513/bin/lava-test-runner /lava-936513/0
1003 20:17:37.411351 + export TESTRUN_ID=0_timesync-off
1004 20:17:37.419275 + TESTRUN_ID=0_timesync-off
1005 20:17:37.419813 + cd /lava-936513/0/tests/0_timesync-off
1006 20:17:37.420312 ++ cat uuid
1007 20:17:37.435519 + UUID=936513_1.6.2.4.1
1008 20:17:37.436110 + set +x
1009 20:17:37.444088 <LAVA_SIGNAL_STARTRUN 0_timesync-off 936513_1.6.2.4.1>
1010 20:17:37.444646 + systemctl stop systemd-timesyncd
1011 20:17:37.445436 Received signal: <STARTRUN> 0_timesync-off 936513_1.6.2.4.1
1012 20:17:37.446005 Starting test lava.0_timesync-off (936513_1.6.2.4.1)
1013 20:17:37.446627 Skipping test definition patterns.
1014 20:17:37.734793 + set +x
1015 20:17:37.735443 <LAVA_SIGNAL_ENDRUN 0_timesync-off 936513_1.6.2.4.1>
1016 20:17:37.736188 Received signal: <ENDRUN> 0_timesync-off 936513_1.6.2.4.1
1017 20:17:37.736737 Ending use of test pattern.
1018 20:17:37.737202 Ending test lava.0_timesync-off (936513_1.6.2.4.1), duration 0.29
1020 20:17:37.903359 + export TESTRUN_ID=1_kselftest-dt
1021 20:17:37.910714 + TESTRUN_ID=1_kselftest-dt
1022 20:17:37.911278 + cd /lava-936513/0/tests/1_kselftest-dt
1023 20:17:37.911771 ++ cat uuid
1024 20:17:37.927579 + UUID=936513_1.6.2.4.5
1025 20:17:37.928210 + set +x
1026 20:17:37.936094 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 936513_1.6.2.4.5>
1027 20:17:37.936681 + cd ./automated/linux/kselftest/
1028 20:17:37.937447 Received signal: <STARTRUN> 1_kselftest-dt 936513_1.6.2.4.5
1029 20:17:37.938029 Starting test lava.1_kselftest-dt (936513_1.6.2.4.5)
1030 20:17:37.938657 Skipping test definition patterns.
1031 20:17:37.963474 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/pm/testing/v6.12-rc6-95-g6db936d4ac0f/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g pm -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1032 20:17:38.070341 INFO: install_deps skipped
1033 20:17:38.588621 --2024-11-04 20:17:38-- http://storage.kernelci.org/pm/testing/v6.12-rc6-95-g6db936d4ac0f/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1034 20:17:38.613971 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1035 20:17:38.753002 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1036 20:17:38.888282 HTTP request sent, awaiting response... 200 OK
1037 20:17:38.888678 Length: 4105992 (3.9M) [application/octet-stream]
1038 20:17:38.893845 Saving to: 'kselftest_armhf.tar.gz'
1039 20:17:38.894155
1040 20:17:41.050058
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 186KB/s
kselftest_armhf.tar 5%[> ] 218.67K 404KB/s
kselftest_armhf.tar 18%[==> ] 740.82K 866KB/s
kselftest_armhf.tar 27%[====> ] 1.07M 1019KB/s
kselftest_armhf.tar 36%[======> ] 1.44M 1.08MB/s
kselftest_armhf.tar 66%[============> ] 2.61M 1.62MB/s
kselftest_armhf.tar 85%[================> ] 3.37M 1.82MB/s
kselftest_armhf.tar 93%[=================> ] 3.66M 1.77MB/s
kselftest_armhf.tar 100%[===================>] 3.92M 1.82MB/s in 2.2s
1041 20:17:41.050752
1042 20:17:41.736508 2024-11-04 20:17:41 (1.82 MB/s) - 'kselftest_armhf.tar.gz' saved [4105992/4105992]
1043 20:17:41.737141
1044 20:17:56.528379 skiplist:
1045 20:17:56.529007 ========================================
1046 20:17:56.534096 ========================================
1047 20:17:56.649113 dt:test_unprobed_devices.sh
1048 20:17:56.681915 ============== Tests to run ===============
1049 20:17:56.689551 dt:test_unprobed_devices.sh
1050 20:17:56.693557 ===========End Tests to run ===============
1051 20:17:56.702645 shardfile-dt pass
1052 20:17:56.933644 <12>[ 74.496748] kselftest: Running tests in dt
1053 20:17:56.961511 TAP version 13
1054 20:17:56.984723 1..1
1055 20:17:57.037574 # timeout set to 45
1056 20:17:57.037989 # selftests: dt: test_unprobed_devices.sh
1057 20:17:57.920526 # TAP version 13
1058 20:18:22.743485 # 1..257
1059 20:18:22.911584 # ok 1 / # SKIP
1060 20:18:22.933725 # ok 2 /clk_mcasp0
1061 20:18:23.004671 # ok 3 /clk_mcasp0_fixed # SKIP
1062 20:18:23.080385 # ok 4 /cpus/cpu@0 # SKIP
1063 20:18:23.151958 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1064 20:18:23.172589 # ok 6 /fixedregulator0
1065 20:18:23.188356 # ok 7 /leds
1066 20:18:23.212408 # ok 8 /ocp
1067 20:18:23.234265 # ok 9 /ocp/interconnect@44c00000
1068 20:18:23.261789 # ok 10 /ocp/interconnect@44c00000/segment@0
1069 20:18:23.284455 # ok 11 /ocp/interconnect@44c00000/segment@100000
1070 20:18:23.304916 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1071 20:18:23.379269 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1072 20:18:23.403477 # ok 14 /ocp/interconnect@44c00000/segment@200000
1073 20:18:23.421840 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1074 20:18:23.529408 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1075 20:18:23.598906 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1076 20:18:23.673033 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1077 20:18:23.742221 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1078 20:18:23.816619 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1079 20:18:23.889147 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1080 20:18:23.961337 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1081 20:18:24.034340 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1082 20:18:24.104049 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1083 20:18:24.177910 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1084 20:18:24.247636 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1085 20:18:24.318995 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1086 20:18:24.390270 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1087 20:18:24.463634 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1088 20:18:24.533567 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1089 20:18:24.604345 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1090 20:18:24.676051 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1091 20:18:24.747597 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1092 20:18:24.817947 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1093 20:18:24.890384 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1094 20:18:24.963744 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1095 20:18:25.037371 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1096 20:18:25.109028 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1097 20:18:25.180038 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1098 20:18:25.251114 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1099 20:18:25.318136 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1100 20:18:25.392386 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1101 20:18:25.461963 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1102 20:18:25.533290 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1103 20:18:25.602542 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1104 20:18:25.674799 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1105 20:18:25.746001 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1106 20:18:25.817120 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1107 20:18:25.888847 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1108 20:18:25.960457 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1109 20:18:26.032019 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1110 20:18:26.102175 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1111 20:18:26.173782 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1112 20:18:26.246817 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1113 20:18:26.317477 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1114 20:18:26.388951 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1115 20:18:26.460205 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1116 20:18:26.529428 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1117 20:18:26.603300 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1118 20:18:26.678552 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1119 20:18:26.749946 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1120 20:18:26.821187 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1121 20:18:26.890833 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1122 20:18:26.960636 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1123 20:18:27.035330 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1124 20:18:27.108151 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1125 20:18:27.179845 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1126 20:18:27.246974 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1127 20:18:27.317022 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1128 20:18:27.391801 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1129 20:18:27.460869 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1130 20:18:27.535747 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1131 20:18:27.607640 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1132 20:18:27.678613 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1133 20:18:27.749717 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1134 20:18:27.820941 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1135 20:18:27.896373 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1136 20:18:27.968310 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1137 20:18:28.040402 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1138 20:18:28.111889 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1139 20:18:28.181194 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1140 20:18:28.254296 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1141 20:18:28.322187 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1142 20:18:28.393856 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1143 20:18:28.464528 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1144 20:18:28.535405 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1145 20:18:28.606195 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1146 20:18:28.676093 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1147 20:18:28.753169 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1148 20:18:28.822984 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1149 20:18:28.891803 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1150 20:18:28.968839 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1151 20:18:29.040627 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1152 20:18:29.112721 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1153 20:18:29.132411 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1154 20:18:29.152969 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1155 20:18:29.177293 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1156 20:18:29.200719 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1157 20:18:29.224394 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1158 20:18:29.248465 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1159 20:18:29.272661 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1160 20:18:29.293607 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1161 20:18:29.399851 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1162 20:18:29.425466 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1163 20:18:29.456501 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1164 20:18:29.480162 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1165 20:18:29.585734 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1166 20:18:29.657408 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1167 20:18:29.728638 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1168 20:18:29.800037 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1169 20:18:29.874849 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1170 20:18:29.944354 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1171 20:18:30.022117 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1172 20:18:30.092604 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1173 20:18:30.160520 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1174 20:18:30.234765 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1175 20:18:30.306480 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1176 20:18:30.382372 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1177 20:18:30.451437 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1178 20:18:30.526760 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1179 20:18:30.599237 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1180 20:18:30.671412 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1181 20:18:30.693107 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1182 20:18:30.765128 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1183 20:18:30.842186 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1184 20:18:30.930521 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1185 20:18:30.949540 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1186 20:18:31.027277 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1187 20:18:31.048694 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1188 20:18:31.119513 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1189 20:18:31.145274 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1190 20:18:31.169194 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1191 20:18:31.194044 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1192 20:18:31.214168 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1193 20:18:31.237298 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1194 20:18:31.266603 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1195 20:18:31.290880 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1196 20:18:31.369979 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1197 20:18:31.386248 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1198 20:18:31.412545 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1199 20:18:31.480704 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1200 20:18:31.556640 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1201 20:18:31.572726 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1202 20:18:31.671780 # not ok 144 /ocp/interconnect@47c00000
1203 20:18:31.743443 # not ok 145 /ocp/interconnect@47c00000/segment@0
1204 20:18:31.765792 # ok 146 /ocp/interconnect@48000000
1205 20:18:31.791342 # ok 147 /ocp/interconnect@48000000/segment@0
1206 20:18:31.812471 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1207 20:18:31.838429 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1208 20:18:31.863148 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1209 20:18:31.886000 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1210 20:18:31.908308 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1211 20:18:31.932262 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1212 20:18:31.951799 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1213 20:18:32.023670 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1214 20:18:32.094420 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1215 20:18:32.118282 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1216 20:18:32.141399 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1217 20:18:32.163752 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1218 20:18:32.187683 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1219 20:18:32.210037 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1220 20:18:32.233916 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1221 20:18:32.258313 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1222 20:18:32.280759 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1223 20:18:32.303064 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1224 20:18:32.326832 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1225 20:18:32.348805 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1226 20:18:32.377114 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1227 20:18:32.398270 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1228 20:18:32.418631 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1229 20:18:32.442026 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1230 20:18:32.466044 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1231 20:18:32.491970 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1232 20:18:32.517355 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1233 20:18:32.536868 # ok 175 /ocp/interconnect@48000000/segment@100000
1234 20:18:32.564856 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1235 20:18:32.582753 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1236 20:18:32.656341 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1237 20:18:32.728056 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1238 20:18:32.798731 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1239 20:18:32.871977 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1240 20:18:32.942675 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1241 20:18:33.014648 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1242 20:18:33.084398 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1243 20:18:33.157638 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1244 20:18:33.176254 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1245 20:18:33.204287 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1246 20:18:33.228427 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1247 20:18:33.247114 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1248 20:18:33.270465 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1249 20:18:33.298397 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1250 20:18:33.318449 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1251 20:18:33.346430 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1252 20:18:33.368478 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1253 20:18:33.388116 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1254 20:18:33.414984 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1255 20:18:33.440982 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1256 20:18:33.460639 # ok 198 /ocp/interconnect@48000000/segment@200000
1257 20:18:33.482162 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1258 20:18:33.554763 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1259 20:18:33.576939 # ok 201 /ocp/interconnect@48000000/segment@300000
1260 20:18:33.599919 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1261 20:18:33.624108 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1262 20:18:33.648005 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1263 20:18:33.671350 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1264 20:18:33.698545 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1265 20:18:33.721682 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1266 20:18:33.788983 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1267 20:18:33.808451 # ok 209 /ocp/interconnect@4a000000
1268 20:18:33.831942 # ok 210 /ocp/interconnect@4a000000/segment@0
1269 20:18:33.858192 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1270 20:18:33.881118 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1271 20:18:33.905647 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1272 20:18:33.927119 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1273 20:18:33.998727 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1274 20:18:34.104101 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1275 20:18:34.180325 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1276 20:18:34.280612 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1277 20:18:34.350199 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1278 20:18:34.424266 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1279 20:18:34.519191 # not ok 221 /ocp/interconnect@4b140000
1280 20:18:34.591370 # not ok 222 /ocp/interconnect@4b140000/segment@0
1281 20:18:34.666656 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1282 20:18:34.686991 # ok 224 /ocp/target-module@40300000
1283 20:18:34.705334 # ok 225 /ocp/target-module@40300000/sram@0
1284 20:18:34.778938 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1285 20:18:34.850180 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1286 20:18:34.869630 # ok 228 /ocp/target-module@47400000
1287 20:18:34.897268 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1288 20:18:34.915831 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1289 20:18:34.938814 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1290 20:18:34.960195 # ok 232 /ocp/target-module@47400000/usb@1400
1291 20:18:34.986283 # ok 233 /ocp/target-module@47400000/usb@1800
1292 20:18:35.003141 # ok 234 /ocp/target-module@47810000
1293 20:18:35.025917 # ok 235 /ocp/target-module@49000000
1294 20:18:35.053087 # ok 236 /ocp/target-module@49000000/dma@0
1295 20:18:35.075648 # ok 237 /ocp/target-module@49800000
1296 20:18:35.093639 # ok 238 /ocp/target-module@49800000/dma@0
1297 20:18:35.120096 # ok 239 /ocp/target-module@49900000
1298 20:18:35.142948 # ok 240 /ocp/target-module@49900000/dma@0
1299 20:18:35.160340 # ok 241 /ocp/target-module@49a00000
1300 20:18:35.186130 # ok 242 /ocp/target-module@49a00000/dma@0
1301 20:18:35.212917 # ok 243 /ocp/target-module@4c000000
1302 20:18:35.276196 # not ok 244 /ocp/target-module@4c000000/emif@0
1303 20:18:35.298739 # ok 245 /ocp/target-module@50000000
1304 20:18:35.324839 # ok 246 /ocp/target-module@53100000
1305 20:18:35.396516 # not ok 247 /ocp/target-module@53100000/sham@0
1306 20:18:35.413357 # ok 248 /ocp/target-module@53500000
1307 20:18:35.486514 # not ok 249 /ocp/target-module@53500000/aes@0
1308 20:18:35.506066 # ok 250 /ocp/target-module@56000000
1309 20:18:35.610724 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1310 20:18:35.683297 # ok 252 /opp-table # SKIP
1311 20:18:35.752757 # ok 253 /soc # SKIP
1312 20:18:35.768784 # ok 254 /sound
1313 20:18:35.792618 # ok 255 /target-module@4b000000
1314 20:18:35.821776 # ok 256 /target-module@4b000000/target-module@140000
1315 20:18:35.838463 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1316 20:18:35.846205 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1317 20:18:35.854063 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1318 20:18:37.954998 dt_test_unprobed_devices_sh_ skip
1319 20:18:37.960432 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1320 20:18:37.966059 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1321 20:18:37.966639 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1322 20:18:37.971603 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1323 20:18:37.977234 dt_test_unprobed_devices_sh_fixedregulator0 pass
1324 20:18:37.982829 dt_test_unprobed_devices_sh_leds pass
1325 20:18:37.983376 dt_test_unprobed_devices_sh_ocp pass
1326 20:18:37.988459 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1327 20:18:37.994062 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1328 20:18:37.999620 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1329 20:18:38.010777 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1330 20:18:38.016465 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1331 20:18:38.022054 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1332 20:18:38.033194 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1333 20:18:38.038847 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1334 20:18:38.050128 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1335 20:18:38.061350 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1336 20:18:38.072529 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1337 20:18:38.078153 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1338 20:18:38.089381 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1339 20:18:38.100621 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1340 20:18:38.112159 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1341 20:18:38.123077 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1342 20:18:38.128669 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1343 20:18:38.139912 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1344 20:18:38.151015 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1345 20:18:38.162179 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1346 20:18:38.173385 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1347 20:18:38.178965 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1348 20:18:38.190167 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1349 20:18:38.201345 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1350 20:18:38.212594 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1351 20:18:38.218214 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1352 20:18:38.229466 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1353 20:18:38.240551 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1354 20:18:38.251719 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1355 20:18:38.262907 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1356 20:18:38.268559 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1357 20:18:38.279865 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1358 20:18:38.291025 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1359 20:18:38.302171 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1360 20:18:38.313399 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1361 20:18:38.324620 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1362 20:18:38.335767 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1363 20:18:38.346916 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1364 20:18:38.358201 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1365 20:18:38.369392 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1366 20:18:38.380533 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1367 20:18:38.391716 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1368 20:18:38.402997 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1369 20:18:38.414158 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1370 20:18:38.425322 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1371 20:18:38.436515 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1372 20:18:38.447748 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1373 20:18:38.458983 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1374 20:18:38.470088 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1375 20:18:38.481252 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1376 20:18:38.492487 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1377 20:18:38.503646 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1378 20:18:38.514951 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1379 20:18:38.526029 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1380 20:18:38.537230 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1381 20:18:38.548413 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1382 20:18:38.554084 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1383 20:18:38.565249 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1384 20:18:38.576392 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1385 20:18:38.587629 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1386 20:18:38.598791 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1387 20:18:38.610055 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1388 20:18:38.621184 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1389 20:18:38.632470 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1390 20:18:38.643564 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1391 20:18:38.654868 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1392 20:18:38.666061 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1393 20:18:38.677176 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1394 20:18:38.688387 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1395 20:18:38.699567 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1396 20:18:38.710757 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1397 20:18:38.722085 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1398 20:18:38.733131 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1399 20:18:38.744339 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1400 20:18:38.750077 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1401 20:18:38.761082 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1402 20:18:38.772307 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1403 20:18:38.783477 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1404 20:18:38.794670 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1405 20:18:38.800369 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1406 20:18:38.817100 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1407 20:18:38.828257 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1408 20:18:38.833909 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1409 20:18:38.850656 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1410 20:18:38.861868 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1411 20:18:38.873082 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1412 20:18:38.878665 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1413 20:18:38.889903 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1414 20:18:38.901060 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1415 20:18:38.906658 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1416 20:18:38.917843 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1417 20:18:38.929087 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1418 20:18:38.934648 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1419 20:18:38.945792 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1420 20:18:38.951490 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1421 20:18:38.962577 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1422 20:18:38.973891 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1423 20:18:38.985074 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1424 20:18:38.996158 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1425 20:18:39.007365 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1426 20:18:39.018512 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1427 20:18:39.029705 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1428 20:18:39.041087 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1429 20:18:39.052088 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1430 20:18:39.063303 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1431 20:18:39.075154 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1432 20:18:39.085761 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1433 20:18:39.102487 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1434 20:18:39.113689 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1435 20:18:39.124974 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1436 20:18:39.136116 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1437 20:18:39.147275 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1438 20:18:39.164176 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1439 20:18:39.175276 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1440 20:18:39.186620 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1441 20:18:39.197666 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1442 20:18:39.203515 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1443 20:18:39.214393 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1444 20:18:39.225596 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1445 20:18:39.231160 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1446 20:18:39.242346 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1447 20:18:39.248025 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1448 20:18:39.259146 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1449 20:18:39.264796 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1450 20:18:39.275995 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1451 20:18:39.281598 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1452 20:18:39.292712 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1453 20:18:39.298397 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1454 20:18:39.309499 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1455 20:18:39.320726 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1456 20:18:39.331882 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1457 20:18:39.343081 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1458 20:18:39.354282 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1459 20:18:39.359969 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1460 20:18:39.371085 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1461 20:18:39.376766 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1462 20:18:39.382351 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1463 20:18:39.387938 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1464 20:18:39.393516 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1465 20:18:39.399121 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1466 20:18:39.410303 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1467 20:18:39.415951 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1468 20:18:39.421544 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1469 20:18:39.432693 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1470 20:18:39.438367 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1471 20:18:39.449429 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1472 20:18:39.455136 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1473 20:18:39.466253 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1474 20:18:39.471899 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1475 20:18:39.483086 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1476 20:18:39.488632 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1477 20:18:39.499937 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1478 20:18:39.505566 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1479 20:18:39.516631 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1480 20:18:39.522287 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1481 20:18:39.533388 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1482 20:18:39.539037 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1483 20:18:39.544645 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1484 20:18:39.555736 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1485 20:18:39.561431 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1486 20:18:39.572570 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1487 20:18:39.578217 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1488 20:18:39.589472 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1489 20:18:39.595030 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1490 20:18:39.606209 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1491 20:18:39.611771 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1492 20:18:39.617335 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1493 20:18:39.628526 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1494 20:18:39.634194 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1495 20:18:39.645313 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1496 20:18:39.656549 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1497 20:18:39.667716 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1498 20:18:39.678863 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1499 20:18:39.690145 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1500 20:18:39.701331 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1501 20:18:39.712482 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1502 20:18:39.723859 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1503 20:18:39.729385 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1504 20:18:39.740467 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1505 20:18:39.746142 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1506 20:18:39.757270 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1507 20:18:39.762903 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1508 20:18:39.774144 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1509 20:18:39.779635 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1510 20:18:39.790795 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1511 20:18:39.796444 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1512 20:18:39.807627 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1513 20:18:39.813300 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1514 20:18:39.824642 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1515 20:18:39.830125 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1516 20:18:39.841254 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1517 20:18:39.846826 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1518 20:18:39.852526 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1519 20:18:39.863590 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1520 20:18:39.869223 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1521 20:18:39.880403 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1522 20:18:39.886021 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1523 20:18:39.897150 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1524 20:18:39.902764 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1525 20:18:39.914039 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1526 20:18:39.919573 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1527 20:18:39.925203 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1528 20:18:39.930751 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1529 20:18:39.941935 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1530 20:18:39.953171 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1531 20:18:39.958734 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1532 20:18:39.964370 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1533 20:18:39.975535 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1534 20:18:39.986702 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1535 20:18:39.997944 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1536 20:18:40.009293 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1537 20:18:40.014790 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1538 20:18:40.020348 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1539 20:18:40.026006 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1540 20:18:40.031615 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1541 20:18:40.037208 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1542 20:18:40.042743 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1543 20:18:40.053959 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1544 20:18:40.059579 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1545 20:18:40.065184 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1546 20:18:40.070815 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1547 20:18:40.076404 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1548 20:18:40.087611 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1549 20:18:40.093215 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1550 20:18:40.098793 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1551 20:18:40.104391 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1552 20:18:40.110050 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1553 20:18:40.115585 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1554 20:18:40.121213 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1555 20:18:40.126776 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1556 20:18:40.132409 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1557 20:18:40.137978 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1558 20:18:40.143573 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1559 20:18:40.149196 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1560 20:18:40.154746 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1561 20:18:40.160377 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1562 20:18:40.166011 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1563 20:18:40.171556 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1564 20:18:40.177173 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1565 20:18:40.182738 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1566 20:18:40.188340 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1567 20:18:40.194126 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1568 20:18:40.199653 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1569 20:18:40.200000 dt_test_unprobed_devices_sh_opp-table skip
1570 20:18:40.205275 dt_test_unprobed_devices_sh_soc skip
1571 20:18:40.210810 dt_test_unprobed_devices_sh_sound pass
1572 20:18:40.216368 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1573 20:18:40.222038 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1574 20:18:40.227584 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1575 20:18:40.233256 dt_test_unprobed_devices_sh fail
1576 20:18:40.233602 + ../../utils/send-to-lava.sh ./output/result.txt
1577 20:18:40.241196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1578 20:18:40.241869 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1580 20:18:40.255119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1581 20:18:40.255716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1583 20:18:40.357847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1584 20:18:40.358466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1586 20:18:40.452110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1587 20:18:40.452714 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1589 20:18:40.543073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1590 20:18:40.543676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1592 20:18:40.633645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1593 20:18:40.634269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1595 20:18:40.723761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1596 20:18:40.724384 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1598 20:18:40.812156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1599 20:18:40.812764 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1601 20:18:40.902749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1602 20:18:40.903335 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1604 20:18:40.994694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1605 20:18:40.995317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1607 20:18:41.085113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1608 20:18:41.085785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1610 20:18:41.178817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1611 20:18:41.179695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1613 20:18:41.272292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1614 20:18:41.273028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1616 20:18:41.366472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1617 20:18:41.367157 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1619 20:18:41.458863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1620 20:18:41.459576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1622 20:18:41.556078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1623 20:18:41.556784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1625 20:18:41.646800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1626 20:18:41.647440 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1628 20:18:41.739990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1629 20:18:41.740682 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1631 20:18:41.837415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1632 20:18:41.838149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1634 20:18:41.930061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1635 20:18:41.930752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1637 20:18:42.020616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1638 20:18:42.021234 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1640 20:18:42.112249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1641 20:18:42.113021 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1643 20:18:42.204405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1644 20:18:42.205158 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1646 20:18:42.297503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1647 20:18:42.298344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1649 20:18:42.388188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1650 20:18:42.388991 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1652 20:18:42.479186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1653 20:18:42.479957 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1655 20:18:42.567354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1656 20:18:42.568092 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1658 20:18:42.658880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1659 20:18:42.659671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1661 20:18:42.748634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1662 20:18:42.749424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1664 20:18:42.839354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1665 20:18:42.840158 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1667 20:18:42.924212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1668 20:18:42.924981 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1670 20:18:43.018823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1671 20:18:43.019596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1673 20:18:43.107604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1674 20:18:43.108426 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1676 20:18:43.199031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1677 20:18:43.199849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1679 20:18:43.287862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1680 20:18:43.288686 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1682 20:18:43.380473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1683 20:18:43.381507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1685 20:18:43.471114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1686 20:18:43.471945 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1688 20:18:43.563391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1689 20:18:43.564260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1691 20:18:43.655734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1692 20:18:43.656787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1694 20:18:43.747649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1695 20:18:43.748537 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1697 20:18:43.839006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1698 20:18:43.839903 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1700 20:18:43.929045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1701 20:18:43.929997 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1703 20:18:44.021160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1704 20:18:44.022243 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1706 20:18:44.115674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1707 20:18:44.116575 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1709 20:18:44.208035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1710 20:18:44.208958 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1712 20:18:44.298788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1713 20:18:44.299707 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1715 20:18:44.390058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1716 20:18:44.390893 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1718 20:18:44.479519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1719 20:18:44.480404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1721 20:18:44.571293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1722 20:18:44.572159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1724 20:18:44.662081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1725 20:18:44.662939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1727 20:18:44.752512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1728 20:18:44.753348 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1730 20:18:44.844126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1731 20:18:44.844964 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1733 20:18:44.935287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1734 20:18:44.936150 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1736 20:18:45.026563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1737 20:18:45.027407 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1739 20:18:45.122461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1740 20:18:45.123306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1742 20:18:45.214816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1743 20:18:45.215685 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1745 20:18:45.306669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1746 20:18:45.307552 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1748 20:18:45.396607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1749 20:18:45.397526 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1751 20:18:45.486914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1752 20:18:45.487795 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1754 20:18:45.577175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1755 20:18:45.577774 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1757 20:18:45.668555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1758 20:18:45.669153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1760 20:18:45.759208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1761 20:18:45.759812 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1763 20:18:45.843421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1764 20:18:45.844020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1766 20:18:45.937133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1767 20:18:45.937705 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1769 20:18:46.030584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1770 20:18:46.031165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1772 20:18:46.119414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1773 20:18:46.119991 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1775 20:18:46.209560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1776 20:18:46.210181 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1778 20:18:46.300303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1779 20:18:46.300880 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1781 20:18:46.389017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1782 20:18:46.389598 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1784 20:18:46.478486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1785 20:18:46.479073 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1787 20:18:46.569557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1788 20:18:46.570195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1790 20:18:46.659037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1791 20:18:46.659615 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1793 20:18:46.748445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1794 20:18:46.749038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1796 20:18:46.841873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1797 20:18:46.842465 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1799 20:18:46.931624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1800 20:18:46.932202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1802 20:18:47.022364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1803 20:18:47.022937 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1805 20:18:47.112857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1806 20:18:47.113435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1808 20:18:47.204102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1809 20:18:47.204672 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1811 20:18:47.294412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1812 20:18:47.294997 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1814 20:18:47.385364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1815 20:18:47.385946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1817 20:18:47.476037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1818 20:18:47.476631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1820 20:18:47.567634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1821 20:18:47.568209 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1823 20:18:47.659472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1824 20:18:47.660068 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1826 20:18:47.748484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1827 20:18:47.749056 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1829 20:18:47.839187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1830 20:18:47.839765 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1832 20:18:47.928535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1833 20:18:47.929112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1835 20:18:48.018965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1836 20:18:48.019561 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1838 20:18:48.110202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1839 20:18:48.111063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1841 20:18:48.202309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1842 20:18:48.203159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1844 20:18:48.296993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1845 20:18:48.297629 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1847 20:18:48.388839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1848 20:18:48.389449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1850 20:18:48.480897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1851 20:18:48.481519 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1853 20:18:48.572728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1854 20:18:48.573342 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1856 20:18:48.664750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1857 20:18:48.665355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1859 20:18:48.758180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1860 20:18:48.758781 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1862 20:18:48.846303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1863 20:18:48.846908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1865 20:18:48.937343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1866 20:18:48.938060 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1868 20:18:49.028366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1869 20:18:49.029317 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1871 20:18:49.121171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1872 20:18:49.122275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1874 20:18:49.213750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1875 20:18:49.214693 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1877 20:18:49.306271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1878 20:18:49.307116 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1880 20:18:49.395570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1881 20:18:49.396421 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1883 20:18:49.486662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1884 20:18:49.487500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1886 20:18:49.577385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1887 20:18:49.578076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1889 20:18:49.671441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1890 20:18:49.672065 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1892 20:18:49.766193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1893 20:18:49.766870 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1895 20:18:49.855813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1896 20:18:49.856476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1898 20:18:49.951115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1899 20:18:49.951744 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1901 20:18:50.044958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1902 20:18:50.045838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1904 20:18:50.136682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1905 20:18:50.137517 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1907 20:18:50.227068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1908 20:18:50.227912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1910 20:18:50.316396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1911 20:18:50.317235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1913 20:18:50.407069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1914 20:18:50.407919 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1916 20:18:50.498564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1917 20:18:50.499462 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1919 20:18:50.590130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1920 20:18:50.591012 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1922 20:18:50.681173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1923 20:18:50.682030 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1925 20:18:50.775308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1926 20:18:50.776142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1928 20:18:50.867050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1929 20:18:50.867896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1931 20:18:50.959479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1932 20:18:50.960284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1934 20:18:51.049612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1935 20:18:51.050438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1937 20:18:51.140556 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1939 20:18:51.142897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1940 20:18:51.232576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1942 20:18:51.235738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1943 20:18:51.325377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1945 20:18:51.327725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1946 20:18:51.418736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1947 20:18:51.419586 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1949 20:18:51.508395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1950 20:18:51.509202 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1952 20:18:51.598729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1953 20:18:51.599538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1955 20:18:51.690705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1956 20:18:51.691501 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1958 20:18:51.781334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1959 20:18:51.782144 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1961 20:18:51.874092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1962 20:18:51.874884 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1964 20:18:51.965843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1965 20:18:51.966708 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1967 20:18:52.055951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1968 20:18:52.056849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1970 20:18:52.147686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1971 20:18:52.148553 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1973 20:18:52.239350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1974 20:18:52.240207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1976 20:18:52.332211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1977 20:18:52.333026 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1979 20:18:52.426891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1980 20:18:52.427770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1982 20:18:52.515054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1983 20:18:52.516046 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1985 20:18:52.607725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1986 20:18:52.608581 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1988 20:18:52.699571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1989 20:18:52.700391 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1991 20:18:52.785224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
1992 20:18:52.786104 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
1994 20:18:52.874084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
1995 20:18:52.874896 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
1997 20:18:52.963996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
1998 20:18:52.964850 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2000 20:18:53.055076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2001 20:18:53.056507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2003 20:18:53.145312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2004 20:18:53.146266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2006 20:18:53.231885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2007 20:18:53.232675 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2009 20:18:53.318195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2010 20:18:53.319002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2012 20:18:53.410779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2013 20:18:53.411579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2015 20:18:53.499689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2016 20:18:53.500477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2018 20:18:53.590745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2019 20:18:53.591559 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2021 20:18:53.682598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2022 20:18:53.683460 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2024 20:18:53.772797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2025 20:18:53.773639 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2027 20:18:53.861578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2028 20:18:53.862571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2030 20:18:53.951786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2031 20:18:53.952629 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2033 20:18:54.046117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2034 20:18:54.047037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2036 20:18:54.137534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2037 20:18:54.138432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2039 20:18:54.227275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2040 20:18:54.227946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2042 20:18:54.316165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2043 20:18:54.316827 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2045 20:18:54.408444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2046 20:18:54.409130 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2048 20:18:54.498580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2049 20:18:54.499251 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2051 20:18:54.591591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2052 20:18:54.592266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2054 20:18:54.682203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2055 20:18:54.682877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2057 20:18:54.773451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2058 20:18:54.774140 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2060 20:18:54.865534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2061 20:18:54.866206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2063 20:18:54.958301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2064 20:18:54.958958 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2066 20:18:55.048385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2067 20:18:55.049048 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2069 20:18:55.141039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2070 20:18:55.141698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2072 20:18:55.232393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2073 20:18:55.233260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2075 20:18:55.323128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2076 20:18:55.323974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2078 20:18:55.414500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2079 20:18:55.415336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2081 20:18:55.506729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2082 20:18:55.507684 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2084 20:18:55.596115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2085 20:18:55.597012 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2087 20:18:55.687104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2088 20:18:55.689960 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2090 20:18:55.776707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2091 20:18:55.777627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2093 20:18:55.866908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2094 20:18:55.867768 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2096 20:18:55.957094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2097 20:18:55.957949 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2099 20:18:56.048557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2100 20:18:56.049414 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2102 20:18:56.139105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2103 20:18:56.139943 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2105 20:18:56.230853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2106 20:18:56.231712 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2108 20:18:56.323836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2109 20:18:56.324688 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2111 20:18:56.415278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2112 20:18:56.416118 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2114 20:18:56.505253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2115 20:18:56.506118 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2117 20:18:56.808904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2118 20:18:56.809740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2120 20:18:56.913916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2121 20:18:56.914731 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2123 20:18:57.005159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2124 20:18:57.006020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2126 20:18:57.102399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2127 20:18:57.103324 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2129 20:18:57.195277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2130 20:18:57.196415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2132 20:18:57.293355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2133 20:18:57.294040 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2135 20:18:57.385399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2136 20:18:57.386019 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2138 20:18:57.475971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2139 20:18:57.476609 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2141 20:18:57.566622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2142 20:18:57.567266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2144 20:18:57.657182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2145 20:18:57.657846 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2147 20:18:57.748356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2148 20:18:57.748990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2150 20:18:57.837122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2151 20:18:57.837774 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2153 20:18:57.922316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2154 20:18:57.922940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2156 20:18:58.016156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2157 20:18:58.016780 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2159 20:18:58.106684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2160 20:18:58.107792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2162 20:18:58.197873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2163 20:18:58.198716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2165 20:18:58.289393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2166 20:18:58.290343 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2168 20:18:58.381548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2169 20:18:58.382656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2171 20:18:58.471365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2172 20:18:58.472367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2174 20:18:58.563938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2175 20:18:58.564802 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2177 20:18:58.653270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2178 20:18:58.654107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2180 20:18:58.741153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2181 20:18:58.741948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2183 20:18:58.831719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2184 20:18:58.832528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2186 20:18:58.923014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2187 20:18:58.923821 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2189 20:18:59.014401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2190 20:18:59.015201 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2192 20:18:59.102957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2193 20:18:59.103751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2195 20:18:59.193977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2196 20:18:59.194787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2198 20:18:59.284003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2199 20:18:59.284771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2201 20:18:59.376762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2202 20:18:59.377571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2204 20:18:59.462090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2205 20:18:59.462870 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2207 20:18:59.548685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2208 20:18:59.549480 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2210 20:18:59.640795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2211 20:18:59.641660 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2213 20:18:59.735054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2214 20:18:59.735839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2216 20:18:59.827611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2217 20:18:59.828382 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2219 20:18:59.916673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2220 20:18:59.917457 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2222 20:19:00.007018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2223 20:19:00.007797 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2225 20:19:00.097798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2226 20:19:00.098627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2228 20:19:00.190000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2229 20:19:00.190767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2231 20:19:00.281541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2232 20:19:00.282390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2234 20:19:00.372105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2235 20:19:00.372888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2237 20:19:00.463430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2238 20:19:00.464025 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2240 20:19:00.552704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2241 20:19:00.553322 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2243 20:19:00.642362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2244 20:19:00.643239 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2246 20:19:00.731424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2247 20:19:00.732366 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2249 20:19:00.821919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2250 20:19:00.822842 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2252 20:19:00.912732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2253 20:19:00.913631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2255 20:19:01.005193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2256 20:19:01.006056 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2258 20:19:01.092924 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2260 20:19:01.095831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2261 20:19:01.184165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2262 20:19:01.185062 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2264 20:19:01.273653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2265 20:19:01.274675 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2267 20:19:01.365151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2268 20:19:01.366165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2270 20:19:01.458843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2271 20:19:01.459764 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2273 20:19:01.550299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2274 20:19:01.551217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2276 20:19:01.642917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2277 20:19:01.643578 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2279 20:19:01.731637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2280 20:19:01.732286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2282 20:19:01.822329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2283 20:19:01.822987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2285 20:19:01.912069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2286 20:19:01.912720 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2288 20:19:02.003508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2289 20:19:02.004142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2291 20:19:02.093561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2292 20:19:02.094225 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2294 20:19:02.183930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2295 20:19:02.184574 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2297 20:19:02.276644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2298 20:19:02.277279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2300 20:19:02.367603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2301 20:19:02.368287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2303 20:19:02.471959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2304 20:19:02.472629 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2306 20:19:02.565052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2307 20:19:02.565699 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2309 20:19:02.659486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2310 20:19:02.660126 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2312 20:19:02.758487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2313 20:19:02.759193 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2315 20:19:02.852515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2316 20:19:02.853176 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2318 20:19:02.968288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2319 20:19:02.968950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2321 20:19:03.064272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2322 20:19:03.064885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2324 20:19:03.152847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2325 20:19:03.154003 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2327 20:19:03.242628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2328 20:19:03.243472 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2330 20:19:03.332843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2331 20:19:03.333687 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2333 20:19:03.422289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2334 20:19:03.423148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2336 20:19:03.513254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2337 20:19:03.514135 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2339 20:19:03.604557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2340 20:19:03.605468 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2342 20:19:03.700107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2343 20:19:03.700944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2345 20:19:03.793360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2346 20:19:03.794250 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2348 20:19:03.886307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2349 20:19:03.887207 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2351 20:19:03.973051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2352 20:19:03.973629 + set +x
2353 20:19:03.974379 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2355 20:19:03.977302 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 936513_1.6.2.4.5>
2356 20:19:03.978026 Received signal: <ENDRUN> 1_kselftest-dt 936513_1.6.2.4.5
2357 20:19:03.978508 Ending use of test pattern.
2358 20:19:03.978921 Ending test lava.1_kselftest-dt (936513_1.6.2.4.5), duration 86.04
2360 20:19:03.984528 <LAVA_TEST_RUNNER EXIT>
2361 20:19:03.985249 ok: lava_test_shell seems to have completed
2362 20:19:03.998092 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2363 20:19:04.000017 end: 3.1 lava-test-shell (duration 00:01:27) [common]
2364 20:19:04.000619 end: 3 lava-test-retry (duration 00:01:27) [common]
2365 20:19:04.001181 start: 4 finalize (timeout 00:05:25) [common]
2366 20:19:04.001749 start: 4.1 power-off (timeout 00:00:30) [common]
2367 20:19:04.002855 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-05'
2368 20:19:04.036017 >> OK - accepted request
2369 20:19:04.038054 Returned 0 in 0 seconds
2370 20:19:04.139298 end: 4.1 power-off (duration 00:00:00) [common]
2372 20:19:04.141057 start: 4.2 read-feedback (timeout 00:05:25) [common]
2373 20:19:04.142276 Listened to connection for namespace 'common' for up to 1s
2374 20:19:04.143184 Listened to connection for namespace 'common' for up to 1s
2375 20:19:05.142961 Finalising connection for namespace 'common'
2376 20:19:05.143686 Disconnecting from shell: Finalise
2377 20:19:05.144207 / #
2378 20:19:05.245174 end: 4.2 read-feedback (duration 00:00:01) [common]
2379 20:19:05.245974 end: 4 finalize (duration 00:00:01) [common]
2380 20:19:05.246614 Cleaning after the job
2381 20:19:05.247199 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936513/tftp-deploy-zj58j50d/ramdisk
2382 20:19:05.256411 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936513/tftp-deploy-zj58j50d/kernel
2383 20:19:05.263650 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936513/tftp-deploy-zj58j50d/dtb
2384 20:19:05.264996 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936513/tftp-deploy-zj58j50d/nfsrootfs
2385 20:19:05.306258 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936513/tftp-deploy-zj58j50d/modules
2386 20:19:05.311005 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/936513
2387 20:19:08.269601 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/936513
2388 20:19:08.270190 Job finished correctly