Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 20:16:36.726975 lava-dispatcher, installed at version: 2024.01
2 20:16:36.727793 start: 0 validate
3 20:16:36.728287 Start time: 2024-11-04 20:16:36.728255+00:00 (UTC)
4 20:16:36.728862 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 20:16:36.729398 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 20:16:36.764518 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 20:16:36.765103 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-95-g6db936d4ac0f%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 20:16:36.795611 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 20:16:36.796335 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-95-g6db936d4ac0f%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 20:16:36.826032 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 20:16:36.826750 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-95-g6db936d4ac0f%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 20:16:36.865096 validate duration: 0.14
14 20:16:36.865972 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 20:16:36.866313 start: 1.1 download-retry (timeout 00:10:00) [common]
16 20:16:36.866625 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 20:16:36.867227 Not decompressing ramdisk as can be used compressed.
18 20:16:36.867670 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 20:16:36.867953 saving as /var/lib/lava/dispatcher/tmp/936637/tftp-deploy-k2uiga9a/ramdisk/rootfs.cpio.gz
20 20:16:36.868264 total size: 8181887 (7 MB)
21 20:16:36.907233 progress 0 % (0 MB)
22 20:16:36.913505 progress 5 % (0 MB)
23 20:16:36.918962 progress 10 % (0 MB)
24 20:16:36.925138 progress 15 % (1 MB)
25 20:16:36.930325 progress 20 % (1 MB)
26 20:16:36.936126 progress 25 % (1 MB)
27 20:16:36.941608 progress 30 % (2 MB)
28 20:16:36.947240 progress 35 % (2 MB)
29 20:16:36.952675 progress 40 % (3 MB)
30 20:16:36.958347 progress 45 % (3 MB)
31 20:16:36.963561 progress 50 % (3 MB)
32 20:16:36.969389 progress 55 % (4 MB)
33 20:16:36.974655 progress 60 % (4 MB)
34 20:16:36.980291 progress 65 % (5 MB)
35 20:16:36.985512 progress 70 % (5 MB)
36 20:16:36.991112 progress 75 % (5 MB)
37 20:16:36.996296 progress 80 % (6 MB)
38 20:16:37.001873 progress 85 % (6 MB)
39 20:16:37.006916 progress 90 % (7 MB)
40 20:16:37.012055 progress 95 % (7 MB)
41 20:16:37.016799 progress 100 % (7 MB)
42 20:16:37.017442 7 MB downloaded in 0.15 s (52.31 MB/s)
43 20:16:37.017990 end: 1.1.1 http-download (duration 00:00:00) [common]
45 20:16:37.018867 end: 1.1 download-retry (duration 00:00:00) [common]
46 20:16:37.019156 start: 1.2 download-retry (timeout 00:10:00) [common]
47 20:16:37.019429 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 20:16:37.019902 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-95-g6db936d4ac0f/arm64/defconfig/gcc-12/kernel/Image
49 20:16:37.020180 saving as /var/lib/lava/dispatcher/tmp/936637/tftp-deploy-k2uiga9a/kernel/Image
50 20:16:37.020391 total size: 45713920 (43 MB)
51 20:16:37.020603 No compression specified
52 20:16:37.054916 progress 0 % (0 MB)
53 20:16:37.086419 progress 5 % (2 MB)
54 20:16:37.118963 progress 10 % (4 MB)
55 20:16:37.151352 progress 15 % (6 MB)
56 20:16:37.181089 progress 20 % (8 MB)
57 20:16:37.209881 progress 25 % (10 MB)
58 20:16:37.240026 progress 30 % (13 MB)
59 20:16:37.269792 progress 35 % (15 MB)
60 20:16:37.301584 progress 40 % (17 MB)
61 20:16:37.331928 progress 45 % (19 MB)
62 20:16:37.360769 progress 50 % (21 MB)
63 20:16:37.390293 progress 55 % (24 MB)
64 20:16:37.419970 progress 60 % (26 MB)
65 20:16:37.449443 progress 65 % (28 MB)
66 20:16:37.479694 progress 70 % (30 MB)
67 20:16:37.510047 progress 75 % (32 MB)
68 20:16:37.539918 progress 80 % (34 MB)
69 20:16:37.569692 progress 85 % (37 MB)
70 20:16:37.599435 progress 90 % (39 MB)
71 20:16:37.629696 progress 95 % (41 MB)
72 20:16:37.658287 progress 100 % (43 MB)
73 20:16:37.658840 43 MB downloaded in 0.64 s (68.29 MB/s)
74 20:16:37.659329 end: 1.2.1 http-download (duration 00:00:01) [common]
76 20:16:37.660197 end: 1.2 download-retry (duration 00:00:01) [common]
77 20:16:37.660484 start: 1.3 download-retry (timeout 00:09:59) [common]
78 20:16:37.660755 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 20:16:37.661226 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-95-g6db936d4ac0f/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 20:16:37.661516 saving as /var/lib/lava/dispatcher/tmp/936637/tftp-deploy-k2uiga9a/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 20:16:37.661766 total size: 53209 (0 MB)
82 20:16:37.661985 No compression specified
83 20:16:37.698415 progress 61 % (0 MB)
84 20:16:37.699287 progress 100 % (0 MB)
85 20:16:37.699839 0 MB downloaded in 0.04 s (1.33 MB/s)
86 20:16:37.700369 end: 1.3.1 http-download (duration 00:00:00) [common]
88 20:16:37.701263 end: 1.3 download-retry (duration 00:00:00) [common]
89 20:16:37.701629 start: 1.4 download-retry (timeout 00:09:59) [common]
90 20:16:37.701984 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 20:16:37.702619 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-95-g6db936d4ac0f/arm64/defconfig/gcc-12/modules.tar.xz
92 20:16:37.702911 saving as /var/lib/lava/dispatcher/tmp/936637/tftp-deploy-k2uiga9a/modules/modules.tar
93 20:16:37.703126 total size: 11612416 (11 MB)
94 20:16:37.703342 Using unxz to decompress xz
95 20:16:37.736165 progress 0 % (0 MB)
96 20:16:37.804719 progress 5 % (0 MB)
97 20:16:37.882493 progress 10 % (1 MB)
98 20:16:37.984157 progress 15 % (1 MB)
99 20:16:38.077277 progress 20 % (2 MB)
100 20:16:38.157354 progress 25 % (2 MB)
101 20:16:38.233735 progress 30 % (3 MB)
102 20:16:38.313222 progress 35 % (3 MB)
103 20:16:38.386913 progress 40 % (4 MB)
104 20:16:38.463805 progress 45 % (5 MB)
105 20:16:38.548840 progress 50 % (5 MB)
106 20:16:38.627134 progress 55 % (6 MB)
107 20:16:38.712993 progress 60 % (6 MB)
108 20:16:38.794450 progress 65 % (7 MB)
109 20:16:38.877997 progress 70 % (7 MB)
110 20:16:38.956894 progress 75 % (8 MB)
111 20:16:39.041417 progress 80 % (8 MB)
112 20:16:39.122621 progress 85 % (9 MB)
113 20:16:39.202305 progress 90 % (9 MB)
114 20:16:39.281194 progress 95 % (10 MB)
115 20:16:39.358535 progress 100 % (11 MB)
116 20:16:39.371278 11 MB downloaded in 1.67 s (6.64 MB/s)
117 20:16:39.371876 end: 1.4.1 http-download (duration 00:00:02) [common]
119 20:16:39.373438 end: 1.4 download-retry (duration 00:00:02) [common]
120 20:16:39.373965 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 20:16:39.374489 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 20:16:39.374981 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 20:16:39.375480 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 20:16:39.376482 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos
125 20:16:39.377382 makedir: /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin
126 20:16:39.378042 makedir: /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/tests
127 20:16:39.378655 makedir: /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/results
128 20:16:39.379268 Creating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin/lava-add-keys
129 20:16:39.380259 Creating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin/lava-add-sources
130 20:16:39.381230 Creating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin/lava-background-process-start
131 20:16:39.382172 Creating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin/lava-background-process-stop
132 20:16:39.383133 Creating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin/lava-common-functions
133 20:16:39.384079 Creating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin/lava-echo-ipv4
134 20:16:39.384989 Creating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin/lava-install-packages
135 20:16:39.385867 Creating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin/lava-installed-packages
136 20:16:39.386745 Creating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin/lava-os-build
137 20:16:39.387652 Creating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin/lava-probe-channel
138 20:16:39.388597 Creating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin/lava-probe-ip
139 20:16:39.389482 Creating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin/lava-target-ip
140 20:16:39.390357 Creating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin/lava-target-mac
141 20:16:39.391229 Creating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin/lava-target-storage
142 20:16:39.392143 Creating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin/lava-test-case
143 20:16:39.393045 Creating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin/lava-test-event
144 20:16:39.393919 Creating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin/lava-test-feedback
145 20:16:39.394795 Creating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin/lava-test-raise
146 20:16:39.395697 Creating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin/lava-test-reference
147 20:16:39.396641 Creating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin/lava-test-runner
148 20:16:39.397668 Creating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin/lava-test-set
149 20:16:39.398588 Creating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin/lava-test-shell
150 20:16:39.399493 Updating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin/lava-install-packages (oe)
151 20:16:39.400471 Updating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/bin/lava-installed-packages (oe)
152 20:16:39.401299 Creating /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/environment
153 20:16:39.402011 LAVA metadata
154 20:16:39.402492 - LAVA_JOB_ID=936637
155 20:16:39.402919 - LAVA_DISPATCHER_IP=192.168.6.2
156 20:16:39.403578 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 20:16:39.405394 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 20:16:39.405980 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 20:16:39.406391 skipped lava-vland-overlay
160 20:16:39.406876 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 20:16:39.407388 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 20:16:39.407813 skipped lava-multinode-overlay
163 20:16:39.408370 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 20:16:39.408878 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 20:16:39.409358 Loading test definitions
166 20:16:39.409905 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 20:16:39.410343 Using /lava-936637 at stage 0
168 20:16:39.412342 uuid=936637_1.5.2.4.1 testdef=None
169 20:16:39.412667 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 20:16:39.412936 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 20:16:39.414752 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 20:16:39.415557 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 20:16:39.417848 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 20:16:39.418676 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 20:16:39.420939 runner path: /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/0/tests/0_dmesg test_uuid 936637_1.5.2.4.1
178 20:16:39.421521 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 20:16:39.422296 Creating lava-test-runner.conf files
181 20:16:39.422503 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/936637/lava-overlay-mem7ymos/lava-936637/0 for stage 0
182 20:16:39.422841 - 0_dmesg
183 20:16:39.423189 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 20:16:39.423468 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 20:16:39.447465 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 20:16:39.447900 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 20:16:39.448197 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 20:16:39.448474 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 20:16:39.448743 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 20:16:40.378578 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 20:16:40.379313 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 20:16:40.380055 extracting modules file /var/lib/lava/dispatcher/tmp/936637/tftp-deploy-k2uiga9a/modules/modules.tar to /var/lib/lava/dispatcher/tmp/936637/extract-overlay-ramdisk-hffhmz0_/ramdisk
193 20:16:41.766430 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 20:16:41.766914 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 20:16:41.767191 [common] Applying overlay /var/lib/lava/dispatcher/tmp/936637/compress-overlay-j0hxcm8d/overlay-1.5.2.5.tar.gz to ramdisk
196 20:16:41.767405 [common] Applying overlay /var/lib/lava/dispatcher/tmp/936637/compress-overlay-j0hxcm8d/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/936637/extract-overlay-ramdisk-hffhmz0_/ramdisk
197 20:16:41.798251 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 20:16:41.798705 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 20:16:41.798974 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 20:16:41.799202 Converting downloaded kernel to a uImage
201 20:16:41.799511 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/936637/tftp-deploy-k2uiga9a/kernel/Image /var/lib/lava/dispatcher/tmp/936637/tftp-deploy-k2uiga9a/kernel/uImage
202 20:16:42.261024 output: Image Name:
203 20:16:42.261456 output: Created: Mon Nov 4 20:16:41 2024
204 20:16:42.261666 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 20:16:42.261872 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 20:16:42.262073 output: Load Address: 01080000
207 20:16:42.262273 output: Entry Point: 01080000
208 20:16:42.262471 output:
209 20:16:42.262803 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 20:16:42.263070 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 20:16:42.263342 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 20:16:42.263595 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 20:16:42.263851 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 20:16:42.264187 Building ramdisk /var/lib/lava/dispatcher/tmp/936637/extract-overlay-ramdisk-hffhmz0_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/936637/extract-overlay-ramdisk-hffhmz0_/ramdisk
215 20:16:44.895832 >> 181606 blocks
216 20:16:54.449282 Adding RAMdisk u-boot header.
217 20:16:54.449974 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/936637/extract-overlay-ramdisk-hffhmz0_/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/936637/extract-overlay-ramdisk-hffhmz0_/ramdisk.cpio.gz.uboot
218 20:16:54.717076 output: Image Name:
219 20:16:54.717502 output: Created: Mon Nov 4 20:16:54 2024
220 20:16:54.717713 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 20:16:54.717918 output: Data Size: 26061785 Bytes = 25450.96 KiB = 24.85 MiB
222 20:16:54.718118 output: Load Address: 00000000
223 20:16:54.718317 output: Entry Point: 00000000
224 20:16:54.718513 output:
225 20:16:54.719101 rename /var/lib/lava/dispatcher/tmp/936637/extract-overlay-ramdisk-hffhmz0_/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/936637/tftp-deploy-k2uiga9a/ramdisk/ramdisk.cpio.gz.uboot
226 20:16:54.719518 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 20:16:54.719802 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
228 20:16:54.720192 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
229 20:16:54.720661 No LXC device requested
230 20:16:54.721156 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 20:16:54.721654 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
232 20:16:54.722140 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 20:16:54.722557 Checking files for TFTP limit of 4294967296 bytes.
234 20:16:54.725231 end: 1 tftp-deploy (duration 00:00:18) [common]
235 20:16:54.725797 start: 2 uboot-action (timeout 00:05:00) [common]
236 20:16:54.726313 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 20:16:54.726805 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 20:16:54.727305 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 20:16:54.727828 Using kernel file from prepare-kernel: 936637/tftp-deploy-k2uiga9a/kernel/uImage
240 20:16:54.728458 substitutions:
241 20:16:54.728865 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 20:16:54.729263 - {DTB_ADDR}: 0x01070000
243 20:16:54.729659 - {DTB}: 936637/tftp-deploy-k2uiga9a/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 20:16:54.730055 - {INITRD}: 936637/tftp-deploy-k2uiga9a/ramdisk/ramdisk.cpio.gz.uboot
245 20:16:54.730447 - {KERNEL_ADDR}: 0x01080000
246 20:16:54.730836 - {KERNEL}: 936637/tftp-deploy-k2uiga9a/kernel/uImage
247 20:16:54.731224 - {LAVA_MAC}: None
248 20:16:54.731650 - {PRESEED_CONFIG}: None
249 20:16:54.732062 - {PRESEED_LOCAL}: None
250 20:16:54.732452 - {RAMDISK_ADDR}: 0x08000000
251 20:16:54.732839 - {RAMDISK}: 936637/tftp-deploy-k2uiga9a/ramdisk/ramdisk.cpio.gz.uboot
252 20:16:54.733229 - {ROOT_PART}: None
253 20:16:54.733619 - {ROOT}: None
254 20:16:54.734004 - {SERVER_IP}: 192.168.6.2
255 20:16:54.734393 - {TEE_ADDR}: 0x83000000
256 20:16:54.734777 - {TEE}: None
257 20:16:54.735164 Parsed boot commands:
258 20:16:54.735541 - setenv autoload no
259 20:16:54.735926 - setenv initrd_high 0xffffffff
260 20:16:54.736338 - setenv fdt_high 0xffffffff
261 20:16:54.736724 - dhcp
262 20:16:54.737112 - setenv serverip 192.168.6.2
263 20:16:54.737496 - tftpboot 0x01080000 936637/tftp-deploy-k2uiga9a/kernel/uImage
264 20:16:54.737884 - tftpboot 0x08000000 936637/tftp-deploy-k2uiga9a/ramdisk/ramdisk.cpio.gz.uboot
265 20:16:54.738269 - tftpboot 0x01070000 936637/tftp-deploy-k2uiga9a/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 20:16:54.738655 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 20:16:54.739051 - bootm 0x01080000 0x08000000 0x01070000
268 20:16:54.739541 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 20:16:54.741043 start: 2.3 connect-device (timeout 00:05:00) [common]
271 20:16:54.741481 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 20:16:54.755848 Setting prompt string to ['lava-test: # ']
273 20:16:54.757367 end: 2.3 connect-device (duration 00:00:00) [common]
274 20:16:54.757967 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 20:16:54.758509 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 20:16:54.759031 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 20:16:54.760194 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 20:16:54.797630 >> OK - accepted request
279 20:16:54.799938 Returned 0 in 0 seconds
280 20:16:54.901121 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 20:16:54.902790 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 20:16:54.903346 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 20:16:54.903837 Setting prompt string to ['Hit any key to stop autoboot']
285 20:16:54.904330 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 20:16:54.905884 Trying 192.168.56.21...
287 20:16:54.906344 Connected to conserv1.
288 20:16:54.906738 Escape character is '^]'.
289 20:16:54.907145
290 20:16:54.907565 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 20:16:54.908017
292 20:17:01.674706 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 20:17:01.675131 bl2_stage_init 0x01
294 20:17:01.675370 bl2_stage_init 0x81
295 20:17:01.680254 hw id: 0x0000 - pwm id 0x01
296 20:17:01.680560 bl2_stage_init 0xc1
297 20:17:01.684503 bl2_stage_init 0x02
298 20:17:01.684788
299 20:17:01.685020 L0:00000000
300 20:17:01.685236 L1:00000703
301 20:17:01.685456 L2:00008067
302 20:17:01.690016 L3:15000000
303 20:17:01.690305 S1:00000000
304 20:17:01.690529 B2:20282000
305 20:17:01.690750 B1:a0f83180
306 20:17:01.690956
307 20:17:01.691162 TE: 70856
308 20:17:01.695621
309 20:17:01.701209 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 20:17:01.701489
311 20:17:01.701719 Board ID = 1
312 20:17:01.701930 Set cpu clk to 24M
313 20:17:01.704545 Set clk81 to 24M
314 20:17:01.704800 Use GP1_pll as DSU clk.
315 20:17:01.710125 DSU clk: 1200 Mhz
316 20:17:01.710388 CPU clk: 1200 MHz
317 20:17:01.710614 Set clk81 to 166.6M
318 20:17:01.715839 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 20:17:01.721330 board id: 1
320 20:17:01.725926 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 20:17:01.737436 fw parse done
322 20:17:01.743382 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 20:17:01.786086 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 20:17:01.797052 PIEI prepare done
325 20:17:01.797579 fastboot data load
326 20:17:01.797989 fastboot data verify
327 20:17:01.803459 verify result: 266
328 20:17:01.808255 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 20:17:01.808760 LPDDR4 probe
330 20:17:01.809171 ddr clk to 1584MHz
331 20:17:01.816336 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 20:17:01.853408
333 20:17:01.853959 dmc_version 0001
334 20:17:01.860109 Check phy result
335 20:17:01.866025 INFO : End of CA training
336 20:17:01.866517 INFO : End of initialization
337 20:17:01.871555 INFO : Training has run successfully!
338 20:17:01.872105 Check phy result
339 20:17:01.877141 INFO : End of initialization
340 20:17:01.877625 INFO : End of read enable training
341 20:17:01.882776 INFO : End of fine write leveling
342 20:17:01.888384 INFO : End of Write leveling coarse delay
343 20:17:01.888869 INFO : Training has run successfully!
344 20:17:01.889263 Check phy result
345 20:17:01.894030 INFO : End of initialization
346 20:17:01.894514 INFO : End of read dq deskew training
347 20:17:01.899537 INFO : End of MPR read delay center optimization
348 20:17:01.905168 INFO : End of write delay center optimization
349 20:17:01.910768 INFO : End of read delay center optimization
350 20:17:01.911246 INFO : End of max read latency training
351 20:17:01.916391 INFO : Training has run successfully!
352 20:17:01.916889 1D training succeed
353 20:17:01.925492 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 20:17:01.973146 Check phy result
355 20:17:01.973679 INFO : End of initialization
356 20:17:01.994989 INFO : End of 2D read delay Voltage center optimization
357 20:17:02.013820 INFO : End of 2D read delay Voltage center optimization
358 20:17:02.066660 INFO : End of 2D write delay Voltage center optimization
359 20:17:02.115891 INFO : End of 2D write delay Voltage center optimization
360 20:17:02.121529 INFO : Training has run successfully!
361 20:17:02.122212
362 20:17:02.122759 channel==0
363 20:17:02.127071 RxClkDly_Margin_A0==88 ps 9
364 20:17:02.127739 TxDqDly_Margin_A0==98 ps 10
365 20:17:02.132547 RxClkDly_Margin_A1==88 ps 9
366 20:17:02.133176 TxDqDly_Margin_A1==88 ps 9
367 20:17:02.133713 TrainedVREFDQ_A0==74
368 20:17:02.138135 TrainedVREFDQ_A1==74
369 20:17:02.138739 VrefDac_Margin_A0==23
370 20:17:02.139250 DeviceVref_Margin_A0==40
371 20:17:02.143692 VrefDac_Margin_A1==23
372 20:17:02.144374 DeviceVref_Margin_A1==40
373 20:17:02.144908
374 20:17:02.145425
375 20:17:02.145935 channel==1
376 20:17:02.149358 RxClkDly_Margin_A0==78 ps 8
377 20:17:02.149978 TxDqDly_Margin_A0==98 ps 10
378 20:17:02.154969 RxClkDly_Margin_A1==78 ps 8
379 20:17:02.155580 TxDqDly_Margin_A1==88 ps 9
380 20:17:02.160498 TrainedVREFDQ_A0==78
381 20:17:02.161112 TrainedVREFDQ_A1==75
382 20:17:02.161630 VrefDac_Margin_A0==22
383 20:17:02.166267 DeviceVref_Margin_A0==36
384 20:17:02.166919 VrefDac_Margin_A1==22
385 20:17:02.172270 DeviceVref_Margin_A1==39
386 20:17:02.173018
387 20:17:02.173581 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 20:17:02.174104
389 20:17:02.205352 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 20:17:02.206098 2D training succeed
391 20:17:02.210918 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 20:17:02.216539 auto size-- 65535DDR cs0 size: 2048MB
393 20:17:02.217148 DDR cs1 size: 2048MB
394 20:17:02.222218 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 20:17:02.222731 cs0 DataBus test pass
396 20:17:02.227694 cs1 DataBus test pass
397 20:17:02.228208 cs0 AddrBus test pass
398 20:17:02.228609 cs1 AddrBus test pass
399 20:17:02.229002
400 20:17:02.233342 100bdlr_step_size ps== 478
401 20:17:02.233825 result report
402 20:17:02.238864 boot times 0Enable ddr reg access
403 20:17:02.244110 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 20:17:02.256982 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 20:17:02.912779 bl2z: ptr: 05129330, size: 00001e40
406 20:17:02.919213 0.0;M3 CHK:0;cm4_sp_mode 0
407 20:17:02.919692 MVN_1=0x00000000
408 20:17:02.920149 MVN_2=0x00000000
409 20:17:02.930679 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 20:17:02.931182 OPS=0x04
411 20:17:02.931582 ring efuse init
412 20:17:02.933703 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 20:17:02.939731 [0.017319 Inits done]
414 20:17:02.940227 secure task start!
415 20:17:02.940628 high task start!
416 20:17:02.941016 low task start!
417 20:17:02.943936 run into bl31
418 20:17:02.952606 NOTICE: BL31: v1.3(release):4fc40b1
419 20:17:02.960384 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 20:17:02.960845 NOTICE: BL31: G12A normal boot!
421 20:17:02.975889 NOTICE: BL31: BL33 decompress pass
422 20:17:02.981610 ERROR: Error initializing runtime service opteed_fast
423 20:17:05.721351 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 20:17:05.721979 bl2_stage_init 0x01
425 20:17:05.722384 bl2_stage_init 0x81
426 20:17:05.726939 hw id: 0x0000 - pwm id 0x01
427 20:17:05.727409 bl2_stage_init 0xc1
428 20:17:05.732515 bl2_stage_init 0x02
429 20:17:05.732965
430 20:17:05.733365 L0:00000000
431 20:17:05.733752 L1:00000703
432 20:17:05.734135 L2:00008067
433 20:17:05.734520 L3:15000000
434 20:17:05.738105 S1:00000000
435 20:17:05.738543 B2:20282000
436 20:17:05.738933 B1:a0f83180
437 20:17:05.739313
438 20:17:05.739696 TE: 67634
439 20:17:05.740117
440 20:17:05.743706 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 20:17:05.744181
442 20:17:05.749296 Board ID = 1
443 20:17:05.749733 Set cpu clk to 24M
444 20:17:05.750122 Set clk81 to 24M
445 20:17:05.754904 Use GP1_pll as DSU clk.
446 20:17:05.755338 DSU clk: 1200 Mhz
447 20:17:05.755723 CPU clk: 1200 MHz
448 20:17:05.760495 Set clk81 to 166.6M
449 20:17:05.766110 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 20:17:05.766595 board id: 1
451 20:17:05.772597 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 20:17:05.783977 fw parse done
453 20:17:05.789920 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 20:17:05.831679 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 20:17:05.843467 PIEI prepare done
456 20:17:05.843904 fastboot data load
457 20:17:05.844338 fastboot data verify
458 20:17:05.849177 verify result: 266
459 20:17:05.854712 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 20:17:05.855149 LPDDR4 probe
461 20:17:05.855540 ddr clk to 1584MHz
462 20:17:05.862687 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 20:17:05.899943
464 20:17:05.900417 dmc_version 0001
465 20:17:05.906680 Check phy result
466 20:17:05.912589 INFO : End of CA training
467 20:17:05.913029 INFO : End of initialization
468 20:17:05.918157 INFO : Training has run successfully!
469 20:17:05.918587 Check phy result
470 20:17:05.923737 INFO : End of initialization
471 20:17:05.924201 INFO : End of read enable training
472 20:17:05.929331 INFO : End of fine write leveling
473 20:17:05.934936 INFO : End of Write leveling coarse delay
474 20:17:05.935365 INFO : Training has run successfully!
475 20:17:05.935757 Check phy result
476 20:17:05.940536 INFO : End of initialization
477 20:17:05.940971 INFO : End of read dq deskew training
478 20:17:05.946139 INFO : End of MPR read delay center optimization
479 20:17:05.951714 INFO : End of write delay center optimization
480 20:17:05.957346 INFO : End of read delay center optimization
481 20:17:05.957780 INFO : End of max read latency training
482 20:17:05.962947 INFO : Training has run successfully!
483 20:17:05.963374 1D training succeed
484 20:17:05.972233 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 20:17:06.018858 Check phy result
486 20:17:06.019323 INFO : End of initialization
487 20:17:06.042138 INFO : End of 2D read delay Voltage center optimization
488 20:17:06.061264 INFO : End of 2D read delay Voltage center optimization
489 20:17:06.113158 INFO : End of 2D write delay Voltage center optimization
490 20:17:06.162309 INFO : End of 2D write delay Voltage center optimization
491 20:17:06.167866 INFO : Training has run successfully!
492 20:17:06.168335
493 20:17:06.168734 channel==0
494 20:17:06.173558 RxClkDly_Margin_A0==69 ps 7
495 20:17:06.173988 TxDqDly_Margin_A0==98 ps 10
496 20:17:06.179078 RxClkDly_Margin_A1==88 ps 9
497 20:17:06.179516 TxDqDly_Margin_A1==98 ps 10
498 20:17:06.179907 TrainedVREFDQ_A0==74
499 20:17:06.184678 TrainedVREFDQ_A1==74
500 20:17:06.185118 VrefDac_Margin_A0==23
501 20:17:06.185509 DeviceVref_Margin_A0==40
502 20:17:06.190289 VrefDac_Margin_A1==23
503 20:17:06.190719 DeviceVref_Margin_A1==40
504 20:17:06.191114
505 20:17:06.191501
506 20:17:06.195964 channel==1
507 20:17:06.196615 RxClkDly_Margin_A0==78 ps 8
508 20:17:06.197150 TxDqDly_Margin_A0==98 ps 10
509 20:17:06.201624 RxClkDly_Margin_A1==88 ps 9
510 20:17:06.202212 TxDqDly_Margin_A1==88 ps 9
511 20:17:06.207156 TrainedVREFDQ_A0==77
512 20:17:06.207751 TrainedVREFDQ_A1==75
513 20:17:06.208333 VrefDac_Margin_A0==23
514 20:17:06.212710 DeviceVref_Margin_A0==37
515 20:17:06.213271 VrefDac_Margin_A1==22
516 20:17:06.218296 DeviceVref_Margin_A1==39
517 20:17:06.218872
518 20:17:06.219387 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 20:17:06.219896
520 20:17:06.251899 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000019 00000017 00000019 00000015 00000018 00000015 00000015 00000017 00000018 00000019 00000018 00000019 0000001c 00000018 00000015 00000017 dram_vref_reg_value 0x 00000061
521 20:17:06.252566 2D training succeed
522 20:17:06.257667 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 20:17:06.263108 auto size-- 65535DDR cs0 size: 2048MB
524 20:17:06.263675 DDR cs1 size: 2048MB
525 20:17:06.268697 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 20:17:06.269257 cs0 DataBus test pass
527 20:17:06.274308 cs1 DataBus test pass
528 20:17:06.274871 cs0 AddrBus test pass
529 20:17:06.275381 cs1 AddrBus test pass
530 20:17:06.275886
531 20:17:06.279909 100bdlr_step_size ps== 478
532 20:17:06.280538 result report
533 20:17:06.285636 boot times 0Enable ddr reg access
534 20:17:06.290749 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 20:17:06.304709 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 20:17:06.958513 bl2z: ptr: 05129330, size: 00001e40
537 20:17:06.965882 0.0;M3 CHK:0;cm4_sp_mode 0
538 20:17:06.966511 MVN_1=0x00000000
539 20:17:06.967025 MVN_2=0x00000000
540 20:17:06.977303 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 20:17:06.977924 OPS=0x04
542 20:17:06.978443 ring efuse init
543 20:17:06.982943 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 20:17:06.983537 [0.017319 Inits done]
545 20:17:06.984096 secure task start!
546 20:17:06.990756 high task start!
547 20:17:06.991335 low task start!
548 20:17:06.991848 run into bl31
549 20:17:06.999323 NOTICE: BL31: v1.3(release):4fc40b1
550 20:17:07.007141 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 20:17:07.007746 NOTICE: BL31: G12A normal boot!
552 20:17:07.022692 NOTICE: BL31: BL33 decompress pass
553 20:17:07.028402 ERROR: Error initializing runtime service opteed_fast
554 20:17:08.424169 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 20:17:08.424950 bl2_stage_init 0x01
556 20:17:08.425497 bl2_stage_init 0x81
557 20:17:08.429704 hw id: 0x0000 - pwm id 0x01
558 20:17:08.430296 bl2_stage_init 0xc1
559 20:17:08.433906 bl2_stage_init 0x02
560 20:17:08.434496
561 20:17:08.435017 L0:00000000
562 20:17:08.435527 L1:00000703
563 20:17:08.436070 L2:00008067
564 20:17:08.439399 L3:15000000
565 20:17:08.439974 S1:00000000
566 20:17:08.440539 B2:20282000
567 20:17:08.441045 B1:a0f83180
568 20:17:08.441548
569 20:17:08.445035 TE: 70051
570 20:17:08.445632
571 20:17:08.450635 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 20:17:08.451217
573 20:17:08.451731 Board ID = 1
574 20:17:08.452279 Set cpu clk to 24M
575 20:17:08.456221 Set clk81 to 24M
576 20:17:08.456806 Use GP1_pll as DSU clk.
577 20:17:08.457327 DSU clk: 1200 Mhz
578 20:17:08.461868 CPU clk: 1200 MHz
579 20:17:08.462454 Set clk81 to 166.6M
580 20:17:08.467423 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 20:17:08.468026 board id: 1
582 20:17:08.473006 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 20:17:08.487002 fw parse done
584 20:17:08.492950 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 20:17:08.536114 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 20:17:08.547245 PIEI prepare done
587 20:17:08.547816 fastboot data load
588 20:17:08.548391 fastboot data verify
589 20:17:08.552930 verify result: 266
590 20:17:08.558454 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 20:17:08.559040 LPDDR4 probe
592 20:17:08.559568 ddr clk to 1584MHz
593 20:17:08.566390 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 20:17:08.604057
595 20:17:08.604695 dmc_version 0001
596 20:17:08.611187 Check phy result
597 20:17:08.617178 INFO : End of CA training
598 20:17:08.617766 INFO : End of initialization
599 20:17:08.622756 INFO : Training has run successfully!
600 20:17:08.623318 Check phy result
601 20:17:08.628380 INFO : End of initialization
602 20:17:08.628953 INFO : End of read enable training
603 20:17:08.633952 INFO : End of fine write leveling
604 20:17:08.639573 INFO : End of Write leveling coarse delay
605 20:17:08.640196 INFO : Training has run successfully!
606 20:17:08.640716 Check phy result
607 20:17:08.645158 INFO : End of initialization
608 20:17:08.645736 INFO : End of read dq deskew training
609 20:17:08.650744 INFO : End of MPR read delay center optimization
610 20:17:08.656318 INFO : End of write delay center optimization
611 20:17:08.661971 INFO : End of read delay center optimization
612 20:17:08.662547 INFO : End of max read latency training
613 20:17:08.667596 INFO : Training has run successfully!
614 20:17:08.668195 1D training succeed
615 20:17:08.676710 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 20:17:08.724299 Check phy result
617 20:17:08.724931 INFO : End of initialization
618 20:17:08.752373 INFO : End of 2D read delay Voltage center optimization
619 20:17:08.776579 INFO : End of 2D read delay Voltage center optimization
620 20:17:08.833301 INFO : End of 2D write delay Voltage center optimization
621 20:17:08.887345 INFO : End of 2D write delay Voltage center optimization
622 20:17:08.893002 INFO : Training has run successfully!
623 20:17:08.893585
624 20:17:08.894126 channel==0
625 20:17:08.898488 RxClkDly_Margin_A0==78 ps 8
626 20:17:08.899064 TxDqDly_Margin_A0==98 ps 10
627 20:17:08.904070 RxClkDly_Margin_A1==88 ps 9
628 20:17:08.904644 TxDqDly_Margin_A1==88 ps 9
629 20:17:08.905154 TrainedVREFDQ_A0==74
630 20:17:08.909682 TrainedVREFDQ_A1==74
631 20:17:08.910259 VrefDac_Margin_A0==23
632 20:17:08.910768 DeviceVref_Margin_A0==40
633 20:17:08.915321 VrefDac_Margin_A1==23
634 20:17:08.915881 DeviceVref_Margin_A1==40
635 20:17:08.916431
636 20:17:08.916952
637 20:17:08.917468 channel==1
638 20:17:08.921048 RxClkDly_Margin_A0==78 ps 8
639 20:17:08.921628 TxDqDly_Margin_A0==98 ps 10
640 20:17:08.926461 RxClkDly_Margin_A1==78 ps 8
641 20:17:08.927040 TxDqDly_Margin_A1==78 ps 8
642 20:17:08.932086 TrainedVREFDQ_A0==78
643 20:17:08.932649 TrainedVREFDQ_A1==76
644 20:17:08.933160 VrefDac_Margin_A0==22
645 20:17:08.937655 DeviceVref_Margin_A0==36
646 20:17:08.938219 VrefDac_Margin_A1==20
647 20:17:08.943225 DeviceVref_Margin_A1==38
648 20:17:08.943798
649 20:17:08.944334 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 20:17:08.944835
651 20:17:08.977008 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
652 20:17:08.977672 2D training succeed
653 20:17:08.982460 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 20:17:08.988077 auto size-- 65535DDR cs0 size: 2048MB
655 20:17:08.988654 DDR cs1 size: 2048MB
656 20:17:08.993674 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 20:17:08.994232 cs0 DataBus test pass
658 20:17:08.999259 cs1 DataBus test pass
659 20:17:08.999840 cs0 AddrBus test pass
660 20:17:09.000396 cs1 AddrBus test pass
661 20:17:09.000902
662 20:17:09.004876 100bdlr_step_size ps== 471
663 20:17:09.005452 result report
664 20:17:09.010438 boot times 0Enable ddr reg access
665 20:17:09.015667 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 20:17:09.029502 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 20:17:09.689292 bl2z: ptr: 05129330, size: 00001e40
668 20:17:09.700368 0.0;M3 CHK:0;cm4_sp_mode 0
669 20:17:09.701012 MVN_1=0x00000000
670 20:17:09.701559 MVN_2=0x00000000
671 20:17:09.711820 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 20:17:09.712485 OPS=0x04
673 20:17:09.713027 ring efuse init
674 20:17:09.717493 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 20:17:09.718100 [0.017354 Inits done]
676 20:17:09.718635 secure task start!
677 20:17:09.725138 high task start!
678 20:17:09.725728 low task start!
679 20:17:09.726259 run into bl31
680 20:17:09.733728 NOTICE: BL31: v1.3(release):4fc40b1
681 20:17:09.741534 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 20:17:09.742131 NOTICE: BL31: G12A normal boot!
683 20:17:09.757114 NOTICE: BL31: BL33 decompress pass
684 20:17:09.762788 ERROR: Error initializing runtime service opteed_fast
685 20:17:10.558106
686 20:17:10.558879
687 20:17:10.563563 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 20:17:10.564228
689 20:17:10.566082 Model: Libre Computer AML-S905D3-CC Solitude
690 20:17:10.714094 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 20:17:10.729404 DRAM: 2 GiB (effective 3.8 GiB)
692 20:17:10.830412 Core: 406 devices, 33 uclasses, devicetree: separate
693 20:17:10.836311 WDT: Not starting watchdog@f0d0
694 20:17:10.861357 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 20:17:10.873782 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 20:17:10.877764 ** Bad device specification mmc 0 **
697 20:17:10.888757 Card did not respond to voltage select! : -110
698 20:17:10.896352 ** Bad device specification mmc 0 **
699 20:17:10.896838 Couldn't find partition mmc 0
700 20:17:10.904637 Card did not respond to voltage select! : -110
701 20:17:10.910196 ** Bad device specification mmc 0 **
702 20:17:10.910664 Couldn't find partition mmc 0
703 20:17:10.915278 Error: could not access storage.
704 20:17:11.211583 Net: eth0: ethernet@ff3f0000
705 20:17:11.212198 starting USB...
706 20:17:11.456386 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 20:17:11.456970 Starting the controller
708 20:17:11.463414 USB XHCI 1.10
709 20:17:13.019589 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 20:17:13.027826 scanning usb for storage devices... 0 Storage Device(s) found
712 20:17:13.079329 Hit any key to stop autoboot: 1
713 20:17:13.080371 end: 2.4.2 bootloader-interrupt (duration 00:00:18) [common]
714 20:17:13.080994 start: 2.4.3 bootloader-commands (timeout 00:04:42) [common]
715 20:17:13.081475 Setting prompt string to ['=>']
716 20:17:13.081946 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:42)
717 20:17:13.093162 0
718 20:17:13.094047 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 20:17:13.195233 => setenv autoload no
721 20:17:13.196134 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
722 20:17:13.200978 setenv autoload no
724 20:17:13.302422 => setenv initrd_high 0xffffffff
725 20:17:13.303316 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 20:17:13.307823 setenv initrd_high 0xffffffff
728 20:17:13.409291 => setenv fdt_high 0xffffffff
729 20:17:13.410170 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 20:17:13.414516 setenv fdt_high 0xffffffff
732 20:17:13.516038 => dhcp
733 20:17:13.516919 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 20:17:13.521200 dhcp
735 20:17:14.076443 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 20:17:14.077046 Speed: 1000, full duplex
737 20:17:14.077473 BOOTP broadcast 1
738 20:17:14.087019 DHCP client bound to address 192.168.6.21 (10 ms)
740 20:17:14.188505 => setenv serverip 192.168.6.2
741 20:17:14.189409 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
742 20:17:14.193919 setenv serverip 192.168.6.2
744 20:17:14.295370 => tftpboot 0x01080000 936637/tftp-deploy-k2uiga9a/kernel/uImage
745 20:17:14.296168 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
746 20:17:14.302797 tftpboot 0x01080000 936637/tftp-deploy-k2uiga9a/kernel/uImage
747 20:17:14.303308 Speed: 1000, full duplex
748 20:17:14.303759 Using ethernet@ff3f0000 device
749 20:17:14.308398 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
750 20:17:14.313851 Filename '936637/tftp-deploy-k2uiga9a/kernel/uImage'.
751 20:17:14.317876 Load address: 0x1080000
752 20:17:17.306080 Loading: *################################################## 43.6 MiB
753 20:17:17.306701 14.6 MiB/s
754 20:17:17.307128 done
755 20:17:17.310700 Bytes transferred = 45713984 (2b98a40 hex)
757 20:17:17.412161 => tftpboot 0x08000000 936637/tftp-deploy-k2uiga9a/ramdisk/ramdisk.cpio.gz.uboot
758 20:17:17.412761 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
759 20:17:17.419504 tftpboot 0x08000000 936637/tftp-deploy-k2uiga9a/ramdisk/ramdisk.cpio.gz.uboot
760 20:17:17.419773 Speed: 1000, full duplex
761 20:17:17.420015 Using ethernet@ff3f0000 device
762 20:17:17.424957 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
763 20:17:17.434972 Filename '936637/tftp-deploy-k2uiga9a/ramdisk/ramdisk.cpio.gz.uboot'.
764 20:17:17.435272 Load address: 0x8000000
765 20:17:19.083936 Loading: *################################################# UDP wrong checksum 00000005 0000a32c
766 20:17:24.085913 T UDP wrong checksum 00000005 0000a32c
767 20:17:34.087862 T T UDP wrong checksum 00000005 0000a32c
768 20:17:34.362059 UDP wrong checksum 00000005 00006414
769 20:17:45.416774 T T UDP wrong checksum 000000ff 00001541
770 20:17:45.428973 UDP wrong checksum 000000ff 00009e33
771 20:17:54.089261 T UDP wrong checksum 00000005 0000a32c
772 20:17:58.628159 T UDP wrong checksum 000000ff 00007bc2
773 20:17:58.652275 UDP wrong checksum 000000ff 000012b5
774 20:17:58.674258 UDP wrong checksum 000000ff 00006af7
775 20:17:58.730229 UDP wrong checksum 000000ff 0000aaa3
776 20:17:58.757749 UDP wrong checksum 000000ff 0000f5e9
777 20:17:58.780118 UDP wrong checksum 000000ff 00003b96
778 20:18:14.096131 T T T
779 20:18:14.096729 Retry count exceeded; starting again
781 20:18:14.098173 end: 2.4.3 bootloader-commands (duration 00:01:01) [common]
784 20:18:14.100071 end: 2.4 uboot-commands (duration 00:01:19) [common]
786 20:18:14.101450 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
788 20:18:14.102521 end: 2 uboot-action (duration 00:01:19) [common]
790 20:18:14.104033 Cleaning after the job
791 20:18:14.104603 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936637/tftp-deploy-k2uiga9a/ramdisk
792 20:18:14.105921 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936637/tftp-deploy-k2uiga9a/kernel
793 20:18:14.157073 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936637/tftp-deploy-k2uiga9a/dtb
794 20:18:14.158139 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936637/tftp-deploy-k2uiga9a/modules
795 20:18:14.183373 start: 4.1 power-off (timeout 00:00:30) [common]
796 20:18:14.184261 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
797 20:18:14.222411 >> OK - accepted request
798 20:18:14.224924 Returned 0 in 0 seconds
799 20:18:14.325724 end: 4.1 power-off (duration 00:00:00) [common]
801 20:18:14.326714 start: 4.2 read-feedback (timeout 00:10:00) [common]
802 20:18:14.327371 Listened to connection for namespace 'common' for up to 1s
803 20:18:15.328338 Finalising connection for namespace 'common'
804 20:18:15.329050 Disconnecting from shell: Finalise
805 20:18:15.329556 =>
806 20:18:15.430518 end: 4.2 read-feedback (duration 00:00:01) [common]
807 20:18:15.431237 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/936637
808 20:18:15.749690 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/936637
809 20:18:15.750281 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.