Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 20:09:36.354191 lava-dispatcher, installed at version: 2024.01
2 20:09:36.354968 start: 0 validate
3 20:09:36.355479 Start time: 2024-11-04 20:09:36.355448+00:00 (UTC)
4 20:09:36.356056 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 20:09:36.356609 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 20:09:36.396524 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 20:09:36.397086 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-95-g6db936d4ac0f%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 20:09:36.426821 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 20:09:36.427806 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-95-g6db936d4ac0f%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 20:09:36.457818 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 20:09:36.458404 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 20:09:36.491957 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 20:09:36.492532 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-95-g6db936d4ac0f%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 20:09:36.529983 validate duration: 0.17
16 20:09:36.530878 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 20:09:36.531233 start: 1.1 download-retry (timeout 00:10:00) [common]
18 20:09:36.531564 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 20:09:36.532183 Not decompressing ramdisk as can be used compressed.
20 20:09:36.532669 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 20:09:36.532970 saving as /var/lib/lava/dispatcher/tmp/936573/tftp-deploy-mv3tvvjf/ramdisk/initrd.cpio.gz
22 20:09:36.533257 total size: 5628182 (5 MB)
23 20:09:36.570211 progress 0 % (0 MB)
24 20:09:36.574367 progress 5 % (0 MB)
25 20:09:36.578442 progress 10 % (0 MB)
26 20:09:36.582043 progress 15 % (0 MB)
27 20:09:36.585998 progress 20 % (1 MB)
28 20:09:36.589605 progress 25 % (1 MB)
29 20:09:36.593545 progress 30 % (1 MB)
30 20:09:36.597470 progress 35 % (1 MB)
31 20:09:36.600981 progress 40 % (2 MB)
32 20:09:36.604906 progress 45 % (2 MB)
33 20:09:36.608456 progress 50 % (2 MB)
34 20:09:36.612439 progress 55 % (2 MB)
35 20:09:36.616378 progress 60 % (3 MB)
36 20:09:36.619888 progress 65 % (3 MB)
37 20:09:36.623827 progress 70 % (3 MB)
38 20:09:36.627338 progress 75 % (4 MB)
39 20:09:36.631210 progress 80 % (4 MB)
40 20:09:36.634533 progress 85 % (4 MB)
41 20:09:36.638224 progress 90 % (4 MB)
42 20:09:36.641927 progress 95 % (5 MB)
43 20:09:36.645211 progress 100 % (5 MB)
44 20:09:36.645855 5 MB downloaded in 0.11 s (47.68 MB/s)
45 20:09:36.646409 end: 1.1.1 http-download (duration 00:00:00) [common]
47 20:09:36.647345 end: 1.1 download-retry (duration 00:00:00) [common]
48 20:09:36.647642 start: 1.2 download-retry (timeout 00:10:00) [common]
49 20:09:36.647917 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 20:09:36.648417 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-95-g6db936d4ac0f/arm64/defconfig/gcc-12/kernel/Image
51 20:09:36.648674 saving as /var/lib/lava/dispatcher/tmp/936573/tftp-deploy-mv3tvvjf/kernel/Image
52 20:09:36.648885 total size: 45713920 (43 MB)
53 20:09:36.649098 No compression specified
54 20:09:36.685295 progress 0 % (0 MB)
55 20:09:36.724462 progress 5 % (2 MB)
56 20:09:36.764143 progress 10 % (4 MB)
57 20:09:36.803442 progress 15 % (6 MB)
58 20:09:36.840740 progress 20 % (8 MB)
59 20:09:36.879915 progress 25 % (10 MB)
60 20:09:36.919648 progress 30 % (13 MB)
61 20:09:36.959382 progress 35 % (15 MB)
62 20:09:36.998945 progress 40 % (17 MB)
63 20:09:37.036375 progress 45 % (19 MB)
64 20:09:37.073939 progress 50 % (21 MB)
65 20:09:37.111048 progress 55 % (24 MB)
66 20:09:37.148644 progress 60 % (26 MB)
67 20:09:37.181909 progress 65 % (28 MB)
68 20:09:37.209863 progress 70 % (30 MB)
69 20:09:37.237624 progress 75 % (32 MB)
70 20:09:37.265114 progress 80 % (34 MB)
71 20:09:37.292935 progress 85 % (37 MB)
72 20:09:37.321552 progress 90 % (39 MB)
73 20:09:37.349121 progress 95 % (41 MB)
74 20:09:37.375922 progress 100 % (43 MB)
75 20:09:37.376472 43 MB downloaded in 0.73 s (59.92 MB/s)
76 20:09:37.376960 end: 1.2.1 http-download (duration 00:00:01) [common]
78 20:09:37.377790 end: 1.2 download-retry (duration 00:00:01) [common]
79 20:09:37.378069 start: 1.3 download-retry (timeout 00:09:59) [common]
80 20:09:37.378340 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 20:09:37.378845 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-95-g6db936d4ac0f/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 20:09:37.379128 saving as /var/lib/lava/dispatcher/tmp/936573/tftp-deploy-mv3tvvjf/dtb/meson-g12b-a311d-libretech-cc.dtb
83 20:09:37.379340 total size: 54703 (0 MB)
84 20:09:37.379551 No compression specified
85 20:09:37.425047 progress 59 % (0 MB)
86 20:09:37.425975 progress 100 % (0 MB)
87 20:09:37.426634 0 MB downloaded in 0.05 s (1.10 MB/s)
88 20:09:37.427167 end: 1.3.1 http-download (duration 00:00:00) [common]
90 20:09:37.428185 end: 1.3 download-retry (duration 00:00:00) [common]
91 20:09:37.428532 start: 1.4 download-retry (timeout 00:09:59) [common]
92 20:09:37.428848 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 20:09:37.429355 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 20:09:37.429654 saving as /var/lib/lava/dispatcher/tmp/936573/tftp-deploy-mv3tvvjf/nfsrootfs/full.rootfs.tar
95 20:09:37.429874 total size: 107552908 (102 MB)
96 20:09:37.430134 Using unxz to decompress xz
97 20:09:37.464238 progress 0 % (0 MB)
98 20:09:38.111276 progress 5 % (5 MB)
99 20:09:38.845492 progress 10 % (10 MB)
100 20:09:39.595969 progress 15 % (15 MB)
101 20:09:40.352243 progress 20 % (20 MB)
102 20:09:40.929638 progress 25 % (25 MB)
103 20:09:41.566242 progress 30 % (30 MB)
104 20:09:42.309799 progress 35 % (35 MB)
105 20:09:42.653735 progress 40 % (41 MB)
106 20:09:43.078540 progress 45 % (46 MB)
107 20:09:43.777510 progress 50 % (51 MB)
108 20:09:44.487803 progress 55 % (56 MB)
109 20:09:45.314464 progress 60 % (61 MB)
110 20:09:46.147471 progress 65 % (66 MB)
111 20:09:46.950344 progress 70 % (71 MB)
112 20:09:47.800054 progress 75 % (76 MB)
113 20:09:48.535747 progress 80 % (82 MB)
114 20:09:49.237715 progress 85 % (87 MB)
115 20:09:49.967721 progress 90 % (92 MB)
116 20:09:50.689767 progress 95 % (97 MB)
117 20:09:51.531861 progress 100 % (102 MB)
118 20:09:51.544244 102 MB downloaded in 14.11 s (7.27 MB/s)
119 20:09:51.545266 end: 1.4.1 http-download (duration 00:00:14) [common]
121 20:09:51.547033 end: 1.4 download-retry (duration 00:00:14) [common]
122 20:09:51.547628 start: 1.5 download-retry (timeout 00:09:45) [common]
123 20:09:51.548286 start: 1.5.1 http-download (timeout 00:09:45) [common]
124 20:09:51.549361 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-95-g6db936d4ac0f/arm64/defconfig/gcc-12/modules.tar.xz
125 20:09:51.549902 saving as /var/lib/lava/dispatcher/tmp/936573/tftp-deploy-mv3tvvjf/modules/modules.tar
126 20:09:51.550354 total size: 11612416 (11 MB)
127 20:09:51.550814 Using unxz to decompress xz
128 20:09:51.589857 progress 0 % (0 MB)
129 20:09:51.656525 progress 5 % (0 MB)
130 20:09:51.732112 progress 10 % (1 MB)
131 20:09:51.830068 progress 15 % (1 MB)
132 20:09:51.922663 progress 20 % (2 MB)
133 20:09:52.002250 progress 25 % (2 MB)
134 20:09:52.083634 progress 30 % (3 MB)
135 20:09:52.163484 progress 35 % (3 MB)
136 20:09:52.236834 progress 40 % (4 MB)
137 20:09:52.313444 progress 45 % (5 MB)
138 20:09:52.398199 progress 50 % (5 MB)
139 20:09:52.475764 progress 55 % (6 MB)
140 20:09:52.561598 progress 60 % (6 MB)
141 20:09:52.642875 progress 65 % (7 MB)
142 20:09:52.723564 progress 70 % (7 MB)
143 20:09:52.801584 progress 75 % (8 MB)
144 20:09:52.885104 progress 80 % (8 MB)
145 20:09:52.965127 progress 85 % (9 MB)
146 20:09:53.044848 progress 90 % (9 MB)
147 20:09:53.122597 progress 95 % (10 MB)
148 20:09:53.199360 progress 100 % (11 MB)
149 20:09:53.211268 11 MB downloaded in 1.66 s (6.67 MB/s)
150 20:09:53.211870 end: 1.5.1 http-download (duration 00:00:02) [common]
152 20:09:53.213550 end: 1.5 download-retry (duration 00:00:02) [common]
153 20:09:53.214124 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 20:09:53.214690 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 20:10:02.892513 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/936573/extract-nfsrootfs-1_5nxmgg
156 20:10:02.893112 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 20:10:02.893403 start: 1.6.2 lava-overlay (timeout 00:09:34) [common]
158 20:10:02.894017 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u
159 20:10:02.894443 makedir: /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin
160 20:10:02.894766 makedir: /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/tests
161 20:10:02.895077 makedir: /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/results
162 20:10:02.895414 Creating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin/lava-add-keys
163 20:10:02.895930 Creating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin/lava-add-sources
164 20:10:02.896458 Creating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin/lava-background-process-start
165 20:10:02.896943 Creating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin/lava-background-process-stop
166 20:10:02.897465 Creating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin/lava-common-functions
167 20:10:02.897944 Creating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin/lava-echo-ipv4
168 20:10:02.898418 Creating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin/lava-install-packages
169 20:10:02.898952 Creating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin/lava-installed-packages
170 20:10:02.899447 Creating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin/lava-os-build
171 20:10:02.899947 Creating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin/lava-probe-channel
172 20:10:02.900449 Creating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin/lava-probe-ip
173 20:10:02.900920 Creating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin/lava-target-ip
174 20:10:02.901386 Creating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin/lava-target-mac
175 20:10:02.901859 Creating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin/lava-target-storage
176 20:10:02.902336 Creating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin/lava-test-case
177 20:10:02.902806 Creating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin/lava-test-event
178 20:10:02.903285 Creating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin/lava-test-feedback
179 20:10:02.903770 Creating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin/lava-test-raise
180 20:10:02.904265 Creating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin/lava-test-reference
181 20:10:02.904736 Creating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin/lava-test-runner
182 20:10:02.905204 Creating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin/lava-test-set
183 20:10:02.905669 Creating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin/lava-test-shell
184 20:10:02.906142 Updating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin/lava-install-packages (oe)
185 20:10:02.906664 Updating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/bin/lava-installed-packages (oe)
186 20:10:02.907093 Creating /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/environment
187 20:10:02.907446 LAVA metadata
188 20:10:02.907702 - LAVA_JOB_ID=936573
189 20:10:02.907915 - LAVA_DISPATCHER_IP=192.168.6.2
190 20:10:02.908287 start: 1.6.2.1 ssh-authorize (timeout 00:09:34) [common]
191 20:10:02.909215 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 20:10:02.909519 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:34) [common]
193 20:10:02.909728 skipped lava-vland-overlay
194 20:10:02.909972 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 20:10:02.910227 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:34) [common]
196 20:10:02.910443 skipped lava-multinode-overlay
197 20:10:02.910686 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 20:10:02.910937 start: 1.6.2.4 test-definition (timeout 00:09:34) [common]
199 20:10:02.911181 Loading test definitions
200 20:10:02.911457 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:34) [common]
201 20:10:02.911677 Using /lava-936573 at stage 0
202 20:10:02.912867 uuid=936573_1.6.2.4.1 testdef=None
203 20:10:02.913173 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 20:10:02.913437 start: 1.6.2.4.2 test-overlay (timeout 00:09:34) [common]
205 20:10:02.915211 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 20:10:02.916023 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:34) [common]
208 20:10:02.918231 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 20:10:02.919043 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:34) [common]
211 20:10:02.921184 runner path: /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/0/tests/0_dmesg test_uuid 936573_1.6.2.4.1
212 20:10:02.921736 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 20:10:02.922490 Creating lava-test-runner.conf files
215 20:10:02.922691 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/936573/lava-overlay-c6svvq1u/lava-936573/0 for stage 0
216 20:10:02.923021 - 0_dmesg
217 20:10:02.923354 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 20:10:02.923625 start: 1.6.2.5 compress-overlay (timeout 00:09:34) [common]
219 20:10:02.944846 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 20:10:02.945203 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:34) [common]
221 20:10:02.945461 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 20:10:02.945727 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 20:10:02.945991 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
224 20:10:03.563946 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 20:10:03.564471 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
226 20:10:03.564742 extracting modules file /var/lib/lava/dispatcher/tmp/936573/tftp-deploy-mv3tvvjf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/936573/extract-nfsrootfs-1_5nxmgg
227 20:10:04.999217 extracting modules file /var/lib/lava/dispatcher/tmp/936573/tftp-deploy-mv3tvvjf/modules/modules.tar to /var/lib/lava/dispatcher/tmp/936573/extract-overlay-ramdisk-yowbqe66/ramdisk
228 20:10:06.565596 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 20:10:06.566085 start: 1.6.5 apply-overlay-tftp (timeout 00:09:30) [common]
230 20:10:06.566374 [common] Applying overlay to NFS
231 20:10:06.566586 [common] Applying overlay /var/lib/lava/dispatcher/tmp/936573/compress-overlay-iq0lekc5/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/936573/extract-nfsrootfs-1_5nxmgg
232 20:10:06.596169 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 20:10:06.596564 start: 1.6.6 prepare-kernel (timeout 00:09:30) [common]
234 20:10:06.596833 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:30) [common]
235 20:10:06.597061 Converting downloaded kernel to a uImage
236 20:10:06.597363 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/936573/tftp-deploy-mv3tvvjf/kernel/Image /var/lib/lava/dispatcher/tmp/936573/tftp-deploy-mv3tvvjf/kernel/uImage
237 20:10:07.052762 output: Image Name:
238 20:10:07.053172 output: Created: Mon Nov 4 20:10:06 2024
239 20:10:07.053378 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 20:10:07.053583 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 20:10:07.053784 output: Load Address: 01080000
242 20:10:07.053983 output: Entry Point: 01080000
243 20:10:07.054179 output:
244 20:10:07.054513 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 20:10:07.054779 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 20:10:07.055046 start: 1.6.7 configure-preseed-file (timeout 00:09:29) [common]
247 20:10:07.055297 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 20:10:07.055552 start: 1.6.8 compress-ramdisk (timeout 00:09:29) [common]
249 20:10:07.055804 Building ramdisk /var/lib/lava/dispatcher/tmp/936573/extract-overlay-ramdisk-yowbqe66/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/936573/extract-overlay-ramdisk-yowbqe66/ramdisk
250 20:10:09.207714 >> 166823 blocks
251 20:10:16.939797 Adding RAMdisk u-boot header.
252 20:10:16.940542 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/936573/extract-overlay-ramdisk-yowbqe66/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/936573/extract-overlay-ramdisk-yowbqe66/ramdisk.cpio.gz.uboot
253 20:10:17.182027 output: Image Name:
254 20:10:17.182449 output: Created: Mon Nov 4 20:10:16 2024
255 20:10:17.182874 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 20:10:17.183290 output: Data Size: 23431293 Bytes = 22882.12 KiB = 22.35 MiB
257 20:10:17.183691 output: Load Address: 00000000
258 20:10:17.184137 output: Entry Point: 00000000
259 20:10:17.184542 output:
260 20:10:17.185607 rename /var/lib/lava/dispatcher/tmp/936573/extract-overlay-ramdisk-yowbqe66/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/936573/tftp-deploy-mv3tvvjf/ramdisk/ramdisk.cpio.gz.uboot
261 20:10:17.186330 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 20:10:17.186884 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
263 20:10:17.187422 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
264 20:10:17.187882 No LXC device requested
265 20:10:17.188432 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 20:10:17.188953 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
267 20:10:17.189457 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 20:10:17.189871 Checking files for TFTP limit of 4294967296 bytes.
269 20:10:17.192580 end: 1 tftp-deploy (duration 00:00:41) [common]
270 20:10:17.193179 start: 2 uboot-action (timeout 00:05:00) [common]
271 20:10:17.193721 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 20:10:17.194227 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 20:10:17.194732 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 20:10:17.195259 Using kernel file from prepare-kernel: 936573/tftp-deploy-mv3tvvjf/kernel/uImage
275 20:10:17.195885 substitutions:
276 20:10:17.196333 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 20:10:17.196746 - {DTB_ADDR}: 0x01070000
278 20:10:17.197149 - {DTB}: 936573/tftp-deploy-mv3tvvjf/dtb/meson-g12b-a311d-libretech-cc.dtb
279 20:10:17.197548 - {INITRD}: 936573/tftp-deploy-mv3tvvjf/ramdisk/ramdisk.cpio.gz.uboot
280 20:10:17.197945 - {KERNEL_ADDR}: 0x01080000
281 20:10:17.198338 - {KERNEL}: 936573/tftp-deploy-mv3tvvjf/kernel/uImage
282 20:10:17.198733 - {LAVA_MAC}: None
283 20:10:17.199171 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/936573/extract-nfsrootfs-1_5nxmgg
284 20:10:17.199571 - {NFS_SERVER_IP}: 192.168.6.2
285 20:10:17.199961 - {PRESEED_CONFIG}: None
286 20:10:17.200428 - {PRESEED_LOCAL}: None
287 20:10:17.200825 - {RAMDISK_ADDR}: 0x08000000
288 20:10:17.201214 - {RAMDISK}: 936573/tftp-deploy-mv3tvvjf/ramdisk/ramdisk.cpio.gz.uboot
289 20:10:17.201620 - {ROOT_PART}: None
290 20:10:17.202022 - {ROOT}: None
291 20:10:17.202413 - {SERVER_IP}: 192.168.6.2
292 20:10:17.202803 - {TEE_ADDR}: 0x83000000
293 20:10:17.203192 - {TEE}: None
294 20:10:17.203581 Parsed boot commands:
295 20:10:17.203956 - setenv autoload no
296 20:10:17.204375 - setenv initrd_high 0xffffffff
297 20:10:17.204766 - setenv fdt_high 0xffffffff
298 20:10:17.205156 - dhcp
299 20:10:17.205542 - setenv serverip 192.168.6.2
300 20:10:17.205927 - tftpboot 0x01080000 936573/tftp-deploy-mv3tvvjf/kernel/uImage
301 20:10:17.206314 - tftpboot 0x08000000 936573/tftp-deploy-mv3tvvjf/ramdisk/ramdisk.cpio.gz.uboot
302 20:10:17.206705 - tftpboot 0x01070000 936573/tftp-deploy-mv3tvvjf/dtb/meson-g12b-a311d-libretech-cc.dtb
303 20:10:17.207091 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/936573/extract-nfsrootfs-1_5nxmgg,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 20:10:17.207491 - bootm 0x01080000 0x08000000 0x01070000
305 20:10:17.208036 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 20:10:17.209550 start: 2.3 connect-device (timeout 00:05:00) [common]
308 20:10:17.209975 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 20:10:17.226035 Setting prompt string to ['lava-test: # ']
310 20:10:17.227537 end: 2.3 connect-device (duration 00:00:00) [common]
311 20:10:17.228179 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 20:10:17.228745 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 20:10:17.229275 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 20:10:17.230449 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 20:10:17.268643 >> OK - accepted request
316 20:10:17.270710 Returned 0 in 0 seconds
317 20:10:17.371836 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 20:10:17.373548 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 20:10:17.374145 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 20:10:17.374670 Setting prompt string to ['Hit any key to stop autoboot']
322 20:10:17.375144 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 20:10:17.376754 Trying 192.168.56.21...
324 20:10:17.377254 Connected to conserv1.
325 20:10:17.377696 Escape character is '^]'.
326 20:10:17.378129
327 20:10:17.378575 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 20:10:17.379009
329 20:10:28.935404 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
330 20:10:28.936069 bl2_stage_init 0x81
331 20:10:28.941056 hw id: 0x0000 - pwm id 0x01
332 20:10:28.941581 bl2_stage_init 0xc1
333 20:10:28.941987 bl2_stage_init 0x02
334 20:10:28.942377
335 20:10:28.946485 L0:00000000
336 20:10:28.946926 L1:20000703
337 20:10:28.947319 L2:00008067
338 20:10:28.947707 L3:14000000
339 20:10:28.948124 B2:00402000
340 20:10:28.949396 B1:e0f83180
341 20:10:28.949816
342 20:10:28.950222 TE: 58150
343 20:10:28.950612
344 20:10:28.960608 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
345 20:10:28.961059
346 20:10:28.961456 Board ID = 1
347 20:10:28.961847 Set A53 clk to 24M
348 20:10:28.962234 Set A73 clk to 24M
349 20:10:28.966234 Set clk81 to 24M
350 20:10:28.966674 A53 clk: 1200 MHz
351 20:10:28.967064 A73 clk: 1200 MHz
352 20:10:28.969689 CLK81: 166.6M
353 20:10:28.970119 smccc: 00012aab
354 20:10:28.975234 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
355 20:10:28.980805 board id: 1
356 20:10:28.986040 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
357 20:10:28.996575 fw parse done
358 20:10:29.001620 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
359 20:10:29.044729 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
360 20:10:29.055966 PIEI prepare done
361 20:10:29.056530 fastboot data load
362 20:10:29.056928 fastboot data verify
363 20:10:29.061605 verify result: 266
364 20:10:29.067221 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
365 20:10:29.067746 LPDDR4 probe
366 20:10:29.068220 ddr clk to 1584MHz
367 20:10:29.075139 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
368 20:10:29.111679
369 20:10:29.112146 dmc_version 0001
370 20:10:29.118260 Check phy result
371 20:10:29.124940 INFO : End of CA training
372 20:10:29.125368 INFO : End of initialization
373 20:10:29.130579 INFO : Training has run successfully!
374 20:10:29.131000 Check phy result
375 20:10:29.136204 INFO : End of initialization
376 20:10:29.136625 INFO : End of read enable training
377 20:10:29.141766 INFO : End of fine write leveling
378 20:10:29.147393 INFO : End of Write leveling coarse delay
379 20:10:29.147831 INFO : Training has run successfully!
380 20:10:29.148269 Check phy result
381 20:10:29.152970 INFO : End of initialization
382 20:10:29.153395 INFO : End of read dq deskew training
383 20:10:29.158558 INFO : End of MPR read delay center optimization
384 20:10:29.164196 INFO : End of write delay center optimization
385 20:10:29.169743 INFO : End of read delay center optimization
386 20:10:29.170163 INFO : End of max read latency training
387 20:10:29.175398 INFO : Training has run successfully!
388 20:10:29.175845 1D training succeed
389 20:10:29.184222 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 20:10:29.231466 Check phy result
391 20:10:29.231891 INFO : End of initialization
392 20:10:29.253852 INFO : End of 2D read delay Voltage center optimization
393 20:10:29.273200 INFO : End of 2D read delay Voltage center optimization
394 20:10:29.325392 INFO : End of 2D write delay Voltage center optimization
395 20:10:29.375673 INFO : End of 2D write delay Voltage center optimization
396 20:10:29.381149 INFO : Training has run successfully!
397 20:10:29.381585
398 20:10:29.381994 channel==0
399 20:10:29.386773 RxClkDly_Margin_A0==88 ps 9
400 20:10:29.387196 TxDqDly_Margin_A0==98 ps 10
401 20:10:29.390121 RxClkDly_Margin_A1==88 ps 9
402 20:10:29.390550 TxDqDly_Margin_A1==88 ps 9
403 20:10:29.395664 TrainedVREFDQ_A0==74
404 20:10:29.396172 TrainedVREFDQ_A1==74
405 20:10:29.396591 VrefDac_Margin_A0==25
406 20:10:29.401183 DeviceVref_Margin_A0==40
407 20:10:29.401606 VrefDac_Margin_A1==25
408 20:10:29.406810 DeviceVref_Margin_A1==40
409 20:10:29.407231
410 20:10:29.407633
411 20:10:29.408068 channel==1
412 20:10:29.408474 RxClkDly_Margin_A0==98 ps 10
413 20:10:29.412651 TxDqDly_Margin_A0==98 ps 10
414 20:10:29.413083 RxClkDly_Margin_A1==98 ps 10
415 20:10:29.418060 TxDqDly_Margin_A1==88 ps 9
416 20:10:29.418483 TrainedVREFDQ_A0==77
417 20:10:29.418886 TrainedVREFDQ_A1==77
418 20:10:29.423582 VrefDac_Margin_A0==22
419 20:10:29.424028 DeviceVref_Margin_A0==37
420 20:10:29.429185 VrefDac_Margin_A1==22
421 20:10:29.429623 DeviceVref_Margin_A1==37
422 20:10:29.430020
423 20:10:29.434777 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
424 20:10:29.435203
425 20:10:29.462820 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
426 20:10:29.468408 2D training succeed
427 20:10:29.473979 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
428 20:10:29.474406 auto size-- 65535DDR cs0 size: 2048MB
429 20:10:29.479593 DDR cs1 size: 2048MB
430 20:10:29.480044 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
431 20:10:29.485196 cs0 DataBus test pass
432 20:10:29.485614 cs1 DataBus test pass
433 20:10:29.486014 cs0 AddrBus test pass
434 20:10:29.490746 cs1 AddrBus test pass
435 20:10:29.491164
436 20:10:29.491565 100bdlr_step_size ps== 420
437 20:10:29.491971 result report
438 20:10:29.496392 boot times 0Enable ddr reg access
439 20:10:29.504070 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
440 20:10:29.517248 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
441 20:10:30.091398 0.0;M3 CHK:0;cm4_sp_mode 0
442 20:10:30.091945 MVN_1=0x00000000
443 20:10:30.096908 MVN_2=0x00000000
444 20:10:30.102587 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
445 20:10:30.103020 OPS=0x10
446 20:10:30.103428 ring efuse init
447 20:10:30.103830 chipver efuse init
448 20:10:30.110852 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
449 20:10:30.111291 [0.018961 Inits done]
450 20:10:30.111694 secure task start!
451 20:10:30.117484 high task start!
452 20:10:30.117906 low task start!
453 20:10:30.118309 run into bl31
454 20:10:30.124906 NOTICE: BL31: v1.3(release):4fc40b1
455 20:10:30.132825 NOTICE: BL31: Built : 15:58:17, May 22 2019
456 20:10:30.133271 NOTICE: BL31: G12A normal boot!
457 20:10:30.158318 NOTICE: BL31: BL33 decompress pass
458 20:10:30.163924 ERROR: Error initializing runtime service opteed_fast
459 20:10:31.396807
460 20:10:31.397481
461 20:10:31.405203 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
462 20:10:31.405767
463 20:10:31.406234 Model: Libre Computer AML-A311D-CC Alta
464 20:10:31.613783 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
465 20:10:31.637007 DRAM: 2 GiB (effective 3.8 GiB)
466 20:10:31.779954 Core: 408 devices, 31 uclasses, devicetree: separate
467 20:10:31.785863 WDT: Not starting watchdog@f0d0
468 20:10:31.818019 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
469 20:10:31.830524 Loading Environment from FAT... Card did not respond to voltage select! : -110
470 20:10:31.834894 ** Bad device specification mmc 0 **
471 20:10:31.845754 Card did not respond to voltage select! : -110
472 20:10:31.853602 ** Bad device specification mmc 0 **
473 20:10:31.854116 Couldn't find partition mmc 0
474 20:10:31.861715 Card did not respond to voltage select! : -110
475 20:10:31.867357 ** Bad device specification mmc 0 **
476 20:10:31.867861 Couldn't find partition mmc 0
477 20:10:31.872357 Error: could not access storage.
478 20:10:33.135909 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
479 20:10:33.136577 bl2_stage_init 0x01
480 20:10:33.137053 bl2_stage_init 0x81
481 20:10:33.141604 hw id: 0x0000 - pwm id 0x01
482 20:10:33.142115 bl2_stage_init 0xc1
483 20:10:33.142573 bl2_stage_init 0x02
484 20:10:33.143024
485 20:10:33.147014 L0:00000000
486 20:10:33.147514 L1:20000703
487 20:10:33.147969 L2:00008067
488 20:10:33.148464 L3:14000000
489 20:10:33.152646 B2:00402000
490 20:10:33.153156 B1:e0f83180
491 20:10:33.153606
492 20:10:33.154050 TE: 58167
493 20:10:33.154496
494 20:10:33.158248 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
495 20:10:33.158755
496 20:10:33.159210 Board ID = 1
497 20:10:33.163753 Set A53 clk to 24M
498 20:10:33.164290 Set A73 clk to 24M
499 20:10:33.164746 Set clk81 to 24M
500 20:10:33.169387 A53 clk: 1200 MHz
501 20:10:33.169888 A73 clk: 1200 MHz
502 20:10:33.170339 CLK81: 166.6M
503 20:10:33.170781 smccc: 00012abe
504 20:10:33.175034 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
505 20:10:33.180628 board id: 1
506 20:10:33.186495 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
507 20:10:33.197163 fw parse done
508 20:10:33.203141 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
509 20:10:33.245687 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
510 20:10:33.256625 PIEI prepare done
511 20:10:33.257198 fastboot data load
512 20:10:33.257659 fastboot data verify
513 20:10:33.262730 verify result: 266
514 20:10:33.267816 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
515 20:10:33.268400 LPDDR4 probe
516 20:10:33.268867 ddr clk to 1584MHz
517 20:10:33.274864 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
518 20:10:33.313114
519 20:10:33.313756 dmc_version 0001
520 20:10:33.319700 Check phy result
521 20:10:33.325626 INFO : End of CA training
522 20:10:33.326152 INFO : End of initialization
523 20:10:33.331242 INFO : Training has run successfully!
524 20:10:33.331762 Check phy result
525 20:10:33.336721 INFO : End of initialization
526 20:10:33.337234 INFO : End of read enable training
527 20:10:33.342359 INFO : End of fine write leveling
528 20:10:33.347953 INFO : End of Write leveling coarse delay
529 20:10:33.348488 INFO : Training has run successfully!
530 20:10:33.348946 Check phy result
531 20:10:33.353645 INFO : End of initialization
532 20:10:33.354151 INFO : End of read dq deskew training
533 20:10:33.359196 INFO : End of MPR read delay center optimization
534 20:10:33.364845 INFO : End of write delay center optimization
535 20:10:33.370468 INFO : End of read delay center optimization
536 20:10:33.370978 INFO : End of max read latency training
537 20:10:33.376081 INFO : Training has run successfully!
538 20:10:33.376630 1D training succeed
539 20:10:33.385160 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 20:10:33.432815 Check phy result
541 20:10:33.433404 INFO : End of initialization
542 20:10:33.454619 INFO : End of 2D read delay Voltage center optimization
543 20:10:33.474787 INFO : End of 2D read delay Voltage center optimization
544 20:10:33.527029 INFO : End of 2D write delay Voltage center optimization
545 20:10:33.576486 INFO : End of 2D write delay Voltage center optimization
546 20:10:33.581916 INFO : Training has run successfully!
547 20:10:33.582418
548 20:10:33.582879 channel==0
549 20:10:33.587390 RxClkDly_Margin_A0==88 ps 9
550 20:10:33.587902 TxDqDly_Margin_A0==98 ps 10
551 20:10:33.592986 RxClkDly_Margin_A1==88 ps 9
552 20:10:33.593510 TxDqDly_Margin_A1==98 ps 10
553 20:10:33.593972 TrainedVREFDQ_A0==74
554 20:10:33.598808 TrainedVREFDQ_A1==74
555 20:10:33.599320 VrefDac_Margin_A0==25
556 20:10:33.599775 DeviceVref_Margin_A0==40
557 20:10:33.604225 VrefDac_Margin_A1==25
558 20:10:33.604727 DeviceVref_Margin_A1==40
559 20:10:33.605177
560 20:10:33.605627
561 20:10:33.609934 channel==1
562 20:10:33.610449 RxClkDly_Margin_A0==98 ps 10
563 20:10:33.610897 TxDqDly_Margin_A0==98 ps 10
564 20:10:33.615409 RxClkDly_Margin_A1==98 ps 10
565 20:10:33.615919 TxDqDly_Margin_A1==88 ps 9
566 20:10:33.620973 TrainedVREFDQ_A0==77
567 20:10:33.621480 TrainedVREFDQ_A1==77
568 20:10:33.621931 VrefDac_Margin_A0==22
569 20:10:33.626735 DeviceVref_Margin_A0==37
570 20:10:33.627234 VrefDac_Margin_A1==22
571 20:10:33.632261 DeviceVref_Margin_A1==37
572 20:10:33.632771
573 20:10:33.633228 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
574 20:10:33.637733
575 20:10:33.665763 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
576 20:10:33.666328 2D training succeed
577 20:10:33.671394 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
578 20:10:33.676927 auto size-- 65535DDR cs0 size: 2048MB
579 20:10:33.677455 DDR cs1 size: 2048MB
580 20:10:33.682545 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
581 20:10:33.683055 cs0 DataBus test pass
582 20:10:33.688177 cs1 DataBus test pass
583 20:10:33.688680 cs0 AddrBus test pass
584 20:10:33.689130 cs1 AddrBus test pass
585 20:10:33.689570
586 20:10:33.693702 100bdlr_step_size ps== 420
587 20:10:33.694214 result report
588 20:10:33.699325 boot times 0Enable ddr reg access
589 20:10:33.704722 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
590 20:10:33.718205 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
591 20:10:34.291916 0.0;M3 CHK:0;cm4_sp_mode 0
592 20:10:34.292576 MVN_1=0x00000000
593 20:10:34.297463 MVN_2=0x00000000
594 20:10:34.304871 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
595 20:10:34.305416 OPS=0x10
596 20:10:34.305869 ring efuse init
597 20:10:34.306296 chipver efuse init
598 20:10:34.308808 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
599 20:10:34.314340 [0.018961 Inits done]
600 20:10:34.314844 secure task start!
601 20:10:34.315275 high task start!
602 20:10:34.319048 low task start!
603 20:10:34.319537 run into bl31
604 20:10:34.325494 NOTICE: BL31: v1.3(release):4fc40b1
605 20:10:34.333392 NOTICE: BL31: Built : 15:58:17, May 22 2019
606 20:10:34.333882 NOTICE: BL31: G12A normal boot!
607 20:10:34.358759 NOTICE: BL31: BL33 decompress pass
608 20:10:34.364502 ERROR: Error initializing runtime service opteed_fast
609 20:10:35.597218
610 20:10:35.597878
611 20:10:35.605820 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
612 20:10:35.606352
613 20:10:35.606835 Model: Libre Computer AML-A311D-CC Alta
614 20:10:35.814140 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
615 20:10:35.837646 DRAM: 2 GiB (effective 3.8 GiB)
616 20:10:35.980877 Core: 408 devices, 31 uclasses, devicetree: separate
617 20:10:35.985554 WDT: Not starting watchdog@f0d0
618 20:10:36.018482 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
619 20:10:36.030889 Loading Environment from FAT... Card did not respond to voltage select! : -110
620 20:10:36.035941 ** Bad device specification mmc 0 **
621 20:10:36.046229 Card did not respond to voltage select! : -110
622 20:10:36.052985 ** Bad device specification mmc 0 **
623 20:10:36.053505 Couldn't find partition mmc 0
624 20:10:36.062274 Card did not respond to voltage select! : -110
625 20:10:36.067734 ** Bad device specification mmc 0 **
626 20:10:36.068288 Couldn't find partition mmc 0
627 20:10:36.071926 Error: could not access storage.
628 20:10:36.415221 Net: eth0: ethernet@ff3f0000
629 20:10:36.415823 starting USB...
630 20:10:36.667018 Bus usb@ff500000: Register 3000140 NbrPorts 3
631 20:10:36.667619 Starting the controller
632 20:10:36.674038 USB XHCI 1.10
633 20:10:38.463123 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
634 20:10:38.463772 bl2_stage_init 0x01
635 20:10:38.464290 bl2_stage_init 0x81
636 20:10:38.464772 hw id: 0x0000 - pwm id 0x01
637 20:10:38.465254 bl2_stage_init 0xc1
638 20:10:38.465735 bl2_stage_init 0x02
639 20:10:38.466208
640 20:10:38.466687 L0:00000000
641 20:10:38.467166 L1:20000703
642 20:10:38.467632 L2:00008067
643 20:10:38.468152 L3:14000000
644 20:10:38.468628 B2:00402000
645 20:10:38.469076 B1:e0f83180
646 20:10:38.469538
647 20:10:38.470009 TE: 58124
648 20:10:38.470471
649 20:10:38.470940 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
650 20:10:38.471403
651 20:10:38.471846 Board ID = 1
652 20:10:38.472357 Set A53 clk to 24M
653 20:10:38.472867 Set A73 clk to 24M
654 20:10:38.473364 Set clk81 to 24M
655 20:10:38.473852 A53 clk: 1200 MHz
656 20:10:38.474315 A73 clk: 1200 MHz
657 20:10:38.474754 CLK81: 166.6M
658 20:10:38.475214 smccc: 00012a92
659 20:10:38.475872 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
660 20:10:38.476421 board id: 1
661 20:10:38.476897 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
662 20:10:38.477329 fw parse done
663 20:10:38.478165 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
664 20:10:38.494702 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
665 20:10:38.506470 PIEI prepare done
666 20:10:38.507022 fastboot data load
667 20:10:38.507480 fastboot data verify
668 20:10:38.512094 verify result: 266
669 20:10:38.517734 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
670 20:10:38.518245 LPDDR4 probe
671 20:10:38.518691 ddr clk to 1584MHz
672 20:10:38.525744 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
673 20:10:38.563119
674 20:10:38.563725 dmc_version 0001
675 20:10:38.569490 Check phy result
676 20:10:38.575551 INFO : End of CA training
677 20:10:38.576133 INFO : End of initialization
678 20:10:38.581353 INFO : Training has run successfully!
679 20:10:38.581942 Check phy result
680 20:10:38.586738 INFO : End of initialization
681 20:10:38.587279 INFO : End of read enable training
682 20:10:38.590170 INFO : End of fine write leveling
683 20:10:38.595799 INFO : End of Write leveling coarse delay
684 20:10:38.601338 INFO : Training has run successfully!
685 20:10:38.601854 Check phy result
686 20:10:38.602309 INFO : End of initialization
687 20:10:38.606997 INFO : End of read dq deskew training
688 20:10:38.612669 INFO : End of MPR read delay center optimization
689 20:10:38.613234 INFO : End of write delay center optimization
690 20:10:38.618238 INFO : End of read delay center optimization
691 20:10:38.623807 INFO : End of max read latency training
692 20:10:38.624385 INFO : Training has run successfully!
693 20:10:38.629357 1D training succeed
694 20:10:38.634669 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 20:10:38.681761 Check phy result
696 20:10:38.682335 INFO : End of initialization
697 20:10:38.705320 INFO : End of 2D read delay Voltage center optimization
698 20:10:38.724742 INFO : End of 2D read delay Voltage center optimization
699 20:10:38.776109 INFO : End of 2D write delay Voltage center optimization
700 20:10:38.826074 INFO : End of 2D write delay Voltage center optimization
701 20:10:38.831653 INFO : Training has run successfully!
702 20:10:38.832211
703 20:10:38.832677 channel==0
704 20:10:38.837273 RxClkDly_Margin_A0==88 ps 9
705 20:10:38.837784 TxDqDly_Margin_A0==98 ps 10
706 20:10:38.842864 RxClkDly_Margin_A1==88 ps 9
707 20:10:38.843371 TxDqDly_Margin_A1==98 ps 10
708 20:10:38.843828 TrainedVREFDQ_A0==74
709 20:10:38.848472 TrainedVREFDQ_A1==74
710 20:10:38.848988 VrefDac_Margin_A0==25
711 20:10:38.849443 DeviceVref_Margin_A0==40
712 20:10:38.854054 VrefDac_Margin_A1==24
713 20:10:38.854562 DeviceVref_Margin_A1==40
714 20:10:38.855011
715 20:10:38.855454
716 20:10:38.859659 channel==1
717 20:10:38.860201 RxClkDly_Margin_A0==98 ps 10
718 20:10:38.860654 TxDqDly_Margin_A0==98 ps 10
719 20:10:38.865256 RxClkDly_Margin_A1==88 ps 9
720 20:10:38.865763 TxDqDly_Margin_A1==88 ps 9
721 20:10:38.870859 TrainedVREFDQ_A0==77
722 20:10:38.871368 TrainedVREFDQ_A1==77
723 20:10:38.871819 VrefDac_Margin_A0==23
724 20:10:38.876424 DeviceVref_Margin_A0==37
725 20:10:38.876926 VrefDac_Margin_A1==24
726 20:10:38.882043 DeviceVref_Margin_A1==37
727 20:10:38.882552
728 20:10:38.883008 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
729 20:10:38.883452
730 20:10:38.915550 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
731 20:10:38.916178 2D training succeed
732 20:10:38.921187 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
733 20:10:38.926807 auto size-- 65535DDR cs0 size: 2048MB
734 20:10:38.927322 DDR cs1 size: 2048MB
735 20:10:38.932393 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
736 20:10:38.932912 cs0 DataBus test pass
737 20:10:38.937994 cs1 DataBus test pass
738 20:10:38.938505 cs0 AddrBus test pass
739 20:10:38.938951 cs1 AddrBus test pass
740 20:10:38.939389
741 20:10:38.943608 100bdlr_step_size ps== 420
742 20:10:38.944180 result report
743 20:10:38.949204 boot times 0Enable ddr reg access
744 20:10:38.954592 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
745 20:10:38.968029 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
746 20:10:39.541433 0.0;M3 CHK:0;cm4_sp_mode 0
747 20:10:39.541838 MVN_1=0x00000000
748 20:10:39.547096 MVN_2=0x00000000
749 20:10:39.552860 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
750 20:10:39.553171 OPS=0x10
751 20:10:39.553400 ring efuse init
752 20:10:39.553624 chipver efuse init
753 20:10:39.558367 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
754 20:10:39.563977 [0.018961 Inits done]
755 20:10:39.564316 secure task start!
756 20:10:39.564548 high task start!
757 20:10:39.568584 low task start!
758 20:10:39.568869 run into bl31
759 20:10:39.575186 NOTICE: BL31: v1.3(release):4fc40b1
760 20:10:39.583024 NOTICE: BL31: Built : 15:58:17, May 22 2019
761 20:10:39.583319 NOTICE: BL31: G12A normal boot!
762 20:10:39.608391 NOTICE: BL31: BL33 decompress pass
763 20:10:39.614078 ERROR: Error initializing runtime service opteed_fast
764 20:10:40.847092
765 20:10:40.847779
766 20:10:40.855508 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
767 20:10:40.856106
768 20:10:40.856576 Model: Libre Computer AML-A311D-CC Alta
769 20:10:41.064115 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
770 20:10:41.087394 DRAM: 2 GiB (effective 3.8 GiB)
771 20:10:41.230321 Core: 408 devices, 31 uclasses, devicetree: separate
772 20:10:41.236261 WDT: Not starting watchdog@f0d0
773 20:10:41.268653 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
774 20:10:41.280957 Loading Environment from FAT... Card did not respond to voltage select! : -110
775 20:10:41.285916 ** Bad device specification mmc 0 **
776 20:10:41.296407 Card did not respond to voltage select! : -110
777 20:10:41.303968 ** Bad device specification mmc 0 **
778 20:10:41.304541 Couldn't find partition mmc 0
779 20:10:41.312366 Card did not respond to voltage select! : -110
780 20:10:41.317654 ** Bad device specification mmc 0 **
781 20:10:41.318117 Couldn't find partition mmc 0
782 20:10:41.322732 Error: could not access storage.
783 20:10:41.665256 Net: eth0: ethernet@ff3f0000
784 20:10:41.665853 starting USB...
785 20:10:41.917133 Bus usb@ff500000: Register 3000140 NbrPorts 3
786 20:10:41.917706 Starting the controller
787 20:10:41.924105 USB XHCI 1.10
788 20:10:44.085962 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
789 20:10:44.086598 bl2_stage_init 0x01
790 20:10:44.087070 bl2_stage_init 0x81
791 20:10:44.091588 hw id: 0x0000 - pwm id 0x01
792 20:10:44.092145 bl2_stage_init 0xc1
793 20:10:44.092616 bl2_stage_init 0x02
794 20:10:44.093066
795 20:10:44.097240 L0:00000000
796 20:10:44.097758 L1:20000703
797 20:10:44.098215 L2:00008067
798 20:10:44.098663 L3:14000000
799 20:10:44.102785 B2:00402000
800 20:10:44.103297 B1:e0f83180
801 20:10:44.103747
802 20:10:44.104250 TE: 58124
803 20:10:44.104705
804 20:10:44.108523 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
805 20:10:44.109042
806 20:10:44.109498 Board ID = 1
807 20:10:44.113966 Set A53 clk to 24M
808 20:10:44.114477 Set A73 clk to 24M
809 20:10:44.114933 Set clk81 to 24M
810 20:10:44.119478 A53 clk: 1200 MHz
811 20:10:44.120019 A73 clk: 1200 MHz
812 20:10:44.120492 CLK81: 166.6M
813 20:10:44.120941 smccc: 00012a92
814 20:10:44.125079 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
815 20:10:44.130790 board id: 1
816 20:10:44.136648 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
817 20:10:44.147320 fw parse done
818 20:10:44.153290 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
819 20:10:44.195635 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
820 20:10:44.206773 PIEI prepare done
821 20:10:44.207316 fastboot data load
822 20:10:44.207790 fastboot data verify
823 20:10:44.212379 verify result: 266
824 20:10:44.218032 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
825 20:10:44.218562 LPDDR4 probe
826 20:10:44.219067 ddr clk to 1584MHz
827 20:10:44.226098 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
828 20:10:44.263240
829 20:10:44.263782 dmc_version 0001
830 20:10:44.269932 Check phy result
831 20:10:44.275815 INFO : End of CA training
832 20:10:44.276369 INFO : End of initialization
833 20:10:44.281439 INFO : Training has run successfully!
834 20:10:44.281957 Check phy result
835 20:10:44.287034 INFO : End of initialization
836 20:10:44.287546 INFO : End of read enable training
837 20:10:44.290277 INFO : End of fine write leveling
838 20:10:44.295788 INFO : End of Write leveling coarse delay
839 20:10:44.301382 INFO : Training has run successfully!
840 20:10:44.301895 Check phy result
841 20:10:44.302349 INFO : End of initialization
842 20:10:44.307038 INFO : End of read dq deskew training
843 20:10:44.312660 INFO : End of MPR read delay center optimization
844 20:10:44.313172 INFO : End of write delay center optimization
845 20:10:44.318217 INFO : End of read delay center optimization
846 20:10:44.323768 INFO : End of max read latency training
847 20:10:44.324306 INFO : Training has run successfully!
848 20:10:44.329437 1D training succeed
849 20:10:44.335523 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 20:10:44.382930 Check phy result
851 20:10:44.383446 INFO : End of initialization
852 20:10:44.404644 INFO : End of 2D read delay Voltage center optimization
853 20:10:44.424079 INFO : End of 2D read delay Voltage center optimization
854 20:10:44.476987 INFO : End of 2D write delay Voltage center optimization
855 20:10:44.526351 INFO : End of 2D write delay Voltage center optimization
856 20:10:44.531819 INFO : Training has run successfully!
857 20:10:44.532318
858 20:10:44.532723 channel==0
859 20:10:44.537453 RxClkDly_Margin_A0==88 ps 9
860 20:10:44.537914 TxDqDly_Margin_A0==98 ps 10
861 20:10:44.540817 RxClkDly_Margin_A1==88 ps 9
862 20:10:44.541266 TxDqDly_Margin_A1==98 ps 10
863 20:10:44.546424 TrainedVREFDQ_A0==74
864 20:10:44.546922 TrainedVREFDQ_A1==74
865 20:10:44.547325 VrefDac_Margin_A0==25
866 20:10:44.552085 DeviceVref_Margin_A0==40
867 20:10:44.552535 VrefDac_Margin_A1==25
868 20:10:44.557644 DeviceVref_Margin_A1==40
869 20:10:44.558185
870 20:10:44.558627
871 20:10:44.559026 channel==1
872 20:10:44.559447 RxClkDly_Margin_A0==98 ps 10
873 20:10:44.561043 TxDqDly_Margin_A0==98 ps 10
874 20:10:44.566663 RxClkDly_Margin_A1==98 ps 10
875 20:10:44.567163 TxDqDly_Margin_A1==88 ps 9
876 20:10:44.567598 TrainedVREFDQ_A0==77
877 20:10:44.572220 TrainedVREFDQ_A1==77
878 20:10:44.572708 VrefDac_Margin_A0==22
879 20:10:44.577760 DeviceVref_Margin_A0==37
880 20:10:44.578244 VrefDac_Margin_A1==22
881 20:10:44.578659 DeviceVref_Margin_A1==37
882 20:10:44.579079
883 20:10:44.583506 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
884 20:10:44.584061
885 20:10:44.617173 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000016 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
886 20:10:44.617745 2D training succeed
887 20:10:44.622656 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
888 20:10:44.628351 auto size-- 65535DDR cs0 size: 2048MB
889 20:10:44.628890 DDR cs1 size: 2048MB
890 20:10:44.633793 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
891 20:10:44.634281 cs0 DataBus test pass
892 20:10:44.634707 cs1 DataBus test pass
893 20:10:44.639380 cs0 AddrBus test pass
894 20:10:44.639870 cs1 AddrBus test pass
895 20:10:44.640360
896 20:10:44.645062 100bdlr_step_size ps== 420
897 20:10:44.645512 result report
898 20:10:44.645905 boot times 0Enable ddr reg access
899 20:10:44.654820 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
900 20:10:44.668157 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
901 20:10:45.242069 0.0;M3 CHK:0;cm4_sp_mode 0
902 20:10:45.242677 MVN_1=0x00000000
903 20:10:45.247389 MVN_2=0x00000000
904 20:10:45.253261 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
905 20:10:45.253742 OPS=0x10
906 20:10:45.254167 ring efuse init
907 20:10:45.254571 chipver efuse init
908 20:10:45.261562 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
909 20:10:45.262093 [0.018960 Inits done]
910 20:10:45.262518 secure task start!
911 20:10:45.269120 high task start!
912 20:10:45.269583 low task start!
913 20:10:45.269999 run into bl31
914 20:10:45.275687 NOTICE: BL31: v1.3(release):4fc40b1
915 20:10:45.283508 NOTICE: BL31: Built : 15:58:17, May 22 2019
916 20:10:45.284078 NOTICE: BL31: G12A normal boot!
917 20:10:45.308918 NOTICE: BL31: BL33 decompress pass
918 20:10:45.314473 ERROR: Error initializing runtime service opteed_fast
919 20:10:46.547458
920 20:10:46.548097
921 20:10:46.556398 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
922 20:10:46.556926
923 20:10:46.557385 Model: Libre Computer AML-A311D-CC Alta
924 20:10:46.764269 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
925 20:10:46.787663 DRAM: 2 GiB (effective 3.8 GiB)
926 20:10:46.930615 Core: 408 devices, 31 uclasses, devicetree: separate
927 20:10:46.936450 WDT: Not starting watchdog@f0d0
928 20:10:46.968738 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
929 20:10:46.981187 Loading Environment from FAT... Card did not respond to voltage select! : -110
930 20:10:46.986102 ** Bad device specification mmc 0 **
931 20:10:46.996452 Card did not respond to voltage select! : -110
932 20:10:47.004149 ** Bad device specification mmc 0 **
933 20:10:47.004594 Couldn't find partition mmc 0
934 20:10:47.012477 Card did not respond to voltage select! : -110
935 20:10:47.017986 ** Bad device specification mmc 0 **
936 20:10:47.018428 Couldn't find partition mmc 0
937 20:10:47.023012 Error: could not access storage.
938 20:10:47.366520 Net: eth0: ethernet@ff3f0000
939 20:10:47.366989 starting USB...
940 20:10:47.618414 Bus usb@ff500000: Register 3000140 NbrPorts 3
941 20:10:47.618888 Starting the controller
942 20:10:47.625399 USB XHCI 1.10
943 20:10:49.485930 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
944 20:10:49.486595 bl2_stage_init 0x81
945 20:10:49.491569 hw id: 0x0000 - pwm id 0x01
946 20:10:49.492076 bl2_stage_init 0xc1
947 20:10:49.492502 bl2_stage_init 0x02
948 20:10:49.492906
949 20:10:49.497044 L0:00000000
950 20:10:49.497490 L1:20000703
951 20:10:49.497900 L2:00008067
952 20:10:49.498304 L3:14000000
953 20:10:49.498699 B2:00402000
954 20:10:49.502632 B1:e0f83180
955 20:10:49.503075
956 20:10:49.503480 TE: 58150
957 20:10:49.503883
958 20:10:49.508234 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
959 20:10:49.508684
960 20:10:49.509093 Board ID = 1
961 20:10:49.513859 Set A53 clk to 24M
962 20:10:49.514299 Set A73 clk to 24M
963 20:10:49.514704 Set clk81 to 24M
964 20:10:49.519562 A53 clk: 1200 MHz
965 20:10:49.520035 A73 clk: 1200 MHz
966 20:10:49.520440 CLK81: 166.6M
967 20:10:49.520832 smccc: 00012aab
968 20:10:49.525050 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
969 20:10:49.530638 board id: 1
970 20:10:49.536431 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
971 20:10:49.547082 fw parse done
972 20:10:49.553068 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
973 20:10:49.595758 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
974 20:10:49.606619 PIEI prepare done
975 20:10:49.607154 fastboot data load
976 20:10:49.607551 fastboot data verify
977 20:10:49.612273 verify result: 266
978 20:10:49.617784 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
979 20:10:49.618271 LPDDR4 probe
980 20:10:49.618675 ddr clk to 1584MHz
981 20:10:49.625803 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
982 20:10:49.663079
983 20:10:49.663636 dmc_version 0001
984 20:10:49.669771 Check phy result
985 20:10:49.675743 INFO : End of CA training
986 20:10:49.676303 INFO : End of initialization
987 20:10:49.681331 INFO : Training has run successfully!
988 20:10:49.681813 Check phy result
989 20:10:49.686954 INFO : End of initialization
990 20:10:49.687444 INFO : End of read enable training
991 20:10:49.692468 INFO : End of fine write leveling
992 20:10:49.698216 INFO : End of Write leveling coarse delay
993 20:10:49.698661 INFO : Training has run successfully!
994 20:10:49.699056 Check phy result
995 20:10:49.703730 INFO : End of initialization
996 20:10:49.704217 INFO : End of read dq deskew training
997 20:10:49.709246 INFO : End of MPR read delay center optimization
998 20:10:49.715027 INFO : End of write delay center optimization
999 20:10:49.720553 INFO : End of read delay center optimization
1000 20:10:49.721010 INFO : End of max read latency training
1001 20:10:49.726214 INFO : Training has run successfully!
1002 20:10:49.726658 1D training succeed
1003 20:10:49.735294 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1004 20:10:49.782866 Check phy result
1005 20:10:49.783395 INFO : End of initialization
1006 20:10:49.805139 INFO : End of 2D read delay Voltage center optimization
1007 20:10:49.825244 INFO : End of 2D read delay Voltage center optimization
1008 20:10:49.877238 INFO : End of 2D write delay Voltage center optimization
1009 20:10:49.926426 INFO : End of 2D write delay Voltage center optimization
1010 20:10:49.932025 INFO : Training has run successfully!
1011 20:10:49.932525
1012 20:10:49.932924 channel==0
1013 20:10:49.937594 RxClkDly_Margin_A0==88 ps 9
1014 20:10:49.938034 TxDqDly_Margin_A0==98 ps 10
1015 20:10:49.943173 RxClkDly_Margin_A1==88 ps 9
1016 20:10:49.943507 TxDqDly_Margin_A1==98 ps 10
1017 20:10:49.943747 TrainedVREFDQ_A0==74
1018 20:10:49.948765 TrainedVREFDQ_A1==74
1019 20:10:49.949051 VrefDac_Margin_A0==24
1020 20:10:49.949286 DeviceVref_Margin_A0==40
1021 20:10:49.954303 VrefDac_Margin_A1==24
1022 20:10:49.954589 DeviceVref_Margin_A1==40
1023 20:10:49.954824
1024 20:10:49.955050
1025 20:10:49.959916 channel==1
1026 20:10:49.960224 RxClkDly_Margin_A0==98 ps 10
1027 20:10:49.960460 TxDqDly_Margin_A0==98 ps 10
1028 20:10:49.965538 RxClkDly_Margin_A1==98 ps 10
1029 20:10:49.965827 TxDqDly_Margin_A1==88 ps 9
1030 20:10:49.971095 TrainedVREFDQ_A0==77
1031 20:10:49.971395 TrainedVREFDQ_A1==77
1032 20:10:49.971633 VrefDac_Margin_A0==22
1033 20:10:49.976732 DeviceVref_Margin_A0==37
1034 20:10:49.977033 VrefDac_Margin_A1==22
1035 20:10:49.982337 DeviceVref_Margin_A1==37
1036 20:10:49.982642
1037 20:10:49.982881 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1038 20:10:49.987890
1039 20:10:50.015937 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
1040 20:10:50.016368 2D training succeed
1041 20:10:50.021549 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1042 20:10:50.027114 auto size-- 65535DDR cs0 size: 2048MB
1043 20:10:50.027422 DDR cs1 size: 2048MB
1044 20:10:50.032705 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1045 20:10:50.033011 cs0 DataBus test pass
1046 20:10:50.038302 cs1 DataBus test pass
1047 20:10:50.038616 cs0 AddrBus test pass
1048 20:10:50.038858 cs1 AddrBus test pass
1049 20:10:50.039086
1050 20:10:50.043938 100bdlr_step_size ps== 420
1051 20:10:50.044293 result report
1052 20:10:50.049625 boot times 0Enable ddr reg access
1053 20:10:50.054340 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1054 20:10:50.068450 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1055 20:10:50.640746 0.0;M3 CHK:0;cm4_sp_mode 0
1056 20:10:50.641396 MVN_1=0x00000000
1057 20:10:50.646125 MVN_2=0x00000000
1058 20:10:50.651817 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1059 20:10:50.652543 OPS=0x10
1060 20:10:50.653091 ring efuse init
1061 20:10:50.653609 chipver efuse init
1062 20:10:50.657395 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1063 20:10:50.663059 [0.018960 Inits done]
1064 20:10:50.663766 secure task start!
1065 20:10:50.664347 high task start!
1066 20:10:50.667555 low task start!
1067 20:10:50.668320 run into bl31
1068 20:10:50.674213 NOTICE: BL31: v1.3(release):4fc40b1
1069 20:10:50.682079 NOTICE: BL31: Built : 15:58:17, May 22 2019
1070 20:10:50.682887 NOTICE: BL31: G12A normal boot!
1071 20:10:50.707479 NOTICE: BL31: BL33 decompress pass
1072 20:10:50.713006 ERROR: Error initializing runtime service opteed_fast
1073 20:10:51.946170
1074 20:10:51.946811
1075 20:10:51.954359 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1076 20:10:51.954865
1077 20:10:51.955270 Model: Libre Computer AML-A311D-CC Alta
1078 20:10:52.162945 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1079 20:10:52.186186 DRAM: 2 GiB (effective 3.8 GiB)
1080 20:10:52.329268 Core: 408 devices, 31 uclasses, devicetree: separate
1081 20:10:52.335045 WDT: Not starting watchdog@f0d0
1082 20:10:52.367252 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1083 20:10:52.379734 Loading Environment from FAT... Card did not respond to voltage select! : -110
1084 20:10:52.384782 ** Bad device specification mmc 0 **
1085 20:10:52.395050 Card did not respond to voltage select! : -110
1086 20:10:52.402695 ** Bad device specification mmc 0 **
1087 20:10:52.403138 Couldn't find partition mmc 0
1088 20:10:52.411039 Card did not respond to voltage select! : -110
1089 20:10:52.416609 ** Bad device specification mmc 0 **
1090 20:10:52.417112 Couldn't find partition mmc 0
1091 20:10:52.421595 Error: could not access storage.
1092 20:10:52.764170 Net: eth0: ethernet@ff3f0000
1093 20:10:52.764776 starting USB...
1094 20:10:53.015897 Bus usb@ff500000: Register 3000140 NbrPorts 3
1095 20:10:53.016498 Starting the controller
1096 20:10:53.022869 USB XHCI 1.10
1097 20:10:54.576912 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1098 20:10:54.585151 scanning usb for storage devices... 0 Storage Device(s) found
1100 20:10:54.636711 Hit any key to stop autoboot: 1
1101 20:10:54.637498 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1102 20:10:54.638051 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1103 20:10:54.638505 Setting prompt string to ['=>']
1104 20:10:54.638968 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1105 20:10:54.652621 0
1106 20:10:54.653489 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1107 20:10:54.653988 Sending with 10 millisecond of delay
1109 20:10:55.788722 => setenv autoload no
1110 20:10:55.799504 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1111 20:10:55.804607 setenv autoload no
1112 20:10:55.805543 Sending with 10 millisecond of delay
1114 20:10:57.604569 => setenv initrd_high 0xffffffff
1115 20:10:57.615330 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1116 20:10:57.616425 setenv initrd_high 0xffffffff
1117 20:10:57.617231 Sending with 10 millisecond of delay
1119 20:10:59.234495 => setenv fdt_high 0xffffffff
1120 20:10:59.245323 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1121 20:10:59.246108 setenv fdt_high 0xffffffff
1122 20:10:59.246798 Sending with 10 millisecond of delay
1124 20:10:59.538677 => dhcp
1125 20:10:59.549486 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1126 20:10:59.550464 dhcp
1127 20:10:59.550954 Speed: 1000, full duplex
1128 20:10:59.551408 BOOTP broadcast 1
1129 20:10:59.744682 DHCP client bound to address 192.168.6.27 (195 ms)
1130 20:10:59.745657 Sending with 10 millisecond of delay
1132 20:11:01.424022 => setenv serverip 192.168.6.2
1133 20:11:01.434797 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1134 20:11:01.435739 setenv serverip 192.168.6.2
1135 20:11:01.436598 Sending with 10 millisecond of delay
1137 20:11:05.161905 => tftpboot 0x01080000 936573/tftp-deploy-mv3tvvjf/kernel/uImage
1138 20:11:05.172923 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1139 20:11:05.174072 tftpboot 0x01080000 936573/tftp-deploy-mv3tvvjf/kernel/uImage
1140 20:11:05.174687 Speed: 1000, full duplex
1141 20:11:05.175256 Using ethernet@ff3f0000 device
1142 20:11:05.176154 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1143 20:11:05.181158 Filename '936573/tftp-deploy-mv3tvvjf/kernel/uImage'.
1144 20:11:05.185050 Load address: 0x1080000
1145 20:11:08.059879 Loading: *################################################## 43.6 MiB
1146 20:11:08.060539 15.2 MiB/s
1147 20:11:08.060951 done
1148 20:11:08.064447 Bytes transferred = 45713984 (2b98a40 hex)
1149 20:11:08.065190 Sending with 10 millisecond of delay
1151 20:11:12.752459 => tftpboot 0x08000000 936573/tftp-deploy-mv3tvvjf/ramdisk/ramdisk.cpio.gz.uboot
1152 20:11:12.763287 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1153 20:11:12.764230 tftpboot 0x08000000 936573/tftp-deploy-mv3tvvjf/ramdisk/ramdisk.cpio.gz.uboot
1154 20:11:12.764683 Speed: 1000, full duplex
1155 20:11:12.765083 Using ethernet@ff3f0000 device
1156 20:11:12.766185 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1157 20:11:12.778082 Filename '936573/tftp-deploy-mv3tvvjf/ramdisk/ramdisk.cpio.gz.uboot'.
1158 20:11:12.778610 Load address: 0x8000000
1159 20:11:19.464507 Loading: *#######################T ########################## UDP wrong checksum 00000005 0000ea89
1160 20:11:20.543104 UDP wrong checksum 000000ff 000019d2
1161 20:11:20.557669 UDP wrong checksum 000000ff 0000a2c4
1162 20:11:24.466582 T UDP wrong checksum 00000005 0000ea89
1163 20:11:34.469055 T T UDP wrong checksum 00000005 0000ea89
1164 20:11:54.474058 T T T T UDP wrong checksum 00000005 0000ea89
1165 20:11:54.701795 UDP wrong checksum 000000ff 00006859
1166 20:11:54.741812 UDP wrong checksum 000000ff 0000ed4b
1167 20:12:02.643506 T UDP wrong checksum 000000ff 000091b7
1168 20:12:02.692244 UDP wrong checksum 000000ff 00002aaa
1169 20:12:09.477208 T
1170 20:12:09.477881 Retry count exceeded; starting again
1172 20:12:09.479440 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1175 20:12:09.481478 end: 2.4 uboot-commands (duration 00:01:52) [common]
1177 20:12:09.482994 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1179 20:12:09.484172 end: 2 uboot-action (duration 00:01:52) [common]
1181 20:12:09.485905 Cleaning after the job
1182 20:12:09.486559 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936573/tftp-deploy-mv3tvvjf/ramdisk
1183 20:12:09.487822 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936573/tftp-deploy-mv3tvvjf/kernel
1184 20:12:09.517807 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936573/tftp-deploy-mv3tvvjf/dtb
1185 20:12:09.519301 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936573/tftp-deploy-mv3tvvjf/nfsrootfs
1186 20:12:09.631571 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936573/tftp-deploy-mv3tvvjf/modules
1187 20:12:09.656142 start: 4.1 power-off (timeout 00:00:30) [common]
1188 20:12:09.656810 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1189 20:12:09.690244 >> OK - accepted request
1190 20:12:09.692466 Returned 0 in 0 seconds
1191 20:12:09.793458 end: 4.1 power-off (duration 00:00:00) [common]
1193 20:12:09.794382 start: 4.2 read-feedback (timeout 00:10:00) [common]
1194 20:12:09.795035 Listened to connection for namespace 'common' for up to 1s
1195 20:12:10.795967 Finalising connection for namespace 'common'
1196 20:12:10.796532 Disconnecting from shell: Finalise
1197 20:12:10.796816 =>
1198 20:12:10.897480 end: 4.2 read-feedback (duration 00:00:01) [common]
1199 20:12:10.897936 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/936573
1200 20:12:12.659731 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/936573
1201 20:12:12.660440 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.