Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 22:04:01.084514 lava-dispatcher, installed at version: 2024.01
2 22:04:01.085311 start: 0 validate
3 22:04:01.085776 Start time: 2024-11-04 22:04:01.085747+00:00 (UTC)
4 22:04:01.086334 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 22:04:01.086876 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 22:04:01.123965 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 22:04:01.124553 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-95-g6db936d4ac0f%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 22:04:01.157424 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 22:04:01.158086 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-95-g6db936d4ac0f%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 22:04:01.188617 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 22:04:01.189136 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-95-g6db936d4ac0f%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 22:04:01.226073 validate duration: 0.14
14 22:04:01.226919 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:04:01.227261 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:04:01.227558 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:04:01.228147 Not decompressing ramdisk as can be used compressed.
18 22:04:01.228585 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 22:04:01.228818 saving as /var/lib/lava/dispatcher/tmp/936558/tftp-deploy-hmoh1lzh/ramdisk/rootfs.cpio.gz
20 22:04:01.229063 total size: 47897469 (45 MB)
21 22:04:01.261608 progress 0 % (0 MB)
22 22:04:01.293674 progress 5 % (2 MB)
23 22:04:01.325306 progress 10 % (4 MB)
24 22:04:01.357592 progress 15 % (6 MB)
25 22:04:01.388969 progress 20 % (9 MB)
26 22:04:01.419632 progress 25 % (11 MB)
27 22:04:01.450133 progress 30 % (13 MB)
28 22:04:01.480991 progress 35 % (16 MB)
29 22:04:01.511541 progress 40 % (18 MB)
30 22:04:01.542138 progress 45 % (20 MB)
31 22:04:01.572889 progress 50 % (22 MB)
32 22:04:01.603531 progress 55 % (25 MB)
33 22:04:01.634477 progress 60 % (27 MB)
34 22:04:01.664988 progress 65 % (29 MB)
35 22:04:01.695923 progress 70 % (32 MB)
36 22:04:01.726600 progress 75 % (34 MB)
37 22:04:01.757057 progress 80 % (36 MB)
38 22:04:01.787655 progress 85 % (38 MB)
39 22:04:01.818139 progress 90 % (41 MB)
40 22:04:01.848691 progress 95 % (43 MB)
41 22:04:01.878572 progress 100 % (45 MB)
42 22:04:01.879343 45 MB downloaded in 0.65 s (70.25 MB/s)
43 22:04:01.879889 end: 1.1.1 http-download (duration 00:00:01) [common]
45 22:04:01.880811 end: 1.1 download-retry (duration 00:00:01) [common]
46 22:04:01.881097 start: 1.2 download-retry (timeout 00:09:59) [common]
47 22:04:01.881367 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 22:04:01.881848 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-95-g6db936d4ac0f/arm64/defconfig/gcc-12/kernel/Image
49 22:04:01.882089 saving as /var/lib/lava/dispatcher/tmp/936558/tftp-deploy-hmoh1lzh/kernel/Image
50 22:04:01.882296 total size: 45713920 (43 MB)
51 22:04:01.882507 No compression specified
52 22:04:01.919415 progress 0 % (0 MB)
53 22:04:01.948432 progress 5 % (2 MB)
54 22:04:01.977461 progress 10 % (4 MB)
55 22:04:02.006219 progress 15 % (6 MB)
56 22:04:02.035639 progress 20 % (8 MB)
57 22:04:02.064341 progress 25 % (10 MB)
58 22:04:02.093529 progress 30 % (13 MB)
59 22:04:02.122982 progress 35 % (15 MB)
60 22:04:02.151827 progress 40 % (17 MB)
61 22:04:02.181020 progress 45 % (19 MB)
62 22:04:02.210214 progress 50 % (21 MB)
63 22:04:02.239458 progress 55 % (24 MB)
64 22:04:02.268835 progress 60 % (26 MB)
65 22:04:02.297525 progress 65 % (28 MB)
66 22:04:02.326823 progress 70 % (30 MB)
67 22:04:02.355922 progress 75 % (32 MB)
68 22:04:02.385390 progress 80 % (34 MB)
69 22:04:02.414186 progress 85 % (37 MB)
70 22:04:02.443018 progress 90 % (39 MB)
71 22:04:02.472361 progress 95 % (41 MB)
72 22:04:02.501051 progress 100 % (43 MB)
73 22:04:02.501601 43 MB downloaded in 0.62 s (70.40 MB/s)
74 22:04:02.502084 end: 1.2.1 http-download (duration 00:00:01) [common]
76 22:04:02.502901 end: 1.2 download-retry (duration 00:00:01) [common]
77 22:04:02.503173 start: 1.3 download-retry (timeout 00:09:59) [common]
78 22:04:02.503434 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 22:04:02.503908 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-95-g6db936d4ac0f/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 22:04:02.504220 saving as /var/lib/lava/dispatcher/tmp/936558/tftp-deploy-hmoh1lzh/dtb/meson-g12b-a311d-libretech-cc.dtb
81 22:04:02.504434 total size: 54703 (0 MB)
82 22:04:02.504647 No compression specified
83 22:04:02.537615 progress 59 % (0 MB)
84 22:04:02.538464 progress 100 % (0 MB)
85 22:04:02.539018 0 MB downloaded in 0.03 s (1.51 MB/s)
86 22:04:02.539535 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:04:02.540467 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:04:02.540757 start: 1.4 download-retry (timeout 00:09:59) [common]
90 22:04:02.541037 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 22:04:02.541531 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-95-g6db936d4ac0f/arm64/defconfig/gcc-12/modules.tar.xz
92 22:04:02.541789 saving as /var/lib/lava/dispatcher/tmp/936558/tftp-deploy-hmoh1lzh/modules/modules.tar
93 22:04:02.542004 total size: 11612416 (11 MB)
94 22:04:02.542222 Using unxz to decompress xz
95 22:04:02.576560 progress 0 % (0 MB)
96 22:04:02.644145 progress 5 % (0 MB)
97 22:04:02.720483 progress 10 % (1 MB)
98 22:04:02.819898 progress 15 % (1 MB)
99 22:04:02.912754 progress 20 % (2 MB)
100 22:04:02.992549 progress 25 % (2 MB)
101 22:04:03.068783 progress 30 % (3 MB)
102 22:04:03.150175 progress 35 % (3 MB)
103 22:04:03.224315 progress 40 % (4 MB)
104 22:04:03.302429 progress 45 % (5 MB)
105 22:04:03.388915 progress 50 % (5 MB)
106 22:04:03.468534 progress 55 % (6 MB)
107 22:04:03.554581 progress 60 % (6 MB)
108 22:04:03.636414 progress 65 % (7 MB)
109 22:04:03.718451 progress 70 % (7 MB)
110 22:04:03.796996 progress 75 % (8 MB)
111 22:04:03.881747 progress 80 % (8 MB)
112 22:04:03.964144 progress 85 % (9 MB)
113 22:04:04.045358 progress 90 % (9 MB)
114 22:04:04.124374 progress 95 % (10 MB)
115 22:04:04.202335 progress 100 % (11 MB)
116 22:04:04.214867 11 MB downloaded in 1.67 s (6.62 MB/s)
117 22:04:04.215472 end: 1.4.1 http-download (duration 00:00:02) [common]
119 22:04:04.216778 end: 1.4 download-retry (duration 00:00:02) [common]
120 22:04:04.217378 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 22:04:04.217948 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 22:04:04.218487 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:04:04.219037 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 22:04:04.220135 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh
125 22:04:04.221068 makedir: /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin
126 22:04:04.221749 makedir: /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/tests
127 22:04:04.222416 makedir: /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/results
128 22:04:04.223088 Creating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin/lava-add-keys
129 22:04:04.224134 Creating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin/lava-add-sources
130 22:04:04.225142 Creating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin/lava-background-process-start
131 22:04:04.226160 Creating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin/lava-background-process-stop
132 22:04:04.227231 Creating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin/lava-common-functions
133 22:04:04.228255 Creating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin/lava-echo-ipv4
134 22:04:04.229237 Creating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin/lava-install-packages
135 22:04:04.230211 Creating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin/lava-installed-packages
136 22:04:04.231166 Creating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin/lava-os-build
137 22:04:04.232162 Creating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin/lava-probe-channel
138 22:04:04.233191 Creating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin/lava-probe-ip
139 22:04:04.234176 Creating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin/lava-target-ip
140 22:04:04.235137 Creating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin/lava-target-mac
141 22:04:04.236158 Creating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin/lava-target-storage
142 22:04:04.237178 Creating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin/lava-test-case
143 22:04:04.238273 Creating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin/lava-test-event
144 22:04:04.239245 Creating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin/lava-test-feedback
145 22:04:04.240262 Creating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin/lava-test-raise
146 22:04:04.241272 Creating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin/lava-test-reference
147 22:04:04.242238 Creating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin/lava-test-runner
148 22:04:04.243224 Creating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin/lava-test-set
149 22:04:04.244219 Creating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin/lava-test-shell
150 22:04:04.245204 Updating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin/lava-install-packages (oe)
151 22:04:04.246240 Updating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/bin/lava-installed-packages (oe)
152 22:04:04.247133 Creating /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/environment
153 22:04:04.247896 LAVA metadata
154 22:04:04.248463 - LAVA_JOB_ID=936558
155 22:04:04.248935 - LAVA_DISPATCHER_IP=192.168.6.2
156 22:04:04.249659 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 22:04:04.251604 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 22:04:04.252312 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 22:04:04.252728 skipped lava-vland-overlay
160 22:04:04.253229 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 22:04:04.253732 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 22:04:04.254156 skipped lava-multinode-overlay
163 22:04:04.254634 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 22:04:04.255128 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 22:04:04.255603 Loading test definitions
166 22:04:04.256180 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 22:04:04.256623 Using /lava-936558 at stage 0
168 22:04:04.258788 uuid=936558_1.5.2.4.1 testdef=None
169 22:04:04.259370 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 22:04:04.259882 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 22:04:04.261777 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 22:04:04.262591 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 22:04:04.264775 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 22:04:04.265613 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 22:04:04.267692 runner path: /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/0/tests/0_igt-gpu-panfrost test_uuid 936558_1.5.2.4.1
178 22:04:04.268283 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 22:04:04.269098 Creating lava-test-runner.conf files
181 22:04:04.269306 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/936558/lava-overlay-rsb3tkyh/lava-936558/0 for stage 0
182 22:04:04.269643 - 0_igt-gpu-panfrost
183 22:04:04.269988 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 22:04:04.270285 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 22:04:04.293642 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 22:04:04.294057 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 22:04:04.294321 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 22:04:04.294588 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 22:04:04.294848 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 22:04:11.557702 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 22:04:11.558163 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 22:04:11.558468 extracting modules file /var/lib/lava/dispatcher/tmp/936558/tftp-deploy-hmoh1lzh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/936558/extract-overlay-ramdisk-o6qrfp27/ramdisk
193 22:04:12.959133 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 22:04:12.959607 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 22:04:12.959881 [common] Applying overlay /var/lib/lava/dispatcher/tmp/936558/compress-overlay-5ya6gf1s/overlay-1.5.2.5.tar.gz to ramdisk
196 22:04:12.960146 [common] Applying overlay /var/lib/lava/dispatcher/tmp/936558/compress-overlay-5ya6gf1s/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/936558/extract-overlay-ramdisk-o6qrfp27/ramdisk
197 22:04:12.990601 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 22:04:12.991062 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 22:04:12.991363 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 22:04:12.991737 Converting downloaded kernel to a uImage
201 22:04:12.992142 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/936558/tftp-deploy-hmoh1lzh/kernel/Image /var/lib/lava/dispatcher/tmp/936558/tftp-deploy-hmoh1lzh/kernel/uImage
202 22:04:13.472007 output: Image Name:
203 22:04:13.472434 output: Created: Mon Nov 4 22:04:12 2024
204 22:04:13.472645 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 22:04:13.472849 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 22:04:13.473048 output: Load Address: 01080000
207 22:04:13.473247 output: Entry Point: 01080000
208 22:04:13.473447 output:
209 22:04:13.473776 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 22:04:13.474043 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 22:04:13.474309 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 22:04:13.474561 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 22:04:13.474817 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 22:04:13.475075 Building ramdisk /var/lib/lava/dispatcher/tmp/936558/extract-overlay-ramdisk-o6qrfp27/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/936558/extract-overlay-ramdisk-o6qrfp27/ramdisk
215 22:04:20.025258 >> 502410 blocks
216 22:04:40.816101 Adding RAMdisk u-boot header.
217 22:04:40.816947 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/936558/extract-overlay-ramdisk-o6qrfp27/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/936558/extract-overlay-ramdisk-o6qrfp27/ramdisk.cpio.gz.uboot
218 22:04:41.476555 output: Image Name:
219 22:04:41.476958 output: Created: Mon Nov 4 22:04:40 2024
220 22:04:41.477376 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 22:04:41.477791 output: Data Size: 65716239 Bytes = 64176.01 KiB = 62.67 MiB
222 22:04:41.478193 output: Load Address: 00000000
223 22:04:41.478587 output: Entry Point: 00000000
224 22:04:41.479132 output:
225 22:04:41.480328 rename /var/lib/lava/dispatcher/tmp/936558/extract-overlay-ramdisk-o6qrfp27/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/936558/tftp-deploy-hmoh1lzh/ramdisk/ramdisk.cpio.gz.uboot
226 22:04:41.481043 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 22:04:41.481591 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 22:04:41.482162 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 22:04:41.482625 No LXC device requested
230 22:04:41.483132 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 22:04:41.483641 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 22:04:41.484172 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 22:04:41.484589 Checking files for TFTP limit of 4294967296 bytes.
234 22:04:41.487228 end: 1 tftp-deploy (duration 00:00:40) [common]
235 22:04:41.487794 start: 2 uboot-action (timeout 00:05:00) [common]
236 22:04:41.488361 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 22:04:41.488863 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 22:04:41.489367 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 22:04:41.489896 Using kernel file from prepare-kernel: 936558/tftp-deploy-hmoh1lzh/kernel/uImage
240 22:04:41.490505 substitutions:
241 22:04:41.490916 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 22:04:41.491321 - {DTB_ADDR}: 0x01070000
243 22:04:41.491720 - {DTB}: 936558/tftp-deploy-hmoh1lzh/dtb/meson-g12b-a311d-libretech-cc.dtb
244 22:04:41.492156 - {INITRD}: 936558/tftp-deploy-hmoh1lzh/ramdisk/ramdisk.cpio.gz.uboot
245 22:04:41.492559 - {KERNEL_ADDR}: 0x01080000
246 22:04:41.492954 - {KERNEL}: 936558/tftp-deploy-hmoh1lzh/kernel/uImage
247 22:04:41.493349 - {LAVA_MAC}: None
248 22:04:41.493783 - {PRESEED_CONFIG}: None
249 22:04:41.494182 - {PRESEED_LOCAL}: None
250 22:04:41.494575 - {RAMDISK_ADDR}: 0x08000000
251 22:04:41.494964 - {RAMDISK}: 936558/tftp-deploy-hmoh1lzh/ramdisk/ramdisk.cpio.gz.uboot
252 22:04:41.495360 - {ROOT_PART}: None
253 22:04:41.495748 - {ROOT}: None
254 22:04:41.496170 - {SERVER_IP}: 192.168.6.2
255 22:04:41.496566 - {TEE_ADDR}: 0x83000000
256 22:04:41.496955 - {TEE}: None
257 22:04:41.497343 Parsed boot commands:
258 22:04:41.497722 - setenv autoload no
259 22:04:41.498108 - setenv initrd_high 0xffffffff
260 22:04:41.498494 - setenv fdt_high 0xffffffff
261 22:04:41.498882 - dhcp
262 22:04:41.499272 - setenv serverip 192.168.6.2
263 22:04:41.499661 - tftpboot 0x01080000 936558/tftp-deploy-hmoh1lzh/kernel/uImage
264 22:04:41.500078 - tftpboot 0x08000000 936558/tftp-deploy-hmoh1lzh/ramdisk/ramdisk.cpio.gz.uboot
265 22:04:41.500474 - tftpboot 0x01070000 936558/tftp-deploy-hmoh1lzh/dtb/meson-g12b-a311d-libretech-cc.dtb
266 22:04:41.500864 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 22:04:41.501258 - bootm 0x01080000 0x08000000 0x01070000
268 22:04:41.501750 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 22:04:41.503259 start: 2.3 connect-device (timeout 00:05:00) [common]
271 22:04:41.503702 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 22:04:41.517620 Setting prompt string to ['lava-test: # ']
273 22:04:41.519090 end: 2.3 connect-device (duration 00:00:00) [common]
274 22:04:41.519702 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 22:04:41.520305 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 22:04:41.520846 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 22:04:41.521987 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 22:04:41.562526 >> OK - accepted request
279 22:04:41.564886 Returned 0 in 0 seconds
280 22:04:41.666188 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 22:04:41.667777 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 22:04:41.668401 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 22:04:41.668914 Setting prompt string to ['Hit any key to stop autoboot']
285 22:04:41.669375 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 22:04:41.670921 Trying 192.168.56.21...
287 22:04:41.671391 Connected to conserv1.
288 22:04:41.671813 Escape character is '^]'.
289 22:04:41.672264
290 22:04:41.672701 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 22:04:41.673140
292 22:04:53.267088 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 22:04:53.267503 bl2_stage_init 0x01
294 22:04:53.267745 bl2_stage_init 0x81
295 22:04:53.272204 hw id: 0x0000 - pwm id 0x01
296 22:04:53.272516 bl2_stage_init 0xc1
297 22:04:53.272746 bl2_stage_init 0x02
298 22:04:53.272961
299 22:04:53.278240 L0:00000000
300 22:04:53.278550 L1:20000703
301 22:04:53.278766 L2:00008067
302 22:04:53.278971 L3:14000000
303 22:04:53.281367 B2:00402000
304 22:04:53.281636 B1:e0f83180
305 22:04:53.281845
306 22:04:53.282055 TE: 58124
307 22:04:53.282269
308 22:04:53.291876 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 22:04:53.292198
310 22:04:53.292411 Board ID = 1
311 22:04:53.292618 Set A53 clk to 24M
312 22:04:53.292829 Set A73 clk to 24M
313 22:04:53.297552 Set clk81 to 24M
314 22:04:53.297826 A53 clk: 1200 MHz
315 22:04:53.298035 A73 clk: 1200 MHz
316 22:04:53.302875 CLK81: 166.6M
317 22:04:53.303151 smccc: 00012a92
318 22:04:53.308517 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 22:04:53.308796 board id: 1
320 22:04:53.316371 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 22:04:53.327673 fw parse done
322 22:04:53.333620 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 22:04:53.375469 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 22:04:53.387183 PIEI prepare done
325 22:04:53.387502 fastboot data load
326 22:04:53.387719 fastboot data verify
327 22:04:53.392823 verify result: 266
328 22:04:53.398353 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 22:04:53.398652 LPDDR4 probe
330 22:04:53.398874 ddr clk to 1584MHz
331 22:04:53.406266 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 22:04:53.442754
333 22:04:53.443113 dmc_version 0001
334 22:04:53.449342 Check phy result
335 22:04:53.456208 INFO : End of CA training
336 22:04:53.456654 INFO : End of initialization
337 22:04:53.461785 INFO : Training has run successfully!
338 22:04:53.462196 Check phy result
339 22:04:53.467405 INFO : End of initialization
340 22:04:53.467693 INFO : End of read enable training
341 22:04:53.473015 INFO : End of fine write leveling
342 22:04:53.478610 INFO : End of Write leveling coarse delay
343 22:04:53.479033 INFO : Training has run successfully!
344 22:04:53.479272 Check phy result
345 22:04:53.484203 INFO : End of initialization
346 22:04:53.484493 INFO : End of read dq deskew training
347 22:04:53.489812 INFO : End of MPR read delay center optimization
348 22:04:53.495395 INFO : End of write delay center optimization
349 22:04:53.501041 INFO : End of read delay center optimization
350 22:04:53.501338 INFO : End of max read latency training
351 22:04:53.506539 INFO : Training has run successfully!
352 22:04:53.506960 1D training succeed
353 22:04:53.515704 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 22:04:53.562996 Check phy result
355 22:04:53.563358 INFO : End of initialization
356 22:04:53.584309 INFO : End of 2D read delay Voltage center optimization
357 22:04:53.604309 INFO : End of 2D read delay Voltage center optimization
358 22:04:53.656381 INFO : End of 2D write delay Voltage center optimization
359 22:04:53.706660 INFO : End of 2D write delay Voltage center optimization
360 22:04:53.712214 INFO : Training has run successfully!
361 22:04:53.712495
362 22:04:53.712718 channel==0
363 22:04:53.717866 RxClkDly_Margin_A0==88 ps 9
364 22:04:53.718161 TxDqDly_Margin_A0==98 ps 10
365 22:04:53.721236 RxClkDly_Margin_A1==88 ps 9
366 22:04:53.721503 TxDqDly_Margin_A1==88 ps 9
367 22:04:53.726818 TrainedVREFDQ_A0==74
368 22:04:53.727096 TrainedVREFDQ_A1==74
369 22:04:53.727310 VrefDac_Margin_A0==25
370 22:04:53.732391 DeviceVref_Margin_A0==40
371 22:04:53.732681 VrefDac_Margin_A1==25
372 22:04:53.738041 DeviceVref_Margin_A1==40
373 22:04:53.738320
374 22:04:53.738542
375 22:04:53.738757 channel==1
376 22:04:53.738967 RxClkDly_Margin_A0==98 ps 10
377 22:04:53.741294 TxDqDly_Margin_A0==98 ps 10
378 22:04:53.746976 RxClkDly_Margin_A1==88 ps 9
379 22:04:53.747261 TxDqDly_Margin_A1==88 ps 9
380 22:04:53.747481 TrainedVREFDQ_A0==77
381 22:04:53.752487 TrainedVREFDQ_A1==75
382 22:04:53.752762 VrefDac_Margin_A0==22
383 22:04:53.758188 DeviceVref_Margin_A0==37
384 22:04:53.758466 VrefDac_Margin_A1==24
385 22:04:53.758680 DeviceVref_Margin_A1==38
386 22:04:53.758890
387 22:04:53.763694 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 22:04:53.764007
389 22:04:53.797282 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 22:04:53.797673 2D training succeed
391 22:04:53.802922 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 22:04:53.808518 auto size-- 65535DDR cs0 size: 2048MB
393 22:04:53.808798 DDR cs1 size: 2048MB
394 22:04:53.814318 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 22:04:53.814593 cs0 DataBus test pass
396 22:04:53.814805 cs1 DataBus test pass
397 22:04:53.819904 cs0 AddrBus test pass
398 22:04:53.820202 cs1 AddrBus test pass
399 22:04:53.820414
400 22:04:53.825338 100bdlr_step_size ps== 420
401 22:04:53.825631 result report
402 22:04:53.825851 boot times 0Enable ddr reg access
403 22:04:53.834247 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 22:04:53.847732 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 22:04:54.422540 0.0;M3 CHK:0;cm4_sp_mode 0
406 22:04:54.423342 MVN_1=0x00000000
407 22:04:54.427951 MVN_2=0x00000000
408 22:04:54.433543 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 22:04:54.434069 OPS=0x10
410 22:04:54.434480 ring efuse init
411 22:04:54.434880 chipver efuse init
412 22:04:54.439215 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 22:04:54.444676 [0.018961 Inits done]
414 22:04:54.445102 secure task start!
415 22:04:54.445496 high task start!
416 22:04:54.449316 low task start!
417 22:04:54.449750 run into bl31
418 22:04:54.455923 NOTICE: BL31: v1.3(release):4fc40b1
419 22:04:54.462856 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 22:04:54.463327 NOTICE: BL31: G12A normal boot!
421 22:04:54.489288 NOTICE: BL31: BL33 decompress pass
422 22:04:54.494855 ERROR: Error initializing runtime service opteed_fast
423 22:04:55.727718
424 22:04:55.728161
425 22:04:55.737847 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 22:04:55.738251
427 22:04:55.739568 Model: Libre Computer AML-A311D-CC Alta
428 22:04:55.943784 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 22:04:55.967395 DRAM: 2 GiB (effective 3.8 GiB)
430 22:04:56.111105 Core: 408 devices, 31 uclasses, devicetree: separate
431 22:04:56.116923 WDT: Not starting watchdog@f0d0
432 22:04:56.149227 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 22:04:56.161809 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 22:04:56.166928 ** Bad device specification mmc 0 **
435 22:04:56.177035 Card did not respond to voltage select! : -110
436 22:04:56.184799 ** Bad device specification mmc 0 **
437 22:04:56.185485 Couldn't find partition mmc 0
438 22:04:56.193006 Card did not respond to voltage select! : -110
439 22:04:56.198738 ** Bad device specification mmc 0 **
440 22:04:56.199145 Couldn't find partition mmc 0
441 22:04:56.203769 Error: could not access storage.
442 22:04:57.467001 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
443 22:04:57.467619 bl2_stage_init 0x81
444 22:04:57.472511 hw id: 0x0000 - pwm id 0x01
445 22:04:57.472965 bl2_stage_init 0xc1
446 22:04:57.473368 bl2_stage_init 0x02
447 22:04:57.473762
448 22:04:57.478049 L0:00000000
449 22:04:57.478488 L1:20000703
450 22:04:57.478883 L2:00008067
451 22:04:57.479272 L3:14000000
452 22:04:57.479659 B2:00402000
453 22:04:57.483687 B1:e0f83180
454 22:04:57.484127
455 22:04:57.484522 TE: 58150
456 22:04:57.484916
457 22:04:57.489267 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 22:04:57.489691
459 22:04:57.490084 Board ID = 1
460 22:04:57.495225 Set A53 clk to 24M
461 22:04:57.495692 Set A73 clk to 24M
462 22:04:57.496115 Set clk81 to 24M
463 22:04:57.500515 A53 clk: 1200 MHz
464 22:04:57.500952 A73 clk: 1200 MHz
465 22:04:57.501342 CLK81: 166.6M
466 22:04:57.501727 smccc: 00012aab
467 22:04:57.506030 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 22:04:57.511629 board id: 1
469 22:04:57.516505 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 22:04:57.528274 fw parse done
471 22:04:57.533164 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 22:04:57.576784 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 22:04:57.587672 PIEI prepare done
474 22:04:57.588159 fastboot data load
475 22:04:57.588555 fastboot data verify
476 22:04:57.593219 verify result: 266
477 22:04:57.598836 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 22:04:57.599259 LPDDR4 probe
479 22:04:57.599653 ddr clk to 1584MHz
480 22:04:57.605918 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 22:04:57.643135
482 22:04:57.643585 dmc_version 0001
483 22:04:57.649848 Check phy result
484 22:04:57.656660 INFO : End of CA training
485 22:04:57.657110 INFO : End of initialization
486 22:04:57.662197 INFO : Training has run successfully!
487 22:04:57.662620 Check phy result
488 22:04:57.667786 INFO : End of initialization
489 22:04:57.668234 INFO : End of read enable training
490 22:04:57.673408 INFO : End of fine write leveling
491 22:04:57.678979 INFO : End of Write leveling coarse delay
492 22:04:57.679405 INFO : Training has run successfully!
493 22:04:57.679795 Check phy result
494 22:04:57.684652 INFO : End of initialization
495 22:04:57.685074 INFO : End of read dq deskew training
496 22:04:57.690210 INFO : End of MPR read delay center optimization
497 22:04:57.695806 INFO : End of write delay center optimization
498 22:04:57.701437 INFO : End of read delay center optimization
499 22:04:57.701854 INFO : End of max read latency training
500 22:04:57.707025 INFO : Training has run successfully!
501 22:04:57.707440 1D training succeed
502 22:04:57.715255 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 22:04:57.762899 Check phy result
504 22:04:57.763344 INFO : End of initialization
505 22:04:57.785477 INFO : End of 2D read delay Voltage center optimization
506 22:04:57.805708 INFO : End of 2D read delay Voltage center optimization
507 22:04:57.857688 INFO : End of 2D write delay Voltage center optimization
508 22:04:57.908059 INFO : End of 2D write delay Voltage center optimization
509 22:04:57.913691 INFO : Training has run successfully!
510 22:04:57.914131
511 22:04:57.914528 channel==0
512 22:04:57.919199 RxClkDly_Margin_A0==88 ps 9
513 22:04:57.919634 TxDqDly_Margin_A0==98 ps 10
514 22:04:57.924854 RxClkDly_Margin_A1==88 ps 9
515 22:04:57.925293 TxDqDly_Margin_A1==98 ps 10
516 22:04:57.925688 TrainedVREFDQ_A0==74
517 22:04:57.930422 TrainedVREFDQ_A1==74
518 22:04:57.930863 VrefDac_Margin_A0==25
519 22:04:57.931255 DeviceVref_Margin_A0==40
520 22:04:57.935956 VrefDac_Margin_A1==25
521 22:04:57.936409 DeviceVref_Margin_A1==40
522 22:04:57.936800
523 22:04:57.937189
524 22:04:57.941708 channel==1
525 22:04:57.942125 RxClkDly_Margin_A0==98 ps 10
526 22:04:57.942511 TxDqDly_Margin_A0==98 ps 10
527 22:04:57.947167 RxClkDly_Margin_A1==88 ps 9
528 22:04:57.947593 TxDqDly_Margin_A1==88 ps 9
529 22:04:57.952812 TrainedVREFDQ_A0==77
530 22:04:57.953248 TrainedVREFDQ_A1==77
531 22:04:57.953640 VrefDac_Margin_A0==22
532 22:04:57.958446 DeviceVref_Margin_A0==37
533 22:04:57.958861 VrefDac_Margin_A1==24
534 22:04:57.964004 DeviceVref_Margin_A1==37
535 22:04:57.964426
536 22:04:57.964820 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 22:04:57.965209
538 22:04:57.997793 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000016 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000019 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
539 22:04:57.998284 2D training succeed
540 22:04:58.003193 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 22:04:58.008808 auto size-- 65535DDR cs0 size: 2048MB
542 22:04:58.009258 DDR cs1 size: 2048MB
543 22:04:58.014362 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 22:04:58.014786 cs0 DataBus test pass
545 22:04:58.020047 cs1 DataBus test pass
546 22:04:58.020487 cs0 AddrBus test pass
547 22:04:58.020878 cs1 AddrBus test pass
548 22:04:58.021269
549 22:04:58.025583 100bdlr_step_size ps== 420
550 22:04:58.026029 result report
551 22:04:58.031335 boot times 0Enable ddr reg access
552 22:04:58.035700 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 22:04:58.049176 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 22:04:58.624268 0.0;M3 CHK:0;cm4_sp_mode 0
555 22:04:58.624849 MVN_1=0x00000000
556 22:04:58.629558 MVN_2=0x00000000
557 22:04:58.635122 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 22:04:58.635546 OPS=0x10
559 22:04:58.635938 ring efuse init
560 22:04:58.636367 chipver efuse init
561 22:04:58.640661 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 22:04:58.646304 [0.018961 Inits done]
563 22:04:58.646740 secure task start!
564 22:04:58.647128 high task start!
565 22:04:58.651035 low task start!
566 22:04:58.651458 run into bl31
567 22:04:58.657543 NOTICE: BL31: v1.3(release):4fc40b1
568 22:04:58.665391 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 22:04:58.665818 NOTICE: BL31: G12A normal boot!
570 22:04:58.690620 NOTICE: BL31: BL33 decompress pass
571 22:04:58.696321 ERROR: Error initializing runtime service opteed_fast
572 22:04:59.929303
573 22:04:59.929898
574 22:04:59.937684 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 22:04:59.938136
576 22:04:59.938549 Model: Libre Computer AML-A311D-CC Alta
577 22:05:00.146138 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 22:05:00.168695 DRAM: 2 GiB (effective 3.8 GiB)
579 22:05:00.312586 Core: 408 devices, 31 uclasses, devicetree: separate
580 22:05:00.317498 WDT: Not starting watchdog@f0d0
581 22:05:00.350634 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 22:05:00.363111 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 22:05:00.367204 ** Bad device specification mmc 0 **
584 22:05:00.378445 Card did not respond to voltage select! : -110
585 22:05:00.385211 ** Bad device specification mmc 0 **
586 22:05:00.385659 Couldn't find partition mmc 0
587 22:05:00.394477 Card did not respond to voltage select! : -110
588 22:05:00.399926 ** Bad device specification mmc 0 **
589 22:05:00.400473 Couldn't find partition mmc 0
590 22:05:00.404034 Error: could not access storage.
591 22:05:00.747655 Net: eth0: ethernet@ff3f0000
592 22:05:00.748711 starting USB...
593 22:05:00.999377 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 22:05:01.000373 Starting the controller
595 22:05:01.006257 USB XHCI 1.10
596 22:05:02.718468 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 22:05:02.719047 bl2_stage_init 0x01
598 22:05:02.719469 bl2_stage_init 0x81
599 22:05:02.724051 hw id: 0x0000 - pwm id 0x01
600 22:05:02.724501 bl2_stage_init 0xc1
601 22:05:02.724911 bl2_stage_init 0x02
602 22:05:02.725311
603 22:05:02.729719 L0:00000000
604 22:05:02.730174 L1:20000703
605 22:05:02.730580 L2:00008067
606 22:05:02.731061 L3:14000000
607 22:05:02.735228 B2:00402000
608 22:05:02.735672 B1:e0f83180
609 22:05:02.736175
610 22:05:02.736602 TE: 58159
611 22:05:02.737001
612 22:05:02.740849 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 22:05:02.741290
614 22:05:02.741697 Board ID = 1
615 22:05:02.746467 Set A53 clk to 24M
616 22:05:02.746898 Set A73 clk to 24M
617 22:05:02.747298 Set clk81 to 24M
618 22:05:02.752032 A53 clk: 1200 MHz
619 22:05:02.752466 A73 clk: 1200 MHz
620 22:05:02.752869 CLK81: 166.6M
621 22:05:02.753265 smccc: 00012ab5
622 22:05:02.757659 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 22:05:02.763236 board id: 1
624 22:05:02.769089 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 22:05:02.779812 fw parse done
626 22:05:02.785787 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 22:05:02.827683 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 22:05:02.839451 PIEI prepare done
629 22:05:02.840012 fastboot data load
630 22:05:02.840524 fastboot data verify
631 22:05:02.844936 verify result: 266
632 22:05:02.850521 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 22:05:02.850972 LPDDR4 probe
634 22:05:02.851465 ddr clk to 1584MHz
635 22:05:02.858539 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 22:05:02.895077
637 22:05:02.895569 dmc_version 0001
638 22:05:02.902598 Check phy result
639 22:05:02.908632 INFO : End of CA training
640 22:05:02.909483 INFO : End of initialization
641 22:05:02.914001 INFO : Training has run successfully!
642 22:05:02.914767 Check phy result
643 22:05:02.919562 INFO : End of initialization
644 22:05:02.920511 INFO : End of read enable training
645 22:05:02.925086 INFO : End of fine write leveling
646 22:05:02.930805 INFO : End of Write leveling coarse delay
647 22:05:02.931253 INFO : Training has run successfully!
648 22:05:02.931647 Check phy result
649 22:05:02.936408 INFO : End of initialization
650 22:05:02.936860 INFO : End of read dq deskew training
651 22:05:02.941990 INFO : End of MPR read delay center optimization
652 22:05:02.947594 INFO : End of write delay center optimization
653 22:05:02.953133 INFO : End of read delay center optimization
654 22:05:02.953571 INFO : End of max read latency training
655 22:05:02.958756 INFO : Training has run successfully!
656 22:05:02.959229 1D training succeed
657 22:05:02.967907 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 22:05:03.015294 Check phy result
659 22:05:03.015813 INFO : End of initialization
660 22:05:03.037982 INFO : End of 2D read delay Voltage center optimization
661 22:05:03.057457 INFO : End of 2D read delay Voltage center optimization
662 22:05:03.110426 INFO : End of 2D write delay Voltage center optimization
663 22:05:03.159760 INFO : End of 2D write delay Voltage center optimization
664 22:05:03.165337 INFO : Training has run successfully!
665 22:05:03.165838
666 22:05:03.166239 channel==0
667 22:05:03.170907 RxClkDly_Margin_A0==88 ps 9
668 22:05:03.171339 TxDqDly_Margin_A0==98 ps 10
669 22:05:03.174235 RxClkDly_Margin_A1==88 ps 9
670 22:05:03.174657 TxDqDly_Margin_A1==98 ps 10
671 22:05:03.179834 TrainedVREFDQ_A0==74
672 22:05:03.180461 TrainedVREFDQ_A1==74
673 22:05:03.180944 VrefDac_Margin_A0==24
674 22:05:03.185521 DeviceVref_Margin_A0==40
675 22:05:03.186024 VrefDac_Margin_A1==24
676 22:05:03.191088 DeviceVref_Margin_A1==40
677 22:05:03.191587
678 22:05:03.192016
679 22:05:03.192470 channel==1
680 22:05:03.192910 RxClkDly_Margin_A0==98 ps 10
681 22:05:03.196673 TxDqDly_Margin_A0==88 ps 9
682 22:05:03.197178 RxClkDly_Margin_A1==98 ps 10
683 22:05:03.202269 TxDqDly_Margin_A1==88 ps 9
684 22:05:03.202708 TrainedVREFDQ_A0==76
685 22:05:03.203102 TrainedVREFDQ_A1==77
686 22:05:03.207843 VrefDac_Margin_A0==22
687 22:05:03.208402 DeviceVref_Margin_A0==38
688 22:05:03.213601 VrefDac_Margin_A1==22
689 22:05:03.214087 DeviceVref_Margin_A1==37
690 22:05:03.214486
691 22:05:03.219107 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 22:05:03.219583
693 22:05:03.247081 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
694 22:05:03.252698 2D training succeed
695 22:05:03.258338 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 22:05:03.258781 auto size-- 65535DDR cs0 size: 2048MB
697 22:05:03.263901 DDR cs1 size: 2048MB
698 22:05:03.264361 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 22:05:03.269517 cs0 DataBus test pass
700 22:05:03.269950 cs1 DataBus test pass
701 22:05:03.270348 cs0 AddrBus test pass
702 22:05:03.275086 cs1 AddrBus test pass
703 22:05:03.275530
704 22:05:03.275931 100bdlr_step_size ps== 420
705 22:05:03.276370 result report
706 22:05:03.280647 boot times 0Enable ddr reg access
707 22:05:03.287914 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 22:05:03.301741 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 22:05:03.875652 0.0;M3 CHK:0;cm4_sp_mode 0
710 22:05:03.876287 MVN_1=0x00000000
711 22:05:03.881211 MVN_2=0x00000000
712 22:05:03.886780 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 22:05:03.887296 OPS=0x10
714 22:05:03.887714 ring efuse init
715 22:05:03.888168 chipver efuse init
716 22:05:03.892512 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 22:05:03.898071 [0.018961 Inits done]
718 22:05:03.898552 secure task start!
719 22:05:03.898948 high task start!
720 22:05:03.902670 low task start!
721 22:05:03.903159 run into bl31
722 22:05:03.909352 NOTICE: BL31: v1.3(release):4fc40b1
723 22:05:03.917124 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 22:05:03.917603 NOTICE: BL31: G12A normal boot!
725 22:05:03.942461 NOTICE: BL31: BL33 decompress pass
726 22:05:03.948118 ERROR: Error initializing runtime service opteed_fast
727 22:05:05.181021
728 22:05:05.181593
729 22:05:05.189392 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 22:05:05.189828
731 22:05:05.190223 Model: Libre Computer AML-A311D-CC Alta
732 22:05:05.397895 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 22:05:05.421234 DRAM: 2 GiB (effective 3.8 GiB)
734 22:05:05.564275 Core: 408 devices, 31 uclasses, devicetree: separate
735 22:05:05.570083 WDT: Not starting watchdog@f0d0
736 22:05:05.602395 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 22:05:05.614759 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 22:05:05.618901 ** Bad device specification mmc 0 **
739 22:05:05.630106 Card did not respond to voltage select! : -110
740 22:05:05.637821 ** Bad device specification mmc 0 **
741 22:05:05.638284 Couldn't find partition mmc 0
742 22:05:05.646162 Card did not respond to voltage select! : -110
743 22:05:05.651526 ** Bad device specification mmc 0 **
744 22:05:05.651965 Couldn't find partition mmc 0
745 22:05:05.656069 Error: could not access storage.
746 22:05:05.998358 Net: eth0: ethernet@ff3f0000
747 22:05:05.998958 starting USB...
748 22:05:06.251128 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 22:05:06.251739 Starting the controller
750 22:05:06.258357 USB XHCI 1.10
751 22:05:08.417380 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 22:05:08.417971 bl2_stage_init 0x01
753 22:05:08.418393 bl2_stage_init 0x81
754 22:05:08.422774 hw id: 0x0000 - pwm id 0x01
755 22:05:08.423220 bl2_stage_init 0xc1
756 22:05:08.423629 bl2_stage_init 0x02
757 22:05:08.424068
758 22:05:08.428317 L0:00000000
759 22:05:08.428750 L1:20000703
760 22:05:08.429153 L2:00008067
761 22:05:08.429548 L3:14000000
762 22:05:08.433975 B2:00402000
763 22:05:08.434400 B1:e0f83180
764 22:05:08.434799
765 22:05:08.435212 TE: 58167
766 22:05:08.435645
767 22:05:08.439542 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 22:05:08.440055
769 22:05:08.440476 Board ID = 1
770 22:05:08.445266 Set A53 clk to 24M
771 22:05:08.445722 Set A73 clk to 24M
772 22:05:08.446129 Set clk81 to 24M
773 22:05:08.450733 A53 clk: 1200 MHz
774 22:05:08.451174 A73 clk: 1200 MHz
775 22:05:08.451577 CLK81: 166.6M
776 22:05:08.451967 smccc: 00012abd
777 22:05:08.456389 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 22:05:08.461967 board id: 1
779 22:05:08.467831 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 22:05:08.478461 fw parse done
781 22:05:08.483699 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 22:05:08.526775 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 22:05:08.537970 PIEI prepare done
784 22:05:08.538404 fastboot data load
785 22:05:08.538806 fastboot data verify
786 22:05:08.543615 verify result: 266
787 22:05:08.549306 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 22:05:08.549768 LPDDR4 probe
789 22:05:08.550183 ddr clk to 1584MHz
790 22:05:08.557179 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 22:05:08.594497
792 22:05:08.594952 dmc_version 0001
793 22:05:08.601119 Check phy result
794 22:05:08.607110 INFO : End of CA training
795 22:05:08.607557 INFO : End of initialization
796 22:05:08.612721 INFO : Training has run successfully!
797 22:05:08.613164 Check phy result
798 22:05:08.618493 INFO : End of initialization
799 22:05:08.618927 INFO : End of read enable training
800 22:05:08.621513 INFO : End of fine write leveling
801 22:05:08.627104 INFO : End of Write leveling coarse delay
802 22:05:08.632587 INFO : Training has run successfully!
803 22:05:08.633013 Check phy result
804 22:05:08.633414 INFO : End of initialization
805 22:05:08.638330 INFO : End of read dq deskew training
806 22:05:08.643858 INFO : End of MPR read delay center optimization
807 22:05:08.644327 INFO : End of write delay center optimization
808 22:05:08.649433 INFO : End of read delay center optimization
809 22:05:08.655142 INFO : End of max read latency training
810 22:05:08.655566 INFO : Training has run successfully!
811 22:05:08.660665 1D training succeed
812 22:05:08.666575 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 22:05:08.714343 Check phy result
814 22:05:08.714854 INFO : End of initialization
815 22:05:08.736078 INFO : End of 2D read delay Voltage center optimization
816 22:05:08.756299 INFO : End of 2D read delay Voltage center optimization
817 22:05:08.808383 INFO : End of 2D write delay Voltage center optimization
818 22:05:08.857638 INFO : End of 2D write delay Voltage center optimization
819 22:05:08.863145 INFO : Training has run successfully!
820 22:05:08.863608
821 22:05:08.864072 channel==0
822 22:05:08.868794 RxClkDly_Margin_A0==88 ps 9
823 22:05:08.869247 TxDqDly_Margin_A0==98 ps 10
824 22:05:08.872217 RxClkDly_Margin_A1==88 ps 9
825 22:05:08.872670 TxDqDly_Margin_A1==88 ps 9
826 22:05:08.877807 TrainedVREFDQ_A0==74
827 22:05:08.878268 TrainedVREFDQ_A1==74
828 22:05:08.878688 VrefDac_Margin_A0==25
829 22:05:08.883430 DeviceVref_Margin_A0==40
830 22:05:08.883901 VrefDac_Margin_A1==25
831 22:05:08.889021 DeviceVref_Margin_A1==40
832 22:05:08.889502
833 22:05:08.889899
834 22:05:08.890295 channel==1
835 22:05:08.890679 RxClkDly_Margin_A0==98 ps 10
836 22:05:08.894682 TxDqDly_Margin_A0==98 ps 10
837 22:05:08.895127 RxClkDly_Margin_A1==88 ps 9
838 22:05:08.900237 TxDqDly_Margin_A1==88 ps 9
839 22:05:08.900683 TrainedVREFDQ_A0==77
840 22:05:08.901082 TrainedVREFDQ_A1==77
841 22:05:08.905773 VrefDac_Margin_A0==22
842 22:05:08.906206 DeviceVref_Margin_A0==37
843 22:05:08.911418 VrefDac_Margin_A1==24
844 22:05:08.911885 DeviceVref_Margin_A1==37
845 22:05:08.912321
846 22:05:08.916952 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 22:05:08.917394
848 22:05:08.944947 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000016 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
849 22:05:08.950480 2D training succeed
850 22:05:08.956087 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 22:05:08.956537 auto size-- 65535DDR cs0 size: 2048MB
852 22:05:08.961671 DDR cs1 size: 2048MB
853 22:05:08.962107 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 22:05:08.967277 cs0 DataBus test pass
855 22:05:08.967715 cs1 DataBus test pass
856 22:05:08.968158 cs0 AddrBus test pass
857 22:05:08.972849 cs1 AddrBus test pass
858 22:05:08.973286
859 22:05:08.973680 100bdlr_step_size ps== 420
860 22:05:08.974073 result report
861 22:05:08.978493 boot times 0Enable ddr reg access
862 22:05:08.985971 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 22:05:08.999453 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 22:05:09.573016 0.0;M3 CHK:0;cm4_sp_mode 0
865 22:05:09.573623 MVN_1=0x00000000
866 22:05:09.578538 MVN_2=0x00000000
867 22:05:09.584352 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 22:05:09.584810 OPS=0x10
869 22:05:09.585227 ring efuse init
870 22:05:09.585632 chipver efuse init
871 22:05:09.589906 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 22:05:09.595460 [0.018961 Inits done]
873 22:05:09.595911 secure task start!
874 22:05:09.596370 high task start!
875 22:05:09.600113 low task start!
876 22:05:09.600561 run into bl31
877 22:05:09.606770 NOTICE: BL31: v1.3(release):4fc40b1
878 22:05:09.613649 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 22:05:09.614110 NOTICE: BL31: G12A normal boot!
880 22:05:09.639947 NOTICE: BL31: BL33 decompress pass
881 22:05:09.645622 ERROR: Error initializing runtime service opteed_fast
882 22:05:10.878512
883 22:05:10.879129
884 22:05:10.886843 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 22:05:10.887313
886 22:05:10.887727 Model: Libre Computer AML-A311D-CC Alta
887 22:05:11.095307 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 22:05:11.118662 DRAM: 2 GiB (effective 3.8 GiB)
889 22:05:11.261637 Core: 408 devices, 31 uclasses, devicetree: separate
890 22:05:11.267706 WDT: Not starting watchdog@f0d0
891 22:05:11.299876 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 22:05:11.312298 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 22:05:11.317262 ** Bad device specification mmc 0 **
894 22:05:11.327659 Card did not respond to voltage select! : -110
895 22:05:11.335233 ** Bad device specification mmc 0 **
896 22:05:11.335707 Couldn't find partition mmc 0
897 22:05:11.343633 Card did not respond to voltage select! : -110
898 22:05:11.349066 ** Bad device specification mmc 0 **
899 22:05:11.349547 Couldn't find partition mmc 0
900 22:05:11.354107 Error: could not access storage.
901 22:05:11.697811 Net: eth0: ethernet@ff3f0000
902 22:05:11.698373 starting USB...
903 22:05:11.949613 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 22:05:11.950156 Starting the controller
905 22:05:11.956431 USB XHCI 1.10
906 22:05:13.510492 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
907 22:05:13.517902 scanning usb for storage devices... 0 Storage Device(s) found
909 22:05:13.569397 Hit any key to stop autoboot: 1
910 22:05:13.570173 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
911 22:05:13.570752 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
912 22:05:13.571229 Setting prompt string to ['=>']
913 22:05:13.571711 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
914 22:05:13.575281 0
915 22:05:13.576155 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
916 22:05:13.576651 Sending with 10 millisecond of delay
918 22:05:14.711119 => setenv autoload no
919 22:05:14.721881 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
920 22:05:14.726714 setenv autoload no
921 22:05:14.727428 Sending with 10 millisecond of delay
923 22:05:16.524098 => setenv initrd_high 0xffffffff
924 22:05:16.534885 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
925 22:05:16.535751 setenv initrd_high 0xffff ffff
926 22:05:16.536508 Sending with 10 millisecond of delay
928 22:05:18.153016 => setenv fdt_high 0xffffffff
929 22:05:18.163572 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
930 22:05:18.164131 setenv fdt_high 0xffffffff
931 22:05:18.164615 Sending with 10 millisecond of delay
933 22:05:18.456212 => dhcp
934 22:05:18.466998 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
935 22:05:18.467809 dhcp
936 22:05:18.468282 Speed: 1000, full duplex
937 22:05:18.468684 BOOTP broadcast 1
938 22:05:18.479906 DHCP client bound to address 192.168.6.27 (12 ms)
939 22:05:18.480665 Sending with 10 millisecond of delay
941 22:05:20.157498 => setenv serverip 192.168.6.2
942 22:05:20.168331 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
943 22:05:20.169239 setenv serverip 192.168.6.2
944 22:05:20.169930 Sending with 10 millisecond of delay
946 22:05:23.896242 => tftpboot 0x01080000 936558/tftp-deploy-hmoh1lzh/kernel/uImage
947 22:05:23.907094 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
948 22:05:23.908303 tftpboot 0x01080000 936558/tftp-deploy-hmoh1lzh/kernel/uImage
949 22:05:23.908778 Speed: 1000, full duplex
950 22:05:23.909192 Using ethernet@ff3f0000 device
951 22:05:23.909694 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
952 22:05:23.915134 Filename '936558/tftp-deploy-hmoh1lzh/kernel/uImage'.
953 22:05:23.918979 Load address: 0x1080000
954 22:05:24.445524 Loading: *######### UDP wrong checksum 000000ff 00003a91
955 22:05:24.704577 #### UDP wrong checksum 000000ff 0000d183
956 22:05:26.807722 ##################################### 43.6 MiB
957 22:05:26.808374 15.1 MiB/s
958 22:05:26.808810 done
959 22:05:26.812132 Bytes transferred = 45713984 (2b98a40 hex)
960 22:05:26.812956 Sending with 10 millisecond of delay
962 22:05:31.501092 => tftpboot 0x08000000 936558/tftp-deploy-hmoh1lzh/ramdisk/ramdisk.cpio.gz.uboot
963 22:05:31.511674 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
964 22:05:31.512244 tftpboot 0x08000000 936558/tftp-deploy-hmoh1lzh/ramdisk/ramdisk.cpio.gz.uboot
965 22:05:31.512502 Speed: 1000, full duplex
966 22:05:31.512715 Using ethernet@ff3f0000 device
967 22:05:31.514589 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
968 22:05:31.526489 Filename '936558/tftp-deploy-hmoh1lzh/ramdisk/ramdisk.cpio.gz.uboot'.
969 22:05:31.527061 Load address: 0x8000000
970 22:05:40.794685 Loading: *########T ######################################### UDP wrong checksum 0000000f 00007b74
971 22:05:44.935411 UDP wrong checksum 000000ff 0000a5f5
972 22:05:44.944091 UDP wrong checksum 000000ff 000033e8
973 22:05:45.795325 T UDP wrong checksum 0000000f 00007b74
974 22:05:53.062046 T UDP wrong checksum 000000ff 0000fea4
975 22:05:53.109846 UDP wrong checksum 000000ff 00008997
976 22:05:55.797407 T UDP wrong checksum 0000000f 00007b74
977 22:06:15.801989 T T T T UDP wrong checksum 0000000f 00007b74
978 22:06:30.805835 T T
979 22:06:30.806286 Retry count exceeded; starting again
981 22:06:30.809007 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
984 22:06:30.810765 end: 2.4 uboot-commands (duration 00:01:49) [common]
986 22:06:30.812138 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
988 22:06:30.813245 end: 2 uboot-action (duration 00:01:49) [common]
990 22:06:30.814803 Cleaning after the job
991 22:06:30.815382 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936558/tftp-deploy-hmoh1lzh/ramdisk
992 22:06:30.816902 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936558/tftp-deploy-hmoh1lzh/kernel
993 22:06:30.825689 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936558/tftp-deploy-hmoh1lzh/dtb
994 22:06:30.827097 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/936558/tftp-deploy-hmoh1lzh/modules
995 22:06:30.844164 start: 4.1 power-off (timeout 00:00:30) [common]
996 22:06:30.845298 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
997 22:06:30.881820 >> OK - accepted request
998 22:06:30.884434 Returned 0 in 0 seconds
999 22:06:30.985366 end: 4.1 power-off (duration 00:00:00) [common]
1001 22:06:30.986562 start: 4.2 read-feedback (timeout 00:10:00) [common]
1002 22:06:30.987386 Listened to connection for namespace 'common' for up to 1s
1003 22:06:31.988024 Finalising connection for namespace 'common'
1004 22:06:31.988536 Disconnecting from shell: Finalise
1005 22:06:31.988808 =>
1006 22:06:32.089572 end: 4.2 read-feedback (duration 00:00:01) [common]
1007 22:06:32.090272 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/936558
1008 22:06:32.757720 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/936558
1009 22:06:32.758445 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.