Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 18:03:51.616128 lava-dispatcher, installed at version: 2024.01
2 18:03:51.616934 start: 0 validate
3 18:03:51.617413 Start time: 2024-11-04 18:03:51.617384+00:00 (UTC)
4 18:03:51.617994 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 18:03:51.618533 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 18:03:51.662823 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 18:03:51.663410 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-98-g57d5fb99dade%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 18:03:52.720605 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 18:03:52.721258 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-98-g57d5fb99dade%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 18:03:57.794534 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 18:03:57.795129 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-98-g57d5fb99dade%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 18:03:58.866279 validate duration: 7.25
14 18:03:58.867906 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 18:03:58.868673 start: 1.1 download-retry (timeout 00:10:00) [common]
16 18:03:58.869346 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 18:03:58.870406 Not decompressing ramdisk as can be used compressed.
18 18:03:58.871229 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 18:03:58.871742 saving as /var/lib/lava/dispatcher/tmp/935728/tftp-deploy-w0rkgci4/ramdisk/rootfs.cpio.gz
20 18:03:58.872355 total size: 8181887 (7 MB)
21 18:03:58.917470 progress 0 % (0 MB)
22 18:03:58.927297 progress 5 % (0 MB)
23 18:03:58.937350 progress 10 % (0 MB)
24 18:03:58.948127 progress 15 % (1 MB)
25 18:03:58.957151 progress 20 % (1 MB)
26 18:03:58.962754 progress 25 % (1 MB)
27 18:03:58.968000 progress 30 % (2 MB)
28 18:03:58.973528 progress 35 % (2 MB)
29 18:03:58.978648 progress 40 % (3 MB)
30 18:03:58.984167 progress 45 % (3 MB)
31 18:03:58.989380 progress 50 % (3 MB)
32 18:03:58.994863 progress 55 % (4 MB)
33 18:03:58.999959 progress 60 % (4 MB)
34 18:03:59.005513 progress 65 % (5 MB)
35 18:03:59.010686 progress 70 % (5 MB)
36 18:03:59.016164 progress 75 % (5 MB)
37 18:03:59.021261 progress 80 % (6 MB)
38 18:03:59.026786 progress 85 % (6 MB)
39 18:03:59.031872 progress 90 % (7 MB)
40 18:03:59.037183 progress 95 % (7 MB)
41 18:03:59.042219 progress 100 % (7 MB)
42 18:03:59.042893 7 MB downloaded in 0.17 s (45.76 MB/s)
43 18:03:59.043464 end: 1.1.1 http-download (duration 00:00:00) [common]
45 18:03:59.044402 end: 1.1 download-retry (duration 00:00:00) [common]
46 18:03:59.044717 start: 1.2 download-retry (timeout 00:10:00) [common]
47 18:03:59.045002 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 18:03:59.045483 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-98-g57d5fb99dade/arm64/defconfig/gcc-12/kernel/Image
49 18:03:59.045734 saving as /var/lib/lava/dispatcher/tmp/935728/tftp-deploy-w0rkgci4/kernel/Image
50 18:03:59.045949 total size: 45713920 (43 MB)
51 18:03:59.046169 No compression specified
52 18:03:59.084148 progress 0 % (0 MB)
53 18:03:59.111959 progress 5 % (2 MB)
54 18:03:59.140126 progress 10 % (4 MB)
55 18:03:59.168908 progress 15 % (6 MB)
56 18:03:59.199610 progress 20 % (8 MB)
57 18:03:59.229214 progress 25 % (10 MB)
58 18:03:59.256691 progress 30 % (13 MB)
59 18:03:59.284217 progress 35 % (15 MB)
60 18:03:59.312109 progress 40 % (17 MB)
61 18:03:59.339862 progress 45 % (19 MB)
62 18:03:59.367291 progress 50 % (21 MB)
63 18:03:59.394960 progress 55 % (24 MB)
64 18:03:59.423699 progress 60 % (26 MB)
65 18:03:59.451226 progress 65 % (28 MB)
66 18:03:59.479332 progress 70 % (30 MB)
67 18:03:59.507299 progress 75 % (32 MB)
68 18:03:59.534892 progress 80 % (34 MB)
69 18:03:59.561984 progress 85 % (37 MB)
70 18:03:59.589652 progress 90 % (39 MB)
71 18:03:59.617964 progress 95 % (41 MB)
72 18:03:59.645278 progress 100 % (43 MB)
73 18:03:59.645832 43 MB downloaded in 0.60 s (72.68 MB/s)
74 18:03:59.646316 end: 1.2.1 http-download (duration 00:00:01) [common]
76 18:03:59.647167 end: 1.2 download-retry (duration 00:00:01) [common]
77 18:03:59.647445 start: 1.3 download-retry (timeout 00:09:59) [common]
78 18:03:59.647715 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 18:03:59.648211 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-98-g57d5fb99dade/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 18:03:59.648493 saving as /var/lib/lava/dispatcher/tmp/935728/tftp-deploy-w0rkgci4/dtb/meson-g12b-a311d-libretech-cc.dtb
81 18:03:59.648705 total size: 54703 (0 MB)
82 18:03:59.648916 No compression specified
83 18:03:59.687364 progress 59 % (0 MB)
84 18:03:59.688265 progress 100 % (0 MB)
85 18:03:59.688851 0 MB downloaded in 0.04 s (1.30 MB/s)
86 18:03:59.689333 end: 1.3.1 http-download (duration 00:00:00) [common]
88 18:03:59.690150 end: 1.3 download-retry (duration 00:00:00) [common]
89 18:03:59.690415 start: 1.4 download-retry (timeout 00:09:59) [common]
90 18:03:59.690680 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 18:03:59.691148 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-98-g57d5fb99dade/arm64/defconfig/gcc-12/modules.tar.xz
92 18:03:59.691391 saving as /var/lib/lava/dispatcher/tmp/935728/tftp-deploy-w0rkgci4/modules/modules.tar
93 18:03:59.691597 total size: 11616108 (11 MB)
94 18:03:59.691807 Using unxz to decompress xz
95 18:03:59.734271 progress 0 % (0 MB)
96 18:03:59.803281 progress 5 % (0 MB)
97 18:03:59.880190 progress 10 % (1 MB)
98 18:03:59.980560 progress 15 % (1 MB)
99 18:04:00.782911 progress 20 % (2 MB)
100 18:04:00.863799 progress 25 % (2 MB)
101 18:04:00.941727 progress 30 % (3 MB)
102 18:04:01.021487 progress 35 % (3 MB)
103 18:04:01.096044 progress 40 % (4 MB)
104 18:04:01.174056 progress 45 % (5 MB)
105 18:04:01.259539 progress 50 % (5 MB)
106 18:04:01.337988 progress 55 % (6 MB)
107 18:04:01.425898 progress 60 % (6 MB)
108 18:04:01.508833 progress 65 % (7 MB)
109 18:04:01.592242 progress 70 % (7 MB)
110 18:04:01.674254 progress 75 % (8 MB)
111 18:04:01.761114 progress 80 % (8 MB)
112 18:04:01.844955 progress 85 % (9 MB)
113 18:04:01.930916 progress 90 % (10 MB)
114 18:04:02.007001 progress 95 % (10 MB)
115 18:04:02.084515 progress 100 % (11 MB)
116 18:04:02.097457 11 MB downloaded in 2.41 s (4.60 MB/s)
117 18:04:02.098063 end: 1.4.1 http-download (duration 00:00:02) [common]
119 18:04:02.098896 end: 1.4 download-retry (duration 00:00:02) [common]
120 18:04:02.099167 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 18:04:02.099434 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 18:04:02.099682 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 18:04:02.099936 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 18:04:02.101033 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s
125 18:04:02.101926 makedir: /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin
126 18:04:02.102304 makedir: /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/tests
127 18:04:02.102628 makedir: /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/results
128 18:04:02.103083 Creating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin/lava-add-keys
129 18:04:02.104091 Creating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin/lava-add-sources
130 18:04:02.105022 Creating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin/lava-background-process-start
131 18:04:02.105951 Creating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin/lava-background-process-stop
132 18:04:02.106916 Creating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin/lava-common-functions
133 18:04:02.107817 Creating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin/lava-echo-ipv4
134 18:04:02.108777 Creating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin/lava-install-packages
135 18:04:02.109666 Creating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin/lava-installed-packages
136 18:04:02.110527 Creating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin/lava-os-build
137 18:04:02.111401 Creating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin/lava-probe-channel
138 18:04:02.112312 Creating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin/lava-probe-ip
139 18:04:02.113207 Creating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin/lava-target-ip
140 18:04:02.114077 Creating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin/lava-target-mac
141 18:04:02.114944 Creating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin/lava-target-storage
142 18:04:02.115820 Creating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin/lava-test-case
143 18:04:02.116396 Creating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin/lava-test-event
144 18:04:02.117141 Creating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin/lava-test-feedback
145 18:04:02.118046 Creating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin/lava-test-raise
146 18:04:02.118941 Creating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin/lava-test-reference
147 18:04:02.119814 Creating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin/lava-test-runner
148 18:04:02.120729 Creating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin/lava-test-set
149 18:04:02.121642 Creating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin/lava-test-shell
150 18:04:02.122528 Updating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin/lava-install-packages (oe)
151 18:04:02.123463 Updating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/bin/lava-installed-packages (oe)
152 18:04:02.124302 Creating /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/environment
153 18:04:02.125001 LAVA metadata
154 18:04:02.125477 - LAVA_JOB_ID=935728
155 18:04:02.125901 - LAVA_DISPATCHER_IP=192.168.6.2
156 18:04:02.126558 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 18:04:02.128373 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 18:04:02.128966 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 18:04:02.129376 skipped lava-vland-overlay
160 18:04:02.129862 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 18:04:02.130365 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 18:04:02.130786 skipped lava-multinode-overlay
163 18:04:02.131266 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 18:04:02.131761 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 18:04:02.132271 Loading test definitions
166 18:04:02.132818 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 18:04:02.133258 Using /lava-935728 at stage 0
168 18:04:02.135499 uuid=935728_1.5.2.4.1 testdef=None
169 18:04:02.136106 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 18:04:02.136389 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 18:04:02.138230 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 18:04:02.139036 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 18:04:02.141317 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 18:04:02.142168 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 18:04:02.144400 runner path: /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/0/tests/0_dmesg test_uuid 935728_1.5.2.4.1
178 18:04:02.144997 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 18:04:02.145775 Creating lava-test-runner.conf files
181 18:04:02.145982 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/935728/lava-overlay-y6ycdf0s/lava-935728/0 for stage 0
182 18:04:02.146323 - 0_dmesg
183 18:04:02.146672 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 18:04:02.146956 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 18:04:02.170588 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 18:04:02.171014 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 18:04:02.171276 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 18:04:02.171545 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 18:04:02.171810 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 18:04:03.111700 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 18:04:03.112209 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 18:04:03.112457 extracting modules file /var/lib/lava/dispatcher/tmp/935728/tftp-deploy-w0rkgci4/modules/modules.tar to /var/lib/lava/dispatcher/tmp/935728/extract-overlay-ramdisk-hy4md73g/ramdisk
193 18:04:04.484340 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 18:04:04.484810 start: 1.5.5 apply-overlay-tftp (timeout 00:09:54) [common]
195 18:04:04.485084 [common] Applying overlay /var/lib/lava/dispatcher/tmp/935728/compress-overlay-87anozs4/overlay-1.5.2.5.tar.gz to ramdisk
196 18:04:04.485299 [common] Applying overlay /var/lib/lava/dispatcher/tmp/935728/compress-overlay-87anozs4/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/935728/extract-overlay-ramdisk-hy4md73g/ramdisk
197 18:04:04.515407 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 18:04:04.515839 start: 1.5.6 prepare-kernel (timeout 00:09:54) [common]
199 18:04:04.516136 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:54) [common]
200 18:04:04.516367 Converting downloaded kernel to a uImage
201 18:04:04.516677 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/935728/tftp-deploy-w0rkgci4/kernel/Image /var/lib/lava/dispatcher/tmp/935728/tftp-deploy-w0rkgci4/kernel/uImage
202 18:04:04.989577 output: Image Name:
203 18:04:04.990010 output: Created: Mon Nov 4 18:04:04 2024
204 18:04:04.990217 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 18:04:04.990423 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 18:04:04.990625 output: Load Address: 01080000
207 18:04:04.990823 output: Entry Point: 01080000
208 18:04:04.991020 output:
209 18:04:04.991357 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 18:04:04.991622 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 18:04:04.991895 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 18:04:04.992204 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 18:04:04.992472 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 18:04:04.992744 Building ramdisk /var/lib/lava/dispatcher/tmp/935728/extract-overlay-ramdisk-hy4md73g/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/935728/extract-overlay-ramdisk-hy4md73g/ramdisk
215 18:04:07.457624 >> 181606 blocks
216 18:04:16.005042 Adding RAMdisk u-boot header.
217 18:04:16.005488 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/935728/extract-overlay-ramdisk-hy4md73g/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/935728/extract-overlay-ramdisk-hy4md73g/ramdisk.cpio.gz.uboot
218 18:04:16.278751 output: Image Name:
219 18:04:16.279183 output: Created: Mon Nov 4 18:04:16 2024
220 18:04:16.279711 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 18:04:16.280244 output: Data Size: 26061609 Bytes = 25450.79 KiB = 24.85 MiB
222 18:04:16.280703 output: Load Address: 00000000
223 18:04:16.281150 output: Entry Point: 00000000
224 18:04:16.281591 output:
225 18:04:16.282931 rename /var/lib/lava/dispatcher/tmp/935728/extract-overlay-ramdisk-hy4md73g/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/935728/tftp-deploy-w0rkgci4/ramdisk/ramdisk.cpio.gz.uboot
226 18:04:16.283768 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 18:04:16.284424 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 18:04:16.285019 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 18:04:16.285530 No LXC device requested
230 18:04:16.286104 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 18:04:16.286686 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 18:04:16.287248 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 18:04:16.287710 Checking files for TFTP limit of 4294967296 bytes.
234 18:04:16.290740 end: 1 tftp-deploy (duration 00:00:17) [common]
235 18:04:16.291440 start: 2 uboot-action (timeout 00:05:00) [common]
236 18:04:16.292078 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 18:04:16.292668 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 18:04:16.293241 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 18:04:16.293849 Using kernel file from prepare-kernel: 935728/tftp-deploy-w0rkgci4/kernel/uImage
240 18:04:16.294555 substitutions:
241 18:04:16.295032 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 18:04:16.295484 - {DTB_ADDR}: 0x01070000
243 18:04:16.295927 - {DTB}: 935728/tftp-deploy-w0rkgci4/dtb/meson-g12b-a311d-libretech-cc.dtb
244 18:04:16.296413 - {INITRD}: 935728/tftp-deploy-w0rkgci4/ramdisk/ramdisk.cpio.gz.uboot
245 18:04:16.296861 - {KERNEL_ADDR}: 0x01080000
246 18:04:16.297303 - {KERNEL}: 935728/tftp-deploy-w0rkgci4/kernel/uImage
247 18:04:16.297747 - {LAVA_MAC}: None
248 18:04:16.298236 - {PRESEED_CONFIG}: None
249 18:04:16.298685 - {PRESEED_LOCAL}: None
250 18:04:16.299126 - {RAMDISK_ADDR}: 0x08000000
251 18:04:16.299563 - {RAMDISK}: 935728/tftp-deploy-w0rkgci4/ramdisk/ramdisk.cpio.gz.uboot
252 18:04:16.300031 - {ROOT_PART}: None
253 18:04:16.300481 - {ROOT}: None
254 18:04:16.300919 - {SERVER_IP}: 192.168.6.2
255 18:04:16.301362 - {TEE_ADDR}: 0x83000000
256 18:04:16.301799 - {TEE}: None
257 18:04:16.302237 Parsed boot commands:
258 18:04:16.302663 - setenv autoload no
259 18:04:16.303097 - setenv initrd_high 0xffffffff
260 18:04:16.303530 - setenv fdt_high 0xffffffff
261 18:04:16.303961 - dhcp
262 18:04:16.304429 - setenv serverip 192.168.6.2
263 18:04:16.304866 - tftpboot 0x01080000 935728/tftp-deploy-w0rkgci4/kernel/uImage
264 18:04:16.305302 - tftpboot 0x08000000 935728/tftp-deploy-w0rkgci4/ramdisk/ramdisk.cpio.gz.uboot
265 18:04:16.305738 - tftpboot 0x01070000 935728/tftp-deploy-w0rkgci4/dtb/meson-g12b-a311d-libretech-cc.dtb
266 18:04:16.306170 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 18:04:16.306611 - bootm 0x01080000 0x08000000 0x01070000
268 18:04:16.307194 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 18:04:16.308913 start: 2.3 connect-device (timeout 00:05:00) [common]
271 18:04:16.309433 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 18:04:16.326918 Setting prompt string to ['lava-test: # ']
273 18:04:16.328709 end: 2.3 connect-device (duration 00:00:00) [common]
274 18:04:16.329411 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 18:04:16.330030 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 18:04:16.330635 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 18:04:16.332004 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 18:04:16.369806 >> OK - accepted request
279 18:04:16.371977 Returned 0 in 0 seconds
280 18:04:16.473374 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 18:04:16.475433 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 18:04:16.476229 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 18:04:16.476902 Setting prompt string to ['Hit any key to stop autoboot']
285 18:04:16.477522 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 18:04:16.479512 Trying 192.168.56.21...
287 18:04:16.480196 Connected to conserv1.
288 18:04:16.480749 Escape character is '^]'.
289 18:04:16.481296
290 18:04:16.481860 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 18:04:16.482423
292 18:04:28.879877 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
293 18:04:28.880623 bl2_stage_init 0x81
294 18:04:28.885485 hw id: 0x0000 - pwm id 0x01
295 18:04:28.886057 bl2_stage_init 0xc1
296 18:04:28.886558 bl2_stage_init 0x02
297 18:04:28.887021
298 18:04:28.890946 L0:00000000
299 18:04:28.891429 L1:20000703
300 18:04:28.891875 L2:00008067
301 18:04:28.892350 L3:14000000
302 18:04:28.892781 B2:00402000
303 18:04:28.896657 B1:e0f83180
304 18:04:28.897124
305 18:04:28.897562 TE: 58150
306 18:04:28.898007
307 18:04:28.902155 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
308 18:04:28.902626
309 18:04:28.903066 Board ID = 1
310 18:04:28.907724 Set A53 clk to 24M
311 18:04:28.908226 Set A73 clk to 24M
312 18:04:28.908664 Set clk81 to 24M
313 18:04:28.913403 A53 clk: 1200 MHz
314 18:04:28.913864 A73 clk: 1200 MHz
315 18:04:28.914300 CLK81: 166.6M
316 18:04:28.914725 smccc: 00012aab
317 18:04:28.918951 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
318 18:04:28.924643 board id: 1
319 18:04:28.930330 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
320 18:04:28.940997 fw parse done
321 18:04:28.946989 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
322 18:04:28.989726 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
323 18:04:29.000486 PIEI prepare done
324 18:04:29.000951 fastboot data load
325 18:04:29.001391 fastboot data verify
326 18:04:29.006098 verify result: 266
327 18:04:29.011753 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
328 18:04:29.012329 LPDDR4 probe
329 18:04:29.012776 ddr clk to 1584MHz
330 18:04:29.019750 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
331 18:04:29.057019
332 18:04:29.057540 dmc_version 0001
333 18:04:29.063799 Check phy result
334 18:04:29.069597 INFO : End of CA training
335 18:04:29.070064 INFO : End of initialization
336 18:04:29.075123 INFO : Training has run successfully!
337 18:04:29.075594 Check phy result
338 18:04:29.080828 INFO : End of initialization
339 18:04:29.081319 INFO : End of read enable training
340 18:04:29.084084 INFO : End of fine write leveling
341 18:04:29.089565 INFO : End of Write leveling coarse delay
342 18:04:29.095141 INFO : Training has run successfully!
343 18:04:29.095608 Check phy result
344 18:04:29.096078 INFO : End of initialization
345 18:04:29.100749 INFO : End of read dq deskew training
346 18:04:29.106319 INFO : End of MPR read delay center optimization
347 18:04:29.106800 INFO : End of write delay center optimization
348 18:04:29.111960 INFO : End of read delay center optimization
349 18:04:29.117485 INFO : End of max read latency training
350 18:04:29.117956 INFO : Training has run successfully!
351 18:04:29.123156 1D training succeed
352 18:04:29.129267 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
353 18:04:29.176740 Check phy result
354 18:04:29.177271 INFO : End of initialization
355 18:04:29.199274 INFO : End of 2D read delay Voltage center optimization
356 18:04:29.218296 INFO : End of 2D read delay Voltage center optimization
357 18:04:29.270305 INFO : End of 2D write delay Voltage center optimization
358 18:04:29.320343 INFO : End of 2D write delay Voltage center optimization
359 18:04:29.325920 INFO : Training has run successfully!
360 18:04:29.326398
361 18:04:29.326853 channel==0
362 18:04:29.331486 RxClkDly_Margin_A0==88 ps 9
363 18:04:29.331958 TxDqDly_Margin_A0==98 ps 10
364 18:04:29.337107 RxClkDly_Margin_A1==88 ps 9
365 18:04:29.337584 TxDqDly_Margin_A1==98 ps 10
366 18:04:29.338038 TrainedVREFDQ_A0==74
367 18:04:29.342745 TrainedVREFDQ_A1==76
368 18:04:29.343221 VrefDac_Margin_A0==24
369 18:04:29.343667 DeviceVref_Margin_A0==40
370 18:04:29.348303 VrefDac_Margin_A1==24
371 18:04:29.348809 DeviceVref_Margin_A1==38
372 18:04:29.349262
373 18:04:29.349708
374 18:04:29.353918 channel==1
375 18:04:29.354409 RxClkDly_Margin_A0==98 ps 10
376 18:04:29.354860 TxDqDly_Margin_A0==98 ps 10
377 18:04:29.359497 RxClkDly_Margin_A1==88 ps 9
378 18:04:29.359970 TxDqDly_Margin_A1==88 ps 9
379 18:04:29.365164 TrainedVREFDQ_A0==77
380 18:04:29.365677 TrainedVREFDQ_A1==77
381 18:04:29.366135 VrefDac_Margin_A0==22
382 18:04:29.370761 DeviceVref_Margin_A0==37
383 18:04:29.371234 VrefDac_Margin_A1==24
384 18:04:29.376289 DeviceVref_Margin_A1==37
385 18:04:29.376760
386 18:04:29.377202 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
387 18:04:29.377649
388 18:04:29.409968 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
389 18:04:29.410610 2D training succeed
390 18:04:29.415494 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
391 18:04:29.421115 auto size-- 65535DDR cs0 size: 2048MB
392 18:04:29.421601 DDR cs1 size: 2048MB
393 18:04:29.426747 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
394 18:04:29.427221 cs0 DataBus test pass
395 18:04:29.432275 cs1 DataBus test pass
396 18:04:29.432745 cs0 AddrBus test pass
397 18:04:29.433187 cs1 AddrBus test pass
398 18:04:29.433618
399 18:04:29.437880 100bdlr_step_size ps== 420
400 18:04:29.438360 result report
401 18:04:29.443527 boot times 0Enable ddr reg access
402 18:04:29.448878 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
403 18:04:29.462335 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
404 18:04:30.034313 0.0;M3 CHK:0;cm4_sp_mode 0
405 18:04:30.034996 MVN_1=0x00000000
406 18:04:30.039792 MVN_2=0x00000000
407 18:04:30.045569 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
408 18:04:30.046118 OPS=0x10
409 18:04:30.046596 ring efuse init
410 18:04:30.047049 chipver efuse init
411 18:04:30.051124 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
412 18:04:30.056751 [0.018960 Inits done]
413 18:04:30.057245 secure task start!
414 18:04:30.057706 high task start!
415 18:04:30.061272 low task start!
416 18:04:30.061761 run into bl31
417 18:04:30.067951 NOTICE: BL31: v1.3(release):4fc40b1
418 18:04:30.075822 NOTICE: BL31: Built : 15:58:17, May 22 2019
419 18:04:30.076346 NOTICE: BL31: G12A normal boot!
420 18:04:30.101094 NOTICE: BL31: BL33 decompress pass
421 18:04:30.106817 ERROR: Error initializing runtime service opteed_fast
422 18:04:31.339686
423 18:04:31.340393
424 18:04:31.348222 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
425 18:04:31.348744
426 18:04:31.349209 Model: Libre Computer AML-A311D-CC Alta
427 18:04:31.556524 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
428 18:04:31.579938 DRAM: 2 GiB (effective 3.8 GiB)
429 18:04:31.722883 Core: 408 devices, 31 uclasses, devicetree: separate
430 18:04:31.728743 WDT: Not starting watchdog@f0d0
431 18:04:31.761013 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
432 18:04:31.773465 Loading Environment from FAT... Card did not respond to voltage select! : -110
433 18:04:31.778423 ** Bad device specification mmc 0 **
434 18:04:31.788787 Card did not respond to voltage select! : -110
435 18:04:31.796427 ** Bad device specification mmc 0 **
436 18:04:31.796926 Couldn't find partition mmc 0
437 18:04:31.804765 Card did not respond to voltage select! : -110
438 18:04:31.810294 ** Bad device specification mmc 0 **
439 18:04:31.810792 Couldn't find partition mmc 0
440 18:04:31.815348 Error: could not access storage.
441 18:04:33.080029 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
442 18:04:33.080658 bl2_stage_init 0x01
443 18:04:33.081137 bl2_stage_init 0x81
444 18:04:33.085541 hw id: 0x0000 - pwm id 0x01
445 18:04:33.086026 bl2_stage_init 0xc1
446 18:04:33.086480 bl2_stage_init 0x02
447 18:04:33.086928
448 18:04:33.091172 L0:00000000
449 18:04:33.091654 L1:20000703
450 18:04:33.092133 L2:00008067
451 18:04:33.092581 L3:14000000
452 18:04:33.096740 B2:00402000
453 18:04:33.097221 B1:e0f83180
454 18:04:33.097666
455 18:04:33.098106 TE: 58124
456 18:04:33.098549
457 18:04:33.102352 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 18:04:33.102844
459 18:04:33.103297 Board ID = 1
460 18:04:33.108084 Set A53 clk to 24M
461 18:04:33.108569 Set A73 clk to 24M
462 18:04:33.109021 Set clk81 to 24M
463 18:04:33.113551 A53 clk: 1200 MHz
464 18:04:33.114032 A73 clk: 1200 MHz
465 18:04:33.114485 CLK81: 166.6M
466 18:04:33.114922 smccc: 00012a92
467 18:04:33.119194 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 18:04:33.124730 board id: 1
469 18:04:33.130656 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 18:04:33.141320 fw parse done
471 18:04:33.147328 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 18:04:33.189923 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 18:04:33.200796 PIEI prepare done
474 18:04:33.201285 fastboot data load
475 18:04:33.201741 fastboot data verify
476 18:04:33.206436 verify result: 266
477 18:04:33.212068 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 18:04:33.212547 LPDDR4 probe
479 18:04:33.212996 ddr clk to 1584MHz
480 18:04:33.220077 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 18:04:33.257392
482 18:04:33.257894 dmc_version 0001
483 18:04:33.263939 Check phy result
484 18:04:33.269936 INFO : End of CA training
485 18:04:33.270423 INFO : End of initialization
486 18:04:33.275447 INFO : Training has run successfully!
487 18:04:33.275923 Check phy result
488 18:04:33.281008 INFO : End of initialization
489 18:04:33.281485 INFO : End of read enable training
490 18:04:33.286601 INFO : End of fine write leveling
491 18:04:33.292244 INFO : End of Write leveling coarse delay
492 18:04:33.292723 INFO : Training has run successfully!
493 18:04:33.293168 Check phy result
494 18:04:33.297800 INFO : End of initialization
495 18:04:33.298281 INFO : End of read dq deskew training
496 18:04:33.303400 INFO : End of MPR read delay center optimization
497 18:04:33.309081 INFO : End of write delay center optimization
498 18:04:33.314702 INFO : End of read delay center optimization
499 18:04:33.315187 INFO : End of max read latency training
500 18:04:33.320279 INFO : Training has run successfully!
501 18:04:33.320754 1D training succeed
502 18:04:33.329392 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 18:04:33.377112 Check phy result
504 18:04:33.377637 INFO : End of initialization
505 18:04:33.398713 INFO : End of 2D read delay Voltage center optimization
506 18:04:33.418095 INFO : End of 2D read delay Voltage center optimization
507 18:04:33.471050 INFO : End of 2D write delay Voltage center optimization
508 18:04:33.520387 INFO : End of 2D write delay Voltage center optimization
509 18:04:33.525923 INFO : Training has run successfully!
510 18:04:33.526411
511 18:04:33.526873 channel==0
512 18:04:33.531565 RxClkDly_Margin_A0==88 ps 9
513 18:04:33.532088 TxDqDly_Margin_A0==98 ps 10
514 18:04:33.537131 RxClkDly_Margin_A1==88 ps 9
515 18:04:33.537608 TxDqDly_Margin_A1==98 ps 10
516 18:04:33.538063 TrainedVREFDQ_A0==74
517 18:04:33.542731 TrainedVREFDQ_A1==74
518 18:04:33.543235 VrefDac_Margin_A0==25
519 18:04:33.543684 DeviceVref_Margin_A0==40
520 18:04:33.548366 VrefDac_Margin_A1==25
521 18:04:33.548840 DeviceVref_Margin_A1==40
522 18:04:33.549287
523 18:04:33.549732
524 18:04:33.553952 channel==1
525 18:04:33.554422 RxClkDly_Margin_A0==98 ps 10
526 18:04:33.554866 TxDqDly_Margin_A0==88 ps 9
527 18:04:33.559552 RxClkDly_Margin_A1==88 ps 9
528 18:04:33.560071 TxDqDly_Margin_A1==98 ps 10
529 18:04:33.565111 TrainedVREFDQ_A0==76
530 18:04:33.565588 TrainedVREFDQ_A1==77
531 18:04:33.566041 VrefDac_Margin_A0==22
532 18:04:33.570725 DeviceVref_Margin_A0==38
533 18:04:33.571204 VrefDac_Margin_A1==24
534 18:04:33.576383 DeviceVref_Margin_A1==37
535 18:04:33.576859
536 18:04:33.577305 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 18:04:33.577749
538 18:04:33.609928 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
539 18:04:33.610456 2D training succeed
540 18:04:33.615708 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 18:04:33.621149 auto size-- 65535DDR cs0 size: 2048MB
542 18:04:33.621640 DDR cs1 size: 2048MB
543 18:04:33.626746 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 18:04:33.627223 cs0 DataBus test pass
545 18:04:33.632378 cs1 DataBus test pass
546 18:04:33.632863 cs0 AddrBus test pass
547 18:04:33.633314 cs1 AddrBus test pass
548 18:04:33.633757
549 18:04:33.637952 100bdlr_step_size ps== 420
550 18:04:33.638439 result report
551 18:04:33.643537 boot times 0Enable ddr reg access
552 18:04:33.648891 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 18:04:33.662404 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 18:04:34.236096 0.0;M3 CHK:0;cm4_sp_mode 0
555 18:04:34.236726 MVN_1=0x00000000
556 18:04:34.241522 MVN_2=0x00000000
557 18:04:34.247371 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 18:04:34.247895 OPS=0x10
559 18:04:34.248410 ring efuse init
560 18:04:34.248879 chipver efuse init
561 18:04:34.252986 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 18:04:34.258537 [0.018961 Inits done]
563 18:04:34.259011 secure task start!
564 18:04:34.259446 high task start!
565 18:04:34.262213 low task start!
566 18:04:34.262675 run into bl31
567 18:04:34.269779 NOTICE: BL31: v1.3(release):4fc40b1
568 18:04:34.277609 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 18:04:34.278077 NOTICE: BL31: G12A normal boot!
570 18:04:34.302913 NOTICE: BL31: BL33 decompress pass
571 18:04:34.308587 ERROR: Error initializing runtime service opteed_fast
572 18:04:35.541663
573 18:04:35.542285
574 18:04:35.550232 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 18:04:35.550724
576 18:04:35.551184 Model: Libre Computer AML-A311D-CC Alta
577 18:04:35.758603 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 18:04:35.781873 DRAM: 2 GiB (effective 3.8 GiB)
579 18:04:35.924904 Core: 408 devices, 31 uclasses, devicetree: separate
580 18:04:35.930782 WDT: Not starting watchdog@f0d0
581 18:04:35.962842 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 18:04:35.975448 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 18:04:35.980447 ** Bad device specification mmc 0 **
584 18:04:35.990717 Card did not respond to voltage select! : -110
585 18:04:35.998407 ** Bad device specification mmc 0 **
586 18:04:35.998885 Couldn't find partition mmc 0
587 18:04:36.006741 Card did not respond to voltage select! : -110
588 18:04:36.012221 ** Bad device specification mmc 0 **
589 18:04:36.012704 Couldn't find partition mmc 0
590 18:04:36.017364 Error: could not access storage.
591 18:04:36.359925 Net: eth0: ethernet@ff3f0000
592 18:04:36.360521 starting USB...
593 18:04:36.611548 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 18:04:36.612189 Starting the controller
595 18:04:36.618656 USB XHCI 1.10
596 18:04:38.330312 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 18:04:38.331000 bl2_stage_init 0x01
598 18:04:38.331715 bl2_stage_init 0x81
599 18:04:38.336036 hw id: 0x0000 - pwm id 0x01
600 18:04:38.336969 bl2_stage_init 0xc1
601 18:04:38.337827 bl2_stage_init 0x02
602 18:04:38.338672
603 18:04:38.341648 L0:00000000
604 18:04:38.342569 L1:20000703
605 18:04:38.343450 L2:00008067
606 18:04:38.344388 L3:14000000
607 18:04:38.347230 B2:00402000
608 18:04:38.348215 B1:e0f83180
609 18:04:38.348775
610 18:04:38.349199 TE: 58159
611 18:04:38.349604
612 18:04:38.352698 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 18:04:38.353181
614 18:04:38.353589 Board ID = 1
615 18:04:38.358280 Set A53 clk to 24M
616 18:04:38.358714 Set A73 clk to 24M
617 18:04:38.359116 Set clk81 to 24M
618 18:04:38.363855 A53 clk: 1200 MHz
619 18:04:38.364320 A73 clk: 1200 MHz
620 18:04:38.364717 CLK81: 166.6M
621 18:04:38.365109 smccc: 00012ab5
622 18:04:38.369475 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 18:04:38.375093 board id: 1
624 18:04:38.380929 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 18:04:38.391582 fw parse done
626 18:04:38.397757 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 18:04:38.440066 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 18:04:38.450914 PIEI prepare done
629 18:04:38.451431 fastboot data load
630 18:04:38.451841 fastboot data verify
631 18:04:38.456595 verify result: 266
632 18:04:38.462144 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 18:04:38.462600 LPDDR4 probe
634 18:04:38.463000 ddr clk to 1584MHz
635 18:04:38.470132 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 18:04:38.506604
637 18:04:38.507126 dmc_version 0001
638 18:04:38.514103 Check phy result
639 18:04:38.520018 INFO : End of CA training
640 18:04:38.520467 INFO : End of initialization
641 18:04:38.525532 INFO : Training has run successfully!
642 18:04:38.526029 Check phy result
643 18:04:38.531126 INFO : End of initialization
644 18:04:38.531570 INFO : End of read enable training
645 18:04:38.536780 INFO : End of fine write leveling
646 18:04:38.542328 INFO : End of Write leveling coarse delay
647 18:04:38.542783 INFO : Training has run successfully!
648 18:04:38.543191 Check phy result
649 18:04:38.547969 INFO : End of initialization
650 18:04:38.548427 INFO : End of read dq deskew training
651 18:04:38.553543 INFO : End of MPR read delay center optimization
652 18:04:38.559145 INFO : End of write delay center optimization
653 18:04:38.564706 INFO : End of read delay center optimization
654 18:04:38.565169 INFO : End of max read latency training
655 18:04:38.570314 INFO : Training has run successfully!
656 18:04:38.570758 1D training succeed
657 18:04:38.579494 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 18:04:38.627156 Check phy result
659 18:04:38.627696 INFO : End of initialization
660 18:04:38.649639 INFO : End of 2D read delay Voltage center optimization
661 18:04:38.669367 INFO : End of 2D read delay Voltage center optimization
662 18:04:38.722000 INFO : End of 2D write delay Voltage center optimization
663 18:04:38.771359 INFO : End of 2D write delay Voltage center optimization
664 18:04:38.776894 INFO : Training has run successfully!
665 18:04:38.777354
666 18:04:38.777760 channel==0
667 18:04:38.782481 RxClkDly_Margin_A0==88 ps 9
668 18:04:38.782929 TxDqDly_Margin_A0==98 ps 10
669 18:04:38.788092 RxClkDly_Margin_A1==88 ps 9
670 18:04:38.788559 TxDqDly_Margin_A1==98 ps 10
671 18:04:38.788962 TrainedVREFDQ_A0==74
672 18:04:38.793653 TrainedVREFDQ_A1==74
673 18:04:38.794096 VrefDac_Margin_A0==25
674 18:04:38.794494 DeviceVref_Margin_A0==40
675 18:04:38.799263 VrefDac_Margin_A1==24
676 18:04:38.799717 DeviceVref_Margin_A1==40
677 18:04:38.800152
678 18:04:38.800552
679 18:04:38.804887 channel==1
680 18:04:38.805324 RxClkDly_Margin_A0==98 ps 10
681 18:04:38.805724 TxDqDly_Margin_A0==88 ps 9
682 18:04:38.810494 RxClkDly_Margin_A1==98 ps 10
683 18:04:38.811011 TxDqDly_Margin_A1==98 ps 10
684 18:04:38.816070 TrainedVREFDQ_A0==76
685 18:04:38.816524 TrainedVREFDQ_A1==78
686 18:04:38.816927 VrefDac_Margin_A0==22
687 18:04:38.821650 DeviceVref_Margin_A0==38
688 18:04:38.822094 VrefDac_Margin_A1==22
689 18:04:38.827352 DeviceVref_Margin_A1==36
690 18:04:38.827851
691 18:04:38.828300 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 18:04:38.832919
693 18:04:38.860885 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000017 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
694 18:04:38.861441 2D training succeed
695 18:04:38.866491 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 18:04:38.872082 auto size-- 65535DDR cs0 size: 2048MB
697 18:04:38.872536 DDR cs1 size: 2048MB
698 18:04:38.877644 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 18:04:38.878085 cs0 DataBus test pass
700 18:04:38.883260 cs1 DataBus test pass
701 18:04:38.883699 cs0 AddrBus test pass
702 18:04:38.884133 cs1 AddrBus test pass
703 18:04:38.884529
704 18:04:38.888865 100bdlr_step_size ps== 420
705 18:04:38.889327 result report
706 18:04:38.894477 boot times 0Enable ddr reg access
707 18:04:38.898924 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 18:04:38.912476 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 18:04:39.486379 0.0;M3 CHK:0;cm4_sp_mode 0
710 18:04:39.486993 MVN_1=0x00000000
711 18:04:39.491932 MVN_2=0x00000000
712 18:04:39.497667 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 18:04:39.498114 OPS=0x10
714 18:04:39.498515 ring efuse init
715 18:04:39.498906 chipver efuse init
716 18:04:39.503233 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 18:04:39.508836 [0.018961 Inits done]
718 18:04:39.509288 secure task start!
719 18:04:39.509682 high task start!
720 18:04:39.513430 low task start!
721 18:04:39.513868 run into bl31
722 18:04:39.520109 NOTICE: BL31: v1.3(release):4fc40b1
723 18:04:39.527953 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 18:04:39.528525 NOTICE: BL31: G12A normal boot!
725 18:04:39.553240 NOTICE: BL31: BL33 decompress pass
726 18:04:39.558961 ERROR: Error initializing runtime service opteed_fast
727 18:04:40.791871
728 18:04:40.792512
729 18:04:40.799331 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 18:04:40.799850
731 18:04:40.800303 Model: Libre Computer AML-A311D-CC Alta
732 18:04:41.008748 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 18:04:41.032055 DRAM: 2 GiB (effective 3.8 GiB)
734 18:04:41.175020 Core: 408 devices, 31 uclasses, devicetree: separate
735 18:04:41.180823 WDT: Not starting watchdog@f0d0
736 18:04:41.213208 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 18:04:41.225552 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 18:04:41.230534 ** Bad device specification mmc 0 **
739 18:04:41.240901 Card did not respond to voltage select! : -110
740 18:04:41.248504 ** Bad device specification mmc 0 **
741 18:04:41.249000 Couldn't find partition mmc 0
742 18:04:41.256851 Card did not respond to voltage select! : -110
743 18:04:41.262359 ** Bad device specification mmc 0 **
744 18:04:41.262828 Couldn't find partition mmc 0
745 18:04:41.266455 Error: could not access storage.
746 18:04:41.609966 Net: eth0: ethernet@ff3f0000
747 18:04:41.610554 starting USB...
748 18:04:41.861776 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 18:04:41.862357 Starting the controller
750 18:04:41.867909 USB XHCI 1.10
751 18:04:44.031935 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
752 18:04:44.032811 bl2_stage_init 0x81
753 18:04:44.037365 hw id: 0x0000 - pwm id 0x01
754 18:04:44.037885 bl2_stage_init 0xc1
755 18:04:44.038348 bl2_stage_init 0x02
756 18:04:44.038813
757 18:04:44.042962 L0:00000000
758 18:04:44.043460 L1:20000703
759 18:04:44.043916 L2:00008067
760 18:04:44.044412 L3:14000000
761 18:04:44.044851 B2:00402000
762 18:04:44.045785 B1:e0f83180
763 18:04:44.046269
764 18:04:44.046719 TE: 58141
765 18:04:44.047164
766 18:04:44.056828 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
767 18:04:44.057345
768 18:04:44.057803 Board ID = 1
769 18:04:44.058253 Set A53 clk to 24M
770 18:04:44.058688 Set A73 clk to 24M
771 18:04:44.062452 Set clk81 to 24M
772 18:04:44.062956 A53 clk: 1200 MHz
773 18:04:44.063425 A73 clk: 1200 MHz
774 18:04:44.066039 CLK81: 166.6M
775 18:04:44.066537 smccc: 00012aa3
776 18:04:44.071484 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
777 18:04:44.077033 board id: 1
778 18:04:44.081406 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
779 18:04:44.092996 fw parse done
780 18:04:44.097978 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
781 18:04:44.140607 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
782 18:04:44.152595 PIEI prepare done
783 18:04:44.153113 fastboot data load
784 18:04:44.153525 fastboot data verify
785 18:04:44.158169 verify result: 266
786 18:04:44.163882 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
787 18:04:44.164420 LPDDR4 probe
788 18:04:44.164822 ddr clk to 1584MHz
789 18:04:44.170845 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
790 18:04:44.209025
791 18:04:44.209543 dmc_version 0001
792 18:04:44.214779 Check phy result
793 18:04:44.221593 INFO : End of CA training
794 18:04:44.222086 INFO : End of initialization
795 18:04:44.227239 INFO : Training has run successfully!
796 18:04:44.227743 Check phy result
797 18:04:44.232854 INFO : End of initialization
798 18:04:44.233346 INFO : End of read enable training
799 18:04:44.236071 INFO : End of fine write leveling
800 18:04:44.241596 INFO : End of Write leveling coarse delay
801 18:04:44.247287 INFO : Training has run successfully!
802 18:04:44.247809 Check phy result
803 18:04:44.248309 INFO : End of initialization
804 18:04:44.252778 INFO : End of read dq deskew training
805 18:04:44.258498 INFO : End of MPR read delay center optimization
806 18:04:44.258994 INFO : End of write delay center optimization
807 18:04:44.264069 INFO : End of read delay center optimization
808 18:04:44.269789 INFO : End of max read latency training
809 18:04:44.270297 INFO : Training has run successfully!
810 18:04:44.275194 1D training succeed
811 18:04:44.280231 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
812 18:04:44.327827 Check phy result
813 18:04:44.328407 INFO : End of initialization
814 18:04:44.350273 INFO : End of 2D read delay Voltage center optimization
815 18:04:44.370320 INFO : End of 2D read delay Voltage center optimization
816 18:04:44.422821 INFO : End of 2D write delay Voltage center optimization
817 18:04:44.472458 INFO : End of 2D write delay Voltage center optimization
818 18:04:44.478099 INFO : Training has run successfully!
819 18:04:44.478632
820 18:04:44.479040 channel==0
821 18:04:44.483636 RxClkDly_Margin_A0==88 ps 9
822 18:04:44.484192 TxDqDly_Margin_A0==98 ps 10
823 18:04:44.486922 RxClkDly_Margin_A1==88 ps 9
824 18:04:44.487414 TxDqDly_Margin_A1==98 ps 10
825 18:04:44.492522 TrainedVREFDQ_A0==74
826 18:04:44.493022 TrainedVREFDQ_A1==74
827 18:04:44.493421 VrefDac_Margin_A0==25
828 18:04:44.498150 DeviceVref_Margin_A0==40
829 18:04:44.498664 VrefDac_Margin_A1==25
830 18:04:44.503769 DeviceVref_Margin_A1==40
831 18:04:44.504321
832 18:04:44.504727
833 18:04:44.505116 channel==1
834 18:04:44.505505 RxClkDly_Margin_A0==98 ps 10
835 18:04:44.509326 TxDqDly_Margin_A0==98 ps 10
836 18:04:44.509829 RxClkDly_Margin_A1==98 ps 10
837 18:04:44.514980 TxDqDly_Margin_A1==88 ps 9
838 18:04:44.515475 TrainedVREFDQ_A0==77
839 18:04:44.515875 TrainedVREFDQ_A1==77
840 18:04:44.520542 VrefDac_Margin_A0==22
841 18:04:44.521045 DeviceVref_Margin_A0==37
842 18:04:44.526138 VrefDac_Margin_A1==22
843 18:04:44.526627 DeviceVref_Margin_A1==37
844 18:04:44.527020
845 18:04:44.531756 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
846 18:04:44.532282
847 18:04:44.559693 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000019 00000017 00000017 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000018 dram_vref_reg_value 0x 00000060
848 18:04:44.565385 2D training succeed
849 18:04:44.570954 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
850 18:04:44.571451 auto size-- 65535DDR cs0 size: 2048MB
851 18:04:44.576540 DDR cs1 size: 2048MB
852 18:04:44.577037 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
853 18:04:44.582157 cs0 DataBus test pass
854 18:04:44.582647 cs1 DataBus test pass
855 18:04:44.583043 cs0 AddrBus test pass
856 18:04:44.587810 cs1 AddrBus test pass
857 18:04:44.588372
858 18:04:44.588778 100bdlr_step_size ps== 420
859 18:04:44.589179 result report
860 18:04:44.593322 boot times 0Enable ddr reg access
861 18:04:44.600194 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
862 18:04:44.614007 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
863 18:04:45.186408 0.0;M3 CHK:0;cm4_sp_mode 0
864 18:04:45.187019 MVN_1=0x00000000
865 18:04:45.192023 MVN_2=0x00000000
866 18:04:45.197731 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
867 18:04:45.198241 OPS=0x10
868 18:04:45.198665 ring efuse init
869 18:04:45.199079 chipver efuse init
870 18:04:45.203346 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
871 18:04:45.208977 [0.018961 Inits done]
872 18:04:45.209483 secure task start!
873 18:04:45.209910 high task start!
874 18:04:45.213468 low task start!
875 18:04:45.213962 run into bl31
876 18:04:45.220183 NOTICE: BL31: v1.3(release):4fc40b1
877 18:04:45.227045 NOTICE: BL31: Built : 15:58:17, May 22 2019
878 18:04:45.227554 NOTICE: BL31: G12A normal boot!
879 18:04:45.253319 NOTICE: BL31: BL33 decompress pass
880 18:04:45.258256 ERROR: Error initializing runtime service opteed_fast
881 18:04:46.492054
882 18:04:46.492689
883 18:04:46.500350 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
884 18:04:46.500875
885 18:04:46.501306 Model: Libre Computer AML-A311D-CC Alta
886 18:04:46.708753 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
887 18:04:46.732224 DRAM: 2 GiB (effective 3.8 GiB)
888 18:04:46.875216 Core: 408 devices, 31 uclasses, devicetree: separate
889 18:04:46.881065 WDT: Not starting watchdog@f0d0
890 18:04:46.913312 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
891 18:04:46.925699 Loading Environment from FAT... Card did not respond to voltage select! : -110
892 18:04:46.930732 ** Bad device specification mmc 0 **
893 18:04:46.941167 Card did not respond to voltage select! : -110
894 18:04:46.948744 ** Bad device specification mmc 0 **
895 18:04:46.949296 Couldn't find partition mmc 0
896 18:04:46.957201 Card did not respond to voltage select! : -110
897 18:04:46.962571 ** Bad device specification mmc 0 **
898 18:04:46.963068 Couldn't find partition mmc 0
899 18:04:46.967629 Error: could not access storage.
900 18:04:47.311145 Net: eth0: ethernet@ff3f0000
901 18:04:47.311734 starting USB...
902 18:04:47.562899 Bus usb@ff500000: Register 3000140 NbrPorts 3
903 18:04:47.563417 Starting the controller
904 18:04:47.569076 USB XHCI 1.10
905 18:04:49.432284 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
906 18:04:49.432870 bl2_stage_init 0x01
907 18:04:49.433305 bl2_stage_init 0x81
908 18:04:49.437378 hw id: 0x0000 - pwm id 0x01
909 18:04:49.437852 bl2_stage_init 0xc1
910 18:04:49.438275 bl2_stage_init 0x02
911 18:04:49.438686
912 18:04:49.443010 L0:00000000
913 18:04:49.443483 L1:20000703
914 18:04:49.443898 L2:00008067
915 18:04:49.444357 L3:14000000
916 18:04:49.448670 B2:00402000
917 18:04:49.449131 B1:e0f83180
918 18:04:49.449546
919 18:04:49.449957 TE: 58124
920 18:04:49.450358
921 18:04:49.454203 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
922 18:04:49.454679
923 18:04:49.455093 Board ID = 1
924 18:04:49.459678 Set A53 clk to 24M
925 18:04:49.460189 Set A73 clk to 24M
926 18:04:49.460606 Set clk81 to 24M
927 18:04:49.465442 A53 clk: 1200 MHz
928 18:04:49.466017 A73 clk: 1200 MHz
929 18:04:49.466498 CLK81: 166.6M
930 18:04:49.466961 smccc: 00012a91
931 18:04:49.471413 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
932 18:04:49.476733 board id: 1
933 18:04:49.482537 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
934 18:04:49.493100 fw parse done
935 18:04:49.499136 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
936 18:04:49.540835 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
937 18:04:49.552560 PIEI prepare done
938 18:04:49.553084 fastboot data load
939 18:04:49.553539 fastboot data verify
940 18:04:49.558265 verify result: 266
941 18:04:49.563787 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
942 18:04:49.564360 LPDDR4 probe
943 18:04:49.564806 ddr clk to 1584MHz
944 18:04:49.571767 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
945 18:04:49.608199
946 18:04:49.608700 dmc_version 0001
947 18:04:49.615712 Check phy result
948 18:04:49.621954 INFO : End of CA training
949 18:04:49.622445 INFO : End of initialization
950 18:04:49.627223 INFO : Training has run successfully!
951 18:04:49.627832 Check phy result
952 18:04:49.632895 INFO : End of initialization
953 18:04:49.633525 INFO : End of read enable training
954 18:04:49.636094 INFO : End of fine write leveling
955 18:04:49.642138 INFO : End of Write leveling coarse delay
956 18:04:49.648416 INFO : Training has run successfully!
957 18:04:49.648950 Check phy result
958 18:04:49.649413 INFO : End of initialization
959 18:04:49.652903 INFO : End of read dq deskew training
960 18:04:49.658676 INFO : End of MPR read delay center optimization
961 18:04:49.659287 INFO : End of write delay center optimization
962 18:04:49.664094 INFO : End of read delay center optimization
963 18:04:49.669684 INFO : End of max read latency training
964 18:04:49.670225 INFO : Training has run successfully!
965 18:04:49.675228 1D training succeed
966 18:04:49.680348 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
967 18:04:49.728752 Check phy result
968 18:04:49.729302 INFO : End of initialization
969 18:04:49.750463 INFO : End of 2D read delay Voltage center optimization
970 18:04:49.769891 INFO : End of 2D read delay Voltage center optimization
971 18:04:49.821976 INFO : End of 2D write delay Voltage center optimization
972 18:04:49.871238 INFO : End of 2D write delay Voltage center optimization
973 18:04:49.876892 INFO : Training has run successfully!
974 18:04:49.877396
975 18:04:49.877865 channel==0
976 18:04:49.882520 RxClkDly_Margin_A0==88 ps 9
977 18:04:49.883054 TxDqDly_Margin_A0==98 ps 10
978 18:04:49.888173 RxClkDly_Margin_A1==88 ps 9
979 18:04:49.888683 TxDqDly_Margin_A1==98 ps 10
980 18:04:49.889147 TrainedVREFDQ_A0==74
981 18:04:49.893674 TrainedVREFDQ_A1==74
982 18:04:49.894163 VrefDac_Margin_A0==25
983 18:04:49.894614 DeviceVref_Margin_A0==40
984 18:04:49.899312 VrefDac_Margin_A1==25
985 18:04:49.899804 DeviceVref_Margin_A1==40
986 18:04:49.900296
987 18:04:49.900752
988 18:04:49.904885 channel==1
989 18:04:49.905377 RxClkDly_Margin_A0==88 ps 9
990 18:04:49.905848 TxDqDly_Margin_A0==88 ps 9
991 18:04:49.910501 RxClkDly_Margin_A1==98 ps 10
992 18:04:49.910989 TxDqDly_Margin_A1==88 ps 9
993 18:04:49.916040 TrainedVREFDQ_A0==76
994 18:04:49.916537 TrainedVREFDQ_A1==77
995 18:04:49.916992 VrefDac_Margin_A0==22
996 18:04:49.921698 DeviceVref_Margin_A0==38
997 18:04:49.922189 VrefDac_Margin_A1==23
998 18:04:49.927272 DeviceVref_Margin_A1==37
999 18:04:49.927758
1000 18:04:49.928426 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1001 18:04:49.928922
1002 18:04:49.960942 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000019 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1003 18:04:49.961536 2D training succeed
1004 18:04:49.966628 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1005 18:04:49.972094 auto size-- 65535DDR cs0 size: 2048MB
1006 18:04:49.972649 DDR cs1 size: 2048MB
1007 18:04:49.977613 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1008 18:04:49.978118 cs0 DataBus test pass
1009 18:04:49.983187 cs1 DataBus test pass
1010 18:04:49.983679 cs0 AddrBus test pass
1011 18:04:49.984173 cs1 AddrBus test pass
1012 18:04:49.984626
1013 18:04:49.988738 100bdlr_step_size ps== 420
1014 18:04:49.989244 result report
1015 18:04:49.994368 boot times 0Enable ddr reg access
1016 18:04:49.999644 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1017 18:04:50.013217 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1018 18:04:50.586781 0.0;M3 CHK:0;cm4_sp_mode 0
1019 18:04:50.587430 MVN_1=0x00000000
1020 18:04:50.592185 MVN_2=0x00000000
1021 18:04:50.597957 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1022 18:04:50.598506 OPS=0x10
1023 18:04:50.598982 ring efuse init
1024 18:04:50.599442 chipver efuse init
1025 18:04:50.603595 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1026 18:04:50.609122 [0.018961 Inits done]
1027 18:04:50.609651 secure task start!
1028 18:04:50.610111 high task start!
1029 18:04:50.613771 low task start!
1030 18:04:50.614293 run into bl31
1031 18:04:50.620405 NOTICE: BL31: v1.3(release):4fc40b1
1032 18:04:50.628195 NOTICE: BL31: Built : 15:58:17, May 22 2019
1033 18:04:50.628711 NOTICE: BL31: G12A normal boot!
1034 18:04:50.654136 NOTICE: BL31: BL33 decompress pass
1035 18:04:50.659816 ERROR: Error initializing runtime service opteed_fast
1036 18:04:51.892751
1037 18:04:51.893379
1038 18:04:51.901081 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1039 18:04:51.901576
1040 18:04:51.902035 Model: Libre Computer AML-A311D-CC Alta
1041 18:04:52.109359 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1042 18:04:52.132942 DRAM: 2 GiB (effective 3.8 GiB)
1043 18:04:52.275893 Core: 408 devices, 31 uclasses, devicetree: separate
1044 18:04:52.281723 WDT: Not starting watchdog@f0d0
1045 18:04:52.314020 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1046 18:04:52.326481 Loading Environment from FAT... Card did not respond to voltage select! : -110
1047 18:04:52.331410 ** Bad device specification mmc 0 **
1048 18:04:52.341879 Card did not respond to voltage select! : -110
1049 18:04:52.349431 ** Bad device specification mmc 0 **
1050 18:04:52.349932 Couldn't find partition mmc 0
1051 18:04:52.357869 Card did not respond to voltage select! : -110
1052 18:04:52.363292 ** Bad device specification mmc 0 **
1053 18:04:52.363786 Couldn't find partition mmc 0
1054 18:04:52.368332 Error: could not access storage.
1055 18:04:52.710921 Net: eth0: ethernet@ff3f0000
1056 18:04:52.711551 starting USB...
1057 18:04:52.962640 Bus usb@ff500000: Register 3000140 NbrPorts 3
1058 18:04:52.963264 Starting the controller
1059 18:04:52.969551 USB XHCI 1.10
1060 18:04:54.523718 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1061 18:04:54.532065 scanning usb for storage devices... 0 Storage Device(s) found
1063 18:04:54.583807 Hit any key to stop autoboot: 1
1064 18:04:54.584732 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1065 18:04:54.585345 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1066 18:04:54.585839 Setting prompt string to ['=>']
1067 18:04:54.586342 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1068 18:04:54.599479 0
1069 18:04:54.600388 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1070 18:04:54.600907 Sending with 10 millisecond of delay
1072 18:04:55.736082 => setenv autoload no
1073 18:04:55.746903 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1074 18:04:55.752254 setenv autoload no
1075 18:04:55.753038 Sending with 10 millisecond of delay
1077 18:04:57.550088 => setenv initrd_high 0xffffffff
1078 18:04:57.560876 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1079 18:04:57.561745 setenv initrd_high 0xffffffff
1080 18:04:57.562505 Sending with 10 millisecond of delay
1082 18:04:59.178682 => setenv fdt_high 0xffffffff
1083 18:04:59.189456 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1084 18:04:59.190302 setenv fdt_high 0xffffffff
1085 18:04:59.191058 Sending with 10 millisecond of delay
1087 18:04:59.482954 => dhcp
1088 18:04:59.493726 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1089 18:04:59.494587 dhcp
1090 18:04:59.495061 Speed: 1000, full duplex
1091 18:04:59.495519 BOOTP broadcast 1
1092 18:04:59.501963 DHCP client bound to address 192.168.6.27 (8 ms)
1093 18:04:59.502708 Sending with 10 millisecond of delay
1095 18:05:01.179379 => setenv serverip 192.168.6.2
1096 18:05:01.190238 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
1097 18:05:01.191167 setenv serverip 192.168.6.2
1098 18:05:01.191907 Sending with 10 millisecond of delay
1100 18:05:04.915502 => tftpboot 0x01080000 935728/tftp-deploy-w0rkgci4/kernel/uImage
1101 18:05:04.926348 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
1102 18:05:04.927209 tftpboot 0x01080000 935728/tftp-deploy-w0rkgci4/kernel/uImage
1103 18:05:04.927696 Speed: 1000, full duplex
1104 18:05:04.928209 Using ethernet@ff3f0000 device
1105 18:05:04.928999 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1106 18:05:04.934587 Filename '935728/tftp-deploy-w0rkgci4/kernel/uImage'.
1107 18:05:04.938404 Load address: 0x1080000
1108 18:05:07.328863 Loading: *####################################### UDP wrong checksum 00000005 0000c7e7
1109 18:05:07.961212 ########### 43.6 MiB
1110 18:05:07.961851 14.4 MiB/s
1111 18:05:07.962323 done
1112 18:05:07.965524 Bytes transferred = 45713984 (2b98a40 hex)
1113 18:05:07.966307 Sending with 10 millisecond of delay
1115 18:05:12.652942 => tftpboot 0x08000000 935728/tftp-deploy-w0rkgci4/ramdisk/ramdisk.cpio.gz.uboot
1116 18:05:12.663777 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1117 18:05:12.664741 tftpboot 0x08000000 935728/tftp-deploy-w0rkgci4/ramdisk/ramdisk.cpio.gz.uboot
1118 18:05:12.665228 Speed: 1000, full duplex
1119 18:05:12.665672 Using ethernet@ff3f0000 device
1120 18:05:12.666437 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1121 18:05:12.675077 Filename '935728/tftp-deploy-w0rkgci4/ramdisk/ramdisk.cpio.gz.uboot'.
1122 18:05:12.675571 Load address: 0x8000000
1123 18:05:19.551847 Loading: *##########T ####################################### UDP wrong checksum 00000005 0000b284
1124 18:05:24.553879 T UDP wrong checksum 00000005 0000b284
1125 18:05:34.555968 T T UDP wrong checksum 00000005 0000b284
1126 18:05:38.868719 UDP wrong checksum 000000ff 0000209b
1127 18:05:38.919367 UDP wrong checksum 000000ff 0000b38d
1128 18:05:54.559698 T T T T UDP wrong checksum 00000005 0000b284
1129 18:06:09.563940 T T
1130 18:06:09.564643 Retry count exceeded; starting again
1132 18:06:09.566182 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1135 18:06:09.568276 end: 2.4 uboot-commands (duration 00:01:53) [common]
1137 18:06:09.569794 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1139 18:06:09.570955 end: 2 uboot-action (duration 00:01:53) [common]
1141 18:06:09.572628 Cleaning after the job
1142 18:06:09.573222 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/935728/tftp-deploy-w0rkgci4/ramdisk
1143 18:06:09.574596 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/935728/tftp-deploy-w0rkgci4/kernel
1144 18:06:09.624611 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/935728/tftp-deploy-w0rkgci4/dtb
1145 18:06:09.625519 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/935728/tftp-deploy-w0rkgci4/modules
1146 18:06:09.654943 start: 4.1 power-off (timeout 00:00:30) [common]
1147 18:06:09.655610 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1148 18:06:09.688760 >> OK - accepted request
1149 18:06:09.690603 Returned 0 in 0 seconds
1150 18:06:09.791328 end: 4.1 power-off (duration 00:00:00) [common]
1152 18:06:09.792363 start: 4.2 read-feedback (timeout 00:10:00) [common]
1153 18:06:09.793023 Listened to connection for namespace 'common' for up to 1s
1154 18:06:10.793989 Finalising connection for namespace 'common'
1155 18:06:10.794761 Disconnecting from shell: Finalise
1156 18:06:10.795326 =>
1157 18:06:10.896302 end: 4.2 read-feedback (duration 00:00:01) [common]
1158 18:06:10.896965 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/935728
1159 18:06:11.195854 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/935728
1160 18:06:11.196455 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.