Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 18:10:11.972517 lava-dispatcher, installed at version: 2024.01
2 18:10:11.973275 start: 0 validate
3 18:10:11.973732 Start time: 2024-11-04 18:10:11.973703+00:00 (UTC)
4 18:10:11.974313 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 18:10:11.974855 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 18:10:12.027334 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 18:10:12.027864 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-98-g57d5fb99dade%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 18:10:12.059478 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 18:10:12.060109 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-98-g57d5fb99dade%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 18:10:12.093315 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 18:10:12.093814 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 18:10:12.137061 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 18:10:12.137588 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-98-g57d5fb99dade%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 18:10:12.188089 validate duration: 0.21
16 18:10:12.189572 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 18:10:12.190161 start: 1.1 download-retry (timeout 00:10:00) [common]
18 18:10:12.190739 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 18:10:12.191689 Not decompressing ramdisk as can be used compressed.
20 18:10:12.192490 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 18:10:12.193005 saving as /var/lib/lava/dispatcher/tmp/935699/tftp-deploy-5gsztoi0/ramdisk/initrd.cpio.gz
22 18:10:12.193510 total size: 5628182 (5 MB)
23 18:10:12.240473 progress 0 % (0 MB)
24 18:10:12.248336 progress 5 % (0 MB)
25 18:10:12.256102 progress 10 % (0 MB)
26 18:10:12.263068 progress 15 % (0 MB)
27 18:10:12.270655 progress 20 % (1 MB)
28 18:10:12.276892 progress 25 % (1 MB)
29 18:10:12.281146 progress 30 % (1 MB)
30 18:10:12.285779 progress 35 % (1 MB)
31 18:10:12.289588 progress 40 % (2 MB)
32 18:10:12.293761 progress 45 % (2 MB)
33 18:10:12.297612 progress 50 % (2 MB)
34 18:10:12.301752 progress 55 % (2 MB)
35 18:10:12.305950 progress 60 % (3 MB)
36 18:10:12.309663 progress 65 % (3 MB)
37 18:10:12.313699 progress 70 % (3 MB)
38 18:10:12.317345 progress 75 % (4 MB)
39 18:10:12.321533 progress 80 % (4 MB)
40 18:10:12.325379 progress 85 % (4 MB)
41 18:10:12.329355 progress 90 % (4 MB)
42 18:10:12.333105 progress 95 % (5 MB)
43 18:10:12.336447 progress 100 % (5 MB)
44 18:10:12.337161 5 MB downloaded in 0.14 s (37.37 MB/s)
45 18:10:12.337738 end: 1.1.1 http-download (duration 00:00:00) [common]
47 18:10:12.338663 end: 1.1 download-retry (duration 00:00:00) [common]
48 18:10:12.339001 start: 1.2 download-retry (timeout 00:10:00) [common]
49 18:10:12.339366 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 18:10:12.340035 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-98-g57d5fb99dade/arm64/defconfig/gcc-12/kernel/Image
51 18:10:12.340352 saving as /var/lib/lava/dispatcher/tmp/935699/tftp-deploy-5gsztoi0/kernel/Image
52 18:10:12.340568 total size: 45713920 (43 MB)
53 18:10:12.340782 No compression specified
54 18:10:12.374683 progress 0 % (0 MB)
55 18:10:12.426953 progress 5 % (2 MB)
56 18:10:12.454922 progress 10 % (4 MB)
57 18:10:12.482712 progress 15 % (6 MB)
58 18:10:12.510590 progress 20 % (8 MB)
59 18:10:12.538020 progress 25 % (10 MB)
60 18:10:12.565796 progress 30 % (13 MB)
61 18:10:12.593344 progress 35 % (15 MB)
62 18:10:12.620984 progress 40 % (17 MB)
63 18:10:12.648514 progress 45 % (19 MB)
64 18:10:12.676375 progress 50 % (21 MB)
65 18:10:12.706343 progress 55 % (24 MB)
66 18:10:12.734671 progress 60 % (26 MB)
67 18:10:12.767920 progress 65 % (28 MB)
68 18:10:12.802345 progress 70 % (30 MB)
69 18:10:12.837011 progress 75 % (32 MB)
70 18:10:12.870488 progress 80 % (34 MB)
71 18:10:12.903780 progress 85 % (37 MB)
72 18:10:12.937287 progress 90 % (39 MB)
73 18:10:12.970771 progress 95 % (41 MB)
74 18:10:13.003916 progress 100 % (43 MB)
75 18:10:13.004658 43 MB downloaded in 0.66 s (65.65 MB/s)
76 18:10:13.005252 end: 1.2.1 http-download (duration 00:00:01) [common]
78 18:10:13.006261 end: 1.2 download-retry (duration 00:00:01) [common]
79 18:10:13.006609 start: 1.3 download-retry (timeout 00:09:59) [common]
80 18:10:13.006934 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 18:10:13.007520 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-98-g57d5fb99dade/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 18:10:13.007876 saving as /var/lib/lava/dispatcher/tmp/935699/tftp-deploy-5gsztoi0/dtb/meson-g12b-a311d-libretech-cc.dtb
83 18:10:13.008162 total size: 54703 (0 MB)
84 18:10:13.008417 No compression specified
85 18:10:13.048354 progress 59 % (0 MB)
86 18:10:13.049395 progress 100 % (0 MB)
87 18:10:13.050066 0 MB downloaded in 0.04 s (1.25 MB/s)
88 18:10:13.050663 end: 1.3.1 http-download (duration 00:00:00) [common]
90 18:10:13.051663 end: 1.3 download-retry (duration 00:00:00) [common]
91 18:10:13.052008 start: 1.4 download-retry (timeout 00:09:59) [common]
92 18:10:13.052345 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 18:10:13.052916 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 18:10:13.053215 saving as /var/lib/lava/dispatcher/tmp/935699/tftp-deploy-5gsztoi0/nfsrootfs/full.rootfs.tar
95 18:10:13.053464 total size: 107552908 (102 MB)
96 18:10:13.053717 Using unxz to decompress xz
97 18:10:13.088228 progress 0 % (0 MB)
98 18:10:13.727043 progress 5 % (5 MB)
99 18:10:14.453563 progress 10 % (10 MB)
100 18:10:15.187487 progress 15 % (15 MB)
101 18:10:15.950930 progress 20 % (20 MB)
102 18:10:16.519037 progress 25 % (25 MB)
103 18:10:17.142202 progress 30 % (30 MB)
104 18:10:17.880266 progress 35 % (35 MB)
105 18:10:18.226814 progress 40 % (41 MB)
106 18:10:18.703748 progress 45 % (46 MB)
107 18:10:19.394769 progress 50 % (51 MB)
108 18:10:20.080500 progress 55 % (56 MB)
109 18:10:20.835386 progress 60 % (61 MB)
110 18:10:21.590685 progress 65 % (66 MB)
111 18:10:22.319829 progress 70 % (71 MB)
112 18:10:23.088114 progress 75 % (76 MB)
113 18:10:23.763529 progress 80 % (82 MB)
114 18:10:24.469579 progress 85 % (87 MB)
115 18:10:25.217073 progress 90 % (92 MB)
116 18:10:25.929612 progress 95 % (97 MB)
117 18:10:26.666874 progress 100 % (102 MB)
118 18:10:26.678709 102 MB downloaded in 13.63 s (7.53 MB/s)
119 18:10:26.679693 end: 1.4.1 http-download (duration 00:00:14) [common]
121 18:10:26.681559 end: 1.4 download-retry (duration 00:00:14) [common]
122 18:10:26.682129 start: 1.5 download-retry (timeout 00:09:46) [common]
123 18:10:26.682699 start: 1.5.1 http-download (timeout 00:09:46) [common]
124 18:10:26.683676 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-98-g57d5fb99dade/arm64/defconfig/gcc-12/modules.tar.xz
125 18:10:26.684301 saving as /var/lib/lava/dispatcher/tmp/935699/tftp-deploy-5gsztoi0/modules/modules.tar
126 18:10:26.684758 total size: 11616108 (11 MB)
127 18:10:26.685221 Using unxz to decompress xz
128 18:10:26.731007 progress 0 % (0 MB)
129 18:10:26.797576 progress 5 % (0 MB)
130 18:10:26.871689 progress 10 % (1 MB)
131 18:10:26.967623 progress 15 % (1 MB)
132 18:10:27.059793 progress 20 % (2 MB)
133 18:10:27.139457 progress 25 % (2 MB)
134 18:10:27.217374 progress 30 % (3 MB)
135 18:10:27.298956 progress 35 % (3 MB)
136 18:10:27.372654 progress 40 % (4 MB)
137 18:10:27.448640 progress 45 % (5 MB)
138 18:10:27.534265 progress 50 % (5 MB)
139 18:10:27.614923 progress 55 % (6 MB)
140 18:10:27.700466 progress 60 % (6 MB)
141 18:10:27.781810 progress 65 % (7 MB)
142 18:10:27.862512 progress 70 % (7 MB)
143 18:10:27.941736 progress 75 % (8 MB)
144 18:10:28.025901 progress 80 % (8 MB)
145 18:10:28.105956 progress 85 % (9 MB)
146 18:10:28.190075 progress 90 % (10 MB)
147 18:10:28.265032 progress 95 % (10 MB)
148 18:10:28.342647 progress 100 % (11 MB)
149 18:10:28.355030 11 MB downloaded in 1.67 s (6.63 MB/s)
150 18:10:28.355674 end: 1.5.1 http-download (duration 00:00:02) [common]
152 18:10:28.356580 end: 1.5 download-retry (duration 00:00:02) [common]
153 18:10:28.356867 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
154 18:10:28.357150 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
155 18:10:37.935205 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/935699/extract-nfsrootfs-5yjbb4tu
156 18:10:37.935818 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 18:10:37.936146 start: 1.6.2 lava-overlay (timeout 00:09:34) [common]
158 18:10:37.936756 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo
159 18:10:37.937197 makedir: /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin
160 18:10:37.937532 makedir: /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/tests
161 18:10:37.937873 makedir: /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/results
162 18:10:37.938217 Creating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin/lava-add-keys
163 18:10:37.938749 Creating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin/lava-add-sources
164 18:10:37.939260 Creating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin/lava-background-process-start
165 18:10:37.939761 Creating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin/lava-background-process-stop
166 18:10:37.940353 Creating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin/lava-common-functions
167 18:10:37.940867 Creating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin/lava-echo-ipv4
168 18:10:37.941359 Creating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin/lava-install-packages
169 18:10:37.941852 Creating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin/lava-installed-packages
170 18:10:37.942338 Creating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin/lava-os-build
171 18:10:37.942839 Creating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin/lava-probe-channel
172 18:10:37.943338 Creating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin/lava-probe-ip
173 18:10:37.943830 Creating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin/lava-target-ip
174 18:10:37.944359 Creating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin/lava-target-mac
175 18:10:37.944853 Creating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin/lava-target-storage
176 18:10:37.945354 Creating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin/lava-test-case
177 18:10:37.945843 Creating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin/lava-test-event
178 18:10:37.946324 Creating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin/lava-test-feedback
179 18:10:37.946809 Creating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin/lava-test-raise
180 18:10:37.947294 Creating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin/lava-test-reference
181 18:10:37.947781 Creating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin/lava-test-runner
182 18:10:37.948325 Creating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin/lava-test-set
183 18:10:37.948818 Creating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin/lava-test-shell
184 18:10:37.949321 Updating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin/lava-install-packages (oe)
185 18:10:37.949865 Updating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/bin/lava-installed-packages (oe)
186 18:10:37.950321 Creating /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/environment
187 18:10:37.950707 LAVA metadata
188 18:10:37.950972 - LAVA_JOB_ID=935699
189 18:10:37.951190 - LAVA_DISPATCHER_IP=192.168.6.2
190 18:10:37.951568 start: 1.6.2.1 ssh-authorize (timeout 00:09:34) [common]
191 18:10:37.952588 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 18:10:37.952918 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:34) [common]
193 18:10:37.953128 skipped lava-vland-overlay
194 18:10:37.953370 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 18:10:37.953630 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:34) [common]
196 18:10:37.953852 skipped lava-multinode-overlay
197 18:10:37.954096 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 18:10:37.954352 start: 1.6.2.4 test-definition (timeout 00:09:34) [common]
199 18:10:37.954605 Loading test definitions
200 18:10:37.954885 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:34) [common]
201 18:10:37.955108 Using /lava-935699 at stage 0
202 18:10:37.956450 uuid=935699_1.6.2.4.1 testdef=None
203 18:10:37.956781 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 18:10:37.957050 start: 1.6.2.4.2 test-overlay (timeout 00:09:34) [common]
205 18:10:37.958917 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 18:10:37.959722 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:34) [common]
208 18:10:37.962072 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 18:10:37.962925 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:34) [common]
211 18:10:37.965163 runner path: /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/0/tests/0_dmesg test_uuid 935699_1.6.2.4.1
212 18:10:37.965741 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 18:10:37.966509 Creating lava-test-runner.conf files
215 18:10:37.966714 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/935699/lava-overlay-u7ydghxo/lava-935699/0 for stage 0
216 18:10:37.967067 - 0_dmesg
217 18:10:37.967418 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 18:10:37.967697 start: 1.6.2.5 compress-overlay (timeout 00:09:34) [common]
219 18:10:37.989388 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 18:10:37.989822 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:34) [common]
221 18:10:37.990090 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 18:10:37.990360 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 18:10:37.990625 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
224 18:10:38.619884 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 18:10:38.620386 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
226 18:10:38.620634 extracting modules file /var/lib/lava/dispatcher/tmp/935699/tftp-deploy-5gsztoi0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/935699/extract-nfsrootfs-5yjbb4tu
227 18:10:40.008120 extracting modules file /var/lib/lava/dispatcher/tmp/935699/tftp-deploy-5gsztoi0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/935699/extract-overlay-ramdisk-w3qrlxz1/ramdisk
228 18:10:41.447572 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 18:10:41.448121 start: 1.6.5 apply-overlay-tftp (timeout 00:09:31) [common]
230 18:10:41.448447 [common] Applying overlay to NFS
231 18:10:41.448676 [common] Applying overlay /var/lib/lava/dispatcher/tmp/935699/compress-overlay-m87f9gu7/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/935699/extract-nfsrootfs-5yjbb4tu
232 18:10:41.480088 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 18:10:41.480559 start: 1.6.6 prepare-kernel (timeout 00:09:31) [common]
234 18:10:41.480836 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:31) [common]
235 18:10:41.481074 Converting downloaded kernel to a uImage
236 18:10:41.481411 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/935699/tftp-deploy-5gsztoi0/kernel/Image /var/lib/lava/dispatcher/tmp/935699/tftp-deploy-5gsztoi0/kernel/uImage
237 18:10:42.053860 output: Image Name:
238 18:10:42.054300 output: Created: Mon Nov 4 18:10:41 2024
239 18:10:42.054513 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 18:10:42.054720 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 18:10:42.054923 output: Load Address: 01080000
242 18:10:42.055124 output: Entry Point: 01080000
243 18:10:42.055324 output:
244 18:10:42.055664 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
245 18:10:42.055939 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
246 18:10:42.056256 start: 1.6.7 configure-preseed-file (timeout 00:09:30) [common]
247 18:10:42.056521 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 18:10:42.056784 start: 1.6.8 compress-ramdisk (timeout 00:09:30) [common]
249 18:10:42.057044 Building ramdisk /var/lib/lava/dispatcher/tmp/935699/extract-overlay-ramdisk-w3qrlxz1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/935699/extract-overlay-ramdisk-w3qrlxz1/ramdisk
250 18:10:44.493933 >> 166823 blocks
251 18:10:52.238389 Adding RAMdisk u-boot header.
252 18:10:52.238830 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/935699/extract-overlay-ramdisk-w3qrlxz1/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/935699/extract-overlay-ramdisk-w3qrlxz1/ramdisk.cpio.gz.uboot
253 18:10:52.482790 output: Image Name:
254 18:10:52.483207 output: Created: Mon Nov 4 18:10:52 2024
255 18:10:52.483420 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 18:10:52.483625 output: Data Size: 23433217 Bytes = 22884.00 KiB = 22.35 MiB
257 18:10:52.483827 output: Load Address: 00000000
258 18:10:52.484167 output: Entry Point: 00000000
259 18:10:52.484616 output:
260 18:10:52.485787 rename /var/lib/lava/dispatcher/tmp/935699/extract-overlay-ramdisk-w3qrlxz1/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/935699/tftp-deploy-5gsztoi0/ramdisk/ramdisk.cpio.gz.uboot
261 18:10:52.486562 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 18:10:52.487158 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
263 18:10:52.487741 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
264 18:10:52.488292 No LXC device requested
265 18:10:52.488850 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 18:10:52.489412 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
267 18:10:52.489954 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 18:10:52.490405 Checking files for TFTP limit of 4294967296 bytes.
269 18:10:52.493357 end: 1 tftp-deploy (duration 00:00:40) [common]
270 18:10:52.493983 start: 2 uboot-action (timeout 00:05:00) [common]
271 18:10:52.494558 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 18:10:52.495104 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 18:10:52.495651 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 18:10:52.496255 Using kernel file from prepare-kernel: 935699/tftp-deploy-5gsztoi0/kernel/uImage
275 18:10:52.496941 substitutions:
276 18:10:52.497395 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 18:10:52.497842 - {DTB_ADDR}: 0x01070000
278 18:10:52.498279 - {DTB}: 935699/tftp-deploy-5gsztoi0/dtb/meson-g12b-a311d-libretech-cc.dtb
279 18:10:52.498721 - {INITRD}: 935699/tftp-deploy-5gsztoi0/ramdisk/ramdisk.cpio.gz.uboot
280 18:10:52.499159 - {KERNEL_ADDR}: 0x01080000
281 18:10:52.499592 - {KERNEL}: 935699/tftp-deploy-5gsztoi0/kernel/uImage
282 18:10:52.500061 - {LAVA_MAC}: None
283 18:10:52.500549 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/935699/extract-nfsrootfs-5yjbb4tu
284 18:10:52.500988 - {NFS_SERVER_IP}: 192.168.6.2
285 18:10:52.501422 - {PRESEED_CONFIG}: None
286 18:10:52.501855 - {PRESEED_LOCAL}: None
287 18:10:52.502286 - {RAMDISK_ADDR}: 0x08000000
288 18:10:52.502714 - {RAMDISK}: 935699/tftp-deploy-5gsztoi0/ramdisk/ramdisk.cpio.gz.uboot
289 18:10:52.503142 - {ROOT_PART}: None
290 18:10:52.503576 - {ROOT}: None
291 18:10:52.504057 - {SERVER_IP}: 192.168.6.2
292 18:10:52.504499 - {TEE_ADDR}: 0x83000000
293 18:10:52.504932 - {TEE}: None
294 18:10:52.505366 Parsed boot commands:
295 18:10:52.505786 - setenv autoload no
296 18:10:52.506218 - setenv initrd_high 0xffffffff
297 18:10:52.506647 - setenv fdt_high 0xffffffff
298 18:10:52.507076 - dhcp
299 18:10:52.507506 - setenv serverip 192.168.6.2
300 18:10:52.507932 - tftpboot 0x01080000 935699/tftp-deploy-5gsztoi0/kernel/uImage
301 18:10:52.508391 - tftpboot 0x08000000 935699/tftp-deploy-5gsztoi0/ramdisk/ramdisk.cpio.gz.uboot
302 18:10:52.508822 - tftpboot 0x01070000 935699/tftp-deploy-5gsztoi0/dtb/meson-g12b-a311d-libretech-cc.dtb
303 18:10:52.509254 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/935699/extract-nfsrootfs-5yjbb4tu,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 18:10:52.509698 - bootm 0x01080000 0x08000000 0x01070000
305 18:10:52.510245 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 18:10:52.511883 start: 2.3 connect-device (timeout 00:05:00) [common]
308 18:10:52.512394 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 18:10:52.527414 Setting prompt string to ['lava-test: # ']
310 18:10:52.529056 end: 2.3 connect-device (duration 00:00:00) [common]
311 18:10:52.529704 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 18:10:52.530294 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 18:10:52.530861 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 18:10:52.532358 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 18:10:52.570390 >> OK - accepted request
316 18:10:52.572591 Returned 0 in 0 seconds
317 18:10:52.673751 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 18:10:52.675470 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 18:10:52.676140 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 18:10:52.676728 Setting prompt string to ['Hit any key to stop autoboot']
322 18:10:52.677241 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 18:10:52.678951 Trying 192.168.56.21...
324 18:10:52.679475 Connected to conserv1.
325 18:10:52.679937 Escape character is '^]'.
326 18:10:52.680430
327 18:10:52.680897 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 18:10:52.681358
329 18:11:03.862383 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 18:11:03.863017 bl2_stage_init 0x01
331 18:11:03.863427 bl2_stage_init 0x81
332 18:11:03.867808 hw id: 0x0000 - pwm id 0x01
333 18:11:03.868354 bl2_stage_init 0xc1
334 18:11:03.868761 bl2_stage_init 0x02
335 18:11:03.869163
336 18:11:03.873352 L0:00000000
337 18:11:03.873793 L1:20000703
338 18:11:03.874194 L2:00008067
339 18:11:03.874580 L3:14000000
340 18:11:03.878971 B2:00402000
341 18:11:03.879504 B1:e0f83180
342 18:11:03.879936
343 18:11:03.880379 TE: 58124
344 18:11:03.880782
345 18:11:03.884511 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 18:11:03.884968
347 18:11:03.885369 Board ID = 1
348 18:11:03.890170 Set A53 clk to 24M
349 18:11:03.890600 Set A73 clk to 24M
350 18:11:03.890994 Set clk81 to 24M
351 18:11:03.895700 A53 clk: 1200 MHz
352 18:11:03.896151 A73 clk: 1200 MHz
353 18:11:03.896544 CLK81: 166.6M
354 18:11:03.896928 smccc: 00012a92
355 18:11:03.901286 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 18:11:03.906951 board id: 1
357 18:11:03.912991 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 18:11:03.923388 fw parse done
359 18:11:03.929319 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 18:11:03.971971 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 18:11:03.982875 PIEI prepare done
362 18:11:03.983335 fastboot data load
363 18:11:03.983780 fastboot data verify
364 18:11:03.988461 verify result: 266
365 18:11:03.994104 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 18:11:03.994605 LPDDR4 probe
367 18:11:03.995010 ddr clk to 1584MHz
368 18:11:04.002041 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 18:11:04.039420
370 18:11:04.040065 dmc_version 0001
371 18:11:04.046072 Check phy result
372 18:11:04.051942 INFO : End of CA training
373 18:11:04.052502 INFO : End of initialization
374 18:11:04.057547 INFO : Training has run successfully!
375 18:11:04.058144 Check phy result
376 18:11:04.063138 INFO : End of initialization
377 18:11:04.063747 INFO : End of read enable training
378 18:11:04.068684 INFO : End of fine write leveling
379 18:11:04.074312 INFO : End of Write leveling coarse delay
380 18:11:04.074829 INFO : Training has run successfully!
381 18:11:04.075229 Check phy result
382 18:11:04.079880 INFO : End of initialization
383 18:11:04.080487 INFO : End of read dq deskew training
384 18:11:04.085500 INFO : End of MPR read delay center optimization
385 18:11:04.091054 INFO : End of write delay center optimization
386 18:11:04.096631 INFO : End of read delay center optimization
387 18:11:04.097108 INFO : End of max read latency training
388 18:11:04.102203 INFO : Training has run successfully!
389 18:11:04.102630 1D training succeed
390 18:11:04.111391 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 18:11:04.159095 Check phy result
392 18:11:04.159672 INFO : End of initialization
393 18:11:04.180613 INFO : End of 2D read delay Voltage center optimization
394 18:11:04.199934 INFO : End of 2D read delay Voltage center optimization
395 18:11:04.251865 INFO : End of 2D write delay Voltage center optimization
396 18:11:04.301070 INFO : End of 2D write delay Voltage center optimization
397 18:11:04.306604 INFO : Training has run successfully!
398 18:11:04.307121
399 18:11:04.307570 channel==0
400 18:11:04.312367 RxClkDly_Margin_A0==88 ps 9
401 18:11:04.312864 TxDqDly_Margin_A0==98 ps 10
402 18:11:04.317912 RxClkDly_Margin_A1==88 ps 9
403 18:11:04.318419 TxDqDly_Margin_A1==98 ps 10
404 18:11:04.318851 TrainedVREFDQ_A0==74
405 18:11:04.323518 TrainedVREFDQ_A1==74
406 18:11:04.324033 VrefDac_Margin_A0==25
407 18:11:04.324444 DeviceVref_Margin_A0==40
408 18:11:04.329100 VrefDac_Margin_A1==25
409 18:11:04.329599 DeviceVref_Margin_A1==40
410 18:11:04.330058
411 18:11:04.330504
412 18:11:04.334820 channel==1
413 18:11:04.335319 RxClkDly_Margin_A0==88 ps 9
414 18:11:04.335734 TxDqDly_Margin_A0==98 ps 10
415 18:11:04.340350 RxClkDly_Margin_A1==88 ps 9
416 18:11:04.340842 TxDqDly_Margin_A1==98 ps 10
417 18:11:04.345933 TrainedVREFDQ_A0==77
418 18:11:04.346429 TrainedVREFDQ_A1==78
419 18:11:04.346840 VrefDac_Margin_A0==22
420 18:11:04.351528 DeviceVref_Margin_A0==37
421 18:11:04.352036 VrefDac_Margin_A1==24
422 18:11:04.357119 DeviceVref_Margin_A1==36
423 18:11:04.357635
424 18:11:04.358085 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 18:11:04.358525
426 18:11:04.390725 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 18:11:04.391537 2D training succeed
428 18:11:04.396312 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 18:11:04.401884 auto size-- 65535DDR cs0 size: 2048MB
430 18:11:04.402507 DDR cs1 size: 2048MB
431 18:11:04.407507 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 18:11:04.408186 cs0 DataBus test pass
433 18:11:04.413145 cs1 DataBus test pass
434 18:11:04.413760 cs0 AddrBus test pass
435 18:11:04.414281 cs1 AddrBus test pass
436 18:11:04.414789
437 18:11:04.418699 100bdlr_step_size ps== 420
438 18:11:04.419302 result report
439 18:11:04.424311 boot times 0Enable ddr reg access
440 18:11:04.429601 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 18:11:04.443112 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 18:11:05.015174 0.0;M3 CHK:0;cm4_sp_mode 0
443 18:11:05.016072 MVN_1=0x00000000
444 18:11:05.020552 MVN_2=0x00000000
445 18:11:05.026258 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 18:11:05.026885 OPS=0x10
447 18:11:05.027447 ring efuse init
448 18:11:05.028016 chipver efuse init
449 18:11:05.034526 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 18:11:05.035163 [0.018961 Inits done]
451 18:11:05.042112 secure task start!
452 18:11:05.042737 high task start!
453 18:11:05.043268 low task start!
454 18:11:05.043811 run into bl31
455 18:11:05.048729 NOTICE: BL31: v1.3(release):4fc40b1
456 18:11:05.056562 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 18:11:05.057211 NOTICE: BL31: G12A normal boot!
458 18:11:05.082535 NOTICE: BL31: BL33 decompress pass
459 18:11:05.088210 ERROR: Error initializing runtime service opteed_fast
460 18:11:06.321163
461 18:11:06.321991
462 18:11:06.329464 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 18:11:06.330142
464 18:11:06.330730 Model: Libre Computer AML-A311D-CC Alta
465 18:11:06.537949 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 18:11:06.561355 DRAM: 2 GiB (effective 3.8 GiB)
467 18:11:06.704386 Core: 408 devices, 31 uclasses, devicetree: separate
468 18:11:06.710030 WDT: Not starting watchdog@f0d0
469 18:11:06.746455 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 18:11:06.754834 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 18:11:06.764253 ** Bad device specification mmc 0 **
472 18:11:06.770257 Card did not respond to voltage select! : -110
473 18:11:06.777788 ** Bad device specification mmc 0 **
474 18:11:06.778466 Couldn't find partition mmc 0
475 18:11:06.786087 Card did not respond to voltage select! : -110
476 18:11:06.791601 ** Bad device specification mmc 0 **
477 18:11:06.792276 Couldn't find partition mmc 0
478 18:11:06.796611 Error: could not access storage.
479 18:11:08.062727 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 18:11:08.063834 bl2_stage_init 0x01
481 18:11:08.064485 bl2_stage_init 0x81
482 18:11:08.068179 hw id: 0x0000 - pwm id 0x01
483 18:11:08.069079 bl2_stage_init 0xc1
484 18:11:08.069696 bl2_stage_init 0x02
485 18:11:08.070271
486 18:11:08.073805 L0:00000000
487 18:11:08.074775 L1:20000703
488 18:11:08.075331 L2:00008067
489 18:11:08.075874 L3:14000000
490 18:11:08.080393 B2:00402000
491 18:11:08.081097 B1:e0f83180
492 18:11:08.081645
493 18:11:08.082194 TE: 58167
494 18:11:08.082773
495 18:11:08.085007 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 18:11:08.085965
497 18:11:08.086596 Board ID = 1
498 18:11:08.090546 Set A53 clk to 24M
499 18:11:08.091224 Set A73 clk to 24M
500 18:11:08.091773 Set clk81 to 24M
501 18:11:08.096199 A53 clk: 1200 MHz
502 18:11:08.096676 A73 clk: 1200 MHz
503 18:11:08.096919 CLK81: 166.6M
504 18:11:08.097179 smccc: 00012abd
505 18:11:08.101883 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 18:11:08.107479 board id: 1
507 18:11:08.113224 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 18:11:08.124093 fw parse done
509 18:11:08.129848 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 18:11:08.172454 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 18:11:08.183417 PIEI prepare done
512 18:11:08.183924 fastboot data load
513 18:11:08.184425 fastboot data verify
514 18:11:08.189012 verify result: 266
515 18:11:08.194647 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 18:11:08.195285 LPDDR4 probe
517 18:11:08.195733 ddr clk to 1584MHz
518 18:11:08.202645 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 18:11:08.239866
520 18:11:08.240493 dmc_version 0001
521 18:11:08.246487 Check phy result
522 18:11:08.252329 INFO : End of CA training
523 18:11:08.252824 INFO : End of initialization
524 18:11:08.257928 INFO : Training has run successfully!
525 18:11:08.258431 Check phy result
526 18:11:08.263609 INFO : End of initialization
527 18:11:08.264135 INFO : End of read enable training
528 18:11:08.269255 INFO : End of fine write leveling
529 18:11:08.275343 INFO : End of Write leveling coarse delay
530 18:11:08.276255 INFO : Training has run successfully!
531 18:11:08.276884 Check phy result
532 18:11:08.280495 INFO : End of initialization
533 18:11:08.281072 INFO : End of read dq deskew training
534 18:11:08.286797 INFO : End of MPR read delay center optimization
535 18:11:08.291762 INFO : End of write delay center optimization
536 18:11:08.297250 INFO : End of read delay center optimization
537 18:11:08.297971 INFO : End of max read latency training
538 18:11:08.302975 INFO : Training has run successfully!
539 18:11:08.303506 1D training succeed
540 18:11:08.311968 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 18:11:08.359682 Check phy result
542 18:11:08.360322 INFO : End of initialization
543 18:11:08.381371 INFO : End of 2D read delay Voltage center optimization
544 18:11:08.400782 INFO : End of 2D read delay Voltage center optimization
545 18:11:08.452835 INFO : End of 2D write delay Voltage center optimization
546 18:11:08.502293 INFO : End of 2D write delay Voltage center optimization
547 18:11:08.507808 INFO : Training has run successfully!
548 18:11:08.508410
549 18:11:08.508868 channel==0
550 18:11:08.513425 RxClkDly_Margin_A0==88 ps 9
551 18:11:08.513956 TxDqDly_Margin_A0==98 ps 10
552 18:11:08.518988 RxClkDly_Margin_A1==88 ps 9
553 18:11:08.519466 TxDqDly_Margin_A1==98 ps 10
554 18:11:08.519888 TrainedVREFDQ_A0==74
555 18:11:08.524588 TrainedVREFDQ_A1==74
556 18:11:08.525159 VrefDac_Margin_A0==25
557 18:11:08.525595 DeviceVref_Margin_A0==40
558 18:11:08.530159 VrefDac_Margin_A1==25
559 18:11:08.530729 DeviceVref_Margin_A1==40
560 18:11:08.531264
561 18:11:08.531791
562 18:11:08.535681 channel==1
563 18:11:08.536278 RxClkDly_Margin_A0==88 ps 9
564 18:11:08.536771 TxDqDly_Margin_A0==98 ps 10
565 18:11:08.541293 RxClkDly_Margin_A1==88 ps 9
566 18:11:08.541828 TxDqDly_Margin_A1==88 ps 9
567 18:11:08.546864 TrainedVREFDQ_A0==77
568 18:11:08.547440 TrainedVREFDQ_A1==77
569 18:11:08.547927 VrefDac_Margin_A0==23
570 18:11:08.552476 DeviceVref_Margin_A0==37
571 18:11:08.552975 VrefDac_Margin_A1==24
572 18:11:08.558091 DeviceVref_Margin_A1==37
573 18:11:08.558563
574 18:11:08.559106 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 18:11:08.559627
576 18:11:08.591672 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
577 18:11:08.592414 2D training succeed
578 18:11:08.597385 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 18:11:08.603566 auto size-- 65535DDR cs0 size: 2048MB
580 18:11:08.604277 DDR cs1 size: 2048MB
581 18:11:08.608552 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 18:11:08.609230 cs0 DataBus test pass
583 18:11:08.614102 cs1 DataBus test pass
584 18:11:08.614703 cs0 AddrBus test pass
585 18:11:08.615223 cs1 AddrBus test pass
586 18:11:08.615731
587 18:11:08.619687 100bdlr_step_size ps== 420
588 18:11:08.620321 result report
589 18:11:08.625306 boot times 0Enable ddr reg access
590 18:11:08.630557 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 18:11:08.644045 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 18:11:09.217211 0.0;M3 CHK:0;cm4_sp_mode 0
593 18:11:09.218044 MVN_1=0x00000000
594 18:11:09.222654 MVN_2=0x00000000
595 18:11:09.228415 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 18:11:09.229031 OPS=0x10
597 18:11:09.229566 ring efuse init
598 18:11:09.230087 chipver efuse init
599 18:11:09.234083 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 18:11:09.239781 [0.018961 Inits done]
601 18:11:09.240574 secure task start!
602 18:11:09.241097 high task start!
603 18:11:09.244167 low task start!
604 18:11:09.244727 run into bl31
605 18:11:09.250729 NOTICE: BL31: v1.3(release):4fc40b1
606 18:11:09.258737 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 18:11:09.259300 NOTICE: BL31: G12A normal boot!
608 18:11:09.283969 NOTICE: BL31: BL33 decompress pass
609 18:11:09.289722 ERROR: Error initializing runtime service opteed_fast
610 18:11:10.522612
611 18:11:10.523151
612 18:11:10.530957 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 18:11:10.531313
614 18:11:10.531555 Model: Libre Computer AML-A311D-CC Alta
615 18:11:10.739555 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 18:11:10.762943 DRAM: 2 GiB (effective 3.8 GiB)
617 18:11:10.905893 Core: 408 devices, 31 uclasses, devicetree: separate
618 18:11:10.911858 WDT: Not starting watchdog@f0d0
619 18:11:10.944072 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 18:11:10.956509 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 18:11:10.961686 ** Bad device specification mmc 0 **
622 18:11:10.971916 Card did not respond to voltage select! : -110
623 18:11:10.979475 ** Bad device specification mmc 0 **
624 18:11:10.980100 Couldn't find partition mmc 0
625 18:11:10.987765 Card did not respond to voltage select! : -110
626 18:11:10.993224 ** Bad device specification mmc 0 **
627 18:11:10.993533 Couldn't find partition mmc 0
628 18:11:10.998320 Error: could not access storage.
629 18:11:11.340865 Net: eth0: ethernet@ff3f0000
630 18:11:11.341280 starting USB...
631 18:11:11.592750 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 18:11:11.593176 Starting the controller
633 18:11:11.599606 USB XHCI 1.10
634 18:11:13.314602 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
635 18:11:13.315294 bl2_stage_init 0x81
636 18:11:13.320153 hw id: 0x0000 - pwm id 0x01
637 18:11:13.320691 bl2_stage_init 0xc1
638 18:11:13.321152 bl2_stage_init 0x02
639 18:11:13.321604
640 18:11:13.325696 L0:00000000
641 18:11:13.326188 L1:20000703
642 18:11:13.326639 L2:00008067
643 18:11:13.327085 L3:14000000
644 18:11:13.327526 B2:00402000
645 18:11:13.328599 B1:e0f83180
646 18:11:13.329116
647 18:11:13.329572 TE: 58150
648 18:11:13.330018
649 18:11:13.339622 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
650 18:11:13.340160
651 18:11:13.340619 Board ID = 1
652 18:11:13.341063 Set A53 clk to 24M
653 18:11:13.341502 Set A73 clk to 24M
654 18:11:13.345174 Set clk81 to 24M
655 18:11:13.345662 A53 clk: 1200 MHz
656 18:11:13.346109 A73 clk: 1200 MHz
657 18:11:13.350750 CLK81: 166.6M
658 18:11:13.351230 smccc: 00012aab
659 18:11:13.356433 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
660 18:11:13.356926 board id: 1
661 18:11:13.365106 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
662 18:11:13.375621 fw parse done
663 18:11:13.381787 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
664 18:11:13.424168 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
665 18:11:13.435190 PIEI prepare done
666 18:11:13.435798 fastboot data load
667 18:11:13.436318 fastboot data verify
668 18:11:13.440687 verify result: 266
669 18:11:13.446227 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
670 18:11:13.446728 LPDDR4 probe
671 18:11:13.447186 ddr clk to 1584MHz
672 18:11:13.454186 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
673 18:11:13.491600
674 18:11:13.492174 dmc_version 0001
675 18:11:13.498211 Check phy result
676 18:11:13.504228 INFO : End of CA training
677 18:11:13.504754 INFO : End of initialization
678 18:11:13.509656 INFO : Training has run successfully!
679 18:11:13.510149 Check phy result
680 18:11:13.515269 INFO : End of initialization
681 18:11:13.515766 INFO : End of read enable training
682 18:11:13.520880 INFO : End of fine write leveling
683 18:11:13.526486 INFO : End of Write leveling coarse delay
684 18:11:13.527007 INFO : Training has run successfully!
685 18:11:13.527465 Check phy result
686 18:11:13.532168 INFO : End of initialization
687 18:11:13.532673 INFO : End of read dq deskew training
688 18:11:13.537685 INFO : End of MPR read delay center optimization
689 18:11:13.543264 INFO : End of write delay center optimization
690 18:11:13.548875 INFO : End of read delay center optimization
691 18:11:13.549380 INFO : End of max read latency training
692 18:11:13.554507 INFO : Training has run successfully!
693 18:11:13.555014 1D training succeed
694 18:11:13.563678 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 18:11:13.611285 Check phy result
696 18:11:13.611829 INFO : End of initialization
697 18:11:13.632951 INFO : End of 2D read delay Voltage center optimization
698 18:11:13.653025 INFO : End of 2D read delay Voltage center optimization
699 18:11:13.704886 INFO : End of 2D write delay Voltage center optimization
700 18:11:13.754274 INFO : End of 2D write delay Voltage center optimization
701 18:11:13.759770 INFO : Training has run successfully!
702 18:11:13.760348
703 18:11:13.760830 channel==0
704 18:11:13.765343 RxClkDly_Margin_A0==88 ps 9
705 18:11:13.765865 TxDqDly_Margin_A0==98 ps 10
706 18:11:13.770937 RxClkDly_Margin_A1==88 ps 9
707 18:11:13.771451 TxDqDly_Margin_A1==98 ps 10
708 18:11:13.771910 TrainedVREFDQ_A0==74
709 18:11:13.776522 TrainedVREFDQ_A1==74
710 18:11:13.777042 VrefDac_Margin_A0==25
711 18:11:13.777495 DeviceVref_Margin_A0==40
712 18:11:13.782166 VrefDac_Margin_A1==25
713 18:11:13.782682 DeviceVref_Margin_A1==40
714 18:11:13.783133
715 18:11:13.783579
716 18:11:13.787775 channel==1
717 18:11:13.788323 RxClkDly_Margin_A0==98 ps 10
718 18:11:13.788775 TxDqDly_Margin_A0==98 ps 10
719 18:11:13.793349 RxClkDly_Margin_A1==98 ps 10
720 18:11:13.793858 TxDqDly_Margin_A1==98 ps 10
721 18:11:13.798965 TrainedVREFDQ_A0==77
722 18:11:13.799482 TrainedVREFDQ_A1==78
723 18:11:13.799931 VrefDac_Margin_A0==22
724 18:11:13.804538 DeviceVref_Margin_A0==37
725 18:11:13.805052 VrefDac_Margin_A1==22
726 18:11:13.810101 DeviceVref_Margin_A1==36
727 18:11:13.810599
728 18:11:13.811047 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
729 18:11:13.815877
730 18:11:13.843744 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
731 18:11:13.844335 2D training succeed
732 18:11:13.849326 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
733 18:11:13.854943 auto size-- 65535DDR cs0 size: 2048MB
734 18:11:13.855461 DDR cs1 size: 2048MB
735 18:11:13.860564 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
736 18:11:13.861086 cs0 DataBus test pass
737 18:11:13.866186 cs1 DataBus test pass
738 18:11:13.866728 cs0 AddrBus test pass
739 18:11:13.867184 cs1 AddrBus test pass
740 18:11:13.867630
741 18:11:13.871734 100bdlr_step_size ps== 420
742 18:11:13.872294 result report
743 18:11:13.877297 boot times 0Enable ddr reg access
744 18:11:13.882796 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
745 18:11:13.896304 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
746 18:11:14.468466 0.0;M3 CHK:0;cm4_sp_mode 0
747 18:11:14.469129 MVN_1=0x00000000
748 18:11:14.473734 MVN_2=0x00000000
749 18:11:14.479531 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
750 18:11:14.480169 OPS=0x10
751 18:11:14.480629 ring efuse init
752 18:11:14.481067 chipver efuse init
753 18:11:14.485075 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
754 18:11:14.490642 [0.018960 Inits done]
755 18:11:14.491109 secure task start!
756 18:11:14.491553 high task start!
757 18:11:14.495246 low task start!
758 18:11:14.495707 run into bl31
759 18:11:14.501927 NOTICE: BL31: v1.3(release):4fc40b1
760 18:11:14.509742 NOTICE: BL31: Built : 15:58:17, May 22 2019
761 18:11:14.510228 NOTICE: BL31: G12A normal boot!
762 18:11:14.535151 NOTICE: BL31: BL33 decompress pass
763 18:11:14.540784 ERROR: Error initializing runtime service opteed_fast
764 18:11:15.773754
765 18:11:15.774419
766 18:11:15.782140 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
767 18:11:15.782732
768 18:11:15.783205 Model: Libre Computer AML-A311D-CC Alta
769 18:11:15.990626 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
770 18:11:16.013899 DRAM: 2 GiB (effective 3.8 GiB)
771 18:11:16.157230 Core: 408 devices, 31 uclasses, devicetree: separate
772 18:11:16.162742 WDT: Not starting watchdog@f0d0
773 18:11:16.195139 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
774 18:11:16.207591 Loading Environment from FAT... Card did not respond to voltage select! : -110
775 18:11:16.212537 ** Bad device specification mmc 0 **
776 18:11:16.222833 Card did not respond to voltage select! : -110
777 18:11:16.230562 ** Bad device specification mmc 0 **
778 18:11:16.231054 Couldn't find partition mmc 0
779 18:11:16.238776 Card did not respond to voltage select! : -110
780 18:11:16.244283 ** Bad device specification mmc 0 **
781 18:11:16.244781 Couldn't find partition mmc 0
782 18:11:16.249324 Error: could not access storage.
783 18:11:16.593274 Net: eth0: ethernet@ff3f0000
784 18:11:16.593930 starting USB...
785 18:11:16.844801 Bus usb@ff500000: Register 3000140 NbrPorts 3
786 18:11:16.845455 Starting the controller
787 18:11:16.851694 USB XHCI 1.10
788 18:11:18.973229 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
789 18:11:18.973957 bl2_stage_init 0x01
790 18:11:18.974571 bl2_stage_init 0x81
791 18:11:18.978369 hw id: 0x0000 - pwm id 0x01
792 18:11:18.979020 bl2_stage_init 0xc1
793 18:11:18.979480 bl2_stage_init 0x02
794 18:11:18.979931
795 18:11:18.984891 L0:00000000
796 18:11:18.985450 L1:20000703
797 18:11:18.985858 L2:00008067
798 18:11:18.986253 L3:14000000
799 18:11:18.990296 B2:00402000
800 18:11:18.990897 B1:e0f83180
801 18:11:18.991348
802 18:11:18.991790 TE: 58167
803 18:11:18.992287
804 18:11:18.999822 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
805 18:11:19.000432
806 18:11:19.000663 Board ID = 1
807 18:11:19.001158 Set A53 clk to 24M
808 18:11:19.001409 Set A73 clk to 24M
809 18:11:19.001617 Set clk81 to 24M
810 18:11:19.006220 A53 clk: 1200 MHz
811 18:11:19.006507 A73 clk: 1200 MHz
812 18:11:19.006717 CLK81: 166.6M
813 18:11:19.006919 smccc: 00012abe
814 18:11:19.011798 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
815 18:11:19.017371 board id: 1
816 18:11:19.023255 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
817 18:11:19.034007 fw parse done
818 18:11:19.039967 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
819 18:11:19.082575 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
820 18:11:19.093471 PIEI prepare done
821 18:11:19.093817 fastboot data load
822 18:11:19.094038 fastboot data verify
823 18:11:19.099099 verify result: 266
824 18:11:19.104684 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
825 18:11:19.104972 LPDDR4 probe
826 18:11:19.105191 ddr clk to 1584MHz
827 18:11:19.112672 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
828 18:11:19.150057
829 18:11:19.150413 dmc_version 0001
830 18:11:19.156670 Check phy result
831 18:11:19.162508 INFO : End of CA training
832 18:11:19.162843 INFO : End of initialization
833 18:11:19.168061 INFO : Training has run successfully!
834 18:11:19.168349 Check phy result
835 18:11:19.173685 INFO : End of initialization
836 18:11:19.173970 INFO : End of read enable training
837 18:11:19.179289 INFO : End of fine write leveling
838 18:11:19.184890 INFO : End of Write leveling coarse delay
839 18:11:19.185173 INFO : Training has run successfully!
840 18:11:19.185391 Check phy result
841 18:11:19.190477 INFO : End of initialization
842 18:11:19.190768 INFO : End of read dq deskew training
843 18:11:19.196084 INFO : End of MPR read delay center optimization
844 18:11:19.201668 INFO : End of write delay center optimization
845 18:11:19.207257 INFO : End of read delay center optimization
846 18:11:19.207546 INFO : End of max read latency training
847 18:11:19.212882 INFO : Training has run successfully!
848 18:11:19.213171 1D training succeed
849 18:11:19.222092 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 18:11:19.269858 Check phy result
851 18:11:19.270238 INFO : End of initialization
852 18:11:19.291489 INFO : End of 2D read delay Voltage center optimization
853 18:11:19.310829 INFO : End of 2D read delay Voltage center optimization
854 18:11:19.361906 INFO : End of 2D write delay Voltage center optimization
855 18:11:19.412294 INFO : End of 2D write delay Voltage center optimization
856 18:11:19.417763 INFO : Training has run successfully!
857 18:11:19.418071
858 18:11:19.418308 channel==0
859 18:11:19.423316 RxClkDly_Margin_A0==88 ps 9
860 18:11:19.423596 TxDqDly_Margin_A0==98 ps 10
861 18:11:19.428972 RxClkDly_Margin_A1==88 ps 9
862 18:11:19.429563 TxDqDly_Margin_A1==98 ps 10
863 18:11:19.430022 TrainedVREFDQ_A0==74
864 18:11:19.434550 TrainedVREFDQ_A1==74
865 18:11:19.435046 VrefDac_Margin_A0==25
866 18:11:19.435492 DeviceVref_Margin_A0==40
867 18:11:19.440246 VrefDac_Margin_A1==25
868 18:11:19.440735 DeviceVref_Margin_A1==40
869 18:11:19.441176
870 18:11:19.441612
871 18:11:19.445869 channel==1
872 18:11:19.446360 RxClkDly_Margin_A0==98 ps 10
873 18:11:19.446801 TxDqDly_Margin_A0==98 ps 10
874 18:11:19.451364 RxClkDly_Margin_A1==88 ps 9
875 18:11:19.451848 TxDqDly_Margin_A1==88 ps 9
876 18:11:19.456940 TrainedVREFDQ_A0==77
877 18:11:19.457427 TrainedVREFDQ_A1==77
878 18:11:19.457870 VrefDac_Margin_A0==23
879 18:11:19.462853 DeviceVref_Margin_A0==37
880 18:11:19.463337 VrefDac_Margin_A1==24
881 18:11:19.468248 DeviceVref_Margin_A1==37
882 18:11:19.468732
883 18:11:19.469168 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
884 18:11:19.469603
885 18:11:19.501759 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000019 00000017 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
886 18:11:19.502284 2D training succeed
887 18:11:19.507332 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
888 18:11:19.513002 auto size-- 65535DDR cs0 size: 2048MB
889 18:11:19.513494 DDR cs1 size: 2048MB
890 18:11:19.518544 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
891 18:11:19.519020 cs0 DataBus test pass
892 18:11:19.524234 cs1 DataBus test pass
893 18:11:19.524709 cs0 AddrBus test pass
894 18:11:19.525138 cs1 AddrBus test pass
895 18:11:19.525562
896 18:11:19.529781 100bdlr_step_size ps== 420
897 18:11:19.530269 result report
898 18:11:19.535346 boot times 0Enable ddr reg access
899 18:11:19.540702 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
900 18:11:19.554152 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
901 18:11:20.127417 0.0;M3 CHK:0;cm4_sp_mode 0
902 18:11:20.128104 MVN_1=0x00000000
903 18:11:20.132725 MVN_2=0x00000000
904 18:11:20.138463 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
905 18:11:20.138965 OPS=0x10
906 18:11:20.139429 ring efuse init
907 18:11:20.139878 chipver efuse init
908 18:11:20.144073 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
909 18:11:20.149668 [0.018961 Inits done]
910 18:11:20.150163 secure task start!
911 18:11:20.150617 high task start!
912 18:11:20.154236 low task start!
913 18:11:20.154722 run into bl31
914 18:11:20.160855 NOTICE: BL31: v1.3(release):4fc40b1
915 18:11:20.168770 NOTICE: BL31: Built : 15:58:17, May 22 2019
916 18:11:20.169287 NOTICE: BL31: G12A normal boot!
917 18:11:20.194273 NOTICE: BL31: BL33 decompress pass
918 18:11:20.199728 ERROR: Error initializing runtime service opteed_fast
919 18:11:21.432748
920 18:11:21.433380
921 18:11:21.441022 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
922 18:11:21.441531
923 18:11:21.441996 Model: Libre Computer AML-A311D-CC Alta
924 18:11:21.649677 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
925 18:11:21.672872 DRAM: 2 GiB (effective 3.8 GiB)
926 18:11:21.815855 Core: 408 devices, 31 uclasses, devicetree: separate
927 18:11:21.821660 WDT: Not starting watchdog@f0d0
928 18:11:21.853955 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
929 18:11:21.866391 Loading Environment from FAT... Card did not respond to voltage select! : -110
930 18:11:21.871323 ** Bad device specification mmc 0 **
931 18:11:21.881684 Card did not respond to voltage select! : -110
932 18:11:21.889319 ** Bad device specification mmc 0 **
933 18:11:21.889806 Couldn't find partition mmc 0
934 18:11:21.897696 Card did not respond to voltage select! : -110
935 18:11:21.903186 ** Bad device specification mmc 0 **
936 18:11:21.903668 Couldn't find partition mmc 0
937 18:11:21.908239 Error: could not access storage.
938 18:11:22.251789 Net: eth0: ethernet@ff3f0000
939 18:11:22.252456 starting USB...
940 18:11:22.503703 Bus usb@ff500000: Register 3000140 NbrPorts 3
941 18:11:22.504386 Starting the controller
942 18:11:22.510601 USB XHCI 1.10
943 18:11:24.372861 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
944 18:11:24.373526 bl2_stage_init 0x01
945 18:11:24.373996 bl2_stage_init 0x81
946 18:11:24.378285 hw id: 0x0000 - pwm id 0x01
947 18:11:24.378776 bl2_stage_init 0xc1
948 18:11:24.379235 bl2_stage_init 0x02
949 18:11:24.379680
950 18:11:24.383959 L0:00000000
951 18:11:24.384480 L1:20000703
952 18:11:24.384931 L2:00008067
953 18:11:24.385374 L3:14000000
954 18:11:24.386864 B2:00402000
955 18:11:24.387337 B1:e0f83180
956 18:11:24.387780
957 18:11:24.388267 TE: 58159
958 18:11:24.388719
959 18:11:24.398056 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
960 18:11:24.398561
961 18:11:24.399016 Board ID = 1
962 18:11:24.399460 Set A53 clk to 24M
963 18:11:24.399898 Set A73 clk to 24M
964 18:11:24.403625 Set clk81 to 24M
965 18:11:24.404137 A53 clk: 1200 MHz
966 18:11:24.404589 A73 clk: 1200 MHz
967 18:11:24.407095 CLK81: 166.6M
968 18:11:24.407579 smccc: 00012ab5
969 18:11:24.412576 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
970 18:11:24.418146 board id: 1
971 18:11:24.423462 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
972 18:11:24.433964 fw parse done
973 18:11:24.439921 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
974 18:11:24.482616 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
975 18:11:24.493545 PIEI prepare done
976 18:11:24.494108 fastboot data load
977 18:11:24.494543 fastboot data verify
978 18:11:24.499065 verify result: 266
979 18:11:24.504709 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
980 18:11:24.505180 LPDDR4 probe
981 18:11:24.505606 ddr clk to 1584MHz
982 18:11:24.512680 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
983 18:11:24.549997
984 18:11:24.550490 dmc_version 0001
985 18:11:24.556686 Check phy result
986 18:11:24.562571 INFO : End of CA training
987 18:11:24.563043 INFO : End of initialization
988 18:11:24.568150 INFO : Training has run successfully!
989 18:11:24.568615 Check phy result
990 18:11:24.573696 INFO : End of initialization
991 18:11:24.574154 INFO : End of read enable training
992 18:11:24.576994 INFO : End of fine write leveling
993 18:11:24.582525 INFO : End of Write leveling coarse delay
994 18:11:24.588146 INFO : Training has run successfully!
995 18:11:24.588603 Check phy result
996 18:11:24.589031 INFO : End of initialization
997 18:11:24.593718 INFO : End of read dq deskew training
998 18:11:24.597192 INFO : End of MPR read delay center optimization
999 18:11:24.602786 INFO : End of write delay center optimization
1000 18:11:24.608316 INFO : End of read delay center optimization
1001 18:11:24.608772 INFO : End of max read latency training
1002 18:11:24.613956 INFO : Training has run successfully!
1003 18:11:24.614414 1D training succeed
1004 18:11:24.622104 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 18:11:24.669731 Check phy result
1006 18:11:24.670324 INFO : End of initialization
1007 18:11:24.691385 INFO : End of 2D read delay Voltage center optimization
1008 18:11:24.711640 INFO : End of 2D read delay Voltage center optimization
1009 18:11:24.763430 INFO : End of 2D write delay Voltage center optimization
1010 18:11:24.813346 INFO : End of 2D write delay Voltage center optimization
1011 18:11:24.818652 INFO : Training has run successfully!
1012 18:11:24.819131
1013 18:11:24.819585 channel==0
1014 18:11:24.824318 RxClkDly_Margin_A0==88 ps 9
1015 18:11:24.824819 TxDqDly_Margin_A0==98 ps 10
1016 18:11:24.830204 RxClkDly_Margin_A1==88 ps 9
1017 18:11:24.830684 TxDqDly_Margin_A1==98 ps 10
1018 18:11:24.831132 TrainedVREFDQ_A0==74
1019 18:11:24.835598 TrainedVREFDQ_A1==74
1020 18:11:24.836106 VrefDac_Margin_A0==25
1021 18:11:24.836564 DeviceVref_Margin_A0==40
1022 18:11:24.841217 VrefDac_Margin_A1==25
1023 18:11:24.841697 DeviceVref_Margin_A1==40
1024 18:11:24.842139
1025 18:11:24.842577
1026 18:11:24.846751 channel==1
1027 18:11:24.847231 RxClkDly_Margin_A0==88 ps 9
1028 18:11:24.847677 TxDqDly_Margin_A0==98 ps 10
1029 18:11:24.852434 RxClkDly_Margin_A1==98 ps 10
1030 18:11:24.852926 TxDqDly_Margin_A1==88 ps 9
1031 18:11:24.857787 TrainedVREFDQ_A0==77
1032 18:11:24.858274 TrainedVREFDQ_A1==77
1033 18:11:24.858724 VrefDac_Margin_A0==22
1034 18:11:24.863585 DeviceVref_Margin_A0==37
1035 18:11:24.864093 VrefDac_Margin_A1==22
1036 18:11:24.868967 DeviceVref_Margin_A1==37
1037 18:11:24.869453
1038 18:11:24.869898 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1039 18:11:24.870341
1040 18:11:24.902575 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1041 18:11:24.903121 2D training succeed
1042 18:11:24.908193 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1043 18:11:24.913709 auto size-- 65535DDR cs0 size: 2048MB
1044 18:11:24.914195 DDR cs1 size: 2048MB
1045 18:11:24.919346 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1046 18:11:24.919823 cs0 DataBus test pass
1047 18:11:24.924945 cs1 DataBus test pass
1048 18:11:24.925438 cs0 AddrBus test pass
1049 18:11:24.925886 cs1 AddrBus test pass
1050 18:11:24.926326
1051 18:11:24.930543 100bdlr_step_size ps== 420
1052 18:11:24.931032 result report
1053 18:11:24.936150 boot times 0Enable ddr reg access
1054 18:11:24.940587 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1055 18:11:24.954980 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1056 18:11:25.528849 0.0;M3 CHK:0;cm4_sp_mode 0
1057 18:11:25.529531 MVN_1=0x00000000
1058 18:11:25.534192 MVN_2=0x00000000
1059 18:11:25.539955 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1060 18:11:25.540488 OPS=0x10
1061 18:11:25.540943 ring efuse init
1062 18:11:25.541386 chipver efuse init
1063 18:11:25.545543 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1064 18:11:25.551143 [0.018960 Inits done]
1065 18:11:25.551617 secure task start!
1066 18:11:25.552098 high task start!
1067 18:11:25.555744 low task start!
1068 18:11:25.556253 run into bl31
1069 18:11:25.562408 NOTICE: BL31: v1.3(release):4fc40b1
1070 18:11:25.570203 NOTICE: BL31: Built : 15:58:17, May 22 2019
1071 18:11:25.570694 NOTICE: BL31: G12A normal boot!
1072 18:11:25.596254 NOTICE: BL31: BL33 decompress pass
1073 18:11:25.601772 ERROR: Error initializing runtime service opteed_fast
1074 18:11:26.834950
1075 18:11:26.835383
1076 18:11:26.843175 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1077 18:11:26.843585
1078 18:11:26.843804 Model: Libre Computer AML-A311D-CC Alta
1079 18:11:27.051627 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1080 18:11:27.075000 DRAM: 2 GiB (effective 3.8 GiB)
1081 18:11:27.217928 Core: 408 devices, 31 uclasses, devicetree: separate
1082 18:11:27.222809 WDT: Not starting watchdog@f0d0
1083 18:11:27.256165 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1084 18:11:27.268548 Loading Environment from FAT... Card did not respond to voltage select! : -110
1085 18:11:27.273471 ** Bad device specification mmc 0 **
1086 18:11:27.283802 Card did not respond to voltage select! : -110
1087 18:11:27.291436 ** Bad device specification mmc 0 **
1088 18:11:27.291922 Couldn't find partition mmc 0
1089 18:11:27.299780 Card did not respond to voltage select! : -110
1090 18:11:27.305332 ** Bad device specification mmc 0 **
1091 18:11:27.305779 Couldn't find partition mmc 0
1092 18:11:27.310372 Error: could not access storage.
1093 18:11:27.652829 Net: eth0: ethernet@ff3f0000
1094 18:11:27.653327 starting USB...
1095 18:11:27.904750 Bus usb@ff500000: Register 3000140 NbrPorts 3
1096 18:11:27.905229 Starting the controller
1097 18:11:27.911625 USB XHCI 1.10
1098 18:11:29.468729 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1099 18:11:29.477017 scanning usb for storage devices... 0 Storage Device(s) found
1101 18:11:29.528538 Hit any key to stop autoboot: 1
1102 18:11:29.529327 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1103 18:11:29.529953 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1104 18:11:29.530447 Setting prompt string to ['=>']
1105 18:11:29.530917 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1106 18:11:29.544513 0
1107 18:11:29.545397 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1108 18:11:29.545908 Sending with 10 millisecond of delay
1110 18:11:30.680272 => setenv autoload no
1111 18:11:30.690956 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1112 18:11:30.695872 setenv autoload no
1113 18:11:30.696627 Sending with 10 millisecond of delay
1115 18:11:32.493125 => setenv initrd_high 0xffffffff
1116 18:11:32.503908 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1117 18:11:32.504789 setenv initrd_high 0xffffffff
1118 18:11:32.505503 Sending with 10 millisecond of delay
1120 18:11:34.121942 => setenv fdt_high 0xffffffff
1121 18:11:34.133262 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1122 18:11:34.134608 setenv fdt_high 0xffffffff
1123 18:11:34.135741 Sending with 10 millisecond of delay
1125 18:11:34.428458 => dhcp
1126 18:11:34.439616 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1127 18:11:34.441024 dhcp
1128 18:11:34.441752 Speed: 1000, full duplex
1129 18:11:34.442505 BOOTP broadcast 1
1130 18:11:34.455655 DHCP client bound to address 192.168.6.27 (16 ms)
1131 18:11:34.456795 Sending with 10 millisecond of delay
1133 18:11:36.133540 => setenv serverip 192.168.6.2
1134 18:11:36.144336 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1135 18:11:36.145257 setenv serverip 192.168.6.2
1136 18:11:36.145945 Sending with 10 millisecond of delay
1138 18:11:39.867689 => tftpboot 0x01080000 935699/tftp-deploy-5gsztoi0/kernel/uImage
1139 18:11:39.878515 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1140 18:11:39.879323 tftpboot 0x01080000 935699/tftp-deploy-5gsztoi0/kernel/uImage
1141 18:11:39.879773 Speed: 1000, full duplex
1142 18:11:39.880221 Using ethernet@ff3f0000 device
1143 18:11:39.881017 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1144 18:11:39.886553 Filename '935699/tftp-deploy-5gsztoi0/kernel/uImage'.
1145 18:11:39.890465 Load address: 0x1080000
1146 18:11:42.796314 Loading: *################################################## 43.6 MiB
1147 18:11:42.797010 15 MiB/s
1148 18:11:42.797501 done
1149 18:11:42.800730 Bytes transferred = 45713984 (2b98a40 hex)
1150 18:11:42.801645 Sending with 10 millisecond of delay
1152 18:11:47.492548 => tftpboot 0x08000000 935699/tftp-deploy-5gsztoi0/ramdisk/ramdisk.cpio.gz.uboot
1153 18:11:47.503305 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1154 18:11:47.503814 tftpboot 0x08000000 935699/tftp-deploy-5gsztoi0/ramdisk/ramdisk.cpio.gz.uboot
1155 18:11:47.504150 Speed: 1000, full duplex
1156 18:11:47.504584 Using ethernet@ff3f0000 device
1157 18:11:47.505964 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1158 18:11:47.514647 Filename '935699/tftp-deploy-5gsztoi0/ramdisk/ramdisk.cpio.gz.uboot'.
1159 18:11:47.515148 Load address: 0x8000000
1160 18:11:53.054373 Loading: *#################T # UDP wrong checksum 000000ff 0000f054
1161 18:11:53.111478 # UDP wrong checksum 000000ff 00008147
1162 18:11:54.559136 ############################## UDP wrong checksum 00000005 0000efea
1163 18:11:59.560715 T UDP wrong checksum 00000005 0000efea
1164 18:12:00.099431 UDP wrong checksum 000000ff 000088be
1165 18:12:00.106645 UDP wrong checksum 000000ff 000016b1
1166 18:12:09.563701 T T UDP wrong checksum 00000005 0000efea
1167 18:12:15.908466 T UDP wrong checksum 000000ff 00000ab3
1168 18:12:15.939429 UDP wrong checksum 000000ff 000093a5
1169 18:12:26.758031 T T UDP wrong checksum 000000ff 00009628
1170 18:12:26.807374 UDP wrong checksum 000000ff 00002f1b
1171 18:12:29.567680 T UDP wrong checksum 00000005 0000efea
1172 18:12:44.571741 T T
1173 18:12:44.572213 Retry count exceeded; starting again
1175 18:12:44.575124 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1178 18:12:44.576089 end: 2.4 uboot-commands (duration 00:01:52) [common]
1180 18:12:44.576797 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1182 18:12:44.577329 end: 2 uboot-action (duration 00:01:52) [common]
1184 18:12:44.578118 Cleaning after the job
1185 18:12:44.578427 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/935699/tftp-deploy-5gsztoi0/ramdisk
1186 18:12:44.579185 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/935699/tftp-deploy-5gsztoi0/kernel
1187 18:12:44.604560 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/935699/tftp-deploy-5gsztoi0/dtb
1188 18:12:44.605329 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/935699/tftp-deploy-5gsztoi0/nfsrootfs
1189 18:12:44.747746 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/935699/tftp-deploy-5gsztoi0/modules
1190 18:12:44.766487 start: 4.1 power-off (timeout 00:00:30) [common]
1191 18:12:44.767108 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1192 18:12:44.803404 >> OK - accepted request
1193 18:12:44.805263 Returned 0 in 0 seconds
1194 18:12:44.905978 end: 4.1 power-off (duration 00:00:00) [common]
1196 18:12:44.906909 start: 4.2 read-feedback (timeout 00:10:00) [common]
1197 18:12:44.907548 Listened to connection for namespace 'common' for up to 1s
1198 18:12:45.908534 Finalising connection for namespace 'common'
1199 18:12:45.909020 Disconnecting from shell: Finalise
1200 18:12:45.909310 =>
1201 18:12:46.009969 end: 4.2 read-feedback (duration 00:00:01) [common]
1202 18:12:46.010382 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/935699
1203 18:12:47.682626 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/935699
1204 18:12:47.683252 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.