Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 7
- Errors: 0
- Boot result: PASS
- Kernel Errors: 6
1 19:03:13.838242 lava-dispatcher, installed at version: 2024.01
2 19:03:13.839026 start: 0 validate
3 19:03:13.839521 Start time: 2024-11-04 19:03:13.839491+00:00 (UTC)
4 19:03:13.840069 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 19:03:13.840623 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 19:03:13.879724 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 19:03:13.880294 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-98-g57d5fb99dade%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 19:03:13.909349 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 19:03:13.909969 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-98-g57d5fb99dade%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 19:03:13.941904 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 19:03:13.942411 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 19:03:13.973297 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 19:03:13.973782 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-98-g57d5fb99dade%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 19:03:14.008429 validate duration: 0.17
16 19:03:14.009291 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:03:14.009631 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:03:14.009955 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:03:14.010543 Not decompressing ramdisk as can be used compressed.
20 19:03:14.011001 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 19:03:14.011301 saving as /var/lib/lava/dispatcher/tmp/935712/tftp-deploy-1sxpfpx3/ramdisk/initrd.cpio.gz
22 19:03:14.011581 total size: 5628169 (5 MB)
23 19:03:14.050214 progress 0 % (0 MB)
24 19:03:14.058143 progress 5 % (0 MB)
25 19:03:14.066339 progress 10 % (0 MB)
26 19:03:14.072843 progress 15 % (0 MB)
27 19:03:14.077202 progress 20 % (1 MB)
28 19:03:14.081037 progress 25 % (1 MB)
29 19:03:14.085279 progress 30 % (1 MB)
30 19:03:14.089554 progress 35 % (1 MB)
31 19:03:14.093192 progress 40 % (2 MB)
32 19:03:14.097274 progress 45 % (2 MB)
33 19:03:14.101222 progress 50 % (2 MB)
34 19:03:14.105336 progress 55 % (2 MB)
35 19:03:14.109464 progress 60 % (3 MB)
36 19:03:14.113048 progress 65 % (3 MB)
37 19:03:14.117195 progress 70 % (3 MB)
38 19:03:14.120816 progress 75 % (4 MB)
39 19:03:14.124741 progress 80 % (4 MB)
40 19:03:14.128339 progress 85 % (4 MB)
41 19:03:14.132364 progress 90 % (4 MB)
42 19:03:14.136228 progress 95 % (5 MB)
43 19:03:14.139480 progress 100 % (5 MB)
44 19:03:14.140143 5 MB downloaded in 0.13 s (41.75 MB/s)
45 19:03:14.140686 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:03:14.141574 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:03:14.141867 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:03:14.142138 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:03:14.142679 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-98-g57d5fb99dade/arm64/defconfig/gcc-12/kernel/Image
51 19:03:14.142939 saving as /var/lib/lava/dispatcher/tmp/935712/tftp-deploy-1sxpfpx3/kernel/Image
52 19:03:14.143151 total size: 45713920 (43 MB)
53 19:03:14.143361 No compression specified
54 19:03:14.181993 progress 0 % (0 MB)
55 19:03:14.217256 progress 5 % (2 MB)
56 19:03:14.252621 progress 10 % (4 MB)
57 19:03:14.287759 progress 15 % (6 MB)
58 19:03:14.322820 progress 20 % (8 MB)
59 19:03:14.351324 progress 25 % (10 MB)
60 19:03:14.380527 progress 30 % (13 MB)
61 19:03:14.409611 progress 35 % (15 MB)
62 19:03:14.438707 progress 40 % (17 MB)
63 19:03:14.466766 progress 45 % (19 MB)
64 19:03:14.495318 progress 50 % (21 MB)
65 19:03:14.524560 progress 55 % (24 MB)
66 19:03:14.553821 progress 60 % (26 MB)
67 19:03:14.582412 progress 65 % (28 MB)
68 19:03:14.611583 progress 70 % (30 MB)
69 19:03:14.640549 progress 75 % (32 MB)
70 19:03:14.668995 progress 80 % (34 MB)
71 19:03:14.697794 progress 85 % (37 MB)
72 19:03:14.726838 progress 90 % (39 MB)
73 19:03:14.756210 progress 95 % (41 MB)
74 19:03:14.785288 progress 100 % (43 MB)
75 19:03:14.785800 43 MB downloaded in 0.64 s (67.84 MB/s)
76 19:03:14.786309 end: 1.2.1 http-download (duration 00:00:01) [common]
78 19:03:14.787171 end: 1.2 download-retry (duration 00:00:01) [common]
79 19:03:14.787457 start: 1.3 download-retry (timeout 00:09:59) [common]
80 19:03:14.787725 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 19:03:14.788233 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-98-g57d5fb99dade/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 19:03:14.788522 saving as /var/lib/lava/dispatcher/tmp/935712/tftp-deploy-1sxpfpx3/dtb/meson-g12b-a311d-libretech-cc.dtb
83 19:03:14.788734 total size: 54703 (0 MB)
84 19:03:14.788943 No compression specified
85 19:03:14.833761 progress 59 % (0 MB)
86 19:03:14.835145 progress 100 % (0 MB)
87 19:03:14.835710 0 MB downloaded in 0.05 s (1.11 MB/s)
88 19:03:14.836215 end: 1.3.1 http-download (duration 00:00:00) [common]
90 19:03:14.837047 end: 1.3 download-retry (duration 00:00:00) [common]
91 19:03:14.837309 start: 1.4 download-retry (timeout 00:09:59) [common]
92 19:03:14.837572 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 19:03:14.838024 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 19:03:14.838265 saving as /var/lib/lava/dispatcher/tmp/935712/tftp-deploy-1sxpfpx3/nfsrootfs/full.rootfs.tar
95 19:03:14.838470 total size: 120894716 (115 MB)
96 19:03:14.838681 Using unxz to decompress xz
97 19:03:14.874219 progress 0 % (0 MB)
98 19:03:15.660820 progress 5 % (5 MB)
99 19:03:16.496395 progress 10 % (11 MB)
100 19:03:17.286389 progress 15 % (17 MB)
101 19:03:18.042710 progress 20 % (23 MB)
102 19:03:18.633892 progress 25 % (28 MB)
103 19:03:19.455618 progress 30 % (34 MB)
104 19:03:20.247870 progress 35 % (40 MB)
105 19:03:20.626735 progress 40 % (46 MB)
106 19:03:21.004546 progress 45 % (51 MB)
107 19:03:21.751740 progress 50 % (57 MB)
108 19:03:22.632909 progress 55 % (63 MB)
109 19:03:23.413808 progress 60 % (69 MB)
110 19:03:24.182888 progress 65 % (74 MB)
111 19:03:24.984690 progress 70 % (80 MB)
112 19:03:25.816541 progress 75 % (86 MB)
113 19:03:26.659719 progress 80 % (92 MB)
114 19:03:27.729314 progress 85 % (98 MB)
115 19:03:28.609415 progress 90 % (103 MB)
116 19:03:29.420996 progress 95 % (109 MB)
117 19:03:30.273411 progress 100 % (115 MB)
118 19:03:30.285902 115 MB downloaded in 15.45 s (7.46 MB/s)
119 19:03:30.286837 end: 1.4.1 http-download (duration 00:00:15) [common]
121 19:03:30.288640 end: 1.4 download-retry (duration 00:00:15) [common]
122 19:03:30.289201 start: 1.5 download-retry (timeout 00:09:44) [common]
123 19:03:30.289757 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 19:03:30.290641 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-98-g57d5fb99dade/arm64/defconfig/gcc-12/modules.tar.xz
125 19:03:30.291154 saving as /var/lib/lava/dispatcher/tmp/935712/tftp-deploy-1sxpfpx3/modules/modules.tar
126 19:03:30.291594 total size: 11616108 (11 MB)
127 19:03:30.292133 Using unxz to decompress xz
128 19:03:30.337858 progress 0 % (0 MB)
129 19:03:30.403934 progress 5 % (0 MB)
130 19:03:30.477884 progress 10 % (1 MB)
131 19:03:30.574258 progress 15 % (1 MB)
132 19:03:30.668229 progress 20 % (2 MB)
133 19:03:30.749191 progress 25 % (2 MB)
134 19:03:30.824728 progress 30 % (3 MB)
135 19:03:30.903242 progress 35 % (3 MB)
136 19:03:30.976079 progress 40 % (4 MB)
137 19:03:31.052006 progress 45 % (5 MB)
138 19:03:31.136522 progress 50 % (5 MB)
139 19:03:31.213784 progress 55 % (6 MB)
140 19:03:31.298862 progress 60 % (6 MB)
141 19:03:31.379851 progress 65 % (7 MB)
142 19:03:31.462133 progress 70 % (7 MB)
143 19:03:31.547247 progress 75 % (8 MB)
144 19:03:31.638033 progress 80 % (8 MB)
145 19:03:31.717957 progress 85 % (9 MB)
146 19:03:31.801993 progress 90 % (10 MB)
147 19:03:31.874986 progress 95 % (10 MB)
148 19:03:31.951137 progress 100 % (11 MB)
149 19:03:31.963223 11 MB downloaded in 1.67 s (6.63 MB/s)
150 19:03:31.964217 end: 1.5.1 http-download (duration 00:00:02) [common]
152 19:03:31.966027 end: 1.5 download-retry (duration 00:00:02) [common]
153 19:03:31.966602 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 19:03:31.967168 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 19:03:48.284160 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/935712/extract-nfsrootfs-36sgurkv
156 19:03:48.284766 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 19:03:48.285051 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 19:03:48.285867 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep
159 19:03:48.286324 makedir: /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin
160 19:03:48.286655 makedir: /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/tests
161 19:03:48.286968 makedir: /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/results
162 19:03:48.287301 Creating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-add-keys
163 19:03:48.287831 Creating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-add-sources
164 19:03:48.288374 Creating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-background-process-start
165 19:03:48.288870 Creating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-background-process-stop
166 19:03:48.289378 Creating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-common-functions
167 19:03:48.289860 Creating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-echo-ipv4
168 19:03:48.290333 Creating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-install-packages
169 19:03:48.290795 Creating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-installed-packages
170 19:03:48.291251 Creating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-os-build
171 19:03:48.291746 Creating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-probe-channel
172 19:03:48.292281 Creating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-probe-ip
173 19:03:48.292755 Creating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-target-ip
174 19:03:48.293218 Creating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-target-mac
175 19:03:48.293680 Creating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-target-storage
176 19:03:48.294150 Creating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-test-case
177 19:03:48.294679 Creating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-test-event
178 19:03:48.295150 Creating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-test-feedback
179 19:03:48.295640 Creating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-test-raise
180 19:03:48.296149 Creating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-test-reference
181 19:03:48.296629 Creating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-test-runner
182 19:03:48.297099 Creating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-test-set
183 19:03:48.297562 Creating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-test-shell
184 19:03:48.298055 Updating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-add-keys (debian)
185 19:03:48.298575 Updating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-add-sources (debian)
186 19:03:48.299064 Updating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-install-packages (debian)
187 19:03:48.299547 Updating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-installed-packages (debian)
188 19:03:48.300043 Updating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/bin/lava-os-build (debian)
189 19:03:48.300476 Creating /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/environment
190 19:03:48.300835 LAVA metadata
191 19:03:48.301088 - LAVA_JOB_ID=935712
192 19:03:48.301301 - LAVA_DISPATCHER_IP=192.168.6.2
193 19:03:48.301657 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 19:03:48.302584 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 19:03:48.302886 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 19:03:48.303094 skipped lava-vland-overlay
197 19:03:48.303332 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 19:03:48.303583 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 19:03:48.303798 skipped lava-multinode-overlay
200 19:03:48.304060 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 19:03:48.304313 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 19:03:48.304555 Loading test definitions
203 19:03:48.304825 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 19:03:48.305042 Using /lava-935712 at stage 0
205 19:03:48.306098 uuid=935712_1.6.2.4.1 testdef=None
206 19:03:48.306397 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 19:03:48.306655 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 19:03:48.308229 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 19:03:48.309016 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 19:03:48.310905 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 19:03:48.311716 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 19:03:48.313519 runner path: /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/0/tests/0_timesync-off test_uuid 935712_1.6.2.4.1
215 19:03:48.314064 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 19:03:48.314868 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 19:03:48.315089 Using /lava-935712 at stage 0
219 19:03:48.315431 Fetching tests from https://github.com/kernelci/test-definitions.git
220 19:03:48.315715 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/0/tests/1_kselftest-alsa'
221 19:03:51.904944 Running '/usr/bin/git checkout kernelci.org
222 19:03:52.351916 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 19:03:52.354483 uuid=935712_1.6.2.4.5 testdef=None
224 19:03:52.355084 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 19:03:52.356570 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 19:03:52.361980 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 19:03:52.363552 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 19:03:52.370656 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 19:03:52.372344 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 19:03:52.379284 runner path: /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/0/tests/1_kselftest-alsa test_uuid 935712_1.6.2.4.5
234 19:03:52.379808 BOARD='meson-g12b-a311d-libretech-cc'
235 19:03:52.380257 BRANCH='pm'
236 19:03:52.380655 SKIPFILE='/dev/null'
237 19:03:52.381046 SKIP_INSTALL='True'
238 19:03:52.381429 TESTPROG_URL='http://storage.kernelci.org/pm/testing/v6.12-rc6-98-g57d5fb99dade/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 19:03:52.381820 TST_CASENAME=''
240 19:03:52.382206 TST_CMDFILES='alsa'
241 19:03:52.383197 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 19:03:52.384751 Creating lava-test-runner.conf files
244 19:03:52.385150 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/935712/lava-overlay-cpkj9fep/lava-935712/0 for stage 0
245 19:03:52.385774 - 0_timesync-off
246 19:03:52.386225 - 1_kselftest-alsa
247 19:03:52.386838 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 19:03:52.387363 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 19:04:15.727441 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 19:04:15.727890 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 19:04:15.728218 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 19:04:15.728498 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 19:04:15.728763 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 19:04:16.347651 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 19:04:16.348189 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 19:04:16.348467 extracting modules file /var/lib/lava/dispatcher/tmp/935712/tftp-deploy-1sxpfpx3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/935712/extract-nfsrootfs-36sgurkv
257 19:04:17.948831 extracting modules file /var/lib/lava/dispatcher/tmp/935712/tftp-deploy-1sxpfpx3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/935712/extract-overlay-ramdisk-hj1ccfon/ramdisk
258 19:04:19.358251 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 19:04:19.358747 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 19:04:19.359055 [common] Applying overlay to NFS
261 19:04:19.359271 [common] Applying overlay /var/lib/lava/dispatcher/tmp/935712/compress-overlay-c64z6gop/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/935712/extract-nfsrootfs-36sgurkv
262 19:04:22.098470 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 19:04:22.098957 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 19:04:22.099267 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 19:04:22.099538 Converting downloaded kernel to a uImage
266 19:04:22.099893 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/935712/tftp-deploy-1sxpfpx3/kernel/Image /var/lib/lava/dispatcher/tmp/935712/tftp-deploy-1sxpfpx3/kernel/uImage
267 19:04:22.548511 output: Image Name:
268 19:04:22.548942 output: Created: Mon Nov 4 19:04:22 2024
269 19:04:22.549153 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 19:04:22.549362 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 19:04:22.549562 output: Load Address: 01080000
272 19:04:22.549765 output: Entry Point: 01080000
273 19:04:22.549963 output:
274 19:04:22.550298 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 19:04:22.550566 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 19:04:22.550834 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 19:04:22.551092 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 19:04:22.551351 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 19:04:22.551612 Building ramdisk /var/lib/lava/dispatcher/tmp/935712/extract-overlay-ramdisk-hj1ccfon/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/935712/extract-overlay-ramdisk-hj1ccfon/ramdisk
280 19:04:24.722454 >> 166823 blocks
281 19:04:33.600183 Adding RAMdisk u-boot header.
282 19:04:33.600878 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/935712/extract-overlay-ramdisk-hj1ccfon/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/935712/extract-overlay-ramdisk-hj1ccfon/ramdisk.cpio.gz.uboot
283 19:04:33.840769 output: Image Name:
284 19:04:33.841174 output: Created: Mon Nov 4 19:04:33 2024
285 19:04:33.841383 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 19:04:33.841589 output: Data Size: 23433372 Bytes = 22884.15 KiB = 22.35 MiB
287 19:04:33.841793 output: Load Address: 00000000
288 19:04:33.841993 output: Entry Point: 00000000
289 19:04:33.842193 output:
290 19:04:33.842776 rename /var/lib/lava/dispatcher/tmp/935712/extract-overlay-ramdisk-hj1ccfon/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/935712/tftp-deploy-1sxpfpx3/ramdisk/ramdisk.cpio.gz.uboot
291 19:04:33.843198 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
292 19:04:33.843481 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 19:04:33.843754 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:40) [common]
294 19:04:33.844083 No LXC device requested
295 19:04:33.844658 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 19:04:33.845247 start: 1.8 deploy-device-env (timeout 00:08:40) [common]
297 19:04:33.845796 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 19:04:33.846248 Checking files for TFTP limit of 4294967296 bytes.
299 19:04:33.849190 end: 1 tftp-deploy (duration 00:01:20) [common]
300 19:04:33.849812 start: 2 uboot-action (timeout 00:05:00) [common]
301 19:04:33.850384 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 19:04:33.850927 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 19:04:33.851477 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 19:04:33.852082 Using kernel file from prepare-kernel: 935712/tftp-deploy-1sxpfpx3/kernel/uImage
305 19:04:33.852774 substitutions:
306 19:04:33.853226 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 19:04:33.853668 - {DTB_ADDR}: 0x01070000
308 19:04:33.854104 - {DTB}: 935712/tftp-deploy-1sxpfpx3/dtb/meson-g12b-a311d-libretech-cc.dtb
309 19:04:33.854545 - {INITRD}: 935712/tftp-deploy-1sxpfpx3/ramdisk/ramdisk.cpio.gz.uboot
310 19:04:33.854982 - {KERNEL_ADDR}: 0x01080000
311 19:04:33.855432 - {KERNEL}: 935712/tftp-deploy-1sxpfpx3/kernel/uImage
312 19:04:33.855875 - {LAVA_MAC}: None
313 19:04:33.856386 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/935712/extract-nfsrootfs-36sgurkv
314 19:04:33.856825 - {NFS_SERVER_IP}: 192.168.6.2
315 19:04:33.857255 - {PRESEED_CONFIG}: None
316 19:04:33.857683 - {PRESEED_LOCAL}: None
317 19:04:33.858110 - {RAMDISK_ADDR}: 0x08000000
318 19:04:33.858534 - {RAMDISK}: 935712/tftp-deploy-1sxpfpx3/ramdisk/ramdisk.cpio.gz.uboot
319 19:04:33.858963 - {ROOT_PART}: None
320 19:04:33.859390 - {ROOT}: None
321 19:04:33.859816 - {SERVER_IP}: 192.168.6.2
322 19:04:33.860267 - {TEE_ADDR}: 0x83000000
323 19:04:33.860694 - {TEE}: None
324 19:04:33.861119 Parsed boot commands:
325 19:04:33.861531 - setenv autoload no
326 19:04:33.861958 - setenv initrd_high 0xffffffff
327 19:04:33.862379 - setenv fdt_high 0xffffffff
328 19:04:33.862799 - dhcp
329 19:04:33.863218 - setenv serverip 192.168.6.2
330 19:04:33.863646 - tftpboot 0x01080000 935712/tftp-deploy-1sxpfpx3/kernel/uImage
331 19:04:33.864095 - tftpboot 0x08000000 935712/tftp-deploy-1sxpfpx3/ramdisk/ramdisk.cpio.gz.uboot
332 19:04:33.864530 - tftpboot 0x01070000 935712/tftp-deploy-1sxpfpx3/dtb/meson-g12b-a311d-libretech-cc.dtb
333 19:04:33.864959 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/935712/extract-nfsrootfs-36sgurkv,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 19:04:33.865398 - bootm 0x01080000 0x08000000 0x01070000
335 19:04:33.865935 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 19:04:33.867562 start: 2.3 connect-device (timeout 00:05:00) [common]
338 19:04:33.868070 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 19:04:33.884378 Setting prompt string to ['lava-test: # ']
340 19:04:33.885984 end: 2.3 connect-device (duration 00:00:00) [common]
341 19:04:33.886651 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 19:04:33.887260 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 19:04:33.887832 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 19:04:33.889085 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 19:04:33.925793 >> OK - accepted request
346 19:04:33.928289 Returned 0 in 0 seconds
347 19:04:34.029480 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 19:04:34.031198 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 19:04:34.031800 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 19:04:34.032401 Setting prompt string to ['Hit any key to stop autoboot']
352 19:04:34.032889 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 19:04:34.034538 Trying 192.168.56.21...
354 19:04:34.035034 Connected to conserv1.
355 19:04:34.035475 Escape character is '^]'.
356 19:04:34.035930
357 19:04:34.036416 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 19:04:34.036885
359 19:04:45.191049 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 19:04:45.191694 bl2_stage_init 0x01
361 19:04:45.192210 bl2_stage_init 0x81
362 19:04:45.196573 hw id: 0x0000 - pwm id 0x01
363 19:04:45.197108 bl2_stage_init 0xc1
364 19:04:45.197567 bl2_stage_init 0x02
365 19:04:45.198017
366 19:04:45.202055 L0:00000000
367 19:04:45.202559 L1:20000703
368 19:04:45.203012 L2:00008067
369 19:04:45.203458 L3:14000000
370 19:04:45.205020 B2:00402000
371 19:04:45.205503 B1:e0f83180
372 19:04:45.205931
373 19:04:45.206360 TE: 58167
374 19:04:45.206789
375 19:04:45.216169 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 19:04:45.216638
377 19:04:45.217069 Board ID = 1
378 19:04:45.217493 Set A53 clk to 24M
379 19:04:45.217915 Set A73 clk to 24M
380 19:04:45.221848 Set clk81 to 24M
381 19:04:45.222305 A53 clk: 1200 MHz
382 19:04:45.222733 A73 clk: 1200 MHz
383 19:04:45.227413 CLK81: 166.6M
384 19:04:45.227881 smccc: 00012abe
385 19:04:45.232955 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 19:04:45.233412 board id: 1
387 19:04:45.240613 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 19:04:45.252159 fw parse done
389 19:04:45.258117 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 19:04:45.300665 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 19:04:45.311577 PIEI prepare done
392 19:04:45.312073 fastboot data load
393 19:04:45.312507 fastboot data verify
394 19:04:45.317247 verify result: 266
395 19:04:45.322927 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 19:04:45.323386 LPDDR4 probe
397 19:04:45.323818 ddr clk to 1584MHz
398 19:04:45.330826 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 19:04:45.368079
400 19:04:45.368540 dmc_version 0001
401 19:04:45.374740 Check phy result
402 19:04:45.380642 INFO : End of CA training
403 19:04:45.381092 INFO : End of initialization
404 19:04:45.386190 INFO : Training has run successfully!
405 19:04:45.386640 Check phy result
406 19:04:45.391879 INFO : End of initialization
407 19:04:45.392366 INFO : End of read enable training
408 19:04:45.397496 INFO : End of fine write leveling
409 19:04:45.403081 INFO : End of Write leveling coarse delay
410 19:04:45.403533 INFO : Training has run successfully!
411 19:04:45.403966 Check phy result
412 19:04:45.408690 INFO : End of initialization
413 19:04:45.409142 INFO : End of read dq deskew training
414 19:04:45.414229 INFO : End of MPR read delay center optimization
415 19:04:45.419922 INFO : End of write delay center optimization
416 19:04:45.425373 INFO : End of read delay center optimization
417 19:04:45.425837 INFO : End of max read latency training
418 19:04:45.431073 INFO : Training has run successfully!
419 19:04:45.431559 1D training succeed
420 19:04:45.440205 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 19:04:45.486948 Check phy result
422 19:04:45.487419 INFO : End of initialization
423 19:04:45.510378 INFO : End of 2D read delay Voltage center optimization
424 19:04:45.530165 INFO : End of 2D read delay Voltage center optimization
425 19:04:45.583073 INFO : End of 2D write delay Voltage center optimization
426 19:04:45.632212 INFO : End of 2D write delay Voltage center optimization
427 19:04:45.637790 INFO : Training has run successfully!
428 19:04:45.638085
429 19:04:45.638285 channel==0
430 19:04:45.643249 RxClkDly_Margin_A0==88 ps 9
431 19:04:45.643768 TxDqDly_Margin_A0==98 ps 10
432 19:04:45.646634 RxClkDly_Margin_A1==78 ps 8
433 19:04:45.647147 TxDqDly_Margin_A1==98 ps 10
434 19:04:45.652197 TrainedVREFDQ_A0==74
435 19:04:45.652688 TrainedVREFDQ_A1==74
436 19:04:45.653148 VrefDac_Margin_A0==24
437 19:04:45.658014 DeviceVref_Margin_A0==40
438 19:04:45.658495 VrefDac_Margin_A1==25
439 19:04:45.663548 DeviceVref_Margin_A1==40
440 19:04:45.664096
441 19:04:45.664558
442 19:04:45.665008 channel==1
443 19:04:45.665448 RxClkDly_Margin_A0==98 ps 10
444 19:04:45.666890 TxDqDly_Margin_A0==98 ps 10
445 19:04:45.672434 RxClkDly_Margin_A1==98 ps 10
446 19:04:45.672915 TxDqDly_Margin_A1==88 ps 9
447 19:04:45.673372 TrainedVREFDQ_A0==77
448 19:04:45.678235 TrainedVREFDQ_A1==77
449 19:04:45.678731 VrefDac_Margin_A0==22
450 19:04:45.683588 DeviceVref_Margin_A0==37
451 19:04:45.684105 VrefDac_Margin_A1==24
452 19:04:45.684555 DeviceVref_Margin_A1==37
453 19:04:45.685000
454 19:04:45.689224 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 19:04:45.689700
456 19:04:45.722669 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
457 19:04:45.723249 2D training succeed
458 19:04:45.728318 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 19:04:45.733899 auto size-- 65535DDR cs0 size: 2048MB
460 19:04:45.734390 DDR cs1 size: 2048MB
461 19:04:45.739544 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 19:04:45.740057 cs0 DataBus test pass
463 19:04:45.740514 cs1 DataBus test pass
464 19:04:45.745118 cs0 AddrBus test pass
465 19:04:45.745604 cs1 AddrBus test pass
466 19:04:45.746057
467 19:04:45.750760 100bdlr_step_size ps== 420
468 19:04:45.751329 result report
469 19:04:45.751821 boot times 0Enable ddr reg access
470 19:04:45.760585 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 19:04:45.774105 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 19:04:46.347221 0.0;M3 CHK:0;cm4_sp_mode 0
473 19:04:46.347902 MVN_1=0x00000000
474 19:04:46.352649 MVN_2=0x00000000
475 19:04:46.358332 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 19:04:46.358882 OPS=0x10
477 19:04:46.359116 ring efuse init
478 19:04:46.359331 chipver efuse init
479 19:04:46.364031 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 19:04:46.369597 [0.018961 Inits done]
481 19:04:46.370131 secure task start!
482 19:04:46.370587 high task start!
483 19:04:46.374155 low task start!
484 19:04:46.374648 run into bl31
485 19:04:46.380825 NOTICE: BL31: v1.3(release):4fc40b1
486 19:04:46.388659 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 19:04:46.389161 NOTICE: BL31: G12A normal boot!
488 19:04:46.413993 NOTICE: BL31: BL33 decompress pass
489 19:04:46.419657 ERROR: Error initializing runtime service opteed_fast
490 19:04:47.652634
491 19:04:47.653068
492 19:04:47.660921 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 19:04:47.661363
494 19:04:47.661680 Model: Libre Computer AML-A311D-CC Alta
495 19:04:47.869367 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 19:04:47.892767 DRAM: 2 GiB (effective 3.8 GiB)
497 19:04:48.035844 Core: 408 devices, 31 uclasses, devicetree: separate
498 19:04:48.041614 WDT: Not starting watchdog@f0d0
499 19:04:48.073909 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 19:04:48.086355 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 19:04:48.091328 ** Bad device specification mmc 0 **
502 19:04:48.101703 Card did not respond to voltage select! : -110
503 19:04:48.109574 ** Bad device specification mmc 0 **
504 19:04:48.110110 Couldn't find partition mmc 0
505 19:04:48.117772 Card did not respond to voltage select! : -110
506 19:04:48.123342 ** Bad device specification mmc 0 **
507 19:04:48.123871 Couldn't find partition mmc 0
508 19:04:48.128385 Error: could not access storage.
509 19:04:49.391213 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 19:04:49.391652 bl2_stage_init 0x01
511 19:04:49.391922 bl2_stage_init 0x81
512 19:04:49.396854 hw id: 0x0000 - pwm id 0x01
513 19:04:49.397294 bl2_stage_init 0xc1
514 19:04:49.397553 bl2_stage_init 0x02
515 19:04:49.397769
516 19:04:49.402443 L0:00000000
517 19:04:49.402840 L1:20000703
518 19:04:49.403073 L2:00008067
519 19:04:49.403304 L3:14000000
520 19:04:49.408046 B2:00402000
521 19:04:49.408451 B1:e0f83180
522 19:04:49.408684
523 19:04:49.408914 TE: 58159
524 19:04:49.409128
525 19:04:49.413588 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 19:04:49.413921
527 19:04:49.414149 Board ID = 1
528 19:04:49.419229 Set A53 clk to 24M
529 19:04:49.419658 Set A73 clk to 24M
530 19:04:49.419890 Set clk81 to 24M
531 19:04:49.424879 A53 clk: 1200 MHz
532 19:04:49.425426 A73 clk: 1200 MHz
533 19:04:49.425714 CLK81: 166.6M
534 19:04:49.425964 smccc: 00012ab5
535 19:04:49.430709 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 19:04:49.436378 board id: 1
537 19:04:49.441885 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 19:04:49.452615 fw parse done
539 19:04:49.457888 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 19:04:49.501214 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 19:04:49.512115 PIEI prepare done
542 19:04:49.512726 fastboot data load
543 19:04:49.513007 fastboot data verify
544 19:04:49.518312 verify result: 266
545 19:04:49.523343 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 19:04:49.523772 LPDDR4 probe
547 19:04:49.524040 ddr clk to 1584MHz
548 19:04:49.531348 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 19:04:49.568789
550 19:04:49.569233 dmc_version 0001
551 19:04:49.577652 Check phy result
552 19:04:49.581096 INFO : End of CA training
553 19:04:49.581608 INFO : End of initialization
554 19:04:49.586664 INFO : Training has run successfully!
555 19:04:49.587003 Check phy result
556 19:04:49.592905 INFO : End of initialization
557 19:04:49.593531 INFO : End of read enable training
558 19:04:49.597910 INFO : End of fine write leveling
559 19:04:49.603520 INFO : End of Write leveling coarse delay
560 19:04:49.603951 INFO : Training has run successfully!
561 19:04:49.604218 Check phy result
562 19:04:49.609102 INFO : End of initialization
563 19:04:49.609705 INFO : End of read dq deskew training
564 19:04:49.614686 INFO : End of MPR read delay center optimization
565 19:04:49.620280 INFO : End of write delay center optimization
566 19:04:49.625858 INFO : End of read delay center optimization
567 19:04:49.626193 INFO : End of max read latency training
568 19:04:49.637930 INFO : Training has run successfully!
569 19:04:49.638558 1D training succeed
570 19:04:49.639679 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 19:04:49.687508 Check phy result
572 19:04:49.687997 INFO : End of initialization
573 19:04:49.709923 INFO : End of 2D read delay Voltage center optimization
574 19:04:49.729950 INFO : End of 2D read delay Voltage center optimization
575 19:04:49.781927 INFO : End of 2D write delay Voltage center optimization
576 19:04:49.832125 INFO : End of 2D write delay Voltage center optimization
577 19:04:49.837547 INFO : Training has run successfully!
578 19:04:49.838121
579 19:04:49.838406 channel==0
580 19:04:49.843777 RxClkDly_Margin_A0==88 ps 9
581 19:04:49.844229 TxDqDly_Margin_A0==98 ps 10
582 19:04:49.849160 RxClkDly_Margin_A1==88 ps 9
583 19:04:49.849782 TxDqDly_Margin_A1==98 ps 10
584 19:04:49.850031 TrainedVREFDQ_A0==74
585 19:04:49.854933 TrainedVREFDQ_A1==74
586 19:04:49.856005 VrefDac_Margin_A0==25
587 19:04:49.856273 DeviceVref_Margin_A0==40
588 19:04:49.860176 VrefDac_Margin_A1==25
589 19:04:49.860682 DeviceVref_Margin_A1==40
590 19:04:49.860901
591 19:04:49.861112
592 19:04:49.866292 channel==1
593 19:04:49.866846 RxClkDly_Margin_A0==98 ps 10
594 19:04:49.867075 TxDqDly_Margin_A0==98 ps 10
595 19:04:49.874457 RxClkDly_Margin_A1==98 ps 10
596 19:04:49.874902 TxDqDly_Margin_A1==98 ps 10
597 19:04:49.880582 TrainedVREFDQ_A0==77
598 19:04:49.881206 TrainedVREFDQ_A1==78
599 19:04:49.881629 VrefDac_Margin_A0==22
600 19:04:49.882744 DeviceVref_Margin_A0==37
601 19:04:49.883236 VrefDac_Margin_A1==22
602 19:04:49.888039 DeviceVref_Margin_A1==36
603 19:04:49.888666
604 19:04:49.889131 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 19:04:49.914608
606 19:04:49.922055 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
607 19:04:49.924893 2D training succeed
608 19:04:49.927117 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 19:04:49.932859 auto size-- 65535DDR cs0 size: 2048MB
610 19:04:49.933725 DDR cs1 size: 2048MB
611 19:04:49.946629 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 19:04:49.948284 cs0 DataBus test pass
613 19:04:49.949437 cs1 DataBus test pass
614 19:04:49.951787 cs0 AddrBus test pass
615 19:04:49.952310 cs1 AddrBus test pass
616 19:04:49.952588
617 19:04:49.953035 100bdlr_step_size ps== 420
618 19:04:49.953723 result report
619 19:04:49.955194 boot times 0Enable ddr reg access
620 19:04:49.959840 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 19:04:49.973421 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 19:04:50.546288 0.0;M3 CHK:0;cm4_sp_mode 0
623 19:04:50.546974 MVN_1=0x00000000
624 19:04:50.551788 MVN_2=0x00000000
625 19:04:50.557481 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 19:04:50.558053 OPS=0x10
627 19:04:50.558477 ring efuse init
628 19:04:50.558888 chipver efuse init
629 19:04:50.563097 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 19:04:50.568695 [0.018960 Inits done]
631 19:04:50.569210 secure task start!
632 19:04:50.569607 high task start!
633 19:04:50.573341 low task start!
634 19:04:50.573884 run into bl31
635 19:04:50.580132 NOTICE: BL31: v1.3(release):4fc40b1
636 19:04:50.587807 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 19:04:50.588449 NOTICE: BL31: G12A normal boot!
638 19:04:50.613072 NOTICE: BL31: BL33 decompress pass
639 19:04:50.618772 ERROR: Error initializing runtime service opteed_fast
640 19:04:51.851761
641 19:04:51.852398
642 19:04:51.860241 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 19:04:51.860718
644 19:04:51.861133 Model: Libre Computer AML-A311D-CC Alta
645 19:04:52.068593 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 19:04:52.092130 DRAM: 2 GiB (effective 3.8 GiB)
647 19:04:52.235075 Core: 408 devices, 31 uclasses, devicetree: separate
648 19:04:52.240835 WDT: Not starting watchdog@f0d0
649 19:04:52.273026 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 19:04:52.285472 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 19:04:52.290552 ** Bad device specification mmc 0 **
652 19:04:52.300762 Card did not respond to voltage select! : -110
653 19:04:52.308515 ** Bad device specification mmc 0 **
654 19:04:52.308973 Couldn't find partition mmc 0
655 19:04:52.316722 Card did not respond to voltage select! : -110
656 19:04:52.322389 ** Bad device specification mmc 0 **
657 19:04:52.322859 Couldn't find partition mmc 0
658 19:04:52.327383 Error: could not access storage.
659 19:04:52.670921 Net: eth0: ethernet@ff3f0000
660 19:04:52.671445 starting USB...
661 19:04:52.922770 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 19:04:52.923304 Starting the controller
663 19:04:52.929736 USB XHCI 1.10
664 19:04:54.641665 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 19:04:54.642307 bl2_stage_init 0x01
666 19:04:54.642741 bl2_stage_init 0x81
667 19:04:54.647405 hw id: 0x0000 - pwm id 0x01
668 19:04:54.647870 bl2_stage_init 0xc1
669 19:04:54.648332 bl2_stage_init 0x02
670 19:04:54.648744
671 19:04:54.652885 L0:00000000
672 19:04:54.653345 L1:20000703
673 19:04:54.653752 L2:00008067
674 19:04:54.654148 L3:14000000
675 19:04:54.655832 B2:00402000
676 19:04:54.656317 B1:e0f83180
677 19:04:54.656727
678 19:04:54.657130 TE: 58124
679 19:04:54.657532
680 19:04:54.666885 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 19:04:54.667347
682 19:04:54.667757 Board ID = 1
683 19:04:54.668200 Set A53 clk to 24M
684 19:04:54.668600 Set A73 clk to 24M
685 19:04:54.672686 Set clk81 to 24M
686 19:04:54.673137 A53 clk: 1200 MHz
687 19:04:54.673540 A73 clk: 1200 MHz
688 19:04:54.676236 CLK81: 166.6M
689 19:04:54.676691 smccc: 00012a92
690 19:04:54.681681 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 19:04:54.687410 board id: 1
692 19:04:54.692542 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 19:04:54.702805 fw parse done
694 19:04:54.708757 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 19:04:54.751352 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 19:04:54.762323 PIEI prepare done
697 19:04:54.762776 fastboot data load
698 19:04:54.763191 fastboot data verify
699 19:04:54.767876 verify result: 266
700 19:04:54.773496 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 19:04:54.773950 LPDDR4 probe
702 19:04:54.774354 ddr clk to 1584MHz
703 19:04:54.780458 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 19:04:54.818745
705 19:04:54.819222 dmc_version 0001
706 19:04:54.825441 Check phy result
707 19:04:54.831288 INFO : End of CA training
708 19:04:54.831743 INFO : End of initialization
709 19:04:54.836883 INFO : Training has run successfully!
710 19:04:54.837335 Check phy result
711 19:04:54.842476 INFO : End of initialization
712 19:04:54.842929 INFO : End of read enable training
713 19:04:54.848249 INFO : End of fine write leveling
714 19:04:54.853720 INFO : End of Write leveling coarse delay
715 19:04:54.854178 INFO : Training has run successfully!
716 19:04:54.854586 Check phy result
717 19:04:54.859299 INFO : End of initialization
718 19:04:54.859753 INFO : End of read dq deskew training
719 19:04:54.864886 INFO : End of MPR read delay center optimization
720 19:04:54.870471 INFO : End of write delay center optimization
721 19:04:54.876263 INFO : End of read delay center optimization
722 19:04:54.876718 INFO : End of max read latency training
723 19:04:54.881717 INFO : Training has run successfully!
724 19:04:54.882168 1D training succeed
725 19:04:54.890882 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 19:04:54.938487 Check phy result
727 19:04:54.938973 INFO : End of initialization
728 19:04:54.961001 INFO : End of 2D read delay Voltage center optimization
729 19:04:54.980983 INFO : End of 2D read delay Voltage center optimization
730 19:04:55.032950 INFO : End of 2D write delay Voltage center optimization
731 19:04:55.082197 INFO : End of 2D write delay Voltage center optimization
732 19:04:55.087773 INFO : Training has run successfully!
733 19:04:55.088359
734 19:04:55.088790 channel==0
735 19:04:55.093309 RxClkDly_Margin_A0==88 ps 9
736 19:04:55.093789 TxDqDly_Margin_A0==98 ps 10
737 19:04:55.098904 RxClkDly_Margin_A1==88 ps 9
738 19:04:55.099375 TxDqDly_Margin_A1==98 ps 10
739 19:04:55.099796 TrainedVREFDQ_A0==74
740 19:04:55.104486 TrainedVREFDQ_A1==74
741 19:04:55.104961 VrefDac_Margin_A0==24
742 19:04:55.105375 DeviceVref_Margin_A0==40
743 19:04:55.110138 VrefDac_Margin_A1==24
744 19:04:55.110596 DeviceVref_Margin_A1==40
745 19:04:55.111008
746 19:04:55.111412
747 19:04:55.115685 channel==1
748 19:04:55.116193 RxClkDly_Margin_A0==98 ps 10
749 19:04:55.116608 TxDqDly_Margin_A0==98 ps 10
750 19:04:55.121312 RxClkDly_Margin_A1==88 ps 9
751 19:04:55.121779 TxDqDly_Margin_A1==88 ps 9
752 19:04:55.126898 TrainedVREFDQ_A0==77
753 19:04:55.127366 TrainedVREFDQ_A1==77
754 19:04:55.127776 VrefDac_Margin_A0==22
755 19:04:55.132512 DeviceVref_Margin_A0==37
756 19:04:55.132975 VrefDac_Margin_A1==24
757 19:04:55.138116 DeviceVref_Margin_A1==37
758 19:04:55.138578
759 19:04:55.138992 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 19:04:55.139395
761 19:04:55.171635 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
762 19:04:55.172202 2D training succeed
763 19:04:55.177312 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 19:04:55.182881 auto size-- 65535DDR cs0 size: 2048MB
765 19:04:55.183338 DDR cs1 size: 2048MB
766 19:04:55.188479 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 19:04:55.188933 cs0 DataBus test pass
768 19:04:55.194077 cs1 DataBus test pass
769 19:04:55.194531 cs0 AddrBus test pass
770 19:04:55.194937 cs1 AddrBus test pass
771 19:04:55.195334
772 19:04:55.199656 100bdlr_step_size ps== 420
773 19:04:55.200152 result report
774 19:04:55.205343 boot times 0Enable ddr reg access
775 19:04:55.210652 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 19:04:55.224082 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 19:04:55.796129 0.0;M3 CHK:0;cm4_sp_mode 0
778 19:04:55.796739 MVN_1=0x00000000
779 19:04:55.801593 MVN_2=0x00000000
780 19:04:55.807346 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 19:04:55.807846 OPS=0x10
782 19:04:55.808280 ring efuse init
783 19:04:55.808667 chipver efuse init
784 19:04:55.812945 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 19:04:55.818490 [0.018961 Inits done]
786 19:04:55.818938 secure task start!
787 19:04:55.819328 high task start!
788 19:04:55.823051 low task start!
789 19:04:55.823493 run into bl31
790 19:04:55.829749 NOTICE: BL31: v1.3(release):4fc40b1
791 19:04:55.837562 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 19:04:55.838019 NOTICE: BL31: G12A normal boot!
793 19:04:55.862938 NOTICE: BL31: BL33 decompress pass
794 19:04:55.868618 ERROR: Error initializing runtime service opteed_fast
795 19:04:57.101417
796 19:04:57.102028
797 19:04:57.109834 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 19:04:57.110335
799 19:04:57.110755 Model: Libre Computer AML-A311D-CC Alta
800 19:04:57.318241 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 19:04:57.341661 DRAM: 2 GiB (effective 3.8 GiB)
802 19:04:57.484622 Core: 408 devices, 31 uclasses, devicetree: separate
803 19:04:57.490573 WDT: Not starting watchdog@f0d0
804 19:04:57.522735 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 19:04:57.535161 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 19:04:57.540201 ** Bad device specification mmc 0 **
807 19:04:57.550542 Card did not respond to voltage select! : -110
808 19:04:57.558214 ** Bad device specification mmc 0 **
809 19:04:57.558668 Couldn't find partition mmc 0
810 19:04:57.566545 Card did not respond to voltage select! : -110
811 19:04:57.572071 ** Bad device specification mmc 0 **
812 19:04:57.572533 Couldn't find partition mmc 0
813 19:04:57.577106 Error: could not access storage.
814 19:04:57.919624 Net: eth0: ethernet@ff3f0000
815 19:04:57.920186 starting USB...
816 19:04:58.171389 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 19:04:58.171962 Starting the controller
818 19:04:58.178467 USB XHCI 1.10
819 19:05:00.341735 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 19:05:00.342147 bl2_stage_init 0x01
821 19:05:00.342387 bl2_stage_init 0x81
822 19:05:00.347146 hw id: 0x0000 - pwm id 0x01
823 19:05:00.347538 bl2_stage_init 0xc1
824 19:05:00.347868 bl2_stage_init 0x02
825 19:05:00.348260
826 19:05:00.352762 L0:00000000
827 19:05:00.353042 L1:20000703
828 19:05:00.353267 L2:00008067
829 19:05:00.353479 L3:14000000
830 19:05:00.355767 B2:00402000
831 19:05:00.356169 B1:e0f83180
832 19:05:00.356499
833 19:05:00.356821 TE: 58167
834 19:05:00.357164
835 19:05:00.366957 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 19:05:00.367364
837 19:05:00.367711 Board ID = 1
838 19:05:00.367956 Set A53 clk to 24M
839 19:05:00.368195 Set A73 clk to 24M
840 19:05:00.372669 Set clk81 to 24M
841 19:05:00.372946 A53 clk: 1200 MHz
842 19:05:00.373158 A73 clk: 1200 MHz
843 19:05:00.378272 CLK81: 166.6M
844 19:05:00.378664 smccc: 00012abe
845 19:05:00.383739 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 19:05:00.384183 board id: 1
847 19:05:00.392349 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 19:05:00.403141 fw parse done
849 19:05:00.408950 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 19:05:00.451516 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 19:05:00.462439 PIEI prepare done
852 19:05:00.463551 fastboot data load
853 19:05:00.464575 fastboot data verify
854 19:05:00.468052 verify result: 266
855 19:05:00.473656 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 19:05:00.474275 LPDDR4 probe
857 19:05:00.474790 ddr clk to 1584MHz
858 19:05:00.481582 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 19:05:00.518794
860 19:05:00.519373 dmc_version 0001
861 19:05:00.525486 Check phy result
862 19:05:00.531956 INFO : End of CA training
863 19:05:00.532513 INFO : End of initialization
864 19:05:00.537357 INFO : Training has run successfully!
865 19:05:00.537895 Check phy result
866 19:05:00.543183 INFO : End of initialization
867 19:05:00.543709 INFO : End of read enable training
868 19:05:00.548236 INFO : End of fine write leveling
869 19:05:00.553864 INFO : End of Write leveling coarse delay
870 19:05:00.554487 INFO : Training has run successfully!
871 19:05:00.554998 Check phy result
872 19:05:00.559367 INFO : End of initialization
873 19:05:00.559911 INFO : End of read dq deskew training
874 19:05:00.564989 INFO : End of MPR read delay center optimization
875 19:05:00.570541 INFO : End of write delay center optimization
876 19:05:00.576274 INFO : End of read delay center optimization
877 19:05:00.577287 INFO : End of max read latency training
878 19:05:00.581948 INFO : Training has run successfully!
879 19:05:00.583060 1D training succeed
880 19:05:00.591121 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 19:05:00.638614 Check phy result
882 19:05:00.639171 INFO : End of initialization
883 19:05:00.660393 INFO : End of 2D read delay Voltage center optimization
884 19:05:00.680587 INFO : End of 2D read delay Voltage center optimization
885 19:05:00.732607 INFO : End of 2D write delay Voltage center optimization
886 19:05:00.781964 INFO : End of 2D write delay Voltage center optimization
887 19:05:00.787613 INFO : Training has run successfully!
888 19:05:00.788207
889 19:05:00.788654 channel==0
890 19:05:00.793272 RxClkDly_Margin_A0==88 ps 9
891 19:05:00.793806 TxDqDly_Margin_A0==98 ps 10
892 19:05:00.798808 RxClkDly_Margin_A1==88 ps 9
893 19:05:00.799337 TxDqDly_Margin_A1==98 ps 10
894 19:05:00.799792 TrainedVREFDQ_A0==74
895 19:05:00.804534 TrainedVREFDQ_A1==74
896 19:05:00.805095 VrefDac_Margin_A0==25
897 19:05:00.805526 DeviceVref_Margin_A0==40
898 19:05:00.809942 VrefDac_Margin_A1==24
899 19:05:00.810468 DeviceVref_Margin_A1==40
900 19:05:00.810861
901 19:05:00.811251
902 19:05:00.815599 channel==1
903 19:05:00.816119 RxClkDly_Margin_A0==98 ps 10
904 19:05:00.816522 TxDqDly_Margin_A0==88 ps 9
905 19:05:00.821183 RxClkDly_Margin_A1==98 ps 10
906 19:05:00.821676 TxDqDly_Margin_A1==88 ps 9
907 19:05:00.826825 TrainedVREFDQ_A0==77
908 19:05:00.827315 TrainedVREFDQ_A1==77
909 19:05:00.827705 VrefDac_Margin_A0==22
910 19:05:00.832344 DeviceVref_Margin_A0==37
911 19:05:00.832835 VrefDac_Margin_A1==22
912 19:05:00.837918 DeviceVref_Margin_A1==37
913 19:05:00.838412
914 19:05:00.838803 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 19:05:00.839188
916 19:05:00.871550 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
917 19:05:00.872110 2D training succeed
918 19:05:00.877134 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 19:05:00.882658 auto size-- 65535DDR cs0 size: 2048MB
920 19:05:00.883154 DDR cs1 size: 2048MB
921 19:05:00.888291 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 19:05:00.888793 cs0 DataBus test pass
923 19:05:00.893850 cs1 DataBus test pass
924 19:05:00.894342 cs0 AddrBus test pass
925 19:05:00.894732 cs1 AddrBus test pass
926 19:05:00.895114
927 19:05:00.899456 100bdlr_step_size ps== 420
928 19:05:00.899960 result report
929 19:05:00.905046 boot times 0Enable ddr reg access
930 19:05:00.910413 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 19:05:00.923913 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 19:05:01.497524 0.0;M3 CHK:0;cm4_sp_mode 0
933 19:05:01.498108 MVN_1=0x00000000
934 19:05:01.503065 MVN_2=0x00000000
935 19:05:01.508822 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 19:05:01.509318 OPS=0x10
937 19:05:01.509740 ring efuse init
938 19:05:01.510144 chipver efuse init
939 19:05:01.514398 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 19:05:01.520085 [0.018961 Inits done]
941 19:05:01.520586 secure task start!
942 19:05:01.521013 high task start!
943 19:05:01.524580 low task start!
944 19:05:01.525066 run into bl31
945 19:05:01.531241 NOTICE: BL31: v1.3(release):4fc40b1
946 19:05:01.539131 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 19:05:01.539639 NOTICE: BL31: G12A normal boot!
948 19:05:01.564469 NOTICE: BL31: BL33 decompress pass
949 19:05:01.570163 ERROR: Error initializing runtime service opteed_fast
950 19:05:02.803002
951 19:05:02.803622
952 19:05:02.811399 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 19:05:02.811894
954 19:05:02.812361 Model: Libre Computer AML-A311D-CC Alta
955 19:05:03.019761 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 19:05:03.042211 DRAM: 2 GiB (effective 3.8 GiB)
957 19:05:03.186086 Core: 408 devices, 31 uclasses, devicetree: separate
958 19:05:03.191146 WDT: Not starting watchdog@f0d0
959 19:05:03.224290 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 19:05:03.236688 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 19:05:03.241705 ** Bad device specification mmc 0 **
962 19:05:03.252053 Card did not respond to voltage select! : -110
963 19:05:03.258687 ** Bad device specification mmc 0 **
964 19:05:03.259167 Couldn't find partition mmc 0
965 19:05:03.268086 Card did not respond to voltage select! : -110
966 19:05:03.273568 ** Bad device specification mmc 0 **
967 19:05:03.274048 Couldn't find partition mmc 0
968 19:05:03.277684 Error: could not access storage.
969 19:05:03.620176 Net: eth0: ethernet@ff3f0000
970 19:05:03.620728 starting USB...
971 19:05:03.872912 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 19:05:03.873512 Starting the controller
973 19:05:03.879915 USB XHCI 1.10
974 19:05:05.433824 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
975 19:05:05.442212 scanning usb for storage devices... 0 Storage Device(s) found
977 19:05:05.494506 Hit any key to stop autoboot: 1
978 19:05:05.495415 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
979 19:05:05.496088 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
980 19:05:05.496578 Setting prompt string to ['=>']
981 19:05:05.497068 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
982 19:05:05.508847 0
983 19:05:05.509744 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
984 19:05:05.510240 Sending with 10 millisecond of delay
986 19:05:06.645669 => setenv autoload no
987 19:05:06.658229 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
988 19:05:06.663830 setenv autoload no
989 19:05:06.664712 Sending with 10 millisecond of delay
991 19:05:08.462206 => setenv initrd_high 0xffffffff
992 19:05:08.473105 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
993 19:05:08.474165 setenv initrd_high 0xffffffff
994 19:05:08.474983 Sending with 10 millisecond of delay
996 19:05:10.092366 => setenv fdt_high 0xffffffff
997 19:05:10.103203 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
998 19:05:10.104197 setenv fdt_high 0xffffffff
999 19:05:10.104969 Sending with 10 millisecond of delay
1001 19:05:10.396875 => dhcp
1002 19:05:10.407739 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
1003 19:05:10.409000 dhcp
1004 19:05:10.409540 Speed: 1000, full duplex
1005 19:05:10.410012 BOOTP broadcast 1
1006 19:05:10.418685 DHCP client bound to address 192.168.6.27 (11 ms)
1007 19:05:10.419700 Sending with 10 millisecond of delay
1009 19:05:12.096873 => setenv serverip 192.168.6.2
1010 19:05:12.107674 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1011 19:05:12.108577 setenv serverip 192.168.6.2
1012 19:05:12.109271 Sending with 10 millisecond of delay
1014 19:05:15.833809 => tftpboot 0x01080000 935712/tftp-deploy-1sxpfpx3/kernel/uImage
1015 19:05:15.844633 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1016 19:05:15.845494 tftpboot 0x01080000 935712/tftp-deploy-1sxpfpx3/kernel/uImage
1017 19:05:15.845948 Speed: 1000, full duplex
1018 19:05:15.846368 Using ethernet@ff3f0000 device
1019 19:05:15.847501 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1020 19:05:15.853023 Filename '935712/tftp-deploy-1sxpfpx3/kernel/uImage'.
1021 19:05:15.856927 Load address: 0x1080000
1022 19:05:17.168168 Loading: *#################### UDP wrong checksum 000000ff 0000431e
1023 19:05:17.192262 # UDP wrong checksum 000000ff 0000d010
1024 19:05:18.903176 ############################# 43.6 MiB
1025 19:05:18.903791 14.3 MiB/s
1026 19:05:18.904276 done
1027 19:05:18.908223 Bytes transferred = 45713984 (2b98a40 hex)
1028 19:05:18.909005 Sending with 10 millisecond of delay
1030 19:05:23.595186 => tftpboot 0x08000000 935712/tftp-deploy-1sxpfpx3/ramdisk/ramdisk.cpio.gz.uboot
1031 19:05:23.605997 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1032 19:05:23.606863 tftpboot 0x08000000 935712/tftp-deploy-1sxpfpx3/ramdisk/ramdisk.cpio.gz.uboot
1033 19:05:23.607329 Speed: 1000, full duplex
1034 19:05:23.607746 Using ethernet@ff3f0000 device
1035 19:05:23.608512 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1036 19:05:23.619306 Filename '935712/tftp-deploy-1sxpfpx3/ramdisk/ramdisk.cpio.gz.uboot'.
1037 19:05:23.619785 Load address: 0x8000000
1038 19:05:30.360464 Loading: *##################T ################################ 22.3 MiB
1039 19:05:30.368286 3.3 MiB/s
1040 19:05:30.368586 done
1041 19:05:30.368811 Bytes transferred = 23433436 (16590dc hex)
1042 19:05:30.369270 Sending with 10 millisecond of delay
1044 19:05:35.537422 => tftpboot 0x01070000 935712/tftp-deploy-1sxpfpx3/dtb/meson-g12b-a311d-libretech-cc.dtb
1045 19:05:35.548172 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:58)
1046 19:05:35.548984 tftpboot 0x01070000 935712/tftp-deploy-1sxpfpx3/dtb/meson-g12b-a311d-libretech-cc.dtb
1047 19:05:35.549451 Speed: 1000, full duplex
1048 19:05:35.549875 Using ethernet@ff3f0000 device
1049 19:05:35.553302 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1050 19:05:35.566426 Filename '935712/tftp-deploy-1sxpfpx3/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1051 19:05:35.566929 Load address: 0x1070000
1052 19:05:35.582962 Loading: *################################################## 53.4 KiB
1053 19:05:35.583440 2.9 MiB/s
1054 19:05:35.583859 done
1055 19:05:35.589460 Bytes transferred = 54703 (d5af hex)
1056 19:05:35.590190 Sending with 10 millisecond of delay
1058 19:05:48.886372 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/935712/extract-nfsrootfs-36sgurkv,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1059 19:05:48.897172 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:45)
1060 19:05:48.898012 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/935712/extract-nfsrootfs-36sgurkv,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1061 19:05:48.898711 Sending with 10 millisecond of delay
1063 19:05:51.236697 => bootm 0x01080000 0x08000000 0x01070000
1064 19:05:51.247514 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1065 19:05:51.248119 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:43)
1066 19:05:51.249117 bootm 0x01080000 0x08000000 0x01070000
1067 19:05:51.249567 ## Booting kernel from Legacy Image at 01080000 ...
1068 19:05:51.252624 Image Name:
1069 19:05:51.258205 Image Type: AArch64 Linux Kernel Image (uncompressed)
1070 19:05:51.258650 Data Size: 45713920 Bytes = 43.6 MiB
1071 19:05:51.263403 Load Address: 01080000
1072 19:05:51.263833 Entry Point: 01080000
1073 19:05:51.458632 Verifying Checksum ... OK
1074 19:05:51.459174 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1075 19:05:51.464035 Image Name:
1076 19:05:51.469588 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1077 19:05:51.470021 Data Size: 23433372 Bytes = 22.3 MiB
1078 19:05:51.471874 Load Address: 00000000
1079 19:05:51.479033 Entry Point: 00000000
1080 19:05:51.577240 Verifying Checksum ... OK
1081 19:05:51.577723 ## Flattened Device Tree blob at 01070000
1082 19:05:51.582646 Booting using the fdt blob at 0x1070000
1083 19:05:51.583074 Working FDT set to 1070000
1084 19:05:51.587161 Loading Kernel Image
1085 19:05:51.738453 Loading Ramdisk to 7e9a6000, end 7ffff09c ... OK
1086 19:05:51.746842 Loading Device Tree to 000000007e995000, end 000000007e9a55ae ... OK
1087 19:05:51.747276 Working FDT set to 7e995000
1088 19:05:51.747681
1089 19:05:51.748604 end: 2.4.3 bootloader-commands (duration 00:00:46) [common]
1090 19:05:51.749177 start: 2.4.4 auto-login-action (timeout 00:03:42) [common]
1091 19:05:51.749634 Setting prompt string to ['Linux version [0-9]']
1092 19:05:51.750083 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1093 19:05:51.750543 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1094 19:05:51.751521 Starting kernel ...
1095 19:05:51.751965
1096 19:05:51.787251 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1097 19:05:51.788174 start: 2.4.4.1 login-action (timeout 00:03:42) [common]
1098 19:05:51.788686 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1099 19:05:51.789144 Setting prompt string to []
1100 19:05:51.789625 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1101 19:05:51.790074 Using line separator: #'\n'#
1102 19:05:51.790478 No login prompt set.
1103 19:05:51.790897 Parsing kernel messages
1104 19:05:51.791288 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1105 19:05:51.792093 [login-action] Waiting for messages, (timeout 00:03:42)
1106 19:05:51.792544 Waiting using forced prompt support (timeout 00:01:51)
1107 19:05:51.803715 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j361855-arm64-gcc-12-defconfig-92r5c) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Mon Nov 4 17:43:13 UTC 2024
1108 19:05:51.809156 [ 0.000000] KASLR disabled due to lack of seed
1109 19:05:51.814736 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1110 19:05:51.820284 [ 0.000000] efi: UEFI not found.
1111 19:05:51.825723 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1112 19:05:51.831307 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1113 19:05:51.842192 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1114 19:05:51.853256 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1115 19:05:51.858767 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1116 19:05:51.869797 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1117 19:05:51.880842 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1118 19:05:51.886350 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1119 19:05:51.891859 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1120 19:05:51.897384 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1121 19:05:51.897815 [ 0.000000] Zone ranges:
1122 19:05:51.903008 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1123 19:05:51.908531 [ 0.000000] DMA32 empty
1124 19:05:51.908991 [ 0.000000] Normal empty
1125 19:05:51.913974 [ 0.000000] Movable zone start for each node
1126 19:05:51.919486 [ 0.000000] Early memory node ranges
1127 19:05:51.925000 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1128 19:05:51.930508 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1129 19:05:51.936065 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1130 19:05:51.941610 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1131 19:05:51.968993 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1132 19:05:51.974481 [ 0.000000] psci: probing for conduit method from DT.
1133 19:05:51.974912 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1134 19:05:51.980038 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1135 19:05:51.985528 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1136 19:05:51.991034 [ 0.000000] psci: SMC Calling Convention v1.1
1137 19:05:51.996591 [ 0.000000] percpu: Embedded 25 pages/cpu s61592 r8192 d32616 u102400
1138 19:05:52.002079 [ 0.000000] Detected VIPT I-cache on CPU0
1139 19:05:52.007681 [ 0.000000] CPU features: detected: ARM erratum 845719
1140 19:05:52.013218 [ 0.000000] alternatives: applying boot alternatives
1141 19:05:52.029692 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/935712/extract-nfsrootfs-36sgurkv,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1142 19:05:52.040743 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1143 19:05:52.046256 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1144 19:05:52.051771 <6>[ 0.000000] Fallback order for Node 0: 0
1145 19:05:52.057288 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1146 19:05:52.062803 <6>[ 0.000000] Policy zone: DMA
1147 19:05:52.068323 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1148 19:05:52.073854 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1149 19:05:52.079370 <6>[ 0.000000] software IO TLB: area num 8.
1150 19:05:52.088371 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1151 19:05:52.134876 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1152 19:05:52.140381 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1153 19:05:52.143945 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1154 19:05:52.149446 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1155 19:05:52.154960 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1156 19:05:52.160497 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1157 19:05:52.169513 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1158 19:05:52.175060 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1159 19:05:52.186104 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1160 19:05:52.191642 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1161 19:05:52.197142 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1162 19:05:52.202684 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1163 19:05:52.208201 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1164 19:05:52.216525 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1165 19:05:52.229157 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1166 19:05:52.240201 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1167 19:05:52.245724 <6>[ 0.000001] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1168 19:05:52.251257 <6>[ 0.008795] Console: colour dummy device 80x25
1169 19:05:52.262281 <6>[ 0.012943] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1170 19:05:52.267804 <6>[ 0.023294] pid_max: default: 32768 minimum: 301
1171 19:05:52.273318 <6>[ 0.028190] LSM: initializing lsm=capability
1172 19:05:52.278848 <6>[ 0.032734] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1173 19:05:52.284362 <6>[ 0.040211] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1174 19:05:52.289882 <6>[ 0.052299] rcu: Hierarchical SRCU implementation.
1175 19:05:52.295405 <6>[ 0.053215] rcu: Max phase no-delay instances is 1000.
1176 19:05:52.306444 <6>[ 0.058885] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1177 19:05:52.314869 <6>[ 0.071608] EFI services will not be available.
1178 19:05:52.315297 <6>[ 0.075258] smp: Bringing up secondary CPUs ...
1179 19:05:52.331269 <6>[ 0.077138] Detected VIPT I-cache on CPU1
1180 19:05:52.336794 <6>[ 0.077262] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1181 19:05:52.342287 <6>[ 0.078608] CPU features: detected: Spectre-v2
1182 19:05:52.347809 <6>[ 0.078622] CPU features: detected: Spectre-v4
1183 19:05:52.353290 <6>[ 0.078627] CPU features: detected: Spectre-BHB
1184 19:05:52.358795 <6>[ 0.078633] CPU features: detected: ARM erratum 858921
1185 19:05:52.364291 <6>[ 0.078641] Detected VIPT I-cache on CPU2
1186 19:05:52.369809 <6>[ 0.078714] arch_timer: Enabling local workaround for ARM erratum 858921
1187 19:05:52.375331 <6>[ 0.078733] arch_timer: CPU2: Trapping CNTVCT access
1188 19:05:52.380853 <6>[ 0.078743] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1189 19:05:52.386350 <6>[ 0.083689] Detected VIPT I-cache on CPU3
1190 19:05:52.391902 <6>[ 0.083735] arch_timer: Enabling local workaround for ARM erratum 858921
1191 19:05:52.397412 <6>[ 0.083745] arch_timer: CPU3: Trapping CNTVCT access
1192 19:05:52.402926 <6>[ 0.083752] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1193 19:05:52.408470 <6>[ 0.091723] Detected VIPT I-cache on CPU4
1194 19:05:52.413979 <6>[ 0.091770] arch_timer: Enabling local workaround for ARM erratum 858921
1195 19:05:52.419496 <6>[ 0.091779] arch_timer: CPU4: Trapping CNTVCT access
1196 19:05:52.430535 <6>[ 0.091787] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1197 19:05:52.430968 <6>[ 0.095675] Detected VIPT I-cache on CPU5
1198 19:05:52.441574 <6>[ 0.095723] arch_timer: Enabling local workaround for ARM erratum 858921
1199 19:05:52.442013 <6>[ 0.095732] arch_timer: CPU5: Trapping CNTVCT access
1200 19:05:52.452673 <6>[ 0.095739] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1201 19:05:52.453107 <6>[ 0.095855] smp: Brought up 1 node, 6 CPUs
1202 19:05:52.458116 <6>[ 0.217083] SMP: Total of 6 processors activated.
1203 19:05:52.463653 <6>[ 0.221991] CPU: All CPU(s) started at EL2
1204 19:05:52.469172 <6>[ 0.226331] CPU features: detected: 32-bit EL0 Support
1205 19:05:52.474713 <6>[ 0.231648] CPU features: detected: 32-bit EL1 Support
1206 19:05:52.480220 <6>[ 0.237011] CPU features: detected: CRC32 instructions
1207 19:05:52.485729 <6>[ 0.242402] alternatives: applying system-wide alternatives
1208 19:05:52.503682 <6>[ 0.249583] Memory: 3557432K/4012396K available (17280K kernel code, 4898K rwdata, 11868K rodata, 10432K init, 742K bss, 187800K reserved, 262144K cma-reserved)
1209 19:05:52.504156 <6>[ 0.263936] devtmpfs: initialized
1210 19:05:52.514834 <6>[ 0.273081] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1211 19:05:52.520299 <6>[ 0.277438] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1212 19:05:52.525771 <6>[ 0.288230] 21392 pages in range for non-PLT usage
1213 19:05:52.531264 <6>[ 0.288240] 512912 pages in range for PLT usage
1214 19:05:52.536789 <6>[ 0.289803] pinctrl core: initialized pinctrl subsystem
1215 19:05:52.542391 <6>[ 0.301878] DMI not present or invalid.
1216 19:05:52.547895 <6>[ 0.306182] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1217 19:05:52.553349 <6>[ 0.310919] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1218 19:05:52.564493 <6>[ 0.317693] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1219 19:05:52.569907 <6>[ 0.325790] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1220 19:05:52.575433 <6>[ 0.333270] audit: initializing netlink subsys (disabled)
1221 19:05:52.586458 <5>[ 0.339006] audit: type=2000 audit(0.260:1): state=initialized audit_enabled=0 res=1
1222 19:05:52.592014 <6>[ 0.340435] thermal_sys: Registered thermal governor 'step_wise'
1223 19:05:52.597530 <6>[ 0.346777] thermal_sys: Registered thermal governor 'power_allocator'
1224 19:05:52.603125 <6>[ 0.353039] cpuidle: using governor menu
1225 19:05:52.608860 <6>[ 0.364083] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1226 19:05:52.614266 <6>[ 0.370956] ASID allocator initialised with 65536 entries
1227 19:05:52.622373 <6>[ 0.378438] Serial: AMBA PL011 UART driver
1228 19:05:52.630200 <6>[ 0.389034] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1229 19:05:52.645320 <6>[ 0.404402] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1230 19:05:52.656371 <6>[ 0.407063] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1231 19:05:52.661863 <6>[ 0.420189] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1232 19:05:52.667335 <6>[ 0.423446] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1233 19:05:52.678471 <6>[ 0.431862] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1234 19:05:52.683924 <6>[ 0.439489] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1235 19:05:52.695020 <6>[ 0.453069] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1236 19:05:52.700545 <6>[ 0.455311] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1237 19:05:52.706004 <6>[ 0.461791] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1238 19:05:52.711567 <6>[ 0.468771] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1239 19:05:52.722598 <6>[ 0.475239] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1240 19:05:52.728121 <6>[ 0.482223] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1241 19:05:52.733659 <6>[ 0.488693] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1242 19:05:52.739170 <6>[ 0.495678] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1243 19:05:52.744682 <6>[ 0.503707] ACPI: Interpreter disabled.
1244 19:05:52.750132 <6>[ 0.509087] iommu: Default domain type: Translated
1245 19:05:52.755638 <6>[ 0.511211] iommu: DMA domain TLB invalidation policy: strict mode
1246 19:05:52.761161 <5>[ 0.517975] SCSI subsystem initialized
1247 19:05:52.766765 <6>[ 0.521851] usbcore: registered new interface driver usbfs
1248 19:05:52.772295 <6>[ 0.527273] usbcore: registered new interface driver hub
1249 19:05:52.777812 <6>[ 0.532786] usbcore: registered new device driver usb
1250 19:05:52.783333 <6>[ 0.539053] pps_core: LinuxPPS API ver. 1 registered
1251 19:05:52.788871 <6>[ 0.543205] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1252 19:05:52.794359 <6>[ 0.552525] PTP clock support registered
1253 19:05:52.799885 <6>[ 0.556766] EDAC MC: Ver: 3.0.0
1254 19:05:52.805408 <6>[ 0.560426] scmi_core: SCMI protocol bus registered
1255 19:05:52.805865 <6>[ 0.566031] FPGA manager framework
1256 19:05:52.810933 <6>[ 0.568785] Advanced Linux Sound Architecture Driver Initialized.
1257 19:05:52.816448 <6>[ 0.575751] vgaarb: loaded
1258 19:05:52.821967 <6>[ 0.578280] clocksource: Switched to clocksource arch_sys_counter
1259 19:05:52.827486 <5>[ 0.584438] VFS: Disk quotas dquot_6.6.0
1260 19:05:52.832966 <6>[ 0.588416] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1261 19:05:52.838475 <6>[ 0.595633] pnp: PnP ACPI: disabled
1262 19:05:52.844020 <6>[ 0.604119] NET: Registered PF_INET protocol family
1263 19:05:52.849507 <6>[ 0.604449] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1264 19:05:52.860599 <6>[ 0.614613] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1265 19:05:52.866061 <6>[ 0.620622] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1266 19:05:52.877167 <6>[ 0.628517] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1267 19:05:52.882698 <6>[ 0.636757] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1268 19:05:52.888176 <6>[ 0.644548] TCP: Hash tables configured (established 32768 bind 32768)
1269 19:05:52.893647 <6>[ 0.651028] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1270 19:05:52.904768 <6>[ 0.657876] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1271 19:05:52.910224 <6>[ 0.665298] NET: Registered PF_UNIX/PF_LOCAL protocol family
1272 19:05:52.915749 <6>[ 0.671386] RPC: Registered named UNIX socket transport module.
1273 19:05:52.921257 <6>[ 0.677164] RPC: Registered udp transport module.
1274 19:05:52.926801 <6>[ 0.682068] RPC: Registered tcp transport module.
1275 19:05:52.932284 <6>[ 0.686982] RPC: Registered tcp-with-tls transport module.
1276 19:05:52.937803 <6>[ 0.692676] RPC: Registered tcp NFSv4.1 backchannel transport module.
1277 19:05:52.943606 <6>[ 0.699325] PCI: CLS 0 bytes, default 64
1278 19:05:52.944073 <6>[ 0.703645] Unpacking initramfs...
1279 19:05:52.949121 <6>[ 0.712937] kvm [1]: nv: 554 coarse grained trap handlers
1280 19:05:52.954639 <6>[ 0.713251] kvm [1]: IPA Size Limit: 40 bits
1281 19:05:52.960204 <6>[ 0.718928] kvm [1]: vgic interrupt IRQ9
1282 19:05:52.965777 <6>[ 0.721618] kvm [1]: Hyp nVHE mode initialized successfully
1283 19:05:52.971208 <5>[ 0.728657] Initialise system trusted keyrings
1284 19:05:52.976782 <6>[ 0.732209] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1285 19:05:52.982295 <6>[ 0.738949] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1286 19:05:52.987880 <5>[ 0.744972] NFS: Registering the id_resolver key type
1287 19:05:52.993293 <5>[ 0.750015] Key type id_resolver registered
1288 19:05:52.998812 <5>[ 0.754373] Key type id_legacy registered
1289 19:05:53.004322 <6>[ 0.758626] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1290 19:05:53.009888 <6>[ 0.765501] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1291 19:05:53.017338 <6>[ 0.773280] 9p: Installing v9fs 9p2000 file system support
1292 19:05:53.055028 <5>[ 0.819553] Key type asymmetric registered
1293 19:05:53.060481 <5>[ 0.819595] Asymmetric key parser 'x509' registered
1294 19:05:53.071522 <6>[ 0.823454] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1295 19:05:53.072021 <6>[ 0.830979] io scheduler mq-deadline registered
1296 19:05:53.076986 <6>[ 0.835715] io scheduler kyber registered
1297 19:05:53.082549 <6>[ 0.839983] io scheduler bfq registered
1298 19:05:53.088989 <6>[ 0.845880] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1299 19:05:53.105478 <6>[ 0.866318] ledtrig-cpu: registered to indicate activity on CPUs
1300 19:05:53.137882 <6>[ 0.897480] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1301 19:05:53.157175 <6>[ 0.910539] Serial: 8250/16550 driver, 4 ports<6>[ 0.915156] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1302 19:05:53.162732 <6>[ 0.924778] printk: legacy console [ttyAML0] enabled
1303 19:05:53.168262 <6>[ 0.924778] printk: legacy console [ttyAML0] enabled
1304 19:05:53.173805 <6>[ 0.929577] printk: legacy bootconsole [meson0] disabled
1305 19:05:53.179353 <6>[ 0.929577] printk: legacy bootconsole [meson0] disabled
1306 19:05:53.184863 <6>[ 0.943077] msm_serial: driver initialized
1307 19:05:53.190373 <6>[ 0.945490] SuperH (H)SCI(F) driver initialized
1308 19:05:53.190807 <6>[ 0.950044] STM32 USART driver initialized
1309 19:05:53.196049 <5>[ 0.956223] random: crng init done
1310 19:05:53.203117 <6>[ 0.961746] loop: module loaded
1311 19:05:53.203611 <6>[ 0.963054] megasas: 07.727.03.00-rc1
1312 19:05:53.208604 <6>[ 0.972158] tun: Universal TUN/TAP device driver, 1.6
1313 19:05:53.214186 <6>[ 0.973361] thunder_xcv, ver 1.0
1314 19:05:53.219678 <6>[ 0.975349] thunder_bgx, ver 1.0
1315 19:05:53.220212 <6>[ 0.978793] nicpf, ver 1.0
1316 19:05:53.225274 <6>[ 0.983375] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1317 19:05:53.230904 <6>[ 0.989186] hns3: Copyright (c) 2017 Huawei Corporation.
1318 19:05:53.236351 <6>[ 0.994768] hclge is initializing
1319 19:05:53.241938 <6>[ 0.998313] e1000: Intel(R) PRO/1000 Network Driver
1320 19:05:53.247506 <6>[ 1.003391] e1000: Copyright (c) 1999-2006 Intel Corporation.
1321 19:05:53.252984 <6>[ 1.009412] e1000e: Intel(R) PRO/1000 Network Driver
1322 19:05:53.258564 <6>[ 1.014572] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1323 19:05:53.264155 <6>[ 1.020752] igb: Intel(R) Gigabit Ethernet Network Driver
1324 19:05:53.269626 <6>[ 1.026356] igb: Copyright (c) 2007-2014 Intel Corporation.
1325 19:05:53.275186 <6>[ 1.032193] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1326 19:05:53.280754 <6>[ 1.038664] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1327 19:05:53.286292 <6>[ 1.045412] sky2: driver version 1.30
1328 19:05:53.291908 <6>[ 1.050537] VFIO - User Level meta-driver version: 0.3
1329 19:05:53.297378 <6>[ 1.058004] usbcore: registered new interface driver usb-storage
1330 19:05:53.303388 <6>[ 1.064078] i2c_dev: i2c /dev entries driver
1331 19:05:53.316191 <6>[ 1.075226] sdhci: Secure Digital Host Controller Interface driver
1332 19:05:53.316841 <6>[ 1.076027] sdhci: Copyright(c) Pierre Ossman
1333 19:05:53.327281 <6>[ 1.081721] Synopsys Designware Multimedia Card Interface Driver
1334 19:05:53.332839 <6>[ 1.088272] sdhci-pltfm: SDHCI platform and OF driver helper
1335 19:05:53.333313 <6>[ 1.095930] meson-sm: secure-monitor enabled
1336 19:05:53.345746 <6>[ 1.098436] usbcore: registered new interface driver usbhid
1337 19:05:53.346259 <6>[ 1.103089] usbhid: USB HID core driver
1338 19:05:53.353253 <6>[ 1.117859] NET: Registered PF_PACKET protocol family
1339 19:05:53.358925 <6>[ 1.117952] 9pnet: Installing 9P2000 support
1340 19:05:53.365693 <5>[ 1.122125] Key type dns_resolver registered
1341 19:05:53.367889 <6>[ 1.133451] registered taskstats version 1
1342 19:05:53.373305 <5>[ 1.133609] Loading compiled-in X.509 certificates
1343 19:05:53.380386 <6>[ 1.142264] Demotion targets for Node 0: null
1344 19:05:53.406865 <6>[ 1.171352] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1345 19:05:53.412291 <6>[ 1.171390] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1346 19:05:53.423418 <4>[ 1.180556] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1347 19:05:53.428964 <4>[ 1.184140] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1348 19:05:53.434527 <6>[ 1.191647] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1349 19:05:53.440012 <6>[ 1.200928] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1350 19:05:53.451106 <6>[ 1.204462] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1351 19:05:53.462294 <6>[ 1.212433] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1352 19:05:53.467753 <6>[ 1.221964] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1353 19:05:53.473342 <6>[ 1.228178] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1354 19:05:53.478849 <6>[ 1.233798] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1355 19:05:53.484356 <6>[ 1.241682] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1356 19:05:53.489910 <6>[ 1.248906] hub 1-0:1.0: USB hub found
1357 19:05:53.495469 <6>[ 1.252449] hub 1-0:1.0: 2 ports detected
1358 19:05:53.501033 <6>[ 1.258533] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1359 19:05:53.506652 <6>[ 1.265423] hub 2-0:1.0: USB hub found
1360 19:05:53.511654 <6>[ 1.269002] hub 2-0:1.0: 1 port detected
1361 19:05:53.531747 <6>[ 1.293696] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1362 19:05:53.547292 <6>[ 1.308629] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1363 19:05:53.580835 <6>[ 1.341729] Trying to probe devices needed for running init ...
1364 19:05:53.742094 <6>[ 1.502318] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1365 19:05:53.882556 <6>[ 1.641604] mmc0: new ultra high speed SDR104 SDXC card at address e624
1366 19:05:53.889562 <6>[ 1.643954] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1367 19:05:53.890037 <6>[ 1.653804] mmcblk0: p1
1368 19:05:53.899726 <6>[ 1.662483] Freeing initrd memory: 22884K
1369 19:05:53.932238 <6>[ 1.696789] hub 1-1:1.0: USB hub found
1370 19:05:53.937987 <6>[ 1.697096] hub 1-1:1.0: 4 ports detected
1371 19:05:53.998065 <6>[ 1.758420] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1372 19:05:54.044992 <6>[ 1.809442] hub 2-1:1.0: USB hub found
1373 19:05:54.050566 <6>[ 1.810263] hub 2-1:1.0: 4 ports detected
1374 19:06:05.882044 <6>[ 13.646344] clk: Disabling unused clocks
1375 19:06:05.887382 <6>[ 13.646513] PM: genpd: Disabling unused power domains
1376 19:06:05.895622 <6>[ 13.650202] ALSA device list:
1377 19:06:05.895911 <6>[ 13.653405] No soundcards found.
1378 19:06:05.900991 <6>[ 13.665610] Freeing unused kernel memory: 10432K
1379 19:06:05.907421 <6>[ 13.665707] Run /init as init process
1380 19:06:05.913373 Loading, please wait...
1381 19:06:05.951119 Starting systemd-udevd version 252.22-1~deb12u1
1382 19:06:06.411243 <6>[ 14.175592] mc: Linux media interface: v0.10
1383 19:06:06.421678 <4>[ 14.178489] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1384 19:06:06.451106 <3>[ 14.207864] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1385 19:06:06.456675 <6>[ 14.218012] videodev: Linux video capture interface: v2.00
1386 19:06:06.462175 <6>[ 14.219716] meson-vrtc ff8000a8.rtc: registered as rtc0
1387 19:06:06.467664 <6>[ 14.223664] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1388 19:06:06.473205 <6>[ 14.225013] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1389 19:06:06.484320 <6>[ 14.242513] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1390 19:06:06.489886 <6>[ 14.244659] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1391 19:06:06.495402 <6>[ 14.251101] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1392 19:06:06.501005 <6>[ 14.257331] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1393 19:06:06.506543 <6>[ 14.264151] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1394 19:06:06.517835 <6>[ 14.266457] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1395 19:06:06.523318 <6>[ 14.270852] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1396 19:06:06.534327 <6>[ 14.270861] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1397 19:06:06.539886 <6>[ 14.270867] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1398 19:06:06.545401 <6>[ 14.270872] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1399 19:06:06.551009 <6>[ 14.307253] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1400 19:06:06.562097 <6>[ 14.314523] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1401 19:06:06.567601 <6>[ 14.322803] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1402 19:06:06.573093 <6>[ 14.327399] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1403 19:06:06.578657 <6>[ 14.333200] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1404 19:06:06.589667 <6>[ 14.333424] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1405 19:06:06.589982 <6>[ 14.346595] Registered IR keymap rc-empty
1406 19:06:06.600834 <6>[ 14.355624] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1407 19:06:06.606349 <3>[ 14.363331] meson-drm ff900000.vpu: DSI transceiver device is disabled
1408 19:06:06.617403 <6>[ 14.371176] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 kHz, changing to: 1000000 kHz
1409 19:06:06.628516 <4>[ 14.377996] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1410 19:06:06.639655 <6>[ 14.386696] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1411 19:06:06.645198 <6>[ 14.392520] panfrost ffe40000.gpu: clock rate = 24000000
1412 19:06:06.650713 <3>[ 14.404948] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1413 19:06:06.661846 <6>[ 14.406518] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1414 19:06:06.667425 <6>[ 14.406698] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 0
1415 19:06:06.672939 <6>[ 14.416306] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1416 19:06:06.678513 <6>[ 14.422243] usbcore: registered new device driver onboard-usb-dev
1417 19:06:06.684063 <6>[ 14.426846] rc rc0: sw decoder init
1418 19:06:06.689576 <6>[ 14.426880] meson-ir ff808000.ir: receiver initialized
1419 19:06:06.700656 <6>[ 14.428673] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1420 19:06:06.706200 <6>[ 14.455689] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1421 19:06:06.717550 <6>[ 14.460471] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1422 19:06:06.894836 <6>[ 14.479031] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1423 19:06:06.900293 <6>[ 14.485317] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 1
1424 19:06:06.905826 <6>[ 14.635051] Console: switching to colour frame buffer device 128x48
1425 19:06:06.914125 <6>[ 14.668340] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1426 19:06:07.148209 <6>[ 14.912738] hub 1-1:1.0: USB hub found
1427 19:06:07.153870 <6>[ 14.913046] hub 1-1:1.0: 4 ports detected
1428 19:06:07.295177 <4>[ 15.054299] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1429 19:06:07.300744 <3>[ 15.056657] onboard-usb-dev 1-1: Failed to suspend device, error -32
1430 19:06:07.307687 <3>[ 15.063097] onboard-usb-dev 1-1: can't set config #1, error -71
1431 19:06:07.323178 <4>[ 15.082305] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1432 19:06:07.328948 <3>[ 15.084672] onboard-usb-dev 1-1: Failed to suspend device, error -32
1433 19:06:07.335793 <6>[ 15.084677] onboard-usb-dev 1-1: USB disconnect, device number 2
1434 19:06:07.453776 <4>[ 15.218332] rc rc0: two consecutive events of type space
1435 19:06:07.488630 <6>[ 15.248744] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1436 19:06:07.621972 <6>[ 15.382328] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1437 19:06:07.820575 <6>[ 15.584914] hub 1-1:1.0: USB hub found
1438 19:06:07.826025 <6>[ 15.585246] hub 1-1:1.0: 4 ports detected
1439 19:06:07.833718 Begin: Loading essential drivers ... done.
1440 19:06:07.839270 Begin: Running /scripts/init-premount ... done.
1441 19:06:07.844934 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1442 19:06:07.858547 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1443 19:06:07.859054 Device /sys/class/net/end0 found
1444 19:06:07.859518 done.
1445 19:06:07.878526 Begin: Waiting up to 180 secs for any network device to become available ... done.
1446 19:06:07.924784 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.679475] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1447 19:06:07.925303
1448 19:06:08.013975 <6>[ 15.770399] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=29)
1449 19:06:08.027335 <6>[ 15.786468] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1450 19:06:08.032880 <6>[ 15.788659] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1451 19:06:08.042203 <6>[ 15.796014] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1452 19:06:09.961071 IP-Config: no response after 2 secs - giving up
1453 19:06:10.000875 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1454 19:06:11.000579 <6>[ 18.759020] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1455 19:06:12.211800 IP-Config: end0 guessed broadcast address 192.168.6.255
1456 19:06:12.216997 IP-Config: end0 complete (dhcp from 192.168.6.1):
1457 19:06:12.222552 address: 192.168.6.27 broadcast: 192.168.6.255 netmask: 255.255.255.0
1458 19:06:12.231712 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1459 19:06:12.237189 rootserver: 192.168.6.1 rootpath:
1460 19:06:12.237687 filename :
1461 19:06:12.343383 done.
1462 19:06:12.353363 Begin: Running /scripts/nfs-bottom ... done.
1463 19:06:12.369317 Begin: Running /scripts/init-bottom ... done.
1464 19:06:12.694401 <30>[ 20.454336] systemd[1]: System time before build time, advancing clock.
1465 19:06:12.747087 <6>[ 20.511521] NET: Registered PF_INET6 protocol family
1466 19:06:12.752641 <6>[ 20.513161] Segment Routing with IPv6
1467 19:06:12.757746 <6>[ 20.515039] In-situ OAM (IOAM) with IPv6
1468 19:06:12.832071 <30>[ 20.568816] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1469 19:06:12.837534 <30>[ 20.596187] systemd[1]: Detected architecture arm64.
1470 19:06:12.838058
1471 19:06:12.844900 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1472 19:06:12.845408
1473 19:06:12.855237 <30>[ 20.615973] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1474 19:06:13.505281 <30>[ 21.264718] systemd[1]: Queued start job for default target graphical.target.
1475 19:06:13.553780 <30>[ 21.312662] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1476 19:06:13.562346 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1477 19:06:13.573800 <30>[ 21.331274] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1478 19:06:13.580715 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1479 19:06:13.592332 <30>[ 21.351370] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1480 19:06:13.605765 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1481 19:06:13.611279 <30>[ 21.371023] systemd[1]: Created slice user.slice - User and Session Slice.
1482 19:06:13.617711 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1483 19:06:13.628831 <30>[ 21.386560] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1484 19:06:13.640246 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1485 19:06:13.651358 <30>[ 21.406495] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1486 19:06:13.657916 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1487 19:06:13.680073 <30>[ 21.426457] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1488 19:06:13.685638 <30>[ 21.440531] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1489 19:06:13.693174 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1490 19:06:13.704270 <30>[ 21.462376] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1491 19:06:13.711463 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1492 19:06:13.727264 <30>[ 21.486403] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1493 19:06:13.740976 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1494 19:06:13.746510 <30>[ 21.506419] systemd[1]: Reached target paths.target - Path Units.
1495 19:06:13.754933 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1496 19:06:13.760496 <30>[ 21.522386] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1497 19:06:13.772236 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1498 19:06:13.777764 <30>[ 21.538378] systemd[1]: Reached target slices.target - Slice Units.
1499 19:06:13.785898 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1500 19:06:13.791444 <30>[ 21.554393] systemd[1]: Reached target swap.target - Swaps.
1501 19:06:13.799296 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1502 19:06:13.811282 <30>[ 21.570412] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1503 19:06:13.820202 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1504 19:06:13.835446 <30>[ 21.594582] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1505 19:06:13.844704 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1506 19:06:13.858072 <30>[ 21.617196] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1507 19:06:13.870554 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1508 19:06:13.876084 <30>[ 21.635379] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1509 19:06:13.889115 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1510 19:06:13.894676 <30>[ 21.654736] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1511 19:06:13.901534 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1512 19:06:13.912624 <30>[ 21.671377] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1513 19:06:13.921431 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1514 19:06:13.933236 <30>[ 21.692361] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1515 19:06:13.938801 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1516 19:06:13.951493 <30>[ 21.710619] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1517 19:06:13.960057 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1518 19:06:13.999475 <30>[ 21.758516] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1519 19:06:14.006223 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1520 19:06:14.021199 <30>[ 21.780144] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1521 19:06:14.028664 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1522 19:06:14.045261 <30>[ 21.804347] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1523 19:06:14.052804 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1524 19:06:14.070031 <30>[ 21.823004] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1525 19:06:14.081106 <30>[ 21.838713] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1526 19:06:14.088236 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1527 19:06:14.104355 <30>[ 21.863449] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1528 19:06:14.112285 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1529 19:06:14.128188 <30>[ 21.887310] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1530 19:06:14.135846 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1531 19:06:14.154685 <30>[ 21.913545] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1532 19:06:14.165644 <6>[ 21.914156] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1533 19:06:14.170483 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
1534 19:06:14.182089 <30>[ 21.941161] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1535 19:06:14.190418 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1536 19:06:14.202117 <30>[ 21.961216] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1537 19:06:14.209414 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1538 19:06:14.220765 <6>[ 21.985315] fuse: init (API version 7.41)
1539 19:06:14.231764 <30>[ 21.985908] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1540 19:06:14.235721 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1541 19:06:14.255802 <30>[ 22.014885] systemd[1]: Starting systemd-journald.service - Journal Service...
1542 19:06:14.262189 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1543 19:06:14.283742 <30>[ 22.042740] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1544 19:06:14.291189 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1545 19:06:14.308495 <30>[ 22.067570] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1546 19:06:14.317878 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1547 19:06:14.332974 <30>[ 22.092039] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1548 19:06:14.341838 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1549 19:06:14.356274 <30>[ 22.115328] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1550 19:06:14.364379 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1551 19:06:14.387087 <30>[ 22.146057] systemd[1]: Started systemd-journald.service - Journal Service.
1552 19:06:14.393888 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1553 19:06:14.408605 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1554 19:06:14.416558 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1555 19:06:14.432541 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1556 19:06:14.449138 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1557 19:06:14.462188 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1558 19:06:14.474217 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1559 19:06:14.485844 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1560 19:06:14.498212 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1561 19:06:14.510053 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1562 19:06:14.525084 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1563 19:06:14.531397 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1564 19:06:14.545245 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1565 19:06:14.557404 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1566 19:06:14.570973 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1567 19:06:14.616287 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1568 19:06:14.631687 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1569 19:06:14.647888 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1570 19:06:14.666297 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1571 19:06:14.683042 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1572 19:06:14.690392 <46>[ 22.446584] systemd-journald[230]: Received client request to flush runtime journal.
1573 19:06:14.702053 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1574 19:06:14.721009 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1575 19:06:14.727275 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1576 19:06:14.740514 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1577 19:06:14.756766 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1578 19:06:14.768425 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1579 19:06:14.877216 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1580 19:06:14.915275 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1581 19:06:14.980185 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1582 19:06:15.023842 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1583 19:06:15.040341 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1584 19:06:15.055370 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1585 19:06:15.127161 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1586 19:06:15.141812 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1587 19:06:15.376805 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1588 19:06:15.447223 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1589 19:06:15.468236 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1590 19:06:15.479188 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1591 19:06:15.538640 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1592 19:06:15.563568 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1593 19:06:15.650188 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1594 19:06:15.658410 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1595 19:06:15.668203 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1596 19:06:15.680131 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1597 19:06:15.695112 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1598 19:06:15.714781 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1599 19:06:15.726379 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1600 19:06:15.743142 <46>[ 23.492629] systemd-journald[230]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1601 19:06:15.759384 <46>[ 23.506668] systemd-journald[230]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1602 19:06:15.771928 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1603 19:06:15.790898 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1604 19:06:15.857711 <5>[ 23.616824] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1605 19:06:15.875627 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1606 19:06:15.882520 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1607 19:06:15.933607 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1608 19:06:15.939190 <5>[ 23.700874] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1609 19:06:15.947664 <5>[ 23.701803] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1610 19:06:15.960429 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1611 19:06:15.971644 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Ba<4>[ 23.727461] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1612 19:06:15.978524 <6>[ 23.735398] cfg80211: failed to load regulatory.db
1613 19:06:15.979189 sic System.
1614 19:06:16.038368 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1615 19:06:16.056946 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1616 19:06:16.080959 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1617 19:06:16.092407 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1618 19:06:16.140295 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1619 19:06:16.151722 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1620 19:06:16.167950 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1621 19:06:16.223577 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1622 19:06:16.243407 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1623 19:06:16.259626 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1624 19:06:16.287857 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1625 19:06:16.301156 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1626 19:06:16.313300 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1627 19:06:16.323803 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1628 19:06:16.390926 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1629 19:06:16.403458 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1630 19:06:16.410558 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1631 19:06:16.420042 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1632 19:06:16.440271 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1633 19:06:16.446704 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1634 19:06:16.487465 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1635 19:06:16.535853 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1636 19:06:16.599048
1637 19:06:16.599647 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1638 19:06:16.600100
1639 19:06:16.606220 debian-bookworm-arm64 login: root (automatic login)
1640 19:06:16.606760
1641 19:06:16.731765 Linux debian-bookworm-arm64 6.12.0-rc6 #1 SMP PREEMPT Mon Nov 4 17:43:13 UTC 2024 aarch64
1642 19:06:16.732420
1643 19:06:16.737274 The programs included with the Debian GNU/Linux system are free software;
1644 19:06:16.742799 the exact distribution terms for each program are described in the
1645 19:06:16.748365 individual files in /usr/share/doc/*/copyright.
1646 19:06:16.748881
1647 19:06:16.753901 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1648 19:06:16.757033 permitted by applicable law.
1649 19:06:17.547785 Matched prompt #10: / #
1651 19:06:17.549345 Setting prompt string to ['/ #']
1652 19:06:17.549904 end: 2.4.4.1 login-action (duration 00:00:26) [common]
1654 19:06:17.551272 end: 2.4.4 auto-login-action (duration 00:00:26) [common]
1655 19:06:17.551794 start: 2.4.5 expect-shell-connection (timeout 00:03:16) [common]
1656 19:06:17.552271 Setting prompt string to ['/ #']
1657 19:06:17.552725 Forcing a shell prompt, looking for ['/ #']
1659 19:06:17.603689 / #
1660 19:06:17.604638 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1661 19:06:17.605144 Waiting using forced prompt support (timeout 00:02:30)
1662 19:06:17.609636
1663 19:06:17.610556 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1664 19:06:17.611195 start: 2.4.6 export-device-env (timeout 00:03:16) [common]
1665 19:06:17.611696 Sending with 10 millisecond of delay
1667 19:06:22.603267 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/935712/extract-nfsrootfs-36sgurkv'
1668 19:06:22.614258 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/935712/extract-nfsrootfs-36sgurkv'
1669 19:06:22.615050 Sending with 10 millisecond of delay
1671 19:06:24.714322 / # export NFS_SERVER_IP='192.168.6.2'
1672 19:06:24.725227 export NFS_SERVER_IP='192.168.6.2'
1673 19:06:24.726116 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1674 19:06:24.726711 end: 2.4 uboot-commands (duration 00:01:51) [common]
1675 19:06:24.727288 end: 2 uboot-action (duration 00:01:51) [common]
1676 19:06:24.727852 start: 3 lava-test-retry (timeout 00:06:49) [common]
1677 19:06:24.728475 start: 3.1 lava-test-shell (timeout 00:06:49) [common]
1678 19:06:24.728942 Using namespace: common
1680 19:06:24.830126 / # #
1681 19:06:24.831048 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1682 19:06:24.836056 #
1683 19:06:24.836829 Using /lava-935712
1685 19:06:24.937968 / # export SHELL=/bin/bash
1686 19:06:24.943781 export SHELL=/bin/bash
1688 19:06:25.045286 / # . /lava-935712/environment
1689 19:06:25.050377 . /lava-935712/environment
1691 19:06:25.154976 / # /lava-935712/bin/lava-test-runner /lava-935712/0
1692 19:06:25.155896 Test shell timeout: 10s (minimum of the action and connection timeout)
1693 19:06:25.160034 /lava-935712/bin/lava-test-runner /lava-935712/0
1694 19:06:25.353282 + export TESTRUN_ID=0_timesync-off
1695 19:06:25.361179 + TESTRUN_ID=0_timesync-off
1696 19:06:25.361673 + cd /lava-935712/0/tests/0_timesync-off
1697 19:06:25.362101 ++ cat uuid
1698 19:06:25.367283 + UUID=935712_1.6.2.4.1
1699 19:06:25.367761 + set +x
1700 19:06:25.375864 <LAVA_SIGNAL_STARTRUN 0_timesync-off 935712_1.6.2.4.1>
1701 19:06:25.376375 + systemctl stop systemd-timesyncd
1702 19:06:25.377086 Received signal: <STARTRUN> 0_timesync-off 935712_1.6.2.4.1
1703 19:06:25.377524 Starting test lava.0_timesync-off (935712_1.6.2.4.1)
1704 19:06:25.378051 Skipping test definition patterns.
1705 19:06:25.435505 + set +x
1706 19:06:25.436124 <LAVA_SIGNAL_ENDRUN 0_timesync-off 935712_1.6.2.4.1>
1707 19:06:25.436814 Received signal: <ENDRUN> 0_timesync-off 935712_1.6.2.4.1
1708 19:06:25.437302 Ending use of test pattern.
1709 19:06:25.437713 Ending test lava.0_timesync-off (935712_1.6.2.4.1), duration 0.06
1711 19:06:25.535566 + export TESTRUN_ID=1_kselftest-alsa
1712 19:06:25.543838 + TESTRUN_ID=1_kselftest-alsa
1713 19:06:25.544394 + cd /lava-935712/0/tests/1_kselftest-alsa
1714 19:06:25.544846 ++ cat uuid
1715 19:06:25.549738 + UUID=935712_1.6.2.4.5
1716 19:06:25.550251 + set +x
1717 19:06:25.555273 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 935712_1.6.2.4.5>
1718 19:06:25.555798 + cd ./automated/linux/kselftest/
1719 19:06:25.556577 Received signal: <STARTRUN> 1_kselftest-alsa 935712_1.6.2.4.5
1720 19:06:25.557052 Starting test lava.1_kselftest-alsa (935712_1.6.2.4.5)
1721 19:06:25.557563 Skipping test definition patterns.
1722 19:06:25.582912 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/pm/testing/v6.12-rc6-98-g57d5fb99dade/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g pm -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1723 19:06:25.610333 INFO: install_deps skipped
1724 19:06:25.727645 --2024-11-04 19:06:25-- http://storage.kernelci.org/pm/testing/v6.12-rc6-98-g57d5fb99dade/arm64/defconfig/gcc-12/kselftest.tar.xz
1725 19:06:25.747520 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1726 19:06:25.883723 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1727 19:06:26.022018 HTTP request sent, awaiting response... 200 OK
1728 19:06:26.022634 Length: 6928428 (6.6M) [application/octet-stream]
1729 19:06:26.027550 Saving to: 'kselftest_armhf.tar.gz'
1730 19:06:26.028067
1731 19:06:27.144419
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 47.54K 178KB/s
kselftest_armhf.tar 3%[ ] 216.29K 403KB/s
kselftest_armhf.tar 13%[=> ] 893.67K 1.09MB/s
kselftest_armhf.tar 53%[=========> ] 3.51M 3.27MB/s
kselftest_armhf.tar 100%[===================>] 6.61M 5.91MB/s in 1.1s
1732 19:06:27.145070
1733 19:06:27.239426 2024-11-04 19:06:27 (5.91 MB/s) - 'kselftest_armhf.tar.gz' saved [6928428/6928428]
1734 19:06:27.240112
1735 19:06:36.180816 skiplist:
1736 19:06:36.181473 ========================================
1737 19:06:36.186428 ========================================
1738 19:06:36.223839 alsa:mixer-test
1739 19:06:36.224439 alsa:pcm-test
1740 19:06:36.224880 alsa:test-pcmtest-driver
1741 19:06:36.228095 alsa:utimer-test
1742 19:06:36.242964 ============== Tests to run ===============
1743 19:06:36.243493 alsa:mixer-test
1744 19:06:36.248300 alsa:pcm-test
1745 19:06:36.248838 alsa:test-pcmtest-driver
1746 19:06:36.249265 alsa:utimer-test
1747 19:06:36.255570 ===========End Tests to run ===============
1748 19:06:36.256085 shardfile-alsa pass
1749 19:06:36.381153 <12>[ 44.143468] kselftest: Running tests in alsa
1750 19:06:36.385592 TAP version 13
1751 19:06:36.400700 1..4
1752 19:06:36.420672 # timeout set to 45
1753 19:06:36.421264 # selftests: alsa: mixer-test
1754 19:06:36.585351 # TAP version 13
1755 19:06:36.585937 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1756 19:06:36.590939 # 1..427
1757 19:06:36.591417 # ok 1 get_value.LCALTA.60
1758 19:06:36.591836 # # LCALTA.60 TDMOUT_A SRC SEL
1759 19:06:36.596358 # ok 2 name.LCALTA.60
1760 19:06:36.596830 # ok 3 write_default.LCALTA.60
1761 19:06:36.601910 # ok 4 write_valid.LCALTA.60
1762 19:06:36.602377 # ok 5 write_invalid.LCALTA.60
1763 19:06:36.607440 # ok 6 event_missing.LCALTA.60
1764 19:06:36.607910 # ok 7 event_spurious.LCALTA.60
1765 19:06:36.613102 # ok 8 get_value.LCALTA.59
1766 19:06:36.613565 # # LCALTA.59 TDMOUT_B SRC SEL
1767 19:06:36.618532 # ok 9 name.LCALTA.59
1768 19:06:36.618992 # ok 10 write_default.LCALTA.59
1769 19:06:36.624111 # ok 11 write_valid.LCALTA.59
1770 19:06:36.624582 # ok 12 write_invalid.LCALTA.59
1771 19:06:36.629632 # ok 13 event_missing.LCALTA.59
1772 19:06:36.630105 # ok 14 event_spurious.LCALTA.59
1773 19:06:36.635161 # ok 15 get_value.LCALTA.58
1774 19:06:36.635615 # # LCALTA.58 TDMOUT_C SRC SEL
1775 19:06:36.640734 # ok 16 name.LCALTA.58
1776 19:06:36.641186 # ok 17 write_default.LCALTA.58
1777 19:06:36.646271 # ok 18 write_valid.LCALTA.58
1778 19:06:36.646719 # ok 19 write_invalid.LCALTA.58
1779 19:06:36.651968 # ok 20 event_missing.LCALTA.58
1780 19:06:36.652458 # ok 21 event_spurious.LCALTA.58
1781 19:06:36.657396 # ok 22 get_value.LCALTA.57
1782 19:06:36.657868 # # LCALTA.57 TDMIN_A SRC SEL
1783 19:06:36.658281 # ok 23 name.LCALTA.57
1784 19:06:36.663075 # ok 24 write_default.LCALTA.57
1785 19:06:36.663535 # ok 25 write_valid.LCALTA.57
1786 19:06:36.668605 # ok 26 write_invalid.LCALTA.57
1787 19:06:36.669108 # ok 27 event_missing.LCALTA.57
1788 19:06:36.674187 # ok 28 event_spurious.LCALTA.57
1789 19:06:36.674656 # ok 29 get_value.LCALTA.56
1790 19:06:36.679637 # # LCALTA.56 TDMIN_B SRC SEL
1791 19:06:36.680131 # ok 30 name.LCALTA.56
1792 19:06:36.685015 # ok 31 write_default.LCALTA.56
1793 19:06:36.685479 # ok 32 write_valid.LCALTA.56
1794 19:06:36.690562 # ok 33 write_invalid.LCALTA.56
1795 19:06:36.691018 # ok 34 event_missing.LCALTA.56
1796 19:06:36.696114 # ok 35 event_spurious.LCALTA.56
1797 19:06:36.707307 # ok 36 get_valu<3>[ 44.459082] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1798 19:06:36.707798 e.LCALTA.55
1799 19:06:36.712891 # # LCALTA.55 TDMIN_C SRC SEL
1800 19:06:36.713380 # ok 37 name.LCALTA.55
1801 19:06:36.718282 # ok 38 write_default.LCALTA.55
1802 19:06:36.718736 # ok 39 write_valid.LCALTA.55
1803 19:06:36.723814 # ok 40 write_invalid.LCALTA.55
1804 19:06:36.724288 # ok 41 event_missing.LCALTA.55
1805 19:06:36.729352 # ok 42 event_spurious.LCALTA.55
1806 19:06:36.729799 # ok 43 get_value.LCALTA.54
1807 19:06:36.734908 # # LCALTA.54 ACODEC Left DAC Sel
1808 19:06:36.735363 # ok 44 name.LCALTA.54
1809 19:06:36.740443 # ok 45 write_default.LCALTA.54
1810 19:06:36.740891 # ok 46 write_valid.LCALTA.54
1811 19:06:36.746004 # ok 47 write_invalid.LCALTA.54
1812 19:06:36.746452 # ok 48 event_missing.LCALTA.54
1813 19:06:36.751556 # ok 49 event_spurious.LCALTA.54
1814 19:06:36.752040 # ok 50 get_value.LCALTA.53
1815 19:06:36.757101 # # LCALTA.53 ACODEC Right DAC Sel
1816 19:06:36.757552 # ok 51 name.LCALTA.53
1817 19:06:36.762638 # ok 52 write_default.LCALTA.53
1818 19:06:36.763083 # ok 53 write_valid.LCALTA.53
1819 19:06:36.768213 # ok 54 write_invalid.LCALTA.53
1820 19:06:36.768666 # ok 55 event_missing.LCALTA.53
1821 19:06:36.773830 # ok 56 event_spurious.LCALTA.53
1822 19:06:36.774274 # ok 57 get_value.LCALTA.52
1823 19:06:36.779304 # # LCALTA.52 TOACODEC OUT EN Switch
1824 19:06:36.779753 # ok 58 name.LCALTA.52
1825 19:06:36.784854 # ok 59 write_default.LCALTA.52
1826 19:06:36.785299 # ok 60 write_valid.LCALTA.52
1827 19:06:36.790390 # ok 61 write_invalid.LCALTA.52
1828 19:06:36.790835 # ok 62 event_missing.LCALTA.52
1829 19:06:36.795940 # ok 63 event_spurious.LCALTA.52
1830 19:06:36.796413 # ok 64 get_value.LCALTA.51
1831 19:06:36.801485 # # LCALTA.51 TOACODEC SRC
1832 19:06:36.801929 # ok 65 name.LCALTA.51
1833 19:06:36.807043 # ok 66 write_default.LCALTA.51
1834 19:06:36.807492 # ok 67 write_valid.LCALTA.51
1835 19:06:36.812608 # ok 68 write_invalid.LCALTA.51
1836 19:06:36.813051 # ok 69 event_missing.LCALTA.51
1837 19:06:36.818128 # ok 70 event_spurious.LCALTA.51
1838 19:06:36.818572 # ok 71 get_value.LCALTA.50
1839 19:06:36.823685 # # LCALTA.50 TOHDMITX SPDIF SRC
1840 19:06:36.824176 # ok 72 name.LCALTA.50
1841 19:06:36.824594 # ok 73 write_default.LCALTA.50
1842 19:06:36.829233 # ok 74 write_valid.LCALTA.50
1843 19:06:36.829703 # ok 75 write_invalid.LCALTA.50
1844 19:06:36.834837 # ok 76 event_missing.LCALTA.50
1845 19:06:36.840346 # ok 77 event_spurious.LCALTA.50
1846 19:06:36.840836 # ok 78 get_value.LCALTA.49
1847 19:06:36.841254 # # LCALTA.49 TOHDMITX Switch
1848 19:06:36.845897 # ok 79 name.LCALTA.49
1849 19:06:36.846384 # ok 80 write_default.LCALTA.49
1850 19:06:36.851441 # ok 81 write_valid.LCALTA.49
1851 19:06:36.851930 # ok 82 write_invalid.LCALTA.49
1852 19:06:36.856988 # ok 83 event_missing.LCALTA.49
1853 19:06:36.857486 # ok 84 event_spurious.LCALTA.49
1854 19:06:36.862543 # ok 85 get_value.LCALTA.48
1855 19:06:36.863034 # # LCALTA.48 TOHDMITX I2S SRC
1856 19:06:36.868093 # ok 86 name.LCALTA.48
1857 19:06:36.868590 # ok 87 write_default.LCALTA.48
1858 19:06:36.873629 # ok 88 write_valid.LCALTA.48
1859 19:06:36.874119 # ok 89 write_invalid.LCALTA.48
1860 19:06:36.879175 # ok 90 event_missing.LCALTA.48
1861 19:06:36.879661 # ok 91 event_spurious.LCALTA.48
1862 19:06:36.884720 # ok 92 get_value.LCALTA.47
1863 19:06:36.885205 # # LCALTA.47 TODDR_C SRC SEL
1864 19:06:36.890226 # ok 93 name.LCALTA.47
1865 19:06:36.890701 # ok 94 write_default.LCALTA.47
1866 19:06:36.895853 # ok 95 write_valid.LCALTA.47
1867 19:06:36.896365 # ok 96 write_invalid.LCALTA.47
1868 19:06:36.901346 # ok 97 event_missing.LCALTA.47
1869 19:06:36.901820 # ok 98 event_spurious.LCALTA.47
1870 19:06:36.906909 # ok 99 get_value.LCALTA.46
1871 19:06:36.907388 # # LCALTA.46 TODDR_B SRC SEL
1872 19:06:36.907802 # ok 100 name.LCALTA.46
1873 19:06:36.912445 # ok 101 write_default.LCALTA.46
1874 19:06:36.917979 # ok 102 write_valid.LCALTA.46
1875 19:06:36.918462 # ok 103 write_invalid.LCALTA.46
1876 19:06:36.923525 # ok 104 event_missing.LCALTA.46
1877 19:06:36.924037 # ok 105 event_spurious.LCALTA.46
1878 19:06:36.929094 # ok 106 get_value.LCALTA.45
1879 19:06:36.929563 # # LCALTA.45 TODDR_A SRC SEL
1880 19:06:36.929974 # ok 107 name.LCALTA.45
1881 19:06:36.934633 # ok 108 write_default.LCALTA.45
1882 19:06:36.940196 # ok 109 write_valid.LCALTA.45
1883 19:06:36.940672 # ok 110 write_invalid.LCALTA.45
1884 19:06:36.945737 # ok 111 event_missing.LCALTA.45
1885 19:06:36.946210 # ok 112 event_spurious.LCALTA.45
1886 19:06:36.951262 # ok 113 get_value.LCALTA.44
1887 19:06:36.951724 # # LCALTA.44 FRDDR_C SINK 3 SEL
1888 19:06:36.956860 # ok 114 name.LCALTA.44
1889 19:06:36.957324 # ok 115 write_default.LCALTA.44
1890 19:06:36.962352 # ok 116 write_valid.LCALTA.44
1891 19:06:36.962804 # ok 117 write_invalid.LCALTA.44
1892 19:06:36.967888 # ok 118 event_missing.LCALTA.44
1893 19:06:36.968369 # ok 119 event_spurious.LCALTA.44
1894 19:06:36.973446 # ok 120 get_value.LCALTA.43
1895 19:06:36.973887 # # LCALTA.43 FRDDR_C SINK 2 SEL
1896 19:06:36.978986 # ok 121 name.LCALTA.43
1897 19:06:36.979428 # ok 122 write_default.LCALTA.43
1898 19:06:36.984529 # ok 123 write_valid.LCALTA.43
1899 19:06:36.984973 # ok 124 write_invalid.LCALTA.43
1900 19:06:36.990081 # ok 125 event_missing.LCALTA.43
1901 19:06:36.990523 # ok 126 event_spurious.LCALTA.43
1902 19:06:36.995624 # ok 127 get_value.LCALTA.42
1903 19:06:36.996096 # # LCALTA.42 FRDDR_C SINK 1 SEL
1904 19:06:37.001163 # ok 128 name.LCALTA.42
1905 19:06:37.001604 # ok 129 write_default.LCALTA.42
1906 19:06:37.006725 # ok 130 write_valid.LCALTA.42
1907 19:06:37.007162 # ok 131 write_invalid.LCALTA.42
1908 19:06:37.012255 # ok 132 event_missing.LCALTA.42
1909 19:06:37.012697 # ok 133 event_spurious.LCALTA.42
1910 19:06:37.017848 # ok 134 get_value.LCALTA.41
1911 19:06:37.018288 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
1912 19:06:37.023332 # ok 135 name.LCALTA.41
1913 19:06:37.023771 # ok 136 write_default.LCALTA.41
1914 19:06:37.028896 # ok 137 write_valid.LCALTA.41
1915 19:06:37.029335 # ok 138 write_invalid.LCALTA.41
1916 19:06:37.034463 # ok 139 event_missing.LCALTA.41
1917 19:06:37.034906 # ok 140 event_spurious.LCALTA.41
1918 19:06:37.040029 # ok 141 get_value.LCALTA.40
1919 19:06:37.040476 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
1920 19:06:37.045542 # ok 142 name.LCALTA.40
1921 19:06:37.045982 # ok 143 write_default.LCALTA.40
1922 19:06:37.051099 # ok 144 write_valid.LCALTA.40
1923 19:06:37.051541 # ok 145 write_invalid.LCALTA.40
1924 19:06:37.056752 # ok 146 event_missing.LCALTA.40
1925 19:06:37.057201 # ok 147 event_spurious.LCALTA.40
1926 19:06:37.062206 # ok 148 get_value.LCALTA.39
1927 19:06:37.067705 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
1928 19:06:37.068179 # ok 149 name.LCALTA.39
1929 19:06:37.068589 # ok 150 write_default.LCALTA.39
1930 19:06:37.073289 # ok 151 write_valid.LCALTA.39
1931 19:06:37.073787 # ok 152 write_invalid.LCALTA.39
1932 19:06:37.078867 # ok 153 event_missing.LCALTA.39
1933 19:06:37.084404 # ok 154 event_spurious.LCALTA.39
1934 19:06:37.084861 # ok 155 get_value.LCALTA.38
1935 19:06:37.089959 # # LCALTA.38 FRDDR_B SINK 3 SEL
1936 19:06:37.090414 # ok 156 name.LCALTA.38
1937 19:06:37.090830 # ok 157 write_default.LCALTA.38
1938 19:06:37.095479 # ok 158 write_valid.LCALTA.38
1939 19:06:37.095934 # ok 159 write_invalid.LCALTA.38
1940 19:06:37.101007 # ok 160 event_missing.LCALTA.38
1941 19:06:37.106560 # ok 161 event_spurious.LCALTA.38
1942 19:06:37.107008 # ok 162 get_value.LCALTA.37
1943 19:06:37.112141 # # LCALTA.37 FRDDR_B SINK 2 SEL
1944 19:06:37.112591 # ok 163 name.LCALTA.37
1945 19:06:37.112998 # ok 164 write_default.LCALTA.37
1946 19:06:37.117647 # ok 165 write_valid.LCALTA.37
1947 19:06:37.123166 # ok 166 write_invalid.LCALTA.37
1948 19:06:37.123613 # ok 167 event_missing.LCALTA.37
1949 19:06:37.128749 # ok 168 event_spurious.LCALTA.37
1950 19:06:37.129206 # ok 169 get_value.LCALTA.36
1951 19:06:37.134288 # # LCALTA.36 FRDDR_B SINK 1 SEL
1952 19:06:37.134735 # ok 170 name.LCALTA.36
1953 19:06:37.139870 # ok 171 write_default.LCALTA.36
1954 19:06:37.140349 # ok 172 write_valid.LCALTA.36
1955 19:06:37.145408 # ok 173 write_invalid.LCALTA.36
1956 19:06:37.145876 # ok 174 event_missing.LCALTA.36
1957 19:06:37.150949 # ok 175 event_spurious.LCALTA.36
1958 19:06:37.151418 # ok 176 get_value.LCALTA.35
1959 19:06:37.156485 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
1960 19:06:37.156943 # ok 177 name.LCALTA.35
1961 19:06:37.162034 # ok 178 write_default.LCALTA.35
1962 19:06:37.162489 # ok 179 write_valid.LCALTA.35
1963 19:06:37.167608 # ok 180 write_invalid.LCALTA.35
1964 19:06:37.168106 # ok 181 event_missing.LCALTA.35
1965 19:06:37.173157 # ok 182 event_spurious.LCALTA.35
1966 19:06:37.173637 # ok 183 get_value.LCALTA.34
1967 19:06:37.178695 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
1968 19:06:37.179181 # ok 184 name.LCALTA.34
1969 19:06:37.184245 # ok 185 write_default.LCALTA.34
1970 19:06:37.184725 # ok 186 write_valid.LCALTA.34
1971 19:06:37.189791 # ok 187 write_invalid.LCALTA.34
1972 19:06:37.190269 # ok 188 event_missing.LCALTA.34
1973 19:06:37.195317 # ok 189 event_spurious.LCALTA.34
1974 19:06:37.195789 # ok 190 get_value.LCALTA.33
1975 19:06:37.200912 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
1976 19:06:37.201391 # ok 191 name.LCALTA.33
1977 19:06:37.206425 # ok 192 write_default.LCALTA.33
1978 19:06:37.206896 # ok 193 write_valid.LCALTA.33
1979 19:06:37.211965 # ok 194 write_invalid.LCALTA.33
1980 19:06:37.212484 # ok 195 event_missing.LCALTA.33
1981 19:06:37.217553 # ok 196 event_spurious.LCALTA.33
1982 19:06:37.218046 # ok 197 get_value.LCALTA.32
1983 19:06:37.223070 # # LCALTA.32 FRDDR_A SINK 3 SEL
1984 19:06:37.223548 # ok 198 name.LCALTA.32
1985 19:06:37.228596 # ok 199 write_default.LCALTA.32
1986 19:06:37.229052 # ok 200 write_valid.LCALTA.32
1987 19:06:37.234155 # ok 201 write_invalid.LCALTA.32
1988 19:06:37.234622 # ok 202 event_missing.LCALTA.32
1989 19:06:37.239718 # ok 203 event_spurious.LCALTA.32
1990 19:06:37.240243 # ok 204 get_value.LCALTA.31
1991 19:06:37.245247 # # LCALTA.31 FRDDR_A SINK 2 SEL
1992 19:06:37.245719 # ok 205 name.LCALTA.31
1993 19:06:37.250835 # ok 206 write_default.LCALTA.31
1994 19:06:37.251338 # ok 207 write_valid.LCALTA.31
1995 19:06:37.256366 # ok 208 write_invalid.LCALTA.31
1996 19:06:37.256875 # ok 209 event_missing.LCALTA.31
1997 19:06:37.261925 # ok 210 event_spurious.LCALTA.31
1998 19:06:37.262390 # ok 211 get_value.LCALTA.30
1999 19:06:37.267421 # # LCALTA.30 FRDDR_A SINK 1 SEL
2000 19:06:37.267880 # ok 212 name.LCALTA.30
2001 19:06:37.272975 # ok 213 write_default.LCALTA.30
2002 19:06:37.273421 # ok 214 write_valid.LCALTA.30
2003 19:06:37.278528 # ok 215 write_invalid.LCALTA.30
2004 19:06:37.284080 # ok 216 event_missing.LCALTA.30
2005 19:06:37.284527 # ok 217 event_spurious.LCALTA.30
2006 19:06:37.289606 # ok 218 get_value.LCALTA.29
2007 19:06:37.290053 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2008 19:06:37.295150 # ok 219 name.LCALTA.29
2009 19:06:37.295593 # ok 220 write_default.LCALTA.29
2010 19:06:37.300704 # ok 221 write_valid.LCALTA.29
2011 19:06:37.301150 # ok 222 write_invalid.LCALTA.29
2012 19:06:37.306271 # ok 223 event_missing.LCALTA.29
2013 19:06:37.306735 # ok 224 event_spurious.LCALTA.29
2014 19:06:37.311814 # ok 225 get_value.LCALTA.28
2015 19:06:37.312295 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2016 19:06:37.317358 # ok 226 name.LCALTA.28
2017 19:06:37.317808 # ok 227 write_default.LCALTA.28
2018 19:06:37.322906 # ok 228 write_valid.LCALTA.28
2019 19:06:37.323348 # ok 229 write_invalid.LCALTA.28
2020 19:06:37.328417 # ok 230 event_missing.LCALTA.28
2021 19:06:37.328854 # ok 231 event_spurious.LCALTA.28
2022 19:06:37.333979 # ok 232 get_value.LCALTA.27
2023 19:06:37.334427 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2024 19:06:37.339536 # ok 233 name.LCALTA.27
2025 19:06:37.339976 # ok 234 write_default.LCALTA.27
2026 19:06:37.345092 # ok 235 write_valid.LCALTA.27
2027 19:06:37.345562 # ok 236 write_invalid.LCALTA.27
2028 19:06:37.350641 # ok 237 event_missing.LCALTA.27
2029 19:06:37.351090 # ok 238 event_spurious.LCALTA.27
2030 19:06:37.356201 # ok 239 get_value.LCALTA.26
2031 19:06:37.356642 # # LCALTA.26 ELD
2032 19:06:37.361731 # ok 240 name.LCALTA.26
2033 19:06:37.362179 # # ELD is not writeable
2034 19:06:37.367267 # ok 241 # SKIP write_default.LCALTA.26
2035 19:06:37.367720 # # ELD is not writeable
2036 19:06:37.372825 # ok 242 # SKIP write_valid.LCALTA.26
2037 19:06:37.373281 # # ELD is not writeable
2038 19:06:37.378340 # ok 243 # SKIP write_invalid.LCALTA.26
2039 19:06:37.378789 # ok 244 event_missing.LCALTA.26
2040 19:06:37.383895 # ok 245 event_spurious.LCALTA.26
2041 19:06:37.384367 # ok 246 get_value.LCALTA.25
2042 19:06:37.389456 # # LCALTA.25 IEC958 Playback Default
2043 19:06:37.389905 # ok 247 name.LCALTA.25
2044 19:06:37.395046 # ok 248 write_default.LCALTA.25
2045 19:06:37.395566 # ok 249 # SKIP write_valid.LCALTA.25
2046 19:06:37.400567 # ok 250 # SKIP write_invalid.LCALTA.25
2047 19:06:37.406106 # ok 251 event_missing.LCALTA.25
2048 19:06:37.406576 # ok 252 event_spurious.LCALTA.25
2049 19:06:37.411655 # ok 253 get_value.LCALTA.24
2050 19:06:37.412154 # # LCALTA.24 IEC958 Playback Mask
2051 19:06:37.412571 # ok 254 name.LCALTA.24
2052 19:06:37.417205 # # IEC958 Playback Mask is not writeable
2053 19:06:37.422739 # ok 255 # SKIP write_default.LCALTA.24
2054 19:06:37.423206 # # IEC958 Playback Mask is not writeable
2055 19:06:37.428293 # ok 256 # SKIP write_valid.LCALTA.24
2056 19:06:37.433831 # # IEC958 Playback Mask is not writeable
2057 19:06:37.434301 # ok 257 # SKIP write_invalid.LCALTA.24
2058 19:06:37.439389 # ok 258 event_missing.LCALTA.24
2059 19:06:37.439851 # ok 259 event_spurious.LCALTA.24
2060 19:06:37.444940 # ok 260 get_value.LCALTA.23
2061 19:06:37.445409 # # LCALTA.23 Playback Channel Map
2062 19:06:37.450462 # ok 261 name.LCALTA.23
2063 19:06:37.456048 # # Playback Channel Map is not writeable
2064 19:06:37.456514 # ok 262 # SKIP write_default.LCALTA.23
2065 19:06:37.461596 # # Playback Channel Map is not writeable
2066 19:06:37.462066 # ok 263 # SKIP write_valid.LCALTA.23
2067 19:06:37.467093 # # Playback Channel Map is not writeable
2068 19:06:37.472671 # ok 264 # SKIP write_invalid.LCALTA.23
2069 19:06:37.473131 # ok 265 event_missing.LCALTA.23
2070 19:06:37.478210 # ok 266 event_spurious.LCALTA.23
2071 19:06:37.478665 # ok 267 get_value.LCALTA.22
2072 19:06:37.483737 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2073 19:06:37.484218 # ok 268 name.LCALTA.22
2074 19:06:37.489292 # ok 269 write_default.LCALTA.22
2075 19:06:37.489743 # ok 270 write_valid.LCALTA.22
2076 19:06:37.494861 # ok 271 write_invalid.LCALTA.22
2077 19:06:37.495308 # ok 272 event_missing.LCALTA.22
2078 19:06:37.500392 # ok 273 event_spurious.LCALTA.22
2079 19:06:37.505916 # ok 274 get_value.LCALTA.21
2080 19:06:37.506365 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2081 19:06:37.506777 # ok 275 name.LCALTA.21
2082 19:06:37.511510 # ok 276 write_default.LCALTA.21
2083 19:06:37.517023 # ok 277 write_valid.LCALTA.21
2084 19:06:37.517471 # ok 278 write_invalid.LCALTA.21
2085 19:06:37.522572 # ok 279 event_missing.LCALTA.21
2086 19:06:37.523016 # ok 280 event_spurious.LCALTA.21
2087 19:06:37.528133 # ok 281 get_value.LCALTA.20
2088 19:06:37.528593 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2089 19:06:37.533661 # ok 282 name.LCALTA.20
2090 19:06:37.534111 # ok 283 write_default.LCALTA.20
2091 19:06:37.539206 # ok 284 write_valid.LCALTA.20
2092 19:06:37.539654 # ok 285 write_invalid.LCALTA.20
2093 19:06:37.544788 # ok 286 event_missing.LCALTA.20
2094 19:06:37.545239 # ok 287 event_spurious.LCALTA.20
2095 19:06:37.550315 # ok 288 get_value.LCALTA.19
2096 19:06:37.550761 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2097 19:06:37.555855 # ok 289 name.LCALTA.19
2098 19:06:37.556334 # ok 290 write_default.LCALTA.19
2099 19:06:37.561401 # ok 291 write_valid.LCALTA.19
2100 19:06:37.561847 # ok 292 write_invalid.LCALTA.19
2101 19:06:37.566945 # ok 293 event_missing.LCALTA.19
2102 19:06:37.567394 # ok 294 event_spurious.LCALTA.19
2103 19:06:37.572500 # ok 295 get_value.LCALTA.18
2104 19:06:37.572946 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2105 19:06:37.578045 # ok 296 name.LCALTA.18
2106 19:06:37.578494 # ok 297 write_default.LCALTA.18
2107 19:06:37.583585 # ok 298 write_valid.LCALTA.18
2108 19:06:37.584063 # ok 299 write_invalid.LCALTA.18
2109 19:06:37.589111 # ok 300 event_missing.LCALTA.18
2110 19:06:37.589562 # ok 301 event_spurious.LCALTA.18
2111 19:06:37.594701 # ok 302 get_value.LCALTA.17
2112 19:06:37.600231 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2113 19:06:37.600683 # ok 303 name.LCALTA.17
2114 19:06:37.601095 # ok 304 write_default.LCALTA.17
2115 19:06:37.605777 # ok 305 write_valid.LCALTA.17
2116 19:06:37.611328 # ok 306 write_invalid.LCALTA.17
2117 19:06:37.611775 # ok 307 event_missing.LCALTA.17
2118 19:06:37.616873 # ok 308 event_spurious.LCALTA.17
2119 19:06:37.617326 # ok 309 get_value.LCALTA.16
2120 19:06:37.622412 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2121 19:06:37.622860 # ok 310 name.LCALTA.16
2122 19:06:37.628056 # ok 311 write_default.LCALTA.16
2123 19:06:37.628528 # ok 312 write_valid.LCALTA.16
2124 19:06:37.633507 # ok 313 write_invalid.LCALTA.16
2125 19:06:37.633955 # ok 314 event_missing.LCALTA.16
2126 19:06:37.639061 # ok 315 event_spurious.LCALTA.16
2127 19:06:37.639511 # ok 316 get_value.LCALTA.15
2128 19:06:37.644600 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2129 19:06:37.645049 # ok 317 name.LCALTA.15
2130 19:06:37.650127 # ok 318 write_default.LCALTA.15
2131 19:06:37.650573 # ok 319 write_valid.LCALTA.15
2132 19:06:37.655662 # ok 320 write_invalid.LCALTA.15
2133 19:06:37.656137 # ok 321 event_missing.LCALTA.15
2134 19:06:37.661223 # ok 322 event_spurious.LCALTA.15
2135 19:06:37.661668 # ok 323 get_value.LCALTA.14
2136 19:06:37.666799 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2137 19:06:37.667248 # ok 324 name.LCALTA.14
2138 19:06:37.672334 # ok 325 write_default.LCALTA.14
2139 19:06:37.672789 # ok 326 write_valid.LCALTA.14
2140 19:06:37.677980 # ok 327 write_invalid.LCALTA.14
2141 19:06:37.678433 # ok 328 event_missing.LCALTA.14
2142 19:06:37.683420 # ok 329 event_spurious.LCALTA.14
2143 19:06:37.683865 # ok 330 get_value.LCALTA.13
2144 19:06:37.689012 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2145 19:06:37.689461 # ok 331 name.LCALTA.13
2146 19:06:37.694522 # ok 332 write_default.LCALTA.13
2147 19:06:37.694970 # ok 333 write_valid.LCALTA.13
2148 19:06:37.700073 # ok 334 write_invalid.LCALTA.13
2149 19:06:37.700521 # ok 335 event_missing.LCALTA.13
2150 19:06:37.705625 # ok 336 event_spurious.LCALTA.13
2151 19:06:37.706068 # ok 337 get_value.LCALTA.12
2152 19:06:37.711168 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2153 19:06:37.711619 # ok 338 name.LCALTA.12
2154 19:06:37.716708 # ok 339 write_default.LCALTA.12
2155 19:06:37.722250 # ok 340 write_valid.LCALTA.12
2156 19:06:37.722696 # ok 341 write_invalid.LCALTA.12
2157 19:06:37.727806 # ok 342 event_missing.LCALTA.12
2158 19:06:37.728277 # ok 343 event_spurious.LCALTA.12
2159 19:06:37.733342 # ok 344 get_value.LCALTA.11
2160 19:06:37.733784 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2161 19:06:37.738987 # ok 345 name.LCALTA.11
2162 19:06:37.739435 # ok 346 write_default.LCALTA.11
2163 19:06:37.744436 # ok 347 write_valid.LCALTA.11
2164 19:06:37.744882 # ok 348 write_invalid.LCALTA.11
2165 19:06:37.750024 # ok 349 event_missing.LCALTA.11
2166 19:06:37.750465 # ok 350 event_spurious.LCALTA.11
2167 19:06:37.755516 # ok 351 get_value.LCALTA.10
2168 19:06:37.755963 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2169 19:06:37.761077 # ok 352 name.LCALTA.10
2170 19:06:37.761524 # ok 353 write_default.LCALTA.10
2171 19:06:37.766619 # ok 354 write_valid.LCALTA.10
2172 19:06:37.767059 # ok 355 write_invalid.LCALTA.10
2173 19:06:37.772206 # ok 356 event_missing.LCALTA.10
2174 19:06:37.772667 # ok 357 event_spurious.LCALTA.10
2175 19:06:37.777721 # ok 358 get_value.LCALTA.9
2176 19:06:37.778174 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2177 19:06:37.783264 # ok 359 name.LCALTA.9
2178 19:06:37.783716 # ok 360 write_default.LCALTA.9
2179 19:06:37.788838 # ok 361 write_valid.LCALTA.9
2180 19:06:37.789315 # ok 362 write_invalid.LCALTA.9
2181 19:06:37.794376 # ok 363 event_missing.LCALTA.9
2182 19:06:37.794839 # ok 364 event_spurious.LCALTA.9
2183 19:06:37.800016 # ok 365 get_value.LCALTA.8
2184 19:06:37.800468 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2185 19:06:37.805461 # ok 366 name.LCALTA.8
2186 19:06:37.805911 # ok 367 write_default.LCALTA.8
2187 19:06:37.810998 # ok 368 write_valid.LCALTA.8
2188 19:06:37.811447 # ok 369 write_invalid.LCALTA.8
2189 19:06:37.816562 # ok 370 event_missing.LCALTA.8
2190 19:06:37.817021 # ok 371 event_spurious.LCALTA.8
2191 19:06:37.822091 # ok 372 get_value.LCALTA.7
2192 19:06:37.822541 # # LCALTA.7 ACODEC Unmute Ramp Switch
2193 19:06:37.827639 # ok 373 name.LCALTA.7
2194 19:06:37.828116 # ok 374 write_default.LCALTA.7
2195 19:06:37.833191 # ok 375 write_valid.LCALTA.7
2196 19:06:37.833649 # ok 376 write_invalid.LCALTA.7
2197 19:06:37.838724 # ok 377 event_missing.LCALTA.7
2198 19:06:37.839170 # ok 378 event_spurious.LCALTA.7
2199 19:06:37.844284 # ok 379 get_value.LCALTA.6
2200 19:06:37.844738 # # LCALTA.6 ACODEC Mute Ramp Switch
2201 19:06:37.849825 # ok 380 name.LCALTA.6
2202 19:06:37.850274 # ok 381 write_default.LCALTA.6
2203 19:06:37.855367 # ok 382 write_valid.LCALTA.6
2204 19:06:37.855812 # ok 383 write_invalid.LCALTA.6
2205 19:06:37.861013 # ok 384 event_missing.LCALTA.6
2206 19:06:37.861463 # ok 385 event_spurious.LCALTA.6
2207 19:06:37.866462 # ok 386 get_value.LCALTA.5
2208 19:06:37.866915 # # LCALTA.5 ACODEC Volume Ramp Switch
2209 19:06:37.872042 # ok 387 name.LCALTA.5
2210 19:06:37.872491 # ok 388 write_default.LCALTA.5
2211 19:06:37.877545 # ok 389 write_valid.LCALTA.5
2212 19:06:37.877994 # ok 390 write_invalid.LCALTA.5
2213 19:06:37.883103 # ok 391 event_missing.LCALTA.5
2214 19:06:37.883556 # ok 392 event_spurious.LCALTA.5
2215 19:06:37.888653 # ok 393 get_value.LCALTA.4
2216 19:06:37.889107 # # LCALTA.4 ACODEC Ramp Rate
2217 19:06:37.894203 # ok 394 name.LCALTA.4
2218 19:06:37.894670 # ok 395 write_default.LCALTA.4
2219 19:06:37.899742 # ok 396 write_valid.LCALTA.4
2220 19:06:37.900223 # ok 397 write_invalid.LCALTA.4
2221 19:06:37.905281 # ok 398 event_missing.LCALTA.4
2222 19:06:37.905732 # ok 399 event_spurious.LCALTA.4
2223 19:06:37.910860 # ok 400 get_value.LCALTA.3
2224 19:06:37.911312 # # LCALTA.3 ACODEC Playback Volume
2225 19:06:37.916386 # ok 401 name.LCALTA.3
2226 19:06:37.916838 # ok 402 write_default.LCALTA.3
2227 19:06:37.922028 # ok 403 write_valid.LCALTA.3
2228 19:06:37.922478 # ok 404 write_invalid.LCALTA.3
2229 19:06:37.927497 # ok 405 event_missing.LCALTA.3
2230 19:06:37.927955 # ok 406 event_spurious.LCALTA.3
2231 19:06:37.933046 # ok 407 get_value.LCALTA.2
2232 19:06:37.933496 # # LCALTA.2 ACODEC Playback Switch
2233 19:06:37.938561 # ok 408 name.LCALTA.2
2234 19:06:37.939012 # ok 409 write_default.LCALTA.2
2235 19:06:37.944142 # ok 410 write_valid.LCALTA.2
2236 19:06:37.944591 # ok 411 write_invalid.LCALTA.2
2237 19:06:37.949672 # ok 412 event_missing.LCALTA.2
2238 19:06:37.950122 # ok 413 event_spurious.LCALTA.2
2239 19:06:37.955192 # ok 414 get_value.LCALTA.1
2240 19:06:37.955643 # # LCALTA.1 ACODEC Playback Channel Mode
2241 19:06:37.960755 # ok 415 name.LCALTA.1
2242 19:06:37.961200 # ok 416 write_default.LCALTA.1
2243 19:06:37.966317 # ok 417 write_valid.LCALTA.1
2244 19:06:37.966764 # ok 418 write_invalid.LCALTA.1
2245 19:06:37.971878 # ok 419 event_missing.LCALTA.1
2246 19:06:37.972356 # ok 420 event_spurious.LCALTA.1
2247 19:06:37.977406 # ok 421 get_value.LCALTA.0
2248 19:06:37.977856 # # LCALTA.0 TOACODEC Lane Select
2249 19:06:37.983017 # ok 422 name.LCALTA.0
2250 19:06:37.983465 # ok 423 write_default.LCALTA.0
2251 19:06:37.988496 # ok 424 write_valid.LCALTA.0
2252 19:06:37.988939 # ok 425 write_invalid.LCALTA.0
2253 19:06:37.994059 # ok 426 event_missing.LCALTA.0
2254 19:06:37.994502 # ok 427 event_spurious.LCALTA.0
2255 19:06:37.999586 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2256 19:06:38.005118 ok 1 selftests: alsa: mixer-test
2257 19:06:38.005564 # timeout set to 45
2258 19:06:38.005972 # selftests: alsa: pcm-test
2259 19:06:38.010670 # TAP version 13
2260 19:06:38.011115 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2261 19:06:38.016230 # # LCALTA.0 - fe.dai-link-0 (*)
2262 19:06:38.016677 # # LCALTA.0 - fe.dai-link-1 (*)
2263 19:06:38.021754 # # LCALTA.0 - fe.dai-link-2 (*)
2264 19:06:38.022212 # # LCALTA.0 - fe.dai-link-3 (*)
2265 19:06:38.027297 # # LCALTA.0 - fe.dai-link-4 (*)
2266 19:06:38.027747 # # LCALTA.0 - fe.dai-link-5 (*)
2267 19:06:38.032859 # 1..42
2268 19:06:38.038420 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2269 19:06:38.038870 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2270 19:06:38.044047 # # snd_pcm_hw_params: Invalid argument
2271 19:06:38.049504 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2272 19:06:38.055059 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2273 19:06:38.055502 # # snd_pcm_hw_params: Invalid argument
2274 19:06:38.060605 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2275 19:06:38.066128 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2276 19:06:38.071688 # # snd_pcm_hw_params: Invalid argument
2277 19:06:38.077252 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2278 19:06:38.082796 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2279 19:06:38.083249 # # snd_pcm_hw_params: Invalid argument
2280 19:06:38.088335 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2281 19:06:38.093880 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2282 19:06:38.099417 # # snd_pcm_hw_params: Invalid argument
2283 19:06:38.105013 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2284 19:06:38.110526 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2285 19:06:38.110970 # # snd_pcm_hw_params: Invalid argument
2286 19:06:38.116073 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2287 19:06:38.121603 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2288 19:06:38.127137 # # snd_pcm_hw_params: Invalid argument
2289 19:06:38.132700 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2290 19:06:38.133147 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2291 19:06:38.138249 # # snd_pcm_hw_params: Invalid argument
2292 19:06:38.143779 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2293 19:06:38.149328 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2294 19:06:38.149775 # # snd_pcm_hw_params: Invalid argument
2295 19:06:38.160382 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2296 19:06:38.160837 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2297 19:06:38.166161 # # snd_pcm_hw_params: Invalid argument
2298 19:06:38.171596 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2299 19:06:38.177133 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2300 19:06:38.177606 # # snd_pcm_hw_params: Invalid argument
2301 19:06:38.182690 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2302 19:06:38.188248 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2303 19:06:38.193774 # # snd_pcm_hw_params: Invalid argument
2304 19:06:38.199310 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2305 19:06:38.204852 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2306 19:06:38.205319 # # snd_pcm_hw_params: Invalid argument
2307 19:06:38.210396 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2308 19:06:38.215942 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2309 19:06:38.221481 # # snd_pcm_hw_params: Invalid argument
2310 19:06:38.227051 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2311 19:06:38.232575 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2312 19:06:38.233034 # # snd_pcm_hw_params: Invalid argument
2313 19:06:38.238151 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2314 19:06:38.243681 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2315 19:06:38.249229 # # snd_pcm_hw_params: Invalid argument
2316 19:06:38.254780 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2317 19:06:38.255243 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2318 19:06:38.260332 # # snd_pcm_hw_params: Invalid argument
2319 19:06:38.265875 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2320 19:06:38.271405 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2321 19:06:38.276950 # # snd_pcm_hw_params: Invalid argument
2322 19:06:38.282492 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2323 19:06:38.282955 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2324 19:06:38.288089 # # snd_pcm_hw_params: Invalid argument
2325 19:06:38.293595 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2326 19:06:38.299142 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2327 19:06:38.304724 # # snd_pcm_hw_params: Invalid argument
2328 19:06:38.310252 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2329 19:06:38.310718 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2330 19:06:38.315801 # # snd_pcm_hw_params: Invalid argument
2331 19:06:38.321340 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2332 19:06:38.326912 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2333 19:06:38.327386 # # snd_pcm_hw_params: Invalid argument
2334 19:06:38.332441 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2335 19:06:38.337971 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2336 19:06:38.343517 # # snd_pcm_hw_params: Invalid argument
2337 19:06:38.349098 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2338 19:06:38.354601 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2339 19:06:38.355061 # # snd_pcm_hw_params: Invalid argument
2340 19:06:38.360194 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2341 19:06:38.365720 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2342 19:06:38.371245 # # snd_pcm_hw_params: Invalid argument
2343 19:06:38.376805 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2344 19:06:38.382348 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2345 19:06:38.382803 # # snd_pcm_hw_params: Invalid argument
2346 19:06:38.387898 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2347 19:06:38.393449 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2348 19:06:38.398985 # # snd_pcm_hw_params: Invalid argument
2349 19:06:38.404532 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2350 19:06:38.410099 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2351 19:06:38.410555 # # snd_pcm_hw_params: Invalid argument
2352 19:06:38.415639 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2353 19:06:38.421178 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2354 19:06:38.426718 # # snd_pcm_hw_params: Invalid argument
2355 19:06:38.432269 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2356 19:06:38.437820 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2357 19:06:38.438274 # # snd_pcm_hw_params: Invalid argument
2358 19:06:38.443346 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2359 19:06:38.448906 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2360 19:06:38.454448 # # snd_pcm_hw_params: Invalid argument
2361 19:06:38.460033 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2362 19:06:38.465539 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2363 19:06:38.465996 # # snd_pcm_hw_params: Invalid argument
2364 19:06:38.471094 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2365 19:06:38.476623 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2366 19:06:38.482155 # # snd_pcm_hw_params: Invalid argument
2367 19:06:38.487692 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2368 19:06:38.493257 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2369 19:06:38.493719 # # snd_pcm_hw_params: Invalid argument
2370 19:06:38.498841 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2371 19:06:38.504383 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2372 19:06:38.509917 # # snd_pcm_hw_params: Invalid argument
2373 19:06:38.515445 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2374 19:06:38.520977 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2375 19:06:38.521436 # # snd_pcm_hw_params: Invalid argument
2376 19:06:38.526542 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2377 19:06:38.532108 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2378 19:06:38.537664 # # snd_pcm_hw_params: Invalid argument
2379 19:06:38.543196 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2380 19:06:38.548753 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2381 19:06:38.549212 # # snd_pcm_hw_params: Invalid argument
2382 19:06:38.554274 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2383 19:06:38.559823 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2384 19:06:38.565372 # # snd_pcm_hw_params: Invalid argument
2385 19:06:38.570914 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2386 19:06:38.576478 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2387 19:06:38.576933 # # snd_pcm_hw_params: Invalid argument
2388 19:06:38.582005 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2389 19:06:38.587549 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2390 19:06:38.593112 # # snd_pcm_hw_params: Invalid argument
2391 19:06:38.598653 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2392 19:06:38.604242 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2393 19:06:38.604728 # # snd_pcm_hw_params: Invalid argument
2394 19:06:38.609754 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2395 19:06:38.615303 ok 2 selftests: alsa: pcm-test
2396 19:06:38.615764 # timeout set to 45
2397 19:06:38.620957 # selftests: alsa: test-pcmtest-driver
2398 19:06:38.621462 # TAP version 13
2399 19:06:38.621899 # 1..5
2400 19:06:38.626379 # # Starting 5 tests from 1 test cases.
2401 19:06:38.626873 # # RUN pcmtest.playback ...
2402 19:06:38.631920 # # SKIP Can't read patterns. Probably, module isn't loaded
2403 19:06:38.637469 # # OK pcmtest.playback
2404 19:06:38.643007 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2405 19:06:38.648539 # # RUN pcmtest.capture ...
2406 19:06:38.654091 # # SKIP Can't read patterns. Probably, module isn't loaded
2407 19:06:38.659639 # # OK pcmtest.capture
2408 19:06:38.665192 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2409 19:06:38.670752 # # RUN pcmtest.ni_capture ...
2410 19:06:38.676349 # # SKIP Can't read patterns. Probably, module isn't loaded
2411 19:06:38.676834 # # OK pcmtest.ni_capture
2412 19:06:38.687365 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2413 19:06:38.687856 # # RUN pcmtest.ni_playback ...
2414 19:06:38.692986 # # SKIP Can't read patterns. Probably, module isn't loaded
2415 19:06:38.698521 # # OK pcmtest.ni_playback
2416 19:06:38.704064 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2417 19:06:38.709597 # # RUN pcmtest.reset_ioctl ...
2418 19:06:38.715132 # # SKIP Can't read patterns. Probably, module isn't loaded
2419 19:06:38.720690 # # OK pcmtest.reset_ioctl
2420 19:06:38.726244 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2421 19:06:38.731778 # # PASSED: 5 / 5 tests passed.
2422 19:06:38.737344 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2423 19:06:38.737811 ok 3 selftests: alsa: test-pcmtest-driver
2424 19:06:38.742882 # timeout set to 45
2425 19:06:38.743344 # selftests: alsa: utimer-test
2426 19:06:38.743758 # TAP version 13
2427 19:06:38.744207 # 1..2
2428 19:06:38.748425 # # Starting 2 tests from 2 test cases.
2429 19:06:38.753963 # # RUN global.wrong_timers_test ...
2430 19:06:38.759508 # # OK global.wrong_timers_test
2431 19:06:38.759965 # ok 1 global.wrong_timers_test
2432 19:06:38.765062 # # RUN timer_f.utimer ...
2433 19:06:38.770608 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2434 19:06:38.776232 # # utimer: Test terminated by assertion
2435 19:06:38.781708 # # FAIL timer_f.utimer
2436 19:06:38.782170 # not ok 2 timer_f.utimer
2437 19:06:38.787274 # # FAILED: 1 / 2 tests passed.
2438 19:06:38.794685 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2439 19:06:38.795149 not ok 4 selftests: alsa: utimer-test # exit=1
2440 19:06:39.294650 alsa_mixer-test_get_value_LCALTA_60 pass
2441 19:06:39.300113 alsa_mixer-test_name_LCALTA_60 pass
2442 19:06:39.300598 alsa_mixer-test_write_default_LCALTA_60 pass
2443 19:06:39.305616 alsa_mixer-test_write_valid_LCALTA_60 pass
2444 19:06:39.309074 alsa_mixer-test_write_invalid_LCALTA_60 pass
2445 19:06:39.314613 alsa_mixer-test_event_missing_LCALTA_60 pass
2446 19:06:39.320213 alsa_mixer-test_event_spurious_LCALTA_60 pass
2447 19:06:39.320688 alsa_mixer-test_get_value_LCALTA_59 pass
2448 19:06:39.325725 alsa_mixer-test_name_LCALTA_59 pass
2449 19:06:39.331282 alsa_mixer-test_write_default_LCALTA_59 pass
2450 19:06:39.331758 alsa_mixer-test_write_valid_LCALTA_59 pass
2451 19:06:39.336794 alsa_mixer-test_write_invalid_LCALTA_59 pass
2452 19:06:39.342353 alsa_mixer-test_event_missing_LCALTA_59 pass
2453 19:06:39.342832 alsa_mixer-test_event_spurious_LCALTA_59 pass
2454 19:06:39.347913 alsa_mixer-test_get_value_LCALTA_58 pass
2455 19:06:39.353463 alsa_mixer-test_name_LCALTA_58 pass
2456 19:06:39.353944 alsa_mixer-test_write_default_LCALTA_58 pass
2457 19:06:39.359015 alsa_mixer-test_write_valid_LCALTA_58 pass
2458 19:06:39.364540 alsa_mixer-test_write_invalid_LCALTA_58 pass
2459 19:06:39.370168 alsa_mixer-test_event_missing_LCALTA_58 pass
2460 19:06:39.370641 alsa_mixer-test_event_spurious_LCALTA_58 pass
2461 19:06:39.375630 alsa_mixer-test_get_value_LCALTA_57 pass
2462 19:06:39.381305 alsa_mixer-test_name_LCALTA_57 pass
2463 19:06:39.381784 alsa_mixer-test_write_default_LCALTA_57 pass
2464 19:06:39.386802 alsa_mixer-test_write_valid_LCALTA_57 pass
2465 19:06:39.392378 alsa_mixer-test_write_invalid_LCALTA_57 pass
2466 19:06:39.392857 alsa_mixer-test_event_missing_LCALTA_57 pass
2467 19:06:39.397933 alsa_mixer-test_event_spurious_LCALTA_57 pass
2468 19:06:39.403439 alsa_mixer-test_get_value_LCALTA_56 pass
2469 19:06:39.403899 alsa_mixer-test_name_LCALTA_56 pass
2470 19:06:39.408964 alsa_mixer-test_write_default_LCALTA_56 pass
2471 19:06:39.414542 alsa_mixer-test_write_valid_LCALTA_56 pass
2472 19:06:39.415005 alsa_mixer-test_write_invalid_LCALTA_56 pass
2473 19:06:39.420098 alsa_mixer-test_event_missing_LCALTA_56 pass
2474 19:06:39.425614 alsa_mixer-test_event_spurious_LCALTA_56 pass
2475 19:06:39.431246 alsa_mixer-test_get_value_LCALTA_55 pass
2476 19:06:39.431704 alsa_mixer-test_name_LCALTA_55 pass
2477 19:06:39.436713 alsa_mixer-test_write_default_LCALTA_55 pass
2478 19:06:39.442312 alsa_mixer-test_write_valid_LCALTA_55 pass
2479 19:06:39.442781 alsa_mixer-test_write_invalid_LCALTA_55 pass
2480 19:06:39.447827 alsa_mixer-test_event_missing_LCALTA_55 pass
2481 19:06:39.453363 alsa_mixer-test_event_spurious_LCALTA_55 pass
2482 19:06:39.453827 alsa_mixer-test_get_value_LCALTA_54 pass
2483 19:06:39.458893 alsa_mixer-test_name_LCALTA_54 pass
2484 19:06:39.464440 alsa_mixer-test_write_default_LCALTA_54 pass
2485 19:06:39.464907 alsa_mixer-test_write_valid_LCALTA_54 pass
2486 19:06:39.469991 alsa_mixer-test_write_invalid_LCALTA_54 pass
2487 19:06:39.475528 alsa_mixer-test_event_missing_LCALTA_54 pass
2488 19:06:39.481091 alsa_mixer-test_event_spurious_LCALTA_54 pass
2489 19:06:39.481552 alsa_mixer-test_get_value_LCALTA_53 pass
2490 19:06:39.486671 alsa_mixer-test_name_LCALTA_53 pass
2491 19:06:39.492296 alsa_mixer-test_write_default_LCALTA_53 pass
2492 19:06:39.492769 alsa_mixer-test_write_valid_LCALTA_53 pass
2493 19:06:39.497745 alsa_mixer-test_write_invalid_LCALTA_53 pass
2494 19:06:39.503306 alsa_mixer-test_event_missing_LCALTA_53 pass
2495 19:06:39.503771 alsa_mixer-test_event_spurious_LCALTA_53 pass
2496 19:06:39.508845 alsa_mixer-test_get_value_LCALTA_52 pass
2497 19:06:39.514386 alsa_mixer-test_name_LCALTA_52 pass
2498 19:06:39.514847 alsa_mixer-test_write_default_LCALTA_52 pass
2499 19:06:39.519914 alsa_mixer-test_write_valid_LCALTA_52 pass
2500 19:06:39.525484 alsa_mixer-test_write_invalid_LCALTA_52 pass
2501 19:06:39.525956 alsa_mixer-test_event_missing_LCALTA_52 pass
2502 19:06:39.531033 alsa_mixer-test_event_spurious_LCALTA_52 pass
2503 19:06:39.536579 alsa_mixer-test_get_value_LCALTA_51 pass
2504 19:06:39.537046 alsa_mixer-test_name_LCALTA_51 pass
2505 19:06:39.542086 alsa_mixer-test_write_default_LCALTA_51 pass
2506 19:06:39.547608 alsa_mixer-test_write_valid_LCALTA_51 pass
2507 19:06:39.553240 alsa_mixer-test_write_invalid_LCALTA_51 pass
2508 19:06:39.553697 alsa_mixer-test_event_missing_LCALTA_51 pass
2509 19:06:39.558783 alsa_mixer-test_event_spurious_LCALTA_51 pass
2510 19:06:39.564313 alsa_mixer-test_get_value_LCALTA_50 pass
2511 19:06:39.564768 alsa_mixer-test_name_LCALTA_50 pass
2512 19:06:39.569855 alsa_mixer-test_write_default_LCALTA_50 pass
2513 19:06:39.575397 alsa_mixer-test_write_valid_LCALTA_50 pass
2514 19:06:39.575863 alsa_mixer-test_write_invalid_LCALTA_50 pass
2515 19:06:39.580934 alsa_mixer-test_event_missing_LCALTA_50 pass
2516 19:06:39.586478 alsa_mixer-test_event_spurious_LCALTA_50 pass
2517 19:06:39.586942 alsa_mixer-test_get_value_LCALTA_49 pass
2518 19:06:39.592054 alsa_mixer-test_name_LCALTA_49 pass
2519 19:06:39.597583 alsa_mixer-test_write_default_LCALTA_49 pass
2520 19:06:39.598046 alsa_mixer-test_write_valid_LCALTA_49 pass
2521 19:06:39.603141 alsa_mixer-test_write_invalid_LCALTA_49 pass
2522 19:06:39.608851 alsa_mixer-test_event_missing_LCALTA_49 pass
2523 19:06:39.614271 alsa_mixer-test_event_spurious_LCALTA_49 pass
2524 19:06:39.614737 alsa_mixer-test_get_value_LCALTA_48 pass
2525 19:06:39.619781 alsa_mixer-test_name_LCALTA_48 pass
2526 19:06:39.625325 alsa_mixer-test_write_default_LCALTA_48 pass
2527 19:06:39.625792 alsa_mixer-test_write_valid_LCALTA_48 pass
2528 19:06:39.630853 alsa_mixer-test_write_invalid_LCALTA_48 pass
2529 19:06:39.636395 alsa_mixer-test_event_missing_LCALTA_48 pass
2530 19:06:39.636860 alsa_mixer-test_event_spurious_LCALTA_48 pass
2531 19:06:39.641955 alsa_mixer-test_get_value_LCALTA_47 pass
2532 19:06:39.647490 alsa_mixer-test_name_LCALTA_47 pass
2533 19:06:39.647954 alsa_mixer-test_write_default_LCALTA_47 pass
2534 19:06:39.653010 alsa_mixer-test_write_valid_LCALTA_47 pass
2535 19:06:39.658559 alsa_mixer-test_write_invalid_LCALTA_47 pass
2536 19:06:39.664188 alsa_mixer-test_event_missing_LCALTA_47 pass
2537 19:06:39.664680 alsa_mixer-test_event_spurious_LCALTA_47 pass
2538 19:06:39.669706 alsa_mixer-test_get_value_LCALTA_46 pass
2539 19:06:39.670178 alsa_mixer-test_name_LCALTA_46 pass
2540 19:06:39.675290 alsa_mixer-test_write_default_LCALTA_46 pass
2541 19:06:39.680798 alsa_mixer-test_write_valid_LCALTA_46 pass
2542 19:06:39.686349 alsa_mixer-test_write_invalid_LCALTA_46 pass
2543 19:06:39.686822 alsa_mixer-test_event_missing_LCALTA_46 pass
2544 19:06:39.691853 alsa_mixer-test_event_spurious_LCALTA_46 pass
2545 19:06:39.697394 alsa_mixer-test_get_value_LCALTA_45 pass
2546 19:06:39.697862 alsa_mixer-test_name_LCALTA_45 pass
2547 19:06:39.702930 alsa_mixer-test_write_default_LCALTA_45 pass
2548 19:06:39.708522 alsa_mixer-test_write_valid_LCALTA_45 pass
2549 19:06:39.708990 alsa_mixer-test_write_invalid_LCALTA_45 pass
2550 19:06:39.714054 alsa_mixer-test_event_missing_LCALTA_45 pass
2551 19:06:39.719590 alsa_mixer-test_event_spurious_LCALTA_45 pass
2552 19:06:39.725151 alsa_mixer-test_get_value_LCALTA_44 pass
2553 19:06:39.725620 alsa_mixer-test_name_LCALTA_44 pass
2554 19:06:39.730702 alsa_mixer-test_write_default_LCALTA_44 pass
2555 19:06:39.736295 alsa_mixer-test_write_valid_LCALTA_44 pass
2556 19:06:39.736762 alsa_mixer-test_write_invalid_LCALTA_44 pass
2557 19:06:39.741801 alsa_mixer-test_event_missing_LCALTA_44 pass
2558 19:06:39.747346 alsa_mixer-test_event_spurious_LCALTA_44 pass
2559 19:06:39.747814 alsa_mixer-test_get_value_LCALTA_43 pass
2560 19:06:39.752896 alsa_mixer-test_name_LCALTA_43 pass
2561 19:06:39.758444 alsa_mixer-test_write_default_LCALTA_43 pass
2562 19:06:39.758912 alsa_mixer-test_write_valid_LCALTA_43 pass
2563 19:06:39.764004 alsa_mixer-test_write_invalid_LCALTA_43 pass
2564 19:06:39.769520 alsa_mixer-test_event_missing_LCALTA_43 pass
2565 19:06:39.769978 alsa_mixer-test_event_spurious_LCALTA_43 pass
2566 19:06:39.775079 alsa_mixer-test_get_value_LCALTA_42 pass
2567 19:06:39.780610 alsa_mixer-test_name_LCALTA_42 pass
2568 19:06:39.781073 alsa_mixer-test_write_default_LCALTA_42 pass
2569 19:06:39.786167 alsa_mixer-test_write_valid_LCALTA_42 pass
2570 19:06:39.791708 alsa_mixer-test_write_invalid_LCALTA_42 pass
2571 19:06:39.797304 alsa_mixer-test_event_missing_LCALTA_42 pass
2572 19:06:39.797765 alsa_mixer-test_event_spurious_LCALTA_42 pass
2573 19:06:39.802802 alsa_mixer-test_get_value_LCALTA_41 pass
2574 19:06:39.808343 alsa_mixer-test_name_LCALTA_41 pass
2575 19:06:39.808804 alsa_mixer-test_write_default_LCALTA_41 pass
2576 19:06:39.813880 alsa_mixer-test_write_valid_LCALTA_41 pass
2577 19:06:39.819449 alsa_mixer-test_write_invalid_LCALTA_41 pass
2578 19:06:39.819910 alsa_mixer-test_event_missing_LCALTA_41 pass
2579 19:06:39.825006 alsa_mixer-test_event_spurious_LCALTA_41 pass
2580 19:06:39.830519 alsa_mixer-test_get_value_LCALTA_40 pass
2581 19:06:39.830973 alsa_mixer-test_name_LCALTA_40 pass
2582 19:06:39.836087 alsa_mixer-test_write_default_LCALTA_40 pass
2583 19:06:39.841629 alsa_mixer-test_write_valid_LCALTA_40 pass
2584 19:06:39.842091 alsa_mixer-test_write_invalid_LCALTA_40 pass
2585 19:06:39.847194 alsa_mixer-test_event_missing_LCALTA_40 pass
2586 19:06:39.852718 alsa_mixer-test_event_spurious_LCALTA_40 pass
2587 19:06:39.858284 alsa_mixer-test_get_value_LCALTA_39 pass
2588 19:06:39.858742 alsa_mixer-test_name_LCALTA_39 pass
2589 19:06:39.863839 alsa_mixer-test_write_default_LCALTA_39 pass
2590 19:06:39.869363 alsa_mixer-test_write_valid_LCALTA_39 pass
2591 19:06:39.869824 alsa_mixer-test_write_invalid_LCALTA_39 pass
2592 19:06:39.874932 alsa_mixer-test_event_missing_LCALTA_39 pass
2593 19:06:39.880460 alsa_mixer-test_event_spurious_LCALTA_39 pass
2594 19:06:39.880929 alsa_mixer-test_get_value_LCALTA_38 pass
2595 19:06:39.885999 alsa_mixer-test_name_LCALTA_38 pass
2596 19:06:39.891558 alsa_mixer-test_write_default_LCALTA_38 pass
2597 19:06:39.892054 alsa_mixer-test_write_valid_LCALTA_38 pass
2598 19:06:39.897107 alsa_mixer-test_write_invalid_LCALTA_38 pass
2599 19:06:39.902642 alsa_mixer-test_event_missing_LCALTA_38 pass
2600 19:06:39.908228 alsa_mixer-test_event_spurious_LCALTA_38 pass
2601 19:06:39.908717 alsa_mixer-test_get_value_LCALTA_37 pass
2602 19:06:39.913763 alsa_mixer-test_name_LCALTA_37 pass
2603 19:06:39.919327 alsa_mixer-test_write_default_LCALTA_37 pass
2604 19:06:39.919792 alsa_mixer-test_write_valid_LCALTA_37 pass
2605 19:06:39.924810 alsa_mixer-test_write_invalid_LCALTA_37 pass
2606 19:06:39.930348 alsa_mixer-test_event_missing_LCALTA_37 pass
2607 19:06:39.930819 alsa_mixer-test_event_spurious_LCALTA_37 pass
2608 19:06:39.935913 alsa_mixer-test_get_value_LCALTA_36 pass
2609 19:06:39.941456 alsa_mixer-test_name_LCALTA_36 pass
2610 19:06:39.941920 alsa_mixer-test_write_default_LCALTA_36 pass
2611 19:06:39.947014 alsa_mixer-test_write_valid_LCALTA_36 pass
2612 19:06:39.952582 alsa_mixer-test_write_invalid_LCALTA_36 pass
2613 19:06:39.953041 alsa_mixer-test_event_missing_LCALTA_36 pass
2614 19:06:39.958104 alsa_mixer-test_event_spurious_LCALTA_36 pass
2615 19:06:39.963650 alsa_mixer-test_get_value_LCALTA_35 pass
2616 19:06:39.964135 alsa_mixer-test_name_LCALTA_35 pass
2617 19:06:39.969180 alsa_mixer-test_write_default_LCALTA_35 pass
2618 19:06:39.974757 alsa_mixer-test_write_valid_LCALTA_35 pass
2619 19:06:39.980330 alsa_mixer-test_write_invalid_LCALTA_35 pass
2620 19:06:39.980796 alsa_mixer-test_event_missing_LCALTA_35 pass
2621 19:06:39.985856 alsa_mixer-test_event_spurious_LCALTA_35 pass
2622 19:06:39.991390 alsa_mixer-test_get_value_LCALTA_34 pass
2623 19:06:39.991857 alsa_mixer-test_name_LCALTA_34 pass
2624 19:06:39.996949 alsa_mixer-test_write_default_LCALTA_34 pass
2625 19:06:40.002482 alsa_mixer-test_write_valid_LCALTA_34 pass
2626 19:06:40.002943 alsa_mixer-test_write_invalid_LCALTA_34 pass
2627 19:06:40.008034 alsa_mixer-test_event_missing_LCALTA_34 pass
2628 19:06:40.013578 alsa_mixer-test_event_spurious_LCALTA_34 pass
2629 19:06:40.014046 alsa_mixer-test_get_value_LCALTA_33 pass
2630 19:06:40.019117 alsa_mixer-test_name_LCALTA_33 pass
2631 19:06:40.024667 alsa_mixer-test_write_default_LCALTA_33 pass
2632 19:06:40.025141 alsa_mixer-test_write_valid_LCALTA_33 pass
2633 19:06:40.030212 alsa_mixer-test_write_invalid_LCALTA_33 pass
2634 19:06:40.035768 alsa_mixer-test_event_missing_LCALTA_33 pass
2635 19:06:40.041325 alsa_mixer-test_event_spurious_LCALTA_33 pass
2636 19:06:40.041788 alsa_mixer-test_get_value_LCALTA_32 pass
2637 19:06:40.046863 alsa_mixer-test_name_LCALTA_32 pass
2638 19:06:40.052411 alsa_mixer-test_write_default_LCALTA_32 pass
2639 19:06:40.052869 alsa_mixer-test_write_valid_LCALTA_32 pass
2640 19:06:40.057950 alsa_mixer-test_write_invalid_LCALTA_32 pass
2641 19:06:40.063500 alsa_mixer-test_event_missing_LCALTA_32 pass
2642 19:06:40.064011 alsa_mixer-test_event_spurious_LCALTA_32 pass
2643 19:06:40.069042 alsa_mixer-test_get_value_LCALTA_31 pass
2644 19:06:40.074570 alsa_mixer-test_name_LCALTA_31 pass
2645 19:06:40.075034 alsa_mixer-test_write_default_LCALTA_31 pass
2646 19:06:40.080208 alsa_mixer-test_write_valid_LCALTA_31 pass
2647 19:06:40.085708 alsa_mixer-test_write_invalid_LCALTA_31 pass
2648 19:06:40.091216 alsa_mixer-test_event_missing_LCALTA_31 pass
2649 19:06:40.091677 alsa_mixer-test_event_spurious_LCALTA_31 pass
2650 19:06:40.096794 alsa_mixer-test_get_value_LCALTA_30 pass
2651 19:06:40.097259 alsa_mixer-test_name_LCALTA_30 pass
2652 19:06:40.102350 alsa_mixer-test_write_default_LCALTA_30 pass
2653 19:06:40.107880 alsa_mixer-test_write_valid_LCALTA_30 pass
2654 19:06:40.113436 alsa_mixer-test_write_invalid_LCALTA_30 pass
2655 19:06:40.113897 alsa_mixer-test_event_missing_LCALTA_30 pass
2656 19:06:40.118968 alsa_mixer-test_event_spurious_LCALTA_30 pass
2657 19:06:40.124505 alsa_mixer-test_get_value_LCALTA_29 pass
2658 19:06:40.124970 alsa_mixer-test_name_LCALTA_29 pass
2659 19:06:40.130069 alsa_mixer-test_write_default_LCALTA_29 pass
2660 19:06:40.135618 alsa_mixer-test_write_valid_LCALTA_29 pass
2661 19:06:40.136123 alsa_mixer-test_write_invalid_LCALTA_29 pass
2662 19:06:40.141164 alsa_mixer-test_event_missing_LCALTA_29 pass
2663 19:06:40.146703 alsa_mixer-test_event_spurious_LCALTA_29 pass
2664 19:06:40.152254 alsa_mixer-test_get_value_LCALTA_28 pass
2665 19:06:40.152729 alsa_mixer-test_name_LCALTA_28 pass
2666 19:06:40.157769 alsa_mixer-test_write_default_LCALTA_28 pass
2667 19:06:40.163348 alsa_mixer-test_write_valid_LCALTA_28 pass
2668 19:06:40.163820 alsa_mixer-test_write_invalid_LCALTA_28 pass
2669 19:06:40.168912 alsa_mixer-test_event_missing_LCALTA_28 pass
2670 19:06:40.174453 alsa_mixer-test_event_spurious_LCALTA_28 pass
2671 19:06:40.174924 alsa_mixer-test_get_value_LCALTA_27 pass
2672 19:06:40.180011 alsa_mixer-test_name_LCALTA_27 pass
2673 19:06:40.185544 alsa_mixer-test_write_default_LCALTA_27 pass
2674 19:06:40.186021 alsa_mixer-test_write_valid_LCALTA_27 pass
2675 19:06:40.191095 alsa_mixer-test_write_invalid_LCALTA_27 pass
2676 19:06:40.196597 alsa_mixer-test_event_missing_LCALTA_27 pass
2677 19:06:40.197074 alsa_mixer-test_event_spurious_LCALTA_27 pass
2678 19:06:40.202181 alsa_mixer-test_get_value_LCALTA_26 pass
2679 19:06:40.207723 alsa_mixer-test_name_LCALTA_26 pass
2680 19:06:40.208223 alsa_mixer-test_write_default_LCALTA_26 skip
2681 19:06:40.213275 alsa_mixer-test_write_valid_LCALTA_26 skip
2682 19:06:40.218807 alsa_mixer-test_write_invalid_LCALTA_26 skip
2683 19:06:40.224344 alsa_mixer-test_event_missing_LCALTA_26 pass
2684 19:06:40.224818 alsa_mixer-test_event_spurious_LCALTA_26 pass
2685 19:06:40.229892 alsa_mixer-test_get_value_LCALTA_25 pass
2686 19:06:40.235453 alsa_mixer-test_name_LCALTA_25 pass
2687 19:06:40.235923 alsa_mixer-test_write_default_LCALTA_25 pass
2688 19:06:40.241012 alsa_mixer-test_write_valid_LCALTA_25 skip
2689 19:06:40.246469 alsa_mixer-test_write_invalid_LCALTA_25 skip
2690 19:06:40.246963 alsa_mixer-test_event_missing_LCALTA_25 pass
2691 19:06:40.252049 alsa_mixer-test_event_spurious_LCALTA_25 pass
2692 19:06:40.257560 alsa_mixer-test_get_value_LCALTA_24 pass
2693 19:06:40.258059 alsa_mixer-test_name_LCALTA_24 pass
2694 19:06:40.263105 alsa_mixer-test_write_default_LCALTA_24 skip
2695 19:06:40.268658 alsa_mixer-test_write_valid_LCALTA_24 skip
2696 19:06:40.269166 alsa_mixer-test_write_invalid_LCALTA_24 skip
2697 19:06:40.274192 alsa_mixer-test_event_missing_LCALTA_24 pass
2698 19:06:40.279740 alsa_mixer-test_event_spurious_LCALTA_24 pass
2699 19:06:40.285285 alsa_mixer-test_get_value_LCALTA_23 pass
2700 19:06:40.285780 alsa_mixer-test_name_LCALTA_23 pass
2701 19:06:40.290832 alsa_mixer-test_write_default_LCALTA_23 skip
2702 19:06:40.296375 alsa_mixer-test_write_valid_LCALTA_23 skip
2703 19:06:40.296864 alsa_mixer-test_write_invalid_LCALTA_23 skip
2704 19:06:40.301923 alsa_mixer-test_event_missing_LCALTA_23 pass
2705 19:06:40.307465 alsa_mixer-test_event_spurious_LCALTA_23 pass
2706 19:06:40.307975 alsa_mixer-test_get_value_LCALTA_22 pass
2707 19:06:40.313024 alsa_mixer-test_name_LCALTA_22 pass
2708 19:06:40.318558 alsa_mixer-test_write_default_LCALTA_22 pass
2709 19:06:40.319064 alsa_mixer-test_write_valid_LCALTA_22 pass
2710 19:06:40.324106 alsa_mixer-test_write_invalid_LCALTA_22 pass
2711 19:06:40.329677 alsa_mixer-test_event_missing_LCALTA_22 pass
2712 19:06:40.335182 alsa_mixer-test_event_spurious_LCALTA_22 pass
2713 19:06:40.335686 alsa_mixer-test_get_value_LCALTA_21 pass
2714 19:06:40.340741 alsa_mixer-test_name_LCALTA_21 pass
2715 19:06:40.346292 alsa_mixer-test_write_default_LCALTA_21 pass
2716 19:06:40.346795 alsa_mixer-test_write_valid_LCALTA_21 pass
2717 19:06:40.351836 alsa_mixer-test_write_invalid_LCALTA_21 pass
2718 19:06:40.357389 alsa_mixer-test_event_missing_LCALTA_21 pass
2719 19:06:40.357893 alsa_mixer-test_event_spurious_LCALTA_21 pass
2720 19:06:40.362930 alsa_mixer-test_get_value_LCALTA_20 pass
2721 19:06:40.368474 alsa_mixer-test_name_LCALTA_20 pass
2722 19:06:40.368977 alsa_mixer-test_write_default_LCALTA_20 pass
2723 19:06:40.374032 alsa_mixer-test_write_valid_LCALTA_20 pass
2724 19:06:40.379577 alsa_mixer-test_write_invalid_LCALTA_20 pass
2725 19:06:40.380108 alsa_mixer-test_event_missing_LCALTA_20 pass
2726 19:06:40.385121 alsa_mixer-test_event_spurious_LCALTA_20 pass
2727 19:06:40.390649 alsa_mixer-test_get_value_LCALTA_19 pass
2728 19:06:40.391167 alsa_mixer-test_name_LCALTA_19 pass
2729 19:06:40.396189 alsa_mixer-test_write_default_LCALTA_19 pass
2730 19:06:40.401744 alsa_mixer-test_write_valid_LCALTA_19 pass
2731 19:06:40.407278 alsa_mixer-test_write_invalid_LCALTA_19 pass
2732 19:06:40.407779 alsa_mixer-test_event_missing_LCALTA_19 pass
2733 19:06:40.412867 alsa_mixer-test_event_spurious_LCALTA_19 pass
2734 19:06:40.418420 alsa_mixer-test_get_value_LCALTA_18 pass
2735 19:06:40.418936 alsa_mixer-test_name_LCALTA_18 pass
2736 19:06:40.423951 alsa_mixer-test_write_default_LCALTA_18 pass
2737 19:06:40.429498 alsa_mixer-test_write_valid_LCALTA_18 pass
2738 19:06:40.430014 alsa_mixer-test_write_invalid_LCALTA_18 pass
2739 19:06:40.435038 alsa_mixer-test_event_missing_LCALTA_18 pass
2740 19:06:40.440598 alsa_mixer-test_event_spurious_LCALTA_18 pass
2741 19:06:40.441128 alsa_mixer-test_get_value_LCALTA_17 pass
2742 19:06:40.446137 alsa_mixer-test_name_LCALTA_17 pass
2743 19:06:40.451679 alsa_mixer-test_write_default_LCALTA_17 pass
2744 19:06:40.452259 alsa_mixer-test_write_valid_LCALTA_17 pass
2745 19:06:40.457328 alsa_mixer-test_write_invalid_LCALTA_17 pass
2746 19:06:40.462772 alsa_mixer-test_event_missing_LCALTA_17 pass
2747 19:06:40.468387 alsa_mixer-test_event_spurious_LCALTA_17 pass
2748 19:06:40.468898 alsa_mixer-test_get_value_LCALTA_16 pass
2749 19:06:40.473875 alsa_mixer-test_name_LCALTA_16 pass
2750 19:06:40.479430 alsa_mixer-test_write_default_LCALTA_16 pass
2751 19:06:40.479936 alsa_mixer-test_write_valid_LCALTA_16 pass
2752 19:06:40.484958 alsa_mixer-test_write_invalid_LCALTA_16 pass
2753 19:06:40.490500 alsa_mixer-test_event_missing_LCALTA_16 pass
2754 19:06:40.490998 alsa_mixer-test_event_spurious_LCALTA_16 pass
2755 19:06:40.496079 alsa_mixer-test_get_value_LCALTA_15 pass
2756 19:06:40.501603 alsa_mixer-test_name_LCALTA_15 pass
2757 19:06:40.502102 alsa_mixer-test_write_default_LCALTA_15 pass
2758 19:06:40.507145 alsa_mixer-test_write_valid_LCALTA_15 pass
2759 19:06:40.512688 alsa_mixer-test_write_invalid_LCALTA_15 pass
2760 19:06:40.518318 alsa_mixer-test_event_missing_LCALTA_15 pass
2761 19:06:40.518825 alsa_mixer-test_event_spurious_LCALTA_15 pass
2762 19:06:40.523805 alsa_mixer-test_get_value_LCALTA_14 pass
2763 19:06:40.524349 alsa_mixer-test_name_LCALTA_14 pass
2764 19:06:40.529369 alsa_mixer-test_write_default_LCALTA_14 pass
2765 19:06:40.534877 alsa_mixer-test_write_valid_LCALTA_14 pass
2766 19:06:40.540440 alsa_mixer-test_write_invalid_LCALTA_14 pass
2767 19:06:40.540948 alsa_mixer-test_event_missing_LCALTA_14 pass
2768 19:06:40.545967 alsa_mixer-test_event_spurious_LCALTA_14 pass
2769 19:06:40.551502 alsa_mixer-test_get_value_LCALTA_13 pass
2770 19:06:40.552046 alsa_mixer-test_name_LCALTA_13 pass
2771 19:06:40.557061 alsa_mixer-test_write_default_LCALTA_13 pass
2772 19:06:40.562596 alsa_mixer-test_write_valid_LCALTA_13 pass
2773 19:06:40.563106 alsa_mixer-test_write_invalid_LCALTA_13 pass
2774 19:06:40.568192 alsa_mixer-test_event_missing_LCALTA_13 pass
2775 19:06:40.573702 alsa_mixer-test_event_spurious_LCALTA_13 pass
2776 19:06:40.579322 alsa_mixer-test_get_value_LCALTA_12 pass
2777 19:06:40.579837 alsa_mixer-test_name_LCALTA_12 pass
2778 19:06:40.584806 alsa_mixer-test_write_default_LCALTA_12 pass
2779 19:06:40.590384 alsa_mixer-test_write_valid_LCALTA_12 pass
2780 19:06:40.590888 alsa_mixer-test_write_invalid_LCALTA_12 pass
2781 19:06:40.595884 alsa_mixer-test_event_missing_LCALTA_12 pass
2782 19:06:40.601454 alsa_mixer-test_event_spurious_LCALTA_12 pass
2783 19:06:40.601960 alsa_mixer-test_get_value_LCALTA_11 pass
2784 19:06:40.606985 alsa_mixer-test_name_LCALTA_11 pass
2785 19:06:40.612543 alsa_mixer-test_write_default_LCALTA_11 pass
2786 19:06:40.613042 alsa_mixer-test_write_valid_LCALTA_11 pass
2787 19:06:40.618079 alsa_mixer-test_write_invalid_LCALTA_11 pass
2788 19:06:40.623625 alsa_mixer-test_event_missing_LCALTA_11 pass
2789 19:06:40.624163 alsa_mixer-test_event_spurious_LCALTA_11 pass
2790 19:06:40.629151 alsa_mixer-test_get_value_LCALTA_10 pass
2791 19:06:40.634705 alsa_mixer-test_name_LCALTA_10 pass
2792 19:06:40.635210 alsa_mixer-test_write_default_LCALTA_10 pass
2793 19:06:40.640339 alsa_mixer-test_write_valid_LCALTA_10 pass
2794 19:06:40.645815 alsa_mixer-test_write_invalid_LCALTA_10 pass
2795 19:06:40.651377 alsa_mixer-test_event_missing_LCALTA_10 pass
2796 19:06:40.651901 alsa_mixer-test_event_spurious_LCALTA_10 pass
2797 19:06:40.656912 alsa_mixer-test_get_value_LCALTA_9 pass
2798 19:06:40.662448 alsa_mixer-test_name_LCALTA_9 pass
2799 19:06:40.662965 alsa_mixer-test_write_default_LCALTA_9 pass
2800 19:06:40.668000 alsa_mixer-test_write_valid_LCALTA_9 pass
2801 19:06:40.673558 alsa_mixer-test_write_invalid_LCALTA_9 pass
2802 19:06:40.674075 alsa_mixer-test_event_missing_LCALTA_9 pass
2803 19:06:40.679076 alsa_mixer-test_event_spurious_LCALTA_9 pass
2804 19:06:40.684646 alsa_mixer-test_get_value_LCALTA_8 pass
2805 19:06:40.685162 alsa_mixer-test_name_LCALTA_8 pass
2806 19:06:40.690186 alsa_mixer-test_write_default_LCALTA_8 pass
2807 19:06:40.695731 alsa_mixer-test_write_valid_LCALTA_8 pass
2808 19:06:40.696288 alsa_mixer-test_write_invalid_LCALTA_8 pass
2809 19:06:40.701367 alsa_mixer-test_event_missing_LCALTA_8 pass
2810 19:06:40.706831 alsa_mixer-test_event_spurious_LCALTA_8 pass
2811 19:06:40.707352 alsa_mixer-test_get_value_LCALTA_7 pass
2812 19:06:40.712396 alsa_mixer-test_name_LCALTA_7 pass
2813 19:06:40.717922 alsa_mixer-test_write_default_LCALTA_7 pass
2814 19:06:40.718450 alsa_mixer-test_write_valid_LCALTA_7 pass
2815 19:06:40.723458 alsa_mixer-test_write_invalid_LCALTA_7 pass
2816 19:06:40.728992 alsa_mixer-test_event_missing_LCALTA_7 pass
2817 19:06:40.729514 alsa_mixer-test_event_spurious_LCALTA_7 pass
2818 19:06:40.734548 alsa_mixer-test_get_value_LCALTA_6 pass
2819 19:06:40.740118 alsa_mixer-test_name_LCALTA_6 pass
2820 19:06:40.740640 alsa_mixer-test_write_default_LCALTA_6 pass
2821 19:06:40.745658 alsa_mixer-test_write_valid_LCALTA_6 pass
2822 19:06:40.751222 alsa_mixer-test_write_invalid_LCALTA_6 pass
2823 19:06:40.751741 alsa_mixer-test_event_missing_LCALTA_6 pass
2824 19:06:40.756746 alsa_mixer-test_event_spurious_LCALTA_6 pass
2825 19:06:40.762374 alsa_mixer-test_get_value_LCALTA_5 pass
2826 19:06:40.762923 alsa_mixer-test_name_LCALTA_5 pass
2827 19:06:40.767834 alsa_mixer-test_write_default_LCALTA_5 pass
2828 19:06:40.773409 alsa_mixer-test_write_valid_LCALTA_5 pass
2829 19:06:40.773924 alsa_mixer-test_write_invalid_LCALTA_5 pass
2830 19:06:40.778918 alsa_mixer-test_event_missing_LCALTA_5 pass
2831 19:06:40.784482 alsa_mixer-test_event_spurious_LCALTA_5 pass
2832 19:06:40.785004 alsa_mixer-test_get_value_LCALTA_4 pass
2833 19:06:40.790032 alsa_mixer-test_name_LCALTA_4 pass
2834 19:06:40.795568 alsa_mixer-test_write_default_LCALTA_4 pass
2835 19:06:40.796114 alsa_mixer-test_write_valid_LCALTA_4 pass
2836 19:06:40.801119 alsa_mixer-test_write_invalid_LCALTA_4 pass
2837 19:06:40.806666 alsa_mixer-test_event_missing_LCALTA_4 pass
2838 19:06:40.812227 alsa_mixer-test_event_spurious_LCALTA_4 pass
2839 19:06:40.812748 alsa_mixer-test_get_value_LCALTA_3 pass
2840 19:06:40.817762 alsa_mixer-test_name_LCALTA_3 pass
2841 19:06:40.818282 alsa_mixer-test_write_default_LCALTA_3 pass
2842 19:06:40.823382 alsa_mixer-test_write_valid_LCALTA_3 pass
2843 19:06:40.828860 alsa_mixer-test_write_invalid_LCALTA_3 pass
2844 19:06:40.834417 alsa_mixer-test_event_missing_LCALTA_3 pass
2845 19:06:40.834926 alsa_mixer-test_event_spurious_LCALTA_3 pass
2846 19:06:40.839952 alsa_mixer-test_get_value_LCALTA_2 pass
2847 19:06:40.840497 alsa_mixer-test_name_LCALTA_2 pass
2848 19:06:40.845496 alsa_mixer-test_write_default_LCALTA_2 pass
2849 19:06:40.851038 alsa_mixer-test_write_valid_LCALTA_2 pass
2850 19:06:40.856586 alsa_mixer-test_write_invalid_LCALTA_2 pass
2851 19:06:40.857095 alsa_mixer-test_event_missing_LCALTA_2 pass
2852 19:06:40.862126 alsa_mixer-test_event_spurious_LCALTA_2 pass
2853 19:06:40.867645 alsa_mixer-test_get_value_LCALTA_1 pass
2854 19:06:40.868201 alsa_mixer-test_name_LCALTA_1 pass
2855 19:06:40.873229 alsa_mixer-test_write_default_LCALTA_1 pass
2856 19:06:40.879280 alsa_mixer-test_write_valid_LCALTA_1 pass
2857 19:06:40.879838 alsa_mixer-test_write_invalid_LCALTA_1 pass
2858 19:06:40.884420 alsa_mixer-test_event_missing_LCALTA_1 pass
2859 19:06:40.889891 alsa_mixer-test_event_spurious_LCALTA_1 pass
2860 19:06:40.890408 alsa_mixer-test_get_value_LCALTA_0 pass
2861 19:06:40.895424 alsa_mixer-test_name_LCALTA_0 pass
2862 19:06:40.900964 alsa_mixer-test_write_default_LCALTA_0 pass
2863 19:06:40.901483 alsa_mixer-test_write_valid_LCALTA_0 pass
2864 19:06:40.906509 alsa_mixer-test_write_invalid_LCALTA_0 pass
2865 19:06:40.912075 alsa_mixer-test_event_missing_LCALTA_0 pass
2866 19:06:40.912597 alsa_mixer-test_event_spurious_LCALTA_0 pass
2867 19:06:40.917604 alsa_mixer-test pass
2868 19:06:40.923131 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
2869 19:06:40.923654 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
2870 19:06:40.928683 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
2871 19:06:40.934228 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
2872 19:06:40.939761 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
2873 19:06:40.945369 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
2874 19:06:40.945913 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
2875 19:06:40.950879 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
2876 19:06:40.956422 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
2877 19:06:40.961969 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
2878 19:06:40.967512 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
2879 19:06:40.973065 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
2880 19:06:40.973597 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
2881 19:06:40.978624 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
2882 19:06:40.984183 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
2883 19:06:40.989701 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
2884 19:06:40.995246 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
2885 19:06:41.000784 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
2886 19:06:41.001310 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
2887 19:06:41.006378 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
2888 19:06:41.011886 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
2889 19:06:41.017411 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
2890 19:06:41.022985 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
2891 19:06:41.028532 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
2892 19:06:41.029043 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
2893 19:06:41.034069 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
2894 19:06:41.039629 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
2895 19:06:41.045171 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
2896 19:06:41.050698 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
2897 19:06:41.056261 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
2898 19:06:41.061812 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
2899 19:06:41.062332 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
2900 19:06:41.067336 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
2901 19:06:41.072884 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
2902 19:06:41.078518 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
2903 19:06:41.084053 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
2904 19:06:41.089544 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
2905 19:06:41.090074 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
2906 19:06:41.095088 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
2907 19:06:41.100634 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
2908 19:06:41.106155 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
2909 19:06:41.111721 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
2910 19:06:41.112274 alsa_pcm-test pass
2911 19:06:41.122821 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2912 19:06:41.128395 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2913 19:06:41.139449 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2914 19:06:41.145024 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2915 19:06:41.156094 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2916 19:06:41.156625 alsa_test-pcmtest-driver pass
2917 19:06:41.161628 alsa_utimer-test_global_wrong_timers_test pass
2918 19:06:41.167171 alsa_utimer-test_timer_f_utimer fail
2919 19:06:41.167679 alsa_utimer-test fail
2920 19:06:41.172752 + ../../utils/send-to-lava.sh ./output/result.txt
2921 19:06:41.178291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
2922 19:06:41.179278 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
2924 19:06:41.184237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
2925 19:06:41.185032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
2927 19:06:41.193280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
2928 19:06:41.194051 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
2930 19:06:41.226735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
2931 19:06:41.227546 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
2933 19:06:41.280053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
2934 19:06:41.280882 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
2936 19:06:41.331507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
2937 19:06:41.332342 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
2939 19:06:41.382738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
2940 19:06:41.383578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
2942 19:06:41.428695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
2943 19:06:41.429497 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
2945 19:06:41.489733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
2946 19:06:41.490537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
2948 19:06:41.551966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
2949 19:06:41.552816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
2951 19:06:41.610451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
2952 19:06:41.611283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
2954 19:06:41.666671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
2955 19:06:41.667469 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
2957 19:06:41.718794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
2958 19:06:41.719578 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
2960 19:06:41.772402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
2961 19:06:41.773181 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
2963 19:06:41.824359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
2964 19:06:41.825157 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
2966 19:06:41.881293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
2967 19:06:41.882089 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
2969 19:06:41.932742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
2970 19:06:41.933536 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
2972 19:06:41.985138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
2973 19:06:41.985938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
2975 19:06:42.029232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
2976 19:06:42.030008 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
2978 19:06:42.085644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
2979 19:06:42.086484 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
2981 19:06:42.131820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
2982 19:06:42.132656 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
2984 19:06:42.189240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
2985 19:06:42.190024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
2987 19:06:42.240054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
2988 19:06:42.240853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
2990 19:06:42.284527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
2991 19:06:42.285392 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
2993 19:06:42.338325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
2994 19:06:42.339235 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
2996 19:06:42.382559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
2997 19:06:42.383405 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
2999 19:06:42.435578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
3000 19:06:42.436469 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
3002 19:06:42.483727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
3003 19:06:42.484626 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
3005 19:06:42.527279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3006 19:06:42.528117 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3008 19:06:42.579380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3009 19:06:42.580166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3011 19:06:42.629817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3012 19:06:42.630557 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3014 19:06:42.681658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3015 19:06:42.682410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3017 19:06:42.738458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3018 19:06:42.739316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3020 19:06:42.786720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3021 19:06:42.787519 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3023 19:06:42.837181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3024 19:06:42.837992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3026 19:06:42.889341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3027 19:06:42.890197 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3029 19:06:42.947479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3030 19:06:42.948296 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3032 19:06:43.016434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3033 19:06:43.017310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3035 19:06:43.070237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3036 19:06:43.071157 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3038 19:06:43.130167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3039 19:06:43.131095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3041 19:06:43.184378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3042 19:06:43.185197 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3044 19:06:43.230112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3045 19:06:43.230923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3047 19:06:43.274560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3048 19:06:43.275350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3050 19:06:43.326470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3051 19:06:43.327272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3053 19:06:43.377908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3054 19:06:43.378705 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3056 19:06:43.435733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3057 19:06:43.436561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3059 19:06:43.486951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3060 19:06:43.487755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3062 19:06:43.538047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3063 19:06:43.538843 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3065 19:06:43.597266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3066 19:06:43.598069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3068 19:06:43.648952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3069 19:06:43.649729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3071 19:06:43.697843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3072 19:06:43.698636 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3074 19:06:43.750951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3075 19:06:43.751724 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3077 19:06:43.804475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3078 19:06:43.805249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3080 19:06:43.845977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3081 19:06:43.846740 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3083 19:06:43.897996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3084 19:06:43.898760 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3086 19:06:43.950840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3087 19:06:43.951606 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3089 19:06:44.004728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3090 19:06:44.005485 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3092 19:06:44.056027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3093 19:06:44.056788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3095 19:06:44.106692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3096 19:06:44.107495 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3098 19:06:44.156829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3099 19:06:44.157594 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3101 19:06:44.205016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3102 19:06:44.205794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3104 19:06:44.258359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3105 19:06:44.259107 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3107 19:06:44.315315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3108 19:06:44.316164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3110 19:06:44.367037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3111 19:06:44.367820 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3113 19:06:44.416739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3114 19:06:44.417559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3116 19:06:44.467269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3117 19:06:44.468092 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3119 19:06:44.516076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3120 19:06:44.516863 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3122 19:06:44.564866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3123 19:06:44.565673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3125 19:06:44.619870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3126 19:06:44.620710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3128 19:06:44.662742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3129 19:06:44.663553 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3131 19:06:44.717759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3132 19:06:44.718546 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3134 19:06:44.774550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3135 19:06:44.775330 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3137 19:06:44.824156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3138 19:06:44.824942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3140 19:06:44.880258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3141 19:06:44.881061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3143 19:06:44.924276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3144 19:06:44.925046 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3146 19:06:44.971612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3147 19:06:44.972429 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3149 19:06:45.022483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3150 19:06:45.023252 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3152 19:06:45.075270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3153 19:06:45.076065 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3155 19:06:45.121622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3156 19:06:45.122425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3158 19:06:45.166605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3159 19:06:45.167361 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3161 19:06:45.213452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3162 19:06:45.214206 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3164 19:06:45.276770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3165 19:06:45.277540 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3167 19:06:45.328607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3168 19:06:45.329375 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3170 19:06:45.379707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3171 19:06:45.380558 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3173 19:06:45.423488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3174 19:06:45.424282 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3176 19:06:45.469967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3177 19:06:45.470723 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3179 19:06:45.517436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3180 19:06:45.518208 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3182 19:06:45.574730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3183 19:06:45.575560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3185 19:06:45.621599 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3186 19:06:45.622390 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3188 19:06:45.673604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3189 19:06:45.674473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3191 19:06:45.725260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3192 19:06:45.726099 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3194 19:06:45.776852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3195 19:06:45.777643 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3197 19:06:45.821751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3198 19:06:45.822638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3200 19:06:45.865651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3201 19:06:45.866459 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3203 19:06:45.916950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3204 19:06:45.917728 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3206 19:06:45.968056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3207 19:06:45.968903 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3209 19:06:46.010172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3210 19:06:46.010958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3212 19:06:46.058255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3213 19:06:46.059078 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3215 19:06:46.109224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3216 19:06:46.110067 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3218 19:06:46.157278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3219 19:06:46.158052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3221 19:06:46.214483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3222 19:06:46.215263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3224 19:06:46.258854 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3225 19:06:46.259651 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3227 19:06:46.315495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3228 19:06:46.316379 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3230 19:06:46.370033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3231 19:06:46.370837 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3233 19:06:46.420654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3234 19:06:46.421448 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3236 19:06:46.472628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3237 19:06:46.473415 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3239 19:06:46.536771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3240 19:06:46.537598 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3242 19:06:46.586919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3243 19:06:46.587729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3245 19:06:46.640657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3246 19:06:46.641444 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3248 19:06:46.689665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3249 19:06:46.690438 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3251 19:06:46.745646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3252 19:06:46.746458 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3254 19:06:46.797815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3255 19:06:46.798589 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3257 19:06:46.858208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3258 19:06:46.858982 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3260 19:06:46.903569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3261 19:06:46.904372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3263 19:06:46.956756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3264 19:06:46.957524 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3266 19:06:47.004224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3267 19:06:47.005016 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3269 19:06:47.062350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3270 19:06:47.063128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3272 19:06:47.116720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3273 19:06:47.117541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3275 19:06:47.167226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3276 19:06:47.168034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3278 19:06:47.221655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3279 19:06:47.222443 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3281 19:06:47.275914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3282 19:06:47.276885 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3284 19:06:47.326571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3285 19:06:47.327362 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3287 19:06:47.387317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3288 19:06:47.388173 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3290 19:06:47.440212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3291 19:06:47.441012 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3293 19:06:47.488111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3294 19:06:47.488938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3296 19:06:47.546278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3297 19:06:47.547059 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3299 19:06:47.604654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3300 19:06:47.605421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3302 19:06:47.658253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3303 19:06:47.659072 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3305 19:06:47.703776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3306 19:06:47.704599 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3308 19:06:47.748636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3309 19:06:47.749404 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3311 19:06:47.807148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3312 19:06:47.807919 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3314 19:06:47.864210 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3315 19:06:47.864979 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3317 19:06:47.928529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3318 19:06:47.929317 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3320 19:06:47.975821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3321 19:06:47.976638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3323 19:06:48.035843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3324 19:06:48.036644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3326 19:06:48.093765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3327 19:06:48.094587 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3329 19:06:48.152238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3330 19:06:48.153123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3332 19:06:48.216647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3333 19:06:48.217604 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3335 19:06:48.278725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3336 19:06:48.279634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3338 19:06:48.340505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3339 19:06:48.341349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3341 19:06:48.420420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3342 19:06:48.421368 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3344 19:06:48.480480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3345 19:06:48.481489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3347 19:06:48.590254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3348 19:06:48.591136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3350 19:06:48.660325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3351 19:06:48.661263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3353 19:06:48.723746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3354 19:06:48.724457 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3356 19:06:48.771085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3357 19:06:48.772121 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3359 19:06:48.824927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3360 19:06:48.825815 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3362 19:06:48.875109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3363 19:06:48.876175 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3365 19:06:48.934659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3366 19:06:48.935533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3368 19:06:48.987180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3369 19:06:48.988086 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3371 19:06:49.040379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3372 19:06:49.041298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3374 19:06:49.095855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3375 19:06:49.096835 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3377 19:06:49.168656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3378 19:06:49.169676 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3380 19:06:49.274124 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3381 19:06:49.275037 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3383 19:06:49.340521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3384 19:06:49.341464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3386 19:06:49.399712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3387 19:06:49.400633 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3389 19:06:49.445252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3390 19:06:49.446094 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3392 19:06:49.502788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3393 19:06:49.503559 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3395 19:06:49.559887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3396 19:06:49.560715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3398 19:06:49.623676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3399 19:06:49.624464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3401 19:06:49.676184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3402 19:06:49.677094 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3404 19:06:49.734531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3405 19:06:49.735316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3407 19:06:49.784371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3408 19:06:49.785108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3410 19:06:49.834917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3411 19:06:49.835686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3413 19:06:49.886701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3414 19:06:49.887453 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3416 19:06:49.943412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3417 19:06:49.944166 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3419 19:06:49.994458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3420 19:06:49.995220 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3422 19:06:50.045177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3423 19:06:50.045946 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3425 19:06:50.094409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3426 19:06:50.095191 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3428 19:06:50.150706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3429 19:06:50.151471 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3431 19:06:50.197870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3432 19:06:50.198626 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3434 19:06:50.250617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3435 19:06:50.251360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3437 19:06:50.297394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3438 19:06:50.298163 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3440 19:06:50.353454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3441 19:06:50.354289 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3443 19:06:50.400904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3444 19:06:50.401650 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3446 19:06:50.451536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3447 19:06:50.452307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3449 19:06:50.503671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3450 19:06:50.504489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3452 19:06:50.564481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3453 19:06:50.565277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3455 19:06:50.623563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3456 19:06:50.624492 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3458 19:06:50.674498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3459 19:06:50.675236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3461 19:06:50.728519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3462 19:06:50.729265 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3464 19:06:50.790062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3465 19:06:50.790889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3467 19:06:50.855508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3468 19:06:50.856414 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3470 19:06:50.913447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3471 19:06:50.914254 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3473 19:06:50.972846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3474 19:06:50.973625 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3476 19:06:51.033130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3477 19:06:51.033992 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3479 19:06:51.096369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3480 19:06:51.097129 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3482 19:06:51.149078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3483 19:06:51.149875 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3485 19:06:51.203861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3486 19:06:51.204729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3488 19:06:51.264643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3489 19:06:51.265440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3491 19:06:51.322509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3492 19:06:51.323277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3494 19:06:51.382521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3495 19:06:51.383287 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3497 19:06:51.442613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3498 19:06:51.443368 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3500 19:06:51.495863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3501 19:06:51.496661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3503 19:06:51.554669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3504 19:06:51.555415 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3506 19:06:51.613465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3507 19:06:51.614215 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3509 19:06:51.672418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3510 19:06:51.673162 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3512 19:06:51.725519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3513 19:06:51.726278 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3515 19:06:51.778273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3516 19:06:51.779059 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3518 19:06:51.832673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3519 19:06:51.833441 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3521 19:06:51.886273 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3522 19:06:51.887119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3524 19:06:51.935526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3525 19:06:51.936320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3527 19:06:51.980345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3528 19:06:51.981099 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3530 19:06:52.033667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3531 19:06:52.034432 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3533 19:06:52.085522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3534 19:06:52.086320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3536 19:06:52.148527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3537 19:06:52.149315 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3539 19:06:52.191853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3540 19:06:52.192690 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3542 19:06:52.247635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3543 19:06:52.248614 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3545 19:06:52.295242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3546 19:06:52.296189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3548 19:06:52.349782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3549 19:06:52.350565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3551 19:06:52.397402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3552 19:06:52.398193 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3554 19:06:52.448983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3555 19:06:52.449760 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3557 19:06:52.503167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3558 19:06:52.503901 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3560 19:06:52.554993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3561 19:06:52.555799 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3563 19:06:52.600271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3564 19:06:52.601044 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3566 19:06:52.647099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3567 19:06:52.647878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3569 19:06:52.703232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3570 19:06:52.704075 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3572 19:06:52.753969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3573 19:06:52.754944 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3575 19:06:52.805875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3576 19:06:52.806674 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3578 19:06:52.857211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3579 19:06:52.858003 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3581 19:06:52.910342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3582 19:06:52.911108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3584 19:06:52.973415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3585 19:06:52.974236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3587 19:06:53.019302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3588 19:06:53.020097 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3590 19:06:53.071003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3591 19:06:53.071850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3593 19:06:53.130246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3594 19:06:53.131061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3596 19:06:53.175977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3597 19:06:53.176878 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3599 19:06:53.234294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3600 19:06:53.235067 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3602 19:06:53.299938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3603 19:06:53.300850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3605 19:06:53.349189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3606 19:06:53.349996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3608 19:06:53.402903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3609 19:06:53.403702 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3611 19:06:53.466253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3612 19:06:53.467073 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3614 19:06:53.523339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3615 19:06:53.524125 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3617 19:06:53.583865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3618 19:06:53.584690 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3620 19:06:53.628688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3621 19:06:53.629478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3623 19:06:53.677258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3624 19:06:53.678053 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3626 19:06:53.723652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3627 19:06:53.724488 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3629 19:06:53.782929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3630 19:06:53.783767 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3632 19:06:53.841414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3633 19:06:53.842246 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3635 19:06:53.895609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3636 19:06:53.896500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3638 19:06:53.956919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3639 19:06:53.957745 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3641 19:06:54.013921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3642 19:06:54.014755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3644 19:06:54.169395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3645 19:06:54.170024 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3647 19:06:54.224242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3648 19:06:54.225020 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3650 19:06:54.284552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3651 19:06:54.285349 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3653 19:06:54.339413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3654 19:06:54.340426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3656 19:06:54.395431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3657 19:06:54.396223 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3659 19:06:54.442815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3660 19:06:54.443668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3662 19:06:54.498548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3663 19:06:54.499404 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3665 19:06:54.555534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3666 19:06:54.556389 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3668 19:06:54.606269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3669 19:06:54.607043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3671 19:06:54.659135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3672 19:06:54.659896 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3674 19:06:54.709767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3675 19:06:54.710533 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3677 19:06:54.768377 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3678 19:06:54.769145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3680 19:06:54.825512 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3681 19:06:54.826272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3683 19:06:54.879219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3684 19:06:54.879973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3686 19:06:54.935542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3687 19:06:54.936319 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3689 19:06:54.992524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3690 19:06:54.993292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3692 19:06:55.049354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3693 19:06:55.050114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3695 19:06:55.094411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3696 19:06:55.095289 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3698 19:06:55.155133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3699 19:06:55.155899 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3701 19:06:55.207466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3702 19:06:55.208330 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3704 19:06:55.263401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3705 19:06:55.264310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3707 19:06:55.316315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3708 19:06:55.317125 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3710 19:06:55.363127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3711 19:06:55.363970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3713 19:06:55.425248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3714 19:06:55.426012 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3716 19:06:55.471501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3717 19:06:55.472405 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3719 19:06:55.532868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3720 19:06:55.533638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3722 19:06:55.589293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3723 19:06:55.590133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3725 19:06:55.648392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3726 19:06:55.649273 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3728 19:06:55.699440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3729 19:06:55.700251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3731 19:06:55.750020 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3732 19:06:55.750829 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3734 19:06:55.802620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3735 19:06:55.803473 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3737 19:06:55.861803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3738 19:06:55.862692 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3740 19:06:55.913928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3741 19:06:55.914772 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3743 19:06:55.967647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3744 19:06:55.968644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3746 19:06:56.018379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3747 19:06:56.019253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3749 19:06:56.064582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3750 19:06:56.065534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3752 19:06:56.121856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3753 19:06:56.122784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3755 19:06:56.182998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3756 19:06:56.183889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3758 19:06:56.244914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3759 19:06:56.245823 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3761 19:06:56.299769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3762 19:06:56.300686 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3764 19:06:56.352820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3765 19:06:56.353773 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3767 19:06:56.408717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3768 19:06:56.409597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3770 19:06:56.461677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3771 19:06:56.462503 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3773 19:06:56.519722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3774 19:06:56.520615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3776 19:06:56.574455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3777 19:06:56.575288 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3779 19:06:56.625657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3780 19:06:56.626490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3782 19:06:56.677657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3783 19:06:56.678484 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3785 19:06:56.721550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3786 19:06:56.722451 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3788 19:06:56.771419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3789 19:06:56.772436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3791 19:06:56.820453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3792 19:06:56.821405 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3794 19:06:56.882115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3795 19:06:56.883002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3797 19:06:56.936795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3798 19:06:56.937733 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3800 19:06:57.000465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3801 19:06:57.001355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3803 19:06:57.058088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3804 19:06:57.059052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3806 19:06:57.113880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3807 19:06:57.114848 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3809 19:06:57.165960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3810 19:06:57.166829 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3812 19:06:57.218307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3813 19:06:57.219054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3815 19:06:57.261931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3816 19:06:57.262736 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3818 19:06:57.324535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3819 19:06:57.325316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3821 19:06:57.368291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3822 19:06:57.369095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3824 19:06:57.422927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3825 19:06:57.423777 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3827 19:06:57.476739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3828 19:06:57.477528 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3830 19:06:57.528449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3831 19:06:57.529253 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3833 19:06:57.576224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3834 19:06:57.576989 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3836 19:06:57.635517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3837 19:06:57.636299 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3839 19:06:57.686942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3840 19:06:57.687674 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3842 19:06:57.736836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3843 19:06:57.737567 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3845 19:06:57.791075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3846 19:06:57.791826 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
3848 19:06:57.837236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
3849 19:06:57.837970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
3851 19:06:57.891363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
3852 19:06:57.892090 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
3854 19:06:57.942928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
3855 19:06:57.943678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
3857 19:06:57.989841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
3858 19:06:57.990583 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
3860 19:06:58.042776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
3861 19:06:58.043531 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
3863 19:06:58.095731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
3864 19:06:58.096613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
3866 19:06:58.156770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
3867 19:06:58.157539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
3869 19:06:58.200718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
3870 19:06:58.201458 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
3872 19:06:58.262356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
3873 19:06:58.263105 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
3875 19:06:58.320954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
3876 19:06:58.321768 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
3878 19:06:58.380808 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
3879 19:06:58.381599 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
3881 19:06:58.434165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
3882 19:06:58.434988 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
3884 19:06:58.482107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
3885 19:06:58.482903 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
3887 19:06:58.532045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
3888 19:06:58.532883 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
3890 19:06:58.585421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
3891 19:06:58.586236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
3893 19:06:58.636600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
3894 19:06:58.637370 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
3896 19:06:58.696744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
3897 19:06:58.697500 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
3899 19:06:58.740227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
3900 19:06:58.740952 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
3902 19:06:58.799331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
3903 19:06:58.800080 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
3905 19:06:58.846061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
3906 19:06:58.846776 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
3908 19:06:58.899823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
3909 19:06:58.900588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
3911 19:06:58.946382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
3912 19:06:58.947102 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
3914 19:06:58.991610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
3915 19:06:58.992355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
3917 19:06:59.047862 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
3918 19:06:59.048605 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
3920 19:06:59.097666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
3921 19:06:59.098417 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
3923 19:06:59.155234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
3924 19:06:59.155945 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
3926 19:06:59.208780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
3927 19:06:59.209491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
3929 19:06:59.259680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
3930 19:06:59.260421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
3932 19:06:59.305191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
3933 19:06:59.305891 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
3935 19:06:59.364918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
3936 19:06:59.365622 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
3938 19:06:59.411145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
3939 19:06:59.411870 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
3941 19:06:59.464173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
3942 19:06:59.464894 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
3944 19:06:59.520178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
3945 19:06:59.520908 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
3947 19:06:59.573330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
3948 19:06:59.574070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
3950 19:06:59.626112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
3951 19:06:59.626889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
3953 19:06:59.677018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
3954 19:06:59.677749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
3956 19:06:59.722165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
3957 19:06:59.722871 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
3959 19:06:59.776074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
3960 19:06:59.776791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
3962 19:06:59.825374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
3963 19:06:59.826081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
3965 19:06:59.876969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
3966 19:06:59.877695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
3968 19:06:59.925884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
3969 19:06:59.926590 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
3971 19:06:59.972844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
3972 19:06:59.973539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
3974 19:07:00.025920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
3975 19:07:00.026633 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
3977 19:07:00.074027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
3978 19:07:00.074747 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
3980 19:07:00.126533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
3981 19:07:00.127278 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
3983 19:07:00.182021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
3984 19:07:00.182732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
3986 19:07:00.232983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
3987 19:07:00.233696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
3989 19:07:00.293678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
3990 19:07:00.294376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
3992 19:07:00.338169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
3993 19:07:00.338899 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
3995 19:07:00.392903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
3996 19:07:00.393617 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
3998 19:07:00.445264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
3999 19:07:00.445970 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
4001 19:07:00.497289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
4002 19:07:00.498030 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
4004 19:07:00.547286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
4005 19:07:00.548028 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4007 19:07:00.603481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4008 19:07:00.604209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4010 19:07:00.659581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4011 19:07:00.660332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4013 19:07:00.717905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4014 19:07:00.718612 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4016 19:07:00.775206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4017 19:07:00.775974 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4019 19:07:00.823206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4020 19:07:00.824009 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4022 19:07:00.872056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4023 19:07:00.872805 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4025 19:07:00.926873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4026 19:07:00.927630 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4028 19:07:00.970687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4029 19:07:00.971449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4031 19:07:01.023342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4032 19:07:01.024089 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4034 19:07:01.068825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4035 19:07:01.069560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4037 19:07:01.128933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4038 19:07:01.129683 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4040 19:07:01.170714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4041 19:07:01.171434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4043 19:07:01.223566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4044 19:07:01.224382 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4046 19:07:01.276393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4047 19:07:01.277212 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4049 19:07:01.321031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4050 19:07:01.321787 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4052 19:07:01.378941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4053 19:07:01.379695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4055 19:07:01.429059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4056 19:07:01.429829 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4058 19:07:01.482947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4059 19:07:01.483762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4061 19:07:01.534797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4062 19:07:01.535556 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4064 19:07:01.594093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4065 19:07:01.594851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4067 19:07:01.637006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4068 19:07:01.637739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4070 19:07:01.689676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4071 19:07:01.690417 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4073 19:07:01.734023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4074 19:07:01.734732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4076 19:07:01.779451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4077 19:07:01.780206 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4079 19:07:01.832330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4080 19:07:01.833063 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4082 19:07:01.875887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4083 19:07:01.876648 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4085 19:07:01.935894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4086 19:07:01.936639 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4088 19:07:01.981744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4089 19:07:01.982546 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4091 19:07:02.035639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4092 19:07:02.036440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4094 19:07:02.080693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4095 19:07:02.081465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4097 19:07:02.132483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4098 19:07:02.133247 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4100 19:07:02.185613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4101 19:07:02.186341 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4103 19:07:02.235077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4104 19:07:02.235871 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4106 19:07:02.293281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4107 19:07:02.294056 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4109 19:07:02.352452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4110 19:07:02.353254 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4112 19:07:02.407902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4113 19:07:02.408774 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4115 19:07:02.457339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4116 19:07:02.458142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4118 19:07:02.512385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4119 19:07:02.513160 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4121 19:07:02.559255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4122 19:07:02.560079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4124 19:07:02.611623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4125 19:07:02.612452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4127 19:07:02.658667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4128 19:07:02.659449 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4130 19:07:02.710454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4131 19:07:02.711260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4133 19:07:02.756307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4134 19:07:02.757110 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4136 19:07:02.814979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4137 19:07:02.815864 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4139 19:07:02.861655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4140 19:07:02.862469 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4142 19:07:02.914924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4143 19:07:02.915737 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4145 19:07:02.972126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4146 19:07:02.973070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4148 19:07:03.016492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4149 19:07:03.017326 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4151 19:07:03.070201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4152 19:07:03.071013 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4154 19:07:03.130297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4155 19:07:03.131130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4157 19:07:03.179631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4158 19:07:03.180453 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4160 19:07:03.229607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4161 19:07:03.230385 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4163 19:07:03.279853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4164 19:07:03.280668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4166 19:07:03.328989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4167 19:07:03.329762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4169 19:07:03.379308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4170 19:07:03.380086 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4172 19:07:03.441713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4173 19:07:03.442489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4175 19:07:03.493753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4176 19:07:03.494521 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4178 19:07:03.546398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4179 19:07:03.547162 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4181 19:07:03.590193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4182 19:07:03.590973 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4184 19:07:03.634645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4185 19:07:03.635425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4187 19:07:03.691355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4188 19:07:03.692128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4190 19:07:03.742731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4191 19:07:03.743507 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4193 19:07:03.800938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4194 19:07:03.801748 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4196 19:07:03.845193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4197 19:07:03.845966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4199 19:07:03.905039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4200 19:07:03.905821 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4202 19:07:03.963929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4203 19:07:03.964746 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4205 19:07:04.010991 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4207 19:07:04.013970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4208 19:07:04.060907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4209 19:07:04.061683 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4211 19:07:04.108686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4212 19:07:04.109493 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4214 19:07:04.165776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4215 19:07:04.166561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4217 19:07:04.224850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4218 19:07:04.225631 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4220 19:07:04.284857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4221 19:07:04.285635 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4223 19:07:04.328864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4224 19:07:04.329640 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4226 19:07:04.376817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4227 19:07:04.377597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4229 19:07:04.430548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4230 19:07:04.431320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4232 19:07:04.478914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4233 19:07:04.479689 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4235 19:07:04.524236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4236 19:07:04.525005 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4238 19:07:04.581132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4239 19:07:04.581911 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4241 19:07:04.634905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4242 19:07:04.635668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4244 19:07:04.691473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4245 19:07:04.692272 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4247 19:07:04.736519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4248 19:07:04.737288 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4250 19:07:04.796516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4251 19:07:04.797307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4253 19:07:04.848838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4254 19:07:04.849609 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4256 19:07:04.900900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4257 19:07:04.901672 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4259 19:07:04.950632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4260 19:07:04.951401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4262 19:07:05.004361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4263 19:07:05.005127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4265 19:07:05.056708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4266 19:07:05.057478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4268 19:07:05.114261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4269 19:07:05.115040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4271 19:07:05.162785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4272 19:07:05.163552 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4274 19:07:05.210467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4275 19:07:05.211234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4277 19:07:05.264583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4278 19:07:05.265376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4280 19:07:05.310956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4281 19:07:05.311727 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4283 19:07:05.365426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4284 19:07:05.366202 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4286 19:07:05.410506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4287 19:07:05.411275 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4289 19:07:05.458984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4290 19:07:05.459744 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4292 19:07:05.514509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4293 19:07:05.515277 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4295 19:07:05.567292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4296 19:07:05.568085 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4298 19:07:05.618052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4299 19:07:05.618819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4301 19:07:05.671478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4302 19:07:05.672275 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4304 19:07:05.736258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4305 19:07:05.737033 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4307 19:07:05.781311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4308 19:07:05.782086 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4310 19:07:05.836185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4311 19:07:05.836960 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4313 19:07:05.880614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4314 19:07:05.881381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4316 19:07:05.934291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4317 19:07:05.935055 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4319 19:07:05.985525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4320 19:07:05.986301 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4322 19:07:06.042467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4323 19:07:06.043249 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4325 19:07:06.088634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4326 19:07:06.089412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4328 19:07:06.137666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4329 19:07:06.138457 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4331 19:07:06.184025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4332 19:07:06.184796 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4334 19:07:06.226046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4335 19:07:06.226824 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4337 19:07:06.282534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4338 19:07:06.283305 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4340 19:07:06.327258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4341 19:07:06.328059 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4343 19:07:06.376106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4344 19:07:06.376873 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4346 19:07:06.438162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4347 19:07:06.438938 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4349 19:07:06.484670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4350 19:07:06.485444 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4352 19:07:06.526423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4353 19:07:06.527285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4355 19:07:06.572821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4356 19:07:06.573615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4358 19:07:06.624468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4359 19:07:06.625313 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4361 19:07:06.675454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4363 19:07:06.680705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4364 19:07:06.681211 + set +x
4365 19:07:06.685696 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 935712_1.6.2.4.5>
4366 19:07:06.686194 <LAVA_TEST_RUNNER EXIT>
4367 19:07:06.686867 Received signal: <ENDRUN> 1_kselftest-alsa 935712_1.6.2.4.5
4368 19:07:06.687328 Ending use of test pattern.
4369 19:07:06.687739 Ending test lava.1_kselftest-alsa (935712_1.6.2.4.5), duration 41.13
4371 19:07:06.689331 ok: lava_test_shell seems to have completed
4372 19:07:06.711882 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4373 19:07:06.713694 end: 3.1 lava-test-shell (duration 00:00:42) [common]
4374 19:07:06.714310 end: 3 lava-test-retry (duration 00:00:42) [common]
4375 19:07:06.714902 start: 4 finalize (timeout 00:06:07) [common]
4376 19:07:06.715484 start: 4.1 power-off (timeout 00:00:30) [common]
4377 19:07:06.716449 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4378 19:07:06.750795 >> OK - accepted request
4379 19:07:06.752856 Returned 0 in 0 seconds
4380 19:07:06.853994 end: 4.1 power-off (duration 00:00:00) [common]
4382 19:07:06.855718 start: 4.2 read-feedback (timeout 00:06:07) [common]
4383 19:07:06.856902 Listened to connection for namespace 'common' for up to 1s
4384 19:07:07.857678 Finalising connection for namespace 'common'
4385 19:07:07.858336 Disconnecting from shell: Finalise
4386 19:07:07.858893 / #
4387 19:07:07.959884 end: 4.2 read-feedback (duration 00:00:01) [common]
4388 19:07:07.960644 end: 4 finalize (duration 00:00:01) [common]
4389 19:07:07.961281 Cleaning after the job
4390 19:07:07.961850 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/935712/tftp-deploy-1sxpfpx3/ramdisk
4391 19:07:07.975831 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/935712/tftp-deploy-1sxpfpx3/kernel
4392 19:07:08.017740 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/935712/tftp-deploy-1sxpfpx3/dtb
4393 19:07:08.018634 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/935712/tftp-deploy-1sxpfpx3/nfsrootfs
4394 19:07:08.186948 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/935712/tftp-deploy-1sxpfpx3/modules
4395 19:07:08.207455 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/935712
4396 19:07:11.343802 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/935712
4397 19:07:11.344415 Job finished correctly