Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 19:07:34.028494 lava-dispatcher, installed at version: 2024.01
2 19:07:34.029292 start: 0 validate
3 19:07:34.029768 Start time: 2024-11-04 19:07:34.029739+00:00 (UTC)
4 19:07:34.030312 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 19:07:34.030863 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 19:07:34.073167 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 19:07:34.073696 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-98-g57d5fb99dade%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 19:07:34.107737 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 19:07:34.108540 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-98-g57d5fb99dade%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 19:07:34.140368 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 19:07:34.140914 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 19:07:34.171971 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 19:07:34.172525 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc6-98-g57d5fb99dade%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 19:07:34.209989 validate duration: 0.18
16 19:07:34.210830 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:07:34.211147 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:07:34.211453 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:07:34.212045 Not decompressing ramdisk as can be used compressed.
20 19:07:34.212524 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 19:07:34.212803 saving as /var/lib/lava/dispatcher/tmp/935717/tftp-deploy-_lt89r3h/ramdisk/initrd.cpio.gz
22 19:07:34.213068 total size: 5628140 (5 MB)
23 19:07:34.249224 progress 0 % (0 MB)
24 19:07:34.253491 progress 5 % (0 MB)
25 19:07:34.257826 progress 10 % (0 MB)
26 19:07:34.261506 progress 15 % (0 MB)
27 19:07:34.265682 progress 20 % (1 MB)
28 19:07:34.269445 progress 25 % (1 MB)
29 19:07:34.273481 progress 30 % (1 MB)
30 19:07:34.277578 progress 35 % (1 MB)
31 19:07:34.281271 progress 40 % (2 MB)
32 19:07:34.285364 progress 45 % (2 MB)
33 19:07:34.289075 progress 50 % (2 MB)
34 19:07:34.293195 progress 55 % (2 MB)
35 19:07:34.297241 progress 60 % (3 MB)
36 19:07:34.300897 progress 65 % (3 MB)
37 19:07:34.304972 progress 70 % (3 MB)
38 19:07:34.308651 progress 75 % (4 MB)
39 19:07:34.312753 progress 80 % (4 MB)
40 19:07:34.316382 progress 85 % (4 MB)
41 19:07:34.320443 progress 90 % (4 MB)
42 19:07:34.324249 progress 95 % (5 MB)
43 19:07:34.327541 progress 100 % (5 MB)
44 19:07:34.328224 5 MB downloaded in 0.12 s (46.62 MB/s)
45 19:07:34.328800 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:07:34.329737 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:07:34.330045 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:07:34.330323 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:07:34.330801 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-98-g57d5fb99dade/arm64/defconfig/gcc-12/kernel/Image
51 19:07:34.331076 saving as /var/lib/lava/dispatcher/tmp/935717/tftp-deploy-_lt89r3h/kernel/Image
52 19:07:34.331290 total size: 45713920 (43 MB)
53 19:07:34.331504 No compression specified
54 19:07:34.367105 progress 0 % (0 MB)
55 19:07:34.396434 progress 5 % (2 MB)
56 19:07:34.426340 progress 10 % (4 MB)
57 19:07:34.455349 progress 15 % (6 MB)
58 19:07:34.484077 progress 20 % (8 MB)
59 19:07:34.512774 progress 25 % (10 MB)
60 19:07:34.541737 progress 30 % (13 MB)
61 19:07:34.570491 progress 35 % (15 MB)
62 19:07:34.599398 progress 40 % (17 MB)
63 19:07:34.628123 progress 45 % (19 MB)
64 19:07:34.656661 progress 50 % (21 MB)
65 19:07:34.685198 progress 55 % (24 MB)
66 19:07:34.713691 progress 60 % (26 MB)
67 19:07:34.742131 progress 65 % (28 MB)
68 19:07:34.770691 progress 70 % (30 MB)
69 19:07:34.799670 progress 75 % (32 MB)
70 19:07:34.828526 progress 80 % (34 MB)
71 19:07:34.856506 progress 85 % (37 MB)
72 19:07:34.885073 progress 90 % (39 MB)
73 19:07:34.913624 progress 95 % (41 MB)
74 19:07:34.941712 progress 100 % (43 MB)
75 19:07:34.942271 43 MB downloaded in 0.61 s (71.36 MB/s)
76 19:07:34.942753 end: 1.2.1 http-download (duration 00:00:01) [common]
78 19:07:34.943576 end: 1.2 download-retry (duration 00:00:01) [common]
79 19:07:34.943861 start: 1.3 download-retry (timeout 00:09:59) [common]
80 19:07:34.944162 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 19:07:34.944614 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-98-g57d5fb99dade/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 19:07:34.944896 saving as /var/lib/lava/dispatcher/tmp/935717/tftp-deploy-_lt89r3h/dtb/meson-g12b-a311d-libretech-cc.dtb
83 19:07:34.945107 total size: 54703 (0 MB)
84 19:07:34.945321 No compression specified
85 19:07:34.984830 progress 59 % (0 MB)
86 19:07:34.985873 progress 100 % (0 MB)
87 19:07:34.986555 0 MB downloaded in 0.04 s (1.26 MB/s)
88 19:07:34.987159 end: 1.3.1 http-download (duration 00:00:00) [common]
90 19:07:34.988193 end: 1.3 download-retry (duration 00:00:00) [common]
91 19:07:34.988531 start: 1.4 download-retry (timeout 00:09:59) [common]
92 19:07:34.988864 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 19:07:34.989495 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 19:07:34.989829 saving as /var/lib/lava/dispatcher/tmp/935717/tftp-deploy-_lt89r3h/nfsrootfs/full.rootfs.tar
95 19:07:34.990085 total size: 474398908 (452 MB)
96 19:07:34.990349 Using unxz to decompress xz
97 19:07:35.028087 progress 0 % (0 MB)
98 19:07:36.185660 progress 5 % (22 MB)
99 19:07:37.674103 progress 10 % (45 MB)
100 19:07:38.126418 progress 15 % (67 MB)
101 19:07:38.954078 progress 20 % (90 MB)
102 19:07:39.492303 progress 25 % (113 MB)
103 19:07:39.858260 progress 30 % (135 MB)
104 19:07:40.470199 progress 35 % (158 MB)
105 19:07:41.387681 progress 40 % (181 MB)
106 19:07:42.234136 progress 45 % (203 MB)
107 19:07:42.933330 progress 50 % (226 MB)
108 19:07:43.571844 progress 55 % (248 MB)
109 19:07:44.788981 progress 60 % (271 MB)
110 19:07:46.274911 progress 65 % (294 MB)
111 19:07:47.945418 progress 70 % (316 MB)
112 19:07:51.005475 progress 75 % (339 MB)
113 19:07:53.430568 progress 80 % (361 MB)
114 19:07:56.295126 progress 85 % (384 MB)
115 19:07:59.408283 progress 90 % (407 MB)
116 19:08:02.562133 progress 95 % (429 MB)
117 19:08:05.710920 progress 100 % (452 MB)
118 19:08:05.724073 452 MB downloaded in 30.73 s (14.72 MB/s)
119 19:08:05.724807 end: 1.4.1 http-download (duration 00:00:31) [common]
121 19:08:05.725803 end: 1.4 download-retry (duration 00:00:31) [common]
122 19:08:05.726145 start: 1.5 download-retry (timeout 00:09:28) [common]
123 19:08:05.726469 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 19:08:05.727117 downloading http://storage.kernelci.org/pm/testing/v6.12-rc6-98-g57d5fb99dade/arm64/defconfig/gcc-12/modules.tar.xz
125 19:08:05.727441 saving as /var/lib/lava/dispatcher/tmp/935717/tftp-deploy-_lt89r3h/modules/modules.tar
126 19:08:05.727694 total size: 11616108 (11 MB)
127 19:08:05.727953 Using unxz to decompress xz
128 19:08:05.774497 progress 0 % (0 MB)
129 19:08:05.841772 progress 5 % (0 MB)
130 19:08:05.919795 progress 10 % (1 MB)
131 19:08:06.018146 progress 15 % (1 MB)
132 19:08:06.112384 progress 20 % (2 MB)
133 19:08:06.193358 progress 25 % (2 MB)
134 19:08:06.270669 progress 30 % (3 MB)
135 19:08:06.351107 progress 35 % (3 MB)
136 19:08:06.428037 progress 40 % (4 MB)
137 19:08:06.507406 progress 45 % (5 MB)
138 19:08:06.592212 progress 50 % (5 MB)
139 19:08:06.676063 progress 55 % (6 MB)
140 19:08:06.762239 progress 60 % (6 MB)
141 19:08:06.842821 progress 65 % (7 MB)
142 19:08:06.922723 progress 70 % (7 MB)
143 19:08:07.001316 progress 75 % (8 MB)
144 19:08:07.084200 progress 80 % (8 MB)
145 19:08:07.163566 progress 85 % (9 MB)
146 19:08:07.246051 progress 90 % (10 MB)
147 19:08:07.319086 progress 95 % (10 MB)
148 19:08:07.395134 progress 100 % (11 MB)
149 19:08:07.407399 11 MB downloaded in 1.68 s (6.60 MB/s)
150 19:08:07.407974 end: 1.5.1 http-download (duration 00:00:02) [common]
152 19:08:07.409610 end: 1.5 download-retry (duration 00:00:02) [common]
153 19:08:07.410128 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 19:08:07.410643 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 19:08:23.721591 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/935717/extract-nfsrootfs-lte_gacv
156 19:08:23.722315 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 19:08:23.722670 start: 1.6.2 lava-overlay (timeout 00:09:10) [common]
158 19:08:23.723610 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a
159 19:08:23.724239 makedir: /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin
160 19:08:23.724679 makedir: /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/tests
161 19:08:23.725066 makedir: /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/results
162 19:08:23.725478 Creating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin/lava-add-keys
163 19:08:23.726139 Creating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin/lava-add-sources
164 19:08:23.726801 Creating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin/lava-background-process-start
165 19:08:23.727467 Creating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin/lava-background-process-stop
166 19:08:23.728202 Creating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin/lava-common-functions
167 19:08:23.728849 Creating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin/lava-echo-ipv4
168 19:08:23.729442 Creating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin/lava-install-packages
169 19:08:23.730060 Creating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin/lava-installed-packages
170 19:08:23.730653 Creating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin/lava-os-build
171 19:08:23.731360 Creating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin/lava-probe-channel
172 19:08:23.731969 Creating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin/lava-probe-ip
173 19:08:23.732700 Creating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin/lava-target-ip
174 19:08:23.733339 Creating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin/lava-target-mac
175 19:08:23.733935 Creating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin/lava-target-storage
176 19:08:23.734527 Creating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin/lava-test-case
177 19:08:23.735137 Creating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin/lava-test-event
178 19:08:23.735756 Creating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin/lava-test-feedback
179 19:08:23.736392 Creating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin/lava-test-raise
180 19:08:23.737043 Creating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin/lava-test-reference
181 19:08:23.737646 Creating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin/lava-test-runner
182 19:08:23.738277 Creating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin/lava-test-set
183 19:08:23.738891 Creating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin/lava-test-shell
184 19:08:23.739506 Updating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin/lava-install-packages (oe)
185 19:08:23.740231 Updating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/bin/lava-installed-packages (oe)
186 19:08:23.740804 Creating /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/environment
187 19:08:23.741259 LAVA metadata
188 19:08:23.741575 - LAVA_JOB_ID=935717
189 19:08:23.741884 - LAVA_DISPATCHER_IP=192.168.6.2
190 19:08:23.742359 start: 1.6.2.1 ssh-authorize (timeout 00:09:10) [common]
191 19:08:23.743567 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 19:08:23.743963 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:10) [common]
193 19:08:23.744258 skipped lava-vland-overlay
194 19:08:23.744559 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 19:08:23.744881 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:10) [common]
196 19:08:23.745152 skipped lava-multinode-overlay
197 19:08:23.745460 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 19:08:23.745767 start: 1.6.2.4 test-definition (timeout 00:09:10) [common]
199 19:08:23.746071 Loading test definitions
200 19:08:23.746450 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:10) [common]
201 19:08:23.746737 Using /lava-935717 at stage 0
202 19:08:23.748219 uuid=935717_1.6.2.4.1 testdef=None
203 19:08:23.748610 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 19:08:23.748939 start: 1.6.2.4.2 test-overlay (timeout 00:09:10) [common]
205 19:08:23.751145 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 19:08:23.752187 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:10) [common]
208 19:08:23.754898 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 19:08:23.755953 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:10) [common]
211 19:08:23.758567 runner path: /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 935717_1.6.2.4.1
212 19:08:23.759266 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 19:08:23.760309 Creating lava-test-runner.conf files
215 19:08:23.760593 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/935717/lava-overlay-65smev9a/lava-935717/0 for stage 0
216 19:08:23.761038 - 0_v4l2-decoder-conformance-vp9
217 19:08:23.761491 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 19:08:23.761850 start: 1.6.2.5 compress-overlay (timeout 00:09:10) [common]
219 19:08:23.788972 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 19:08:23.789475 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:10) [common]
221 19:08:23.789797 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 19:08:23.790130 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 19:08:23.790447 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:10) [common]
224 19:08:24.409558 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 19:08:24.410028 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 19:08:24.410297 extracting modules file /var/lib/lava/dispatcher/tmp/935717/tftp-deploy-_lt89r3h/modules/modules.tar to /var/lib/lava/dispatcher/tmp/935717/extract-nfsrootfs-lte_gacv
227 19:08:25.799492 extracting modules file /var/lib/lava/dispatcher/tmp/935717/tftp-deploy-_lt89r3h/modules/modules.tar to /var/lib/lava/dispatcher/tmp/935717/extract-overlay-ramdisk-gl4wlsm9/ramdisk
228 19:08:27.195751 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 19:08:27.196262 start: 1.6.5 apply-overlay-tftp (timeout 00:09:07) [common]
230 19:08:27.196544 [common] Applying overlay to NFS
231 19:08:27.196759 [common] Applying overlay /var/lib/lava/dispatcher/tmp/935717/compress-overlay-n3vvm_bw/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/935717/extract-nfsrootfs-lte_gacv
232 19:08:27.225767 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 19:08:27.226174 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 19:08:27.226451 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 19:08:27.226682 Converting downloaded kernel to a uImage
236 19:08:27.226989 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/935717/tftp-deploy-_lt89r3h/kernel/Image /var/lib/lava/dispatcher/tmp/935717/tftp-deploy-_lt89r3h/kernel/uImage
237 19:08:27.712909 output: Image Name:
238 19:08:27.713329 output: Created: Mon Nov 4 19:08:27 2024
239 19:08:27.713544 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 19:08:27.713750 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 19:08:27.713952 output: Load Address: 01080000
242 19:08:27.714152 output: Entry Point: 01080000
243 19:08:27.714350 output:
244 19:08:27.714685 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 19:08:27.714955 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 19:08:27.715226 start: 1.6.7 configure-preseed-file (timeout 00:09:06) [common]
247 19:08:27.715482 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 19:08:27.715742 start: 1.6.8 compress-ramdisk (timeout 00:09:06) [common]
249 19:08:27.716027 Building ramdisk /var/lib/lava/dispatcher/tmp/935717/extract-overlay-ramdisk-gl4wlsm9/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/935717/extract-overlay-ramdisk-gl4wlsm9/ramdisk
250 19:08:30.068972 >> 166823 blocks
251 19:08:38.171510 Adding RAMdisk u-boot header.
252 19:08:38.172411 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/935717/extract-overlay-ramdisk-gl4wlsm9/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/935717/extract-overlay-ramdisk-gl4wlsm9/ramdisk.cpio.gz.uboot
253 19:08:38.411382 output: Image Name:
254 19:08:38.411842 output: Created: Mon Nov 4 19:08:38 2024
255 19:08:38.412340 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 19:08:38.412765 output: Data Size: 23433893 Bytes = 22884.66 KiB = 22.35 MiB
257 19:08:38.413194 output: Load Address: 00000000
258 19:08:38.413601 output: Entry Point: 00000000
259 19:08:38.414001 output:
260 19:08:38.415118 rename /var/lib/lava/dispatcher/tmp/935717/extract-overlay-ramdisk-gl4wlsm9/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/935717/tftp-deploy-_lt89r3h/ramdisk/ramdisk.cpio.gz.uboot
261 19:08:38.415851 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
262 19:08:38.416451 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
263 19:08:38.416995 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:56) [common]
264 19:08:38.417461 No LXC device requested
265 19:08:38.417978 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 19:08:38.418505 start: 1.8 deploy-device-env (timeout 00:08:56) [common]
267 19:08:38.419014 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 19:08:38.419434 Checking files for TFTP limit of 4294967296 bytes.
269 19:08:38.422191 end: 1 tftp-deploy (duration 00:01:04) [common]
270 19:08:38.422782 start: 2 uboot-action (timeout 00:05:00) [common]
271 19:08:38.423323 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 19:08:38.423833 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 19:08:38.424423 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 19:08:38.424981 Using kernel file from prepare-kernel: 935717/tftp-deploy-_lt89r3h/kernel/uImage
275 19:08:38.425622 substitutions:
276 19:08:38.426037 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 19:08:38.426443 - {DTB_ADDR}: 0x01070000
278 19:08:38.426847 - {DTB}: 935717/tftp-deploy-_lt89r3h/dtb/meson-g12b-a311d-libretech-cc.dtb
279 19:08:38.427247 - {INITRD}: 935717/tftp-deploy-_lt89r3h/ramdisk/ramdisk.cpio.gz.uboot
280 19:08:38.427645 - {KERNEL_ADDR}: 0x01080000
281 19:08:38.428112 - {KERNEL}: 935717/tftp-deploy-_lt89r3h/kernel/uImage
282 19:08:38.428530 - {LAVA_MAC}: None
283 19:08:38.428971 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/935717/extract-nfsrootfs-lte_gacv
284 19:08:38.429374 - {NFS_SERVER_IP}: 192.168.6.2
285 19:08:38.429768 - {PRESEED_CONFIG}: None
286 19:08:38.430162 - {PRESEED_LOCAL}: None
287 19:08:38.430555 - {RAMDISK_ADDR}: 0x08000000
288 19:08:38.430942 - {RAMDISK}: 935717/tftp-deploy-_lt89r3h/ramdisk/ramdisk.cpio.gz.uboot
289 19:08:38.431333 - {ROOT_PART}: None
290 19:08:38.431721 - {ROOT}: None
291 19:08:38.432142 - {SERVER_IP}: 192.168.6.2
292 19:08:38.432538 - {TEE_ADDR}: 0x83000000
293 19:08:38.432928 - {TEE}: None
294 19:08:38.433319 Parsed boot commands:
295 19:08:38.433697 - setenv autoload no
296 19:08:38.434086 - setenv initrd_high 0xffffffff
297 19:08:38.434474 - setenv fdt_high 0xffffffff
298 19:08:38.434859 - dhcp
299 19:08:38.435245 - setenv serverip 192.168.6.2
300 19:08:38.435630 - tftpboot 0x01080000 935717/tftp-deploy-_lt89r3h/kernel/uImage
301 19:08:38.436049 - tftpboot 0x08000000 935717/tftp-deploy-_lt89r3h/ramdisk/ramdisk.cpio.gz.uboot
302 19:08:38.436447 - tftpboot 0x01070000 935717/tftp-deploy-_lt89r3h/dtb/meson-g12b-a311d-libretech-cc.dtb
303 19:08:38.436837 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/935717/extract-nfsrootfs-lte_gacv,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 19:08:38.437241 - bootm 0x01080000 0x08000000 0x01070000
305 19:08:38.437757 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 19:08:38.439260 start: 2.3 connect-device (timeout 00:05:00) [common]
308 19:08:38.439687 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 19:08:38.456086 Setting prompt string to ['lava-test: # ']
310 19:08:38.457581 end: 2.3 connect-device (duration 00:00:00) [common]
311 19:08:38.458189 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 19:08:38.458758 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 19:08:38.459536 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 19:08:38.460794 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 19:08:38.498690 >> OK - accepted request
316 19:08:38.500697 Returned 0 in 0 seconds
317 19:08:38.601835 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 19:08:38.603520 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 19:08:38.604159 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 19:08:38.604700 Setting prompt string to ['Hit any key to stop autoboot']
322 19:08:38.605184 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 19:08:38.606787 Trying 192.168.56.21...
324 19:08:38.607274 Connected to conserv1.
325 19:08:38.607721 Escape character is '^]'.
326 19:08:38.608181
327 19:08:38.608612 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 19:08:38.609046
329 19:08:49.753247 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 19:08:49.753879 bl2_stage_init 0x01
331 19:08:49.754330 bl2_stage_init 0x81
332 19:08:49.758360 hw id: 0x0000 - pwm id 0x01
333 19:08:49.758883 bl2_stage_init 0xc1
334 19:08:49.759285 bl2_stage_init 0x02
335 19:08:49.759678
336 19:08:49.763889 L0:00000000
337 19:08:49.764373 L1:20000703
338 19:08:49.764768 L2:00008067
339 19:08:49.765156 L3:14000000
340 19:08:49.769554 B2:00402000
341 19:08:49.769999 B1:e0f83180
342 19:08:49.770390
343 19:08:49.770787 TE: 58124
344 19:08:49.771180
345 19:08:49.775500 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 19:08:49.775943
347 19:08:49.776382 Board ID = 1
348 19:08:49.780746 Set A53 clk to 24M
349 19:08:49.781180 Set A73 clk to 24M
350 19:08:49.781571 Set clk81 to 24M
351 19:08:49.786436 A53 clk: 1200 MHz
352 19:08:49.786873 A73 clk: 1200 MHz
353 19:08:49.787261 CLK81: 166.6M
354 19:08:49.787644 smccc: 00012a92
355 19:08:49.791890 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 19:08:49.797496 board id: 1
357 19:08:49.803554 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 19:08:49.813880 fw parse done
359 19:08:49.819841 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 19:08:49.862509 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 19:08:49.873387 PIEI prepare done
362 19:08:49.873830 fastboot data load
363 19:08:49.874228 fastboot data verify
364 19:08:49.879198 verify result: 266
365 19:08:49.884679 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 19:08:49.885153 LPDDR4 probe
367 19:08:49.885567 ddr clk to 1584MHz
368 19:08:49.892512 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 19:08:49.929946
370 19:08:49.930454 dmc_version 0001
371 19:08:49.936522 Check phy result
372 19:08:49.942478 INFO : End of CA training
373 19:08:49.942945 INFO : End of initialization
374 19:08:49.948121 INFO : Training has run successfully!
375 19:08:49.948588 Check phy result
376 19:08:49.953678 INFO : End of initialization
377 19:08:49.954141 INFO : End of read enable training
378 19:08:49.959293 INFO : End of fine write leveling
379 19:08:49.964870 INFO : End of Write leveling coarse delay
380 19:08:49.965336 INFO : Training has run successfully!
381 19:08:49.965748 Check phy result
382 19:08:49.970468 INFO : End of initialization
383 19:08:49.970929 INFO : End of read dq deskew training
384 19:08:49.976102 INFO : End of MPR read delay center optimization
385 19:08:49.981697 INFO : End of write delay center optimization
386 19:08:49.987290 INFO : End of read delay center optimization
387 19:08:49.987764 INFO : End of max read latency training
388 19:08:49.992884 INFO : Training has run successfully!
389 19:08:49.993347 1D training succeed
390 19:08:50.001756 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 19:08:50.049726 Check phy result
392 19:08:50.050276 INFO : End of initialization
393 19:08:50.071374 INFO : End of 2D read delay Voltage center optimization
394 19:08:50.091615 INFO : End of 2D read delay Voltage center optimization
395 19:08:50.143735 INFO : End of 2D write delay Voltage center optimization
396 19:08:50.193013 INFO : End of 2D write delay Voltage center optimization
397 19:08:50.198609 INFO : Training has run successfully!
398 19:08:50.199077
399 19:08:50.199494 channel==0
400 19:08:50.204248 RxClkDly_Margin_A0==88 ps 9
401 19:08:50.204711 TxDqDly_Margin_A0==98 ps 10
402 19:08:50.209788 RxClkDly_Margin_A1==88 ps 9
403 19:08:50.210262 TxDqDly_Margin_A1==88 ps 9
404 19:08:50.210674 TrainedVREFDQ_A0==74
405 19:08:50.215384 TrainedVREFDQ_A1==74
406 19:08:50.215848 VrefDac_Margin_A0==25
407 19:08:50.216303 DeviceVref_Margin_A0==40
408 19:08:50.220992 VrefDac_Margin_A1==25
409 19:08:50.221481 DeviceVref_Margin_A1==40
410 19:08:50.221906
411 19:08:50.222320
412 19:08:50.222724 channel==1
413 19:08:50.226614 RxClkDly_Margin_A0==98 ps 10
414 19:08:50.227084 TxDqDly_Margin_A0==88 ps 9
415 19:08:50.232286 RxClkDly_Margin_A1==98 ps 10
416 19:08:50.232795 TxDqDly_Margin_A1==88 ps 9
417 19:08:50.237866 TrainedVREFDQ_A0==77
418 19:08:50.238406 TrainedVREFDQ_A1==77
419 19:08:50.238822 VrefDac_Margin_A0==22
420 19:08:50.243387 DeviceVref_Margin_A0==37
421 19:08:50.243882 VrefDac_Margin_A1==22
422 19:08:50.249041 DeviceVref_Margin_A1==37
423 19:08:50.249530
424 19:08:50.249946 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 19:08:50.250349
426 19:08:50.282576 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
427 19:08:50.283247 2D training succeed
428 19:08:50.288336 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 19:08:50.293807 auto size-- 65535DDR cs0 size: 2048MB
430 19:08:50.294311 DDR cs1 size: 2048MB
431 19:08:50.299421 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 19:08:50.299904 cs0 DataBus test pass
433 19:08:50.304991 cs1 DataBus test pass
434 19:08:50.305509 cs0 AddrBus test pass
435 19:08:50.305930 cs1 AddrBus test pass
436 19:08:50.306333
437 19:08:50.310638 100bdlr_step_size ps== 420
438 19:08:50.311137 result report
439 19:08:50.316322 boot times 0Enable ddr reg access
440 19:08:50.321486 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 19:08:50.335001 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 19:08:50.908532 0.0;M3 CHK:0;cm4_sp_mode 0
443 19:08:50.908928 MVN_1=0x00000000
444 19:08:50.914011 MVN_2=0x00000000
445 19:08:50.919759 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 19:08:50.920051 OPS=0x10
447 19:08:50.920279 ring efuse init
448 19:08:50.920492 chipver efuse init
449 19:08:50.925323 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 19:08:50.930910 [0.018961 Inits done]
451 19:08:50.931151 secure task start!
452 19:08:50.931360 high task start!
453 19:08:50.934567 low task start!
454 19:08:50.934809 run into bl31
455 19:08:50.942295 NOTICE: BL31: v1.3(release):4fc40b1
456 19:08:50.949345 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 19:08:50.949813 NOTICE: BL31: G12A normal boot!
458 19:08:50.975448 NOTICE: BL31: BL33 decompress pass
459 19:08:50.981126 ERROR: Error initializing runtime service opteed_fast
460 19:08:52.214009
461 19:08:52.214428
462 19:08:52.222570 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 19:08:52.223024
464 19:08:52.223414 Model: Libre Computer AML-A311D-CC Alta
465 19:08:52.430994 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 19:08:52.454377 DRAM: 2 GiB (effective 3.8 GiB)
467 19:08:52.597342 Core: 408 devices, 31 uclasses, devicetree: separate
468 19:08:52.603140 WDT: Not starting watchdog@f0d0
469 19:08:52.635396 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 19:08:52.647834 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 19:08:52.652773 ** Bad device specification mmc 0 **
472 19:08:52.663234 Card did not respond to voltage select! : -110
473 19:08:52.670900 ** Bad device specification mmc 0 **
474 19:08:52.671469 Couldn't find partition mmc 0
475 19:08:52.679245 Card did not respond to voltage select! : -110
476 19:08:52.684733 ** Bad device specification mmc 0 **
477 19:08:52.685261 Couldn't find partition mmc 0
478 19:08:52.689795 Error: could not access storage.
479 19:08:53.953171 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 19:08:53.953616 bl2_stage_init 0x01
481 19:08:53.953863 bl2_stage_init 0x81
482 19:08:53.958656 hw id: 0x0000 - pwm id 0x01
483 19:08:53.958994 bl2_stage_init 0xc1
484 19:08:53.959222 bl2_stage_init 0x02
485 19:08:53.959432
486 19:08:53.964482 L0:00000000
487 19:08:53.964950 L1:20000703
488 19:08:53.965291 L2:00008067
489 19:08:53.965616 L3:14000000
490 19:08:53.969850 B2:00402000
491 19:08:53.970268 B1:e0f83180
492 19:08:53.970600
493 19:08:53.970929 TE: 58159
494 19:08:53.971175
495 19:08:53.975444 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 19:08:53.975782
497 19:08:53.976031 Board ID = 1
498 19:08:53.981065 Set A53 clk to 24M
499 19:08:53.981365 Set A73 clk to 24M
500 19:08:53.981588 Set clk81 to 24M
501 19:08:53.986676 A53 clk: 1200 MHz
502 19:08:53.987109 A73 clk: 1200 MHz
503 19:08:53.987469 CLK81: 166.6M
504 19:08:53.987819 smccc: 00012ab5
505 19:08:53.992299 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 19:08:53.997932 board id: 1
507 19:08:54.003738 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 19:08:54.014435 fw parse done
509 19:08:54.020392 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 19:08:54.063048 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 19:08:54.073945 PIEI prepare done
512 19:08:54.074520 fastboot data load
513 19:08:54.075032 fastboot data verify
514 19:08:54.079616 verify result: 266
515 19:08:54.085171 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 19:08:54.085699 LPDDR4 probe
517 19:08:54.086167 ddr clk to 1584MHz
518 19:08:54.093157 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 19:08:54.130406
520 19:08:54.130963 dmc_version 0001
521 19:08:54.137077 Check phy result
522 19:08:54.143043 INFO : End of CA training
523 19:08:54.143609 INFO : End of initialization
524 19:08:54.148586 INFO : Training has run successfully!
525 19:08:54.149100 Check phy result
526 19:08:54.154166 INFO : End of initialization
527 19:08:54.154689 INFO : End of read enable training
528 19:08:54.159769 INFO : End of fine write leveling
529 19:08:54.165356 INFO : End of Write leveling coarse delay
530 19:08:54.165879 INFO : Training has run successfully!
531 19:08:54.166341 Check phy result
532 19:08:54.171000 INFO : End of initialization
533 19:08:54.171510 INFO : End of read dq deskew training
534 19:08:54.176558 INFO : End of MPR read delay center optimization
535 19:08:54.182136 INFO : End of write delay center optimization
536 19:08:54.187770 INFO : End of read delay center optimization
537 19:08:54.188314 INFO : End of max read latency training
538 19:08:54.193343 INFO : Training has run successfully!
539 19:08:54.193842 1D training succeed
540 19:08:54.202535 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 19:08:54.250107 Check phy result
542 19:08:54.250651 INFO : End of initialization
543 19:08:54.270931 INFO : End of 2D read delay Voltage center optimization
544 19:08:54.292095 INFO : End of 2D read delay Voltage center optimization
545 19:08:54.343884 INFO : End of 2D write delay Voltage center optimization
546 19:08:54.393104 INFO : End of 2D write delay Voltage center optimization
547 19:08:54.398651 INFO : Training has run successfully!
548 19:08:54.399175
549 19:08:54.399625 channel==0
550 19:08:54.404295 RxClkDly_Margin_A0==88 ps 9
551 19:08:54.404825 TxDqDly_Margin_A0==98 ps 10
552 19:08:54.409871 RxClkDly_Margin_A1==88 ps 9
553 19:08:54.410392 TxDqDly_Margin_A1==98 ps 10
554 19:08:54.410828 TrainedVREFDQ_A0==74
555 19:08:54.415469 TrainedVREFDQ_A1==74
556 19:08:54.416022 VrefDac_Margin_A0==25
557 19:08:54.416452 DeviceVref_Margin_A0==40
558 19:08:54.421052 VrefDac_Margin_A1==25
559 19:08:54.421563 DeviceVref_Margin_A1==40
560 19:08:54.421979
561 19:08:54.422391
562 19:08:54.426655 channel==1
563 19:08:54.427164 RxClkDly_Margin_A0==98 ps 10
564 19:08:54.427583 TxDqDly_Margin_A0==98 ps 10
565 19:08:54.432277 RxClkDly_Margin_A1==98 ps 10
566 19:08:54.432788 TxDqDly_Margin_A1==88 ps 9
567 19:08:54.437798 TrainedVREFDQ_A0==77
568 19:08:54.438341 TrainedVREFDQ_A1==77
569 19:08:54.438770 VrefDac_Margin_A0==22
570 19:08:54.443482 DeviceVref_Margin_A0==37
571 19:08:54.444027 VrefDac_Margin_A1==24
572 19:08:54.448938 DeviceVref_Margin_A1==37
573 19:08:54.449249
574 19:08:54.449480 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 19:08:54.454664
576 19:08:54.482576 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000018 dram_vref_reg_value 0x 00000060
577 19:08:54.483148 2D training succeed
578 19:08:54.488282 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 19:08:54.493833 auto size-- 65535DDR cs0 size: 2048MB
580 19:08:54.494371 DDR cs1 size: 2048MB
581 19:08:54.499445 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 19:08:54.499960 cs0 DataBus test pass
583 19:08:54.505096 cs1 DataBus test pass
584 19:08:54.505819 cs0 AddrBus test pass
585 19:08:54.506285 cs1 AddrBus test pass
586 19:08:54.506601
587 19:08:54.510606 100bdlr_step_size ps== 420
588 19:08:54.510943 result report
589 19:08:54.516295 boot times 0Enable ddr reg access
590 19:08:54.521152 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 19:08:54.534987 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 19:08:55.107297 0.0;M3 CHK:0;cm4_sp_mode 0
593 19:08:55.107740 MVN_1=0x00000000
594 19:08:55.112787 MVN_2=0x00000000
595 19:08:55.118431 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 19:08:55.118781 OPS=0x10
597 19:08:55.119058 ring efuse init
598 19:08:55.119323 chipver efuse init
599 19:08:55.126696 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 19:08:55.127068 [0.018961 Inits done]
601 19:08:55.127319 secure task start!
602 19:08:55.134322 high task start!
603 19:08:55.134730 low task start!
604 19:08:55.135002 run into bl31
605 19:08:55.141142 NOTICE: BL31: v1.3(release):4fc40b1
606 19:08:55.148811 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 19:08:55.149203 NOTICE: BL31: G12A normal boot!
608 19:08:55.174059 NOTICE: BL31: BL33 decompress pass
609 19:08:55.179828 ERROR: Error initializing runtime service opteed_fast
610 19:08:56.412804
611 19:08:56.413609
612 19:08:56.421229 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 19:08:56.421873
614 19:08:56.422436 Model: Libre Computer AML-A311D-CC Alta
615 19:08:56.629528 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 19:08:56.652912 DRAM: 2 GiB (effective 3.8 GiB)
617 19:08:56.795820 Core: 408 devices, 31 uclasses, devicetree: separate
618 19:08:56.801774 WDT: Not starting watchdog@f0d0
619 19:08:56.833988 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 19:08:56.846471 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 19:08:56.851435 ** Bad device specification mmc 0 **
622 19:08:56.861784 Card did not respond to voltage select! : -110
623 19:08:56.869368 ** Bad device specification mmc 0 **
624 19:08:56.869995 Couldn't find partition mmc 0
625 19:08:56.877745 Card did not respond to voltage select! : -110
626 19:08:56.883366 ** Bad device specification mmc 0 **
627 19:08:56.883973 Couldn't find partition mmc 0
628 19:08:56.888427 Error: could not access storage.
629 19:08:57.230761 Net: eth0: ethernet@ff3f0000
630 19:08:57.231523 starting USB...
631 19:08:57.482613 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 19:08:57.483355 Starting the controller
633 19:08:57.489724 USB XHCI 1.10
634 19:08:59.204283 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 19:08:59.205075 bl2_stage_init 0x01
636 19:08:59.205634 bl2_stage_init 0x81
637 19:08:59.210081 hw id: 0x0000 - pwm id 0x01
638 19:08:59.210701 bl2_stage_init 0xc1
639 19:08:59.211247 bl2_stage_init 0x02
640 19:08:59.211773
641 19:08:59.215663 L0:00000000
642 19:08:59.216302 L1:20000703
643 19:08:59.216841 L2:00008067
644 19:08:59.217362 L3:14000000
645 19:08:59.221153 B2:00402000
646 19:08:59.221748 B1:e0f83180
647 19:08:59.222281
648 19:08:59.222805 TE: 58124
649 19:08:59.223335
650 19:08:59.226751 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 19:08:59.227362
652 19:08:59.227905 Board ID = 1
653 19:08:59.232368 Set A53 clk to 24M
654 19:08:59.232848 Set A73 clk to 24M
655 19:08:59.233270 Set clk81 to 24M
656 19:08:59.237920 A53 clk: 1200 MHz
657 19:08:59.238533 A73 clk: 1200 MHz
658 19:08:59.239075 CLK81: 166.6M
659 19:08:59.239593 smccc: 00012a92
660 19:08:59.243663 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 19:08:59.249245 board id: 1
662 19:08:59.255155 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 19:08:59.265536 fw parse done
664 19:08:59.271497 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 19:08:59.314075 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 19:08:59.325031 PIEI prepare done
667 19:08:59.325632 fastboot data load
668 19:08:59.326175 fastboot data verify
669 19:08:59.330635 verify result: 266
670 19:08:59.336259 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 19:08:59.336741 LPDDR4 probe
672 19:08:59.337165 ddr clk to 1584MHz
673 19:08:59.344162 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 19:08:59.381432
675 19:08:59.382084 dmc_version 0001
676 19:08:59.388185 Check phy result
677 19:08:59.394034 INFO : End of CA training
678 19:08:59.394638 INFO : End of initialization
679 19:08:59.399644 INFO : Training has run successfully!
680 19:08:59.400310 Check phy result
681 19:08:59.405238 INFO : End of initialization
682 19:08:59.405847 INFO : End of read enable training
683 19:08:59.408575 INFO : End of fine write leveling
684 19:08:59.414125 INFO : End of Write leveling coarse delay
685 19:08:59.419717 INFO : Training has run successfully!
686 19:08:59.420353 Check phy result
687 19:08:59.420887 INFO : End of initialization
688 19:08:59.425357 INFO : End of read dq deskew training
689 19:08:59.430950 INFO : End of MPR read delay center optimization
690 19:08:59.431554 INFO : End of write delay center optimization
691 19:08:59.436572 INFO : End of read delay center optimization
692 19:08:59.442154 INFO : End of max read latency training
693 19:08:59.442763 INFO : Training has run successfully!
694 19:08:59.447766 1D training succeed
695 19:08:59.453641 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 19:08:59.501130 Check phy result
697 19:08:59.501757 INFO : End of initialization
698 19:08:59.522875 INFO : End of 2D read delay Voltage center optimization
699 19:08:59.542262 INFO : End of 2D read delay Voltage center optimization
700 19:08:59.594286 INFO : End of 2D write delay Voltage center optimization
701 19:08:59.643710 INFO : End of 2D write delay Voltage center optimization
702 19:08:59.649341 INFO : Training has run successfully!
703 19:08:59.649954
704 19:08:59.650502 channel==0
705 19:08:59.654916 RxClkDly_Margin_A0==88 ps 9
706 19:08:59.655517 TxDqDly_Margin_A0==98 ps 10
707 19:08:59.660469 RxClkDly_Margin_A1==88 ps 9
708 19:08:59.661079 TxDqDly_Margin_A1==98 ps 10
709 19:08:59.661626 TrainedVREFDQ_A0==74
710 19:08:59.666174 TrainedVREFDQ_A1==76
711 19:08:59.666799 VrefDac_Margin_A0==25
712 19:08:59.667354 DeviceVref_Margin_A0==40
713 19:08:59.671697 VrefDac_Margin_A1==25
714 19:08:59.672326 DeviceVref_Margin_A1==38
715 19:08:59.672866
716 19:08:59.673398
717 19:08:59.677279 channel==1
718 19:08:59.677894 RxClkDly_Margin_A0==98 ps 10
719 19:08:59.678433 TxDqDly_Margin_A0==98 ps 10
720 19:08:59.682916 RxClkDly_Margin_A1==88 ps 9
721 19:08:59.683517 TxDqDly_Margin_A1==98 ps 10
722 19:08:59.688478 TrainedVREFDQ_A0==77
723 19:08:59.689083 TrainedVREFDQ_A1==77
724 19:08:59.689623 VrefDac_Margin_A0==23
725 19:08:59.694151 DeviceVref_Margin_A0==37
726 19:08:59.694745 VrefDac_Margin_A1==23
727 19:08:59.699726 DeviceVref_Margin_A1==37
728 19:08:59.700354
729 19:08:59.700881 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 19:08:59.705310
731 19:08:59.733260 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000018 dram_vref_reg_value 0x 00000060
732 19:08:59.733925 2D training succeed
733 19:08:59.738934 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 19:08:59.744522 auto size-- 65535DDR cs0 size: 2048MB
735 19:08:59.745129 DDR cs1 size: 2048MB
736 19:08:59.750108 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 19:08:59.750695 cs0 DataBus test pass
738 19:08:59.755713 cs1 DataBus test pass
739 19:08:59.756347 cs0 AddrBus test pass
740 19:08:59.756872 cs1 AddrBus test pass
741 19:08:59.757399
742 19:08:59.761316 100bdlr_step_size ps== 420
743 19:08:59.761929 result report
744 19:08:59.766915 boot times 0Enable ddr reg access
745 19:08:59.772364 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 19:08:59.785809 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 19:09:00.359512 0.0;M3 CHK:0;cm4_sp_mode 0
748 19:09:00.360308 MVN_1=0x00000000
749 19:09:00.365040 MVN_2=0x00000000
750 19:09:00.370739 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 19:09:00.371396 OPS=0x10
752 19:09:00.371923 ring efuse init
753 19:09:00.372487 chipver efuse init
754 19:09:00.376373 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 19:09:00.381931 [0.018961 Inits done]
756 19:09:00.382524 secure task start!
757 19:09:00.383035 high task start!
758 19:09:00.386530 low task start!
759 19:09:00.387124 run into bl31
760 19:09:00.393183 NOTICE: BL31: v1.3(release):4fc40b1
761 19:09:00.401001 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 19:09:00.401598 NOTICE: BL31: G12A normal boot!
763 19:09:00.426327 NOTICE: BL31: BL33 decompress pass
764 19:09:00.432049 ERROR: Error initializing runtime service opteed_fast
765 19:09:01.664611
766 19:09:01.665011
767 19:09:01.673024 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 19:09:01.673440
769 19:09:01.673780 Model: Libre Computer AML-A311D-CC Alta
770 19:09:01.881401 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 19:09:01.904806 DRAM: 2 GiB (effective 3.8 GiB)
772 19:09:02.047789 Core: 408 devices, 31 uclasses, devicetree: separate
773 19:09:02.053679 WDT: Not starting watchdog@f0d0
774 19:09:02.085929 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 19:09:02.098323 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 19:09:02.103326 ** Bad device specification mmc 0 **
777 19:09:02.113704 Card did not respond to voltage select! : -110
778 19:09:02.121309 ** Bad device specification mmc 0 **
779 19:09:02.121582 Couldn't find partition mmc 0
780 19:09:02.129689 Card did not respond to voltage select! : -110
781 19:09:02.135195 ** Bad device specification mmc 0 **
782 19:09:02.135581 Couldn't find partition mmc 0
783 19:09:02.140235 Error: could not access storage.
784 19:09:02.483734 Net: eth0: ethernet@ff3f0000
785 19:09:02.484300 starting USB...
786 19:09:02.735567 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 19:09:02.736184 Starting the controller
788 19:09:02.742486 USB XHCI 1.10
789 19:09:04.903517 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 19:09:04.904221 bl2_stage_init 0x01
791 19:09:04.904714 bl2_stage_init 0x81
792 19:09:04.909099 hw id: 0x0000 - pwm id 0x01
793 19:09:04.909605 bl2_stage_init 0xc1
794 19:09:04.910067 bl2_stage_init 0x02
795 19:09:04.910516
796 19:09:04.914704 L0:00000000
797 19:09:04.915198 L1:20000703
798 19:09:04.915656 L2:00008067
799 19:09:04.916151 L3:14000000
800 19:09:04.917634 B2:00402000
801 19:09:04.918122 B1:e0f83180
802 19:09:04.918576
803 19:09:04.919023 TE: 58167
804 19:09:04.919471
805 19:09:04.928704 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 19:09:04.929211
807 19:09:04.929669 Board ID = 1
808 19:09:04.930119 Set A53 clk to 24M
809 19:09:04.930564 Set A73 clk to 24M
810 19:09:04.934473 Set clk81 to 24M
811 19:09:04.934960 A53 clk: 1200 MHz
812 19:09:04.935416 A73 clk: 1200 MHz
813 19:09:04.939973 CLK81: 166.6M
814 19:09:04.940496 smccc: 00012abd
815 19:09:04.945568 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 19:09:04.946063 board id: 1
817 19:09:04.954353 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 19:09:04.964689 fw parse done
819 19:09:04.970640 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 19:09:05.013383 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 19:09:05.024292 PIEI prepare done
822 19:09:05.024783 fastboot data load
823 19:09:05.025242 fastboot data verify
824 19:09:05.029841 verify result: 266
825 19:09:05.035454 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 19:09:05.035944 LPDDR4 probe
827 19:09:05.036449 ddr clk to 1584MHz
828 19:09:05.043417 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 19:09:05.080660
830 19:09:05.081172 dmc_version 0001
831 19:09:05.087354 Check phy result
832 19:09:05.093203 INFO : End of CA training
833 19:09:05.093696 INFO : End of initialization
834 19:09:05.098822 INFO : Training has run successfully!
835 19:09:05.099305 Check phy result
836 19:09:05.104417 INFO : End of initialization
837 19:09:05.104906 INFO : End of read enable training
838 19:09:05.110047 INFO : End of fine write leveling
839 19:09:05.115619 INFO : End of Write leveling coarse delay
840 19:09:05.116135 INFO : Training has run successfully!
841 19:09:05.116597 Check phy result
842 19:09:05.121206 INFO : End of initialization
843 19:09:05.121689 INFO : End of read dq deskew training
844 19:09:05.126814 INFO : End of MPR read delay center optimization
845 19:09:05.132400 INFO : End of write delay center optimization
846 19:09:05.138013 INFO : End of read delay center optimization
847 19:09:05.138503 INFO : End of max read latency training
848 19:09:05.143609 INFO : Training has run successfully!
849 19:09:05.144138 1D training succeed
850 19:09:05.152825 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 19:09:05.200432 Check phy result
852 19:09:05.200963 INFO : End of initialization
853 19:09:05.222032 INFO : End of 2D read delay Voltage center optimization
854 19:09:05.242133 INFO : End of 2D read delay Voltage center optimization
855 19:09:05.294170 INFO : End of 2D write delay Voltage center optimization
856 19:09:05.343374 INFO : End of 2D write delay Voltage center optimization
857 19:09:05.348853 INFO : Training has run successfully!
858 19:09:05.349351
859 19:09:05.349808 channel==0
860 19:09:05.354439 RxClkDly_Margin_A0==88 ps 9
861 19:09:05.354926 TxDqDly_Margin_A0==98 ps 10
862 19:09:05.360080 RxClkDly_Margin_A1==88 ps 9
863 19:09:05.360577 TxDqDly_Margin_A1==98 ps 10
864 19:09:05.361055 TrainedVREFDQ_A0==74
865 19:09:05.365655 TrainedVREFDQ_A1==74
866 19:09:05.366205 VrefDac_Margin_A0==25
867 19:09:05.366671 DeviceVref_Margin_A0==40
868 19:09:05.371398 VrefDac_Margin_A1==25
869 19:09:05.371935 DeviceVref_Margin_A1==40
870 19:09:05.372409
871 19:09:05.372842
872 19:09:05.376869 channel==1
873 19:09:05.377346 RxClkDly_Margin_A0==98 ps 10
874 19:09:05.377778 TxDqDly_Margin_A0==88 ps 9
875 19:09:05.382589 RxClkDly_Margin_A1==98 ps 10
876 19:09:05.383063 TxDqDly_Margin_A1==88 ps 9
877 19:09:05.388072 TrainedVREFDQ_A0==75
878 19:09:05.388544 TrainedVREFDQ_A1==77
879 19:09:05.388979 VrefDac_Margin_A0==22
880 19:09:05.393648 DeviceVref_Margin_A0==39
881 19:09:05.394116 VrefDac_Margin_A1==24
882 19:09:05.399261 DeviceVref_Margin_A1==37
883 19:09:05.399727
884 19:09:05.400197 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 19:09:05.400627
886 19:09:05.432842 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
887 19:09:05.433339 2D training succeed
888 19:09:05.438424 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 19:09:05.444135 auto size-- 65535DDR cs0 size: 2048MB
890 19:09:05.444608 DDR cs1 size: 2048MB
891 19:09:05.449632 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 19:09:05.450096 cs0 DataBus test pass
893 19:09:05.455263 cs1 DataBus test pass
894 19:09:05.455730 cs0 AddrBus test pass
895 19:09:05.456193 cs1 AddrBus test pass
896 19:09:05.456621
897 19:09:05.460814 100bdlr_step_size ps== 420
898 19:09:05.461294 result report
899 19:09:05.466432 boot times 0Enable ddr reg access
900 19:09:05.471772 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 19:09:05.485216 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 19:09:06.057318 0.0;M3 CHK:0;cm4_sp_mode 0
903 19:09:06.057952 MVN_1=0x00000000
904 19:09:06.062756 MVN_2=0x00000000
905 19:09:06.068495 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 19:09:06.068997 OPS=0x10
907 19:09:06.069457 ring efuse init
908 19:09:06.069902 chipver efuse init
909 19:09:06.074092 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 19:09:06.079690 [0.018961 Inits done]
911 19:09:06.080237 secure task start!
912 19:09:06.080693 high task start!
913 19:09:06.084272 low task start!
914 19:09:06.084781 run into bl31
915 19:09:06.090928 NOTICE: BL31: v1.3(release):4fc40b1
916 19:09:06.098734 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 19:09:06.099251 NOTICE: BL31: G12A normal boot!
918 19:09:06.124144 NOTICE: BL31: BL33 decompress pass
919 19:09:06.129807 ERROR: Error initializing runtime service opteed_fast
920 19:09:07.362717
921 19:09:07.363339
922 19:09:07.371074 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 19:09:07.371580
924 19:09:07.372080 Model: Libre Computer AML-A311D-CC Alta
925 19:09:07.579568 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 19:09:07.602883 DRAM: 2 GiB (effective 3.8 GiB)
927 19:09:07.745889 Core: 408 devices, 31 uclasses, devicetree: separate
928 19:09:07.751731 WDT: Not starting watchdog@f0d0
929 19:09:07.783977 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 19:09:07.796514 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 19:09:07.801437 ** Bad device specification mmc 0 **
932 19:09:07.811767 Card did not respond to voltage select! : -110
933 19:09:07.819409 ** Bad device specification mmc 0 **
934 19:09:07.819892 Couldn't find partition mmc 0
935 19:09:07.827754 Card did not respond to voltage select! : -110
936 19:09:07.833263 ** Bad device specification mmc 0 **
937 19:09:07.833749 Couldn't find partition mmc 0
938 19:09:07.838342 Error: could not access storage.
939 19:09:08.180828 Net: eth0: ethernet@ff3f0000
940 19:09:08.181373 starting USB...
941 19:09:08.432535 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 19:09:08.433078 Starting the controller
943 19:09:08.439533 USB XHCI 1.10
944 19:09:10.303221 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 19:09:10.303840 bl2_stage_init 0x01
946 19:09:10.304316 bl2_stage_init 0x81
947 19:09:10.308757 hw id: 0x0000 - pwm id 0x01
948 19:09:10.309240 bl2_stage_init 0xc1
949 19:09:10.309654 bl2_stage_init 0x02
950 19:09:10.310058
951 19:09:10.314384 L0:00000000
952 19:09:10.314857 L1:20000703
953 19:09:10.315274 L2:00008067
954 19:09:10.315673 L3:14000000
955 19:09:10.317328 B2:00402000
956 19:09:10.317792 B1:e0f83180
957 19:09:10.318202
958 19:09:10.318609 TE: 58167
959 19:09:10.319015
960 19:09:10.328421 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 19:09:10.328898
962 19:09:10.329314 Board ID = 1
963 19:09:10.329717 Set A53 clk to 24M
964 19:09:10.330115 Set A73 clk to 24M
965 19:09:10.334050 Set clk81 to 24M
966 19:09:10.334514 A53 clk: 1200 MHz
967 19:09:10.334922 A73 clk: 1200 MHz
968 19:09:10.337595 CLK81: 166.6M
969 19:09:10.338056 smccc: 00012abd
970 19:09:10.343268 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 19:09:10.348772 board id: 1
972 19:09:10.354053 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 19:09:10.364356 fw parse done
974 19:09:10.370367 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 19:09:10.412983 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 19:09:10.423914 PIEI prepare done
977 19:09:10.424417 fastboot data load
978 19:09:10.424816 fastboot data verify
979 19:09:10.429506 verify result: 266
980 19:09:10.435120 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 19:09:10.435575 LPDDR4 probe
982 19:09:10.435968 ddr clk to 1584MHz
983 19:09:10.443109 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 19:09:10.480335
985 19:09:10.480796 dmc_version 0001
986 19:09:10.487077 Check phy result
987 19:09:10.492925 INFO : End of CA training
988 19:09:10.493384 INFO : End of initialization
989 19:09:10.498502 INFO : Training has run successfully!
990 19:09:10.498954 Check phy result
991 19:09:10.504227 INFO : End of initialization
992 19:09:10.504717 INFO : End of read enable training
993 19:09:10.509733 INFO : End of fine write leveling
994 19:09:10.515311 INFO : End of Write leveling coarse delay
995 19:09:10.515783 INFO : Training has run successfully!
996 19:09:10.516221 Check phy result
997 19:09:10.520932 INFO : End of initialization
998 19:09:10.521396 INFO : End of read dq deskew training
999 19:09:10.526515 INFO : End of MPR read delay center optimization
1000 19:09:10.532145 INFO : End of write delay center optimization
1001 19:09:10.537700 INFO : End of read delay center optimization
1002 19:09:10.538165 INFO : End of max read latency training
1003 19:09:10.543305 INFO : Training has run successfully!
1004 19:09:10.543770 1D training succeed
1005 19:09:10.552453 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 19:09:10.600157 Check phy result
1007 19:09:10.600628 INFO : End of initialization
1008 19:09:10.621664 INFO : End of 2D read delay Voltage center optimization
1009 19:09:10.641750 INFO : End of 2D read delay Voltage center optimization
1010 19:09:10.693702 INFO : End of 2D write delay Voltage center optimization
1011 19:09:10.742947 INFO : End of 2D write delay Voltage center optimization
1012 19:09:10.748496 INFO : Training has run successfully!
1013 19:09:10.748962
1014 19:09:10.749388 channel==0
1015 19:09:10.754142 RxClkDly_Margin_A0==88 ps 9
1016 19:09:10.754610 TxDqDly_Margin_A0==108 ps 11
1017 19:09:10.759693 RxClkDly_Margin_A1==88 ps 9
1018 19:09:10.760202 TxDqDly_Margin_A1==98 ps 10
1019 19:09:10.760622 TrainedVREFDQ_A0==74
1020 19:09:10.765299 TrainedVREFDQ_A1==75
1021 19:09:10.765776 VrefDac_Margin_A0==25
1022 19:09:10.770894 DeviceVref_Margin_A0==40
1023 19:09:10.771360 VrefDac_Margin_A1==25
1024 19:09:10.771770 DeviceVref_Margin_A1==39
1025 19:09:10.772212
1026 19:09:10.772617
1027 19:09:10.776494 channel==1
1028 19:09:10.776952 RxClkDly_Margin_A0==98 ps 10
1029 19:09:10.777364 TxDqDly_Margin_A0==88 ps 9
1030 19:09:10.782139 RxClkDly_Margin_A1==88 ps 9
1031 19:09:10.782601 TxDqDly_Margin_A1==88 ps 9
1032 19:09:10.787693 TrainedVREFDQ_A0==76
1033 19:09:10.788190 TrainedVREFDQ_A1==77
1034 19:09:10.788602 VrefDac_Margin_A0==22
1035 19:09:10.793292 DeviceVref_Margin_A0==38
1036 19:09:10.793758 VrefDac_Margin_A1==24
1037 19:09:10.798885 DeviceVref_Margin_A1==37
1038 19:09:10.799350
1039 19:09:10.799756 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 19:09:10.800189
1041 19:09:10.832433 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1042 19:09:10.832927 2D training succeed
1043 19:09:10.838117 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 19:09:10.843707 auto size-- 65535DDR cs0 size: 2048MB
1045 19:09:10.844205 DDR cs1 size: 2048MB
1046 19:09:10.849294 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 19:09:10.849757 cs0 DataBus test pass
1048 19:09:10.854895 cs1 DataBus test pass
1049 19:09:10.855357 cs0 AddrBus test pass
1050 19:09:10.855766 cs1 AddrBus test pass
1051 19:09:10.856199
1052 19:09:10.860500 100bdlr_step_size ps== 420
1053 19:09:10.860969 result report
1054 19:09:10.866138 boot times 0Enable ddr reg access
1055 19:09:10.871433 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 19:09:10.884856 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 19:09:11.456880 0.0;M3 CHK:0;cm4_sp_mode 0
1058 19:09:11.457434 MVN_1=0x00000000
1059 19:09:11.462400 MVN_2=0x00000000
1060 19:09:11.468237 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 19:09:11.468877 OPS=0x10
1062 19:09:11.469438 ring efuse init
1063 19:09:11.469978 chipver efuse init
1064 19:09:11.473770 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 19:09:11.479357 [0.018961 Inits done]
1066 19:09:11.479815 secure task start!
1067 19:09:11.480267 high task start!
1068 19:09:11.483932 low task start!
1069 19:09:11.484417 run into bl31
1070 19:09:11.490582 NOTICE: BL31: v1.3(release):4fc40b1
1071 19:09:11.498385 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 19:09:11.498850 NOTICE: BL31: G12A normal boot!
1073 19:09:11.523770 NOTICE: BL31: BL33 decompress pass
1074 19:09:11.529472 ERROR: Error initializing runtime service opteed_fast
1075 19:09:12.762437
1076 19:09:12.763070
1077 19:09:12.770752 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 19:09:12.771239
1079 19:09:12.771663 Model: Libre Computer AML-A311D-CC Alta
1080 19:09:12.979181 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 19:09:13.002542 DRAM: 2 GiB (effective 3.8 GiB)
1082 19:09:13.145551 Core: 408 devices, 31 uclasses, devicetree: separate
1083 19:09:13.151399 WDT: Not starting watchdog@f0d0
1084 19:09:13.183717 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 19:09:13.196083 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 19:09:13.201107 ** Bad device specification mmc 0 **
1087 19:09:13.211444 Card did not respond to voltage select! : -110
1088 19:09:13.219094 ** Bad device specification mmc 0 **
1089 19:09:13.219585 Couldn't find partition mmc 0
1090 19:09:13.227416 Card did not respond to voltage select! : -110
1091 19:09:13.232927 ** Bad device specification mmc 0 **
1092 19:09:13.233406 Couldn't find partition mmc 0
1093 19:09:13.238008 Error: could not access storage.
1094 19:09:13.580489 Net: eth0: ethernet@ff3f0000
1095 19:09:13.581074 starting USB...
1096 19:09:13.832326 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 19:09:13.832897 Starting the controller
1098 19:09:13.839294 USB XHCI 1.10
1099 19:09:15.393584 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 19:09:15.402005 scanning usb for storage devices... 0 Storage Device(s) found
1102 19:09:15.453270 Hit any key to stop autoboot: 1
1103 19:09:15.453981 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 19:09:15.454334 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 19:09:15.454594 Setting prompt string to ['=>']
1106 19:09:15.454865 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 19:09:15.469268 0
1108 19:09:15.470076 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 19:09:15.470380 Sending with 10 millisecond of delay
1111 19:09:16.605537 => setenv autoload no
1112 19:09:16.616345 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1113 19:09:16.621890 setenv autoload no
1114 19:09:16.622704 Sending with 10 millisecond of delay
1116 19:09:18.422195 => setenv initrd_high 0xffffffff
1117 19:09:18.433023 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 19:09:18.433933 setenv initrd_high 0xffffffff
1119 19:09:18.434695 Sending with 10 millisecond of delay
1121 19:09:20.050825 => setenv fdt_high 0xffffffff
1122 19:09:20.061655 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 19:09:20.062558 setenv fdt_high 0xffffffff
1124 19:09:20.063333 Sending with 10 millisecond of delay
1126 19:09:20.355438 => dhcp
1127 19:09:20.366363 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 19:09:20.367341 dhcp
1129 19:09:20.367839 Speed: 1000, full duplex
1130 19:09:20.368353 BOOTP broadcast 1
1131 19:09:20.584176 DHCP client bound to address 192.168.6.27 (217 ms)
1132 19:09:20.585596 Sending with 10 millisecond of delay
1134 19:09:22.262437 => setenv serverip 192.168.6.2
1135 19:09:22.273245 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1136 19:09:22.274123 setenv serverip 192.168.6.2
1137 19:09:22.274825 Sending with 10 millisecond of delay
1139 19:09:25.999394 => tftpboot 0x01080000 935717/tftp-deploy-_lt89r3h/kernel/uImage
1140 19:09:26.010277 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1141 19:09:26.011175 tftpboot 0x01080000 935717/tftp-deploy-_lt89r3h/kernel/uImage
1142 19:09:26.011713 Speed: 1000, full duplex
1143 19:09:26.012161 Using ethernet@ff3f0000 device
1144 19:09:26.013079 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1145 19:09:26.018672 Filename '935717/tftp-deploy-_lt89r3h/kernel/uImage'.
1146 19:09:26.022536 Load address: 0x1080000
1147 19:09:29.085044 Loading: *################################################## 43.6 MiB
1148 19:09:29.085826 14.2 MiB/s
1149 19:09:29.086422 done
1150 19:09:29.089209 Bytes transferred = 45713984 (2b98a40 hex)
1151 19:09:29.090164 Sending with 10 millisecond of delay
1153 19:09:33.781650 => tftpboot 0x08000000 935717/tftp-deploy-_lt89r3h/ramdisk/ramdisk.cpio.gz.uboot
1154 19:09:33.792490 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1155 19:09:33.793477 tftpboot 0x08000000 935717/tftp-deploy-_lt89r3h/ramdisk/ramdisk.cpio.gz.uboot
1156 19:09:33.793919 Speed: 1000, full duplex
1157 19:09:33.794318 Using ethernet@ff3f0000 device
1158 19:09:33.795834 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1159 19:09:33.804054 Filename '935717/tftp-deploy-_lt89r3h/ramdisk/ramdisk.cpio.gz.uboot'.
1160 19:09:33.804619 Load address: 0x8000000
1161 19:09:39.203369 Loading: *############## UDP wrong checksum 000000ff 000034c6
1162 19:09:39.224773 UDP wrong checksum 000000ff 0000b8b8
1163 19:09:40.367126 T ################################### UDP wrong checksum 00000005 00008c50
1164 19:09:45.369467 T UDP wrong checksum 00000005 00008c50
1165 19:09:55.371415 T T UDP wrong checksum 00000005 00008c50
1166 19:10:15.375481 T T T T UDP wrong checksum 00000005 00008c50
1167 19:10:30.379458 T T
1168 19:10:30.380166 Retry count exceeded; starting again
1170 19:10:30.381718 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1173 19:10:30.383819 end: 2.4 uboot-commands (duration 00:01:52) [common]
1175 19:10:30.385397 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1177 19:10:30.386559 end: 2 uboot-action (duration 00:01:52) [common]
1179 19:10:30.388339 Cleaning after the job
1180 19:10:30.388944 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/935717/tftp-deploy-_lt89r3h/ramdisk
1181 19:10:30.391048 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/935717/tftp-deploy-_lt89r3h/kernel
1182 19:10:30.440467 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/935717/tftp-deploy-_lt89r3h/dtb
1183 19:10:30.441293 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/935717/tftp-deploy-_lt89r3h/nfsrootfs
1184 19:10:30.652451 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/935717/tftp-deploy-_lt89r3h/modules
1185 19:10:30.674136 start: 4.1 power-off (timeout 00:00:30) [common]
1186 19:10:30.674795 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1187 19:10:30.706351 >> OK - accepted request
1188 19:10:30.708360 Returned 0 in 0 seconds
1189 19:10:30.809108 end: 4.1 power-off (duration 00:00:00) [common]
1191 19:10:30.810077 start: 4.2 read-feedback (timeout 00:10:00) [common]
1192 19:10:30.810734 Listened to connection for namespace 'common' for up to 1s
1193 19:10:31.811672 Finalising connection for namespace 'common'
1194 19:10:31.812162 Disconnecting from shell: Finalise
1195 19:10:31.812439 =>
1196 19:10:31.913081 end: 4.2 read-feedback (duration 00:00:01) [common]
1197 19:10:31.913448 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/935717
1198 19:10:34.661978 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/935717
1199 19:10:34.662625 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.