Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 18:58:25.650852 lava-dispatcher, installed at version: 2024.01
2 18:58:25.651651 start: 0 validate
3 18:58:25.652150 Start time: 2024-11-11 18:58:25.652117+00:00 (UTC)
4 18:58:25.652711 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 18:58:25.653260 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 18:58:25.696323 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 18:58:25.696883 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc7-108-g7b04a3bdf53e%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 18:58:25.729168 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 18:58:25.729795 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc7-108-g7b04a3bdf53e%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 18:58:25.761251 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 18:58:25.761848 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 18:58:25.793313 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 18:58:25.793796 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fpm%2Ftesting%2Fv6.12-rc7-108-g7b04a3bdf53e%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 18:58:25.833458 validate duration: 0.18
16 18:58:25.834362 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 18:58:25.834694 start: 1.1 download-retry (timeout 00:10:00) [common]
18 18:58:25.835003 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 18:58:25.835602 Not decompressing ramdisk as can be used compressed.
20 18:58:25.836075 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 18:58:25.836356 saving as /var/lib/lava/dispatcher/tmp/976601/tftp-deploy-9l7315sr/ramdisk/initrd.cpio.gz
22 18:58:25.836631 total size: 4775763 (4 MB)
23 18:58:25.873286 progress 0 % (0 MB)
24 18:58:25.879909 progress 5 % (0 MB)
25 18:58:25.886184 progress 10 % (0 MB)
26 18:58:25.892448 progress 15 % (0 MB)
27 18:58:25.899349 progress 20 % (0 MB)
28 18:58:25.903006 progress 25 % (1 MB)
29 18:58:25.906323 progress 30 % (1 MB)
30 18:58:25.909954 progress 35 % (1 MB)
31 18:58:25.913193 progress 40 % (1 MB)
32 18:58:25.916465 progress 45 % (2 MB)
33 18:58:25.919661 progress 50 % (2 MB)
34 18:58:25.923246 progress 55 % (2 MB)
35 18:58:25.926425 progress 60 % (2 MB)
36 18:58:25.931295 progress 65 % (2 MB)
37 18:58:25.935296 progress 70 % (3 MB)
38 18:58:25.938514 progress 75 % (3 MB)
39 18:58:25.941818 progress 80 % (3 MB)
40 18:58:25.945055 progress 85 % (3 MB)
41 18:58:25.948700 progress 90 % (4 MB)
42 18:58:25.951786 progress 95 % (4 MB)
43 18:58:25.954834 progress 100 % (4 MB)
44 18:58:25.955564 4 MB downloaded in 0.12 s (38.30 MB/s)
45 18:58:25.956201 end: 1.1.1 http-download (duration 00:00:00) [common]
47 18:58:25.957267 end: 1.1 download-retry (duration 00:00:00) [common]
48 18:58:25.957609 start: 1.2 download-retry (timeout 00:10:00) [common]
49 18:58:25.957890 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 18:58:25.958366 downloading http://storage.kernelci.org/pm/testing/v6.12-rc7-108-g7b04a3bdf53e/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 18:58:25.958657 saving as /var/lib/lava/dispatcher/tmp/976601/tftp-deploy-9l7315sr/kernel/zImage
52 18:58:25.958868 total size: 11448832 (10 MB)
53 18:58:25.959084 No compression specified
54 18:58:25.994080 progress 0 % (0 MB)
55 18:58:26.001738 progress 5 % (0 MB)
56 18:58:26.009154 progress 10 % (1 MB)
57 18:58:26.017172 progress 15 % (1 MB)
58 18:58:26.024973 progress 20 % (2 MB)
59 18:58:26.033061 progress 25 % (2 MB)
60 18:58:26.040709 progress 30 % (3 MB)
61 18:58:26.048653 progress 35 % (3 MB)
62 18:58:26.056027 progress 40 % (4 MB)
63 18:58:26.064142 progress 45 % (4 MB)
64 18:58:26.071747 progress 50 % (5 MB)
65 18:58:26.080276 progress 55 % (6 MB)
66 18:58:26.087549 progress 60 % (6 MB)
67 18:58:26.095148 progress 65 % (7 MB)
68 18:58:26.102401 progress 70 % (7 MB)
69 18:58:26.110014 progress 75 % (8 MB)
70 18:58:26.117278 progress 80 % (8 MB)
71 18:58:26.124686 progress 85 % (9 MB)
72 18:58:26.132738 progress 90 % (9 MB)
73 18:58:26.140140 progress 95 % (10 MB)
74 18:58:26.147414 progress 100 % (10 MB)
75 18:58:26.148045 10 MB downloaded in 0.19 s (57.74 MB/s)
76 18:58:26.148597 end: 1.2.1 http-download (duration 00:00:00) [common]
78 18:58:26.149513 end: 1.2 download-retry (duration 00:00:00) [common]
79 18:58:26.149831 start: 1.3 download-retry (timeout 00:10:00) [common]
80 18:58:26.150122 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 18:58:26.150585 downloading http://storage.kernelci.org/pm/testing/v6.12-rc7-108-g7b04a3bdf53e/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 18:58:26.150899 saving as /var/lib/lava/dispatcher/tmp/976601/tftp-deploy-9l7315sr/dtb/am335x-boneblack.dtb
83 18:58:26.151126 total size: 70568 (0 MB)
84 18:58:26.151339 No compression specified
85 18:58:26.187904 progress 46 % (0 MB)
86 18:58:26.188850 progress 92 % (0 MB)
87 18:58:26.189586 progress 100 % (0 MB)
88 18:58:26.190049 0 MB downloaded in 0.04 s (1.73 MB/s)
89 18:58:26.190577 end: 1.3.1 http-download (duration 00:00:00) [common]
91 18:58:26.191476 end: 1.3 download-retry (duration 00:00:00) [common]
92 18:58:26.191761 start: 1.4 download-retry (timeout 00:10:00) [common]
93 18:58:26.192069 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 18:58:26.192564 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 18:58:26.192849 saving as /var/lib/lava/dispatcher/tmp/976601/tftp-deploy-9l7315sr/nfsrootfs/full.rootfs.tar
96 18:58:26.193076 total size: 117747780 (112 MB)
97 18:58:26.193299 Using unxz to decompress xz
98 18:58:26.233526 progress 0 % (0 MB)
99 18:58:26.963327 progress 5 % (5 MB)
100 18:58:27.732750 progress 10 % (11 MB)
101 18:58:28.506244 progress 15 % (16 MB)
102 18:58:29.225861 progress 20 % (22 MB)
103 18:58:29.820900 progress 25 % (28 MB)
104 18:58:30.627961 progress 30 % (33 MB)
105 18:58:31.432700 progress 35 % (39 MB)
106 18:58:31.833013 progress 40 % (44 MB)
107 18:58:32.189937 progress 45 % (50 MB)
108 18:58:32.855731 progress 50 % (56 MB)
109 18:58:33.665703 progress 55 % (61 MB)
110 18:58:34.391826 progress 60 % (67 MB)
111 18:58:35.110520 progress 65 % (73 MB)
112 18:58:35.865493 progress 70 % (78 MB)
113 18:58:36.617487 progress 75 % (84 MB)
114 18:58:37.345420 progress 80 % (89 MB)
115 18:58:38.047228 progress 85 % (95 MB)
116 18:58:38.830574 progress 90 % (101 MB)
117 18:58:39.597780 progress 95 % (106 MB)
118 18:58:40.415356 progress 100 % (112 MB)
119 18:58:40.429306 112 MB downloaded in 14.24 s (7.89 MB/s)
120 18:58:40.429993 end: 1.4.1 http-download (duration 00:00:14) [common]
122 18:58:40.430838 end: 1.4 download-retry (duration 00:00:14) [common]
123 18:58:40.431109 start: 1.5 download-retry (timeout 00:09:45) [common]
124 18:58:40.431370 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 18:58:40.431948 downloading http://storage.kernelci.org/pm/testing/v6.12-rc7-108-g7b04a3bdf53e/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 18:58:40.432443 saving as /var/lib/lava/dispatcher/tmp/976601/tftp-deploy-9l7315sr/modules/modules.tar
127 18:58:40.432856 total size: 6609684 (6 MB)
128 18:58:40.433274 Using unxz to decompress xz
129 18:58:40.476257 progress 0 % (0 MB)
130 18:58:40.512643 progress 5 % (0 MB)
131 18:58:40.556312 progress 10 % (0 MB)
132 18:58:40.600332 progress 15 % (0 MB)
133 18:58:40.645833 progress 20 % (1 MB)
134 18:58:40.693503 progress 25 % (1 MB)
135 18:58:40.737181 progress 30 % (1 MB)
136 18:58:40.779521 progress 35 % (2 MB)
137 18:58:40.823096 progress 40 % (2 MB)
138 18:58:40.866140 progress 45 % (2 MB)
139 18:58:40.909468 progress 50 % (3 MB)
140 18:58:40.951826 progress 55 % (3 MB)
141 18:58:41.001289 progress 60 % (3 MB)
142 18:58:41.043673 progress 65 % (4 MB)
143 18:58:41.086695 progress 70 % (4 MB)
144 18:58:41.132379 progress 75 % (4 MB)
145 18:58:41.174960 progress 80 % (5 MB)
146 18:58:41.217453 progress 85 % (5 MB)
147 18:58:41.260404 progress 90 % (5 MB)
148 18:58:41.303530 progress 95 % (6 MB)
149 18:58:41.347664 progress 100 % (6 MB)
150 18:58:41.361559 6 MB downloaded in 0.93 s (6.79 MB/s)
151 18:58:41.362177 end: 1.5.1 http-download (duration 00:00:01) [common]
153 18:58:41.363014 end: 1.5 download-retry (duration 00:00:01) [common]
154 18:58:41.363279 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 18:58:41.363546 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 18:58:57.756230 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/976601/extract-nfsrootfs-70gq04xx
157 18:58:57.756814 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 18:58:57.757103 start: 1.6.2 lava-overlay (timeout 00:09:28) [common]
159 18:58:57.757870 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__
160 18:58:57.758354 makedir: /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin
161 18:58:57.758689 makedir: /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/tests
162 18:58:57.759008 makedir: /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/results
163 18:58:57.759344 Creating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-add-keys
164 18:58:57.759882 Creating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-add-sources
165 18:58:57.760432 Creating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-background-process-start
166 18:58:57.760935 Creating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-background-process-stop
167 18:58:57.761462 Creating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-common-functions
168 18:58:57.761959 Creating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-echo-ipv4
169 18:58:57.762448 Creating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-install-packages
170 18:58:57.762926 Creating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-installed-packages
171 18:58:57.763410 Creating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-os-build
172 18:58:57.763894 Creating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-probe-channel
173 18:58:57.764418 Creating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-probe-ip
174 18:58:57.764928 Creating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-target-ip
175 18:58:57.765450 Creating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-target-mac
176 18:58:57.765957 Creating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-target-storage
177 18:58:57.766454 Creating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-test-case
178 18:58:57.766944 Creating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-test-event
179 18:58:57.767423 Creating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-test-feedback
180 18:58:57.767899 Creating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-test-raise
181 18:58:57.768411 Creating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-test-reference
182 18:58:57.768890 Creating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-test-runner
183 18:58:57.769400 Creating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-test-set
184 18:58:57.769899 Creating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-test-shell
185 18:58:57.770390 Updating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-add-keys (debian)
186 18:58:57.770923 Updating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-add-sources (debian)
187 18:58:57.771449 Updating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-install-packages (debian)
188 18:58:57.771957 Updating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-installed-packages (debian)
189 18:58:57.772488 Updating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/bin/lava-os-build (debian)
190 18:58:57.772929 Creating /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/environment
191 18:58:57.773303 LAVA metadata
192 18:58:57.773561 - LAVA_JOB_ID=976601
193 18:58:57.773779 - LAVA_DISPATCHER_IP=192.168.6.2
194 18:58:57.774138 start: 1.6.2.1 ssh-authorize (timeout 00:09:28) [common]
195 18:58:57.775097 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 18:58:57.775411 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:28) [common]
197 18:58:57.775619 skipped lava-vland-overlay
198 18:58:57.775863 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 18:58:57.776149 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:28) [common]
200 18:58:57.776371 skipped lava-multinode-overlay
201 18:58:57.776614 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 18:58:57.776864 start: 1.6.2.4 test-definition (timeout 00:09:28) [common]
203 18:58:57.777112 Loading test definitions
204 18:58:57.777390 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:28) [common]
205 18:58:57.777608 Using /lava-976601 at stage 0
206 18:58:57.778779 uuid=976601_1.6.2.4.1 testdef=None
207 18:58:57.779093 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 18:58:57.779355 start: 1.6.2.4.2 test-overlay (timeout 00:09:28) [common]
209 18:58:57.780980 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 18:58:57.781771 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:28) [common]
212 18:58:57.783682 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 18:58:57.784539 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:28) [common]
215 18:58:57.786367 runner path: /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/0/tests/0_timesync-off test_uuid 976601_1.6.2.4.1
216 18:58:57.786915 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 18:58:57.787731 start: 1.6.2.4.5 git-repo-action (timeout 00:09:28) [common]
219 18:58:57.787968 Using /lava-976601 at stage 0
220 18:58:57.788360 Fetching tests from https://github.com/kernelci/test-definitions.git
221 18:58:57.788651 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/0/tests/1_kselftest-dt'
222 18:59:01.233594 Running '/usr/bin/git checkout kernelci.org
223 18:59:01.470110 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 18:59:01.471560 uuid=976601_1.6.2.4.5 testdef=None
225 18:59:01.471905 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 18:59:01.472695 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 18:59:01.475553 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 18:59:01.476420 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 18:59:01.480236 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 18:59:01.481110 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 18:59:01.484728 runner path: /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/0/tests/1_kselftest-dt test_uuid 976601_1.6.2.4.5
235 18:59:01.485028 BOARD='beaglebone-black'
236 18:59:01.485234 BRANCH='pm'
237 18:59:01.485432 SKIPFILE='/dev/null'
238 18:59:01.485629 SKIP_INSTALL='True'
239 18:59:01.485826 TESTPROG_URL='http://storage.kernelci.org/pm/testing/v6.12-rc7-108-g7b04a3bdf53e/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 18:59:01.486026 TST_CASENAME=''
241 18:59:01.486223 TST_CMDFILES='dt'
242 18:59:01.486793 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 18:59:01.487599 Creating lava-test-runner.conf files
245 18:59:01.487807 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/976601/lava-overlay-h7xkh7__/lava-976601/0 for stage 0
246 18:59:01.488201 - 0_timesync-off
247 18:59:01.488458 - 1_kselftest-dt
248 18:59:01.488805 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 18:59:01.489092 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 18:59:25.558655 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 18:59:25.559102 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:00) [common]
252 18:59:25.559400 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 18:59:25.559712 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
254 18:59:25.560038 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:00) [common]
255 18:59:25.940850 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 18:59:25.941345 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 18:59:25.941624 extracting modules file /var/lib/lava/dispatcher/tmp/976601/tftp-deploy-9l7315sr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/976601/extract-nfsrootfs-70gq04xx
258 18:59:26.836291 extracting modules file /var/lib/lava/dispatcher/tmp/976601/tftp-deploy-9l7315sr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/976601/extract-overlay-ramdisk-wpah4hz_/ramdisk
259 18:59:27.768464 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 18:59:27.768946 start: 1.6.5 apply-overlay-tftp (timeout 00:08:58) [common]
261 18:59:27.769240 [common] Applying overlay to NFS
262 18:59:27.769471 [common] Applying overlay /var/lib/lava/dispatcher/tmp/976601/compress-overlay-r_jb2bmt/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/976601/extract-nfsrootfs-70gq04xx
263 18:59:30.644258 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 18:59:30.644757 start: 1.6.6 prepare-kernel (timeout 00:08:55) [common]
265 18:59:30.645083 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:55) [common]
266 18:59:30.645406 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 18:59:30.645690 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 18:59:30.645968 start: 1.6.7 configure-preseed-file (timeout 00:08:55) [common]
269 18:59:30.646241 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 18:59:30.646524 start: 1.6.8 compress-ramdisk (timeout 00:08:55) [common]
271 18:59:30.646791 Building ramdisk /var/lib/lava/dispatcher/tmp/976601/extract-overlay-ramdisk-wpah4hz_/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/976601/extract-overlay-ramdisk-wpah4hz_/ramdisk
272 18:59:31.708478 >> 74902 blocks
273 18:59:36.469018 Adding RAMdisk u-boot header.
274 18:59:36.469506 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/976601/extract-overlay-ramdisk-wpah4hz_/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/976601/extract-overlay-ramdisk-wpah4hz_/ramdisk.cpio.gz.uboot
275 18:59:36.628943 output: Image Name:
276 18:59:36.629371 output: Created: Mon Nov 11 18:59:36 2024
277 18:59:36.629582 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 18:59:36.629789 output: Data Size: 14791487 Bytes = 14444.81 KiB = 14.11 MiB
279 18:59:36.629995 output: Load Address: 00000000
280 18:59:36.630199 output: Entry Point: 00000000
281 18:59:36.630399 output:
282 18:59:36.631066 rename /var/lib/lava/dispatcher/tmp/976601/extract-overlay-ramdisk-wpah4hz_/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/976601/tftp-deploy-9l7315sr/ramdisk/ramdisk.cpio.gz.uboot
283 18:59:36.631496 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 18:59:36.631782 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 18:59:36.632154 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:49) [common]
286 18:59:36.632622 No LXC device requested
287 18:59:36.633124 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 18:59:36.633631 start: 1.8 deploy-device-env (timeout 00:08:49) [common]
289 18:59:36.634128 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 18:59:36.634539 Checking files for TFTP limit of 4294967296 bytes.
291 18:59:36.637246 end: 1 tftp-deploy (duration 00:01:11) [common]
292 18:59:36.637820 start: 2 uboot-action (timeout 00:05:00) [common]
293 18:59:36.638339 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 18:59:36.638833 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 18:59:36.639330 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 18:59:36.640112 substitutions:
297 18:59:36.640544 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 18:59:36.640947 - {DTB_ADDR}: 0x88000000
299 18:59:36.641345 - {DTB}: 976601/tftp-deploy-9l7315sr/dtb/am335x-boneblack.dtb
300 18:59:36.641739 - {INITRD}: 976601/tftp-deploy-9l7315sr/ramdisk/ramdisk.cpio.gz.uboot
301 18:59:36.642135 - {KERNEL_ADDR}: 0x82000000
302 18:59:36.642525 - {KERNEL}: 976601/tftp-deploy-9l7315sr/kernel/zImage
303 18:59:36.642914 - {LAVA_MAC}: None
304 18:59:36.643345 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/976601/extract-nfsrootfs-70gq04xx
305 18:59:36.643743 - {NFS_SERVER_IP}: 192.168.6.2
306 18:59:36.644166 - {PRESEED_CONFIG}: None
307 18:59:36.644557 - {PRESEED_LOCAL}: None
308 18:59:36.644946 - {RAMDISK_ADDR}: 0x83000000
309 18:59:36.645336 - {RAMDISK}: 976601/tftp-deploy-9l7315sr/ramdisk/ramdisk.cpio.gz.uboot
310 18:59:36.645729 - {ROOT_PART}: None
311 18:59:36.646111 - {ROOT}: None
312 18:59:36.646495 - {SERVER_IP}: 192.168.6.2
313 18:59:36.646878 - {TEE_ADDR}: 0x83000000
314 18:59:36.647261 - {TEE}: None
315 18:59:36.647644 Parsed boot commands:
316 18:59:36.648040 - setenv autoload no
317 18:59:36.648428 - setenv initrd_high 0xffffffff
318 18:59:36.648814 - setenv fdt_high 0xffffffff
319 18:59:36.649197 - dhcp
320 18:59:36.649578 - setenv serverip 192.168.6.2
321 18:59:36.649962 - tftp 0x82000000 976601/tftp-deploy-9l7315sr/kernel/zImage
322 18:59:36.650347 - tftp 0x83000000 976601/tftp-deploy-9l7315sr/ramdisk/ramdisk.cpio.gz.uboot
323 18:59:36.650733 - setenv initrd_size ${filesize}
324 18:59:36.651113 - tftp 0x88000000 976601/tftp-deploy-9l7315sr/dtb/am335x-boneblack.dtb
325 18:59:36.651498 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/976601/extract-nfsrootfs-70gq04xx,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 18:59:36.651893 - bootz 0x82000000 0x83000000 0x88000000
327 18:59:36.652415 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 18:59:36.653883 start: 2.3 connect-device (timeout 00:05:00) [common]
330 18:59:36.654296 [common] connect-device Connecting to device using 'telnet conserv1 3003'
331 18:59:36.669420 Setting prompt string to ['lava-test: # ']
332 18:59:36.670914 end: 2.3 connect-device (duration 00:00:00) [common]
333 18:59:36.671509 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 18:59:36.672134 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 18:59:36.672811 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 18:59:36.673664 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-01'
337 18:59:36.708166 >> OK - accepted request
338 18:59:36.710039 Returned 0 in 0 seconds
339 18:59:36.811143 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 18:59:36.812806 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 18:59:36.813370 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 18:59:36.813883 Setting prompt string to ['Hit any key to stop autoboot']
344 18:59:36.814346 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 18:59:36.815902 Trying 192.168.56.21...
346 18:59:36.816421 Connected to conserv1.
347 18:59:36.816838 Escape character is '^]'.
348 18:59:36.817251
349 18:59:36.817651 ser2net port telnet,3003 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
350 18:59:36.818054
351 18:59:44.338629
352 18:59:44.339070 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
353 18:59:44.343812 Trying to boot from MMC1
354 18:59:44.916772
355 18:59:44.917413
356 18:59:44.917824 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
357 18:59:44.918225
358 18:59:44.922166 CPU : AM335X-GP rev 2.1
359 18:59:44.922658 Model: TI AM335x BeagleBone Black
360 18:59:44.926310 DRAM: 512 MiB
361 18:59:45.009125 Core: 160 devices, 18 uclasses, devicetree: separate
362 18:59:45.019026 WDT: Started wdt@44e35000 with servicing (60s timeout)
363 18:59:48.389241 7[r[999;999H[6n8NAND:
364 18:59:48.389691 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
365 18:59:48.394390 Trying to boot from MMC1
366 18:59:48.966641
367 18:59:48.967228
368 18:59:48.967638 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
369 18:59:48.968086
370 18:59:48.971948 CPU : AM335X-GP rev 2.1
371 18:59:48.972404 Model: TI AM335x BeagleBone Black
372 18:59:48.976123 DRAM: 512 MiB
373 18:59:49.058945 Core: 160 devices, 18 uclasses, devicetree: separate
374 18:59:49.068398 WDT: Started wdt@44e35000 with servicing (60s timeout)
375 18:59:51.088316 7[r[999;999H[6n8NAND:
376 18:59:51.088949 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
377 18:59:51.093366 Trying to boot from MMC1
378 18:59:51.666349
379 18:59:51.666961
380 18:59:51.667391 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
381 18:59:51.667813
382 18:59:51.671872 CPU : AM335X-GP rev 2.1
383 18:59:51.672385 Model: TI AM335x BeagleBone Black
384 18:59:51.675942 DRAM: 512 MiB
385 18:59:51.758708 Core: 160 devices, 18 uclasses, devicetree: separate
386 18:59:51.768292 WDT: Started wdt@44e35000 with servicing (60s timeout)
387 18:59:52.273621 7[r[999;999H[6n8NAND: 0 MiB
388 18:59:52.283598 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
389 18:59:52.356584 Loading Environment from FAT... Unable to use mmc 0:1...
390 18:59:52.377785 <ethaddr> not set. Validating first E-fuse MAC
391 18:59:52.408151 Net: eth2: ethernet@4a100000, eth3: usb_ether
393 18:59:52.466715 Hit any key to stop autoboot: 2
394 18:59:52.467453 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
395 18:59:52.467792 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
396 18:59:52.468066 Setting prompt string to ['=>']
397 18:59:52.468320 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
398 18:59:52.476652 0
399 18:59:52.477257 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
400 18:59:52.477534 Sending with 10 millisecond of delay
402 18:59:53.611425 => setenv autoload no
403 18:59:53.624811 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
404 18:59:53.630299 setenv autoload no
405 18:59:53.631078 Sending with 10 millisecond of delay
407 18:59:55.428530 => setenv initrd_high 0xffffffff
408 18:59:55.439358 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
409 18:59:55.440341 setenv initrd_high 0xffffffff
410 18:59:55.441135 Sending with 10 millisecond of delay
412 18:59:57.057791 => setenv fdt_high 0xffffffff
413 18:59:57.068611 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
414 18:59:57.069503 setenv fdt_high 0xffffffff
415 18:59:57.070273 Sending with 10 millisecond of delay
417 18:59:57.362305 => dhcp
418 18:59:57.373488 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
419 18:59:57.374551 dhcp
420 18:59:57.375105 link up on port 0, speed 100, full duplex
421 18:59:57.375590 BOOTP broadcast 1
422 18:59:57.395908 DHCP client bound to address 192.168.6.12 (17 ms)
423 18:59:57.396756 Sending with 10 millisecond of delay
425 18:59:59.073908 => setenv serverip 192.168.6.2
426 18:59:59.084519 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
427 18:59:59.085177 setenv serverip 192.168.6.2
428 18:59:59.085721 Sending with 10 millisecond of delay
430 19:00:02.569218 => tftp 0x82000000 976601/tftp-deploy-9l7315sr/kernel/zImage
431 19:00:02.580187 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
432 19:00:02.580748 tftp 0x82000000 976601/tftp-deploy-9l7315sr/kernel/zImage
433 19:00:02.581009 link up on port 0, speed 100, full duplex
434 19:00:02.584511 Using ethernet@4a100000 device
435 19:00:02.590087 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
436 19:00:02.598924 Filename '976601/tftp-deploy-9l7315sr/kernel/zImage'.
437 19:00:02.599379 Load address: 0x82000000
438 19:00:04.934639 Loading: *################################################## 10.9 MiB
439 19:00:04.935268 4.7 MiB/s
440 19:00:04.935710 done
441 19:00:04.938936 Bytes transferred = 11448832 (aeb200 hex)
442 19:00:04.939768 Sending with 10 millisecond of delay
444 19:00:09.387757 => tftp 0x83000000 976601/tftp-deploy-9l7315sr/ramdisk/ramdisk.cpio.gz.uboot
445 19:00:09.398397 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
446 19:00:09.399035 tftp 0x83000000 976601/tftp-deploy-9l7315sr/ramdisk/ramdisk.cpio.gz.uboot
447 19:00:09.399291 link up on port 0, speed 100, full duplex
448 19:00:09.403309 Using ethernet@4a100000 device
449 19:00:09.408937 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
450 19:00:09.417398 Filename '976601/tftp-deploy-9l7315sr/ramdisk/ramdisk.cpio.gz.uboot'.
451 19:00:09.417799 Load address: 0x83000000
452 19:00:12.447905 Loading: *################################################## 14.1 MiB
453 19:00:12.448551 4.7 MiB/s
454 19:00:12.449001 done
455 19:00:12.452095 Bytes transferred = 14791551 (e1b37f hex)
456 19:00:12.452898 Sending with 10 millisecond of delay
458 19:00:14.309795 => setenv initrd_size ${filesize}
459 19:00:14.320510 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
460 19:00:14.321002 setenv initrd_size ${filesize}
461 19:00:14.321456 Sending with 10 millisecond of delay
463 19:00:18.464653 => tftp 0x88000000 976601/tftp-deploy-9l7315sr/dtb/am335x-boneblack.dtb
464 19:00:18.477746 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
465 19:00:18.478369 tftp 0x88000000 976601/tftp-deploy-9l7315sr/dtb/am335x-boneblack.dtb
466 19:00:18.478615 link up on port 0, speed 100, full duplex
467 19:00:18.480052 Using ethernet@4a100000 device
468 19:00:18.485644 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
469 19:00:18.497341 Filename '976601/tftp-deploy-9l7315sr/dtb/am335x-boneblack.dtb'.
470 19:00:18.497686 Load address: 0x88000000
471 19:00:18.510483 Loading: *################################################## 68.9 KiB
472 19:00:18.510794 4 MiB/s
473 19:00:18.511000 done
474 19:00:18.519371 Bytes transferred = 70568 (113a8 hex)
475 19:00:18.519856 Sending with 10 millisecond of delay
477 19:00:31.727543 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/976601/extract-nfsrootfs-70gq04xx,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 19:00:31.738188 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
479 19:00:31.738827 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/976601/extract-nfsrootfs-70gq04xx,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 19:00:31.739600 Sending with 10 millisecond of delay
482 19:00:34.084394 => bootz 0x82000000 0x83000000 0x88000000
483 19:00:34.095182 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 19:00:34.095642 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
485 19:00:34.096289 bootz 0x82000000 0x83000000 0x88000000
486 19:00:34.096565 Kernel image @ 0x82000000 [ 0x000000 - 0xaeb200 ]
487 19:00:34.097676 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 19:00:34.103263 Image Name:
489 19:00:34.103766 Created: 2024-11-11 18:59:36 UTC
490 19:00:34.106677 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 19:00:34.111768 Data Size: 14791487 Bytes = 14.1 MiB
492 19:00:34.120110 Load Address: 00000000
493 19:00:34.120644 Entry Point: 00000000
494 19:00:34.288700 Verifying Checksum ... OK
495 19:00:34.289286 ## Flattened Device Tree blob at 88000000
496 19:00:34.295272 Booting using the fdt blob at 0x88000000
497 19:00:34.299944 Using Device Tree in place at 88000000, end 880143a7
498 19:00:34.313646
499 19:00:34.314054 Starting kernel ...
500 19:00:34.314273
501 19:00:34.314947 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 19:00:34.315417 start: 2.4.4 auto-login-action (timeout 00:04:02) [common]
503 19:00:34.315792 Setting prompt string to ['Linux version [0-9]']
504 19:00:34.316216 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
505 19:00:34.316590 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
506 19:00:35.161173 [ 0.000000] Booting Linux on physical CPU 0x0
507 19:00:35.167056 start: 2.4.4.1 login-action (timeout 00:04:01) [common]
508 19:00:35.167537 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 19:00:35.167828 Setting prompt string to []
510 19:00:35.168145 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 19:00:35.168420 Using line separator: #'\n'#
512 19:00:35.168641 No login prompt set.
513 19:00:35.168881 Parsing kernel messages
514 19:00:35.169103 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 19:00:35.169525 [login-action] Waiting for messages, (timeout 00:04:01)
516 19:00:35.169785 Waiting using forced prompt support (timeout 00:02:01)
517 19:00:35.183808 [ 0.000000] Linux version 6.12.0-rc7 (KernelCI@build-j373033-arm-gcc-12-multi-v7-defconfig-6xv2d) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Mon Nov 11 18:16:08 UTC 2024
518 19:00:35.189672 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
519 19:00:35.195320 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
520 19:00:35.206703 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
521 19:00:35.212274 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
522 19:00:35.218335 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
523 19:00:35.218759 [ 0.000000] Memory policy: Data cache writeback
524 19:00:35.224704 [ 0.000000] efi: UEFI not found.
525 19:00:35.230219 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
526 19:00:35.235894 [ 0.000000] Zone ranges:
527 19:00:35.241643 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
528 19:00:35.247345 [ 0.000000] Normal empty
529 19:00:35.247751 [ 0.000000] HighMem empty
530 19:00:35.253197 [ 0.000000] Movable zone start for each node
531 19:00:35.253776 [ 0.000000] Early memory node ranges
532 19:00:35.264935 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
533 19:00:35.269954 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
534 19:00:35.295371 [ 0.000000] CPU: All CPU(s) started in SVC mode.
535 19:00:35.301090 [ 0.000000] AM335X ES2.1 (sgx neon)
536 19:00:35.312629 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
537 19:00:35.330254 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/976601/extract-nfsrootfs-70gq04xx,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
538 19:00:35.342214 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
539 19:00:35.347576 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
540 19:00:35.353262 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
541 19:00:35.363264 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
542 19:00:35.392214 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
543 19:00:35.398207 <6>[ 0.000000] trace event string verifier disabled
544 19:00:35.398561 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
545 19:00:35.406193 <6>[ 0.000000] rcu: RCU event tracing is enabled.
546 19:00:35.412276 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
547 19:00:35.423386 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
548 19:00:35.428406 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
549 19:00:35.443262 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
550 19:00:35.460517 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
551 19:00:35.467244 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
552 19:00:35.559605 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
553 19:00:35.568278 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
554 19:00:35.580724 <6>[ 0.008338] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
555 19:00:35.588782 <6>[ 0.019141] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
556 19:00:35.598189 <6>[ 0.033949] Console: colour dummy device 80x30
557 19:00:35.604167 Matched prompt #6: WARNING:
558 19:00:35.604546 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
559 19:00:35.609695 <3>[ 0.038848] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
560 19:00:35.615463 <3>[ 0.045922] This ensures that you still see kernel messages. Please
561 19:00:35.618653 <3>[ 0.052646] update your kernel commandline.
562 19:00:35.659357 <6>[ 0.057255] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
563 19:00:35.665105 <6>[ 0.096146] CPU: Testing write buffer coherency: ok
564 19:00:35.671057 <6>[ 0.101509] CPU0: Spectre v2: using BPIALL workaround
565 19:00:35.671439 <6>[ 0.106975] pid_max: default: 32768 minimum: 301
566 19:00:35.682614 <6>[ 0.112168] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
567 19:00:35.689606 <6>[ 0.119994] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 19:00:35.696589 <6>[ 0.129356] CPU0: thread -1, cpu 0, socket -1, mpidr 0
569 19:00:35.705187 <6>[ 0.136358] Setting up static identity map for 0x80300000 - 0x803000ac
570 19:00:35.710262 <6>[ 0.145983] rcu: Hierarchical SRCU implementation.
571 19:00:35.717401 <6>[ 0.151266] rcu: Max phase no-delay instances is 1000.
572 19:00:35.726935 <6>[ 0.162388] EFI services will not be available.
573 19:00:35.732788 <6>[ 0.167674] smp: Bringing up secondary CPUs ...
574 19:00:35.738599 <6>[ 0.172720] smp: Brought up 1 node, 1 CPU
575 19:00:35.744275 <6>[ 0.177121] SMP: Total of 1 processors activated (996.14 BogoMIPS).
576 19:00:35.750179 <6>[ 0.183890] CPU: All CPU(s) started in SVC mode.
577 19:00:35.770586 <6>[ 0.189074] Memory: 405996K/522240K available (16384K kernel code, 2543K rwdata, 6788K rodata, 2048K init, 430K bss, 49052K reserved, 65536K cma-reserved, 0K highmem)
578 19:00:35.771008 <6>[ 0.205340] devtmpfs: initialized
579 19:00:35.792846 <6>[ 0.222567] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
580 19:00:35.804369 <6>[ 0.231145] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
581 19:00:35.810313 <6>[ 0.241595] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
582 19:00:35.821099 <6>[ 0.253923] pinctrl core: initialized pinctrl subsystem
583 19:00:35.830403 <6>[ 0.264555] DMI not present or invalid.
584 19:00:35.838713 <6>[ 0.270413] NET: Registered PF_NETLINK/PF_ROUTE protocol family
585 19:00:35.848199 <6>[ 0.279348] DMA: preallocated 256 KiB pool for atomic coherent allocations
586 19:00:35.863371 <6>[ 0.290950] thermal_sys: Registered thermal governor 'step_wise'
587 19:00:35.863805 <6>[ 0.291109] cpuidle: using governor menu
588 19:00:35.891165 <6>[ 0.326871] No ATAGs?
589 19:00:35.897337 <6>[ 0.329604] hw-breakpoint: debug architecture 0x4 unsupported.
590 19:00:35.907479 <6>[ 0.341509] Serial: AMBA PL011 UART driver
591 19:00:35.939235 <6>[ 0.374915] iommu: Default domain type: Translated
592 19:00:35.948416 <6>[ 0.380260] iommu: DMA domain TLB invalidation policy: strict mode
593 19:00:35.975766 <5>[ 0.410688] SCSI subsystem initialized
594 19:00:35.981503 <6>[ 0.415568] usbcore: registered new interface driver usbfs
595 19:00:35.987405 <6>[ 0.421590] usbcore: registered new interface driver hub
596 19:00:35.993983 <6>[ 0.427371] usbcore: registered new device driver usb
597 19:00:36.000014 <6>[ 0.433873] pps_core: LinuxPPS API ver. 1 registered
598 19:00:36.011180 <6>[ 0.439258] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
599 19:00:36.018401 <6>[ 0.448982] PTP clock support registered
600 19:00:36.018951 <6>[ 0.453439] EDAC MC: Ver: 3.0.0
601 19:00:36.351459 <6>[ 0.500351] scmi_core: SCMI protocol bus registered
602 19:00:36.352115 <6>[ 0.517706] vgaarb: loaded
603 19:00:36.352386 <6>[ 0.521547] clocksource: Switched to clocksource dmtimer
604 19:00:36.352623 <6>[ 0.557640] NET: Registered PF_INET protocol family
605 19:00:36.352872 <6>[ 0.563341] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
606 19:00:36.353104 <6>[ 0.572174] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
607 19:00:36.353334 <6>[ 0.581067] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
608 19:00:36.353568 <6>[ 0.589342] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
609 19:00:36.354667 <6>[ 0.597631] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
610 19:00:36.355151 <6>[ 0.605347] TCP: Hash tables configured (established 4096 bind 4096)
611 19:00:36.355539 <6>[ 0.612262] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
612 19:00:36.355965 <6>[ 0.619273] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
613 19:00:36.356379 <6>[ 0.626891] NET: Registered PF_UNIX/PF_LOCAL protocol family
614 19:00:36.356765 <6>[ 0.710562] RPC: Registered named UNIX socket transport module.
615 19:00:36.357139 <6>[ 0.717000] RPC: Registered udp transport module.
616 19:00:36.357520 <6>[ 0.722121] RPC: Registered tcp transport module.
617 19:00:36.357905 <6>[ 0.727227] RPC: Registered tcp-with-tls transport module.
618 19:00:36.358277 <6>[ 0.733156] RPC: Registered tcp NFSv4.1 backchannel transport module.
619 19:00:36.358646 <6>[ 0.740064] PCI: CLS 0 bytes, default 64
620 19:00:36.359026 <5>[ 0.745867] Initialise system trusted keyrings
621 19:00:36.359472 <6>[ 0.765952] Trying to unpack rootfs image as initramfs...
622 19:00:36.412645 <6>[ 0.842218] workingset: timestamp_bits=30 max_order=17 bucket_order=0
623 19:00:36.417397 <6>[ 0.849726] squashfs: version 4.0 (2009/01/31) Phillip Lougher
624 19:00:36.456602 <5>[ 0.892291] NFS: Registering the id_resolver key type
625 19:00:36.462347 <5>[ 0.897878] Key type id_resolver registered
626 19:00:36.468156 <5>[ 0.902547] Key type id_legacy registered
627 19:00:36.476565 <6>[ 0.906987] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
628 19:00:36.483468 <6>[ 0.914178] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
629 19:00:36.552755 <5>[ 0.988505] Key type asymmetric registered
630 19:00:36.558668 <5>[ 0.993091] Asymmetric key parser 'x509' registered
631 19:00:36.570057 <6>[ 0.998515] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
632 19:00:36.570474 <6>[ 1.006430] io scheduler mq-deadline registered
633 19:00:36.575956 <6>[ 1.011360] io scheduler kyber registered
634 19:00:36.581503 <6>[ 1.015849] io scheduler bfq registered
635 19:00:36.685921 <6>[ 1.118067] ledtrig-cpu: registered to indicate activity on CPUs
636 19:00:36.956188 <6>[ 1.387951] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
637 19:00:37.001277 <6>[ 1.436054] msm_serial: driver initialized
638 19:00:37.006556 <6>[ 1.440836] SuperH (H)SCI(F) driver initialized
639 19:00:37.012408 <6>[ 1.446166] STMicroelectronics ASC driver initialized
640 19:00:37.017713 <6>[ 1.451843] STM32 USART driver initialized
641 19:00:37.124239 <6>[ 1.556297] brd: module loaded
642 19:00:37.154132 <6>[ 1.589221] loop: module loaded
643 19:00:37.195730 <6>[ 1.629370] CAN device driver interface
644 19:00:37.201102 <6>[ 1.634645] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
645 19:00:37.208210 <6>[ 1.641694] e1000e: Intel(R) PRO/1000 Network Driver
646 19:00:37.213756 <6>[ 1.647083] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
647 19:00:37.219248 <6>[ 1.653518] igb: Intel(R) Gigabit Ethernet Network Driver
648 19:00:37.226676 <6>[ 1.659341] igb: Copyright (c) 2007-2014 Intel Corporation.
649 19:00:37.238598 <6>[ 1.668538] pegasus: Pegasus/Pegasus II USB Ethernet driver
650 19:00:37.244292 <6>[ 1.674731] usbcore: registered new interface driver pegasus
651 19:00:37.250057 <6>[ 1.680861] usbcore: registered new interface driver asix
652 19:00:37.255863 <6>[ 1.686743] usbcore: registered new interface driver ax88179_178a
653 19:00:37.261727 <6>[ 1.693333] usbcore: registered new interface driver cdc_ether
654 19:00:37.268133 <6>[ 1.699629] usbcore: registered new interface driver smsc75xx
655 19:00:37.273187 <6>[ 1.705860] usbcore: registered new interface driver smsc95xx
656 19:00:37.278971 <6>[ 1.712100] usbcore: registered new interface driver net1080
657 19:00:37.285290 <6>[ 1.718220] usbcore: registered new interface driver cdc_subset
658 19:00:37.290537 <6>[ 1.724628] usbcore: registered new interface driver zaurus
659 19:00:37.298171 <6>[ 1.730677] usbcore: registered new interface driver cdc_ncm
660 19:00:37.308281 <6>[ 1.740132] usbcore: registered new interface driver usb-storage
661 19:00:37.317242 <6>[ 1.751148] i2c_dev: i2c /dev entries driver
662 19:00:37.341446 <5>[ 1.769258] cpuidle: enable-method property 'ti,am3352' found operations
663 19:00:37.347309 <6>[ 1.778731] sdhci: Secure Digital Host Controller Interface driver
664 19:00:37.354777 <6>[ 1.785504] sdhci: Copyright(c) Pierre Ossman
665 19:00:37.361871 <6>[ 1.792062] Synopsys Designware Multimedia Card Interface Driver
666 19:00:37.367356 <6>[ 1.799892] sdhci-pltfm: SDHCI platform and OF driver helper
667 19:00:37.381521 <6>[ 1.809812] usbcore: registered new interface driver usbhid
668 19:00:37.381943 <6>[ 1.815920] usbhid: USB HID core driver
669 19:00:37.394404 <6>[ 1.827571] NET: Registered PF_INET6 protocol family
670 19:00:37.866987 <6>[ 2.302818] Segment Routing with IPv6
671 19:00:37.872703 <6>[ 2.306971] In-situ OAM (IOAM) with IPv6
672 19:00:37.879503 <6>[ 2.311369] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
673 19:00:37.885282 <6>[ 2.318794] NET: Registered PF_PACKET protocol family
674 19:00:37.891091 <6>[ 2.324354] can: controller area network core
675 19:00:37.896888 <6>[ 2.329182] NET: Registered PF_CAN protocol family
676 19:00:37.897242 <6>[ 2.334415] can: raw protocol
677 19:00:37.902670 <6>[ 2.337741] can: broadcast manager protocol
678 19:00:37.909149 <6>[ 2.342338] can: netlink gateway - max_hops=1
679 19:00:37.915270 <5>[ 2.347828] Key type dns_resolver registered
680 19:00:37.921565 <6>[ 2.352903] ThumbEE CPU extension supported.
681 19:00:37.921917 <5>[ 2.357590] Registering SWP/SWPB emulation handler
682 19:00:37.931296 <3>[ 2.363284] omap_voltage_late_init: Voltage driver support not added
683 19:00:38.109179 <5>[ 2.542582] Loading compiled-in X.509 certificates
684 19:00:38.239856 <6>[ 2.662853] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
685 19:00:38.247228 <6>[ 2.679463] pinctrl-single 44e10800.pinmux: 142 pins, size 568
686 19:00:38.273656 <3>[ 2.703358] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
687 19:00:38.481280 <3>[ 2.911082] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
688 19:00:38.688218 <6>[ 3.122235] OMAP GPIO hardware version 0.1
689 19:00:38.708855 <6>[ 3.140920] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
690 19:00:38.802740 <4>[ 3.234601] at24 2-0054: supply vcc not found, using dummy regulator
691 19:00:38.844427 <4>[ 3.276265] at24 2-0055: supply vcc not found, using dummy regulator
692 19:00:38.886002 <4>[ 3.315463] at24 2-0056: supply vcc not found, using dummy regulator
693 19:00:38.923272 <4>[ 3.355190] at24 2-0057: supply vcc not found, using dummy regulator
694 19:00:38.962580 <6>[ 3.395267] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
695 19:00:39.046271 <3>[ 3.474791] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
696 19:00:39.070749 <6>[ 3.495755] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
697 19:00:39.092914 <4>[ 3.522477] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
698 19:00:39.100513 <4>[ 3.531221] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
699 19:00:39.259747 <6>[ 3.691855] omap_rng 48310000.rng: Random Number Generator ver. 20
700 19:00:39.283233 <5>[ 3.718173] random: crng init done
701 19:00:39.331668 <6>[ 3.762317] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
702 19:00:39.365210 <6>[ 3.799443] Freeing initrd memory: 14448K
703 19:00:39.414447 <6>[ 3.844037] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
704 19:00:39.420281 <6>[ 3.854377] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
705 19:00:39.432104 <6>[ 3.861728] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
706 19:00:39.437858 <6>[ 3.869169] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
707 19:00:39.449398 <6>[ 3.877304] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
708 19:00:39.456748 <6>[ 3.888937] cpsw-switch 4a100000.switch: Detected MACID = 78:a5:04:e2:4c:3d
709 19:00:39.469821 <5>[ 3.897956] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
710 19:00:39.497585 <3>[ 3.927810] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
711 19:00:39.503374 <6>[ 3.936400] edma 49000000.dma: TI EDMA DMA engine driver
712 19:00:39.574769 <3>[ 4.004277] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
713 19:00:39.589446 <6>[ 4.018639] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
714 19:00:39.602392 <3>[ 4.035736] l3-aon-clkctrl:0000:0: failed to disable
715 19:00:39.652515 <6>[ 4.082691] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
716 19:00:39.658158 <6>[ 4.092161] printk: legacy console [ttyS0] enabled
717 19:00:39.660943 <6>[ 4.092161] printk: legacy console [ttyS0] enabled
718 19:00:39.666484 <6>[ 4.102489] printk: legacy bootconsole [omap8250] disabled
719 19:00:39.675297 <6>[ 4.102489] printk: legacy bootconsole [omap8250] disabled
720 19:00:39.713069 <4>[ 4.142306] tps65217-pmic: Failed to locate of_node [id: -1]
721 19:00:39.716664 <4>[ 4.149713] tps65217-bl: Failed to locate of_node [id: -1]
722 19:00:39.733159 <6>[ 4.169355] tps65217 0-0024: TPS65217 ID 0xe version 1.2
723 19:00:39.751529 <6>[ 4.176291] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
724 19:00:39.763258 <6>[ 4.189979] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
725 19:00:39.769038 <6>[ 4.201890] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
726 19:00:39.791785 <6>[ 4.222427] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
727 19:00:39.797721 <6>[ 4.231481] sdhci-omap 48060000.mmc: Got CD GPIO
728 19:00:39.805805 <4>[ 4.236701] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
729 19:00:39.820240 <4>[ 4.249875] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
730 19:00:39.826732 <4>[ 4.258799] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
731 19:00:39.836593 <4>[ 4.267580] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
732 19:00:39.935061 <6>[ 4.366654] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
733 19:00:39.960921 <6>[ 4.391498] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
734 19:00:40.000697 <6>[ 4.430483] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
735 19:00:40.007462 <6>[ 4.439401] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
736 19:00:40.051601 <6>[ 4.484632] mmc1: new high speed MMC card at address 0001
737 19:00:40.060234 <6>[ 4.493589] mmcblk1: mmc1:0001 MMC04G 3.60 GiB
738 19:00:40.068525 <6>[ 4.501097] mmc0: new high speed SDHC card at address 1234
739 19:00:40.075532 <6>[ 4.509640] mmcblk0: mmc0:1234 SA32G 29.1 GiB
740 19:00:40.090746 <6>[ 4.524344] mmcblk1boot0: mmc1:0001 MMC04G 2.00 MiB
741 19:00:40.096122 <6>[ 4.532097] mmcblk0: p1
742 19:00:40.109063 <6>[ 4.538350] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
743 19:00:40.116966 <6>[ 4.550588] mmcblk1boot1: mmc1:0001 MMC04G 2.00 MiB
744 19:00:40.130630 <6>[ 4.562985] mmcblk1rpmb: mmc1:0001 MMC04G 128 KiB, chardev (236:0)
745 19:00:42.252631 <6>[ 6.682597] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
746 19:00:42.315968 <5>[ 6.711573] Sending DHCP requests ., OK
747 19:00:42.327222 <6>[ 6.756111] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.12
748 19:00:42.327649 <6>[ 6.764263] IP-Config: Complete:
749 19:00:42.338439 <6>[ 6.767802] device=eth0, hwaddr=78:a5:04:e2:4c:3d, ipaddr=192.168.6.12, mask=255.255.255.0, gw=192.168.6.1
750 19:00:42.344306 <6>[ 6.778348] host=192.168.6.12, domain=, nis-domain=(none)
751 19:00:42.356466 <6>[ 6.784564] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
752 19:00:42.356876 <6>[ 6.784600] nameserver0=10.255.253.1
753 19:00:42.362765 <6>[ 6.797159] clk: Disabling unused clocks
754 19:00:42.368539 <6>[ 6.801905] PM: genpd: Disabling unused power domains
755 19:00:42.387830 <6>[ 6.820357] Freeing unused kernel image (initmem) memory: 2048K
756 19:00:42.395275 <6>[ 6.830133] Run /init as init process
757 19:00:42.418343 Loading, please wait...
758 19:00:42.494180 Starting systemd-udevd version 252.22-1~deb12u1
759 19:00:45.566146 <4>[ 9.994798] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
760 19:00:45.681730 <4>[ 10.110162] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
761 19:00:45.884872 <6>[ 10.320602] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
762 19:00:45.895135 <6>[ 10.326434] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
763 19:00:46.099433 <6>[ 10.534375] hub 1-0:1.0: USB hub found
764 19:00:46.117251 <6>[ 10.551837] hub 1-0:1.0: 1 port detected
765 19:00:46.140554 <6>[ 10.574931] tda998x 0-0070: found TDA19988
766 19:00:49.060064 Begin: Loading essential drivers ... done.
767 19:00:49.065651 Begin: Running /scripts/init-premount ... done.
768 19:00:49.071076 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
769 19:00:49.081466 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
770 19:00:49.090376 Device /sys/class/net/eth0 found
771 19:00:49.090729 done.
772 19:00:49.148941 Begin: Waiting up to 180 secs for any network device to become available ... done.
773 19:00:49.218404 IP-Config: eth0 hardware address 78:a5:04:e2:4c:3d mtu 1500 DHCP
774 19:00:49.271296 IP-Config: eth0 guessed broadcast address 192.168.6.255
775 19:00:49.276873 IP-Config: eth0 complete (dhcp from 192.168.6.1):
776 19:00:49.282474 address: 192.168.6.12 broadcast: 192.168.6.255 netmask: 255.255.255.0
777 19:00:49.291312 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
778 19:00:49.297244 rootserver: 192.168.6.1 rootpath:
779 19:00:49.297595 filename :
780 19:00:49.402302 done.
781 19:00:49.415451 Begin: Running /scripts/nfs-bottom ... done.
782 19:00:49.506096 Begin: Running /scripts/init-bottom ... done.
783 19:00:50.910443 <30>[ 15.340511] systemd[1]: System time before build time, advancing clock.
784 19:00:51.119017 <30>[ 15.525037] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
785 19:00:51.127847 <30>[ 15.561892] systemd[1]: Detected architecture arm.
786 19:00:51.140161
787 19:00:51.140483 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
788 19:00:51.140697
789 19:00:51.170920 <30>[ 15.602228] systemd[1]: Hostname set to <debian-bookworm-armhf>.
790 19:00:53.289024 <30>[ 17.721433] systemd[1]: Queued start job for default target graphical.target.
791 19:00:53.307034 <30>[ 17.736318] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
792 19:00:53.314271 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
793 19:00:53.334223 <30>[ 17.764394] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
794 19:00:53.342783 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
795 19:00:53.364960 <30>[ 17.794887] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
796 19:00:53.373244 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
797 19:00:53.393224 <30>[ 17.823538] systemd[1]: Created slice user.slice - User and Session Slice.
798 19:00:53.399947 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
799 19:00:53.428501 <30>[ 17.853027] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
800 19:00:53.434397 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
801 19:00:53.452320 <30>[ 17.882676] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
802 19:00:53.461701 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
803 19:00:53.490663 <30>[ 17.912597] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
804 19:00:53.502628 <30>[ 17.933116] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
805 19:00:53.507614 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
806 19:00:53.531478 <30>[ 17.962080] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
807 19:00:53.539443 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
808 19:00:53.562167 <30>[ 17.992405] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
809 19:00:53.570678 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
810 19:00:53.592111 <30>[ 18.022572] systemd[1]: Reached target paths.target - Path Units.
811 19:00:53.596151 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
812 19:00:53.621685 <30>[ 18.052228] systemd[1]: Reached target remote-fs.target - Remote File Systems.
813 19:00:53.628204 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
814 19:00:53.651590 <30>[ 18.082136] systemd[1]: Reached target slices.target - Slice Units.
815 19:00:53.656486 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
816 19:00:53.681801 <30>[ 18.112364] systemd[1]: Reached target swap.target - Swaps.
817 19:00:53.685070 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
818 19:00:53.712020 <30>[ 18.142282] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
819 19:00:53.720767 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
820 19:00:53.742947 <30>[ 18.173199] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
821 19:00:53.751474 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
822 19:00:53.832520 <30>[ 18.258101] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
823 19:00:53.845346 <30>[ 18.275489] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
824 19:00:53.853047 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
825 19:00:53.883709 <30>[ 18.313300] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
826 19:00:53.890426 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
827 19:00:53.915199 <30>[ 18.345209] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
828 19:00:53.923325 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
829 19:00:53.951340 <30>[ 18.382442] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
830 19:00:53.962507 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
831 19:00:53.983322 <30>[ 18.412975] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
832 19:00:53.991450 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
833 19:00:54.018277 <30>[ 18.443409] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
834 19:00:54.037632 <30>[ 18.462021] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
835 19:00:54.088227 <30>[ 18.520329] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
836 19:00:54.104133 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
837 19:00:54.170923 <30>[ 18.602795] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
838 19:00:54.196143 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
839 19:00:54.263076 <30>[ 18.693446] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
840 19:00:54.289872 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
841 19:00:54.342607 <30>[ 18.774117] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
842 19:00:54.380035 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
843 19:00:54.432796 <30>[ 18.864310] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
844 19:00:54.459018 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
845 19:00:54.511562 <30>[ 18.943471] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
846 19:00:54.529263 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
847 19:00:54.596008 <30>[ 19.026717] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
848 19:00:54.620311 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
849 19:00:54.671399 <30>[ 19.103392] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
850 19:00:54.691630 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
851 19:00:54.726986 <30>[ 19.158374] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
852 19:00:54.750730 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
853 19:00:54.780453 <28>[ 19.203788] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
854 19:00:54.788151 <28>[ 19.218976] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
855 19:00:54.831607 <30>[ 19.263051] systemd[1]: Starting systemd-journald.service - Journal Service...
856 19:00:54.841872 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
857 19:00:54.921103 <30>[ 19.352897] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
858 19:00:54.933490 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
859 19:00:54.968932 <30>[ 19.399766] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
860 19:00:55.014371 Starting [0;1;39msystemd-network-g… units from Kernel command line...
861 19:00:55.067825 <30>[ 19.498340] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
862 19:00:55.124159 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
863 19:00:55.176103 <30>[ 19.607300] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
864 19:00:55.236626 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
865 19:00:55.306423 <30>[ 19.738530] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
866 19:00:55.374236 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
867 19:00:55.412522 <30>[ 19.843986] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
868 19:00:55.434928 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
869 19:00:55.465727 <30>[ 19.896218] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
870 19:00:55.487386 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
871 19:00:55.635170 <30>[ 20.066916] systemd[1]: modprobe@configfs.service: Deactivated successfully.
872 19:00:55.671384 <30>[ 20.103161] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
873 19:00:55.700867 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
874 19:00:55.721418 <30>[ 20.154431] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
875 19:00:55.761676 <30>[ 20.193220] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
876 19:00:55.790582 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
877 19:00:55.812909 <30>[ 20.243256] systemd[1]: Started systemd-journald.service - Journal Service.
878 19:00:55.819092 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
879 19:00:55.862638 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
880 19:00:55.893902 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
881 19:00:55.922009 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
882 19:00:55.947134 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
883 19:00:55.973254 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
884 19:00:56.003426 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
885 19:00:56.024241 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
886 19:00:56.055795 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
887 19:00:56.123954 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
888 19:00:56.172730 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
889 19:00:56.236199 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
890 19:00:56.335234 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
891 19:00:56.439208 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
892 19:00:56.531063 <46>[ 20.962385] systemd-journald[163]: Received client request to flush runtime journal.
893 19:00:56.550032 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
894 19:00:56.626243 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
895 19:00:57.507169 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
896 19:00:57.900804 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
897 19:00:57.943613 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
898 19:00:58.310815 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
899 19:00:58.503109 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
900 19:00:58.522923 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
901 19:00:58.541841 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
902 19:00:58.601685 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
903 19:00:58.659178 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
904 19:00:59.571671 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
905 19:00:59.648929 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
906 19:00:59.919270 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
907 19:01:00.031474 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
908 19:01:00.111467 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
909 19:01:02.143119 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
910 19:01:02.465056 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
911 19:01:02.622783 <5>[ 27.054523] cfg80211: Loading compiled-in X.509 certificates for regulatory database
912 19:01:03.605211 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
913 19:01:04.260379 <5>[ 28.694251] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
914 19:01:04.326208 <5>[ 28.758524] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
915 19:01:04.339769 <4>[ 28.771213] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
916 19:01:04.345648 <6>[ 28.780342] cfg80211: failed to load regulatory.db
917 19:01:05.016555 <46>[ 29.439237] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
918 19:01:05.129263 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
919 19:01:05.181396 <46>[ 29.606264] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
920 19:01:05.465109 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
921 19:01:13.988593 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
922 19:01:14.010766 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
923 19:01:14.035454 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
924 19:01:14.067798 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
925 19:01:14.135589 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
926 19:01:14.183595 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
927 19:01:14.224281 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
928 19:01:14.290739 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
929 19:01:14.342511 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
930 19:01:14.369797 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
931 19:01:14.395647 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
932 19:01:14.436272 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
933 19:01:14.464208 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
934 19:01:14.511697 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
935 19:01:14.535077 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
936 19:01:14.573443 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
937 19:01:14.614984 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
938 19:01:14.646756 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
939 19:01:14.676990 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
940 19:01:14.701273 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
941 19:01:14.731112 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
942 19:01:14.751294 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
943 19:01:14.777889 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
944 19:01:14.851761 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
945 19:01:14.901806 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
946 19:01:14.976135 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
947 19:01:15.072523 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
948 19:01:15.141090 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
949 19:01:15.190127 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
950 19:01:15.222277 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
951 19:01:15.430512 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
952 19:01:15.491790 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
953 19:01:15.553759 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
954 19:01:15.581218 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
955 19:01:15.602611 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
956 19:01:15.798290 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
957 19:01:16.180698 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
958 19:01:16.228099 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
959 19:01:16.255185 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
960 19:01:16.347644 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
961 19:01:16.512089 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
962 19:01:16.642001
963 19:01:16.645308 Debian GNU/Linux 12 dworm-armhf login: root (automatic login)
964 19:01:16.645832
965 19:01:17.024491 Linux debian-bookworm-armhf 6.12.0-rc7 #1 SMP Mon Nov 11 18:16:08 UTC 2024 armv7l
966 19:01:17.025148
967 19:01:17.030016 The programs included with the Debian GNU/Linux system are free software;
968 19:01:17.035722 the exact distribution terms for each program are described in the
969 19:01:17.041315 individual files in /usr/share/doc/*/copyright.
970 19:01:17.041891
971 19:01:17.049211 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
972 19:01:17.049755 permitted by applicable law.
973 19:01:21.722132 Unable to match end of the kernel message
975 19:01:21.723798 Setting prompt string to ['/ #']
976 19:01:21.724466 end: 2.4.4.1 login-action (duration 00:00:47) [common]
978 19:01:21.725960 end: 2.4.4 auto-login-action (duration 00:00:47) [common]
979 19:01:21.726537 start: 2.4.5 expect-shell-connection (timeout 00:03:15) [common]
980 19:01:21.727002 Setting prompt string to ['/ #']
981 19:01:21.727443 Forcing a shell prompt, looking for ['/ #']
983 19:01:21.778539 / #
984 19:01:21.779027 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
985 19:01:21.779316 Waiting using forced prompt support (timeout 00:02:30)
986 19:01:21.782648
987 19:01:21.787617 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
988 19:01:21.788021 start: 2.4.6 export-device-env (timeout 00:03:15) [common]
989 19:01:21.788336 Sending with 10 millisecond of delay
991 19:01:26.776710 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/976601/extract-nfsrootfs-70gq04xx'
992 19:01:26.788172 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/976601/extract-nfsrootfs-70gq04xx'
993 19:01:26.789112 Sending with 10 millisecond of delay
995 19:01:28.893743 / # export NFS_SERVER_IP='192.168.6.2'
996 19:01:28.905815 export NFS_SERVER_IP='192.168.6.2'
997 19:01:28.906880 end: 2.4.6 export-device-env (duration 00:00:07) [common]
998 19:01:28.907464 end: 2.4 uboot-commands (duration 00:01:52) [common]
999 19:01:28.908084 end: 2 uboot-action (duration 00:01:52) [common]
1000 19:01:28.908650 start: 3 lava-test-retry (timeout 00:06:57) [common]
1001 19:01:28.908999 start: 3.1 lava-test-shell (timeout 00:06:57) [common]
1002 19:01:28.909245 Using namespace: common
1004 19:01:29.009977 / # #
1005 19:01:29.010554 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1006 19:01:29.014345 #
1007 19:01:29.023183 Using /lava-976601
1009 19:01:29.124191 / # export SHELL=/bin/bash
1010 19:01:29.128838 export SHELL=/bin/bash
1012 19:01:29.236918 / # . /lava-976601/environment
1013 19:01:29.242500 . /lava-976601/environment
1015 19:01:29.356739 / # /lava-976601/bin/lava-test-runner /lava-976601/0
1016 19:01:29.357571 Test shell timeout: 10s (minimum of the action and connection timeout)
1017 19:01:29.362398 /lava-976601/bin/lava-test-runner /lava-976601/0
1018 19:01:29.813383 + export TESTRUN_ID=0_timesync-off
1019 19:01:29.821238 + TESTRUN_ID=0_timesync-off
1020 19:01:29.821592 + cd /lava-976601/0/tests/0_timesync-off
1021 19:01:29.821814 ++ cat uuid
1022 19:01:29.836818 + UUID=976601_1.6.2.4.1
1023 19:01:29.837131 + set +x
1024 19:01:29.845328 <LAVA_SIGNAL_STARTRUN 0_timesync-off 976601_1.6.2.4.1>
1025 19:01:29.845655 + systemctl stop systemd-timesyncd
1026 19:01:29.846128 Received signal: <STARTRUN> 0_timesync-off 976601_1.6.2.4.1
1027 19:01:29.846381 Starting test lava.0_timesync-off (976601_1.6.2.4.1)
1028 19:01:29.846680 Skipping test definition patterns.
1029 19:01:30.151827 + set +x
1030 19:01:30.152305 <LAVA_SIGNAL_ENDRUN 0_timesync-off 976601_1.6.2.4.1>
1031 19:01:30.152768 Received signal: <ENDRUN> 0_timesync-off 976601_1.6.2.4.1
1032 19:01:30.153082 Ending use of test pattern.
1033 19:01:30.153310 Ending test lava.0_timesync-off (976601_1.6.2.4.1), duration 0.31
1035 19:01:30.348954 + export TESTRUN_ID=1_kselftest-dt
1036 19:01:30.357078 + TESTRUN_ID=1_kselftest-dt
1037 19:01:30.357439 + cd /lava-976601/0/tests/1_kselftest-dt
1038 19:01:30.357664 ++ cat uuid
1039 19:01:30.373171 + UUID=976601_1.6.2.4.5
1040 19:01:30.373533 + set +x
1041 19:01:30.378564 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 976601_1.6.2.4.5>
1042 19:01:30.378924 + cd ./automated/linux/kselftest/
1043 19:01:30.379390 Received signal: <STARTRUN> 1_kselftest-dt 976601_1.6.2.4.5
1044 19:01:30.379646 Starting test lava.1_kselftest-dt (976601_1.6.2.4.5)
1045 19:01:30.379924 Skipping test definition patterns.
1046 19:01:30.405698 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/pm/testing/v6.12-rc7-108-g7b04a3bdf53e/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g pm -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1047 19:01:30.511793 INFO: install_deps skipped
1048 19:01:31.075933 --2024-11-11 19:01:31-- http://storage.kernelci.org/pm/testing/v6.12-rc7-108-g7b04a3bdf53e/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1049 19:01:31.099529 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1050 19:01:31.242688 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1051 19:01:31.390923 HTTP request sent, awaiting response... 200 OK
1052 19:01:31.391343 Length: 4107632 (3.9M) [application/octet-stream]
1053 19:01:31.396418 Saving to: 'kselftest_armhf.tar.gz'
1054 19:01:31.396732
1055 19:01:33.045135
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 178KB/s
kselftest_armhf.tar 4%[ ] 194.76K 337KB/s
kselftest_armhf.tar 16%[==> ] 652.76K 821KB/s
kselftest_armhf.tar 25%[====> ] 1013K 943KB/s
kselftest_armhf.tar 59%[==========> ] 2.33M 1.75MB/s
kselftest_armhf.tar 87%[================> ] 3.43M 2.22MB/s
kselftest_armhf.tar 100%[===================>] 3.92M 2.38MB/s in 1.6s
1056 19:01:33.045554
1057 19:01:33.538978 2024-11-11 19:01:33 (2.38 MB/s) - 'kselftest_armhf.tar.gz' saved [4107632/4107632]
1058 19:01:33.539400
1059 19:01:46.639689 skiplist:
1060 19:01:46.640322 ========================================
1061 19:01:46.645274 ========================================
1062 19:01:46.742348 dt:test_unprobed_devices.sh
1063 19:01:46.775756 ============== Tests to run ===============
1064 19:01:46.783852 dt:test_unprobed_devices.sh
1065 19:01:46.787829 ===========End Tests to run ===============
1066 19:01:46.795834 shardfile-dt pass
1067 19:01:47.023786 <12>[ 71.461242] kselftest: Running tests in dt
1068 19:01:47.062778 TAP version 13
1069 19:01:47.087537 1..1
1070 19:01:47.140961 # timeout set to 45
1071 19:01:47.141393 # selftests: dt: test_unprobed_devices.sh
1072 19:01:47.961402 # TAP version 13
1073 19:02:12.940793 # 1..257
1074 19:02:13.120398 # ok 1 / # SKIP
1075 19:02:13.148352 # ok 2 /clk_mcasp0
1076 19:02:13.220331 # ok 3 /clk_mcasp0_fixed # SKIP
1077 19:02:13.290259 # ok 4 /cpus/cpu@0 # SKIP
1078 19:02:13.357669 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1079 19:02:13.378167 # ok 6 /fixedregulator0
1080 19:02:13.399186 # ok 7 /leds
1081 19:02:13.419525 # ok 8 /ocp
1082 19:02:13.443791 # ok 9 /ocp/interconnect@44c00000
1083 19:02:13.471025 # ok 10 /ocp/interconnect@44c00000/segment@0
1084 19:02:13.489172 # ok 11 /ocp/interconnect@44c00000/segment@100000
1085 19:02:13.518662 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1086 19:02:13.588915 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1087 19:02:13.609605 # ok 14 /ocp/interconnect@44c00000/segment@200000
1088 19:02:13.629526 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1089 19:02:13.734908 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1090 19:02:13.811015 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1091 19:02:13.877607 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1092 19:02:13.947742 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1093 19:02:14.023434 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1094 19:02:14.093817 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1095 19:02:14.165123 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1096 19:02:14.237102 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1097 19:02:14.306889 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1098 19:02:14.382744 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1099 19:02:14.464360 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1100 19:02:14.555182 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1101 19:02:14.629541 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1102 19:02:14.697558 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1103 19:02:14.768667 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1104 19:02:14.840750 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1105 19:02:14.911965 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1106 19:02:14.984212 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1107 19:02:15.055017 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1108 19:02:15.127872 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1109 19:02:15.198092 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1110 19:02:15.269884 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1111 19:02:15.341522 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1112 19:02:15.411883 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1113 19:02:15.482397 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1114 19:02:15.553031 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1115 19:02:15.624738 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1116 19:02:15.697307 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1117 19:02:15.769213 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1118 19:02:15.842622 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1119 19:02:15.914822 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1120 19:02:15.985796 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1121 19:02:16.061227 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1122 19:02:16.129332 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1123 19:02:16.200630 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1124 19:02:16.273522 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1125 19:02:16.351058 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1126 19:02:16.433666 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1127 19:02:16.502057 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1128 19:02:16.574145 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1129 19:02:16.647866 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1130 19:02:16.718547 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1131 19:02:16.791526 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1132 19:02:16.861804 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1133 19:02:16.932690 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1134 19:02:17.003652 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1135 19:02:17.076538 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1136 19:02:17.148098 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1137 19:02:17.242743 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1138 19:02:17.302701 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1139 19:02:17.376723 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1140 19:02:17.445588 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1141 19:02:17.519458 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1142 19:02:17.592798 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1143 19:02:17.667489 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1144 19:02:17.737660 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1145 19:02:17.809926 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1146 19:02:17.880291 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1147 19:02:17.953705 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1148 19:02:18.031600 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1149 19:02:18.106516 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1150 19:02:18.184279 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1151 19:02:18.257356 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1152 19:02:18.327288 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1153 19:02:18.401459 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1154 19:02:18.468975 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1155 19:02:18.539887 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1156 19:02:18.611305 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1157 19:02:18.682291 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1158 19:02:18.753759 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1159 19:02:18.825570 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1160 19:02:18.901164 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1161 19:02:18.972603 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1162 19:02:19.045556 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1163 19:02:19.117348 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1164 19:02:19.185344 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1165 19:02:19.255412 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1166 19:02:19.326609 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1167 19:02:19.399051 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1168 19:02:19.419435 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1169 19:02:19.442968 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1170 19:02:19.466940 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1171 19:02:19.490310 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1172 19:02:19.513652 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1173 19:02:19.542562 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1174 19:02:19.565078 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1175 19:02:19.588909 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1176 19:02:19.694876 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1177 19:02:19.716503 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1178 19:02:19.740725 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1179 19:02:19.763938 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1180 19:02:19.869084 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1181 19:02:19.943946 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1182 19:02:20.014981 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1183 19:02:20.086854 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1184 19:02:20.163017 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1185 19:02:20.231254 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1186 19:02:20.302671 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1187 19:02:20.375619 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1188 19:02:20.449817 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1189 19:02:20.520389 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1190 19:02:20.592828 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1191 19:02:20.663701 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1192 19:02:20.734629 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1193 19:02:20.814217 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1194 19:02:20.886776 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1195 19:02:20.962042 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1196 19:02:20.983557 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1197 19:02:21.055569 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1198 19:02:21.127257 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1199 19:02:21.201619 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1200 19:02:21.230214 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1201 19:02:21.302884 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1202 19:02:21.324179 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1203 19:02:21.401961 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1204 19:02:21.424075 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1205 19:02:21.453319 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1206 19:02:21.470886 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1207 19:02:21.501241 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1208 19:02:21.523512 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1209 19:02:21.544396 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1210 19:02:21.570268 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1211 19:02:21.647658 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1212 19:02:21.665440 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1213 19:02:21.688414 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1214 19:02:21.763816 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1215 19:02:21.834472 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1216 19:02:21.855628 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1217 19:02:21.957439 # not ok 144 /ocp/interconnect@47c00000
1218 19:02:22.041841 # not ok 145 /ocp/interconnect@47c00000/segment@0
1219 19:02:22.062613 # ok 146 /ocp/interconnect@48000000
1220 19:02:22.089363 # ok 147 /ocp/interconnect@48000000/segment@0
1221 19:02:22.113698 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1222 19:02:22.133081 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1223 19:02:22.160518 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1224 19:02:22.183594 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1225 19:02:22.201770 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1226 19:02:22.227266 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1227 19:02:22.249918 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1228 19:02:22.322288 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1229 19:02:22.400978 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1230 19:02:22.422964 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1231 19:02:22.443255 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1232 19:02:22.469961 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1233 19:02:22.494205 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1234 19:02:22.513523 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1235 19:02:22.540567 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1236 19:02:22.562831 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1237 19:02:22.584253 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1238 19:02:22.605288 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1239 19:02:22.633265 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1240 19:02:22.653545 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1241 19:02:22.680423 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1242 19:02:22.702748 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1243 19:02:22.724211 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1244 19:02:22.744655 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1245 19:02:22.773818 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1246 19:02:22.793588 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1247 19:02:22.816734 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1248 19:02:22.836807 # ok 175 /ocp/interconnect@48000000/segment@100000
1249 19:02:22.861545 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1250 19:02:22.890383 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1251 19:02:22.963873 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1252 19:02:23.037585 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1253 19:02:23.105479 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1254 19:02:23.177651 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1255 19:02:23.247420 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1256 19:02:23.326052 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1257 19:02:23.395731 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1258 19:02:23.466592 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1259 19:02:23.489619 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1260 19:02:23.506952 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1261 19:02:23.529809 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1262 19:02:23.556822 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1263 19:02:23.581946 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1264 19:02:23.604643 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1265 19:02:23.625655 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1266 19:02:23.654539 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1267 19:02:23.680796 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1268 19:02:23.697155 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1269 19:02:23.721144 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1270 19:02:23.745422 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1271 19:02:23.765886 # ok 198 /ocp/interconnect@48000000/segment@200000
1272 19:02:23.793481 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1273 19:02:23.864700 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1274 19:02:23.882884 # ok 201 /ocp/interconnect@48000000/segment@300000
1275 19:02:23.908058 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1276 19:02:23.931606 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1277 19:02:23.960475 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1278 19:02:23.983021 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1279 19:02:24.003748 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1280 19:02:24.025812 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1281 19:02:24.097814 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1282 19:02:24.120145 # ok 209 /ocp/interconnect@4a000000
1283 19:02:24.141666 # ok 210 /ocp/interconnect@4a000000/segment@0
1284 19:02:24.170288 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1285 19:02:24.193611 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1286 19:02:24.221529 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1287 19:02:24.243551 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1288 19:02:24.315673 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1289 19:02:24.432468 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1290 19:02:24.508646 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1291 19:02:24.614515 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1292 19:02:24.685770 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1293 19:02:24.754128 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1294 19:02:24.852944 # not ok 221 /ocp/interconnect@4b140000
1295 19:02:24.924473 # not ok 222 /ocp/interconnect@4b140000/segment@0
1296 19:02:24.999339 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1297 19:02:25.020981 # ok 224 /ocp/target-module@40300000
1298 19:02:25.040849 # ok 225 /ocp/target-module@40300000/sram@0
1299 19:02:25.119663 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1300 19:02:25.192046 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1301 19:02:25.210907 # ok 228 /ocp/target-module@47400000
1302 19:02:25.231822 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1303 19:02:25.257823 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1304 19:02:25.279479 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1305 19:02:25.298040 # ok 232 /ocp/target-module@47400000/usb@1400
1306 19:02:25.321736 # ok 233 /ocp/target-module@47400000/usb@1800
1307 19:02:25.346588 # ok 234 /ocp/target-module@47810000
1308 19:02:25.368555 # ok 235 /ocp/target-module@49000000
1309 19:02:25.391666 # ok 236 /ocp/target-module@49000000/dma@0
1310 19:02:25.409925 # ok 237 /ocp/target-module@49800000
1311 19:02:25.433221 # ok 238 /ocp/target-module@49800000/dma@0
1312 19:02:25.457942 # ok 239 /ocp/target-module@49900000
1313 19:02:25.481571 # ok 240 /ocp/target-module@49900000/dma@0
1314 19:02:25.498436 # ok 241 /ocp/target-module@49a00000
1315 19:02:25.525923 # ok 242 /ocp/target-module@49a00000/dma@0
1316 19:02:25.547429 # ok 243 /ocp/target-module@4c000000
1317 19:02:25.619362 # not ok 244 /ocp/target-module@4c000000/emif@0
1318 19:02:25.637048 # ok 245 /ocp/target-module@50000000
1319 19:02:25.661092 # ok 246 /ocp/target-module@53100000
1320 19:02:25.730712 # not ok 247 /ocp/target-module@53100000/sham@0
1321 19:02:25.756249 # ok 248 /ocp/target-module@53500000
1322 19:02:25.830986 # not ok 249 /ocp/target-module@53500000/aes@0
1323 19:02:25.849930 # ok 250 /ocp/target-module@56000000
1324 19:02:25.958212 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1325 19:02:26.026798 # ok 252 /opp-table # SKIP
1326 19:02:26.092278 # ok 253 /soc # SKIP
1327 19:02:26.116934 # ok 254 /sound
1328 19:02:26.135421 # ok 255 /target-module@4b000000
1329 19:02:26.160383 # ok 256 /target-module@4b000000/target-module@140000
1330 19:02:26.180757 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1331 19:02:26.188313 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1332 19:02:26.197922 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1333 19:02:28.535035 dt_test_unprobed_devices_sh_ skip
1334 19:02:28.540338 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1335 19:02:28.546196 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1336 19:02:28.546772 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1337 19:02:28.555004 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1338 19:02:28.555475 dt_test_unprobed_devices_sh_fixedregulator0 pass
1339 19:02:28.560515 dt_test_unprobed_devices_sh_leds pass
1340 19:02:28.566142 dt_test_unprobed_devices_sh_ocp pass
1341 19:02:28.569602 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1342 19:02:28.575234 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1343 19:02:28.580883 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1344 19:02:28.589803 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1345 19:02:28.600915 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1346 19:02:28.606567 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1347 19:02:28.615500 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1348 19:02:28.621118 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1349 19:02:28.632324 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1350 19:02:28.637947 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1351 19:02:28.649140 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1352 19:02:28.660305 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1353 19:02:28.671535 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1354 19:02:28.683481 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1355 19:02:28.694076 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1356 19:02:28.699624 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1357 19:02:28.710721 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1358 19:02:28.722007 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1359 19:02:28.733159 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1360 19:02:28.738779 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1361 19:02:28.749910 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1362 19:02:28.761115 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1363 19:02:28.772304 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1364 19:02:28.777931 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1365 19:02:28.789043 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1366 19:02:28.800310 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1367 19:02:28.811486 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1368 19:02:28.817070 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1369 19:02:28.828245 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1370 19:02:28.844279 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1371 19:02:28.850665 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1372 19:02:28.861782 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1373 19:02:28.873122 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1374 19:02:28.884239 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1375 19:02:28.895371 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1376 19:02:28.906589 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1377 19:02:28.917826 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1378 19:02:28.928970 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1379 19:02:28.940191 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1380 19:02:28.951275 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1381 19:02:28.962482 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1382 19:02:28.973687 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1383 19:02:28.984867 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1384 19:02:28.996135 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1385 19:02:29.007261 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1386 19:02:29.018419 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1387 19:02:29.029613 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1388 19:02:29.040807 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1389 19:02:29.052080 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1390 19:02:29.063200 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1391 19:02:29.074361 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1392 19:02:29.085539 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1393 19:02:29.091219 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1394 19:02:29.102514 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1395 19:02:29.113561 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1396 19:02:29.124745 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1397 19:02:29.135962 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1398 19:02:29.149446 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1399 19:02:29.158762 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1400 19:02:29.177352 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1401 19:02:29.181829 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1402 19:02:29.191907 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1403 19:02:29.203156 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1404 19:02:29.214259 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1405 19:02:29.225897 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1406 19:02:29.236707 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1407 19:02:29.247937 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1408 19:02:29.253481 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1409 19:02:29.264663 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1410 19:02:29.275796 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1411 19:02:29.287038 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1412 19:02:29.298087 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1413 19:02:29.309262 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1414 19:02:29.320611 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1415 19:02:29.331764 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1416 19:02:29.342918 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1417 19:02:29.354108 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1418 19:02:29.359656 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1419 19:02:29.370873 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1420 19:02:29.382006 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1421 19:02:29.393287 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1422 19:02:29.404524 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1423 19:02:29.415630 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1424 19:02:29.426811 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1425 19:02:29.438144 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1426 19:02:29.449209 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1427 19:02:29.460378 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1428 19:02:29.471612 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1429 19:02:29.477185 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1430 19:02:29.488366 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1431 19:02:29.499523 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1432 19:02:29.505159 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1433 19:02:29.516347 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1434 19:02:29.527547 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1435 19:02:29.533143 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1436 19:02:29.544326 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1437 19:02:29.555512 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1438 19:02:29.561142 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1439 19:02:29.572320 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1440 19:02:29.583458 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1441 19:02:29.594713 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1442 19:02:29.611500 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1443 19:02:29.622644 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1444 19:02:29.633852 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1445 19:02:29.645044 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1446 19:02:29.656235 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1447 19:02:29.667376 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1448 19:02:29.678589 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1449 19:02:29.689792 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1450 19:02:29.706553 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1451 19:02:29.717763 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1452 19:02:29.728942 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1453 19:02:29.740152 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1454 19:02:29.756926 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1455 19:02:29.768135 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1456 19:02:29.779327 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1457 19:02:29.784889 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1458 19:02:29.796125 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1459 19:02:29.801693 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1460 19:02:29.812896 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1461 19:02:29.818536 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1462 19:02:29.829792 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1463 19:02:29.835345 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1464 19:02:29.846455 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1465 19:02:29.852183 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1466 19:02:29.863274 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1467 19:02:29.868814 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1468 19:02:29.880092 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1469 19:02:29.891263 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1470 19:02:29.902446 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1471 19:02:29.913666 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1472 19:02:29.919318 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1473 19:02:29.930341 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1474 19:02:29.941584 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1475 19:02:29.947167 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1476 19:02:29.952777 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1477 19:02:29.958349 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1478 19:02:29.963922 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1479 19:02:29.969529 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1480 19:02:29.980737 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1481 19:02:29.986319 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1482 19:02:29.997520 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1483 19:02:30.003105 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1484 19:02:30.014332 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1485 19:02:30.019932 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1486 19:02:30.025478 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1487 19:02:30.036689 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1488 19:02:30.042274 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1489 19:02:30.053478 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1490 19:02:30.059134 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1491 19:02:30.070226 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1492 19:02:30.075856 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1493 19:02:30.087032 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1494 19:02:30.092648 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1495 19:02:30.103804 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1496 19:02:30.109415 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1497 19:02:30.120633 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1498 19:02:30.126190 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1499 19:02:30.131837 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1500 19:02:30.142998 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1501 19:02:30.148588 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1502 19:02:30.159759 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1503 19:02:30.165356 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1504 19:02:30.176556 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1505 19:02:30.182174 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1506 19:02:30.193336 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1507 19:02:30.198938 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1508 19:02:30.210110 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1509 19:02:30.215711 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1510 19:02:30.226880 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1511 19:02:30.238110 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1512 19:02:30.249259 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1513 19:02:30.260483 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1514 19:02:30.271649 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1515 19:02:30.282857 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1516 19:02:30.294054 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1517 19:02:30.305293 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1518 19:02:30.310953 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1519 19:02:30.322167 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1520 19:02:30.327694 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1521 19:02:30.333406 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1522 19:02:30.344841 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1523 19:02:30.356168 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1524 19:02:30.361503 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1525 19:02:30.372691 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1526 19:02:30.378345 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1527 19:02:30.389514 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1528 19:02:30.395814 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1529 19:02:30.406337 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1530 19:02:30.411917 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1531 19:02:30.417533 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1532 19:02:30.429767 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1533 19:02:30.434389 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1534 19:02:30.440051 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1535 19:02:30.451158 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1536 19:02:30.456697 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1537 19:02:30.467878 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1538 19:02:30.473434 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1539 19:02:30.484705 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1540 19:02:30.490309 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1541 19:02:30.495889 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1542 19:02:30.501448 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1543 19:02:30.512769 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1544 19:02:30.518290 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1545 19:02:30.529413 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1546 19:02:30.540770 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1547 19:02:30.546122 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1548 19:02:30.557319 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1549 19:02:30.568623 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1550 19:02:30.579841 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1551 19:02:30.585338 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1552 19:02:30.596573 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1553 19:02:30.602275 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1554 19:02:30.607760 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1555 19:02:30.613396 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1556 19:02:30.618999 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1557 19:02:30.624649 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1558 19:02:30.630256 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1559 19:02:30.641495 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1560 19:02:30.647023 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1561 19:02:30.652676 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1562 19:02:30.658259 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1563 19:02:30.663847 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1564 19:02:30.669463 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1565 19:02:30.675006 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1566 19:02:30.680622 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1567 19:02:30.686238 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1568 19:02:30.691800 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1569 19:02:30.697483 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1570 19:02:30.702996 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1571 19:02:30.708893 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1572 19:02:30.714268 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1573 19:02:30.720071 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1574 19:02:30.725551 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1575 19:02:30.731132 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1576 19:02:30.736777 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1577 19:02:30.742347 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1578 19:02:30.747972 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1579 19:02:30.753532 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1580 19:02:30.759128 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1581 19:02:30.764745 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1582 19:02:30.770394 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1583 19:02:30.775950 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1584 19:02:30.781550 dt_test_unprobed_devices_sh_opp-table skip
1585 19:02:30.787162 dt_test_unprobed_devices_sh_soc skip
1586 19:02:30.787749 dt_test_unprobed_devices_sh_sound pass
1587 19:02:30.792742 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1588 19:02:30.798434 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1589 19:02:30.809534 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1590 19:02:30.810139 dt_test_unprobed_devices_sh fail
1591 19:02:30.815142 + ../../utils/send-to-lava.sh ./output/result.txt
1592 19:02:30.820738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1593 19:02:30.821745 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1595 19:02:30.827797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1596 19:02:30.828716 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1598 19:02:30.902797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1599 19:02:30.903742 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1601 19:02:30.993626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1602 19:02:30.994583 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1604 19:02:31.083974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1605 19:02:31.084955 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1607 19:02:31.185935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1608 19:02:31.187332 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1610 19:02:31.277704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1611 19:02:31.278638 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1613 19:02:31.361716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1614 19:02:31.362637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1616 19:02:31.453328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1617 19:02:31.454245 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1619 19:02:31.546809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1620 19:02:31.547463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1622 19:02:31.641078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1623 19:02:31.641751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1625 19:02:31.726690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1626 19:02:31.727325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1628 19:02:31.815734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1629 19:02:31.816394 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1631 19:02:31.902440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1632 19:02:31.903168 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1634 19:02:31.992840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1635 19:02:31.993599 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1637 19:02:32.086228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1638 19:02:32.086976 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1640 19:02:32.183960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1641 19:02:32.184891 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1643 19:02:32.274813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1644 19:02:32.275527 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1646 19:02:32.368275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1647 19:02:32.369261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1649 19:02:32.455874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1650 19:02:32.456591 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1652 19:02:32.549853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1653 19:02:32.550548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1655 19:02:32.633907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1656 19:02:32.634585 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1658 19:02:32.725125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1659 19:02:32.725781 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1661 19:02:32.833500 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1662 19:02:32.834233 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1664 19:02:32.920362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1665 19:02:32.921141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1667 19:02:33.015378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1668 19:02:33.017002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1670 19:02:33.107757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1671 19:02:33.108465 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1673 19:02:33.193330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1674 19:02:33.193984 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1676 19:02:33.277731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1677 19:02:33.278453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1679 19:02:33.370606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1680 19:02:33.371266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1682 19:02:33.463910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1683 19:02:33.464603 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1685 19:02:33.558374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1686 19:02:33.559058 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1688 19:02:33.648781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1689 19:02:33.649477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1691 19:02:33.740756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1692 19:02:33.741406 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1694 19:02:33.831046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1695 19:02:33.831696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1697 19:02:33.933437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1698 19:02:33.934057 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1700 19:02:34.017973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1701 19:02:34.018588 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1703 19:02:34.104726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1704 19:02:34.105329 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1706 19:02:34.197339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1707 19:02:34.197969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1709 19:02:34.290072 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1710 19:02:34.290694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1712 19:02:34.374161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1713 19:02:34.374804 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1715 19:02:34.458035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1716 19:02:34.458665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1718 19:02:34.543474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1719 19:02:34.544127 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1721 19:02:34.629049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1722 19:02:34.629679 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1724 19:02:34.714919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1725 19:02:34.715563 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1727 19:02:34.800121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1728 19:02:34.800720 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1730 19:02:34.895565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1731 19:02:34.896175 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1733 19:02:34.982256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1734 19:02:34.982873 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1736 19:02:35.074269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1737 19:02:35.074915 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1739 19:02:35.166241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1740 19:02:35.166836 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1742 19:02:35.253381 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1743 19:02:35.253978 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1745 19:02:35.344707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1746 19:02:35.345395 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1748 19:02:35.428623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1749 19:02:35.429316 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1751 19:02:35.510844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1752 19:02:35.511911 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1754 19:02:35.595809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1755 19:02:35.596466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1757 19:02:35.682409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1758 19:02:35.683064 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1760 19:02:35.774913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1761 19:02:35.775574 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1763 19:02:35.860759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1764 19:02:35.861429 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1766 19:02:35.946369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1767 19:02:35.947068 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1769 19:02:36.039434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1770 19:02:36.040117 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1772 19:02:36.132887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1773 19:02:36.133541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1775 19:02:36.224391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1776 19:02:36.225026 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1778 19:02:36.316115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1779 19:02:36.316747 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1781 19:02:36.399298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1782 19:02:36.399930 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1784 19:02:36.488937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1785 19:02:36.489574 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1787 19:02:36.589226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1788 19:02:36.589870 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1790 19:02:36.680506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1791 19:02:36.681157 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1793 19:02:36.773574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1794 19:02:36.774220 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1796 19:02:36.865773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1797 19:02:36.866396 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1799 19:02:36.952119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1800 19:02:36.952784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1802 19:02:37.043774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1803 19:02:37.044568 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1805 19:02:37.133556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1806 19:02:37.134186 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1808 19:02:37.226446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1809 19:02:37.227076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1811 19:02:37.311654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1812 19:02:37.312327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1814 19:02:37.402639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1815 19:02:37.403551 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1817 19:02:37.486335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1818 19:02:37.487197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1820 19:02:37.571467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1821 19:02:37.572295 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1823 19:02:37.663851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1824 19:02:37.664564 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1826 19:02:37.755070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1827 19:02:37.755735 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1829 19:02:37.839483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1830 19:02:37.840449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1832 19:02:37.930637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1833 19:02:37.931431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1835 19:02:38.024838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1836 19:02:38.025698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1838 19:02:38.114323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1839 19:02:38.115143 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1841 19:02:38.203788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1842 19:02:38.204615 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1844 19:02:38.288832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1845 19:02:38.289618 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1847 19:02:38.378398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1848 19:02:38.379221 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1850 19:02:38.461391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1851 19:02:38.462199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1853 19:02:38.546547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1854 19:02:38.547331 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1856 19:02:38.630991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1857 19:02:38.631790 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1859 19:02:38.718913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1860 19:02:38.719713 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1862 19:02:38.810868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1863 19:02:38.811706 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1865 19:02:38.901185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1866 19:02:38.902020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1868 19:02:38.994043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1869 19:02:38.994872 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1871 19:02:39.085022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1872 19:02:39.085852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1874 19:02:39.171296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1875 19:02:39.172101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1877 19:02:39.254183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1878 19:02:39.254963 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1880 19:02:39.344780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1881 19:02:39.345665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1883 19:02:39.427634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1884 19:02:39.428523 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1886 19:02:39.520380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1887 19:02:39.521229 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1889 19:02:39.612345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1890 19:02:39.613165 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1892 19:02:39.702775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1893 19:02:39.703592 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1895 19:02:39.794174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1896 19:02:39.795002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1898 19:02:39.878530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1899 19:02:39.879320 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1901 19:02:39.971221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1902 19:02:39.972085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1904 19:02:40.063597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1905 19:02:40.064465 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1907 19:02:40.148631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1908 19:02:40.149443 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1910 19:02:40.239931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1911 19:02:40.240792 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1913 19:02:40.326548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1914 19:02:40.327407 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1916 19:02:40.419293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1917 19:02:40.420171 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1919 19:02:40.504861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1920 19:02:40.505710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1922 19:02:40.591312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1923 19:02:40.592122 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1925 19:02:40.683442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1926 19:02:40.684300 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1928 19:02:40.774904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1929 19:02:40.775700 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1931 19:02:40.867724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1932 19:02:40.868575 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1934 19:02:40.954084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1935 19:02:40.954887 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1937 19:02:41.046269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1938 19:02:41.047085 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1940 19:02:41.132747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1941 19:02:41.133516 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1943 19:02:41.225732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1944 19:02:41.226500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1946 19:02:41.318094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1947 19:02:41.318898 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1949 19:02:41.403322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1950 19:02:41.404167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1952 19:02:41.495169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1954 19:02:41.498332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1955 19:02:41.582049 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1957 19:02:41.585187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1958 19:02:41.674251 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1960 19:02:41.677336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1961 19:02:41.761223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1962 19:02:41.762001 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1964 19:02:41.852865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1965 19:02:41.853644 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1967 19:02:41.941889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1968 19:02:41.942699 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1970 19:02:42.028940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1971 19:02:42.029784 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1973 19:02:42.120225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1974 19:02:42.121045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1976 19:02:42.212789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1977 19:02:42.213570 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1979 19:02:42.298139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1980 19:02:42.298913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1982 19:02:42.387781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1983 19:02:42.388717 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1985 19:02:42.473406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1986 19:02:42.474232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1988 19:02:42.566938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1989 19:02:42.567768 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1991 19:02:42.658163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1992 19:02:42.658995 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1994 19:02:42.751032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1995 19:02:42.751834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1997 19:02:42.841288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1998 19:02:42.842145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2000 19:02:42.933032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2001 19:02:42.933830 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2003 19:02:43.025882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2004 19:02:43.026735 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2006 19:02:43.114266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2007 19:02:43.115091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2009 19:02:43.205588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2010 19:02:43.206395 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2012 19:02:43.296505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2013 19:02:43.297313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2015 19:02:43.382801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2016 19:02:43.383685 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2018 19:02:43.473251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2019 19:02:43.474091 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2021 19:02:43.558886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2022 19:02:43.559713 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2024 19:02:43.647174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2025 19:02:43.648002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2027 19:02:43.740026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2028 19:02:43.740837 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2030 19:02:43.824094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2031 19:02:43.824854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2033 19:02:43.910924 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2034 19:02:43.911701 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2036 19:02:44.003856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2037 19:02:44.004678 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2039 19:02:44.089732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2040 19:02:44.090526 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2042 19:02:44.181356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2043 19:02:44.182132 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2045 19:02:44.272817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2046 19:02:44.273580 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2048 19:02:44.357371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2049 19:02:44.358244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2051 19:02:44.447776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2052 19:02:44.448670 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2054 19:02:44.533605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2055 19:02:44.534471 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2057 19:02:44.627026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2058 19:02:44.627860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2060 19:02:44.719649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2061 19:02:44.720635 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2063 19:02:44.810791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2064 19:02:44.811580 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2066 19:02:44.900783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2067 19:02:44.901600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2069 19:02:44.991915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2070 19:02:44.992724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2072 19:02:45.083483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2073 19:02:45.084311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2075 19:02:45.169886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2076 19:02:45.170672 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2078 19:02:45.260549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2079 19:02:45.261353 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2081 19:02:45.351049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2082 19:02:45.351679 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2084 19:02:45.434589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2085 19:02:45.435464 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2087 19:02:45.520584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2088 19:02:45.521404 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2090 19:02:45.611863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2091 19:02:45.612738 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2093 19:02:45.696809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2094 19:02:45.697615 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2096 19:02:45.791549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2097 19:02:45.792431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2099 19:02:45.875850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2100 19:02:45.876671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2102 19:02:45.967647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2103 19:02:45.968511 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2105 19:02:46.057125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2106 19:02:46.057972 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2108 19:02:46.152447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2109 19:02:46.153287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2111 19:02:46.239759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2112 19:02:46.240606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2114 19:02:46.331406 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2115 19:02:46.332313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2117 19:02:46.419296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2118 19:02:46.420158 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2120 19:02:46.506692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2121 19:02:46.507505 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2123 19:02:46.592714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2124 19:02:46.593504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2126 19:02:46.684814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2127 19:02:46.685606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2129 19:02:46.771109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2130 19:02:46.771920 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2132 19:02:46.861149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2133 19:02:46.861938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2135 19:02:46.954568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2136 19:02:46.955357 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2138 19:02:47.042621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2139 19:02:47.043472 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2141 19:02:47.129551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2142 19:02:47.130392 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2144 19:02:47.214922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2145 19:02:47.215838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2147 19:02:47.306843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2148 19:02:47.307689 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2150 19:02:47.390906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2151 19:02:47.391752 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2153 19:02:47.547527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2154 19:02:47.548394 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2156 19:02:47.645217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2157 19:02:47.645994 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2159 19:02:47.735743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2160 19:02:47.736382 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2162 19:02:47.825978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2163 19:02:47.826551 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2165 19:02:47.912877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2166 19:02:47.913432 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2168 19:02:47.997280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2169 19:02:47.997857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2171 19:02:48.083849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2172 19:02:48.084500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2174 19:02:48.174220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2175 19:02:48.174866 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2177 19:02:48.260505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2178 19:02:48.261315 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2180 19:02:48.350633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2181 19:02:48.351491 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2183 19:02:48.441818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2184 19:02:48.442663 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2186 19:02:48.524646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2187 19:02:48.525476 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2189 19:02:48.616822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2190 19:02:48.617600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2192 19:02:48.703329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2193 19:02:48.704131 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2195 19:02:48.792691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2196 19:02:48.793506 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2198 19:02:48.879152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2199 19:02:48.879912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2201 19:02:48.969730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2202 19:02:48.970503 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2204 19:02:49.061343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2205 19:02:49.062187 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2207 19:02:49.146110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2208 19:02:49.146908 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2210 19:02:49.236676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2211 19:02:49.237463 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2213 19:02:49.323109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2214 19:02:49.323931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2216 19:02:49.409849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2217 19:02:49.410666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2219 19:02:49.497277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2220 19:02:49.498159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2222 19:02:49.588674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2223 19:02:49.589467 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2225 19:02:49.675916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2226 19:02:49.676798 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2228 19:02:49.761575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2229 19:02:49.762374 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2231 19:02:49.853402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2232 19:02:49.854187 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2234 19:02:49.936893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2235 19:02:49.937668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2237 19:02:50.028157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2238 19:02:50.029101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2240 19:02:50.119936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2241 19:02:50.120763 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2243 19:02:50.208235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2244 19:02:50.209009 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2246 19:02:50.297881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2247 19:02:50.298665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2249 19:02:50.383549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2250 19:02:50.384431 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2252 19:02:50.475922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2253 19:02:50.476746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2255 19:02:50.553385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2256 19:02:50.554234 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2258 19:02:50.640423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2259 19:02:50.641217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2261 19:02:50.724842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2262 19:02:50.725622 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2264 19:02:50.815278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2265 19:02:50.816084 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2267 19:02:50.908471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2268 19:02:50.909271 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2270 19:02:51.000727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2271 19:02:51.001532 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2273 19:02:51.092313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2275 19:02:51.094755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2276 19:02:51.183594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2277 19:02:51.184461 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2279 19:02:51.276844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2280 19:02:51.277656 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2282 19:02:51.367850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2283 19:02:51.368751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2285 19:02:51.459061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2286 19:02:51.459912 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2288 19:02:51.552266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2289 19:02:51.553097 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2291 19:02:51.639248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2292 19:02:51.640069 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2294 19:02:51.725666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2295 19:02:51.726440 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2297 19:02:51.816202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2298 19:02:51.816995 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2300 19:02:51.910851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2301 19:02:51.911625 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2303 19:02:51.997167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2304 19:02:51.997929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2306 19:02:52.087540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2307 19:02:52.088493 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2309 19:02:52.177446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2310 19:02:52.178281 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2312 19:02:52.267668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2313 19:02:52.268522 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2315 19:02:52.352456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2316 19:02:52.353244 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2318 19:02:52.439259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2319 19:02:52.440081 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2321 19:02:52.531275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2322 19:02:52.532078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2324 19:02:52.621929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2325 19:02:52.622748 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2327 19:02:52.705646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2328 19:02:52.706529 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2330 19:02:52.797727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2331 19:02:52.798590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2333 19:02:52.890656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2334 19:02:52.891485 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2336 19:02:52.983674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2337 19:02:52.984473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2339 19:02:53.076770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2340 19:02:53.077599 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2342 19:02:53.169418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2343 19:02:53.170215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2345 19:02:53.261926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2346 19:02:53.262712 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2348 19:02:53.352094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2349 19:02:53.353219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2351 19:02:53.445252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2352 19:02:53.446053 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2354 19:02:53.536045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2355 19:02:53.537179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2357 19:02:53.624656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2358 19:02:53.625638 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2360 19:02:53.720606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2361 19:02:53.722112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2363 19:02:53.807618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2364 19:02:53.808538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2366 19:02:53.896666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2367 19:02:53.897260 + set +x
2368 19:02:53.897989 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2370 19:02:53.904919 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 976601_1.6.2.4.5>
2371 19:02:53.905467 <LAVA_TEST_RUNNER EXIT>
2372 19:02:53.906182 Received signal: <ENDRUN> 1_kselftest-dt 976601_1.6.2.4.5
2373 19:02:53.906674 Ending use of test pattern.
2374 19:02:53.907115 Ending test lava.1_kselftest-dt (976601_1.6.2.4.5), duration 83.53
2376 19:02:53.908762 ok: lava_test_shell seems to have completed
2377 19:02:53.921517 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2378 19:02:53.923588 end: 3.1 lava-test-shell (duration 00:01:25) [common]
2379 19:02:53.924272 end: 3 lava-test-retry (duration 00:01:25) [common]
2380 19:02:53.924909 start: 4 finalize (timeout 00:05:32) [common]
2381 19:02:53.925528 start: 4.1 power-off (timeout 00:00:30) [common]
2382 19:02:53.926586 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-01'
2383 19:02:53.965447 >> OK - accepted request
2384 19:02:53.967589 Returned 0 in 0 seconds
2385 19:02:54.068902 end: 4.1 power-off (duration 00:00:00) [common]
2387 19:02:54.070611 start: 4.2 read-feedback (timeout 00:05:32) [common]
2388 19:02:54.071707 Listened to connection for namespace 'common' for up to 1s
2389 19:02:54.072629 Listened to connection for namespace 'common' for up to 1s
2390 19:02:55.072207 Finalising connection for namespace 'common'
2391 19:02:55.072928 Disconnecting from shell: Finalise
2392 19:02:55.073463 / #
2393 19:02:55.174431 end: 4.2 read-feedback (duration 00:00:01) [common]
2394 19:02:55.175114 end: 4 finalize (duration 00:00:01) [common]
2395 19:02:55.175784 Cleaning after the job
2396 19:02:55.176561 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/976601/tftp-deploy-9l7315sr/ramdisk
2397 19:02:55.179279 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/976601/tftp-deploy-9l7315sr/kernel
2398 19:02:55.183003 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/976601/tftp-deploy-9l7315sr/dtb
2399 19:02:55.184234 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/976601/tftp-deploy-9l7315sr/nfsrootfs
2400 19:02:55.219351 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/976601/tftp-deploy-9l7315sr/modules
2401 19:02:55.225400 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/976601
2402 19:02:58.177420 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/976601
2403 19:02:58.177936 Job finished correctly