Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 13:28:38.641543 lava-dispatcher, installed at version: 2024.01
2 13:28:38.642348 start: 0 validate
3 13:28:38.642820 Start time: 2024-10-01 13:28:38.642791+00:00 (UTC)
4 13:28:38.643356 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 13:28:38.643883 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 13:28:38.677301 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 13:28:38.677826 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fmaster%2Frenesas-devel-2024-10-01-v6.12-rc1%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 13:28:39.714047 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 13:28:39.714720 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fmaster%2Frenesas-devel-2024-10-01-v6.12-rc1%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 13:28:44.781631 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 13:28:44.782142 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fmaster%2Frenesas-devel-2024-10-01-v6.12-rc1%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 13:28:45.834129 validate duration: 7.19
14 13:28:45.835729 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:28:45.836455 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:28:45.837112 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:28:45.838122 Not decompressing ramdisk as can be used compressed.
18 13:28:45.838918 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 13:28:45.839412 saving as /var/lib/lava/dispatcher/tmp/786642/tftp-deploy-bbmh6s7o/ramdisk/rootfs.cpio.gz
20 13:28:45.839942 total size: 8181887 (7 MB)
21 13:28:45.881741 progress 0 % (0 MB)
22 13:28:45.893841 progress 5 % (0 MB)
23 13:28:45.905217 progress 10 % (0 MB)
24 13:28:45.917551 progress 15 % (1 MB)
25 13:28:45.924197 progress 20 % (1 MB)
26 13:28:45.929873 progress 25 % (1 MB)
27 13:28:45.935137 progress 30 % (2 MB)
28 13:28:45.940897 progress 35 % (2 MB)
29 13:28:45.946322 progress 40 % (3 MB)
30 13:28:45.952113 progress 45 % (3 MB)
31 13:28:45.957413 progress 50 % (3 MB)
32 13:28:45.963009 progress 55 % (4 MB)
33 13:28:45.968309 progress 60 % (4 MB)
34 13:28:45.973983 progress 65 % (5 MB)
35 13:28:45.979220 progress 70 % (5 MB)
36 13:28:45.984811 progress 75 % (5 MB)
37 13:28:45.990008 progress 80 % (6 MB)
38 13:28:45.995726 progress 85 % (6 MB)
39 13:28:46.001028 progress 90 % (7 MB)
40 13:28:46.006787 progress 95 % (7 MB)
41 13:28:46.011621 progress 100 % (7 MB)
42 13:28:46.012299 7 MB downloaded in 0.17 s (45.27 MB/s)
43 13:28:46.012870 end: 1.1.1 http-download (duration 00:00:00) [common]
45 13:28:46.013795 end: 1.1 download-retry (duration 00:00:00) [common]
46 13:28:46.014104 start: 1.2 download-retry (timeout 00:10:00) [common]
47 13:28:46.014386 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 13:28:46.014879 downloading http://storage.kernelci.org/renesas/master/renesas-devel-2024-10-01-v6.12-rc1/arm64/defconfig/gcc-12/kernel/Image
49 13:28:46.015128 saving as /var/lib/lava/dispatcher/tmp/786642/tftp-deploy-bbmh6s7o/kernel/Image
50 13:28:46.015343 total size: 45713920 (43 MB)
51 13:28:46.015563 No compression specified
52 13:28:46.051502 progress 0 % (0 MB)
53 13:28:46.080373 progress 5 % (2 MB)
54 13:28:46.111390 progress 10 % (4 MB)
55 13:28:46.140709 progress 15 % (6 MB)
56 13:28:46.169823 progress 20 % (8 MB)
57 13:28:46.198265 progress 25 % (10 MB)
58 13:28:46.227646 progress 30 % (13 MB)
59 13:28:46.256460 progress 35 % (15 MB)
60 13:28:46.285685 progress 40 % (17 MB)
61 13:28:46.314094 progress 45 % (19 MB)
62 13:28:46.343304 progress 50 % (21 MB)
63 13:28:46.372326 progress 55 % (24 MB)
64 13:28:46.401124 progress 60 % (26 MB)
65 13:28:46.430081 progress 65 % (28 MB)
66 13:28:46.459777 progress 70 % (30 MB)
67 13:28:46.489649 progress 75 % (32 MB)
68 13:28:46.519313 progress 80 % (34 MB)
69 13:28:46.549106 progress 85 % (37 MB)
70 13:28:46.579895 progress 90 % (39 MB)
71 13:28:46.612023 progress 95 % (41 MB)
72 13:28:46.640849 progress 100 % (43 MB)
73 13:28:46.641423 43 MB downloaded in 0.63 s (69.64 MB/s)
74 13:28:46.641907 end: 1.2.1 http-download (duration 00:00:01) [common]
76 13:28:46.642731 end: 1.2 download-retry (duration 00:00:01) [common]
77 13:28:46.643005 start: 1.3 download-retry (timeout 00:09:59) [common]
78 13:28:46.643269 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 13:28:46.643759 downloading http://storage.kernelci.org/renesas/master/renesas-devel-2024-10-01-v6.12-rc1/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 13:28:46.644067 saving as /var/lib/lava/dispatcher/tmp/786642/tftp-deploy-bbmh6s7o/dtb/meson-g12b-a311d-libretech-cc.dtb
81 13:28:46.644283 total size: 54703 (0 MB)
82 13:28:46.644495 No compression specified
83 13:28:46.676192 progress 59 % (0 MB)
84 13:28:46.677030 progress 100 % (0 MB)
85 13:28:46.677591 0 MB downloaded in 0.03 s (1.57 MB/s)
86 13:28:46.678070 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:28:46.678894 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:28:46.679156 start: 1.4 download-retry (timeout 00:09:59) [common]
90 13:28:46.679420 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 13:28:46.679908 downloading http://storage.kernelci.org/renesas/master/renesas-devel-2024-10-01-v6.12-rc1/arm64/defconfig/gcc-12/modules.tar.xz
92 13:28:46.680204 saving as /var/lib/lava/dispatcher/tmp/786642/tftp-deploy-bbmh6s7o/modules/modules.tar
93 13:28:46.680420 total size: 11615528 (11 MB)
94 13:28:46.680637 Using unxz to decompress xz
95 13:28:46.726429 progress 0 % (0 MB)
96 13:28:46.792233 progress 5 % (0 MB)
97 13:28:46.871061 progress 10 % (1 MB)
98 13:28:46.958256 progress 15 % (1 MB)
99 13:28:47.050087 progress 20 % (2 MB)
100 13:28:47.134435 progress 25 % (2 MB)
101 13:28:47.211499 progress 30 % (3 MB)
102 13:28:47.294382 progress 35 % (3 MB)
103 13:28:47.370149 progress 40 % (4 MB)
104 13:28:47.447589 progress 45 % (5 MB)
105 13:28:47.530461 progress 50 % (5 MB)
106 13:28:47.608942 progress 55 % (6 MB)
107 13:28:47.693562 progress 60 % (6 MB)
108 13:28:47.768757 progress 65 % (7 MB)
109 13:28:47.849838 progress 70 % (7 MB)
110 13:28:47.923413 progress 75 % (8 MB)
111 13:28:48.000215 progress 80 % (8 MB)
112 13:28:48.084937 progress 85 % (9 MB)
113 13:28:48.168819 progress 90 % (10 MB)
114 13:28:48.244528 progress 95 % (10 MB)
115 13:28:48.323889 progress 100 % (11 MB)
116 13:28:48.336326 11 MB downloaded in 1.66 s (6.69 MB/s)
117 13:28:48.336915 end: 1.4.1 http-download (duration 00:00:02) [common]
119 13:28:48.337745 end: 1.4 download-retry (duration 00:00:02) [common]
120 13:28:48.338018 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 13:28:48.338286 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 13:28:48.338536 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:28:48.338792 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 13:28:48.339393 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3
125 13:28:48.339888 makedir: /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin
126 13:28:48.340555 makedir: /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/tests
127 13:28:48.341198 makedir: /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/results
128 13:28:48.341824 Creating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin/lava-add-keys
129 13:28:48.342752 Creating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin/lava-add-sources
130 13:28:48.343694 Creating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin/lava-background-process-start
131 13:28:48.344759 Creating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin/lava-background-process-stop
132 13:28:48.345746 Creating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin/lava-common-functions
133 13:28:48.346656 Creating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin/lava-echo-ipv4
134 13:28:48.347546 Creating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin/lava-install-packages
135 13:28:48.348458 Creating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin/lava-installed-packages
136 13:28:48.349350 Creating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin/lava-os-build
137 13:28:48.350233 Creating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin/lava-probe-channel
138 13:28:48.351104 Creating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin/lava-probe-ip
139 13:28:48.352001 Creating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin/lava-target-ip
140 13:28:48.352900 Creating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin/lava-target-mac
141 13:28:48.353800 Creating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin/lava-target-storage
142 13:28:48.354749 Creating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin/lava-test-case
143 13:28:48.355684 Creating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin/lava-test-event
144 13:28:48.356615 Creating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin/lava-test-feedback
145 13:28:48.357499 Creating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin/lava-test-raise
146 13:28:48.358373 Creating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin/lava-test-reference
147 13:28:48.359247 Creating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin/lava-test-runner
148 13:28:48.360146 Creating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin/lava-test-set
149 13:28:48.361053 Creating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin/lava-test-shell
150 13:28:48.361945 Updating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin/lava-install-packages (oe)
151 13:28:48.362890 Updating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/bin/lava-installed-packages (oe)
152 13:28:48.363697 Creating /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/environment
153 13:28:48.364448 LAVA metadata
154 13:28:48.364934 - LAVA_JOB_ID=786642
155 13:28:48.365362 - LAVA_DISPATCHER_IP=192.168.6.2
156 13:28:48.366018 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 13:28:48.367793 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 13:28:48.368413 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 13:28:48.368823 skipped lava-vland-overlay
160 13:28:48.369307 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 13:28:48.369807 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 13:28:48.370231 skipped lava-multinode-overlay
163 13:28:48.370714 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 13:28:48.371212 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 13:28:48.371686 Loading test definitions
166 13:28:48.372261 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 13:28:48.372703 Using /lava-786642 at stage 0
168 13:28:48.374881 uuid=786642_1.5.2.4.1 testdef=None
169 13:28:48.375452 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 13:28:48.375970 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 13:28:48.377929 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 13:28:48.378747 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 13:28:48.381039 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 13:28:48.381882 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 13:28:48.384113 runner path: /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/0/tests/0_dmesg test_uuid 786642_1.5.2.4.1
178 13:28:48.384768 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 13:28:48.385551 Creating lava-test-runner.conf files
181 13:28:48.385758 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/786642/lava-overlay-8fgb4ga3/lava-786642/0 for stage 0
182 13:28:48.386099 - 0_dmesg
183 13:28:48.386453 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 13:28:48.386736 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 13:28:48.410615 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 13:28:48.411028 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 13:28:48.411292 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 13:28:48.411561 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 13:28:48.411826 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 13:28:49.341164 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 13:28:49.341637 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 13:28:49.341885 extracting modules file /var/lib/lava/dispatcher/tmp/786642/tftp-deploy-bbmh6s7o/modules/modules.tar to /var/lib/lava/dispatcher/tmp/786642/extract-overlay-ramdisk-2po891le/ramdisk
193 13:28:50.707642 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 13:28:50.708153 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 13:28:50.708436 [common] Applying overlay /var/lib/lava/dispatcher/tmp/786642/compress-overlay-z9m2obew/overlay-1.5.2.5.tar.gz to ramdisk
196 13:28:50.708648 [common] Applying overlay /var/lib/lava/dispatcher/tmp/786642/compress-overlay-z9m2obew/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/786642/extract-overlay-ramdisk-2po891le/ramdisk
197 13:28:50.738761 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 13:28:50.739164 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 13:28:50.739433 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 13:28:50.739658 Converting downloaded kernel to a uImage
201 13:28:50.739973 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/786642/tftp-deploy-bbmh6s7o/kernel/Image /var/lib/lava/dispatcher/tmp/786642/tftp-deploy-bbmh6s7o/kernel/uImage
202 13:28:51.229319 output: Image Name:
203 13:28:51.229746 output: Created: Tue Oct 1 13:28:50 2024
204 13:28:51.229958 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 13:28:51.230165 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 13:28:51.230368 output: Load Address: 01080000
207 13:28:51.230567 output: Entry Point: 01080000
208 13:28:51.230766 output:
209 13:28:51.231098 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 13:28:51.231367 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 13:28:51.231633 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 13:28:51.231889 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 13:28:51.232197 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 13:28:51.232460 Building ramdisk /var/lib/lava/dispatcher/tmp/786642/extract-overlay-ramdisk-2po891le/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/786642/extract-overlay-ramdisk-2po891le/ramdisk
215 13:28:53.961767 >> 181555 blocks
216 13:29:02.415973 Adding RAMdisk u-boot header.
217 13:29:02.416444 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/786642/extract-overlay-ramdisk-2po891le/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/786642/extract-overlay-ramdisk-2po891le/ramdisk.cpio.gz.uboot
218 13:29:02.731355 output: Image Name:
219 13:29:02.731778 output: Created: Tue Oct 1 13:29:02 2024
220 13:29:02.732019 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 13:29:02.732435 output: Data Size: 26049379 Bytes = 25438.85 KiB = 24.84 MiB
222 13:29:02.732839 output: Load Address: 00000000
223 13:29:02.733236 output: Entry Point: 00000000
224 13:29:02.733627 output:
225 13:29:02.734570 rename /var/lib/lava/dispatcher/tmp/786642/extract-overlay-ramdisk-2po891le/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/786642/tftp-deploy-bbmh6s7o/ramdisk/ramdisk.cpio.gz.uboot
226 13:29:02.735272 end: 1.5.8 compress-ramdisk (duration 00:00:12) [common]
227 13:29:02.735812 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 13:29:02.736419 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 13:29:02.736878 No LXC device requested
230 13:29:02.737374 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 13:29:02.737877 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 13:29:02.738362 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 13:29:02.738770 Checking files for TFTP limit of 4294967296 bytes.
234 13:29:02.741485 end: 1 tftp-deploy (duration 00:00:17) [common]
235 13:29:02.742067 start: 2 uboot-action (timeout 00:05:00) [common]
236 13:29:02.742588 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 13:29:02.743079 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 13:29:02.743571 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 13:29:02.744116 Using kernel file from prepare-kernel: 786642/tftp-deploy-bbmh6s7o/kernel/uImage
240 13:29:02.744724 substitutions:
241 13:29:02.745131 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 13:29:02.745532 - {DTB_ADDR}: 0x01070000
243 13:29:02.745929 - {DTB}: 786642/tftp-deploy-bbmh6s7o/dtb/meson-g12b-a311d-libretech-cc.dtb
244 13:29:02.746326 - {INITRD}: 786642/tftp-deploy-bbmh6s7o/ramdisk/ramdisk.cpio.gz.uboot
245 13:29:02.746723 - {KERNEL_ADDR}: 0x01080000
246 13:29:02.747114 - {KERNEL}: 786642/tftp-deploy-bbmh6s7o/kernel/uImage
247 13:29:02.747505 - {LAVA_MAC}: None
248 13:29:02.747936 - {PRESEED_CONFIG}: None
249 13:29:02.748362 - {PRESEED_LOCAL}: None
250 13:29:02.748752 - {RAMDISK_ADDR}: 0x08000000
251 13:29:02.749140 - {RAMDISK}: 786642/tftp-deploy-bbmh6s7o/ramdisk/ramdisk.cpio.gz.uboot
252 13:29:02.749533 - {ROOT_PART}: None
253 13:29:02.749922 - {ROOT}: None
254 13:29:02.750310 - {SERVER_IP}: 192.168.6.2
255 13:29:02.750703 - {TEE_ADDR}: 0x83000000
256 13:29:02.751091 - {TEE}: None
257 13:29:02.751477 Parsed boot commands:
258 13:29:02.751855 - setenv autoload no
259 13:29:02.752273 - setenv initrd_high 0xffffffff
260 13:29:02.752664 - setenv fdt_high 0xffffffff
261 13:29:02.753050 - dhcp
262 13:29:02.753437 - setenv serverip 192.168.6.2
263 13:29:02.753825 - tftpboot 0x01080000 786642/tftp-deploy-bbmh6s7o/kernel/uImage
264 13:29:02.754211 - tftpboot 0x08000000 786642/tftp-deploy-bbmh6s7o/ramdisk/ramdisk.cpio.gz.uboot
265 13:29:02.754597 - tftpboot 0x01070000 786642/tftp-deploy-bbmh6s7o/dtb/meson-g12b-a311d-libretech-cc.dtb
266 13:29:02.754984 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 13:29:02.755378 - bootm 0x01080000 0x08000000 0x01070000
268 13:29:02.755869 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 13:29:02.757378 start: 2.3 connect-device (timeout 00:05:00) [common]
271 13:29:02.757817 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 13:29:02.772483 Setting prompt string to ['lava-test: # ']
273 13:29:02.773969 end: 2.3 connect-device (duration 00:00:00) [common]
274 13:29:02.774606 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 13:29:02.775160 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 13:29:02.775673 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 13:29:02.776854 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 13:29:02.813173 >> OK - accepted request
279 13:29:02.815393 Returned 0 in 0 seconds
280 13:29:02.916574 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 13:29:02.918220 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 13:29:02.918762 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 13:29:02.919258 Setting prompt string to ['Hit any key to stop autoboot']
285 13:29:02.919697 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 13:29:02.921311 Trying 192.168.56.21...
287 13:29:02.921792 Connected to conserv1.
288 13:29:02.922198 Escape character is '^]'.
289 13:29:02.922610
290 13:29:02.923030 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 13:29:02.923445
292 13:29:13.652864 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 13:29:13.653640 bl2_stage_init 0x01
294 13:29:13.654197 bl2_stage_init 0x81
295 13:29:13.658436 hw id: 0x0000 - pwm id 0x01
296 13:29:13.659142 bl2_stage_init 0xc1
297 13:29:13.659681 bl2_stage_init 0x02
298 13:29:13.660246
299 13:29:13.663817 L0:00000000
300 13:29:13.664334 L1:20000703
301 13:29:13.664740 L2:00008067
302 13:29:13.665147 L3:14000000
303 13:29:13.666771 B2:00402000
304 13:29:13.667199 B1:e0f83180
305 13:29:13.667589
306 13:29:13.668189 TE: 58159
307 13:29:13.668609
308 13:29:13.677951 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 13:29:13.678434
310 13:29:13.678954 Board ID = 1
311 13:29:13.679393 Set A53 clk to 24M
312 13:29:13.679793 Set A73 clk to 24M
313 13:29:13.683541 Set clk81 to 24M
314 13:29:13.684013 A53 clk: 1200 MHz
315 13:29:13.684411 A73 clk: 1200 MHz
316 13:29:13.689146 CLK81: 166.6M
317 13:29:13.689610 smccc: 00012ab5
318 13:29:13.694744 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 13:29:13.695229 board id: 1
320 13:29:13.702411 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 13:29:13.713981 fw parse done
322 13:29:13.719950 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 13:29:13.762658 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 13:29:13.773422 PIEI prepare done
325 13:29:13.773914 fastboot data load
326 13:29:13.774308 fastboot data verify
327 13:29:13.779094 verify result: 266
328 13:29:13.784640 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 13:29:13.785112 LPDDR4 probe
330 13:29:13.785519 ddr clk to 1584MHz
331 13:29:13.792761 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 13:29:13.829936
333 13:29:13.830533 dmc_version 0001
334 13:29:13.836674 Check phy result
335 13:29:13.842441 INFO : End of CA training
336 13:29:13.842924 INFO : End of initialization
337 13:29:13.848062 INFO : Training has run successfully!
338 13:29:13.848548 Check phy result
339 13:29:13.853730 INFO : End of initialization
340 13:29:13.854207 INFO : End of read enable training
341 13:29:13.859265 INFO : End of fine write leveling
342 13:29:13.864885 INFO : End of Write leveling coarse delay
343 13:29:13.865357 INFO : Training has run successfully!
344 13:29:13.865795 Check phy result
345 13:29:13.870489 INFO : End of initialization
346 13:29:13.870958 INFO : End of read dq deskew training
347 13:29:13.876072 INFO : End of MPR read delay center optimization
348 13:29:13.881700 INFO : End of write delay center optimization
349 13:29:13.887206 INFO : End of read delay center optimization
350 13:29:13.887696 INFO : End of max read latency training
351 13:29:13.892960 INFO : Training has run successfully!
352 13:29:13.893463 1D training succeed
353 13:29:13.902537 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 13:29:13.949859 Check phy result
355 13:29:13.950479 INFO : End of initialization
356 13:29:13.971311 INFO : End of 2D read delay Voltage center optimization
357 13:29:13.991392 INFO : End of 2D read delay Voltage center optimization
358 13:29:14.043380 INFO : End of 2D write delay Voltage center optimization
359 13:29:14.092678 INFO : End of 2D write delay Voltage center optimization
360 13:29:14.098166 INFO : Training has run successfully!
361 13:29:14.098707
362 13:29:14.099151 channel==0
363 13:29:14.103791 RxClkDly_Margin_A0==88 ps 9
364 13:29:14.104348 TxDqDly_Margin_A0==98 ps 10
365 13:29:14.109385 RxClkDly_Margin_A1==88 ps 9
366 13:29:14.109861 TxDqDly_Margin_A1==98 ps 10
367 13:29:14.110303 TrainedVREFDQ_A0==74
368 13:29:14.114906 TrainedVREFDQ_A1==75
369 13:29:14.115446 VrefDac_Margin_A0==25
370 13:29:14.115881 DeviceVref_Margin_A0==40
371 13:29:14.120598 VrefDac_Margin_A1==25
372 13:29:14.121077 DeviceVref_Margin_A1==39
373 13:29:14.121517
374 13:29:14.121952
375 13:29:14.126100 channel==1
376 13:29:14.126568 RxClkDly_Margin_A0==98 ps 10
377 13:29:14.127003 TxDqDly_Margin_A0==98 ps 10
378 13:29:14.131719 RxClkDly_Margin_A1==98 ps 10
379 13:29:14.132408 TxDqDly_Margin_A1==88 ps 9
380 13:29:14.137426 TrainedVREFDQ_A0==77
381 13:29:14.137904 TrainedVREFDQ_A1==77
382 13:29:14.138392 VrefDac_Margin_A0==22
383 13:29:14.142872 DeviceVref_Margin_A0==37
384 13:29:14.143353 VrefDac_Margin_A1==24
385 13:29:14.148642 DeviceVref_Margin_A1==37
386 13:29:14.149161
387 13:29:14.149605 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 13:29:14.154175
389 13:29:14.182039 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 13:29:14.182696 2D training succeed
391 13:29:14.187647 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 13:29:14.193256 auto size-- 65535DDR cs0 size: 2048MB
393 13:29:14.193804 DDR cs1 size: 2048MB
394 13:29:14.198909 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 13:29:14.199409 cs0 DataBus test pass
396 13:29:14.204478 cs1 DataBus test pass
397 13:29:14.205049 cs0 AddrBus test pass
398 13:29:14.205487 cs1 AddrBus test pass
399 13:29:14.205919
400 13:29:14.210100 100bdlr_step_size ps== 420
401 13:29:14.210582 result report
402 13:29:14.215699 boot times 0Enable ddr reg access
403 13:29:14.220104 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 13:29:14.234586 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 13:29:14.806513 0.0;M3 CHK:0;cm4_sp_mode 0
406 13:29:14.807183 MVN_1=0x00000000
407 13:29:14.811937 MVN_2=0x00000000
408 13:29:14.817681 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 13:29:14.818200 OPS=0x10
410 13:29:14.818711 ring efuse init
411 13:29:14.819185 chipver efuse init
412 13:29:14.823263 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 13:29:14.828892 [0.018960 Inits done]
414 13:29:14.829433 secure task start!
415 13:29:14.829886 high task start!
416 13:29:14.833442 low task start!
417 13:29:14.833920 run into bl31
418 13:29:14.840191 NOTICE: BL31: v1.3(release):4fc40b1
419 13:29:14.847957 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 13:29:14.848553 NOTICE: BL31: G12A normal boot!
421 13:29:14.873374 NOTICE: BL31: BL33 decompress pass
422 13:29:14.878933 ERROR: Error initializing runtime service opteed_fast
423 13:29:16.112551
424 13:29:16.113228
425 13:29:16.120218 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 13:29:16.120747
427 13:29:16.121284 Model: Libre Computer AML-A311D-CC Alta
428 13:29:16.328712 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 13:29:16.351119 DRAM: 2 GiB (effective 3.8 GiB)
430 13:29:16.495167 Core: 408 devices, 31 uclasses, devicetree: separate
431 13:29:16.500890 WDT: Not starting watchdog@f0d0
432 13:29:16.533158 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 13:29:16.545625 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 13:29:16.550572 ** Bad device specification mmc 0 **
435 13:29:16.560883 Card did not respond to voltage select! : -110
436 13:29:16.568527 ** Bad device specification mmc 0 **
437 13:29:16.569018 Couldn't find partition mmc 0
438 13:29:16.576877 Card did not respond to voltage select! : -110
439 13:29:16.582391 ** Bad device specification mmc 0 **
440 13:29:16.582869 Couldn't find partition mmc 0
441 13:29:17.823139 Error: cou G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
442 13:29:17.823738 bl2_stage_init 0x01
443 13:29:17.824246 bl2_stage_init 0x81
444 13:29:17.828513 hw id: 0x0000 - pwm id 0x01
445 13:29:17.829013 bl2_stage_init 0xc1
446 13:29:17.829461 bl2_stage_init 0x02
447 13:29:17.829899
448 13:29:17.834241 L0:00000000
449 13:29:17.834739 L1:20000703
450 13:29:17.835187 L2:00008067
451 13:29:17.835625 L3:14000000
452 13:29:17.837351 B2:00402000
453 13:29:17.837822 B1:e0f83180
454 13:29:17.838267
455 13:29:17.838706 TE: 58159
456 13:29:17.839144
457 13:29:17.848239 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 13:29:17.848756
459 13:29:17.849209 Board ID = 1
460 13:29:17.849646 Set A53 clk to 24M
461 13:29:17.850081 Set A73 clk to 24M
462 13:29:17.853855 Set clk81 to 24M
463 13:29:17.854342 A53 clk: 1200 MHz
464 13:29:17.854782 A73 clk: 1200 MHz
465 13:29:17.859427 CLK81: 166.6M
466 13:29:17.859901 smccc: 00012ab5
467 13:29:17.865051 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 13:29:17.865535 board id: 1
469 13:29:17.872570 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 13:29:17.884202 fw parse done
471 13:29:17.889253 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 13:29:17.931918 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 13:29:17.943703 PIEI prepare done
474 13:29:17.944229 fastboot data load
475 13:29:17.944676 fastboot data verify
476 13:29:17.949368 verify result: 266
477 13:29:17.955056 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 13:29:17.955543 LPDDR4 probe
479 13:29:17.956020 ddr clk to 1584MHz
480 13:29:17.962001 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 13:29:17.999276
482 13:29:17.999775 dmc_version 0001
483 13:29:18.006830 Check phy result
484 13:29:18.012759 INFO : End of CA training
485 13:29:18.013236 INFO : End of initialization
486 13:29:18.018452 INFO : Training has run successfully!
487 13:29:18.018935 Check phy result
488 13:29:18.023932 INFO : End of initialization
489 13:29:18.024432 INFO : End of read enable training
490 13:29:18.027235 INFO : End of fine write leveling
491 13:29:18.032742 INFO : End of Write leveling coarse delay
492 13:29:18.038370 INFO : Training has run successfully!
493 13:29:18.038850 Check phy result
494 13:29:18.039290 INFO : End of initialization
495 13:29:18.044063 INFO : End of read dq deskew training
496 13:29:18.047344 INFO : End of MPR read delay center optimization
497 13:29:18.052931 INFO : End of write delay center optimization
498 13:29:18.058472 INFO : End of read delay center optimization
499 13:29:18.058951 INFO : End of max read latency training
500 13:29:18.064135 INFO : Training has run successfully!
501 13:29:18.064610 1D training succeed
502 13:29:18.071503 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 13:29:18.119250 Check phy result
504 13:29:18.119782 INFO : End of initialization
505 13:29:18.141700 INFO : End of 2D read delay Voltage center optimization
506 13:29:18.161105 INFO : End of 2D read delay Voltage center optimization
507 13:29:18.212801 INFO : End of 2D write delay Voltage center optimization
508 13:29:18.262577 INFO : End of 2D write delay Voltage center optimization
509 13:29:18.268121 INFO : Training has run successfully!
510 13:29:18.268738
511 13:29:18.269248 channel==0
512 13:29:18.273604 RxClkDly_Margin_A0==88 ps 9
513 13:29:18.274174 TxDqDly_Margin_A0==98 ps 10
514 13:29:18.279188 RxClkDly_Margin_A1==88 ps 9
515 13:29:18.279736 TxDqDly_Margin_A1==98 ps 10
516 13:29:18.280237 TrainedVREFDQ_A0==74
517 13:29:18.284769 TrainedVREFDQ_A1==74
518 13:29:18.285256 VrefDac_Margin_A0==25
519 13:29:18.285700 DeviceVref_Margin_A0==40
520 13:29:18.290366 VrefDac_Margin_A1==25
521 13:29:18.290848 DeviceVref_Margin_A1==40
522 13:29:18.291292
523 13:29:18.291735
524 13:29:18.295970 channel==1
525 13:29:18.296473 RxClkDly_Margin_A0==88 ps 9
526 13:29:18.296929 TxDqDly_Margin_A0==88 ps 9
527 13:29:18.301534 RxClkDly_Margin_A1==88 ps 9
528 13:29:18.302012 TxDqDly_Margin_A1==88 ps 9
529 13:29:18.307173 TrainedVREFDQ_A0==77
530 13:29:18.307656 TrainedVREFDQ_A1==77
531 13:29:18.308171 VrefDac_Margin_A0==23
532 13:29:18.312831 DeviceVref_Margin_A0==37
533 13:29:18.313302 VrefDac_Margin_A1==24
534 13:29:18.318421 DeviceVref_Margin_A1==37
535 13:29:18.318913
536 13:29:18.319363 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 13:29:18.319801
538 13:29:18.351971 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000019 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
539 13:29:18.352563 2D training succeed
540 13:29:18.357548 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 13:29:18.363146 auto size-- 65535DDR cs0 size: 2048MB
542 13:29:18.363646 DDR cs1 size: 2048MB
543 13:29:18.368749 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 13:29:18.369237 cs0 DataBus test pass
545 13:29:18.374389 cs1 DataBus test pass
546 13:29:18.374875 cs0 AddrBus test pass
547 13:29:18.375321 cs1 AddrBus test pass
548 13:29:18.375761
549 13:29:18.379965 100bdlr_step_size ps== 420
550 13:29:18.380494 result report
551 13:29:18.385548 boot times 0Enable ddr reg access
552 13:29:18.390716 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 13:29:18.403270 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 13:29:18.977925 0.0;M3 CHK:0;cm4_sp_mode 0
555 13:29:18.978562 MVN_1=0x00000000
556 13:29:18.983416 MVN_2=0x00000000
557 13:29:18.989247 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 13:29:18.989770 OPS=0x10
559 13:29:18.990252 ring efuse init
560 13:29:18.990713 chipver efuse init
561 13:29:18.997452 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 13:29:18.998006 [0.018961 Inits done]
563 13:29:19.004114 secure task start!
564 13:29:19.004583 high task start!
565 13:29:19.005013 low task start!
566 13:29:19.005443 run into bl31
567 13:29:19.011672 NOTICE: BL31: v1.3(release):4fc40b1
568 13:29:19.019434 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 13:29:19.019906 NOTICE: BL31: G12A normal boot!
570 13:29:19.044822 NOTICE: BL31: BL33 decompress pass
571 13:29:19.049519 ERROR: Error initializing runtime service opteed_fast
572 13:29:20.283612
573 13:29:20.284319
574 13:29:20.292007 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 13:29:20.292535
576 13:29:20.292999 Model: Libre Computer AML-A311D-CC Alta
577 13:29:20.500416 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 13:29:20.523744 DRAM: 2 GiB (effective 3.8 GiB)
579 13:29:20.666783 Core: 408 devices, 31 uclasses, devicetree: separate
580 13:29:20.672729 WDT: Not starting watchdog@f0d0
581 13:29:20.704796 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 13:29:20.717408 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 13:29:20.722315 ** Bad device specification mmc 0 **
584 13:29:20.732618 Card did not respond to voltage select! : -110
585 13:29:20.740244 ** Bad device specification mmc 0 **
586 13:29:20.740866 Couldn't find partition mmc 0
587 13:29:20.748934 Card did not respond to voltage select! : -110
588 13:29:20.754071 ** Bad device specification mmc 0 **
589 13:29:20.754550 Couldn't find partition mmc 0
590 13:29:20.759205 Error: could not access storage.
591 13:29:21.102715 Net: eth0: ethernet@ff3f0000
592 13:29:21.103330 starting USB...
593 13:29:21.354429 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 13:29:21.355025 Starting the controller
595 13:29:21.361386 USB XHCI 1.10
596 13:29:23.075329 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 13:29:23.076230 bl2_stage_init 0x01
598 13:29:23.076815 bl2_stage_init 0x81
599 13:29:23.080952 hw id: 0x0000 - pwm id 0x01
600 13:29:23.081541 bl2_stage_init 0xc1
601 13:29:23.082086 bl2_stage_init 0x02
602 13:29:23.082607
603 13:29:23.086260 L0:00000000
604 13:29:23.086837 L1:20000703
605 13:29:23.087378 L2:00008067
606 13:29:23.087909 L3:14000000
607 13:29:23.092165 B2:00402000
608 13:29:23.092748 B1:e0f83180
609 13:29:23.093291
610 13:29:23.093814 TE: 58167
611 13:29:23.094348
612 13:29:23.097578 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 13:29:23.098173
614 13:29:23.098711 Board ID = 1
615 13:29:23.102892 Set A53 clk to 24M
616 13:29:23.103470 Set A73 clk to 24M
617 13:29:23.104027 Set clk81 to 24M
618 13:29:23.109365 A53 clk: 1200 MHz
619 13:29:23.109949 A73 clk: 1200 MHz
620 13:29:23.110487 CLK81: 166.6M
621 13:29:23.111004 smccc: 00012abe
622 13:29:23.114335 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 13:29:23.120247 board id: 1
624 13:29:23.124645 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 13:29:23.136289 fw parse done
626 13:29:23.142117 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 13:29:23.184767 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 13:29:23.195548 PIEI prepare done
629 13:29:23.196118 fastboot data load
630 13:29:23.196546 fastboot data verify
631 13:29:23.201219 verify result: 266
632 13:29:23.206796 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 13:29:23.207252 LPDDR4 probe
634 13:29:23.207660 ddr clk to 1584MHz
635 13:29:23.214866 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 13:29:23.252087
637 13:29:23.252624 dmc_version 0001
638 13:29:23.258767 Check phy result
639 13:29:23.264579 INFO : End of CA training
640 13:29:23.265032 INFO : End of initialization
641 13:29:23.270177 INFO : Training has run successfully!
642 13:29:23.270624 Check phy result
643 13:29:23.275831 INFO : End of initialization
644 13:29:23.276304 INFO : End of read enable training
645 13:29:23.281344 INFO : End of fine write leveling
646 13:29:23.287099 INFO : End of Write leveling coarse delay
647 13:29:23.287562 INFO : Training has run successfully!
648 13:29:23.287970 Check phy result
649 13:29:23.292589 INFO : End of initialization
650 13:29:23.293042 INFO : End of read dq deskew training
651 13:29:23.298227 INFO : End of MPR read delay center optimization
652 13:29:23.303873 INFO : End of write delay center optimization
653 13:29:23.309493 INFO : End of read delay center optimization
654 13:29:23.309957 INFO : End of max read latency training
655 13:29:23.314987 INFO : Training has run successfully!
656 13:29:23.315427 1D training succeed
657 13:29:23.324181 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 13:29:23.371803 Check phy result
659 13:29:23.372322 INFO : End of initialization
660 13:29:23.393598 INFO : End of 2D read delay Voltage center optimization
661 13:29:23.412912 INFO : End of 2D read delay Voltage center optimization
662 13:29:23.464989 INFO : End of 2D write delay Voltage center optimization
663 13:29:23.514312 INFO : End of 2D write delay Voltage center optimization
664 13:29:23.519816 INFO : Training has run successfully!
665 13:29:23.520298
666 13:29:23.520708 channel==0
667 13:29:23.525391 RxClkDly_Margin_A0==88 ps 9
668 13:29:23.525824 TxDqDly_Margin_A0==98 ps 10
669 13:29:23.531000 RxClkDly_Margin_A1==88 ps 9
670 13:29:23.531433 TxDqDly_Margin_A1==98 ps 10
671 13:29:23.531839 TrainedVREFDQ_A0==74
672 13:29:23.536665 TrainedVREFDQ_A1==74
673 13:29:23.537109 VrefDac_Margin_A0==25
674 13:29:23.537513 DeviceVref_Margin_A0==40
675 13:29:23.542288 VrefDac_Margin_A1==25
676 13:29:23.542735 DeviceVref_Margin_A1==40
677 13:29:23.543134
678 13:29:23.543530
679 13:29:23.547828 channel==1
680 13:29:23.548302 RxClkDly_Margin_A0==78 ps 8
681 13:29:23.548722 TxDqDly_Margin_A0==98 ps 10
682 13:29:23.553453 RxClkDly_Margin_A1==88 ps 9
683 13:29:23.553890 TxDqDly_Margin_A1==88 ps 9
684 13:29:23.559011 TrainedVREFDQ_A0==77
685 13:29:23.559448 TrainedVREFDQ_A1==77
686 13:29:23.559850 VrefDac_Margin_A0==23
687 13:29:23.564694 DeviceVref_Margin_A0==37
688 13:29:23.565131 VrefDac_Margin_A1==24
689 13:29:23.570192 DeviceVref_Margin_A1==37
690 13:29:23.570627
691 13:29:23.571030 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 13:29:23.571423
693 13:29:23.603831 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
694 13:29:23.604368 2D training succeed
695 13:29:23.609504 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 13:29:23.615002 auto size-- 65535DDR cs0 size: 2048MB
697 13:29:23.615440 DDR cs1 size: 2048MB
698 13:29:23.620621 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 13:29:23.621058 cs0 DataBus test pass
700 13:29:23.626208 cs1 DataBus test pass
701 13:29:23.626721 cs0 AddrBus test pass
702 13:29:23.627127 cs1 AddrBus test pass
703 13:29:23.627522
704 13:29:23.631827 100bdlr_step_size ps== 420
705 13:29:23.632309 result report
706 13:29:23.637369 boot times 0Enable ddr reg access
707 13:29:23.642700 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 13:29:23.656176 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 13:29:24.229832 0.0;M3 CHK:0;cm4_sp_mode 0
710 13:29:24.230489 MVN_1=0x00000000
711 13:29:24.235295 MVN_2=0x00000000
712 13:29:24.242173 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 13:29:24.242797 OPS=0x10
714 13:29:24.243262 ring efuse init
715 13:29:24.243681 chipver efuse init
716 13:29:24.249437 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 13:29:24.249931 [0.018960 Inits done]
718 13:29:24.256289 secure task start!
719 13:29:24.257000 high task start!
720 13:29:24.257560 low task start!
721 13:29:24.258126 run into bl31
722 13:29:24.263815 NOTICE: BL31: v1.3(release):4fc40b1
723 13:29:24.270548 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 13:29:24.271302 NOTICE: BL31: G12A normal boot!
725 13:29:24.297132 NOTICE: BL31: BL33 decompress pass
726 13:29:24.301445 ERROR: Error initializing runtime service opteed_fast
727 13:29:25.535204
728 13:29:25.535636
729 13:29:25.543530 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 13:29:25.543860
731 13:29:25.544120 Model: Libre Computer AML-A311D-CC Alta
732 13:29:25.752059 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 13:29:25.775402 DRAM: 2 GiB (effective 3.8 GiB)
734 13:29:25.918382 Core: 408 devices, 31 uclasses, devicetree: separate
735 13:29:25.924183 WDT: Not starting watchdog@f0d0
736 13:29:25.956572 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 13:29:25.968933 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 13:29:25.972949 ** Bad device specification mmc 0 **
739 13:29:25.984209 Card did not respond to voltage select! : -110
740 13:29:25.991875 ** Bad device specification mmc 0 **
741 13:29:25.992324 Couldn't find partition mmc 0
742 13:29:26.000251 Card did not respond to voltage select! : -110
743 13:29:26.005707 ** Bad device specification mmc 0 **
744 13:29:26.006002 Couldn't find partition mmc 0
745 13:29:26.010790 Error: could not access storage.
746 13:29:26.353342 Net: eth0: ethernet@ff3f0000
747 13:29:26.353766 starting USB...
748 13:29:26.605073 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 13:29:26.605489 Starting the controller
750 13:29:26.612066 USB XHCI 1.10
751 13:29:28.773446 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 13:29:28.774048 bl2_stage_init 0x01
753 13:29:28.774475 bl2_stage_init 0x81
754 13:29:28.779021 hw id: 0x0000 - pwm id 0x01
755 13:29:28.779493 bl2_stage_init 0xc1
756 13:29:28.779910 bl2_stage_init 0x02
757 13:29:28.780358
758 13:29:28.784622 L0:00000000
759 13:29:28.785067 L1:20000703
760 13:29:28.785473 L2:00008067
761 13:29:28.785873 L3:14000000
762 13:29:28.790200 B2:00402000
763 13:29:28.790636 B1:e0f83180
764 13:29:28.791040
765 13:29:28.791446 TE: 58167
766 13:29:28.791846
767 13:29:28.795777 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 13:29:28.796257
769 13:29:28.796673 Board ID = 1
770 13:29:28.801385 Set A53 clk to 24M
771 13:29:28.801823 Set A73 clk to 24M
772 13:29:28.802226 Set clk81 to 24M
773 13:29:28.806989 A53 clk: 1200 MHz
774 13:29:28.807421 A73 clk: 1200 MHz
775 13:29:28.807818 CLK81: 166.6M
776 13:29:28.808251 smccc: 00012abd
777 13:29:28.812542 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 13:29:28.825392 board id: 1
779 13:29:28.827748 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 13:29:28.834733 fw parse done
781 13:29:28.840709 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 13:29:28.883357 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 13:29:28.894334 PIEI prepare done
784 13:29:28.894782 fastboot data load
785 13:29:28.895190 fastboot data verify
786 13:29:28.899940 verify result: 266
787 13:29:28.905482 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 13:29:28.905930 LPDDR4 probe
789 13:29:28.906333 ddr clk to 1584MHz
790 13:29:28.913458 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 13:29:28.950787
792 13:29:28.951266 dmc_version 0001
793 13:29:28.957439 Check phy result
794 13:29:28.963266 INFO : End of CA training
795 13:29:28.963712 INFO : End of initialization
796 13:29:28.969259 INFO : Training has run successfully!
797 13:29:28.969715 Check phy result
798 13:29:28.974587 INFO : End of initialization
799 13:29:28.975029 INFO : End of read enable training
800 13:29:28.977815 INFO : End of fine write leveling
801 13:29:28.983297 INFO : End of Write leveling coarse delay
802 13:29:28.989060 INFO : Training has run successfully!
803 13:29:28.989512 Check phy result
804 13:29:28.989919 INFO : End of initialization
805 13:29:28.994665 INFO : End of read dq deskew training
806 13:29:29.000154 INFO : End of MPR read delay center optimization
807 13:29:29.000638 INFO : End of write delay center optimization
808 13:29:29.005786 INFO : End of read delay center optimization
809 13:29:29.011436 INFO : End of max read latency training
810 13:29:29.011893 INFO : Training has run successfully!
811 13:29:29.017088 1D training succeed
812 13:29:29.022033 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 13:29:29.070542 Check phy result
814 13:29:29.071028 INFO : End of initialization
815 13:29:29.091525 INFO : End of 2D read delay Voltage center optimization
816 13:29:29.110834 INFO : End of 2D read delay Voltage center optimization
817 13:29:29.163758 INFO : End of 2D write delay Voltage center optimization
818 13:29:29.213034 INFO : End of 2D write delay Voltage center optimization
819 13:29:29.218656 INFO : Training has run successfully!
820 13:29:29.219110
821 13:29:29.219524 channel==0
822 13:29:29.224197 RxClkDly_Margin_A0==88 ps 9
823 13:29:29.224664 TxDqDly_Margin_A0==98 ps 10
824 13:29:29.229719 RxClkDly_Margin_A1==88 ps 9
825 13:29:29.230159 TxDqDly_Margin_A1==98 ps 10
826 13:29:29.230567 TrainedVREFDQ_A0==74
827 13:29:29.235326 TrainedVREFDQ_A1==74
828 13:29:29.235809 VrefDac_Margin_A0==25
829 13:29:29.236238 DeviceVref_Margin_A0==40
830 13:29:29.240942 VrefDac_Margin_A1==25
831 13:29:29.241428 DeviceVref_Margin_A1==40
832 13:29:29.241815
833 13:29:29.242198
834 13:29:29.246930 channel==1
835 13:29:29.247393 RxClkDly_Margin_A0==88 ps 9
836 13:29:29.247780 TxDqDly_Margin_A0==98 ps 10
837 13:29:29.252203 RxClkDly_Margin_A1==88 ps 9
838 13:29:29.252638 TxDqDly_Margin_A1==108 ps 11
839 13:29:29.257771 TrainedVREFDQ_A0==77
840 13:29:29.258220 TrainedVREFDQ_A1==77
841 13:29:29.258611 VrefDac_Margin_A0==23
842 13:29:29.263350 DeviceVref_Margin_A0==37
843 13:29:29.263774 VrefDac_Margin_A1==24
844 13:29:29.269002 DeviceVref_Margin_A1==37
845 13:29:29.269436
846 13:29:29.269830 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 13:29:29.274521
848 13:29:29.302620 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
849 13:29:29.303117 2D training succeed
850 13:29:29.308230 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 13:29:29.313718 auto size-- 65535DDR cs0 size: 2048MB
852 13:29:29.314150 DDR cs1 size: 2048MB
853 13:29:29.319329 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 13:29:29.319758 cs0 DataBus test pass
855 13:29:29.324898 cs1 DataBus test pass
856 13:29:29.325326 cs0 AddrBus test pass
857 13:29:29.325714 cs1 AddrBus test pass
858 13:29:29.326096
859 13:29:29.330507 100bdlr_step_size ps== 420
860 13:29:29.330947 result report
861 13:29:29.336100 boot times 0Enable ddr reg access
862 13:29:29.341669 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 13:29:29.354152 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 13:29:29.928297 0.0;M3 CHK:0;cm4_sp_mode 0
865 13:29:29.928923 MVN_1=0x00000000
866 13:29:29.933743 MVN_2=0x00000000
867 13:29:29.939441 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 13:29:29.939890 OPS=0x10
869 13:29:29.940349 ring efuse init
870 13:29:29.940750 chipver efuse init
871 13:29:29.945012 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 13:29:29.950743 [0.018961 Inits done]
873 13:29:29.951182 secure task start!
874 13:29:29.951583 high task start!
875 13:29:29.954253 low task start!
876 13:29:29.954696 run into bl31
877 13:29:29.961835 NOTICE: BL31: v1.3(release):4fc40b1
878 13:29:29.969744 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 13:29:29.970191 NOTICE: BL31: G12A normal boot!
880 13:29:29.995089 NOTICE: BL31: BL33 decompress pass
881 13:29:30.000854 ERROR: Error initializing runtime service opteed_fast
882 13:29:31.233650
883 13:29:31.234231
884 13:29:31.242028 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 13:29:31.242477
886 13:29:31.242802 Model: Libre Computer AML-A311D-CC Alta
887 13:29:31.450687 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 13:29:31.473908 DRAM: 2 GiB (effective 3.8 GiB)
889 13:29:31.616850 Core: 408 devices, 31 uclasses, devicetree: separate
890 13:29:31.622754 WDT: Not starting watchdog@f0d0
891 13:29:31.655090 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 13:29:31.667454 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 13:29:31.671501 ** Bad device specification mmc 0 **
894 13:29:31.682809 Card did not respond to voltage select! : -110
895 13:29:31.690409 ** Bad device specification mmc 0 **
896 13:29:31.690857 Couldn't find partition mmc 0
897 13:29:31.698765 Card did not respond to voltage select! : -110
898 13:29:31.704227 ** Bad device specification mmc 0 **
899 13:29:31.704674 Couldn't find partition mmc 0
900 13:29:31.709314 Error: could not access storage.
901 13:29:32.052858 Net: eth0: ethernet@ff3f0000
902 13:29:32.053272 starting USB...
903 13:29:32.304811 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 13:29:32.305240 Starting the controller
905 13:29:32.311678 USB XHCI 1.10
906 13:29:33.865998 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
907 13:29:33.874393 scanning usb for storage devices... 0 Storage Device(s) found
909 13:29:33.926111 Hit any key to stop autoboot: 1
910 13:29:33.927127 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
911 13:29:33.927843 start: 2.4.3 bootloader-commands (timeout 00:04:29) [common]
912 13:29:33.928518 Setting prompt string to ['=>']
913 13:29:33.929078 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:29)
914 13:29:33.941801 0
915 13:29:33.942996 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
916 13:29:33.943605 Sending with 10 millisecond of delay
918 13:29:35.079149 => setenv autoload no
919 13:29:35.090051 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:28)
920 13:29:35.095093 setenv autoload no
921 13:29:35.095884 Sending with 10 millisecond of delay
923 13:29:36.894269 => setenv initrd_high 0xffffffff
924 13:29:36.905132 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
925 13:29:36.906080 setenv initrd_high 0xffffffff
926 13:29:36.906892 Sending with 10 millisecond of delay
928 13:29:38.523882 => setenv fdt_high 0xffffffff
929 13:29:38.534759 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
930 13:29:38.535655 setenv fdt_high 0xffffffff
931 13:29:38.536452 Sending with 10 millisecond of delay
933 13:29:38.828411 => dhcp
934 13:29:38.839224 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
935 13:29:38.840228 dhcp
936 13:29:38.840748 Speed: 1000, full duplex
937 13:29:38.841228 BOOTP broadcast 1
938 13:29:39.087424 BOOTP broadcast 2
939 13:29:39.108733 DHCP client bound to address 192.168.6.33 (269 ms)
940 13:29:39.109549 Sending with 10 millisecond of delay
942 13:29:40.786386 => setenv serverip 192.168.6.2
943 13:29:40.797227 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
944 13:29:40.798116 setenv serverip 192.168.6.2
945 13:29:40.798858 Sending with 10 millisecond of delay
947 13:29:44.524104 => tftpboot 0x01080000 786642/tftp-deploy-bbmh6s7o/kernel/uImage
948 13:29:44.535077 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
949 13:29:44.536099 tftpboot 0x01080000 786642/tftp-deploy-bbmh6s7o/kernel/uImage
950 13:29:44.536626 Speed: 1000, full duplex
951 13:29:44.537083 Using ethernet@ff3f0000 device
952 13:29:44.538004 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
953 13:29:44.543343 Filename '786642/tftp-deploy-bbmh6s7o/kernel/uImage'.
954 13:29:44.547269 Load address: 0x1080000
955 13:29:52.150383 Loading: *###################################### UDP wrong checksum 00000005 00007c10
956 13:29:56.143230 T ############ 43.6 MiB
957 13:29:56.143829 3.8 MiB/s
958 13:29:56.144305 done
959 13:29:56.146592 Bytes transferred = 45713984 (2b98a40 hex)
960 13:29:56.147368 Sending with 10 millisecond of delay
962 13:30:00.834752 => tftpboot 0x08000000 786642/tftp-deploy-bbmh6s7o/ramdisk/ramdisk.cpio.gz.uboot
963 13:30:00.845582 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
964 13:30:00.846436 tftpboot 0x08000000 786642/tftp-deploy-bbmh6s7o/ramdisk/ramdisk.cpio.gz.uboot
965 13:30:00.846931 Speed: 1000, full duplex
966 13:30:00.847374 Using ethernet@ff3f0000 device
967 13:30:00.848376 TFTP from server 192.168.6.2; our IP address is 192.168.6.33
968 13:30:00.860266 Filename '786642/tftp-deploy-bbmh6s7o/ramdisk/ramdisk.cpio.gz.uboot'.
969 13:30:00.860803 Load address: 0x8000000
970 13:30:04.158940 Loading: *################################################# UDP wrong checksum 00000005 00006f55
971 13:30:09.158795 T UDP wrong checksum 00000005 00006f55
972 13:30:19.160962 T T UDP wrong checksum 00000005 00006f55
973 13:30:39.165114 T T T UDP wrong checksum 00000005 00006f55
974 13:30:40.119278 T UDP wrong checksum 000000ff 0000a3d5
975 13:30:40.136713 UDP wrong checksum 000000ff 000027c8
976 13:30:45.421036 T UDP wrong checksum 000000ff 00009504
977 13:30:45.442644 UDP wrong checksum 000000ff 000019f7
978 13:30:53.130866 T UDP wrong checksum 000000ff 000009e2
979 13:30:53.169256 UDP wrong checksum 000000ff 000090d4
980 13:30:59.172167 T
981 13:30:59.172564 Retry count exceeded; starting again
983 13:30:59.173450 end: 2.4.3 bootloader-commands (duration 00:01:25) [common]
986 13:30:59.175250 end: 2.4 uboot-commands (duration 00:01:56) [common]
988 13:30:59.176649 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
990 13:30:59.177683 end: 2 uboot-action (duration 00:01:56) [common]
992 13:30:59.179202 Cleaning after the job
993 13:30:59.179766 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/786642/tftp-deploy-bbmh6s7o/ramdisk
994 13:30:59.180969 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/786642/tftp-deploy-bbmh6s7o/kernel
995 13:30:59.223829 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/786642/tftp-deploy-bbmh6s7o/dtb
996 13:30:59.224695 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/786642/tftp-deploy-bbmh6s7o/modules
997 13:30:59.246965 start: 4.1 power-off (timeout 00:00:30) [common]
998 13:30:59.247617 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
999 13:30:59.283365 >> OK - accepted request
1000 13:30:59.285446 Returned 0 in 0 seconds
1001 13:30:59.386237 end: 4.1 power-off (duration 00:00:00) [common]
1003 13:30:59.387224 start: 4.2 read-feedback (timeout 00:10:00) [common]
1004 13:30:59.387875 Listened to connection for namespace 'common' for up to 1s
1005 13:31:00.388795 Finalising connection for namespace 'common'
1006 13:31:00.389292 Disconnecting from shell: Finalise
1007 13:31:00.389613 =>
1008 13:31:00.490318 end: 4.2 read-feedback (duration 00:00:01) [common]
1009 13:31:00.490792 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/786642
1010 13:31:00.773465 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/786642
1011 13:31:00.774082 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.