Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 15:52:04.328051 lava-dispatcher, installed at version: 2024.01
2 15:52:04.328843 start: 0 validate
3 15:52:04.329338 Start time: 2024-10-01 15:52:04.329308+00:00 (UTC)
4 15:52:04.329891 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 15:52:04.330412 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 15:52:04.365387 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 15:52:04.365956 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fmaster%2Frenesas-devel-2024-10-01-v6.12-rc1%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 15:52:04.400325 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 15:52:04.400966 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fmaster%2Frenesas-devel-2024-10-01-v6.12-rc1%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 15:52:04.433038 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 15:52:04.433519 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fmaster%2Frenesas-devel-2024-10-01-v6.12-rc1%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 15:52:04.471274 validate duration: 0.14
14 15:52:04.472150 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 15:52:04.472702 start: 1.1 download-retry (timeout 00:10:00) [common]
16 15:52:04.473051 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 15:52:04.473652 Not decompressing ramdisk as can be used compressed.
18 15:52:04.474093 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 15:52:04.474370 saving as /var/lib/lava/dispatcher/tmp/786659/tftp-deploy-bb4slxeq/ramdisk/rootfs.cpio.gz
20 15:52:04.474818 total size: 47897469 (45 MB)
21 15:52:04.508495 progress 0 % (0 MB)
22 15:52:04.539823 progress 5 % (2 MB)
23 15:52:04.570565 progress 10 % (4 MB)
24 15:52:04.601027 progress 15 % (6 MB)
25 15:52:04.631720 progress 20 % (9 MB)
26 15:52:04.662101 progress 25 % (11 MB)
27 15:52:04.692241 progress 30 % (13 MB)
28 15:52:04.722605 progress 35 % (16 MB)
29 15:52:04.753280 progress 40 % (18 MB)
30 15:52:04.783588 progress 45 % (20 MB)
31 15:52:04.814488 progress 50 % (22 MB)
32 15:52:04.845252 progress 55 % (25 MB)
33 15:52:04.876198 progress 60 % (27 MB)
34 15:52:04.906452 progress 65 % (29 MB)
35 15:52:04.936941 progress 70 % (32 MB)
36 15:52:04.967637 progress 75 % (34 MB)
37 15:52:04.998170 progress 80 % (36 MB)
38 15:52:05.028538 progress 85 % (38 MB)
39 15:52:05.059861 progress 90 % (41 MB)
40 15:52:05.090391 progress 95 % (43 MB)
41 15:52:05.120537 progress 100 % (45 MB)
42 15:52:05.121285 45 MB downloaded in 0.65 s (70.66 MB/s)
43 15:52:05.121839 end: 1.1.1 http-download (duration 00:00:01) [common]
45 15:52:05.122725 end: 1.1 download-retry (duration 00:00:01) [common]
46 15:52:05.123017 start: 1.2 download-retry (timeout 00:09:59) [common]
47 15:52:05.123289 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 15:52:05.123770 downloading http://storage.kernelci.org/renesas/master/renesas-devel-2024-10-01-v6.12-rc1/arm64/defconfig/gcc-12/kernel/Image
49 15:52:05.124034 saving as /var/lib/lava/dispatcher/tmp/786659/tftp-deploy-bb4slxeq/kernel/Image
50 15:52:05.124249 total size: 45713920 (43 MB)
51 15:52:05.124463 No compression specified
52 15:52:05.159600 progress 0 % (0 MB)
53 15:52:05.187851 progress 5 % (2 MB)
54 15:52:05.216175 progress 10 % (4 MB)
55 15:52:05.244559 progress 15 % (6 MB)
56 15:52:05.272869 progress 20 % (8 MB)
57 15:52:05.300911 progress 25 % (10 MB)
58 15:52:05.329760 progress 30 % (13 MB)
59 15:52:05.357918 progress 35 % (15 MB)
60 15:52:05.386467 progress 40 % (17 MB)
61 15:52:05.414489 progress 45 % (19 MB)
62 15:52:05.442696 progress 50 % (21 MB)
63 15:52:05.470880 progress 55 % (24 MB)
64 15:52:05.499558 progress 60 % (26 MB)
65 15:52:05.527427 progress 65 % (28 MB)
66 15:52:05.555608 progress 70 % (30 MB)
67 15:52:05.584247 progress 75 % (32 MB)
68 15:52:05.612317 progress 80 % (34 MB)
69 15:52:05.640063 progress 85 % (37 MB)
70 15:52:05.668186 progress 90 % (39 MB)
71 15:52:05.696705 progress 95 % (41 MB)
72 15:52:05.724245 progress 100 % (43 MB)
73 15:52:05.724790 43 MB downloaded in 0.60 s (72.60 MB/s)
74 15:52:05.725271 end: 1.2.1 http-download (duration 00:00:01) [common]
76 15:52:05.726090 end: 1.2 download-retry (duration 00:00:01) [common]
77 15:52:05.726364 start: 1.3 download-retry (timeout 00:09:59) [common]
78 15:52:05.726628 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 15:52:05.727097 downloading http://storage.kernelci.org/renesas/master/renesas-devel-2024-10-01-v6.12-rc1/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 15:52:05.727342 saving as /var/lib/lava/dispatcher/tmp/786659/tftp-deploy-bb4slxeq/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 15:52:05.727549 total size: 53209 (0 MB)
82 15:52:05.727758 No compression specified
83 15:52:05.764163 progress 61 % (0 MB)
84 15:52:05.765003 progress 100 % (0 MB)
85 15:52:05.765530 0 MB downloaded in 0.04 s (1.34 MB/s)
86 15:52:05.765996 end: 1.3.1 http-download (duration 00:00:00) [common]
88 15:52:05.766807 end: 1.3 download-retry (duration 00:00:00) [common]
89 15:52:05.767069 start: 1.4 download-retry (timeout 00:09:59) [common]
90 15:52:05.767333 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 15:52:05.767819 downloading http://storage.kernelci.org/renesas/master/renesas-devel-2024-10-01-v6.12-rc1/arm64/defconfig/gcc-12/modules.tar.xz
92 15:52:05.768100 saving as /var/lib/lava/dispatcher/tmp/786659/tftp-deploy-bb4slxeq/modules/modules.tar
93 15:52:05.768308 total size: 11615528 (11 MB)
94 15:52:05.768518 Using unxz to decompress xz
95 15:52:05.800951 progress 0 % (0 MB)
96 15:52:05.877412 progress 5 % (0 MB)
97 15:52:05.956441 progress 10 % (1 MB)
98 15:52:06.043825 progress 15 % (1 MB)
99 15:52:06.136391 progress 20 % (2 MB)
100 15:52:06.220066 progress 25 % (2 MB)
101 15:52:06.298144 progress 30 % (3 MB)
102 15:52:06.381404 progress 35 % (3 MB)
103 15:52:06.457841 progress 40 % (4 MB)
104 15:52:06.536031 progress 45 % (5 MB)
105 15:52:06.619578 progress 50 % (5 MB)
106 15:52:06.697973 progress 55 % (6 MB)
107 15:52:06.783150 progress 60 % (6 MB)
108 15:52:06.860052 progress 65 % (7 MB)
109 15:52:06.941268 progress 70 % (7 MB)
110 15:52:07.016358 progress 75 % (8 MB)
111 15:52:07.094967 progress 80 % (8 MB)
112 15:52:07.179781 progress 85 % (9 MB)
113 15:52:07.264079 progress 90 % (10 MB)
114 15:52:07.342029 progress 95 % (10 MB)
115 15:52:07.423354 progress 100 % (11 MB)
116 15:52:07.435833 11 MB downloaded in 1.67 s (6.64 MB/s)
117 15:52:07.436762 end: 1.4.1 http-download (duration 00:00:02) [common]
119 15:52:07.438514 end: 1.4 download-retry (duration 00:00:02) [common]
120 15:52:07.439090 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 15:52:07.439665 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 15:52:07.440243 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 15:52:07.440801 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 15:52:07.441878 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p
125 15:52:07.442793 makedir: /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin
126 15:52:07.443479 makedir: /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/tests
127 15:52:07.444189 makedir: /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/results
128 15:52:07.444864 Creating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin/lava-add-keys
129 15:52:07.445881 Creating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin/lava-add-sources
130 15:52:07.446884 Creating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin/lava-background-process-start
131 15:52:07.447906 Creating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin/lava-background-process-stop
132 15:52:07.449045 Creating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin/lava-common-functions
133 15:52:07.450044 Creating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin/lava-echo-ipv4
134 15:52:07.451030 Creating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin/lava-install-packages
135 15:52:07.452029 Creating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin/lava-installed-packages
136 15:52:07.453027 Creating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin/lava-os-build
137 15:52:07.454034 Creating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin/lava-probe-channel
138 15:52:07.455033 Creating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin/lava-probe-ip
139 15:52:07.456067 Creating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin/lava-target-ip
140 15:52:07.457067 Creating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin/lava-target-mac
141 15:52:07.458031 Creating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin/lava-target-storage
142 15:52:07.459019 Creating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin/lava-test-case
143 15:52:07.460031 Creating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin/lava-test-event
144 15:52:07.461025 Creating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin/lava-test-feedback
145 15:52:07.461996 Creating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin/lava-test-raise
146 15:52:07.463207 Creating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin/lava-test-reference
147 15:52:07.464238 Creating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin/lava-test-runner
148 15:52:07.465243 Creating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin/lava-test-set
149 15:52:07.466224 Creating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin/lava-test-shell
150 15:52:07.467200 Updating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin/lava-install-packages (oe)
151 15:52:07.468293 Updating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/bin/lava-installed-packages (oe)
152 15:52:07.469207 Creating /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/environment
153 15:52:07.469984 LAVA metadata
154 15:52:07.470636 - LAVA_JOB_ID=786659
155 15:52:07.471112 - LAVA_DISPATCHER_IP=192.168.6.2
156 15:52:07.471838 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 15:52:07.473742 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 15:52:07.474328 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 15:52:07.474737 skipped lava-vland-overlay
160 15:52:07.475221 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 15:52:07.475723 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 15:52:07.476190 skipped lava-multinode-overlay
163 15:52:07.476679 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 15:52:07.477180 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 15:52:07.477655 Loading test definitions
166 15:52:07.478196 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 15:52:07.478631 Using /lava-786659 at stage 0
168 15:52:07.480493 uuid=786659_1.5.2.4.1 testdef=None
169 15:52:07.480835 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 15:52:07.481106 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 15:52:07.482896 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 15:52:07.483698 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 15:52:07.485883 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 15:52:07.486705 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 15:52:07.488840 runner path: /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/0/tests/0_igt-gpu-panfrost test_uuid 786659_1.5.2.4.1
178 15:52:07.489442 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 15:52:07.490250 Creating lava-test-runner.conf files
181 15:52:07.490459 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/786659/lava-overlay-nsqwn71p/lava-786659/0 for stage 0
182 15:52:07.490805 - 0_igt-gpu-panfrost
183 15:52:07.491155 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 15:52:07.491435 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 15:52:07.515062 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 15:52:07.515467 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 15:52:07.515732 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 15:52:07.516040 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 15:52:07.516318 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 15:52:14.487948 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 15:52:14.488442 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 15:52:14.488693 extracting modules file /var/lib/lava/dispatcher/tmp/786659/tftp-deploy-bb4slxeq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/786659/extract-overlay-ramdisk-wtiwx38f/ramdisk
193 15:52:15.918436 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 15:52:15.918916 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
195 15:52:15.919198 [common] Applying overlay /var/lib/lava/dispatcher/tmp/786659/compress-overlay-b1aqg54j/overlay-1.5.2.5.tar.gz to ramdisk
196 15:52:15.919413 [common] Applying overlay /var/lib/lava/dispatcher/tmp/786659/compress-overlay-b1aqg54j/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/786659/extract-overlay-ramdisk-wtiwx38f/ramdisk
197 15:52:15.949657 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 15:52:15.950071 start: 1.5.6 prepare-kernel (timeout 00:09:49) [common]
199 15:52:15.950347 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:49) [common]
200 15:52:15.950578 Converting downloaded kernel to a uImage
201 15:52:15.950886 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/786659/tftp-deploy-bb4slxeq/kernel/Image /var/lib/lava/dispatcher/tmp/786659/tftp-deploy-bb4slxeq/kernel/uImage
202 15:52:16.426058 output: Image Name:
203 15:52:16.426469 output: Created: Tue Oct 1 15:52:15 2024
204 15:52:16.426679 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 15:52:16.426881 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 15:52:16.427081 output: Load Address: 01080000
207 15:52:16.427281 output: Entry Point: 01080000
208 15:52:16.427480 output:
209 15:52:16.427808 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 15:52:16.428138 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 15:52:16.428424 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 15:52:16.428680 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 15:52:16.428939 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 15:52:16.429194 Building ramdisk /var/lib/lava/dispatcher/tmp/786659/extract-overlay-ramdisk-wtiwx38f/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/786659/extract-overlay-ramdisk-wtiwx38f/ramdisk
215 15:52:23.127883 >> 502360 blocks
216 15:52:43.759975 Adding RAMdisk u-boot header.
217 15:52:43.760665 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/786659/extract-overlay-ramdisk-wtiwx38f/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/786659/extract-overlay-ramdisk-wtiwx38f/ramdisk.cpio.gz.uboot
218 15:52:44.431489 output: Image Name:
219 15:52:44.431896 output: Created: Tue Oct 1 15:52:43 2024
220 15:52:44.432461 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 15:52:44.432929 output: Data Size: 65706165 Bytes = 64166.18 KiB = 62.66 MiB
222 15:52:44.433383 output: Load Address: 00000000
223 15:52:44.433832 output: Entry Point: 00000000
224 15:52:44.434269 output:
225 15:52:44.435308 rename /var/lib/lava/dispatcher/tmp/786659/extract-overlay-ramdisk-wtiwx38f/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/786659/tftp-deploy-bb4slxeq/ramdisk/ramdisk.cpio.gz.uboot
226 15:52:44.436108 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 15:52:44.436729 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 15:52:44.437324 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 15:52:44.437832 No LXC device requested
230 15:52:44.438392 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 15:52:44.438963 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 15:52:44.439516 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 15:52:44.439975 Checking files for TFTP limit of 4294967296 bytes.
234 15:52:44.442933 end: 1 tftp-deploy (duration 00:00:40) [common]
235 15:52:44.443569 start: 2 uboot-action (timeout 00:05:00) [common]
236 15:52:44.444193 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 15:52:44.444759 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 15:52:44.445341 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 15:52:44.445925 Using kernel file from prepare-kernel: 786659/tftp-deploy-bb4slxeq/kernel/uImage
240 15:52:44.446600 substitutions:
241 15:52:44.447057 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 15:52:44.447509 - {DTB_ADDR}: 0x01070000
243 15:52:44.447959 - {DTB}: 786659/tftp-deploy-bb4slxeq/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 15:52:44.448442 - {INITRD}: 786659/tftp-deploy-bb4slxeq/ramdisk/ramdisk.cpio.gz.uboot
245 15:52:44.448888 - {KERNEL_ADDR}: 0x01080000
246 15:52:44.449328 - {KERNEL}: 786659/tftp-deploy-bb4slxeq/kernel/uImage
247 15:52:44.449773 - {LAVA_MAC}: None
248 15:52:44.450258 - {PRESEED_CONFIG}: None
249 15:52:44.450703 - {PRESEED_LOCAL}: None
250 15:52:44.451142 - {RAMDISK_ADDR}: 0x08000000
251 15:52:44.451576 - {RAMDISK}: 786659/tftp-deploy-bb4slxeq/ramdisk/ramdisk.cpio.gz.uboot
252 15:52:44.452050 - {ROOT_PART}: None
253 15:52:44.452492 - {ROOT}: None
254 15:52:44.452931 - {SERVER_IP}: 192.168.6.2
255 15:52:44.453371 - {TEE_ADDR}: 0x83000000
256 15:52:44.453809 - {TEE}: None
257 15:52:44.454246 Parsed boot commands:
258 15:52:44.454669 - setenv autoload no
259 15:52:44.455105 - setenv initrd_high 0xffffffff
260 15:52:44.455536 - setenv fdt_high 0xffffffff
261 15:52:44.455966 - dhcp
262 15:52:44.456483 - setenv serverip 192.168.6.2
263 15:52:44.456923 - tftpboot 0x01080000 786659/tftp-deploy-bb4slxeq/kernel/uImage
264 15:52:44.457361 - tftpboot 0x08000000 786659/tftp-deploy-bb4slxeq/ramdisk/ramdisk.cpio.gz.uboot
265 15:52:44.457798 - tftpboot 0x01070000 786659/tftp-deploy-bb4slxeq/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 15:52:44.458237 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 15:52:44.458678 - bootm 0x01080000 0x08000000 0x01070000
268 15:52:44.459240 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 15:52:44.460928 start: 2.3 connect-device (timeout 00:05:00) [common]
271 15:52:44.461431 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 15:52:44.477497 Setting prompt string to ['lava-test: # ']
273 15:52:44.479093 end: 2.3 connect-device (duration 00:00:00) [common]
274 15:52:44.479780 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 15:52:44.480500 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 15:52:44.481091 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 15:52:44.482325 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 15:52:44.519922 >> OK - accepted request
279 15:52:44.522217 Returned 0 in 0 seconds
280 15:52:44.623448 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 15:52:44.625320 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 15:52:44.625966 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 15:52:44.626551 Setting prompt string to ['Hit any key to stop autoboot']
285 15:52:44.627068 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 15:52:44.628880 Trying 192.168.56.21...
287 15:52:44.629412 Connected to conserv1.
288 15:52:44.629880 Escape character is '^]'.
289 15:52:44.630342
290 15:52:44.630826 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 15:52:44.631315
292 15:52:46.803587 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 15:52:46.804339 bl2_stage_init 0x01
294 15:52:46.804850 bl2_stage_init 0x81
295 15:52:46.809048 hw id: 0x0000 - pwm id 0x01
296 15:52:46.809624 bl2_stage_init 0xc1
297 15:52:46.814520 bl2_stage_init 0x02
298 15:52:46.815097
299 15:52:46.815589 L0:00000000
300 15:52:46.816103 L1:00000703
301 15:52:46.816578 L2:00008067
302 15:52:46.817027 L3:15000000
303 15:52:46.819971 S1:00000000
304 15:52:46.820518 B2:20282000
305 15:52:46.820981 B1:a0f83180
306 15:52:46.821434
307 15:52:46.821893 TE: 69531
308 15:52:46.822347
309 15:52:46.825754 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 15:52:46.826287
311 15:52:46.831322 Board ID = 1
312 15:52:46.831852 Set cpu clk to 24M
313 15:52:46.832369 Set clk81 to 24M
314 15:52:46.835031 Use GP1_pll as DSU clk.
315 15:52:46.835538 DSU clk: 1200 Mhz
316 15:52:46.840425 CPU clk: 1200 MHz
317 15:52:46.840944 Set clk81 to 166.6M
318 15:52:46.846152 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 15:52:46.846697 board id: 1
320 15:52:46.855300 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 15:52:46.866050 fw parse done
322 15:52:46.871854 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 15:52:46.914577 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 15:52:46.925421 PIEI prepare done
325 15:52:46.926098 fastboot data load
326 15:52:46.926595 fastboot data verify
327 15:52:46.930879 verify result: 266
328 15:52:46.936543 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 15:52:46.937126 LPDDR4 probe
330 15:52:46.937594 ddr clk to 1584MHz
331 15:52:46.944900 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 15:52:46.982106
333 15:52:46.982823 dmc_version 0001
334 15:52:46.988642 Check phy result
335 15:52:46.994584 INFO : End of CA training
336 15:52:46.995211 INFO : End of initialization
337 15:52:47.000169 INFO : Training has run successfully!
338 15:52:47.000793 Check phy result
339 15:52:47.005707 INFO : End of initialization
340 15:52:47.006297 INFO : End of read enable training
341 15:52:47.009029 INFO : End of fine write leveling
342 15:52:47.014686 INFO : End of Write leveling coarse delay
343 15:52:47.020252 INFO : Training has run successfully!
344 15:52:47.020865 Check phy result
345 15:52:47.021362 INFO : End of initialization
346 15:52:47.025922 INFO : End of read dq deskew training
347 15:52:47.029186 INFO : End of MPR read delay center optimization
348 15:52:47.034868 INFO : End of write delay center optimization
349 15:52:47.040418 INFO : End of read delay center optimization
350 15:52:47.041029 INFO : End of max read latency training
351 15:52:47.045944 INFO : Training has run successfully!
352 15:52:47.046584 1D training succeed
353 15:52:47.054061 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 15:52:47.101758 Check phy result
355 15:52:47.102468 INFO : End of initialization
356 15:52:47.124132 INFO : End of 2D read delay Voltage center optimization
357 15:52:47.142302 INFO : End of 2D read delay Voltage center optimization
358 15:52:47.195086 INFO : End of 2D write delay Voltage center optimization
359 15:52:47.244261 INFO : End of 2D write delay Voltage center optimization
360 15:52:47.249953 INFO : Training has run successfully!
361 15:52:47.250519
362 15:52:47.250983 channel==0
363 15:52:47.255435 RxClkDly_Margin_A0==88 ps 9
364 15:52:47.256051 TxDqDly_Margin_A0==98 ps 10
365 15:52:47.261095 RxClkDly_Margin_A1==88 ps 9
366 15:52:47.261662 TxDqDly_Margin_A1==98 ps 10
367 15:52:47.262133 TrainedVREFDQ_A0==76
368 15:52:47.266763 TrainedVREFDQ_A1==74
369 15:52:47.267332 VrefDac_Margin_A0==24
370 15:52:47.267792 DeviceVref_Margin_A0==38
371 15:52:47.272330 VrefDac_Margin_A1==23
372 15:52:47.272896 DeviceVref_Margin_A1==40
373 15:52:47.273352
374 15:52:47.273807
375 15:52:47.278014 channel==1
376 15:52:47.278591 RxClkDly_Margin_A0==78 ps 8
377 15:52:47.279050 TxDqDly_Margin_A0==98 ps 10
378 15:52:47.283468 RxClkDly_Margin_A1==88 ps 9
379 15:52:47.284081 TxDqDly_Margin_A1==88 ps 9
380 15:52:47.289178 TrainedVREFDQ_A0==78
381 15:52:47.289751 TrainedVREFDQ_A1==78
382 15:52:47.290222 VrefDac_Margin_A0==22
383 15:52:47.295316 DeviceVref_Margin_A0==36
384 15:52:47.295886 VrefDac_Margin_A1==22
385 15:52:47.300338 DeviceVref_Margin_A1==36
386 15:52:47.300902
387 15:52:47.301370 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 15:52:47.301828
389 15:52:47.333883 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000016 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
390 15:52:47.334592 2D training succeed
391 15:52:47.339269 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 15:52:47.344874 auto size-- 65535DDR cs0 size: 2048MB
393 15:52:47.345418 DDR cs1 size: 2048MB
394 15:52:47.350522 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 15:52:47.351070 cs0 DataBus test pass
396 15:52:47.356102 cs1 DataBus test pass
397 15:52:47.356647 cs0 AddrBus test pass
398 15:52:47.357108 cs1 AddrBus test pass
399 15:52:47.357554
400 15:52:47.361804 100bdlr_step_size ps== 471
401 15:52:47.362358 result report
402 15:52:47.367244 boot times 0Enable ddr reg access
403 15:52:47.372493 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 15:52:47.386308 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 15:52:48.041227 bl2z: ptr: 05129330, size: 00001e40
406 15:52:48.048203 0.0;M3 CHK:0;cm4_sp_mode 0
407 15:52:48.048796 MVN_1=0x00000000
408 15:52:48.049265 MVN_2=0x00000000
409 15:52:48.059780 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 15:52:48.060415 OPS=0x04
411 15:52:48.060889 ring efuse init
412 15:52:48.062679 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 15:52:48.068315 [0.017320 Inits done]
414 15:52:48.068869 secure task start!
415 15:52:48.069337 high task start!
416 15:52:48.069794 low task start!
417 15:52:48.072521 run into bl31
418 15:52:48.081106 NOTICE: BL31: v1.3(release):4fc40b1
419 15:52:48.088913 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 15:52:48.089471 NOTICE: BL31: G12A normal boot!
421 15:52:48.104392 NOTICE: BL31: BL33 decompress pass
422 15:52:48.110092 ERROR: Error initializing runtime service opteed_fast
423 15:52:50.841325 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 15:52:50.841987 bl2_stage_init 0x01
425 15:52:50.842467 bl2_stage_init 0x81
426 15:52:50.847031 hw id: 0x0000 - pwm id 0x01
427 15:52:50.847556 bl2_stage_init 0xc1
428 15:52:50.852621 bl2_stage_init 0x02
429 15:52:50.853161
430 15:52:50.853639 L0:00000000
431 15:52:50.854112 L1:00000703
432 15:52:50.854545 L2:00008067
433 15:52:50.854978 L3:15000000
434 15:52:50.858149 S1:00000000
435 15:52:50.858652 B2:20282000
436 15:52:50.859084 B1:a0f83180
437 15:52:50.859509
438 15:52:50.859934 TE: 67853
439 15:52:50.860410
440 15:52:50.863783 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 15:52:50.864309
442 15:52:50.869320 Board ID = 1
443 15:52:50.869811 Set cpu clk to 24M
444 15:52:50.870246 Set clk81 to 24M
445 15:52:50.874905 Use GP1_pll as DSU clk.
446 15:52:50.875421 DSU clk: 1200 Mhz
447 15:52:50.875854 CPU clk: 1200 MHz
448 15:52:50.880570 Set clk81 to 166.6M
449 15:52:50.886153 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 15:52:50.886648 board id: 1
451 15:52:50.893386 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 15:52:50.904281 fw parse done
453 15:52:50.910270 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 15:52:50.952346 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 15:52:50.964540 PIEI prepare done
456 15:52:50.965050 fastboot data load
457 15:52:50.965487 fastboot data verify
458 15:52:50.970111 verify result: 266
459 15:52:50.975742 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 15:52:50.976281 LPDDR4 probe
461 15:52:50.976718 ddr clk to 1584MHz
462 15:52:50.983723 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 15:52:51.020476
464 15:52:51.021014 dmc_version 0001
465 15:52:51.028482 Check phy result
466 15:52:51.034486 INFO : End of CA training
467 15:52:51.034987 INFO : End of initialization
468 15:52:51.040097 INFO : Training has run successfully!
469 15:52:51.040607 Check phy result
470 15:52:51.045687 INFO : End of initialization
471 15:52:51.046187 INFO : End of read enable training
472 15:52:51.049016 INFO : End of fine write leveling
473 15:52:51.054688 INFO : End of Write leveling coarse delay
474 15:52:51.060337 INFO : Training has run successfully!
475 15:52:51.060875 Check phy result
476 15:52:51.061333 INFO : End of initialization
477 15:52:51.065852 INFO : End of read dq deskew training
478 15:52:51.069125 INFO : End of MPR read delay center optimization
479 15:52:51.074712 INFO : End of write delay center optimization
480 15:52:51.080301 INFO : End of read delay center optimization
481 15:52:51.080818 INFO : End of max read latency training
482 15:52:51.085872 INFO : Training has run successfully!
483 15:52:51.086387 1D training succeed
484 15:52:51.094138 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 15:52:51.142445 Check phy result
486 15:52:51.143033 INFO : End of initialization
487 15:52:51.169845 INFO : End of 2D read delay Voltage center optimization
488 15:52:51.194018 INFO : End of 2D read delay Voltage center optimization
489 15:52:51.250684 INFO : End of 2D write delay Voltage center optimization
490 15:52:51.304688 INFO : End of 2D write delay Voltage center optimization
491 15:52:51.310347 INFO : Training has run successfully!
492 15:52:51.310869
493 15:52:51.311328 channel==0
494 15:52:51.315791 RxClkDly_Margin_A0==78 ps 8
495 15:52:51.316332 TxDqDly_Margin_A0==88 ps 9
496 15:52:51.319108 RxClkDly_Margin_A1==88 ps 9
497 15:52:51.319609 TxDqDly_Margin_A1==98 ps 10
498 15:52:51.324719 TrainedVREFDQ_A0==74
499 15:52:51.325235 TrainedVREFDQ_A1==74
500 15:52:51.325695 VrefDac_Margin_A0==24
501 15:52:51.330328 DeviceVref_Margin_A0==40
502 15:52:51.330855 VrefDac_Margin_A1==23
503 15:52:51.335910 DeviceVref_Margin_A1==40
504 15:52:51.336458
505 15:52:51.336921
506 15:52:51.337373 channel==1
507 15:52:51.337821 RxClkDly_Margin_A0==88 ps 9
508 15:52:51.339324 TxDqDly_Margin_A0==98 ps 10
509 15:52:51.344935 RxClkDly_Margin_A1==78 ps 8
510 15:52:51.345444 TxDqDly_Margin_A1==78 ps 8
511 15:52:51.345906 TrainedVREFDQ_A0==78
512 15:52:51.350515 TrainedVREFDQ_A1==77
513 15:52:51.351045 VrefDac_Margin_A0==23
514 15:52:51.356117 DeviceVref_Margin_A0==36
515 15:52:51.356621 VrefDac_Margin_A1==22
516 15:52:51.357073 DeviceVref_Margin_A1==37
517 15:52:51.357515
518 15:52:51.361749 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 15:52:51.362257
520 15:52:51.395276 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
521 15:52:51.395854 2D training succeed
522 15:52:51.401505 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 15:52:51.406613 auto size-- 65535DDR cs0 size: 2048MB
524 15:52:51.407114 DDR cs1 size: 2048MB
525 15:52:51.412260 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 15:52:51.412772 cs0 DataBus test pass
527 15:52:51.413225 cs1 DataBus test pass
528 15:52:51.417938 cs0 AddrBus test pass
529 15:52:51.418441 cs1 AddrBus test pass
530 15:52:51.418892
531 15:52:51.423327 100bdlr_step_size ps== 464
532 15:52:51.423842 result report
533 15:52:51.424348 boot times 0Enable ddr reg access
534 15:52:51.434359 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 15:52:51.446866 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 15:52:52.106252 bl2z: ptr: 05129330, size: 00001e40
537 15:52:52.113927 0.0;M3 CHK:0;cm4_sp_mode 0
538 15:52:52.114459 MVN_1=0x00000000
539 15:52:52.114914 MVN_2=0x00000000
540 15:52:52.125343 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 15:52:52.125860 OPS=0x04
542 15:52:52.126323 ring efuse init
543 15:52:52.130993 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 15:52:52.131511 [0.017354 Inits done]
545 15:52:52.131969 secure task start!
546 15:52:52.138453 high task start!
547 15:52:52.138956 low task start!
548 15:52:52.139407 run into bl31
549 15:52:52.147047 NOTICE: BL31: v1.3(release):4fc40b1
550 15:52:52.154886 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 15:52:52.155447 NOTICE: BL31: G12A normal boot!
552 15:52:52.170554 NOTICE: BL31: BL33 decompress pass
553 15:52:52.176407 ERROR: Error initializing runtime service opteed_fast
554 15:52:53.443133 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 15:52:53.443756 bl2_stage_init 0x01
556 15:52:53.444245 bl2_stage_init 0x81
557 15:52:53.448875 hw id: 0x0000 - pwm id 0x01
558 15:52:53.449321 bl2_stage_init 0xc1
559 15:52:53.454466 bl2_stage_init 0x02
560 15:52:53.454903
561 15:52:53.455319 L0:00000000
562 15:52:53.455725 L1:00000703
563 15:52:53.456164 L2:00008067
564 15:52:53.456566 L3:15000000
565 15:52:53.460069 S1:00000000
566 15:52:53.460509 B2:20282000
567 15:52:53.460916 B1:a0f83180
568 15:52:53.461317
569 15:52:53.461718 TE: 69364
570 15:52:53.462121
571 15:52:53.465469 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 15:52:53.465911
573 15:52:53.471455 Board ID = 1
574 15:52:53.471885 Set cpu clk to 24M
575 15:52:53.472328 Set clk81 to 24M
576 15:52:53.474907 Use GP1_pll as DSU clk.
577 15:52:53.475338 DSU clk: 1200 Mhz
578 15:52:53.480159 CPU clk: 1200 MHz
579 15:52:53.480597 Set clk81 to 166.6M
580 15:52:53.485623 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 15:52:53.486053 board id: 1
582 15:52:53.495135 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 15:52:53.505755 fw parse done
584 15:52:53.511814 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 15:52:53.554310 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 15:52:53.565270 PIEI prepare done
587 15:52:53.565701 fastboot data load
588 15:52:53.566117 fastboot data verify
589 15:52:53.570857 verify result: 266
590 15:52:53.576450 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 15:52:53.576886 LPDDR4 probe
592 15:52:53.577293 ddr clk to 1584MHz
593 15:52:53.584463 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 15:52:53.621715
595 15:52:53.622168 dmc_version 0001
596 15:52:53.628397 Check phy result
597 15:52:53.634262 INFO : End of CA training
598 15:52:53.634692 INFO : End of initialization
599 15:52:53.639907 INFO : Training has run successfully!
600 15:52:53.640380 Check phy result
601 15:52:53.645649 INFO : End of initialization
602 15:52:53.646085 INFO : End of read enable training
603 15:52:53.651083 INFO : End of fine write leveling
604 15:52:53.656723 INFO : End of Write leveling coarse delay
605 15:52:53.657157 INFO : Training has run successfully!
606 15:52:53.657567 Check phy result
607 15:52:53.662257 INFO : End of initialization
608 15:52:53.662696 INFO : End of read dq deskew training
609 15:52:53.667809 INFO : End of MPR read delay center optimization
610 15:52:53.673620 INFO : End of write delay center optimization
611 15:52:53.679102 INFO : End of read delay center optimization
612 15:52:53.679532 INFO : End of max read latency training
613 15:52:53.684670 INFO : Training has run successfully!
614 15:52:53.685103 1D training succeed
615 15:52:53.693922 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 15:52:53.741528 Check phy result
617 15:52:53.742002 INFO : End of initialization
618 15:52:53.763820 INFO : End of 2D read delay Voltage center optimization
619 15:52:53.782984 INFO : End of 2D read delay Voltage center optimization
620 15:52:53.834861 INFO : End of 2D write delay Voltage center optimization
621 15:52:53.884243 INFO : End of 2D write delay Voltage center optimization
622 15:52:53.889759 INFO : Training has run successfully!
623 15:52:53.890199
624 15:52:53.890614 channel==0
625 15:52:53.895248 RxClkDly_Margin_A0==78 ps 8
626 15:52:53.895680 TxDqDly_Margin_A0==88 ps 9
627 15:52:53.898590 RxClkDly_Margin_A1==88 ps 9
628 15:52:53.899019 TxDqDly_Margin_A1==98 ps 10
629 15:52:53.904031 TrainedVREFDQ_A0==74
630 15:52:53.904468 TrainedVREFDQ_A1==74
631 15:52:53.904874 VrefDac_Margin_A0==24
632 15:52:53.909743 DeviceVref_Margin_A0==40
633 15:52:53.910171 VrefDac_Margin_A1==22
634 15:52:53.915320 DeviceVref_Margin_A1==40
635 15:52:53.915754
636 15:52:53.916192
637 15:52:53.916596 channel==1
638 15:52:53.916991 RxClkDly_Margin_A0==78 ps 8
639 15:52:53.920876 TxDqDly_Margin_A0==98 ps 10
640 15:52:53.921319 RxClkDly_Margin_A1==88 ps 9
641 15:52:53.926467 TxDqDly_Margin_A1==88 ps 9
642 15:52:53.926903 TrainedVREFDQ_A0==78
643 15:52:53.927307 TrainedVREFDQ_A1==75
644 15:52:53.932112 VrefDac_Margin_A0==22
645 15:52:53.932558 DeviceVref_Margin_A0==36
646 15:52:53.937749 VrefDac_Margin_A1==22
647 15:52:53.938175 DeviceVref_Margin_A1==39
648 15:52:53.938582
649 15:52:53.943358 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 15:52:53.943793
651 15:52:53.971211 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
652 15:52:53.976789 2D training succeed
653 15:52:53.982399 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 15:52:53.982836 auto size-- 65535DDR cs0 size: 2048MB
655 15:52:53.988096 DDR cs1 size: 2048MB
656 15:52:53.988523 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 15:52:53.993641 cs0 DataBus test pass
658 15:52:53.994074 cs1 DataBus test pass
659 15:52:53.994480 cs0 AddrBus test pass
660 15:52:53.999247 cs1 AddrBus test pass
661 15:52:53.999677
662 15:52:54.000132 100bdlr_step_size ps== 478
663 15:52:54.000546 result report
664 15:52:54.004858 boot times 0Enable ddr reg access
665 15:52:54.011543 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 15:52:54.026208 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 15:52:54.679844 bl2z: ptr: 05129330, size: 00001e40
668 15:52:54.687601 0.0;M3 CHK:0;cm4_sp_mode 0
669 15:52:54.688103 MVN_1=0x00000000
670 15:52:54.688528 MVN_2=0x00000000
671 15:52:54.699188 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 15:52:54.699639 OPS=0x04
673 15:52:54.700104 ring efuse init
674 15:52:54.702168 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 15:52:54.707737 [0.017310 Inits done]
676 15:52:54.708235 secure task start!
677 15:52:54.708655 high task start!
678 15:52:54.709065 low task start!
679 15:52:54.711918 run into bl31
680 15:52:54.720644 NOTICE: BL31: v1.3(release):4fc40b1
681 15:52:54.728320 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 15:52:54.728801 NOTICE: BL31: G12A normal boot!
683 15:52:54.743809 NOTICE: BL31: BL33 decompress pass
684 15:52:54.749481 ERROR: Error initializing runtime service opteed_fast
685 15:52:55.545007
686 15:52:55.545692
687 15:52:55.550419 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 15:52:55.550949
689 15:52:55.553893 Model: Libre Computer AML-S905D3-CC Solitude
690 15:52:55.701017 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 15:52:55.716258 DRAM: 2 GiB (effective 3.8 GiB)
692 15:53:02.459960 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
693 15:53:02.460636 bl2_stage_init 0x01
694 15:53:02.461113 bl2_stage_init 0x81
695 15:53:02.465558 hw id: 0x0000 - pwm id 0x01
696 15:53:02.466075 bl2_stage_init 0xc1
697 15:53:02.471091 bl2_stage_init 0x02
698 15:53:02.471598
699 15:53:02.472102 L0:00000000
700 15:53:02.472563 L1:00000703
701 15:53:02.473008 L2:00008067
702 15:53:02.473452 L3:15000000
703 15:53:02.476795 S1:00000000
704 15:53:02.477303 B2:20282000
705 15:53:02.477758 B1:a0f83180
706 15:53:02.478202
707 15:53:02.478645 TE: 67628
708 15:53:02.479091
709 15:53:02.482303 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
710 15:53:02.482819
711 15:53:02.487898 Board ID = 1
712 15:53:02.488440 Set cpu clk to 24M
713 15:53:02.488893 Set clk81 to 24M
714 15:53:02.493480 Use GP1_pll as DSU clk.
715 15:53:02.493987 DSU clk: 1200 Mhz
716 15:53:02.494440 CPU clk: 1200 MHz
717 15:53:02.499107 Set clk81 to 166.6M
718 15:53:02.504762 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
719 15:53:02.505277 board id: 1
720 15:53:02.511914 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
721 15:53:02.522520 fw parse done
722 15:53:02.528493 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
723 15:53:02.571130 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
724 15:53:02.582209 PIEI prepare done
725 15:53:02.582740 fastboot data load
726 15:53:02.583205 fastboot data verify
727 15:53:02.587759 verify result: 266
728 15:53:02.593398 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
729 15:53:02.593918 LPDDR4 probe
730 15:53:02.594373 ddr clk to 1584MHz
731 15:53:02.601262 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
732 15:53:02.638603
733 15:53:02.639157 dmc_version 0001
734 15:53:02.645271 Check phy result
735 15:53:02.651179 INFO : End of CA training
736 15:53:02.651688 INFO : End of initialization
737 15:53:02.656903 INFO : Training has run successfully!
738 15:53:02.657419 Check phy result
739 15:53:02.662364 INFO : End of initialization
740 15:53:02.662873 INFO : End of read enable training
741 15:53:02.665665 INFO : End of fine write leveling
742 15:53:02.671289 INFO : End of Write leveling coarse delay
743 15:53:02.676878 INFO : Training has run successfully!
744 15:53:02.677387 Check phy result
745 15:53:02.677843 INFO : End of initialization
746 15:53:02.682389 INFO : End of read dq deskew training
747 15:53:02.688118 INFO : End of MPR read delay center optimization
748 15:53:02.688655 INFO : End of write delay center optimization
749 15:53:02.693631 INFO : End of read delay center optimization
750 15:53:02.699270 INFO : End of max read latency training
751 15:53:02.699794 INFO : Training has run successfully!
752 15:53:02.704861 1D training succeed
753 15:53:02.710775 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
754 15:53:02.758060 Check phy result
755 15:53:02.758610 INFO : End of initialization
756 15:53:02.780710 INFO : End of 2D read delay Voltage center optimization
757 15:53:02.800030 INFO : End of 2D read delay Voltage center optimization
758 15:53:02.851756 INFO : End of 2D write delay Voltage center optimization
759 15:53:02.900949 INFO : End of 2D write delay Voltage center optimization
760 15:53:02.906537 INFO : Training has run successfully!
761 15:53:02.907061
762 15:53:02.907522 channel==0
763 15:53:02.912109 RxClkDly_Margin_A0==78 ps 8
764 15:53:02.912646 TxDqDly_Margin_A0==98 ps 10
765 15:53:02.917685 RxClkDly_Margin_A1==88 ps 9
766 15:53:02.918196 TxDqDly_Margin_A1==98 ps 10
767 15:53:02.918659 TrainedVREFDQ_A0==75
768 15:53:02.923316 TrainedVREFDQ_A1==75
769 15:53:02.923837 VrefDac_Margin_A0==24
770 15:53:02.924340 DeviceVref_Margin_A0==39
771 15:53:02.928922 VrefDac_Margin_A1==23
772 15:53:02.929430 DeviceVref_Margin_A1==39
773 15:53:02.929888
774 15:53:02.930346
775 15:53:02.934506 channel==1
776 15:53:02.935019 RxClkDly_Margin_A0==78 ps 8
777 15:53:02.935474 TxDqDly_Margin_A0==98 ps 10
778 15:53:02.940112 RxClkDly_Margin_A1==88 ps 9
779 15:53:02.940623 TxDqDly_Margin_A1==88 ps 9
780 15:53:02.945673 TrainedVREFDQ_A0==78
781 15:53:02.946190 TrainedVREFDQ_A1==75
782 15:53:02.946648 VrefDac_Margin_A0==22
783 15:53:02.951313 DeviceVref_Margin_A0==36
784 15:53:02.951823 VrefDac_Margin_A1==22
785 15:53:02.956937 DeviceVref_Margin_A1==39
786 15:53:02.957447
787 15:53:02.957899 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
788 15:53:02.958346
789 15:53:02.990501 soc_vref_reg_value 0x 00000019 00000018 00000017 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000014 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
790 15:53:02.991108 2D training succeed
791 15:53:02.996093 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
792 15:53:03.001733 auto size-- 65535DDR cs0 size: 2048MB
793 15:53:03.002253 DDR cs1 size: 2048MB
794 15:53:03.007311 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
795 15:53:03.007839 cs0 DataBus test pass
796 15:53:03.012984 cs1 DataBus test pass
797 15:53:03.013499 cs0 AddrBus test pass
798 15:53:03.013954 cs1 AddrBus test pass
799 15:53:03.014402
800 15:53:03.018577 100bdlr_step_size ps== 478
801 15:53:03.019104 result report
802 15:53:03.024138 boot times 0Enable ddr reg access
803 15:53:03.028578 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
804 15:53:03.043143 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
805 15:53:03.698130 bl2z: ptr: 05129330, size: 00001e40
806 15:53:03.705281 0.0;M3 CHK:0;cm4_sp_mode 0
807 15:53:03.705827 MVN_1=0x00000000
808 15:53:03.706293 MVN_2=0x00000000
809 15:53:03.716704 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
810 15:53:03.717236 OPS=0x04
811 15:53:03.717697 ring efuse init
812 15:53:03.719714 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
813 15:53:03.726082 [0.017310 Inits done]
814 15:53:03.726592 secure task start!
815 15:53:03.727051 high task start!
816 15:53:03.727503 low task start!
817 15:53:03.730366 run into bl31
818 15:53:03.738984 NOTICE: BL31: v1.3(release):4fc40b1
819 15:53:03.746774 NOTICE: BL31: Built : 15:57:33, May 22 2019
820 15:53:03.747288 NOTICE: BL31: G12A normal boot!
821 15:53:03.762210 NOTICE: BL31: BL33 decompress pass
822 15:53:03.768195 ERROR: Error initializing runtime service opteed_fast
823 15:53:06.434100 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
824 15:53:06.434731 bl2_stage_init 0x01
825 15:53:06.435182 bl2_stage_init 0x81
826 15:53:06.439594 hw id: 0x0000 - pwm id 0x01
827 15:53:06.440089 bl2_stage_init 0xc1
828 15:53:06.445179 bl2_stage_init 0x02
829 15:53:06.446008
830 15:53:06.446514 L0:00000000
831 15:53:06.446981 L1:00000703
832 15:53:06.447414 L2:00008067
833 15:53:06.447855 L3:15000000
834 15:53:06.450883 S1:00000000
835 15:53:06.451382 B2:20282000
836 15:53:06.451870 B1:a0f83180
837 15:53:06.452387
838 15:53:06.452851 TE: 71643
839 15:53:06.453284
840 15:53:06.456508 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
841 15:53:06.456973
842 15:53:06.462413 Board ID = 1
843 15:53:06.462840 Set cpu clk to 24M
844 15:53:06.463231 Set clk81 to 24M
845 15:53:06.467499 Use GP1_pll as DSU clk.
846 15:53:06.467916 DSU clk: 1200 Mhz
847 15:53:06.468343 CPU clk: 1200 MHz
848 15:53:06.473201 Set clk81 to 166.6M
849 15:53:06.478952 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
850 15:53:06.479589 board id: 1
851 15:53:06.485987 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
852 15:53:06.496584 fw parse done
853 15:53:06.502448 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
854 15:53:06.545049 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
855 15:53:06.556225 PIEI prepare done
856 15:53:06.556813 fastboot data load
857 15:53:06.557267 fastboot data verify
858 15:53:06.561638 verify result: 266
859 15:53:06.567294 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
860 15:53:06.567782 LPDDR4 probe
861 15:53:06.568279 ddr clk to 1584MHz
862 15:53:06.574626 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
863 15:53:06.612404
864 15:53:06.612898 dmc_version 0001
865 15:53:06.618166 Check phy result
866 15:53:06.624948 INFO : End of CA training
867 15:53:06.625425 INFO : End of initialization
868 15:53:06.630638 INFO : Training has run successfully!
869 15:53:06.631121 Check phy result
870 15:53:06.636271 INFO : End of initialization
871 15:53:06.636780 INFO : End of read enable training
872 15:53:06.641742 INFO : End of fine write leveling
873 15:53:06.647428 INFO : End of Write leveling coarse delay
874 15:53:06.647954 INFO : Training has run successfully!
875 15:53:06.648463 Check phy result
876 15:53:06.653019 INFO : End of initialization
877 15:53:06.653636 INFO : End of read dq deskew training
878 15:53:06.658600 INFO : End of MPR read delay center optimization
879 15:53:06.664272 INFO : End of write delay center optimization
880 15:53:06.669772 INFO : End of read delay center optimization
881 15:53:06.670278 INFO : End of max read latency training
882 15:53:06.675420 INFO : Training has run successfully!
883 15:53:06.675932 1D training succeed
884 15:53:06.684586 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
885 15:53:06.732275 Check phy result
886 15:53:06.732837 INFO : End of initialization
887 15:53:06.753901 INFO : End of 2D read delay Voltage center optimization
888 15:53:06.773709 INFO : End of 2D read delay Voltage center optimization
889 15:53:06.824658 INFO : End of 2D write delay Voltage center optimization
890 15:53:06.874770 INFO : End of 2D write delay Voltage center optimization
891 15:53:06.880326 INFO : Training has run successfully!
892 15:53:06.880823
893 15:53:06.881284 channel==0
894 15:53:06.885875 RxClkDly_Margin_A0==78 ps 8
895 15:53:06.886365 TxDqDly_Margin_A0==98 ps 10
896 15:53:06.891479 RxClkDly_Margin_A1==88 ps 9
897 15:53:06.891969 TxDqDly_Margin_A1==88 ps 9
898 15:53:06.892482 TrainedVREFDQ_A0==77
899 15:53:06.897128 TrainedVREFDQ_A1==74
900 15:53:06.897631 VrefDac_Margin_A0==24
901 15:53:06.898087 DeviceVref_Margin_A0==37
902 15:53:06.902700 VrefDac_Margin_A1==22
903 15:53:06.903203 DeviceVref_Margin_A1==40
904 15:53:06.903655
905 15:53:06.904145
906 15:53:06.904597 channel==1
907 15:53:06.908331 RxClkDly_Margin_A0==88 ps 9
908 15:53:06.908830 TxDqDly_Margin_A0==98 ps 10
909 15:53:06.913887 RxClkDly_Margin_A1==88 ps 9
910 15:53:06.914382 TxDqDly_Margin_A1==78 ps 8
911 15:53:06.919480 TrainedVREFDQ_A0==78
912 15:53:06.920004 TrainedVREFDQ_A1==77
913 15:53:06.920473 VrefDac_Margin_A0==23
914 15:53:06.925109 DeviceVref_Margin_A0==36
915 15:53:06.925602 VrefDac_Margin_A1==22
916 15:53:06.930679 DeviceVref_Margin_A1==37
917 15:53:06.931164
918 15:53:06.931623 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
919 15:53:06.932105
920 15:53:06.964339 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000019 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000062
921 15:53:06.964885 2D training succeed
922 15:53:06.969919 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
923 15:53:06.975479 auto size-- 65535DDR cs0 size: 2048MB
924 15:53:06.975975 DDR cs1 size: 2048MB
925 15:53:06.981122 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
926 15:53:06.981614 cs0 DataBus test pass
927 15:53:06.986669 cs1 DataBus test pass
928 15:53:06.987163 cs0 AddrBus test pass
929 15:53:06.987622 cs1 AddrBus test pass
930 15:53:06.988109
931 15:53:06.992291 100bdlr_step_size ps== 478
932 15:53:06.992795 result report
933 15:53:06.997867 boot times 0Enable ddr reg access
934 15:53:07.003071 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
935 15:53:07.016867 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
936 15:53:07.672362 bl2z: ptr: 05129330, size: 00001e40
937 15:53:07.677821 0.0;M3 CHK:0;cm4_sp_mode 0
938 15:53:07.678383 MVN_1=0x00000000
939 15:53:07.678852 MVN_2=0x00000000
940 15:53:07.683436 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
941 15:53:07.683962 OPS=0x04
942 15:53:07.689289 ring efuse init
943 15:53:07.694931 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
944 15:53:07.695437 [0.017319 Inits done]
945 15:53:07.695895 secure task start!
946 15:53:07.701538 high task start!
947 15:53:07.702027 low task start!
948 15:53:07.702483 run into bl31
949 15:53:07.710218 NOTICE: BL31: v1.3(release):4fc40b1
950 15:53:07.717987 NOTICE: BL31: Built : 15:57:33, May 22 2019
951 15:53:07.718484 NOTICE: BL31: G12A normal boot!
952 15:53:07.733454 NOTICE: BL31: BL33 decompress pass
953 15:53:07.738250 ERROR: Error initializing runtime service opteed_fast
954 15:53:09.077635 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
955 15:53:09.078266 bl2_stage_init 0x01
956 15:53:09.078738 bl2_stage_init 0x81
957 15:53:09.083258 hw id: 0x0000 - pwm id 0x01
958 15:53:09.083743 bl2_stage_init 0xc1
959 15:53:09.084235 bl2_stage_init 0x02
960 15:53:09.084690
961 15:53:09.088781 L0:00000000
962 15:53:09.089260 L1:00000703
963 15:53:09.089715 L2:00008067
964 15:53:09.090161 L3:15000000
965 15:53:09.090603 S1:00000000
966 15:53:09.092148 B2:20282000
967 15:53:09.092634 B1:a0f83180
968 15:53:09.093085
969 15:53:09.093535 TE: 73546
970 15:53:09.093982
971 15:53:09.103341 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
972 15:53:09.103831
973 15:53:09.104322 Board ID = 1
974 15:53:09.104771 Set cpu clk to 24M
975 15:53:09.105213 Set clk81 to 24M
976 15:53:09.109552 Use GP1_pll as DSU clk.
977 15:53:09.110028 DSU clk: 1200 Mhz
978 15:53:09.110478 CPU clk: 1200 MHz
979 15:53:09.114487 Set clk81 to 166.6M
980 15:53:09.120154 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
981 15:53:09.120635 board id: 1
982 15:53:09.127965 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
983 15:53:09.138621 fw parse done
984 15:53:09.144685 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
985 15:53:09.186441 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
986 15:53:09.198186 PIEI prepare done
987 15:53:09.198672 fastboot data load
988 15:53:09.199133 fastboot data verify
989 15:53:09.203793 verify result: 266
990 15:53:09.209397 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
991 15:53:09.209882 LPDDR4 probe
992 15:53:09.210333 ddr clk to 1584MHz
993 15:53:09.216485 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
994 15:53:09.253570
995 15:53:09.254069 dmc_version 0001
996 15:53:09.260390 Check phy result
997 15:53:09.267323 INFO : End of CA training
998 15:53:09.267808 INFO : End of initialization
999 15:53:09.272815 INFO : Training has run successfully!
1000 15:53:09.273299 Check phy result
1001 15:53:09.278453 INFO : End of initialization
1002 15:53:09.278936 INFO : End of read enable training
1003 15:53:09.281759 INFO : End of fine write leveling
1004 15:53:09.287114 INFO : End of Write leveling coarse delay
1005 15:53:09.292690 INFO : Training has run successfully!
1006 15:53:09.293188 Check phy result
1007 15:53:09.293631 INFO : End of initialization
1008 15:53:09.298227 INFO : End of read dq deskew training
1009 15:53:09.301842 INFO : End of MPR read delay center optimization
1010 15:53:09.307453 INFO : End of write delay center optimization
1011 15:53:09.313025 INFO : End of read delay center optimization
1012 15:53:09.313518 INFO : End of max read latency training
1013 15:53:09.318697 INFO : Training has run successfully!
1014 15:53:09.319188 1D training succeed
1015 15:53:09.326759 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1016 15:53:09.373347 Check phy result
1017 15:53:09.373834 INFO : End of initialization
1018 15:53:09.396786 INFO : End of 2D read delay Voltage center optimization
1019 15:53:09.415929 INFO : End of 2D read delay Voltage center optimization
1020 15:53:09.466836 INFO : End of 2D write delay Voltage center optimization
1021 15:53:09.516920 INFO : End of 2D write delay Voltage center optimization
1022 15:53:09.522559 INFO : Training has run successfully!
1023 15:53:09.523048
1024 15:53:09.523512 channel==0
1025 15:53:09.528164 RxClkDly_Margin_A0==69 ps 7
1026 15:53:09.528652 TxDqDly_Margin_A0==98 ps 10
1027 15:53:09.531504 RxClkDly_Margin_A1==88 ps 9
1028 15:53:09.532017 TxDqDly_Margin_A1==98 ps 10
1029 15:53:09.537003 TrainedVREFDQ_A0==74
1030 15:53:09.537496 TrainedVREFDQ_A1==75
1031 15:53:09.542538 VrefDac_Margin_A0==24
1032 15:53:09.543026 DeviceVref_Margin_A0==40
1033 15:53:09.543476 VrefDac_Margin_A1==23
1034 15:53:09.548230 DeviceVref_Margin_A1==39
1035 15:53:09.548715
1036 15:53:09.549170
1037 15:53:09.549621 channel==1
1038 15:53:09.550061 RxClkDly_Margin_A0==78 ps 8
1039 15:53:09.551574 TxDqDly_Margin_A0==98 ps 10
1040 15:53:09.557249 RxClkDly_Margin_A1==78 ps 8
1041 15:53:09.557731 TxDqDly_Margin_A1==78 ps 8
1042 15:53:09.558181 TrainedVREFDQ_A0==78
1043 15:53:09.562789 TrainedVREFDQ_A1==75
1044 15:53:09.563275 VrefDac_Margin_A0==22
1045 15:53:09.568378 DeviceVref_Margin_A0==36
1046 15:53:09.568857 VrefDac_Margin_A1==22
1047 15:53:09.569309 DeviceVref_Margin_A1==39
1048 15:53:09.569751
1049 15:53:09.577296 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1050 15:53:09.577780
1051 15:53:09.605318 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000015 00000016 dram_vref_reg_value 0x 00000062
1052 15:53:09.605835 2D training succeed
1053 15:53:09.616514 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1054 15:53:09.617018 auto size-- 65535DDR cs0 size: 2048MB
1055 15:53:09.617473 DDR cs1 size: 2048MB
1056 15:53:09.622084 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1057 15:53:09.622560 cs0 DataBus test pass
1058 15:53:09.627752 cs1 DataBus test pass
1059 15:53:09.628268 cs0 AddrBus test pass
1060 15:53:09.633318 cs1 AddrBus test pass
1061 15:53:09.633801
1062 15:53:09.634253 100bdlr_step_size ps== 464
1063 15:53:09.634706 result report
1064 15:53:09.638903 boot times 0Enable ddr reg access
1065 15:53:09.645381 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1066 15:53:09.659321 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
1067 15:53:10.315034 bl2z: ptr: 05129330, size: 00001e40
1068 15:53:10.323419 0.0;M3 CHK:0;cm4_sp_mode 0
1069 15:53:10.323942 MVN_1=0x00000000
1070 15:53:10.324435 MVN_2=0x00000000
1071 15:53:10.334871 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
1072 15:53:10.335360 OPS=0x04
1073 15:53:10.335816 ring efuse init
1074 15:53:10.340522 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
1075 15:53:10.341017 [0.017319 Inits done]
1076 15:53:10.341469 secure task start!
1077 15:53:10.347582 high task start!
1078 15:53:10.348091 low task start!
1079 15:53:10.348540 run into bl31
1080 15:53:10.356968 NOTICE: BL31: v1.3(release):4fc40b1
1081 15:53:10.364210 NOTICE: BL31: Built : 15:57:33, May 22 2019
1082 15:53:10.364696 NOTICE: BL31: G12A normal boot!
1083 15:53:10.380258 NOTICE: BL31: BL33 decompress pass
1084 15:53:10.386004 ERROR: Error initializing runtime service opteed_fast
1085 15:53:11.181535
1086 15:53:11.182137
1087 15:53:11.186905 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
1088 15:53:11.187394
1089 15:53:11.190369 Model: Libre Computer AML-S905D3-CC Solitude
1090 15:53:11.337351 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
1091 15:53:11.352152 DRAM: 2 GiB (effective 3.8 GiB)
1092 15:53:11.453628 Core: 406 devices, 33 uclasses, devicetree: separate
1093 15:53:11.459591 WDT: Not starting watchdog@f0d0
1094 15:53:11.484634 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1095 15:53:11.497116 Loading Environment from FAT... Card did not respond to voltage select! : -110
1096 15:53:11.502039 ** Bad device specification mmc 0 **
1097 15:53:11.512081 Card did not respond to voltage select! : -110
1098 15:53:11.519702 ** Bad device specification mmc 0 **
1099 15:53:11.520208 Couldn't find partition mmc 0
1100 15:53:11.528083 Card did not respond to voltage select! : -110
1101 15:53:11.533599 ** Bad device specification mmc 0 **
1102 15:53:11.534064 Couldn't find partition mmc 0
1103 15:53:11.537761 Error: could not access storage.
1104 15:53:11.835061 Net: eth0: ethernet@ff3f0000
1105 15:53:11.835678 starting USB...
1106 15:53:12.079770 Bus usb@ff500000: Register 3000140 NbrPorts 3
1107 15:53:12.080412 Starting the controller
1108 15:53:12.086628 USB XHCI 1.10
1109 15:53:14.742125 scanning bus usb@ff500000 for devices... SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
1110 15:53:14.742736 bl2_stage_init 0x01
1111 15:53:14.743204 bl2_stage_init 0x81
1112 15:53:14.747772 hw id: 0x0000 - pwm id 0x01
1113 15:53:14.748288 bl2_stage_init 0xc1
1114 15:53:14.753544 bl2_stage_init 0x02
1115 15:53:14.754020
1116 15:53:14.754477 L0:00000000
1117 15:53:14.754923 L1:00000703
1118 15:53:14.755369 L2:00008067
1119 15:53:14.755813 L3:15000000
1120 15:53:14.759056 S1:00000000
1121 15:53:14.759529 B2:20282000
1122 15:53:14.760005 B1:a0f83180
1123 15:53:14.760461
1124 15:53:14.760908 TE: 69651
1125 15:53:14.761357
1126 15:53:14.764524 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
1127 15:53:14.765011
1128 15:53:14.770107 Board ID = 1
1129 15:53:14.770586 Set cpu clk to 24M
1130 15:53:14.771036 Set clk81 to 24M
1131 15:53:14.775699 Use GP1_pll as DSU clk.
1132 15:53:14.776217 DSU clk: 1200 Mhz
1133 15:53:14.776668 CPU clk: 1200 MHz
1134 15:53:14.781443 Set clk81 to 166.6M
1135 15:53:14.786950 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
1136 15:53:14.787441 board id: 1
1137 15:53:14.794117 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1138 15:53:14.804766 fw parse done
1139 15:53:14.810765 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1140 15:53:14.853412 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1141 15:53:14.864304 PIEI prepare done
1142 15:53:14.864785 fastboot data load
1143 15:53:14.865242 fastboot data verify
1144 15:53:14.869899 verify result: 266
1145 15:53:14.875505 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
1146 15:53:14.876013 LPDDR4 probe
1147 15:53:14.876473 ddr clk to 1584MHz
1148 15:53:14.883584 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1149 15:53:14.920734
1150 15:53:14.921242 dmc_version 0001
1151 15:53:14.927435 Check phy result
1152 15:53:14.933335 INFO : End of CA training
1153 15:53:14.933820 INFO : End of initialization
1154 15:53:14.938997 INFO : Training has run successfully!
1155 15:53:14.939480 Check phy result
1156 15:53:14.944511 INFO : End of initialization
1157 15:53:14.945002 INFO : End of read enable training
1158 15:53:14.950151 INFO : End of fine write leveling
1159 15:53:14.955722 INFO : End of Write leveling coarse delay
1160 15:53:14.956227 INFO : Training has run successfully!
1161 15:53:14.956683 Check phy result
1162 15:53:14.961325 INFO : End of initialization
1163 15:53:14.961801 INFO : End of read dq deskew training
1164 15:53:14.967002 INFO : End of MPR read delay center optimization
1165 15:53:14.972563 INFO : End of write delay center optimization
1166 15:53:14.978203 INFO : End of read delay center optimization
1167 15:53:14.978674 INFO : End of max read latency training
1168 15:53:14.983771 INFO : Training has run successfully!
1169 15:53:14.984289 1D training succeed
1170 15:53:14.992465 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1171 15:53:15.040562 Check phy result
1172 15:53:15.041061 INFO : End of initialization
1173 15:53:15.062951 INFO : End of 2D read delay Voltage center optimization
1174 15:53:15.082056 INFO : End of 2D read delay Voltage center optimization
1175 15:53:15.133926 INFO : End of 2D write delay Voltage center optimization
1176 15:53:15.183216 INFO : End of 2D write delay Voltage center optimization
1177 15:53:15.188831 INFO : Training has run successfully!
1178 15:53:15.189320
1179 15:53:15.189780 channel==0
1180 15:53:15.194331 RxClkDly_Margin_A0==88 ps 9
1181 15:53:15.194841 TxDqDly_Margin_A0==98 ps 10
1182 15:53:15.199939 RxClkDly_Margin_A1==78 ps 8
1183 15:53:15.200444 TxDqDly_Margin_A1==88 ps 9
1184 15:53:15.200896 TrainedVREFDQ_A0==75
1185 15:53:15.205677 TrainedVREFDQ_A1==75
1186 15:53:15.206158 VrefDac_Margin_A0==24
1187 15:53:15.206604 DeviceVref_Margin_A0==39
1188 15:53:15.211139 VrefDac_Margin_A1==22
1189 15:53:15.211624 DeviceVref_Margin_A1==39
1190 15:53:15.212107
1191 15:53:15.212559
1192 15:53:15.213007 channel==1
1193 15:53:15.216831 RxClkDly_Margin_A0==78 ps 8
1194 15:53:15.217306 TxDqDly_Margin_A0==98 ps 10
1195 15:53:15.222621 RxClkDly_Margin_A1==88 ps 9
1196 15:53:15.223092 TxDqDly_Margin_A1==88 ps 9
1197 15:53:15.227957 TrainedVREFDQ_A0==78
1198 15:53:15.228460 TrainedVREFDQ_A1==78
1199 15:53:15.228910 VrefDac_Margin_A0==22
1200 15:53:15.233602 DeviceVref_Margin_A0==36
1201 15:53:15.234077 VrefDac_Margin_A1==22
1202 15:53:15.239180 DeviceVref_Margin_A1==36
1203 15:53:15.239656
1204 15:53:15.240134 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1205 15:53:15.240584
1206 15:53:15.272807 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000016 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000014 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000061
1207 15:53:15.273344 2D training succeed
1208 15:53:15.278510 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1209 15:53:15.283794 auto size-- 65535DDR cs0 size: 2048MB
1210 15:53:15.284351 DDR cs1 size: 2048MB
1211 15:53:15.289494 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1212 15:53:15.289985 cs0 DataBus test pass
1213 15:53:15.295004 cs1 DataBus test pass
1214 15:53:15.295482 cs0 AddrBus test pass
1215 15:53:15.295931 cs1 AddrBus test pass
1216 15:53:15.296414
1217 15:53:15.300600 100bdlr_step_size ps== 478
1218 15:53:15.301093 result report
1219 15:53:15.306203 boot times 0Enable ddr reg access
1220 15:53:15.310451 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1221 15:53:15.324330 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
1222 15:53:15.980320 bl2z: ptr: 05129330, size: 00001e40
1223 15:53:15.987807 0.0;M3 CHK:0;cm4_sp_mode 0
1224 15:53:15.988411 MVN_1=0x00000000
1225 15:53:15.988880 MVN_2=0x00000000
1226 15:53:15.999334 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
1227 15:53:15.999830 OPS=0x04
1228 15:53:16.000327 ring efuse init
1229 15:53:16.004942 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
1230 15:53:16.005441 [0.017319 Inits done]
1231 15:53:16.005892 secure task start!
1232 15:53:16.012364 high task start!
1233 15:53:16.012857 low task start!
1234 15:53:16.013311 run into bl31
1235 15:53:16.020967 NOTICE: BL31: v1.3(release):4fc40b1
1236 15:53:16.028761 NOTICE: BL31: Built : 15:57:33, May 22 2019
1237 15:53:16.029264 NOTICE: BL31: G12A normal boot!
1238 15:53:16.044435 NOTICE: BL31: BL33 decompress pass
1239 15:53:16.050110 ERROR: Error initializing runtime service opteed_fast
1240 15:53:18.791924 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
1241 15:53:18.792715 bl2_stage_init 0x01
1242 15:53:18.793252 bl2_stage_init 0x81
1243 15:53:18.797469 hw id: 0x0000 - pwm id 0x01
1244 15:53:18.798076 bl2_stage_init 0xc1
1245 15:53:18.803064 bl2_stage_init 0x02
1246 15:53:18.803639
1247 15:53:18.804082 L0:00000000
1248 15:53:18.804484 L1:00000703
1249 15:53:18.804875 L2:00008067
1250 15:53:18.805263 L3:15000000
1251 15:53:18.808509 S1:00000000
1252 15:53:18.809062 B2:20282000
1253 15:53:18.809453 B1:a0f83180
1254 15:53:18.809840
1255 15:53:18.810227 TE: 69489
1256 15:53:18.810622
1257 15:53:18.814085 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
1258 15:53:18.814551
1259 15:53:18.819810 Board ID = 1
1260 15:53:18.820499 Set cpu clk to 24M
1261 15:53:18.820921 Set clk81 to 24M
1262 15:53:18.825369 Use GP1_pll as DSU clk.
1263 15:53:18.825990 DSU clk: 1200 Mhz
1264 15:53:18.826397 CPU clk: 1200 MHz
1265 15:53:18.831137 Set clk81 to 166.6M
1266 15:53:18.836666 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
1267 15:53:18.837350 board id: 1
1268 15:53:18.843956 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1269 15:53:18.854451 fw parse done
1270 15:53:18.860446 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1271 15:53:18.903046 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1272 15:53:18.913984 PIEI prepare done
1273 15:53:18.914425 fastboot data load
1274 15:53:18.914695 fastboot data verify
1275 15:53:18.919567 verify result: 266
1276 15:53:18.925100 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
1277 15:53:18.925509 LPDDR4 probe
1278 15:53:18.925772 ddr clk to 1584MHz
1279 15:53:18.933128 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1280 15:53:18.970401
1281 15:53:18.970825 dmc_version 0001
1282 15:53:18.977122 Check phy result
1283 15:53:18.983043 INFO : End of CA training
1284 15:53:18.983506 INFO : End of initialization
1285 15:53:18.988596 INFO : Training has run successfully!
1286 15:53:18.989044 Check phy result
1287 15:53:18.994145 INFO : End of initialization
1288 15:53:18.994722 INFO : End of read enable training
1289 15:53:18.999850 INFO : End of fine write leveling
1290 15:53:19.005380 INFO : End of Write leveling coarse delay
1291 15:53:19.006022 INFO : Training has run successfully!
1292 15:53:19.006349 Check phy result
1293 15:53:19.011048 INFO : End of initialization
1294 15:53:19.011652 INFO : End of read dq deskew training
1295 15:53:19.016549 INFO : End of MPR read delay center optimization
1296 15:53:19.022265 INFO : End of write delay center optimization
1297 15:53:19.028036 INFO : End of read delay center optimization
1298 15:53:19.028727 INFO : End of max read latency training
1299 15:53:19.033556 INFO : Training has run successfully!
1300 15:53:19.034186 1D training succeed
1301 15:53:19.042683 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1302 15:53:19.090319 Check phy result
1303 15:53:19.090954 INFO : End of initialization
1304 15:53:19.112692 INFO : End of 2D read delay Voltage center optimization
1305 15:53:19.131805 INFO : End of 2D read delay Voltage center optimization
1306 15:53:19.183757 INFO : End of 2D write delay Voltage center optimization
1307 15:53:19.232960 INFO : End of 2D write delay Voltage center optimization
1308 15:53:19.238453 INFO : Training has run successfully!
1309 15:53:19.239074
1310 15:53:19.239598 channel==0
1311 15:53:19.244023 RxClkDly_Margin_A0==88 ps 9
1312 15:53:19.244619 TxDqDly_Margin_A0==98 ps 10
1313 15:53:19.249547 RxClkDly_Margin_A1==78 ps 8
1314 15:53:19.250122 TxDqDly_Margin_A1==98 ps 10
1315 15:53:19.250590 TrainedVREFDQ_A0==74
1316 15:53:19.255174 TrainedVREFDQ_A1==75
1317 15:53:19.255698 VrefDac_Margin_A0==24
1318 15:53:19.256193 DeviceVref_Margin_A0==40
1319 15:53:19.260770 VrefDac_Margin_A1==23
1320 15:53:19.261285 DeviceVref_Margin_A1==39
1321 15:53:19.261740
1322 15:53:19.262188
1323 15:53:19.266340 channel==1
1324 15:53:19.266866 RxClkDly_Margin_A0==78 ps 8
1325 15:53:19.267322 TxDqDly_Margin_A0==98 ps 10
1326 15:53:19.271918 RxClkDly_Margin_A1==88 ps 9
1327 15:53:19.272459 TxDqDly_Margin_A1==88 ps 9
1328 15:53:19.277566 TrainedVREFDQ_A0==78
1329 15:53:19.278089 TrainedVREFDQ_A1==77
1330 15:53:19.278542 VrefDac_Margin_A0==22
1331 15:53:19.283172 DeviceVref_Margin_A0==36
1332 15:53:19.283689 VrefDac_Margin_A1==22
1333 15:53:19.288799 DeviceVref_Margin_A1==37
1334 15:53:19.289319
1335 15:53:19.289780 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1336 15:53:19.290228
1337 15:53:19.322304 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000019 00000015 00000017 00000014 00000014 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000016 00000016 dram_vref_reg_value 0x 00000062
1338 15:53:19.322917 2D training succeed
1339 15:53:19.327938 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1340 15:53:19.333580 auto size-- 65535DDR cs0 size: 2048MB
1341 15:53:19.334109 DDR cs1 size: 2048MB
1342 15:53:19.339193 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1343 15:53:19.339718 cs0 DataBus test pass
1344 15:53:19.344758 cs1 DataBus test pass
1345 15:53:19.345280 cs0 AddrBus test pass
1346 15:53:19.345742 cs1 AddrBus test pass
1347 15:53:19.346190
1348 15:53:19.350380 100bdlr_step_size ps== 478
1349 15:53:19.350920 result report
1350 15:53:19.356012 boot times 0Enable ddr reg access
1351 15:53:19.361267 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1352 15:53:19.374971 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
1353 15:53:20.029514 bl2z: ptr: 05129330, size: 00001e40
1354 15:53:20.038226 0.0;M3 CHK:0;cm4_sp_mode 0
1355 15:53:20.038815 MVN_1=0x00000000
1356 15:53:20.039280 MVN_2=0x00000000
1357 15:53:20.049693 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
1358 15:53:20.050243 OPS=0x04
1359 15:53:20.050708 ring efuse init
1360 15:53:20.055347 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
1361 15:53:20.055876 [0.017320 Inits done]
1362 15:53:20.056377 secure task start!
1363 15:53:20.063269 high task start!
1364 15:53:20.063784 low task start!
1365 15:53:20.064289 run into bl31
1366 15:53:20.071814 NOTICE: BL31: v1.3(release):4fc40b1
1367 15:53:20.079601 NOTICE: BL31: Built : 15:57:33, May 22 2019
1368 15:53:20.080151 NOTICE: BL31: G12A normal boot!
1369 15:53:20.095128 NOTICE: BL31: BL33 decompress pass
1370 15:53:20.100663 ERROR: Error initializing runtime service opteed_fast
1371 15:53:21.495052 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
1372 15:53:21.495454 bl2_stage_init 0x01
1373 15:53:21.495733 bl2_stage_init 0x81
1374 15:53:21.500519 hw id: 0x0000 - pwm id 0x01
1375 15:53:21.500824 bl2_stage_init 0xc1
1376 15:53:21.501072 bl2_stage_init 0x02
1377 15:53:21.501320
1378 15:53:21.506116 L0:00000000
1379 15:53:21.506413 L1:00000703
1380 15:53:21.506642 L2:00008067
1381 15:53:21.506875 L3:15000000
1382 15:53:21.507123 S1:00000000
1383 15:53:21.511727 B2:20282000
1384 15:53:21.512046 B1:a0f83180
1385 15:53:21.512295
1386 15:53:21.512541 TE: 71668
1387 15:53:21.512774
1388 15:53:21.517328 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
1389 15:53:21.517630
1390 15:53:21.522925 Board ID = 1
1391 15:53:21.523220 Set cpu clk to 24M
1392 15:53:21.523463 Set clk81 to 24M
1393 15:53:21.528522 Use GP1_pll as DSU clk.
1394 15:53:21.528820 DSU clk: 1200 Mhz
1395 15:53:21.529066 CPU clk: 1200 MHz
1396 15:53:21.529305 Set clk81 to 166.6M
1397 15:53:21.539717 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
1398 15:53:21.540062 board id: 1
1399 15:53:21.545191 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1400 15:53:21.557036 fw parse done
1401 15:53:21.563008 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1402 15:53:21.605302 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1403 15:53:21.617456 PIEI prepare done
1404 15:53:21.617824 fastboot data load
1405 15:53:21.618061 fastboot data verify
1406 15:53:21.622913 verify result: 266
1407 15:53:21.628491 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
1408 15:53:21.628819 LPDDR4 probe
1409 15:53:21.629056 ddr clk to 1584MHz
1410 15:53:21.636528 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1411 15:53:21.674171
1412 15:53:21.674743 dmc_version 0001
1413 15:53:21.681305 Check phy result
1414 15:53:21.687159 INFO : End of CA training
1415 15:53:21.687735 INFO : End of initialization
1416 15:53:21.692730 INFO : Training has run successfully!
1417 15:53:21.693137 Check phy result
1418 15:53:21.698359 INFO : End of initialization
1419 15:53:21.698779 INFO : End of read enable training
1420 15:53:21.703994 INFO : End of fine write leveling
1421 15:53:21.709517 INFO : End of Write leveling coarse delay
1422 15:53:21.709970 INFO : Training has run successfully!
1423 15:53:21.710621 Check phy result
1424 15:53:21.715094 INFO : End of initialization
1425 15:53:21.715441 INFO : End of read dq deskew training
1426 15:53:21.720726 INFO : End of MPR read delay center optimization
1427 15:53:21.726302 INFO : End of write delay center optimization
1428 15:53:21.731952 INFO : End of read delay center optimization
1429 15:53:21.732323 INFO : End of max read latency training
1430 15:53:21.737542 INFO : Training has run successfully!
1431 15:53:21.737881 1D training succeed
1432 15:53:21.746740 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1433 15:53:21.795080 Check phy result
1434 15:53:21.795474 INFO : End of initialization
1435 15:53:21.822715 INFO : End of 2D read delay Voltage center optimization
1436 15:53:21.845914 INFO : End of 2D read delay Voltage center optimization
1437 15:53:21.903403 INFO : End of 2D write delay Voltage center optimization
1438 15:53:21.957419 INFO : End of 2D write delay Voltage center optimization
1439 15:53:21.962998 INFO : Training has run successfully!
1440 15:53:21.963610
1441 15:53:21.964133 channel==0
1442 15:53:21.968599 RxClkDly_Margin_A0==88 ps 9
1443 15:53:21.969171 TxDqDly_Margin_A0==98 ps 10
1444 15:53:21.974160 RxClkDly_Margin_A1==69 ps 7
1445 15:53:21.974723 TxDqDly_Margin_A1==98 ps 10
1446 15:53:21.975190 TrainedVREFDQ_A0==74
1447 15:53:21.979768 TrainedVREFDQ_A1==75
1448 15:53:21.980367 VrefDac_Margin_A0==22
1449 15:53:21.980834 DeviceVref_Margin_A0==40
1450 15:53:21.985342 VrefDac_Margin_A1==23
1451 15:53:21.985908 DeviceVref_Margin_A1==39
1452 15:53:21.986371
1453 15:53:21.986856
1454 15:53:21.990957 channel==1
1455 15:53:21.991522 RxClkDly_Margin_A0==88 ps 9
1456 15:53:21.992019 TxDqDly_Margin_A0==98 ps 10
1457 15:53:21.996541 RxClkDly_Margin_A1==88 ps 9
1458 15:53:21.997101 TxDqDly_Margin_A1==88 ps 9
1459 15:53:22.002174 TrainedVREFDQ_A0==78
1460 15:53:22.002747 TrainedVREFDQ_A1==76
1461 15:53:22.003216 VrefDac_Margin_A0==23
1462 15:53:22.007759 DeviceVref_Margin_A0==36
1463 15:53:22.008340 VrefDac_Margin_A1==22
1464 15:53:22.013351 DeviceVref_Margin_A1==38
1465 15:53:22.013905
1466 15:53:22.014373 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1467 15:53:22.014826
1468 15:53:22.046908 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000014 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
1469 15:53:22.047561 2D training succeed
1470 15:53:22.052570 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1471 15:53:22.058191 auto size-- 65535DDR cs0 size: 2048MB
1472 15:53:22.058766 DDR cs1 size: 2048MB
1473 15:53:22.063764 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1474 15:53:22.064362 cs0 DataBus test pass
1475 15:53:22.069288 cs1 DataBus test pass
1476 15:53:22.069683 cs0 AddrBus test pass
1477 15:53:22.069973 cs1 AddrBus test pass
1478 15:53:22.070220
1479 15:53:22.074847 100bdlr_step_size ps== 464
1480 15:53:22.075221 result report
1481 15:53:22.080437 boot times 0Enable ddr reg access
1482 15:53:22.084763 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1483 15:53:22.098612 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
1484 15:53:22.759124 bl2z: ptr: 05129330, size: 00001e40
1485 15:53:22.767735 0.0;M3 CHK:0;cm4_sp_mode 0
1486 15:53:22.768403 MVN_1=0x00000000
1487 15:53:22.768884 MVN_2=0x00000000
1488 15:53:22.778967 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
1489 15:53:22.779587 OPS=0x04
1490 15:53:22.780100 ring efuse init
1491 15:53:22.781969 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
1492 15:53:22.788094 [0.017354 Inits done]
1493 15:53:22.788674 secure task start!
1494 15:53:22.789151 high task start!
1495 15:53:22.789611 low task start!
1496 15:53:22.792328 run into bl31
1497 15:53:22.801004 NOTICE: BL31: v1.3(release):4fc40b1
1498 15:53:22.808680 NOTICE: BL31: Built : 15:57:33, May 22 2019
1499 15:53:22.809060 NOTICE: BL31: G12A normal boot!
1500 15:53:22.824248 NOTICE: BL31: BL33 decompress pass
1501 15:53:22.830021 ERROR: Error initializing runtime service opteed_fast
1502 15:53:23.625355
1503 15:53:23.626031
1504 15:53:23.630795 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
1505 15:53:23.631346
1506 15:53:23.634298 Model: Libre Computer AML-S905D3-CC Solitude
1507 15:53:23.781285 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
1508 15:53:23.795817 DRAM: 2 GiB (effective 3.8 GiB)
1509 15:53:23.897596 Core: 406 devices, 33 uclasses, devicetree: separate
1510 15:53:23.903525 WDT: Not starting watchdog@f0d0
1511 15:53:23.928555 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1512 15:53:23.940783 Loading Environment from FAT... Card did not respond to voltage select! : -110
1513 15:53:23.945865 ** Bad device specification mmc 0 **
1514 15:53:23.955876 Card did not respond to voltage select! : -110
1515 15:53:23.963490 ** Bad device specification mmc 0 **
1516 15:53:23.964052 Couldn't find partition mmc 0
1517 15:53:23.971852 Card did not respond to voltage select! : -110
1518 15:53:23.977369 ** Bad device specification mmc 0 **
1519 15:53:23.977899 Couldn't find partition mmc 0
1520 15:53:23.982420 Error: could not access storage.
1521 15:53:24.278919 Net: eth0: ethernet@ff3f0000
1522 15:53:24.279569 starting USB...
1523 15:53:24.523573 Bus usb@ff500000: Register 3000140 NbrPorts 3
1524 15:53:24.524269 Starting the controller
1525 15:53:24.530519 USB XHCI 1.10
1526 15:53:26.084692 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1527 15:53:26.093025 scanning usb for storage devices... 0 Storage Device(s) found
1529 15:53:26.144768 Hit any key to stop autoboot: 1
1530 15:53:26.146064 end: 2.4.2 bootloader-interrupt (duration 00:00:42) [common]
1531 15:53:26.146780 start: 2.4.3 bootloader-commands (timeout 00:04:18) [common]
1532 15:53:26.147318 Setting prompt string to ['=>']
1533 15:53:26.147862 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:18)
1534 15:53:26.158112 0
1535 15:53:26.159126 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1537 15:53:26.260663 => setenv autoload no
1538 15:53:26.261401 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1539 15:53:26.266247 setenv autoload no
1541 15:53:26.367771 => setenv initrd_high 0xffffffff
1542 15:53:26.368478 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1543 15:53:26.372064 setenv initrd_high 0xffffffff
1545 15:53:26.473473 => setenv fdt_high 0xffffffff
1546 15:53:26.474087 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1547 15:53:26.477682 setenv fdt_high 0xffffffff
1549 15:53:26.579124 => dhcp
1550 15:53:26.579788 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1551 15:53:26.584077 dhcp
1552 15:53:27.789242 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete... done
1553 15:53:27.789863 Speed: 1000, full duplex
1554 15:53:27.790303 BOOTP broadcast 1
1555 15:53:28.037449 BOOTP broadcast 2
1556 15:53:28.538128 BOOTP broadcast 3
1557 15:53:29.539225 BOOTP broadcast 4
1558 15:53:31.540251 BOOTP broadcast 5
1559 15:53:31.553914 DHCP client bound to address 192.168.6.12 (3763 ms)
1561 15:53:31.655696 => setenv serverip 192.168.6.2
1562 15:53:31.656491 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1563 15:53:31.660070 setenv serverip 192.168.6.2
1565 15:53:31.761547 => tftpboot 0x01080000 786659/tftp-deploy-bb4slxeq/kernel/uImage
1566 15:53:31.762291 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1567 15:53:31.769080 tftpboot 0x01080000 786659/tftp-deploy-bb4slxeq/kernel/uImage
1568 15:53:31.769738 Speed: 1000, full duplex
1569 15:53:31.770192 Using ethernet@ff3f0000 device
1570 15:53:31.774639 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
1571 15:53:31.780057 Filename '786659/tftp-deploy-bb4slxeq/kernel/uImage'.
1572 15:53:31.784451 Load address: 0x1080000
1573 15:53:35.261541 Loading: *################################################## 43.6 MiB
1574 15:53:35.262194 12.5 MiB/s
1575 15:53:35.262648 done
1576 15:53:35.265143 Bytes transferred = 45713984 (2b98a40 hex)
1578 15:53:35.366737 => tftpboot 0x08000000 786659/tftp-deploy-bb4slxeq/ramdisk/ramdisk.cpio.gz.uboot
1579 15:53:35.367550 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:09)
1580 15:53:35.374103 tftpboot 0x08000000 786659/tftp-deploy-bb4slxeq/ramdisk/ramdisk.cpio.gz.uboot
1581 15:53:35.374605 Speed: 1000, full duplex
1582 15:53:35.375050 Using ethernet@ff3f0000 device
1583 15:53:35.379592 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
1584 15:53:35.388502 Filename '786659/tftp-deploy-bb4slxeq/ramdisk/ramdisk.cpio.gz.uboot'.
1585 15:53:35.388988 Load address: 0x8000000
1586 15:53:45.582811 Loading: *###############T ######################## UDP wrong checksum 000000ff 00007911
1587 15:53:45.612522 UDP wrong checksum 000000ff 00000b04
1588 15:53:47.261485 ########## UDP wrong checksum 0000000f 00003f75
1589 15:53:52.262957 T UDP wrong checksum 0000000f 00003f75
1590 15:54:02.265221 T T UDP wrong checksum 0000000f 00003f75
1591 15:54:02.723724 UDP wrong checksum 000000ff 0000cf93
1592 15:54:02.753550 UDP wrong checksum 000000ff 00005886
1593 15:54:09.322968 T UDP wrong checksum 000000ff 00002bce
1594 15:54:09.373712 UDP wrong checksum 000000ff 0000b1c0
1595 15:54:22.269410 T T T UDP wrong checksum 0000000f 00003f75
1596 15:54:37.272994 T T
1597 15:54:37.274091 Retry count exceeded; starting again
1599 15:54:37.276560 end: 2.4.3 bootloader-commands (duration 00:01:11) [common]
1602 15:54:37.278776 end: 2.4 uboot-commands (duration 00:01:53) [common]
1604 15:54:37.281678 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1606 15:54:37.283019 end: 2 uboot-action (duration 00:01:53) [common]
1608 15:54:37.284720 Cleaning after the job
1609 15:54:37.285311 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/786659/tftp-deploy-bb4slxeq/ramdisk
1610 15:54:37.287757 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/786659/tftp-deploy-bb4slxeq/kernel
1611 15:54:37.344480 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/786659/tftp-deploy-bb4slxeq/dtb
1612 15:54:37.345276 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/786659/tftp-deploy-bb4slxeq/modules
1613 15:54:37.376986 start: 4.1 power-off (timeout 00:00:30) [common]
1614 15:54:37.377672 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
1615 15:54:37.414142 >> OK - accepted request
1616 15:54:37.416440 Returned 0 in 0 seconds
1617 15:54:37.517743 end: 4.1 power-off (duration 00:00:00) [common]
1619 15:54:37.518772 start: 4.2 read-feedback (timeout 00:10:00) [common]
1620 15:54:37.519433 Listened to connection for namespace 'common' for up to 1s
1621 15:54:38.520347 Finalising connection for namespace 'common'
1622 15:54:38.520847 Disconnecting from shell: Finalise
1623 15:54:38.521135 =>
1624 15:54:38.621958 end: 4.2 read-feedback (duration 00:00:01) [common]
1625 15:54:38.622831 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/786659
1626 15:54:39.377208 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/786659
1627 15:54:39.377838 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.