Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 15:55:04.077294 lava-dispatcher, installed at version: 2024.01
2 15:55:04.078082 start: 0 validate
3 15:55:04.078544 Start time: 2024-10-01 15:55:04.078514+00:00 (UTC)
4 15:55:04.079078 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 15:55:04.079613 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 15:55:04.121888 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 15:55:04.122448 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fmaster%2Frenesas-devel-2024-10-01-v6.12-rc1%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 15:55:04.152892 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 15:55:04.153515 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fmaster%2Frenesas-devel-2024-10-01-v6.12-rc1%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 15:55:04.187291 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 15:55:04.187764 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 15:55:04.217894 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 15:55:04.218357 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fmaster%2Frenesas-devel-2024-10-01-v6.12-rc1%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 15:55:04.259721 validate duration: 0.18
16 15:55:04.260592 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 15:55:04.260946 start: 1.1 download-retry (timeout 00:10:00) [common]
18 15:55:04.261265 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 15:55:04.261882 Not decompressing ramdisk as can be used compressed.
20 15:55:04.262355 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 15:55:04.262639 saving as /var/lib/lava/dispatcher/tmp/786675/tftp-deploy-r5v_txwe/ramdisk/initrd.cpio.gz
22 15:55:04.262929 total size: 5628140 (5 MB)
23 15:55:04.306467 progress 0 % (0 MB)
24 15:55:04.313804 progress 5 % (0 MB)
25 15:55:04.321465 progress 10 % (0 MB)
26 15:55:04.328333 progress 15 % (0 MB)
27 15:55:04.334068 progress 20 % (1 MB)
28 15:55:04.337672 progress 25 % (1 MB)
29 15:55:04.341665 progress 30 % (1 MB)
30 15:55:04.345605 progress 35 % (1 MB)
31 15:55:04.349213 progress 40 % (2 MB)
32 15:55:04.353146 progress 45 % (2 MB)
33 15:55:04.356675 progress 50 % (2 MB)
34 15:55:04.360648 progress 55 % (2 MB)
35 15:55:04.364606 progress 60 % (3 MB)
36 15:55:04.368169 progress 65 % (3 MB)
37 15:55:04.372117 progress 70 % (3 MB)
38 15:55:04.375711 progress 75 % (4 MB)
39 15:55:04.379527 progress 80 % (4 MB)
40 15:55:04.382891 progress 85 % (4 MB)
41 15:55:04.386580 progress 90 % (4 MB)
42 15:55:04.390188 progress 95 % (5 MB)
43 15:55:04.393467 progress 100 % (5 MB)
44 15:55:04.394137 5 MB downloaded in 0.13 s (40.92 MB/s)
45 15:55:04.394702 end: 1.1.1 http-download (duration 00:00:00) [common]
47 15:55:04.395591 end: 1.1 download-retry (duration 00:00:00) [common]
48 15:55:04.395945 start: 1.2 download-retry (timeout 00:10:00) [common]
49 15:55:04.396253 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 15:55:04.396723 downloading http://storage.kernelci.org/renesas/master/renesas-devel-2024-10-01-v6.12-rc1/arm64/defconfig/gcc-12/kernel/Image
51 15:55:04.396975 saving as /var/lib/lava/dispatcher/tmp/786675/tftp-deploy-r5v_txwe/kernel/Image
52 15:55:04.397185 total size: 45713920 (43 MB)
53 15:55:04.397393 No compression specified
54 15:55:04.439632 progress 0 % (0 MB)
55 15:55:04.467509 progress 5 % (2 MB)
56 15:55:04.495641 progress 10 % (4 MB)
57 15:55:04.523745 progress 15 % (6 MB)
58 15:55:04.551437 progress 20 % (8 MB)
59 15:55:04.578788 progress 25 % (10 MB)
60 15:55:04.606550 progress 30 % (13 MB)
61 15:55:04.634445 progress 35 % (15 MB)
62 15:55:04.662246 progress 40 % (17 MB)
63 15:55:04.689708 progress 45 % (19 MB)
64 15:55:04.717602 progress 50 % (21 MB)
65 15:55:04.745173 progress 55 % (24 MB)
66 15:55:04.772894 progress 60 % (26 MB)
67 15:55:04.800100 progress 65 % (28 MB)
68 15:55:04.828169 progress 70 % (30 MB)
69 15:55:04.855670 progress 75 % (32 MB)
70 15:55:04.883187 progress 80 % (34 MB)
71 15:55:04.910381 progress 85 % (37 MB)
72 15:55:04.938072 progress 90 % (39 MB)
73 15:55:04.965599 progress 95 % (41 MB)
74 15:55:04.992271 progress 100 % (43 MB)
75 15:55:04.992775 43 MB downloaded in 0.60 s (73.20 MB/s)
76 15:55:04.993239 end: 1.2.1 http-download (duration 00:00:01) [common]
78 15:55:04.994053 end: 1.2 download-retry (duration 00:00:01) [common]
79 15:55:04.994328 start: 1.3 download-retry (timeout 00:09:59) [common]
80 15:55:04.994592 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 15:55:04.995060 downloading http://storage.kernelci.org/renesas/master/renesas-devel-2024-10-01-v6.12-rc1/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
82 15:55:04.995337 saving as /var/lib/lava/dispatcher/tmp/786675/tftp-deploy-r5v_txwe/dtb/meson-sm1-s905d3-libretech-cc.dtb
83 15:55:04.995544 total size: 53209 (0 MB)
84 15:55:04.995752 No compression specified
85 15:55:05.032520 progress 61 % (0 MB)
86 15:55:05.033370 progress 100 % (0 MB)
87 15:55:05.033892 0 MB downloaded in 0.04 s (1.32 MB/s)
88 15:55:05.034345 end: 1.3.1 http-download (duration 00:00:00) [common]
90 15:55:05.035147 end: 1.3 download-retry (duration 00:00:00) [common]
91 15:55:05.035411 start: 1.4 download-retry (timeout 00:09:59) [common]
92 15:55:05.035674 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 15:55:05.036157 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 15:55:05.036407 saving as /var/lib/lava/dispatcher/tmp/786675/tftp-deploy-r5v_txwe/nfsrootfs/full.rootfs.tar
95 15:55:05.036612 total size: 474398908 (452 MB)
96 15:55:05.036821 Using unxz to decompress xz
97 15:55:05.075556 progress 0 % (0 MB)
98 15:55:06.196296 progress 5 % (22 MB)
99 15:55:07.660030 progress 10 % (45 MB)
100 15:55:08.097670 progress 15 % (67 MB)
101 15:55:08.898329 progress 20 % (90 MB)
102 15:55:09.457479 progress 25 % (113 MB)
103 15:55:09.814214 progress 30 % (135 MB)
104 15:55:10.419367 progress 35 % (158 MB)
105 15:55:11.350238 progress 40 % (181 MB)
106 15:55:12.174622 progress 45 % (203 MB)
107 15:55:12.724668 progress 50 % (226 MB)
108 15:55:13.363075 progress 55 % (248 MB)
109 15:55:14.600769 progress 60 % (271 MB)
110 15:55:16.040917 progress 65 % (294 MB)
111 15:55:17.723748 progress 70 % (316 MB)
112 15:55:20.956384 progress 75 % (339 MB)
113 15:55:23.395383 progress 80 % (361 MB)
114 15:55:26.262611 progress 85 % (384 MB)
115 15:55:29.408396 progress 90 % (407 MB)
116 15:55:32.578233 progress 95 % (429 MB)
117 15:55:35.711560 progress 100 % (452 MB)
118 15:55:35.724422 452 MB downloaded in 30.69 s (14.74 MB/s)
119 15:55:35.725301 end: 1.4.1 http-download (duration 00:00:31) [common]
121 15:55:35.726912 end: 1.4 download-retry (duration 00:00:31) [common]
122 15:55:35.727443 start: 1.5 download-retry (timeout 00:09:29) [common]
123 15:55:35.727968 start: 1.5.1 http-download (timeout 00:09:29) [common]
124 15:55:35.729061 downloading http://storage.kernelci.org/renesas/master/renesas-devel-2024-10-01-v6.12-rc1/arm64/defconfig/gcc-12/modules.tar.xz
125 15:55:35.729556 saving as /var/lib/lava/dispatcher/tmp/786675/tftp-deploy-r5v_txwe/modules/modules.tar
126 15:55:35.729972 total size: 11615528 (11 MB)
127 15:55:35.730392 Using unxz to decompress xz
128 15:55:35.776595 progress 0 % (0 MB)
129 15:55:35.841488 progress 5 % (0 MB)
130 15:55:35.919943 progress 10 % (1 MB)
131 15:55:36.008487 progress 15 % (1 MB)
132 15:55:36.101279 progress 20 % (2 MB)
133 15:55:36.184535 progress 25 % (2 MB)
134 15:55:36.262355 progress 30 % (3 MB)
135 15:55:36.347322 progress 35 % (3 MB)
136 15:55:36.424381 progress 40 % (4 MB)
137 15:55:36.502091 progress 45 % (5 MB)
138 15:55:36.585156 progress 50 % (5 MB)
139 15:55:36.663920 progress 55 % (6 MB)
140 15:55:36.748601 progress 60 % (6 MB)
141 15:55:36.825118 progress 65 % (7 MB)
142 15:55:36.907103 progress 70 % (7 MB)
143 15:55:36.981259 progress 75 % (8 MB)
144 15:55:37.058039 progress 80 % (8 MB)
145 15:55:37.143571 progress 85 % (9 MB)
146 15:55:37.227634 progress 90 % (10 MB)
147 15:55:37.304276 progress 95 % (10 MB)
148 15:55:37.385283 progress 100 % (11 MB)
149 15:55:37.398299 11 MB downloaded in 1.67 s (6.64 MB/s)
150 15:55:37.399356 end: 1.5.1 http-download (duration 00:00:02) [common]
152 15:55:37.401000 end: 1.5 download-retry (duration 00:00:02) [common]
153 15:55:37.401534 start: 1.6 prepare-tftp-overlay (timeout 00:09:27) [common]
154 15:55:37.402046 start: 1.6.1 extract-nfsrootfs (timeout 00:09:27) [common]
155 15:55:53.217284 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/786675/extract-nfsrootfs-ut3qx_99
156 15:55:53.217896 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 15:55:53.218183 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 15:55:53.218793 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m
159 15:55:53.219222 makedir: /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin
160 15:55:53.219547 makedir: /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/tests
161 15:55:53.219860 makedir: /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/results
162 15:55:53.220222 Creating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin/lava-add-keys
163 15:55:53.220763 Creating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin/lava-add-sources
164 15:55:53.221275 Creating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin/lava-background-process-start
165 15:55:53.221772 Creating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin/lava-background-process-stop
166 15:55:53.222293 Creating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin/lava-common-functions
167 15:55:53.222780 Creating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin/lava-echo-ipv4
168 15:55:53.223264 Creating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin/lava-install-packages
169 15:55:53.223744 Creating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin/lava-installed-packages
170 15:55:53.224258 Creating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin/lava-os-build
171 15:55:53.224871 Creating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin/lava-probe-channel
172 15:55:53.225374 Creating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin/lava-probe-ip
173 15:55:53.225846 Creating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin/lava-target-ip
174 15:55:53.226342 Creating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin/lava-target-mac
175 15:55:53.226830 Creating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin/lava-target-storage
176 15:55:53.227308 Creating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin/lava-test-case
177 15:55:53.227779 Creating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin/lava-test-event
178 15:55:53.228276 Creating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin/lava-test-feedback
179 15:55:53.228749 Creating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin/lava-test-raise
180 15:55:53.229210 Creating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin/lava-test-reference
181 15:55:53.229690 Creating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin/lava-test-runner
182 15:55:53.230195 Creating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin/lava-test-set
183 15:55:53.230688 Creating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin/lava-test-shell
184 15:55:53.231205 Updating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin/lava-install-packages (oe)
185 15:55:53.231727 Updating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/bin/lava-installed-packages (oe)
186 15:55:53.232181 Creating /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/environment
187 15:55:53.232555 LAVA metadata
188 15:55:53.232812 - LAVA_JOB_ID=786675
189 15:55:53.233025 - LAVA_DISPATCHER_IP=192.168.6.2
190 15:55:53.233380 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 15:55:53.234326 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 15:55:53.234633 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 15:55:53.234842 skipped lava-vland-overlay
194 15:55:53.235081 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 15:55:53.235332 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 15:55:53.235546 skipped lava-multinode-overlay
197 15:55:53.235787 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 15:55:53.236067 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 15:55:53.236318 Loading test definitions
200 15:55:53.236595 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 15:55:53.236815 Using /lava-786675 at stage 0
202 15:55:53.237967 uuid=786675_1.6.2.4.1 testdef=None
203 15:55:53.238277 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 15:55:53.238541 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 15:55:53.240302 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 15:55:53.241091 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 15:55:53.243212 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 15:55:53.244051 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 15:55:53.246101 runner path: /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/0/tests/0_v4l2-decoder-conformance-vp9 test_uuid 786675_1.6.2.4.1
212 15:55:53.246665 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 15:55:53.247418 Creating lava-test-runner.conf files
215 15:55:53.247619 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/786675/lava-overlay-z7mynk9m/lava-786675/0 for stage 0
216 15:55:53.247952 - 0_v4l2-decoder-conformance-vp9
217 15:55:53.248313 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 15:55:53.248584 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 15:55:53.270140 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 15:55:53.270504 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 15:55:53.270763 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 15:55:53.271024 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 15:55:53.271285 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 15:55:53.927887 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 15:55:53.928401 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 15:55:53.928654 extracting modules file /var/lib/lava/dispatcher/tmp/786675/tftp-deploy-r5v_txwe/modules/modules.tar to /var/lib/lava/dispatcher/tmp/786675/extract-nfsrootfs-ut3qx_99
227 15:55:55.286045 extracting modules file /var/lib/lava/dispatcher/tmp/786675/tftp-deploy-r5v_txwe/modules/modules.tar to /var/lib/lava/dispatcher/tmp/786675/extract-overlay-ramdisk-8xpix732/ramdisk
228 15:55:56.682426 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 15:55:56.682934 start: 1.6.5 apply-overlay-tftp (timeout 00:09:08) [common]
230 15:55:56.683219 [common] Applying overlay to NFS
231 15:55:56.683436 [common] Applying overlay /var/lib/lava/dispatcher/tmp/786675/compress-overlay-vnl52gor/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/786675/extract-nfsrootfs-ut3qx_99
232 15:55:56.713570 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 15:55:56.714043 start: 1.6.6 prepare-kernel (timeout 00:09:08) [common]
234 15:55:56.714319 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:08) [common]
235 15:55:56.714557 Converting downloaded kernel to a uImage
236 15:55:56.714886 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/786675/tftp-deploy-r5v_txwe/kernel/Image /var/lib/lava/dispatcher/tmp/786675/tftp-deploy-r5v_txwe/kernel/uImage
237 15:55:57.184799 output: Image Name:
238 15:55:57.185213 output: Created: Tue Oct 1 15:55:56 2024
239 15:55:57.185424 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 15:55:57.185629 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 15:55:57.185831 output: Load Address: 01080000
242 15:55:57.186031 output: Entry Point: 01080000
243 15:55:57.186229 output:
244 15:55:57.186561 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 15:55:57.186829 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 15:55:57.187098 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 15:55:57.187353 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 15:55:57.187611 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 15:55:57.187862 Building ramdisk /var/lib/lava/dispatcher/tmp/786675/extract-overlay-ramdisk-8xpix732/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/786675/extract-overlay-ramdisk-8xpix732/ramdisk
250 15:55:59.633366 >> 166772 blocks
251 15:56:07.454018 Adding RAMdisk u-boot header.
252 15:56:07.454729 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/786675/extract-overlay-ramdisk-8xpix732/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/786675/extract-overlay-ramdisk-8xpix732/ramdisk.cpio.gz.uboot
253 15:56:07.695679 output: Image Name:
254 15:56:07.696181 output: Created: Tue Oct 1 15:56:07 2024
255 15:56:07.696655 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 15:56:07.697110 output: Data Size: 23425141 Bytes = 22876.11 KiB = 22.34 MiB
257 15:56:07.697558 output: Load Address: 00000000
258 15:56:07.697996 output: Entry Point: 00000000
259 15:56:07.698431 output:
260 15:56:07.699653 rename /var/lib/lava/dispatcher/tmp/786675/extract-overlay-ramdisk-8xpix732/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/786675/tftp-deploy-r5v_txwe/ramdisk/ramdisk.cpio.gz.uboot
261 15:56:07.700491 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
262 15:56:07.701093 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 15:56:07.701680 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:57) [common]
264 15:56:07.702184 No LXC device requested
265 15:56:07.702736 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 15:56:07.703299 start: 1.8 deploy-device-env (timeout 00:08:57) [common]
267 15:56:07.703849 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 15:56:07.704353 Checking files for TFTP limit of 4294967296 bytes.
269 15:56:07.707291 end: 1 tftp-deploy (duration 00:01:03) [common]
270 15:56:07.707930 start: 2 uboot-action (timeout 00:05:00) [common]
271 15:56:07.708553 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 15:56:07.709104 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 15:56:07.709661 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 15:56:07.710238 Using kernel file from prepare-kernel: 786675/tftp-deploy-r5v_txwe/kernel/uImage
275 15:56:07.710927 substitutions:
276 15:56:07.711377 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 15:56:07.711819 - {DTB_ADDR}: 0x01070000
278 15:56:07.712299 - {DTB}: 786675/tftp-deploy-r5v_txwe/dtb/meson-sm1-s905d3-libretech-cc.dtb
279 15:56:07.712740 - {INITRD}: 786675/tftp-deploy-r5v_txwe/ramdisk/ramdisk.cpio.gz.uboot
280 15:56:07.713178 - {KERNEL_ADDR}: 0x01080000
281 15:56:07.713611 - {KERNEL}: 786675/tftp-deploy-r5v_txwe/kernel/uImage
282 15:56:07.714043 - {LAVA_MAC}: None
283 15:56:07.714519 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/786675/extract-nfsrootfs-ut3qx_99
284 15:56:07.714956 - {NFS_SERVER_IP}: 192.168.6.2
285 15:56:07.715385 - {PRESEED_CONFIG}: None
286 15:56:07.715813 - {PRESEED_LOCAL}: None
287 15:56:07.716271 - {RAMDISK_ADDR}: 0x08000000
288 15:56:07.716700 - {RAMDISK}: 786675/tftp-deploy-r5v_txwe/ramdisk/ramdisk.cpio.gz.uboot
289 15:56:07.717131 - {ROOT_PART}: None
290 15:56:07.717561 - {ROOT}: None
291 15:56:07.717989 - {SERVER_IP}: 192.168.6.2
292 15:56:07.718419 - {TEE_ADDR}: 0x83000000
293 15:56:07.718846 - {TEE}: None
294 15:56:07.719273 Parsed boot commands:
295 15:56:07.719689 - setenv autoload no
296 15:56:07.720139 - setenv initrd_high 0xffffffff
297 15:56:07.720572 - setenv fdt_high 0xffffffff
298 15:56:07.720999 - dhcp
299 15:56:07.721423 - setenv serverip 192.168.6.2
300 15:56:07.721847 - tftpboot 0x01080000 786675/tftp-deploy-r5v_txwe/kernel/uImage
301 15:56:07.722276 - tftpboot 0x08000000 786675/tftp-deploy-r5v_txwe/ramdisk/ramdisk.cpio.gz.uboot
302 15:56:07.722700 - tftpboot 0x01070000 786675/tftp-deploy-r5v_txwe/dtb/meson-sm1-s905d3-libretech-cc.dtb
303 15:56:07.723128 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/786675/extract-nfsrootfs-ut3qx_99,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 15:56:07.723570 - bootm 0x01080000 0x08000000 0x01070000
305 15:56:07.724165 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 15:56:07.725793 start: 2.3 connect-device (timeout 00:05:00) [common]
308 15:56:07.726251 [common] connect-device Connecting to device using 'telnet conserv1 3008'
309 15:56:07.743141 Setting prompt string to ['lava-test: # ']
310 15:56:07.744796 end: 2.3 connect-device (duration 00:00:00) [common]
311 15:56:07.745446 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 15:56:07.746034 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 15:56:07.746604 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 15:56:07.747823 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
315 15:56:07.789778 >> OK - accepted request
316 15:56:07.791872 Returned 0 in 0 seconds
317 15:56:07.893105 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 15:56:07.894810 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 15:56:07.895434 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 15:56:07.896034 Setting prompt string to ['Hit any key to stop autoboot']
322 15:56:07.896555 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 15:56:07.898258 Trying 192.168.56.21...
324 15:56:07.898772 Connected to conserv1.
325 15:56:07.899232 Escape character is '^]'.
326 15:56:07.899683
327 15:56:07.900175 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 15:56:07.900639
329 15:56:15.222734 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
330 15:56:15.223397 bl2_stage_init 0x01
331 15:56:15.223851 bl2_stage_init 0x81
332 15:56:15.228243 hw id: 0x0000 - pwm id 0x01
333 15:56:15.228735 bl2_stage_init 0xc1
334 15:56:15.233806 bl2_stage_init 0x02
335 15:56:15.234290
336 15:56:15.234749 L0:00000000
337 15:56:15.235182 L1:00000703
338 15:56:15.235614 L2:00008067
339 15:56:15.236076 L3:15000000
340 15:56:15.239742 S1:00000000
341 15:56:15.240254 B2:20282000
342 15:56:15.240693 B1:a0f83180
343 15:56:15.241133
344 15:56:15.241570 TE: 69558
345 15:56:15.242003
346 15:56:15.245274 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
347 15:56:15.245755
348 15:56:15.250894 Board ID = 1
349 15:56:15.251357 Set cpu clk to 24M
350 15:56:15.251795 Set clk81 to 24M
351 15:56:15.256478 Use GP1_pll as DSU clk.
352 15:56:15.256941 DSU clk: 1200 Mhz
353 15:56:15.257374 CPU clk: 1200 MHz
354 15:56:15.262081 Set clk81 to 166.6M
355 15:56:15.267755 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
356 15:56:15.268262 board id: 1
357 15:56:15.274608 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 15:56:15.285264 fw parse done
359 15:56:15.290812 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 15:56:15.333956 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 15:56:15.344839 PIEI prepare done
362 15:56:15.345310 fastboot data load
363 15:56:15.345748 fastboot data verify
364 15:56:15.350433 verify result: 266
365 15:56:15.356090 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
366 15:56:15.356557 LPDDR4 probe
367 15:56:15.356991 ddr clk to 1584MHz
368 15:56:15.364057 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 15:56:15.401274
370 15:56:15.401752 dmc_version 0001
371 15:56:15.407972 Check phy result
372 15:56:15.413889 INFO : End of CA training
373 15:56:15.414355 INFO : End of initialization
374 15:56:15.419455 INFO : Training has run successfully!
375 15:56:15.419909 Check phy result
376 15:56:15.425263 INFO : End of initialization
377 15:56:15.425769 INFO : End of read enable training
378 15:56:15.430676 INFO : End of fine write leveling
379 15:56:15.436248 INFO : End of Write leveling coarse delay
380 15:56:15.436714 INFO : Training has run successfully!
381 15:56:15.437151 Check phy result
382 15:56:15.441884 INFO : End of initialization
383 15:56:15.442345 INFO : End of read dq deskew training
384 15:56:15.447438 INFO : End of MPR read delay center optimization
385 15:56:15.453048 INFO : End of write delay center optimization
386 15:56:15.458673 INFO : End of read delay center optimization
387 15:56:15.459130 INFO : End of max read latency training
388 15:56:15.464274 INFO : Training has run successfully!
389 15:56:15.464776 1D training succeed
390 15:56:15.473500 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 15:56:15.521095 Check phy result
392 15:56:15.521627 INFO : End of initialization
393 15:56:15.543766 INFO : End of 2D read delay Voltage center optimization
394 15:56:15.562635 INFO : End of 2D read delay Voltage center optimization
395 15:56:15.614462 INFO : End of 2D write delay Voltage center optimization
396 15:56:15.663654 INFO : End of 2D write delay Voltage center optimization
397 15:56:15.669256 INFO : Training has run successfully!
398 15:56:15.669717
399 15:56:15.670155 channel==0
400 15:56:15.674770 RxClkDly_Margin_A0==88 ps 9
401 15:56:15.675231 TxDqDly_Margin_A0==98 ps 10
402 15:56:15.680396 RxClkDly_Margin_A1==88 ps 9
403 15:56:15.680855 TxDqDly_Margin_A1==98 ps 10
404 15:56:15.681291 TrainedVREFDQ_A0==75
405 15:56:15.685995 TrainedVREFDQ_A1==74
406 15:56:15.686457 VrefDac_Margin_A0==22
407 15:56:15.686890 DeviceVref_Margin_A0==39
408 15:56:15.691561 VrefDac_Margin_A1==23
409 15:56:15.692038 DeviceVref_Margin_A1==40
410 15:56:15.692472
411 15:56:15.692897
412 15:56:15.697206 channel==1
413 15:56:15.697661 RxClkDly_Margin_A0==78 ps 8
414 15:56:15.698090 TxDqDly_Margin_A0==98 ps 10
415 15:56:15.702757 RxClkDly_Margin_A1==78 ps 8
416 15:56:15.703238 TxDqDly_Margin_A1==78 ps 8
417 15:56:15.708421 TrainedVREFDQ_A0==75
418 15:56:15.708903 TrainedVREFDQ_A1==75
419 15:56:15.709344 VrefDac_Margin_A0==23
420 15:56:15.714059 DeviceVref_Margin_A0==39
421 15:56:15.714527 VrefDac_Margin_A1==20
422 15:56:15.719624 DeviceVref_Margin_A1==38
423 15:56:15.720107
424 15:56:15.720543 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 15:56:15.720968
426 15:56:15.753249 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000019 00000019 00000017 00000019 00000015 00000018 00000015 00000015 00000017 00000019 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
427 15:56:15.753797 2D training succeed
428 15:56:15.758735 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 15:56:15.764411 auto size-- 65535DDR cs0 size: 2048MB
430 15:56:15.764903 DDR cs1 size: 2048MB
431 15:56:15.770002 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 15:56:15.770502 cs0 DataBus test pass
433 15:56:15.775600 cs1 DataBus test pass
434 15:56:15.776097 cs0 AddrBus test pass
435 15:56:15.776534 cs1 AddrBus test pass
436 15:56:15.776962
437 15:56:15.781270 100bdlr_step_size ps== 478
438 15:56:15.781738 result report
439 15:56:15.786744 boot times 0Enable ddr reg access
440 15:56:15.792071 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 15:56:15.805917 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
442 15:56:16.459880 bl2z: ptr: 05129330, size: 00001e40
443 15:56:16.467338 0.0;M3 CHK:0;cm4_sp_mode 0
444 15:56:16.467872 MVN_1=0x00000000
445 15:56:16.468363 MVN_2=0x00000000
446 15:56:16.478799 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
447 15:56:16.479304 OPS=0x04
448 15:56:16.479748 ring efuse init
449 15:56:16.484422 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
450 15:56:16.484918 [0.017319 Inits done]
451 15:56:16.485354 secure task start!
452 15:56:16.491039 high task start!
453 15:56:16.491548 low task start!
454 15:56:16.492019 run into bl31
455 15:56:16.500604 NOTICE: BL31: v1.3(release):4fc40b1
456 15:56:16.508543 NOTICE: BL31: Built : 15:57:33, May 22 2019
457 15:56:16.509045 NOTICE: BL31: G12A normal boot!
458 15:56:16.524101 NOTICE: BL31: BL33 decompress pass
459 15:56:16.529622 ERROR: Error initializing runtime service opteed_fast
460 15:56:19.272846 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
461 15:56:19.273529 bl2_stage_init 0x01
462 15:56:19.274014 bl2_stage_init 0x81
463 15:56:19.278381 hw id: 0x0000 - pwm id 0x01
464 15:56:19.278893 bl2_stage_init 0xc1
465 15:56:19.284109 bl2_stage_init 0x02
466 15:56:19.284639
467 15:56:19.285113 L0:00000000
468 15:56:19.285550 L1:00000703
469 15:56:19.286000 L2:00008067
470 15:56:19.286437 L3:15000000
471 15:56:19.289685 S1:00000000
472 15:56:19.290172 B2:20282000
473 15:56:19.290602 B1:a0f83180
474 15:56:19.291025
475 15:56:19.291452 TE: 69757
476 15:56:19.291876
477 15:56:19.295163 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
478 15:56:19.295629
479 15:56:19.300744 Board ID = 1
480 15:56:19.301246 Set cpu clk to 24M
481 15:56:19.301677 Set clk81 to 24M
482 15:56:19.306336 Use GP1_pll as DSU clk.
483 15:56:19.306802 DSU clk: 1200 Mhz
484 15:56:19.307227 CPU clk: 1200 MHz
485 15:56:19.311961 Set clk81 to 166.6M
486 15:56:19.317676 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
487 15:56:19.318137 board id: 1
488 15:56:19.324795 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
489 15:56:19.335684 fw parse done
490 15:56:19.341751 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
491 15:56:19.384786 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
492 15:56:19.395955 PIEI prepare done
493 15:56:19.396510 fastboot data load
494 15:56:19.396957 fastboot data verify
495 15:56:19.401470 verify result: 266
496 15:56:19.407124 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
497 15:56:19.407658 LPDDR4 probe
498 15:56:19.408147 ddr clk to 1584MHz
499 15:56:19.415033 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
500 15:56:19.452954
501 15:56:19.453510 dmc_version 0001
502 15:56:19.459919 Check phy result
503 15:56:19.465911 INFO : End of CA training
504 15:56:19.466445 INFO : End of initialization
505 15:56:19.471437 INFO : Training has run successfully!
506 15:56:19.471934 Check phy result
507 15:56:19.477090 INFO : End of initialization
508 15:56:19.477615 INFO : End of read enable training
509 15:56:19.480377 INFO : End of fine write leveling
510 15:56:19.485948 INFO : End of Write leveling coarse delay
511 15:56:19.491599 INFO : Training has run successfully!
512 15:56:19.492152 Check phy result
513 15:56:19.492617 INFO : End of initialization
514 15:56:19.497168 INFO : End of read dq deskew training
515 15:56:19.502859 INFO : End of MPR read delay center optimization
516 15:56:19.503375 INFO : End of write delay center optimization
517 15:56:19.508388 INFO : End of read delay center optimization
518 15:56:19.514031 INFO : End of max read latency training
519 15:56:19.514569 INFO : Training has run successfully!
520 15:56:19.519848 1D training succeed
521 15:56:19.525735 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
522 15:56:19.574085 Check phy result
523 15:56:19.574618 INFO : End of initialization
524 15:56:19.600507 INFO : End of 2D read delay Voltage center optimization
525 15:56:19.625469 INFO : End of 2D read delay Voltage center optimization
526 15:56:19.682078 INFO : End of 2D write delay Voltage center optimization
527 15:56:19.736118 INFO : End of 2D write delay Voltage center optimization
528 15:56:19.741726 INFO : Training has run successfully!
529 15:56:19.742195
530 15:56:19.742645 channel==0
531 15:56:19.747635 RxClkDly_Margin_A0==78 ps 8
532 15:56:19.748122 TxDqDly_Margin_A0==98 ps 10
533 15:56:19.750618 RxClkDly_Margin_A1==88 ps 9
534 15:56:19.751075 TxDqDly_Margin_A1==98 ps 10
535 15:56:19.756210 TrainedVREFDQ_A0==76
536 15:56:19.756670 TrainedVREFDQ_A1==75
537 15:56:19.757104 VrefDac_Margin_A0==23
538 15:56:19.761891 DeviceVref_Margin_A0==38
539 15:56:19.762350 VrefDac_Margin_A1==23
540 15:56:19.767401 DeviceVref_Margin_A1==39
541 15:56:19.767870
542 15:56:19.768348
543 15:56:19.768788 channel==1
544 15:56:19.769216 RxClkDly_Margin_A0==78 ps 8
545 15:56:19.770909 TxDqDly_Margin_A0==88 ps 9
546 15:56:19.776370 RxClkDly_Margin_A1==78 ps 8
547 15:56:19.776828 TxDqDly_Margin_A1==88 ps 9
548 15:56:19.777260 TrainedVREFDQ_A0==75
549 15:56:19.782027 TrainedVREFDQ_A1==78
550 15:56:19.782513 VrefDac_Margin_A0==22
551 15:56:19.787621 DeviceVref_Margin_A0==39
552 15:56:19.788124 VrefDac_Margin_A1==22
553 15:56:19.788565 DeviceVref_Margin_A1==36
554 15:56:19.788993
555 15:56:19.797044 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
556 15:56:19.797514
557 15:56:19.824493 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
558 15:56:19.825063 2D training succeed
559 15:56:19.830079 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
560 15:56:19.835821 auto size-- 65535DDR cs0 size: 2048MB
561 15:56:19.836323 DDR cs1 size: 2048MB
562 15:56:19.841273 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
563 15:56:19.841753 cs0 DataBus test pass
564 15:56:19.846853 cs1 DataBus test pass
565 15:56:19.847310 cs0 AddrBus test pass
566 15:56:19.847737 cs1 AddrBus test pass
567 15:56:19.852463
568 15:56:19.852921 100bdlr_step_size ps== 471
569 15:56:19.853364 result report
570 15:56:19.858042 boot times 0Enable ddr reg access
571 15:56:19.864307 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
572 15:56:19.877146 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
573 15:56:20.537841 bl2z: ptr: 05129330, size: 00001e40
574 15:56:20.545849 0.0;M3 CHK:0;cm4_sp_mode 0
575 15:56:20.546341 MVN_1=0x00000000
576 15:56:20.546774 MVN_2=0x00000000
577 15:56:20.557228 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
578 15:56:20.557701 OPS=0x04
579 15:56:20.558134 ring efuse init
580 15:56:20.562818 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
581 15:56:20.563296 [0.017354 Inits done]
582 15:56:20.563917 secure task start!
583 15:56:20.570862 high task start!
584 15:56:20.571331 low task start!
585 15:56:20.571763 run into bl31
586 15:56:20.579452 NOTICE: BL31: v1.3(release):4fc40b1
587 15:56:20.587251 NOTICE: BL31: Built : 15:57:33, May 22 2019
588 15:56:20.587724 NOTICE: BL31: G12A normal boot!
589 15:56:20.602937 NOTICE: BL31: BL33 decompress pass
590 15:56:20.608521 ERROR: Error initializing runtime service opteed_fast
591 15:56:21.973553 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
592 15:56:21.974213 bl2_stage_init 0x01
593 15:56:21.974676 bl2_stage_init 0x81
594 15:56:21.979099 hw id: 0x0000 - pwm id 0x01
595 15:56:21.979597 bl2_stage_init 0xc1
596 15:56:21.984106 bl2_stage_init 0x02
597 15:56:21.984585
598 15:56:21.985039 L0:00000000
599 15:56:21.985484 L1:00000703
600 15:56:21.985923 L2:00008067
601 15:56:21.989791 L3:15000000
602 15:56:21.990272 S1:00000000
603 15:56:21.990716 B2:20282000
604 15:56:21.991153 B1:a0f83180
605 15:56:21.991587
606 15:56:21.992061 TE: 70130
607 15:56:21.992505
608 15:56:22.000859 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
609 15:56:22.001343
610 15:56:22.001789 Board ID = 1
611 15:56:22.002228 Set cpu clk to 24M
612 15:56:22.002666 Set clk81 to 24M
613 15:56:22.006462 Use GP1_pll as DSU clk.
614 15:56:22.006942 DSU clk: 1200 Mhz
615 15:56:22.007384 CPU clk: 1200 MHz
616 15:56:22.012081 Set clk81 to 166.6M
617 15:56:22.017714 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
618 15:56:22.018196 board id: 1
619 15:56:22.025465 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
620 15:56:22.036194 fw parse done
621 15:56:22.042176 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
622 15:56:22.084881 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
623 15:56:22.095651 PIEI prepare done
624 15:56:22.096413 fastboot data load
625 15:56:22.096893 fastboot data verify
626 15:56:22.101253 verify result: 266
627 15:56:22.106841 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
628 15:56:22.107318 LPDDR4 probe
629 15:56:22.107761 ddr clk to 1584MHz
630 15:56:22.114786 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
631 15:56:22.151864
632 15:56:22.152449 dmc_version 0001
633 15:56:22.157946 Check phy result
634 15:56:22.164755 INFO : End of CA training
635 15:56:22.165233 INFO : End of initialization
636 15:56:22.170272 INFO : Training has run successfully!
637 15:56:22.170750 Check phy result
638 15:56:22.175908 INFO : End of initialization
639 15:56:22.176432 INFO : End of read enable training
640 15:56:22.181489 INFO : End of fine write leveling
641 15:56:22.187124 INFO : End of Write leveling coarse delay
642 15:56:22.187619 INFO : Training has run successfully!
643 15:56:22.188108 Check phy result
644 15:56:22.192783 INFO : End of initialization
645 15:56:22.193287 INFO : End of read dq deskew training
646 15:56:22.198272 INFO : End of MPR read delay center optimization
647 15:56:22.203898 INFO : End of write delay center optimization
648 15:56:22.209475 INFO : End of read delay center optimization
649 15:56:22.209947 INFO : End of max read latency training
650 15:56:22.215136 INFO : Training has run successfully!
651 15:56:22.215611 1D training succeed
652 15:56:22.224249 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
653 15:56:22.271309 Check phy result
654 15:56:22.271882 INFO : End of initialization
655 15:56:22.294316 INFO : End of 2D read delay Voltage center optimization
656 15:56:22.312492 INFO : End of 2D read delay Voltage center optimization
657 15:56:22.365375 INFO : End of 2D write delay Voltage center optimization
658 15:56:22.414484 INFO : End of 2D write delay Voltage center optimization
659 15:56:22.420189 INFO : Training has run successfully!
660 15:56:22.420687
661 15:56:22.421142 channel==0
662 15:56:22.425654 RxClkDly_Margin_A0==69 ps 7
663 15:56:22.426135 TxDqDly_Margin_A0==88 ps 9
664 15:56:22.431237 RxClkDly_Margin_A1==88 ps 9
665 15:56:22.431739 TxDqDly_Margin_A1==98 ps 10
666 15:56:22.432248 TrainedVREFDQ_A0==74
667 15:56:22.436847 TrainedVREFDQ_A1==75
668 15:56:22.437386 VrefDac_Margin_A0==24
669 15:56:22.437855 DeviceVref_Margin_A0==40
670 15:56:22.442446 VrefDac_Margin_A1==23
671 15:56:22.442927 DeviceVref_Margin_A1==39
672 15:56:22.443380
673 15:56:22.443833
674 15:56:22.444344 channel==1
675 15:56:22.448197 RxClkDly_Margin_A0==88 ps 9
676 15:56:22.448681 TxDqDly_Margin_A0==98 ps 10
677 15:56:22.453610 RxClkDly_Margin_A1==78 ps 8
678 15:56:22.454082 TxDqDly_Margin_A1==88 ps 9
679 15:56:22.459221 TrainedVREFDQ_A0==78
680 15:56:22.459696 TrainedVREFDQ_A1==78
681 15:56:22.460175 VrefDac_Margin_A0==23
682 15:56:22.464825 DeviceVref_Margin_A0==36
683 15:56:22.465305 VrefDac_Margin_A1==22
684 15:56:22.470437 DeviceVref_Margin_A1==36
685 15:56:22.470908
686 15:56:22.471352 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
687 15:56:22.471791
688 15:56:22.504210 soc_vref_reg_value 0x 00000019 00000018 00000018 00000016 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000018 00000018 0000001c 00000017 00000016 00000016 dram_vref_reg_value 0x 00000062
689 15:56:22.504764 2D training succeed
690 15:56:22.509655 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
691 15:56:22.515222 auto size-- 65535DDR cs0 size: 2048MB
692 15:56:22.515716 DDR cs1 size: 2048MB
693 15:56:22.520822 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
694 15:56:22.521300 cs0 DataBus test pass
695 15:56:22.526423 cs1 DataBus test pass
696 15:56:22.526891 cs0 AddrBus test pass
697 15:56:22.527335 cs1 AddrBus test pass
698 15:56:22.527772
699 15:56:22.532199 100bdlr_step_size ps== 478
700 15:56:22.532677 result report
701 15:56:22.537652 boot times 0Enable ddr reg access
702 15:56:22.542155 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
703 15:56:22.556646 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
704 15:56:23.211085 bl2z: ptr: 05129330, size: 00001e40
705 15:56:23.219909 0.0;M3 CHK:0;cm4_sp_mode 0
706 15:56:23.220252 MVN_1=0x00000000
707 15:56:23.220470 MVN_2=0x00000000
708 15:56:23.231424 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
709 15:56:23.231712 OPS=0x04
710 15:56:23.231943 ring efuse init
711 15:56:23.237035 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
712 15:56:23.237305 [0.017319 Inits done]
713 15:56:23.237556 secure task start!
714 15:56:23.243840 high task start!
715 15:56:23.244140 low task start!
716 15:56:23.244361 run into bl31
717 15:56:23.253367 NOTICE: BL31: v1.3(release):4fc40b1
718 15:56:23.261077 NOTICE: BL31: Built : 15:57:33, May 22 2019
719 15:56:23.261358 NOTICE: BL31: G12A normal boot!
720 15:56:23.276734 NOTICE: BL31: BL33 decompress pass
721 15:56:23.281738 ERROR: Error initializing runtime service opteed_fast
722 15:56:24.077830
723 15:56:24.078233
724 15:56:24.083359 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
725 15:56:24.083632
726 15:56:24.086253 Model: Libre Computer AML-S905D3-CC Solitude
727 15:56:24.232837 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
728 15:56:24.248430 DRAM: 2 GiB (effective 3.8 GiB)
729 15:56:24.350235 Core: 406 devices, 33 uclasses, devicetree: separate
730 15:56:24.355175 WDT: Not starting watchdog@f0d0
731 15:56:24.381159 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
732 15:56:24.393435 Loading Environment from FAT... Card did not respond to voltage select! : -110
733 15:56:24.397524 ** Bad device specification mmc 0 **
734 15:56:24.408388 Card did not respond to voltage select! : -110
735 15:56:24.415808 ** Bad device specification mmc 0 **
736 15:56:24.416473 Couldn't find partition mmc 0
737 15:56:24.424434 Card did not respond to voltage select! : -110
738 15:56:24.429871 ** Bad device specification mmc 0 **
739 15:56:24.430484 Couldn't find partition mmc 0
740 15:56:24.434534 Error: could not access storage.
741 15:56:24.730459 Net: eth0: ethernet@ff3f0000
742 15:56:24.731260 starting USB...
743 15:56:24.976264 Bus usb@ff500000: Register 3000140 NbrPorts 3
744 15:56:24.977104 Starting the controller
745 15:56:24.982299 USB XHCI 1.10
746 15:56:26.537119 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
747 15:56:26.544528 scanning usb for storage devices... 0 Storage Device(s) found
749 15:56:26.596383 Hit any key to stop autoboot: 1
750 15:56:26.597329 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
751 15:56:26.597968 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
752 15:56:26.598533 Setting prompt string to ['=>']
753 15:56:26.599112 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
754 15:56:26.610725 0
755 15:56:26.611756 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
757 15:56:26.713286 => setenv autoload no
758 15:56:26.714131 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
759 15:56:26.720733 setenv autoload no
761 15:56:26.822542 => setenv initrd_high 0xffffffff
762 15:56:26.823657 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
763 15:56:26.828295 setenv initrd_high 0xffffffff
765 15:56:26.929993 => setenv fdt_high 0xffffffff
766 15:56:26.930779 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
767 15:56:26.934570 setenv fdt_high 0xffffffff
769 15:56:27.036258 => dhcp
770 15:56:27.037007 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
771 15:56:27.040961 dhcp
772 15:56:27.946297 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete.. done
773 15:56:27.946977 Speed: 1000, full duplex
774 15:56:27.947491 BOOTP broadcast 1
775 15:56:28.195687 BOOTP broadcast 2
776 15:56:28.696695 BOOTP broadcast 3
777 15:56:29.697801 BOOTP broadcast 4
778 15:56:31.698139 BOOTP broadcast 5
779 15:56:31.715655 DHCP client bound to address 192.168.6.12 (3768 ms)
781 15:56:31.817415 => setenv serverip 192.168.6.2
782 15:56:31.818248 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
783 15:56:31.821952 setenv serverip 192.168.6.2
785 15:56:31.923476 => tftpboot 0x01080000 786675/tftp-deploy-r5v_txwe/kernel/uImage
786 15:56:31.924563 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
787 15:56:31.931270 tftpboot 0x01080000 786675/tftp-deploy-r5v_txwe/kernel/uImage
788 15:56:31.931789 Speed: 1000, full duplex
789 15:56:31.932288 Using ethernet@ff3f0000 device
790 15:56:31.936775 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
791 15:56:31.942273 Filename '786675/tftp-deploy-r5v_txwe/kernel/uImage'.
792 15:56:31.946167 Load address: 0x1080000
793 15:56:45.555618 Loading: *#############################################T T ##### 43.6 MiB
794 15:56:45.556253 3.2 MiB/s
795 15:56:45.556690 done
796 15:56:45.559089 Bytes transferred = 45713984 (2b98a40 hex)
798 15:56:45.660848 => tftpboot 0x08000000 786675/tftp-deploy-r5v_txwe/ramdisk/ramdisk.cpio.gz.uboot
799 15:56:45.661650 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
800 15:56:45.668316 tftpboot 0x08000000 786675/tftp-deploy-r5v_txwe/ramdisk/ramdisk.cpio.gz.uboot
801 15:56:45.668887 Speed: 1000, full duplex
802 15:56:45.669385 Using ethernet@ff3f0000 device
803 15:56:45.673811 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
804 15:56:45.682562 Filename '786675/tftp-deploy-r5v_txwe/ramdisk/ramdisk.cpio.gz.uboot'.
805 15:56:45.683095 Load address: 0x8000000
806 15:56:47.459002 Loading: *################################################# UDP wrong checksum 00000005 0000406c
807 15:56:52.458912 T UDP wrong checksum 00000005 0000406c
808 15:57:02.460255 T UDP wrong checksum 00000005 0000406c
809 15:57:16.580091 T T T UDP wrong checksum 000000ff 00009c85
810 15:57:16.595930 UDP wrong checksum 000000ff 00002678
811 15:57:22.463909 T T UDP wrong checksum 00000005 0000406c
812 15:57:28.935317 T UDP wrong checksum 000000ff 00003c4c
813 15:57:28.974364 UDP wrong checksum 000000ff 0000c13e
814 15:57:31.173583 UDP wrong checksum 000000ff 00004739
815 15:57:31.202102 UDP wrong checksum 000000ff 0000ce2b
816 15:57:42.470026 T T
817 15:57:42.470668 Retry count exceeded; starting again
819 15:57:42.472158 end: 2.4.3 bootloader-commands (duration 00:01:16) [common]
822 15:57:42.474041 end: 2.4 uboot-commands (duration 00:01:35) [common]
824 15:57:42.475440 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
826 15:57:42.476484 end: 2 uboot-action (duration 00:01:35) [common]
828 15:57:42.477988 Cleaning after the job
829 15:57:42.478536 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/786675/tftp-deploy-r5v_txwe/ramdisk
830 15:57:42.479767 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/786675/tftp-deploy-r5v_txwe/kernel
831 15:57:42.524591 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/786675/tftp-deploy-r5v_txwe/dtb
832 15:57:42.525511 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/786675/tftp-deploy-r5v_txwe/nfsrootfs
833 15:57:42.822591 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/786675/tftp-deploy-r5v_txwe/modules
834 15:57:42.843295 start: 4.1 power-off (timeout 00:00:30) [common]
835 15:57:42.843951 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
836 15:57:42.878398 >> OK - accepted request
837 15:57:42.880737 Returned 0 in 0 seconds
838 15:57:42.981456 end: 4.1 power-off (duration 00:00:00) [common]
840 15:57:42.982398 start: 4.2 read-feedback (timeout 00:10:00) [common]
841 15:57:42.983053 Listened to connection for namespace 'common' for up to 1s
842 15:57:43.984013 Finalising connection for namespace 'common'
843 15:57:43.984498 Disconnecting from shell: Finalise
844 15:57:43.984776 =>
845 15:57:44.085512 end: 4.2 read-feedback (duration 00:00:01) [common]
846 15:57:44.086192 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/786675
847 15:57:47.161245 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/786675
848 15:57:47.161872 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.