Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 16:49:01.187099 lava-dispatcher, installed at version: 2024.01
2 16:49:01.187910 start: 0 validate
3 16:49:01.188419 Start time: 2024-11-11 16:49:01.188390+00:00 (UTC)
4 16:49:01.188969 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 16:49:01.189502 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 16:49:01.226319 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 16:49:01.226888 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fmaster%2Frenesas-devel-2024-11-11-v6.12-rc7%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 16:49:01.263560 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 16:49:01.264451 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fmaster%2Frenesas-devel-2024-11-11-v6.12-rc7%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 16:49:01.299862 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 16:49:01.300378 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fmaster%2Frenesas-devel-2024-11-11-v6.12-rc7%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 16:49:01.343527 validate duration: 0.16
14 16:49:01.344477 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 16:49:01.344827 start: 1.1 download-retry (timeout 00:10:00) [common]
16 16:49:01.345140 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 16:49:01.345737 Not decompressing ramdisk as can be used compressed.
18 16:49:01.346176 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 16:49:01.346450 saving as /var/lib/lava/dispatcher/tmp/975710/tftp-deploy-gj5mxchg/ramdisk/rootfs.cpio.gz
20 16:49:01.346728 total size: 47897469 (45 MB)
21 16:49:01.388584 progress 0 % (0 MB)
22 16:49:01.418809 progress 5 % (2 MB)
23 16:49:01.448297 progress 10 % (4 MB)
24 16:49:01.477856 progress 15 % (6 MB)
25 16:49:01.507299 progress 20 % (9 MB)
26 16:49:01.536831 progress 25 % (11 MB)
27 16:49:01.566416 progress 30 % (13 MB)
28 16:49:01.595694 progress 35 % (16 MB)
29 16:49:01.625112 progress 40 % (18 MB)
30 16:49:01.654488 progress 45 % (20 MB)
31 16:49:01.684047 progress 50 % (22 MB)
32 16:49:01.713436 progress 55 % (25 MB)
33 16:49:01.743340 progress 60 % (27 MB)
34 16:49:01.772794 progress 65 % (29 MB)
35 16:49:01.802136 progress 70 % (32 MB)
36 16:49:01.833821 progress 75 % (34 MB)
37 16:49:01.863098 progress 80 % (36 MB)
38 16:49:01.893020 progress 85 % (38 MB)
39 16:49:01.922651 progress 90 % (41 MB)
40 16:49:01.952228 progress 95 % (43 MB)
41 16:49:01.980958 progress 100 % (45 MB)
42 16:49:01.981713 45 MB downloaded in 0.63 s (71.94 MB/s)
43 16:49:01.982276 end: 1.1.1 http-download (duration 00:00:01) [common]
45 16:49:01.983152 end: 1.1 download-retry (duration 00:00:01) [common]
46 16:49:01.983443 start: 1.2 download-retry (timeout 00:09:59) [common]
47 16:49:01.983713 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 16:49:01.984212 downloading http://storage.kernelci.org/renesas/master/renesas-devel-2024-11-11-v6.12-rc7/arm64/defconfig/gcc-12/kernel/Image
49 16:49:01.984471 saving as /var/lib/lava/dispatcher/tmp/975710/tftp-deploy-gj5mxchg/kernel/Image
50 16:49:01.984680 total size: 45713920 (43 MB)
51 16:49:01.984892 No compression specified
52 16:49:02.023941 progress 0 % (0 MB)
53 16:49:02.052878 progress 5 % (2 MB)
54 16:49:02.082635 progress 10 % (4 MB)
55 16:49:02.112245 progress 15 % (6 MB)
56 16:49:02.141715 progress 20 % (8 MB)
57 16:49:02.170675 progress 25 % (10 MB)
58 16:49:02.199884 progress 30 % (13 MB)
59 16:49:02.229107 progress 35 % (15 MB)
60 16:49:02.258689 progress 40 % (17 MB)
61 16:49:02.287652 progress 45 % (19 MB)
62 16:49:02.319030 progress 50 % (21 MB)
63 16:49:02.351593 progress 55 % (24 MB)
64 16:49:02.384563 progress 60 % (26 MB)
65 16:49:02.413882 progress 65 % (28 MB)
66 16:49:02.443546 progress 70 % (30 MB)
67 16:49:02.473238 progress 75 % (32 MB)
68 16:49:02.502829 progress 80 % (34 MB)
69 16:49:02.531969 progress 85 % (37 MB)
70 16:49:02.561309 progress 90 % (39 MB)
71 16:49:02.590926 progress 95 % (41 MB)
72 16:49:02.619760 progress 100 % (43 MB)
73 16:49:02.620357 43 MB downloaded in 0.64 s (68.58 MB/s)
74 16:49:02.620848 end: 1.2.1 http-download (duration 00:00:01) [common]
76 16:49:02.621661 end: 1.2 download-retry (duration 00:00:01) [common]
77 16:49:02.621932 start: 1.3 download-retry (timeout 00:09:59) [common]
78 16:49:02.622194 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 16:49:02.622658 downloading http://storage.kernelci.org/renesas/master/renesas-devel-2024-11-11-v6.12-rc7/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 16:49:02.622930 saving as /var/lib/lava/dispatcher/tmp/975710/tftp-deploy-gj5mxchg/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 16:49:02.623140 total size: 53209 (0 MB)
82 16:49:02.623347 No compression specified
83 16:49:02.670304 progress 61 % (0 MB)
84 16:49:02.671188 progress 100 % (0 MB)
85 16:49:02.671776 0 MB downloaded in 0.05 s (1.04 MB/s)
86 16:49:02.672323 end: 1.3.1 http-download (duration 00:00:00) [common]
88 16:49:02.673175 end: 1.3 download-retry (duration 00:00:00) [common]
89 16:49:02.673453 start: 1.4 download-retry (timeout 00:09:59) [common]
90 16:49:02.673727 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 16:49:02.674204 downloading http://storage.kernelci.org/renesas/master/renesas-devel-2024-11-11-v6.12-rc7/arm64/defconfig/gcc-12/modules.tar.xz
92 16:49:02.674463 saving as /var/lib/lava/dispatcher/tmp/975710/tftp-deploy-gj5mxchg/modules/modules.tar
93 16:49:02.674675 total size: 11621176 (11 MB)
94 16:49:02.674890 Using unxz to decompress xz
95 16:49:02.714162 progress 0 % (0 MB)
96 16:49:02.779879 progress 5 % (0 MB)
97 16:49:02.855899 progress 10 % (1 MB)
98 16:49:02.956348 progress 15 % (1 MB)
99 16:49:03.048909 progress 20 % (2 MB)
100 16:49:03.128928 progress 25 % (2 MB)
101 16:49:03.204898 progress 30 % (3 MB)
102 16:49:03.284268 progress 35 % (3 MB)
103 16:49:03.360883 progress 40 % (4 MB)
104 16:49:03.437479 progress 45 % (5 MB)
105 16:49:03.522282 progress 50 % (5 MB)
106 16:49:03.604713 progress 55 % (6 MB)
107 16:49:03.686475 progress 60 % (6 MB)
108 16:49:03.769462 progress 65 % (7 MB)
109 16:49:03.850552 progress 70 % (7 MB)
110 16:49:03.928342 progress 75 % (8 MB)
111 16:49:04.012624 progress 80 % (8 MB)
112 16:49:04.093614 progress 85 % (9 MB)
113 16:49:04.177803 progress 90 % (10 MB)
114 16:49:04.252277 progress 95 % (10 MB)
115 16:49:04.328907 progress 100 % (11 MB)
116 16:49:04.342878 11 MB downloaded in 1.67 s (6.64 MB/s)
117 16:49:04.343536 end: 1.4.1 http-download (duration 00:00:02) [common]
119 16:49:04.344782 end: 1.4 download-retry (duration 00:00:02) [common]
120 16:49:04.345315 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 16:49:04.345833 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 16:49:04.346321 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 16:49:04.346814 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 16:49:04.347788 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e
125 16:49:04.348669 makedir: /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin
126 16:49:04.349308 makedir: /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/tests
127 16:49:04.349918 makedir: /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/results
128 16:49:04.350531 Creating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin/lava-add-keys
129 16:49:04.351514 Creating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin/lava-add-sources
130 16:49:04.352495 Creating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin/lava-background-process-start
131 16:49:04.353436 Creating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin/lava-background-process-stop
132 16:49:04.354401 Creating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin/lava-common-functions
133 16:49:04.355302 Creating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin/lava-echo-ipv4
134 16:49:04.356232 Creating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin/lava-install-packages
135 16:49:04.357111 Creating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin/lava-installed-packages
136 16:49:04.358025 Creating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin/lava-os-build
137 16:49:04.358963 Creating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin/lava-probe-channel
138 16:49:04.359850 Creating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin/lava-probe-ip
139 16:49:04.360899 Creating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin/lava-target-ip
140 16:49:04.361778 Creating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin/lava-target-mac
141 16:49:04.362650 Creating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin/lava-target-storage
142 16:49:04.363535 Creating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin/lava-test-case
143 16:49:04.364465 Creating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin/lava-test-event
144 16:49:04.365378 Creating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin/lava-test-feedback
145 16:49:04.366307 Creating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin/lava-test-raise
146 16:49:04.367176 Creating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin/lava-test-reference
147 16:49:04.368070 Creating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin/lava-test-runner
148 16:49:04.368967 Creating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin/lava-test-set
149 16:49:04.369837 Creating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin/lava-test-shell
150 16:49:04.370744 Updating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin/lava-install-packages (oe)
151 16:49:04.371705 Updating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/bin/lava-installed-packages (oe)
152 16:49:04.372579 Creating /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/environment
153 16:49:04.373295 LAVA metadata
154 16:49:04.373785 - LAVA_JOB_ID=975710
155 16:49:04.374213 - LAVA_DISPATCHER_IP=192.168.6.2
156 16:49:04.374890 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 16:49:04.376464 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 16:49:04.376818 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 16:49:04.377031 skipped lava-vland-overlay
160 16:49:04.377280 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 16:49:04.377538 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 16:49:04.377760 skipped lava-multinode-overlay
163 16:49:04.378008 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 16:49:04.378262 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 16:49:04.378513 Loading test definitions
166 16:49:04.378797 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 16:49:04.379024 Using /lava-975710 at stage 0
168 16:49:04.380317 uuid=975710_1.5.2.4.1 testdef=None
169 16:49:04.380650 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 16:49:04.380919 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 16:49:04.382661 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 16:49:04.383470 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 16:49:04.385667 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 16:49:04.386539 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 16:49:04.388637 runner path: /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/0/tests/0_igt-gpu-panfrost test_uuid 975710_1.5.2.4.1
178 16:49:04.389222 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 16:49:04.390030 Creating lava-test-runner.conf files
181 16:49:04.390239 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/975710/lava-overlay-h4q_702e/lava-975710/0 for stage 0
182 16:49:04.390574 - 0_igt-gpu-panfrost
183 16:49:04.390924 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 16:49:04.391205 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 16:49:04.415002 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 16:49:04.415427 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 16:49:04.415693 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 16:49:04.415964 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 16:49:04.416268 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 16:49:11.504825 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 16:49:11.505281 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 16:49:11.505539 extracting modules file /var/lib/lava/dispatcher/tmp/975710/tftp-deploy-gj5mxchg/modules/modules.tar to /var/lib/lava/dispatcher/tmp/975710/extract-overlay-ramdisk-0_vg7a5i/ramdisk
193 16:49:12.918070 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 16:49:12.918521 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 16:49:12.918797 [common] Applying overlay /var/lib/lava/dispatcher/tmp/975710/compress-overlay-bmz_zse6/overlay-1.5.2.5.tar.gz to ramdisk
196 16:49:12.919012 [common] Applying overlay /var/lib/lava/dispatcher/tmp/975710/compress-overlay-bmz_zse6/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/975710/extract-overlay-ramdisk-0_vg7a5i/ramdisk
197 16:49:12.949263 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 16:49:12.949654 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 16:49:12.949926 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 16:49:12.950155 Converting downloaded kernel to a uImage
201 16:49:12.950463 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/975710/tftp-deploy-gj5mxchg/kernel/Image /var/lib/lava/dispatcher/tmp/975710/tftp-deploy-gj5mxchg/kernel/uImage
202 16:49:13.441010 output: Image Name:
203 16:49:13.441411 output: Created: Mon Nov 11 16:49:12 2024
204 16:49:13.441620 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 16:49:13.441822 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 16:49:13.442024 output: Load Address: 01080000
207 16:49:13.442223 output: Entry Point: 01080000
208 16:49:13.442423 output:
209 16:49:13.442750 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 16:49:13.443017 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 16:49:13.443287 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 16:49:13.443540 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 16:49:13.443797 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 16:49:13.444087 Building ramdisk /var/lib/lava/dispatcher/tmp/975710/extract-overlay-ramdisk-0_vg7a5i/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/975710/extract-overlay-ramdisk-0_vg7a5i/ramdisk
215 16:49:20.011721 >> 502416 blocks
216 16:49:40.725079 Adding RAMdisk u-boot header.
217 16:49:40.725782 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/975710/extract-overlay-ramdisk-0_vg7a5i/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/975710/extract-overlay-ramdisk-0_vg7a5i/ramdisk.cpio.gz.uboot
218 16:49:41.418198 output: Image Name:
219 16:49:41.418616 output: Created: Mon Nov 11 16:49:40 2024
220 16:49:41.418825 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 16:49:41.419029 output: Data Size: 65715399 Bytes = 64175.19 KiB = 62.67 MiB
222 16:49:41.419225 output: Load Address: 00000000
223 16:49:41.419421 output: Entry Point: 00000000
224 16:49:41.419616 output:
225 16:49:41.420383 rename /var/lib/lava/dispatcher/tmp/975710/extract-overlay-ramdisk-0_vg7a5i/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/975710/tftp-deploy-gj5mxchg/ramdisk/ramdisk.cpio.gz.uboot
226 16:49:41.421120 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 16:49:41.421656 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 16:49:41.422171 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 16:49:41.422611 No LXC device requested
230 16:49:41.423102 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 16:49:41.423599 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 16:49:41.424107 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 16:49:41.424514 Checking files for TFTP limit of 4294967296 bytes.
234 16:49:41.427120 end: 1 tftp-deploy (duration 00:00:40) [common]
235 16:49:41.427686 start: 2 uboot-action (timeout 00:05:00) [common]
236 16:49:41.428234 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 16:49:41.428742 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 16:49:41.429250 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 16:49:41.429777 Using kernel file from prepare-kernel: 975710/tftp-deploy-gj5mxchg/kernel/uImage
240 16:49:41.430400 substitutions:
241 16:49:41.430809 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 16:49:41.431205 - {DTB_ADDR}: 0x01070000
243 16:49:41.431594 - {DTB}: 975710/tftp-deploy-gj5mxchg/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 16:49:41.432010 - {INITRD}: 975710/tftp-deploy-gj5mxchg/ramdisk/ramdisk.cpio.gz.uboot
245 16:49:41.432403 - {KERNEL_ADDR}: 0x01080000
246 16:49:41.432787 - {KERNEL}: 975710/tftp-deploy-gj5mxchg/kernel/uImage
247 16:49:41.433173 - {LAVA_MAC}: None
248 16:49:41.433596 - {PRESEED_CONFIG}: None
249 16:49:41.433983 - {PRESEED_LOCAL}: None
250 16:49:41.434365 - {RAMDISK_ADDR}: 0x08000000
251 16:49:41.434743 - {RAMDISK}: 975710/tftp-deploy-gj5mxchg/ramdisk/ramdisk.cpio.gz.uboot
252 16:49:41.435128 - {ROOT_PART}: None
253 16:49:41.435507 - {ROOT}: None
254 16:49:41.435888 - {SERVER_IP}: 192.168.6.2
255 16:49:41.436303 - {TEE_ADDR}: 0x83000000
256 16:49:41.436686 - {TEE}: None
257 16:49:41.437065 Parsed boot commands:
258 16:49:41.437434 - setenv autoload no
259 16:49:41.437812 - setenv initrd_high 0xffffffff
260 16:49:41.438189 - setenv fdt_high 0xffffffff
261 16:49:41.438565 - dhcp
262 16:49:41.438944 - setenv serverip 192.168.6.2
263 16:49:41.439322 - tftpboot 0x01080000 975710/tftp-deploy-gj5mxchg/kernel/uImage
264 16:49:41.439704 - tftpboot 0x08000000 975710/tftp-deploy-gj5mxchg/ramdisk/ramdisk.cpio.gz.uboot
265 16:49:41.440106 - tftpboot 0x01070000 975710/tftp-deploy-gj5mxchg/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 16:49:41.440491 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 16:49:41.440877 - bootm 0x01080000 0x08000000 0x01070000
268 16:49:41.441376 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 16:49:41.442827 start: 2.3 connect-device (timeout 00:05:00) [common]
271 16:49:41.443263 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 16:49:41.457895 Setting prompt string to ['lava-test: # ']
273 16:49:41.459387 end: 2.3 connect-device (duration 00:00:00) [common]
274 16:49:41.459970 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 16:49:41.460644 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 16:49:41.461158 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 16:49:41.462266 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 16:49:41.507587 >> OK - accepted request
279 16:49:41.509718 Returned 0 in 0 seconds
280 16:49:41.610815 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 16:49:41.612467 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 16:49:41.613023 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 16:49:41.613514 Setting prompt string to ['Hit any key to stop autoboot']
285 16:49:41.613960 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 16:49:41.615521 Trying 192.168.56.21...
287 16:49:41.616030 Connected to conserv1.
288 16:49:41.616438 Escape character is '^]'.
289 16:49:41.616852
290 16:49:41.617272 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 16:49:41.617695
292 16:49:48.716024 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 16:49:48.716660 bl2_stage_init 0x01
294 16:49:48.717110 bl2_stage_init 0x81
295 16:49:48.721291 hw id: 0x0000 - pwm id 0x01
296 16:49:48.721757 bl2_stage_init 0xc1
297 16:49:48.727112 bl2_stage_init 0x02
298 16:49:48.727548
299 16:49:48.727955 L0:00000000
300 16:49:48.728405 L1:00000703
301 16:49:48.728802 L2:00008067
302 16:49:48.729193 L3:15000000
303 16:49:48.732302 S1:00000000
304 16:49:48.732735 B2:20282000
305 16:49:48.733135 B1:a0f83180
306 16:49:48.733529
307 16:49:48.733922 TE: 69335
308 16:49:48.734315
309 16:49:48.737773 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 16:49:48.738209
311 16:49:48.743387 Board ID = 1
312 16:49:48.743818 Set cpu clk to 24M
313 16:49:48.744250 Set clk81 to 24M
314 16:49:48.748998 Use GP1_pll as DSU clk.
315 16:49:48.749427 DSU clk: 1200 Mhz
316 16:49:48.749829 CPU clk: 1200 MHz
317 16:49:48.754594 Set clk81 to 166.6M
318 16:49:48.760213 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 16:49:48.760638 board id: 1
320 16:49:48.767467 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 16:49:48.778436 fw parse done
322 16:49:48.784234 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 16:49:48.827524 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 16:49:48.838540 PIEI prepare done
325 16:49:48.838979 fastboot data load
326 16:49:48.839388 fastboot data verify
327 16:49:48.844146 verify result: 266
328 16:49:48.849821 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 16:49:48.850117 LPDDR4 probe
330 16:49:48.850328 ddr clk to 1584MHz
331 16:49:48.857764 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 16:49:48.895585
333 16:49:48.895931 dmc_version 0001
334 16:49:48.902571 Check phy result
335 16:49:48.908483 INFO : End of CA training
336 16:49:48.908759 INFO : End of initialization
337 16:49:48.914095 INFO : Training has run successfully!
338 16:49:48.914459 Check phy result
339 16:49:48.919704 INFO : End of initialization
340 16:49:48.920089 INFO : End of read enable training
341 16:49:48.925339 INFO : End of fine write leveling
342 16:49:48.930846 INFO : End of Write leveling coarse delay
343 16:49:48.931097 INFO : Training has run successfully!
344 16:49:48.931302 Check phy result
345 16:49:48.936463 INFO : End of initialization
346 16:49:48.936709 INFO : End of read dq deskew training
347 16:49:48.942088 INFO : End of MPR read delay center optimization
348 16:49:48.947632 INFO : End of write delay center optimization
349 16:49:48.953319 INFO : End of read delay center optimization
350 16:49:48.953580 INFO : End of max read latency training
351 16:49:48.958875 INFO : Training has run successfully!
352 16:49:48.959145 1D training succeed
353 16:49:48.968122 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 16:49:49.016430 Check phy result
355 16:49:49.016775 INFO : End of initialization
356 16:49:49.043947 INFO : End of 2D read delay Voltage center optimization
357 16:49:49.068005 INFO : End of 2D read delay Voltage center optimization
358 16:49:49.124695 INFO : End of 2D write delay Voltage center optimization
359 16:49:49.178618 INFO : End of 2D write delay Voltage center optimization
360 16:49:49.184207 INFO : Training has run successfully!
361 16:49:49.184682
362 16:49:49.185082 channel==0
363 16:49:49.189712 RxClkDly_Margin_A0==78 ps 8
364 16:49:49.190179 TxDqDly_Margin_A0==98 ps 10
365 16:49:49.195359 RxClkDly_Margin_A1==69 ps 7
366 16:49:49.195860 TxDqDly_Margin_A1==98 ps 10
367 16:49:49.196310 TrainedVREFDQ_A0==75
368 16:49:49.202678 TrainedVREFDQ_A1==74
369 16:49:49.203150 VrefDac_Margin_A0==24
370 16:49:49.203540 DeviceVref_Margin_A0==39
371 16:49:49.206531 VrefDac_Margin_A1==23
372 16:49:49.206991 DeviceVref_Margin_A1==40
373 16:49:49.207378
374 16:49:49.207764
375 16:49:49.212127 channel==1
376 16:49:49.212614 RxClkDly_Margin_A0==78 ps 8
377 16:49:49.213004 TxDqDly_Margin_A0==98 ps 10
378 16:49:49.217725 RxClkDly_Margin_A1==88 ps 9
379 16:49:49.218182 TxDqDly_Margin_A1==88 ps 9
380 16:49:49.222847 TrainedVREFDQ_A0==78
381 16:49:49.223307 TrainedVREFDQ_A1==75
382 16:49:49.223700 VrefDac_Margin_A0==22
383 16:49:49.228341 DeviceVref_Margin_A0==36
384 16:49:49.228797 VrefDac_Margin_A1==20
385 16:49:49.233922 DeviceVref_Margin_A1==38
386 16:49:49.234378
387 16:49:49.239546 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 16:49:49.240038
389 16:49:49.267505 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 16:49:49.268156 2D training succeed
391 16:49:49.273297 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 16:49:49.278641 auto size-- 65535DDR cs0 size: 2048MB
393 16:49:49.279158 DDR cs1 size: 2048MB
394 16:49:49.284249 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 16:49:49.284771 cs0 DataBus test pass
396 16:49:49.289830 cs1 DataBus test pass
397 16:49:49.290333 cs0 AddrBus test pass
398 16:49:49.290744 cs1 AddrBus test pass
399 16:49:49.291134
400 16:49:49.295522 100bdlr_step_size ps== 478
401 16:49:49.296093 result report
402 16:49:49.301026 boot times 0Enable ddr reg access
403 16:49:49.306913 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 16:49:49.320750 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 16:49:49.979970 bl2z: ptr: 05129330, size: 00001e40
406 16:49:49.986974 0.0;M3 CHK:0;cm4_sp_mode 0
407 16:49:49.987486 MVN_1=0x00000000
408 16:49:49.987900 MVN_2=0x00000000
409 16:49:49.998381 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 16:49:49.998913 OPS=0x04
411 16:49:49.999339 ring efuse init
412 16:49:50.001381 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 16:49:50.007436 [0.017354 Inits done]
414 16:49:50.007897 secure task start!
415 16:49:50.008601 high task start!
416 16:49:50.009097 low task start!
417 16:49:50.011779 run into bl31
418 16:49:50.020287 NOTICE: BL31: v1.3(release):4fc40b1
419 16:49:50.028139 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 16:49:50.028654 NOTICE: BL31: G12A normal boot!
421 16:49:50.043786 NOTICE: BL31: BL33 decompress pass
422 16:49:50.049353 ERROR: Error initializing runtime service opteed_fast
423 16:49:52.764275 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 16:49:52.764723 bl2_stage_init 0x01
425 16:49:52.764943 bl2_stage_init 0x81
426 16:49:52.770063 hw id: 0x0000 - pwm id 0x01
427 16:49:52.770663 bl2_stage_init 0xc1
428 16:49:52.775441 bl2_stage_init 0x02
429 16:49:52.775958
430 16:49:52.776452 L0:00000000
431 16:49:52.776887 L1:00000703
432 16:49:52.777325 L2:00008067
433 16:49:52.777792 L3:15000000
434 16:49:52.781186 S1:00000000
435 16:49:52.781695 B2:20282000
436 16:49:52.782133 B1:a0f83180
437 16:49:52.782555
438 16:49:52.782982 TE: 68316
439 16:49:52.783405
440 16:49:52.786642 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 16:49:52.787168
442 16:49:52.792238 Board ID = 1
443 16:49:52.792765 Set cpu clk to 24M
444 16:49:52.793222 Set clk81 to 24M
445 16:49:52.797926 Use GP1_pll as DSU clk.
446 16:49:52.798437 DSU clk: 1200 Mhz
447 16:49:52.798868 CPU clk: 1200 MHz
448 16:49:52.803476 Set clk81 to 166.6M
449 16:49:52.809045 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 16:49:52.809586 board id: 1
451 16:49:52.816292 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 16:49:52.827179 fw parse done
453 16:49:52.833118 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 16:49:52.876255 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 16:49:52.887515 PIEI prepare done
456 16:49:52.888139 fastboot data load
457 16:49:52.888554 fastboot data verify
458 16:49:52.893077 verify result: 266
459 16:49:52.898627 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 16:49:52.899119 LPDDR4 probe
461 16:49:52.899512 ddr clk to 1584MHz
462 16:49:52.906612 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 16:49:52.944336
464 16:49:52.944838 dmc_version 0001
465 16:49:52.951406 Check phy result
466 16:49:52.957425 INFO : End of CA training
467 16:49:52.957910 INFO : End of initialization
468 16:49:52.963066 INFO : Training has run successfully!
469 16:49:52.963551 Check phy result
470 16:49:52.968607 INFO : End of initialization
471 16:49:52.969103 INFO : End of read enable training
472 16:49:52.974233 INFO : End of fine write leveling
473 16:49:52.979780 INFO : End of Write leveling coarse delay
474 16:49:52.980299 INFO : Training has run successfully!
475 16:49:52.980712 Check phy result
476 16:49:52.985399 INFO : End of initialization
477 16:49:52.985890 INFO : End of read dq deskew training
478 16:49:52.991092 INFO : End of MPR read delay center optimization
479 16:49:52.996569 INFO : End of write delay center optimization
480 16:49:53.002186 INFO : End of read delay center optimization
481 16:49:53.002666 INFO : End of max read latency training
482 16:49:53.007776 INFO : Training has run successfully!
483 16:49:53.008294 1D training succeed
484 16:49:53.017010 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 16:49:53.065382 Check phy result
486 16:49:53.065945 INFO : End of initialization
487 16:49:53.092700 INFO : End of 2D read delay Voltage center optimization
488 16:49:53.116862 INFO : End of 2D read delay Voltage center optimization
489 16:49:53.173494 INFO : End of 2D write delay Voltage center optimization
490 16:49:53.227531 INFO : End of 2D write delay Voltage center optimization
491 16:49:53.233164 INFO : Training has run successfully!
492 16:49:53.233649
493 16:49:53.234062 channel==0
494 16:49:53.238676 RxClkDly_Margin_A0==78 ps 8
495 16:49:53.239151 TxDqDly_Margin_A0==88 ps 9
496 16:49:53.244279 RxClkDly_Margin_A1==78 ps 8
497 16:49:53.244754 TxDqDly_Margin_A1==98 ps 10
498 16:49:53.245167 TrainedVREFDQ_A0==74
499 16:49:53.249879 TrainedVREFDQ_A1==74
500 16:49:53.250366 VrefDac_Margin_A0==24
501 16:49:53.250771 DeviceVref_Margin_A0==40
502 16:49:53.255469 VrefDac_Margin_A1==23
503 16:49:53.255946 DeviceVref_Margin_A1==40
504 16:49:53.256394
505 16:49:53.256796
506 16:49:53.257193 channel==1
507 16:49:53.261142 RxClkDly_Margin_A0==78 ps 8
508 16:49:53.261636 TxDqDly_Margin_A0==98 ps 10
509 16:49:53.266651 RxClkDly_Margin_A1==88 ps 9
510 16:49:53.267133 TxDqDly_Margin_A1==88 ps 9
511 16:49:53.272248 TrainedVREFDQ_A0==78
512 16:49:53.272725 TrainedVREFDQ_A1==77
513 16:49:53.273135 VrefDac_Margin_A0==22
514 16:49:53.277856 DeviceVref_Margin_A0==36
515 16:49:53.278332 VrefDac_Margin_A1==22
516 16:49:53.283441 DeviceVref_Margin_A1==37
517 16:49:53.283913
518 16:49:53.284366 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 16:49:53.284772
520 16:49:53.317170 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000019 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
521 16:49:53.317752 2D training succeed
522 16:49:53.322657 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 16:49:53.328278 auto size-- 65535DDR cs0 size: 2048MB
524 16:49:53.328771 DDR cs1 size: 2048MB
525 16:49:53.333894 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 16:49:53.334383 cs0 DataBus test pass
527 16:49:53.339492 cs1 DataBus test pass
528 16:49:53.340024 cs0 AddrBus test pass
529 16:49:53.340448 cs1 AddrBus test pass
530 16:49:53.340846
531 16:49:53.345152 100bdlr_step_size ps== 471
532 16:49:53.345664 result report
533 16:49:53.350674 boot times 0Enable ddr reg access
534 16:49:53.355847 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 16:49:53.369632 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 16:49:54.028990 bl2z: ptr: 05129330, size: 00001e40
537 16:49:54.035658 0.0;M3 CHK:0;cm4_sp_mode 0
538 16:49:54.036216 MVN_1=0x00000000
539 16:49:54.036638 MVN_2=0x00000000
540 16:49:54.047142 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 16:49:54.047622 OPS=0x04
542 16:49:54.048075 ring efuse init
543 16:49:54.052848 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 16:49:54.053342 [0.017354 Inits done]
545 16:49:54.053752 secure task start!
546 16:49:54.060187 high task start!
547 16:49:54.060687 low task start!
548 16:49:54.061099 run into bl31
549 16:49:54.068806 NOTICE: BL31: v1.3(release):4fc40b1
550 16:49:54.076577 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 16:49:54.077062 NOTICE: BL31: G12A normal boot!
552 16:49:54.092160 NOTICE: BL31: BL33 decompress pass
553 16:49:54.097828 ERROR: Error initializing runtime service opteed_fast
554 16:49:55.465848 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 16:49:55.466465 bl2_stage_init 0x01
556 16:49:55.466889 bl2_stage_init 0x81
557 16:49:55.471353 hw id: 0x0000 - pwm id 0x01
558 16:49:55.471815 bl2_stage_init 0xc1
559 16:49:55.476981 bl2_stage_init 0x02
560 16:49:55.477447
561 16:49:55.477857 L0:00000000
562 16:49:55.478256 L1:00000703
563 16:49:55.478649 L2:00008067
564 16:49:55.479039 L3:15000000
565 16:49:55.482486 S1:00000000
566 16:49:55.482920 B2:20282000
567 16:49:55.483321 B1:a0f83180
568 16:49:55.483710
569 16:49:55.484159 TE: 69289
570 16:49:55.484585
571 16:49:55.488183 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 16:49:55.488702
573 16:49:55.493696 Board ID = 1
574 16:49:55.494144 Set cpu clk to 24M
575 16:49:55.494543 Set clk81 to 24M
576 16:49:55.499444 Use GP1_pll as DSU clk.
577 16:49:55.499897 DSU clk: 1200 Mhz
578 16:49:55.500336 CPU clk: 1200 MHz
579 16:49:55.504884 Set clk81 to 166.6M
580 16:49:55.510484 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 16:49:55.510929 board id: 1
582 16:49:55.517749 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 16:49:55.528558 fw parse done
584 16:49:55.534476 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 16:49:55.576937 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 16:49:55.587844 PIEI prepare done
587 16:49:55.588401 fastboot data load
588 16:49:55.588823 fastboot data verify
589 16:49:55.593378 verify result: 266
590 16:49:55.599031 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 16:49:55.599491 LPDDR4 probe
592 16:49:55.599892 ddr clk to 1584MHz
593 16:49:55.606955 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 16:49:55.644305
595 16:49:55.644813 dmc_version 0001
596 16:49:55.650928 Check phy result
597 16:49:55.656803 INFO : End of CA training
598 16:49:55.657252 INFO : End of initialization
599 16:49:55.662454 INFO : Training has run successfully!
600 16:49:55.662895 Check phy result
601 16:49:55.668092 INFO : End of initialization
602 16:49:55.668736 INFO : End of read enable training
603 16:49:55.673692 INFO : End of fine write leveling
604 16:49:55.679270 INFO : End of Write leveling coarse delay
605 16:49:55.679782 INFO : Training has run successfully!
606 16:49:55.680291 Check phy result
607 16:49:55.684874 INFO : End of initialization
608 16:49:55.685377 INFO : End of read dq deskew training
609 16:49:55.690392 INFO : End of MPR read delay center optimization
610 16:49:55.696086 INFO : End of write delay center optimization
611 16:49:55.701644 INFO : End of read delay center optimization
612 16:49:55.702148 INFO : End of max read latency training
613 16:49:55.707269 INFO : Training has run successfully!
614 16:49:55.707772 1D training succeed
615 16:49:55.716485 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 16:49:55.764087 Check phy result
617 16:49:55.764614 INFO : End of initialization
618 16:49:55.786442 INFO : End of 2D read delay Voltage center optimization
619 16:49:55.805566 INFO : End of 2D read delay Voltage center optimization
620 16:49:55.857508 INFO : End of 2D write delay Voltage center optimization
621 16:49:55.906689 INFO : End of 2D write delay Voltage center optimization
622 16:49:55.912221 INFO : Training has run successfully!
623 16:49:55.912717
624 16:49:55.913176 channel==0
625 16:49:55.917801 RxClkDly_Margin_A0==78 ps 8
626 16:49:55.918300 TxDqDly_Margin_A0==98 ps 10
627 16:49:55.921121 RxClkDly_Margin_A1==69 ps 7
628 16:49:55.921607 TxDqDly_Margin_A1==98 ps 10
629 16:49:55.926810 TrainedVREFDQ_A0==74
630 16:49:55.927309 TrainedVREFDQ_A1==74
631 16:49:55.927764 VrefDac_Margin_A0==22
632 16:49:55.932321 DeviceVref_Margin_A0==40
633 16:49:55.932819 VrefDac_Margin_A1==23
634 16:49:55.937952 DeviceVref_Margin_A1==40
635 16:49:55.938436
636 16:49:55.938890
637 16:49:55.939332 channel==1
638 16:49:55.939764 RxClkDly_Margin_A0==78 ps 8
639 16:49:55.941317 TxDqDly_Margin_A0==98 ps 10
640 16:49:55.946823 RxClkDly_Margin_A1==78 ps 8
641 16:49:55.947312 TxDqDly_Margin_A1==88 ps 9
642 16:49:55.947759 TrainedVREFDQ_A0==78
643 16:49:55.952557 TrainedVREFDQ_A1==75
644 16:49:55.953059 VrefDac_Margin_A0==22
645 16:49:55.958151 DeviceVref_Margin_A0==36
646 16:49:55.958643 VrefDac_Margin_A1==22
647 16:49:55.959083 DeviceVref_Margin_A1==39
648 16:49:55.959526
649 16:49:55.967107 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 16:49:55.967613
651 16:49:55.995151 soc_vref_reg_value 0x 00000019 00000018 00000017 00000016 00000018 00000014 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000015 00000017 dram_vref_reg_value 0x 00000061
652 16:49:55.995740 2D training succeed
653 16:49:56.000735 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 16:49:56.006280 auto size-- 65535DDR cs0 size: 2048MB
655 16:49:56.006776 DDR cs1 size: 2048MB
656 16:49:56.011802 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 16:49:56.012331 cs0 DataBus test pass
658 16:49:56.017385 cs1 DataBus test pass
659 16:49:56.017873 cs0 AddrBus test pass
660 16:49:56.023010 cs1 AddrBus test pass
661 16:49:56.023526
662 16:49:56.024017 100bdlr_step_size ps== 478
663 16:49:56.024491 result report
664 16:49:56.028675 boot times 0Enable ddr reg access
665 16:49:56.034939 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 16:49:56.048748 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 16:49:56.703318 bl2z: ptr: 05129330, size: 00001e40
668 16:49:56.708841 0.0;M3 CHK:0;cm4_sp_mode 0
669 16:49:56.709383 MVN_1=0x00000000
670 16:49:56.709833 MVN_2=0x00000000
671 16:49:56.720345 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 16:49:56.720850 OPS=0x04
673 16:49:56.721298 ring efuse init
674 16:49:56.725935 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 16:49:56.726427 [0.017310 Inits done]
676 16:49:56.726869 secure task start!
677 16:49:56.733478 high task start!
678 16:49:56.733967 low task start!
679 16:49:56.734411 run into bl31
680 16:49:56.742024 NOTICE: BL31: v1.3(release):4fc40b1
681 16:49:56.749806 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 16:49:56.750296 NOTICE: BL31: G12A normal boot!
683 16:49:56.765365 NOTICE: BL31: BL33 decompress pass
684 16:49:56.771032 ERROR: Error initializing runtime service opteed_fast
685 16:49:57.565208
686 16:49:57.565839
687 16:49:57.570728 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 16:49:57.571227
689 16:49:57.574184 Model: Libre Computer AML-S905D3-CC Solitude
690 16:49:57.720917 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 16:49:57.736417 DRAM: 2 GiB (effective 3.8 GiB)
692 16:49:57.837341 Core: 406 devices, 33 uclasses, devicetree: separate
693 16:49:57.843195 WDT: Not starting watchdog@f0d0
694 16:49:57.868281 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 16:49:57.880508 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 16:49:57.885469 ** Bad device specification mmc 0 **
697 16:49:57.895569 Card did not respond to voltage select! : -110
698 16:49:57.903146 ** Bad device specification mmc 0 **
699 16:49:57.903651 Couldn't find partition mmc 0
700 16:49:57.911567 Card did not respond to voltage select! : -110
701 16:49:57.916996 ** Bad device specification mmc 0 **
702 16:49:57.917463 Couldn't find partition mmc 0
703 16:49:57.922050 Error: could not access storage.
704 16:49:58.219558 Net: eth0: ethernet@ff3f0000
705 16:49:58.220193 starting USB...
706 16:49:58.464158 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 16:49:58.464579 Starting the controller
708 16:49:58.471055 USB XHCI 1.10
709 16:50:00.024905 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 16:50:00.033210 scanning usb for storage devices... 0 Storage Device(s) found
712 16:50:00.084427 Hit any key to stop autoboot: 1
713 16:50:00.085461 end: 2.4.2 bootloader-interrupt (duration 00:00:18) [common]
714 16:50:00.085847 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 16:50:00.086103 Setting prompt string to ['=>']
716 16:50:00.086363 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 16:50:00.099267 0
718 16:50:00.099950 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 16:50:00.201012 => setenv autoload no
721 16:50:00.201926 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
722 16:50:00.205955 setenv autoload no
724 16:50:00.307021 => setenv initrd_high 0xffffffff
725 16:50:00.307731 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
726 16:50:00.312037 setenv initrd_high 0xffffffff
728 16:50:00.413571 => setenv fdt_high 0xffffffff
729 16:50:00.414359 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
730 16:50:00.418874 setenv fdt_high 0xffffffff
732 16:50:00.520398 => dhcp
733 16:50:00.521120 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
734 16:50:00.525249 dhcp
735 16:50:01.030630 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 16:50:01.031015 Speed: 1000, full duplex
737 16:50:01.031223 BOOTP broadcast 1
738 16:50:01.278817 BOOTP broadcast 2
739 16:50:01.309868 DHCP client bound to address 192.168.6.21 (278 ms)
741 16:50:01.411505 => setenv serverip 192.168.6.2
742 16:50:01.412316 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
743 16:50:01.416825 setenv serverip 192.168.6.2
745 16:50:01.518252 => tftpboot 0x01080000 975710/tftp-deploy-gj5mxchg/kernel/uImage
746 16:50:01.519040 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
747 16:50:01.525828 tftpboot 0x01080000 975710/tftp-deploy-gj5mxchg/kernel/uImage
748 16:50:01.526339 Speed: 1000, full duplex
749 16:50:01.526753 Using ethernet@ff3f0000 device
750 16:50:01.531333 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
751 16:50:01.536620 Filename '975710/tftp-deploy-gj5mxchg/kernel/uImage'.
752 16:50:01.540576 Load address: 0x1080000
753 16:50:04.414955 Loading: *################################################## 43.6 MiB
754 16:50:04.415756 15.2 MiB/s
755 16:50:04.416398 done
756 16:50:04.419367 Bytes transferred = 45713984 (2b98a40 hex)
758 16:50:04.521243 => tftpboot 0x08000000 975710/tftp-deploy-gj5mxchg/ramdisk/ramdisk.cpio.gz.uboot
759 16:50:04.522211 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
760 16:50:04.528712 tftpboot 0x08000000 975710/tftp-deploy-gj5mxchg/ramdisk/ramdisk.cpio.gz.uboot
761 16:50:04.529302 Speed: 1000, full duplex
762 16:50:04.529824 Using ethernet@ff3f0000 device
763 16:50:04.534215 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
764 16:50:04.544058 Filename '975710/tftp-deploy-gj5mxchg/ramdisk/ramdisk.cpio.gz.uboot'.
765 16:50:04.544623 Load address: 0x8000000
766 16:50:07.245819 Loading: *########################## UDP wrong checksum 00000005 00004005
767 16:50:13.563217 T ####################### UDP wrong checksum 0000000f 0000b36a
768 16:50:18.564325 T UDP wrong checksum 0000000f 0000b36a
769 16:50:28.565605 T T UDP wrong checksum 0000000f 0000b36a
770 16:50:48.569870 T T T T UDP wrong checksum 0000000f 0000b36a
771 16:51:03.573336 T T
772 16:51:03.573930 Retry count exceeded; starting again
774 16:51:03.575347 end: 2.4.3 bootloader-commands (duration 00:01:03) [common]
777 16:51:03.577277 end: 2.4 uboot-commands (duration 00:01:22) [common]
779 16:51:03.578634 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
781 16:51:03.579693 end: 2 uboot-action (duration 00:01:22) [common]
783 16:51:03.581213 Cleaning after the job
784 16:51:03.581746 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975710/tftp-deploy-gj5mxchg/ramdisk
785 16:51:03.583092 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975710/tftp-deploy-gj5mxchg/kernel
786 16:51:03.590441 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975710/tftp-deploy-gj5mxchg/dtb
787 16:51:03.591662 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975710/tftp-deploy-gj5mxchg/modules
788 16:51:03.597746 start: 4.1 power-off (timeout 00:00:30) [common]
789 16:51:03.598719 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
790 16:51:03.634375 >> OK - accepted request
791 16:51:03.636631 Returned 0 in 0 seconds
792 16:51:03.737815 end: 4.1 power-off (duration 00:00:00) [common]
794 16:51:03.739532 start: 4.2 read-feedback (timeout 00:10:00) [common]
795 16:51:03.740693 Listened to connection for namespace 'common' for up to 1s
796 16:51:04.741491 Finalising connection for namespace 'common'
797 16:51:04.742218 Disconnecting from shell: Finalise
798 16:51:04.742734 =>
799 16:51:04.843774 end: 4.2 read-feedback (duration 00:00:01) [common]
800 16:51:04.844551 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/975710
801 16:51:05.503109 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/975710
802 16:51:05.503716 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.