Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 17:28:22.052719 lava-dispatcher, installed at version: 2024.01
2 17:28:22.053488 start: 0 validate
3 17:28:22.053975 Start time: 2024-11-11 17:28:22.053944+00:00 (UTC)
4 17:28:22.054507 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 17:28:22.055059 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 17:28:22.097876 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 17:28:22.098420 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fmaster%2Frenesas-devel-2024-11-11-v6.12-rc7%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 17:28:22.131578 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 17:28:22.132402 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fmaster%2Frenesas-devel-2024-11-11-v6.12-rc7%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 17:28:22.169116 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 17:28:22.169615 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 17:28:22.202629 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 17:28:22.203115 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fmaster%2Frenesas-devel-2024-11-11-v6.12-rc7%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 17:28:22.242804 validate duration: 0.19
16 17:28:22.243641 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 17:28:22.243959 start: 1.1 download-retry (timeout 00:10:00) [common]
18 17:28:22.244301 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 17:28:22.244878 Not decompressing ramdisk as can be used compressed.
20 17:28:22.245326 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 17:28:22.245601 saving as /var/lib/lava/dispatcher/tmp/975787/tftp-deploy-9lpck33t/ramdisk/initrd.cpio.gz
22 17:28:22.245858 total size: 5628169 (5 MB)
23 17:28:22.286830 progress 0 % (0 MB)
24 17:28:22.294504 progress 5 % (0 MB)
25 17:28:22.302306 progress 10 % (0 MB)
26 17:28:22.308742 progress 15 % (0 MB)
27 17:28:22.312898 progress 20 % (1 MB)
28 17:28:22.316773 progress 25 % (1 MB)
29 17:28:22.321099 progress 30 % (1 MB)
30 17:28:22.325215 progress 35 % (1 MB)
31 17:28:22.328857 progress 40 % (2 MB)
32 17:28:22.332886 progress 45 % (2 MB)
33 17:28:22.336527 progress 50 % (2 MB)
34 17:28:22.340592 progress 55 % (2 MB)
35 17:28:22.344754 progress 60 % (3 MB)
36 17:28:22.348673 progress 65 % (3 MB)
37 17:28:22.352704 progress 70 % (3 MB)
38 17:28:22.356377 progress 75 % (4 MB)
39 17:28:22.360385 progress 80 % (4 MB)
40 17:28:22.363973 progress 85 % (4 MB)
41 17:28:22.368052 progress 90 % (4 MB)
42 17:28:22.371901 progress 95 % (5 MB)
43 17:28:22.375219 progress 100 % (5 MB)
44 17:28:22.375911 5 MB downloaded in 0.13 s (41.28 MB/s)
45 17:28:22.376531 end: 1.1.1 http-download (duration 00:00:00) [common]
47 17:28:22.377482 end: 1.1 download-retry (duration 00:00:00) [common]
48 17:28:22.377802 start: 1.2 download-retry (timeout 00:10:00) [common]
49 17:28:22.378092 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 17:28:22.378580 downloading http://storage.kernelci.org/renesas/master/renesas-devel-2024-11-11-v6.12-rc7/arm64/defconfig/gcc-12/kernel/Image
51 17:28:22.378846 saving as /var/lib/lava/dispatcher/tmp/975787/tftp-deploy-9lpck33t/kernel/Image
52 17:28:22.379070 total size: 45713920 (43 MB)
53 17:28:22.379290 No compression specified
54 17:28:22.417102 progress 0 % (0 MB)
55 17:28:22.447462 progress 5 % (2 MB)
56 17:28:22.477813 progress 10 % (4 MB)
57 17:28:22.508048 progress 15 % (6 MB)
58 17:28:22.539002 progress 20 % (8 MB)
59 17:28:22.568671 progress 25 % (10 MB)
60 17:28:22.598985 progress 30 % (13 MB)
61 17:28:22.629576 progress 35 % (15 MB)
62 17:28:22.660323 progress 40 % (17 MB)
63 17:28:22.690773 progress 45 % (19 MB)
64 17:28:22.720829 progress 50 % (21 MB)
65 17:28:22.751693 progress 55 % (24 MB)
66 17:28:22.782403 progress 60 % (26 MB)
67 17:28:22.812415 progress 65 % (28 MB)
68 17:28:22.843034 progress 70 % (30 MB)
69 17:28:22.873284 progress 75 % (32 MB)
70 17:28:22.902414 progress 80 % (34 MB)
71 17:28:22.930629 progress 85 % (37 MB)
72 17:28:22.959208 progress 90 % (39 MB)
73 17:28:22.988212 progress 95 % (41 MB)
74 17:28:23.016446 progress 100 % (43 MB)
75 17:28:23.016983 43 MB downloaded in 0.64 s (68.34 MB/s)
76 17:28:23.017473 end: 1.2.1 http-download (duration 00:00:01) [common]
78 17:28:23.018298 end: 1.2 download-retry (duration 00:00:01) [common]
79 17:28:23.018579 start: 1.3 download-retry (timeout 00:09:59) [common]
80 17:28:23.018843 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 17:28:23.019314 downloading http://storage.kernelci.org/renesas/master/renesas-devel-2024-11-11-v6.12-rc7/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 17:28:23.019598 saving as /var/lib/lava/dispatcher/tmp/975787/tftp-deploy-9lpck33t/dtb/meson-g12b-a311d-libretech-cc.dtb
83 17:28:23.019807 total size: 54703 (0 MB)
84 17:28:23.020043 No compression specified
85 17:28:23.058629 progress 59 % (0 MB)
86 17:28:23.059485 progress 100 % (0 MB)
87 17:28:23.060083 0 MB downloaded in 0.04 s (1.30 MB/s)
88 17:28:23.060595 end: 1.3.1 http-download (duration 00:00:00) [common]
90 17:28:23.061417 end: 1.3 download-retry (duration 00:00:00) [common]
91 17:28:23.061681 start: 1.4 download-retry (timeout 00:09:59) [common]
92 17:28:23.061943 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 17:28:23.062398 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 17:28:23.062644 saving as /var/lib/lava/dispatcher/tmp/975787/tftp-deploy-9lpck33t/nfsrootfs/full.rootfs.tar
95 17:28:23.062848 total size: 120894716 (115 MB)
96 17:28:23.063058 Using unxz to decompress xz
97 17:28:23.100187 progress 0 % (0 MB)
98 17:28:23.943155 progress 5 % (5 MB)
99 17:28:24.865007 progress 10 % (11 MB)
100 17:28:25.651680 progress 15 % (17 MB)
101 17:28:26.380820 progress 20 % (23 MB)
102 17:28:26.974126 progress 25 % (28 MB)
103 17:28:27.834329 progress 30 % (34 MB)
104 17:28:28.630263 progress 35 % (40 MB)
105 17:28:29.009247 progress 40 % (46 MB)
106 17:28:29.403635 progress 45 % (51 MB)
107 17:28:30.122377 progress 50 % (57 MB)
108 17:28:31.002552 progress 55 % (63 MB)
109 17:28:31.786451 progress 60 % (69 MB)
110 17:28:32.545251 progress 65 % (74 MB)
111 17:28:33.327752 progress 70 % (80 MB)
112 17:28:34.164993 progress 75 % (86 MB)
113 17:28:34.977061 progress 80 % (92 MB)
114 17:28:35.738845 progress 85 % (98 MB)
115 17:28:36.657247 progress 90 % (103 MB)
116 17:28:37.443077 progress 95 % (109 MB)
117 17:28:38.268335 progress 100 % (115 MB)
118 17:28:38.280797 115 MB downloaded in 15.22 s (7.58 MB/s)
119 17:28:38.281760 end: 1.4.1 http-download (duration 00:00:15) [common]
121 17:28:38.283474 end: 1.4 download-retry (duration 00:00:15) [common]
122 17:28:38.284084 start: 1.5 download-retry (timeout 00:09:44) [common]
123 17:28:38.284650 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 17:28:38.285874 downloading http://storage.kernelci.org/renesas/master/renesas-devel-2024-11-11-v6.12-rc7/arm64/defconfig/gcc-12/modules.tar.xz
125 17:28:38.286394 saving as /var/lib/lava/dispatcher/tmp/975787/tftp-deploy-9lpck33t/modules/modules.tar
126 17:28:38.286837 total size: 11621176 (11 MB)
127 17:28:38.287287 Using unxz to decompress xz
128 17:28:38.335272 progress 0 % (0 MB)
129 17:28:38.402269 progress 5 % (0 MB)
130 17:28:38.475586 progress 10 % (1 MB)
131 17:28:38.570433 progress 15 % (1 MB)
132 17:28:38.662555 progress 20 % (2 MB)
133 17:28:38.749548 progress 25 % (2 MB)
134 17:28:38.829301 progress 30 % (3 MB)
135 17:28:38.907101 progress 35 % (3 MB)
136 17:28:38.978958 progress 40 % (4 MB)
137 17:28:39.054602 progress 45 % (5 MB)
138 17:28:39.138759 progress 50 % (5 MB)
139 17:28:39.220951 progress 55 % (6 MB)
140 17:28:39.302283 progress 60 % (6 MB)
141 17:28:39.383505 progress 65 % (7 MB)
142 17:28:39.464455 progress 70 % (7 MB)
143 17:28:39.542169 progress 75 % (8 MB)
144 17:28:39.625581 progress 80 % (8 MB)
145 17:28:39.705707 progress 85 % (9 MB)
146 17:28:39.788917 progress 90 % (10 MB)
147 17:28:39.862367 progress 95 % (10 MB)
148 17:28:39.938777 progress 100 % (11 MB)
149 17:28:39.951867 11 MB downloaded in 1.67 s (6.66 MB/s)
150 17:28:39.952769 end: 1.5.1 http-download (duration 00:00:02) [common]
152 17:28:39.954343 end: 1.5 download-retry (duration 00:00:02) [common]
153 17:28:39.954856 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 17:28:39.955364 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 17:28:56.393890 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/975787/extract-nfsrootfs-u32cir2o
156 17:28:56.394494 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 17:28:56.394781 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 17:28:56.395418 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl
159 17:28:56.395858 makedir: /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin
160 17:28:56.396229 makedir: /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/tests
161 17:28:56.396542 makedir: /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/results
162 17:28:56.396880 Creating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-add-keys
163 17:28:56.397449 Creating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-add-sources
164 17:28:56.397976 Creating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-background-process-start
165 17:28:56.398552 Creating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-background-process-stop
166 17:28:56.399076 Creating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-common-functions
167 17:28:56.399565 Creating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-echo-ipv4
168 17:28:56.400093 Creating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-install-packages
169 17:28:56.400588 Creating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-installed-packages
170 17:28:56.401138 Creating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-os-build
171 17:28:56.401621 Creating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-probe-channel
172 17:28:56.402095 Creating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-probe-ip
173 17:28:56.402581 Creating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-target-ip
174 17:28:56.403045 Creating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-target-mac
175 17:28:56.403508 Creating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-target-storage
176 17:28:56.404030 Creating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-test-case
177 17:28:56.404536 Creating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-test-event
178 17:28:56.405003 Creating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-test-feedback
179 17:28:56.405469 Creating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-test-raise
180 17:28:56.405930 Creating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-test-reference
181 17:28:56.406390 Creating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-test-runner
182 17:28:56.406857 Creating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-test-set
183 17:28:56.407317 Creating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-test-shell
184 17:28:56.407810 Updating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-add-keys (debian)
185 17:28:56.408397 Updating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-add-sources (debian)
186 17:28:56.408899 Updating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-install-packages (debian)
187 17:28:56.409391 Updating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-installed-packages (debian)
188 17:28:56.409871 Updating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/bin/lava-os-build (debian)
189 17:28:56.410294 Creating /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/environment
190 17:28:56.410655 LAVA metadata
191 17:28:56.410912 - LAVA_JOB_ID=975787
192 17:28:56.411125 - LAVA_DISPATCHER_IP=192.168.6.2
193 17:28:56.411487 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 17:28:56.412472 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 17:28:56.412787 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 17:28:56.412995 skipped lava-vland-overlay
197 17:28:56.413233 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 17:28:56.413482 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 17:28:56.413697 skipped lava-multinode-overlay
200 17:28:56.413937 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 17:28:56.414185 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 17:28:56.414431 Loading test definitions
203 17:28:56.414704 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 17:28:56.414919 Using /lava-975787 at stage 0
205 17:28:56.416009 uuid=975787_1.6.2.4.1 testdef=None
206 17:28:56.416317 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 17:28:56.416576 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 17:28:56.418142 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 17:28:56.418923 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 17:28:56.420872 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 17:28:56.421685 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 17:28:56.423489 runner path: /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/0/tests/0_timesync-off test_uuid 975787_1.6.2.4.1
215 17:28:56.424067 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 17:28:56.424879 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 17:28:56.425101 Using /lava-975787 at stage 0
219 17:28:56.425455 Fetching tests from https://github.com/kernelci/test-definitions.git
220 17:28:56.425744 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/0/tests/1_kselftest-alsa'
221 17:28:59.830671 Running '/usr/bin/git checkout kernelci.org
222 17:29:00.282205 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 17:29:00.283643 uuid=975787_1.6.2.4.5 testdef=None
224 17:29:00.284039 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 17:29:00.284802 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 17:29:00.287596 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 17:29:00.288431 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 17:29:00.292134 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 17:29:00.292978 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 17:29:00.296536 runner path: /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/0/tests/1_kselftest-alsa test_uuid 975787_1.6.2.4.5
234 17:29:00.296819 BOARD='meson-g12b-a311d-libretech-cc'
235 17:29:00.297024 BRANCH='renesas'
236 17:29:00.297219 SKIPFILE='/dev/null'
237 17:29:00.297418 SKIP_INSTALL='True'
238 17:29:00.297612 TESTPROG_URL='http://storage.kernelci.org/renesas/master/renesas-devel-2024-11-11-v6.12-rc7/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 17:29:00.297810 TST_CASENAME=''
240 17:29:00.298003 TST_CMDFILES='alsa'
241 17:29:00.298570 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 17:29:00.299354 Creating lava-test-runner.conf files
244 17:29:00.299557 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/975787/lava-overlay-o91pb7wl/lava-975787/0 for stage 0
245 17:29:00.299902 - 0_timesync-off
246 17:29:00.300160 - 1_kselftest-alsa
247 17:29:00.300498 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 17:29:00.300774 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 17:29:24.801177 end: 1.6.2.5 compress-overlay (duration 00:00:25) [common]
250 17:29:24.801641 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:57) [common]
251 17:29:24.801909 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 17:29:24.802182 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
253 17:29:24.802448 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:57) [common]
254 17:29:25.545914 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 17:29:25.546421 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 17:29:25.546704 extracting modules file /var/lib/lava/dispatcher/tmp/975787/tftp-deploy-9lpck33t/modules/modules.tar to /var/lib/lava/dispatcher/tmp/975787/extract-nfsrootfs-u32cir2o
257 17:29:27.098605 extracting modules file /var/lib/lava/dispatcher/tmp/975787/tftp-deploy-9lpck33t/modules/modules.tar to /var/lib/lava/dispatcher/tmp/975787/extract-overlay-ramdisk-reuisyex/ramdisk
258 17:29:28.519903 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 17:29:28.520423 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 17:29:28.520703 [common] Applying overlay to NFS
261 17:29:28.520917 [common] Applying overlay /var/lib/lava/dispatcher/tmp/975787/compress-overlay-8y_m5oon/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/975787/extract-nfsrootfs-u32cir2o
262 17:29:31.370579 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 17:29:31.371079 start: 1.6.6 prepare-kernel (timeout 00:08:51) [common]
264 17:29:31.371369 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:51) [common]
265 17:29:31.371600 Converting downloaded kernel to a uImage
266 17:29:31.371911 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/975787/tftp-deploy-9lpck33t/kernel/Image /var/lib/lava/dispatcher/tmp/975787/tftp-deploy-9lpck33t/kernel/uImage
267 17:29:31.986689 output: Image Name:
268 17:29:31.987124 output: Created: Mon Nov 11 17:29:31 2024
269 17:29:31.987338 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 17:29:31.987544 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 17:29:31.987745 output: Load Address: 01080000
272 17:29:31.987948 output: Entry Point: 01080000
273 17:29:31.988202 output:
274 17:29:31.988551 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 17:29:31.988827 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 17:29:31.989098 start: 1.6.7 configure-preseed-file (timeout 00:08:50) [common]
277 17:29:31.989352 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 17:29:31.989611 start: 1.6.8 compress-ramdisk (timeout 00:08:50) [common]
279 17:29:31.989871 Building ramdisk /var/lib/lava/dispatcher/tmp/975787/extract-overlay-ramdisk-reuisyex/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/975787/extract-overlay-ramdisk-reuisyex/ramdisk
280 17:29:34.467834 >> 166829 blocks
281 17:29:42.261191 Adding RAMdisk u-boot header.
282 17:29:42.261859 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/975787/extract-overlay-ramdisk-reuisyex/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/975787/extract-overlay-ramdisk-reuisyex/ramdisk.cpio.gz.uboot
283 17:29:42.516739 output: Image Name:
284 17:29:42.517161 output: Created: Mon Nov 11 17:29:42 2024
285 17:29:42.517371 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 17:29:42.517577 output: Data Size: 23434735 Bytes = 22885.48 KiB = 22.35 MiB
287 17:29:42.517780 output: Load Address: 00000000
288 17:29:42.517979 output: Entry Point: 00000000
289 17:29:42.518180 output:
290 17:29:42.518917 rename /var/lib/lava/dispatcher/tmp/975787/extract-overlay-ramdisk-reuisyex/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/975787/tftp-deploy-9lpck33t/ramdisk/ramdisk.cpio.gz.uboot
291 17:29:42.519361 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
292 17:29:42.519646 end: 1.6 prepare-tftp-overlay (duration 00:01:03) [common]
293 17:29:42.519921 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:40) [common]
294 17:29:42.520422 No LXC device requested
295 17:29:42.520985 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 17:29:42.521548 start: 1.8 deploy-device-env (timeout 00:08:40) [common]
297 17:29:42.522091 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 17:29:42.522553 Checking files for TFTP limit of 4294967296 bytes.
299 17:29:42.525602 end: 1 tftp-deploy (duration 00:01:20) [common]
300 17:29:42.526255 start: 2 uboot-action (timeout 00:05:00) [common]
301 17:29:42.526831 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 17:29:42.527379 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 17:29:42.527938 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 17:29:42.528559 Using kernel file from prepare-kernel: 975787/tftp-deploy-9lpck33t/kernel/uImage
305 17:29:42.529256 substitutions:
306 17:29:42.529709 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 17:29:42.530154 - {DTB_ADDR}: 0x01070000
308 17:29:42.530598 - {DTB}: 975787/tftp-deploy-9lpck33t/dtb/meson-g12b-a311d-libretech-cc.dtb
309 17:29:42.531043 - {INITRD}: 975787/tftp-deploy-9lpck33t/ramdisk/ramdisk.cpio.gz.uboot
310 17:29:42.531482 - {KERNEL_ADDR}: 0x01080000
311 17:29:42.531919 - {KERNEL}: 975787/tftp-deploy-9lpck33t/kernel/uImage
312 17:29:42.532389 - {LAVA_MAC}: None
313 17:29:42.532869 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/975787/extract-nfsrootfs-u32cir2o
314 17:29:42.533312 - {NFS_SERVER_IP}: 192.168.6.2
315 17:29:42.533746 - {PRESEED_CONFIG}: None
316 17:29:42.534179 - {PRESEED_LOCAL}: None
317 17:29:42.534613 - {RAMDISK_ADDR}: 0x08000000
318 17:29:42.535045 - {RAMDISK}: 975787/tftp-deploy-9lpck33t/ramdisk/ramdisk.cpio.gz.uboot
319 17:29:42.535478 - {ROOT_PART}: None
320 17:29:42.535909 - {ROOT}: None
321 17:29:42.536367 - {SERVER_IP}: 192.168.6.2
322 17:29:42.536798 - {TEE_ADDR}: 0x83000000
323 17:29:42.537227 - {TEE}: None
324 17:29:42.537655 Parsed boot commands:
325 17:29:42.538076 - setenv autoload no
326 17:29:42.538499 - setenv initrd_high 0xffffffff
327 17:29:42.538924 - setenv fdt_high 0xffffffff
328 17:29:42.539347 - dhcp
329 17:29:42.539775 - setenv serverip 192.168.6.2
330 17:29:42.540232 - tftpboot 0x01080000 975787/tftp-deploy-9lpck33t/kernel/uImage
331 17:29:42.540668 - tftpboot 0x08000000 975787/tftp-deploy-9lpck33t/ramdisk/ramdisk.cpio.gz.uboot
332 17:29:42.541097 - tftpboot 0x01070000 975787/tftp-deploy-9lpck33t/dtb/meson-g12b-a311d-libretech-cc.dtb
333 17:29:42.541529 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/975787/extract-nfsrootfs-u32cir2o,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 17:29:42.541970 - bootm 0x01080000 0x08000000 0x01070000
335 17:29:42.542529 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 17:29:42.544191 start: 2.3 connect-device (timeout 00:05:00) [common]
338 17:29:42.544655 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 17:29:42.560727 Setting prompt string to ['lava-test: # ']
340 17:29:42.562393 end: 2.3 connect-device (duration 00:00:00) [common]
341 17:29:42.563068 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 17:29:42.563691 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 17:29:42.564357 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 17:29:42.565922 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 17:29:42.604825 >> OK - accepted request
346 17:29:42.607382 Returned 0 in 0 seconds
347 17:29:42.708646 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 17:29:42.710472 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 17:29:42.711097 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 17:29:42.711668 Setting prompt string to ['Hit any key to stop autoboot']
352 17:29:42.712235 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 17:29:42.713999 Trying 192.168.56.21...
354 17:29:42.714540 Connected to conserv1.
355 17:29:42.715006 Escape character is '^]'.
356 17:29:42.715467
357 17:29:42.715930 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 17:29:42.716658
359 17:29:53.696775 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
360 17:29:53.697419 bl2_stage_init 0x81
361 17:29:53.702322 hw id: 0x0000 - pwm id 0x01
362 17:29:53.702771 bl2_stage_init 0xc1
363 17:29:53.703169 bl2_stage_init 0x02
364 17:29:53.703576
365 17:29:53.707748 L0:00000000
366 17:29:53.708234 L1:20000703
367 17:29:53.708643 L2:00008067
368 17:29:53.709056 L3:14000000
369 17:29:53.709452 B2:00402000
370 17:29:53.713279 B1:e0f83180
371 17:29:53.713719
372 17:29:53.714122 TE: 58150
373 17:29:53.714518
374 17:29:53.718961 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
375 17:29:53.719378
376 17:29:53.719767 Board ID = 1
377 17:29:53.724640 Set A53 clk to 24M
378 17:29:53.725056 Set A73 clk to 24M
379 17:29:53.725441 Set clk81 to 24M
380 17:29:53.730078 A53 clk: 1200 MHz
381 17:29:53.730490 A73 clk: 1200 MHz
382 17:29:53.730875 CLK81: 166.6M
383 17:29:53.731253 smccc: 00012aac
384 17:29:53.735648 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
385 17:29:53.741309 board id: 1
386 17:29:53.747188 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
387 17:29:53.757732 fw parse done
388 17:29:53.763257 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
389 17:29:53.806379 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
390 17:29:53.817230 PIEI prepare done
391 17:29:53.817660 fastboot data load
392 17:29:53.818051 fastboot data verify
393 17:29:53.822963 verify result: 266
394 17:29:53.828496 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
395 17:29:53.828916 LPDDR4 probe
396 17:29:53.829307 ddr clk to 1584MHz
397 17:29:53.835532 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
398 17:29:53.872951
399 17:29:53.873465 dmc_version 0001
400 17:29:53.880410 Check phy result
401 17:29:53.886274 INFO : End of CA training
402 17:29:53.886689 INFO : End of initialization
403 17:29:53.891908 INFO : Training has run successfully!
404 17:29:53.892368 Check phy result
405 17:29:53.897476 INFO : End of initialization
406 17:29:53.897890 INFO : End of read enable training
407 17:29:53.903170 INFO : End of fine write leveling
408 17:29:53.908685 INFO : End of Write leveling coarse delay
409 17:29:53.909096 INFO : Training has run successfully!
410 17:29:53.909488 Check phy result
411 17:29:53.914247 INFO : End of initialization
412 17:29:53.914666 INFO : End of read dq deskew training
413 17:29:53.919823 INFO : End of MPR read delay center optimization
414 17:29:53.925441 INFO : End of write delay center optimization
415 17:29:53.931150 INFO : End of read delay center optimization
416 17:29:53.931570 INFO : End of max read latency training
417 17:29:53.936686 INFO : Training has run successfully!
418 17:29:53.937101 1D training succeed
419 17:29:53.945981 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
420 17:29:53.993526 Check phy result
421 17:29:53.993946 INFO : End of initialization
422 17:29:54.015285 INFO : End of 2D read delay Voltage center optimization
423 17:29:54.035646 INFO : End of 2D read delay Voltage center optimization
424 17:29:54.087568 INFO : End of 2D write delay Voltage center optimization
425 17:29:54.136874 INFO : End of 2D write delay Voltage center optimization
426 17:29:54.142412 INFO : Training has run successfully!
427 17:29:54.142840
428 17:29:54.143236 channel==0
429 17:29:54.148202 RxClkDly_Margin_A0==88 ps 9
430 17:29:54.148632 TxDqDly_Margin_A0==98 ps 10
431 17:29:54.153702 RxClkDly_Margin_A1==88 ps 9
432 17:29:54.154114 TxDqDly_Margin_A1==98 ps 10
433 17:29:54.154506 TrainedVREFDQ_A0==74
434 17:29:54.159294 TrainedVREFDQ_A1==74
435 17:29:54.159709 VrefDac_Margin_A0==25
436 17:29:54.160145 DeviceVref_Margin_A0==40
437 17:29:54.164767 VrefDac_Margin_A1==25
438 17:29:54.165180 DeviceVref_Margin_A1==40
439 17:29:54.165566
440 17:29:54.165954
441 17:29:54.170469 channel==1
442 17:29:54.170880 RxClkDly_Margin_A0==98 ps 10
443 17:29:54.171268 TxDqDly_Margin_A0==88 ps 9
444 17:29:54.176093 RxClkDly_Margin_A1==98 ps 10
445 17:29:54.176504 TxDqDly_Margin_A1==88 ps 9
446 17:29:54.181590 TrainedVREFDQ_A0==76
447 17:29:54.182004 TrainedVREFDQ_A1==77
448 17:29:54.182394 VrefDac_Margin_A0==22
449 17:29:54.187258 DeviceVref_Margin_A0==38
450 17:29:54.187666 VrefDac_Margin_A1==22
451 17:29:54.192929 DeviceVref_Margin_A1==37
452 17:29:54.193346
453 17:29:54.193738 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
454 17:29:54.194128
455 17:29:54.226460 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
456 17:29:54.226951 2D training succeed
457 17:29:54.232103 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
458 17:29:54.237581 auto size-- 65535DDR cs0 size: 2048MB
459 17:29:54.238001 DDR cs1 size: 2048MB
460 17:29:54.243196 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
461 17:29:54.243628 cs0 DataBus test pass
462 17:29:54.248815 cs1 DataBus test pass
463 17:29:54.249230 cs0 AddrBus test pass
464 17:29:54.249616 cs1 AddrBus test pass
465 17:29:54.250001
466 17:29:54.254370 100bdlr_step_size ps== 420
467 17:29:54.254793 result report
468 17:29:54.260215 boot times 0Enable ddr reg access
469 17:29:54.265362 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
470 17:29:54.278850 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
471 17:29:54.852653 0.0;M3 CHK:0;cm4_sp_mode 0
472 17:29:54.853247 MVN_1=0x00000000
473 17:29:54.858281 MVN_2=0x00000000
474 17:29:54.863796 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
475 17:29:54.864267 OPS=0x10
476 17:29:54.864667 ring efuse init
477 17:29:54.865055 chipver efuse init
478 17:29:54.869542 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
479 17:29:54.875034 [0.018960 Inits done]
480 17:29:54.875453 secure task start!
481 17:29:54.875841 high task start!
482 17:29:54.879661 low task start!
483 17:29:54.880107 run into bl31
484 17:29:54.886345 NOTICE: BL31: v1.3(release):4fc40b1
485 17:29:54.893989 NOTICE: BL31: Built : 15:58:17, May 22 2019
486 17:29:54.894408 NOTICE: BL31: G12A normal boot!
487 17:29:54.919413 NOTICE: BL31: BL33 decompress pass
488 17:29:54.925163 ERROR: Error initializing runtime service opteed_fast
489 17:29:56.158008
490 17:29:56.158612
491 17:29:56.166399 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
492 17:29:56.166840
493 17:29:56.167254 Model: Libre Computer AML-A311D-CC Alta
494 17:29:56.374944 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
495 17:29:56.398136 DRAM: 2 GiB (effective 3.8 GiB)
496 17:29:56.541256 Core: 408 devices, 31 uclasses, devicetree: separate
497 17:29:56.547027 WDT: Not starting watchdog@f0d0
498 17:29:56.579526 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
499 17:29:56.591715 Loading Environment from FAT... Card did not respond to voltage select! : -110
500 17:29:56.596798 ** Bad device specification mmc 0 **
501 17:29:56.607150 Card did not respond to voltage select! : -110
502 17:29:56.614769 ** Bad device specification mmc 0 **
503 17:29:56.615198 Couldn't find partition mmc 0
504 17:29:56.623162 Card did not respond to voltage select! : -110
505 17:29:56.628661 ** Bad device specification mmc 0 **
506 17:29:56.629092 Couldn't find partition mmc 0
507 17:29:56.633705 Error: could not access storage.
508 17:29:57.896916 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
509 17:29:57.897533 bl2_stage_init 0x01
510 17:29:57.897970 bl2_stage_init 0x81
511 17:29:57.902350 hw id: 0x0000 - pwm id 0x01
512 17:29:57.902803 bl2_stage_init 0xc1
513 17:29:57.903217 bl2_stage_init 0x02
514 17:29:57.903624
515 17:29:57.907952 L0:00000000
516 17:29:57.908416 L1:20000703
517 17:29:57.908822 L2:00008067
518 17:29:57.909218 L3:14000000
519 17:29:57.910893 B2:00402000
520 17:29:57.911335 B1:e0f83180
521 17:29:57.911737
522 17:29:57.912172 TE: 58124
523 17:29:57.912578
524 17:29:57.922098 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
525 17:29:57.922541
526 17:29:57.922949 Board ID = 1
527 17:29:57.923345 Set A53 clk to 24M
528 17:29:57.923738 Set A73 clk to 24M
529 17:29:57.927686 Set clk81 to 24M
530 17:29:57.928165 A53 clk: 1200 MHz
531 17:29:57.928574 A73 clk: 1200 MHz
532 17:29:57.933163 CLK81: 166.6M
533 17:29:57.933595 smccc: 00012a92
534 17:29:57.938682 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
535 17:29:57.939135 board id: 1
536 17:29:57.947288 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
537 17:29:57.957927 fw parse done
538 17:29:57.963827 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
539 17:29:58.006526 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
540 17:29:58.017418 PIEI prepare done
541 17:29:58.017887 fastboot data load
542 17:29:58.018303 fastboot data verify
543 17:29:58.023179 verify result: 266
544 17:29:58.028763 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
545 17:29:58.029195 LPDDR4 probe
546 17:29:58.029598 ddr clk to 1584MHz
547 17:29:58.036870 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
548 17:29:58.073990
549 17:29:58.074442 dmc_version 0001
550 17:29:58.080677 Check phy result
551 17:29:58.086562 INFO : End of CA training
552 17:29:58.086995 INFO : End of initialization
553 17:29:58.092103 INFO : Training has run successfully!
554 17:29:58.092531 Check phy result
555 17:29:58.097760 INFO : End of initialization
556 17:29:58.098187 INFO : End of read enable training
557 17:29:58.101031 INFO : End of fine write leveling
558 17:29:58.106492 INFO : End of Write leveling coarse delay
559 17:29:58.112200 INFO : Training has run successfully!
560 17:29:58.112625 Check phy result
561 17:29:58.113026 INFO : End of initialization
562 17:29:58.117782 INFO : End of read dq deskew training
563 17:29:58.123374 INFO : End of MPR read delay center optimization
564 17:29:58.123807 INFO : End of write delay center optimization
565 17:29:58.128937 INFO : End of read delay center optimization
566 17:29:58.134551 INFO : End of max read latency training
567 17:29:58.134983 INFO : Training has run successfully!
568 17:29:58.140185 1D training succeed
569 17:29:58.145976 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
570 17:29:58.193708 Check phy result
571 17:29:58.194156 INFO : End of initialization
572 17:29:58.216320 INFO : End of 2D read delay Voltage center optimization
573 17:29:58.236540 INFO : End of 2D read delay Voltage center optimization
574 17:29:58.288639 INFO : End of 2D write delay Voltage center optimization
575 17:29:58.338030 INFO : End of 2D write delay Voltage center optimization
576 17:29:58.343693 INFO : Training has run successfully!
577 17:29:58.344156
578 17:29:58.344405 channel==0
579 17:29:58.349175 RxClkDly_Margin_A0==88 ps 9
580 17:29:58.349619 TxDqDly_Margin_A0==98 ps 10
581 17:29:58.352449 RxClkDly_Margin_A1==88 ps 9
582 17:29:58.352860 TxDqDly_Margin_A1==98 ps 10
583 17:29:58.357978 TrainedVREFDQ_A0==74
584 17:29:58.358388 TrainedVREFDQ_A1==74
585 17:29:58.363668 VrefDac_Margin_A0==24
586 17:29:58.363959 DeviceVref_Margin_A0==40
587 17:29:58.364204 VrefDac_Margin_A1==25
588 17:29:58.369221 DeviceVref_Margin_A1==40
589 17:29:58.369507
590 17:29:58.369723
591 17:29:58.369933 channel==1
592 17:29:58.370137 RxClkDly_Margin_A0==98 ps 10
593 17:29:58.374899 TxDqDly_Margin_A0==98 ps 10
594 17:29:58.375239 RxClkDly_Margin_A1==98 ps 10
595 17:29:58.380264 TxDqDly_Margin_A1==88 ps 9
596 17:29:58.380508 TrainedVREFDQ_A0==77
597 17:29:58.380719 TrainedVREFDQ_A1==77
598 17:29:58.385951 VrefDac_Margin_A0==22
599 17:29:58.386181 DeviceVref_Margin_A0==37
600 17:29:58.391667 VrefDac_Margin_A1==22
601 17:29:58.391897 DeviceVref_Margin_A1==37
602 17:29:58.392132
603 17:29:58.397138 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
604 17:29:58.397374
605 17:29:58.425097 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
606 17:29:58.430881 2D training succeed
607 17:29:58.436223 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
608 17:29:58.436676 auto size-- 65535DDR cs0 size: 2048MB
609 17:29:58.441869 DDR cs1 size: 2048MB
610 17:29:58.442316 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
611 17:29:58.447500 cs0 DataBus test pass
612 17:29:58.447962 cs1 DataBus test pass
613 17:29:58.448411 cs0 AddrBus test pass
614 17:29:58.453238 cs1 AddrBus test pass
615 17:29:58.453704
616 17:29:58.454117 100bdlr_step_size ps== 420
617 17:29:58.454530 result report
618 17:29:58.458862 boot times 0Enable ddr reg access
619 17:29:58.466477 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
620 17:29:58.479958 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
621 17:29:59.053706 0.0;M3 CHK:0;cm4_sp_mode 0
622 17:29:59.054330 MVN_1=0x00000000
623 17:29:59.059115 MVN_2=0x00000000
624 17:29:59.064880 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
625 17:29:59.065372 OPS=0x10
626 17:29:59.065814 ring efuse init
627 17:29:59.066256 chipver efuse init
628 17:29:59.073108 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
629 17:29:59.073595 [0.018961 Inits done]
630 17:29:59.080632 secure task start!
631 17:29:59.081053 high task start!
632 17:29:59.081439 low task start!
633 17:29:59.081823 run into bl31
634 17:29:59.087304 NOTICE: BL31: v1.3(release):4fc40b1
635 17:29:59.095105 NOTICE: BL31: Built : 15:58:17, May 22 2019
636 17:29:59.095534 NOTICE: BL31: G12A normal boot!
637 17:29:59.120552 NOTICE: BL31: BL33 decompress pass
638 17:29:59.126150 ERROR: Error initializing runtime service opteed_fast
639 17:30:00.359132
640 17:30:00.359575
641 17:30:00.367492 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
642 17:30:00.367815
643 17:30:00.368062 Model: Libre Computer AML-A311D-CC Alta
644 17:30:00.575937 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
645 17:30:00.599264 DRAM: 2 GiB (effective 3.8 GiB)
646 17:30:00.742244 Core: 408 devices, 31 uclasses, devicetree: separate
647 17:30:00.748158 WDT: Not starting watchdog@f0d0
648 17:30:00.780391 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
649 17:30:00.793011 Loading Environment from FAT... Card did not respond to voltage select! : -110
650 17:30:00.796924 ** Bad device specification mmc 0 **
651 17:30:00.808163 Card did not respond to voltage select! : -110
652 17:30:00.815822 ** Bad device specification mmc 0 **
653 17:30:00.816300 Couldn't find partition mmc 0
654 17:30:00.824165 Card did not respond to voltage select! : -110
655 17:30:00.829660 ** Bad device specification mmc 0 **
656 17:30:00.830089 Couldn't find partition mmc 0
657 17:30:00.834713 Error: could not access storage.
658 17:30:01.177254 Net: eth0: ethernet@ff3f0000
659 17:30:01.177791 starting USB...
660 17:30:01.430222 Bus usb@ff500000: Register 3000140 NbrPorts 3
661 17:30:01.430833 Starting the controller
662 17:30:01.437120 USB XHCI 1.10
663 17:30:03.145614 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
664 17:30:03.146251 bl2_stage_init 0x01
665 17:30:03.146682 bl2_stage_init 0x81
666 17:30:03.151148 hw id: 0x0000 - pwm id 0x01
667 17:30:03.151599 bl2_stage_init 0xc1
668 17:30:03.152057 bl2_stage_init 0x02
669 17:30:03.152470
670 17:30:03.156721 L0:00000000
671 17:30:03.157162 L1:20000703
672 17:30:03.157573 L2:00008067
673 17:30:03.157973 L3:14000000
674 17:30:03.162349 B2:00402000
675 17:30:03.162795 B1:e0f83180
676 17:30:03.163200
677 17:30:03.163597 TE: 58167
678 17:30:03.164023
679 17:30:03.167927 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
680 17:30:03.168393
681 17:30:03.168800 Board ID = 1
682 17:30:03.173523 Set A53 clk to 24M
683 17:30:03.173958 Set A73 clk to 24M
684 17:30:03.174362 Set clk81 to 24M
685 17:30:03.179128 A53 clk: 1200 MHz
686 17:30:03.179560 A73 clk: 1200 MHz
687 17:30:03.179961 CLK81: 166.6M
688 17:30:03.180397 smccc: 00012abd
689 17:30:03.184714 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
690 17:30:03.190320 board id: 1
691 17:30:03.195248 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
692 17:30:03.206853 fw parse done
693 17:30:03.212800 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 17:30:03.255480 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
695 17:30:03.266360 PIEI prepare done
696 17:30:03.266809 fastboot data load
697 17:30:03.267218 fastboot data verify
698 17:30:03.272041 verify result: 266
699 17:30:03.277601 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
700 17:30:03.278034 LPDDR4 probe
701 17:30:03.278437 ddr clk to 1584MHz
702 17:30:03.285572 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
703 17:30:03.322876
704 17:30:03.323267 dmc_version 0001
705 17:30:03.328624 Check phy result
706 17:30:03.335420 INFO : End of CA training
707 17:30:03.335882 INFO : End of initialization
708 17:30:03.340992 INFO : Training has run successfully!
709 17:30:03.341322 Check phy result
710 17:30:03.346594 INFO : End of initialization
711 17:30:03.347088 INFO : End of read enable training
712 17:30:03.352227 INFO : End of fine write leveling
713 17:30:03.357788 INFO : End of Write leveling coarse delay
714 17:30:03.358089 INFO : Training has run successfully!
715 17:30:03.358304 Check phy result
716 17:30:03.363435 INFO : End of initialization
717 17:30:03.363831 INFO : End of read dq deskew training
718 17:30:03.368990 INFO : End of MPR read delay center optimization
719 17:30:03.374630 INFO : End of write delay center optimization
720 17:30:03.380187 INFO : End of read delay center optimization
721 17:30:03.380471 INFO : End of max read latency training
722 17:30:03.385745 INFO : Training has run successfully!
723 17:30:03.385988 1D training succeed
724 17:30:03.394973 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
725 17:30:03.442779 Check phy result
726 17:30:03.443313 INFO : End of initialization
727 17:30:03.464463 INFO : End of 2D read delay Voltage center optimization
728 17:30:03.484691 INFO : End of 2D read delay Voltage center optimization
729 17:30:03.536793 INFO : End of 2D write delay Voltage center optimization
730 17:30:03.586001 INFO : End of 2D write delay Voltage center optimization
731 17:30:03.591619 INFO : Training has run successfully!
732 17:30:03.592115
733 17:30:03.592542 channel==0
734 17:30:03.597198 RxClkDly_Margin_A0==88 ps 9
735 17:30:03.597645 TxDqDly_Margin_A0==98 ps 10
736 17:30:03.602832 RxClkDly_Margin_A1==88 ps 9
737 17:30:03.603279 TxDqDly_Margin_A1==98 ps 10
738 17:30:03.603689 TrainedVREFDQ_A0==74
739 17:30:03.608385 TrainedVREFDQ_A1==74
740 17:30:03.608839 VrefDac_Margin_A0==25
741 17:30:03.609243 DeviceVref_Margin_A0==40
742 17:30:03.613927 VrefDac_Margin_A1==25
743 17:30:03.614372 DeviceVref_Margin_A1==40
744 17:30:03.614772
745 17:30:03.615174
746 17:30:03.619571 channel==1
747 17:30:03.620042 RxClkDly_Margin_A0==98 ps 10
748 17:30:03.620451 TxDqDly_Margin_A0==98 ps 10
749 17:30:03.625162 RxClkDly_Margin_A1==88 ps 9
750 17:30:03.625618 TxDqDly_Margin_A1==88 ps 9
751 17:30:03.630749 TrainedVREFDQ_A0==77
752 17:30:03.631197 TrainedVREFDQ_A1==77
753 17:30:03.631604 VrefDac_Margin_A0==22
754 17:30:03.636388 DeviceVref_Margin_A0==37
755 17:30:03.636824 VrefDac_Margin_A1==24
756 17:30:03.641944 DeviceVref_Margin_A1==37
757 17:30:03.642384
758 17:30:03.642788 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
759 17:30:03.643189
760 17:30:03.675533 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000016 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
761 17:30:03.676077 2D training succeed
762 17:30:03.681129 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
763 17:30:03.686788 auto size-- 65535DDR cs0 size: 2048MB
764 17:30:03.687231 DDR cs1 size: 2048MB
765 17:30:03.692351 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
766 17:30:03.692795 cs0 DataBus test pass
767 17:30:03.697934 cs1 DataBus test pass
768 17:30:03.698383 cs0 AddrBus test pass
769 17:30:03.698788 cs1 AddrBus test pass
770 17:30:03.699190
771 17:30:03.703540 100bdlr_step_size ps== 420
772 17:30:03.704035 result report
773 17:30:03.709127 boot times 0Enable ddr reg access
774 17:30:03.714597 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
775 17:30:03.728016 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
776 17:30:04.301570 0.0;M3 CHK:0;cm4_sp_mode 0
777 17:30:04.301983 MVN_1=0x00000000
778 17:30:04.308345 MVN_2=0x00000000
779 17:30:04.313027 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
780 17:30:04.313584 OPS=0x10
781 17:30:04.314062 ring efuse init
782 17:30:04.314526 chipver efuse init
783 17:30:04.321203 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
784 17:30:04.321792 [0.018960 Inits done]
785 17:30:04.328798 secure task start!
786 17:30:04.329345 high task start!
787 17:30:04.329788 low task start!
788 17:30:04.330219 run into bl31
789 17:30:04.335455 NOTICE: BL31: v1.3(release):4fc40b1
790 17:30:04.343218 NOTICE: BL31: Built : 15:58:17, May 22 2019
791 17:30:04.343566 NOTICE: BL31: G12A normal boot!
792 17:30:04.368529 NOTICE: BL31: BL33 decompress pass
793 17:30:04.374171 ERROR: Error initializing runtime service opteed_fast
794 17:30:05.606959
795 17:30:05.607639
796 17:30:05.614822 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
797 17:30:05.615346
798 17:30:05.615817 Model: Libre Computer AML-A311D-CC Alta
799 17:30:05.823734 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
800 17:30:05.847150 DRAM: 2 GiB (effective 3.8 GiB)
801 17:30:05.990149 Core: 408 devices, 31 uclasses, devicetree: separate
802 17:30:05.995936 WDT: Not starting watchdog@f0d0
803 17:30:06.028247 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
804 17:30:06.040750 Loading Environment from FAT... Card did not respond to voltage select! : -110
805 17:30:06.045633 ** Bad device specification mmc 0 **
806 17:30:06.056016 Card did not respond to voltage select! : -110
807 17:30:06.063628 ** Bad device specification mmc 0 **
808 17:30:06.064161 Couldn't find partition mmc 0
809 17:30:06.071966 Card did not respond to voltage select! : -110
810 17:30:06.077517 ** Bad device specification mmc 0 **
811 17:30:06.078008 Couldn't find partition mmc 0
812 17:30:06.082587 Error: could not access storage.
813 17:30:06.425032 Net: eth0: ethernet@ff3f0000
814 17:30:06.425454 starting USB...
815 17:30:06.677000 Bus usb@ff500000: Register 3000140 NbrPorts 3
816 17:30:06.677686 Starting the controller
817 17:30:06.684037 USB XHCI 1.10
818 17:30:08.845667 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
819 17:30:08.846342 bl2_stage_init 0x01
820 17:30:08.846854 bl2_stage_init 0x81
821 17:30:08.851383 hw id: 0x0000 - pwm id 0x01
822 17:30:08.851913 bl2_stage_init 0xc1
823 17:30:08.852431 bl2_stage_init 0x02
824 17:30:08.852883
825 17:30:08.856939 L0:00000000
826 17:30:08.857467 L1:20000703
827 17:30:08.857963 L2:00008067
828 17:30:08.858409 L3:14000000
829 17:30:08.862317 B2:00402000
830 17:30:08.862839 B1:e0f83180
831 17:30:08.863298
832 17:30:08.863742 TE: 58167
833 17:30:08.864233
834 17:30:08.868329 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
835 17:30:08.868876
836 17:30:08.869338 Board ID = 1
837 17:30:08.873571 Set A53 clk to 24M
838 17:30:08.874101 Set A73 clk to 24M
839 17:30:08.874573 Set clk81 to 24M
840 17:30:08.879290 A53 clk: 1200 MHz
841 17:30:08.879818 A73 clk: 1200 MHz
842 17:30:08.880319 CLK81: 166.6M
843 17:30:08.880769 smccc: 00012abe
844 17:30:08.884744 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
845 17:30:08.890324 board id: 1
846 17:30:08.896334 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
847 17:30:08.906971 fw parse done
848 17:30:08.912875 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 17:30:08.955506 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
850 17:30:08.966357 PIEI prepare done
851 17:30:08.966923 fastboot data load
852 17:30:08.967383 fastboot data verify
853 17:30:08.972063 verify result: 266
854 17:30:08.977612 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
855 17:30:08.978141 LPDDR4 probe
856 17:30:08.978594 ddr clk to 1584MHz
857 17:30:08.985573 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
858 17:30:09.022876
859 17:30:09.023505 dmc_version 0001
860 17:30:09.029522 Check phy result
861 17:30:09.035375 INFO : End of CA training
862 17:30:09.035893 INFO : End of initialization
863 17:30:09.040943 INFO : Training has run successfully!
864 17:30:09.041486 Check phy result
865 17:30:09.046537 INFO : End of initialization
866 17:30:09.047060 INFO : End of read enable training
867 17:30:09.049828 INFO : End of fine write leveling
868 17:30:09.055431 INFO : End of Write leveling coarse delay
869 17:30:09.061083 INFO : Training has run successfully!
870 17:30:09.061619 Check phy result
871 17:30:09.062078 INFO : End of initialization
872 17:30:09.066571 INFO : End of read dq deskew training
873 17:30:09.072350 INFO : End of MPR read delay center optimization
874 17:30:09.072872 INFO : End of write delay center optimization
875 17:30:09.077824 INFO : End of read delay center optimization
876 17:30:09.083436 INFO : End of max read latency training
877 17:30:09.083968 INFO : Training has run successfully!
878 17:30:09.089020 1D training succeed
879 17:30:09.094980 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
880 17:30:09.142571 Check phy result
881 17:30:09.143174 INFO : End of initialization
882 17:30:09.164298 INFO : End of 2D read delay Voltage center optimization
883 17:30:09.184470 INFO : End of 2D read delay Voltage center optimization
884 17:30:09.235473 INFO : End of 2D write delay Voltage center optimization
885 17:30:09.285460 INFO : End of 2D write delay Voltage center optimization
886 17:30:09.291311 INFO : Training has run successfully!
887 17:30:09.291803
888 17:30:09.292292 channel==0
889 17:30:09.296725 RxClkDly_Margin_A0==88 ps 9
890 17:30:09.297237 TxDqDly_Margin_A0==98 ps 10
891 17:30:09.302213 RxClkDly_Margin_A1==88 ps 9
892 17:30:09.302688 TxDqDly_Margin_A1==98 ps 10
893 17:30:09.303141 TrainedVREFDQ_A0==74
894 17:30:09.307854 TrainedVREFDQ_A1==74
895 17:30:09.308426 VrefDac_Margin_A0==25
896 17:30:09.308893 DeviceVref_Margin_A0==40
897 17:30:09.313453 VrefDac_Margin_A1==25
898 17:30:09.313982 DeviceVref_Margin_A1==40
899 17:30:09.314435
900 17:30:09.314876
901 17:30:09.318978 channel==1
902 17:30:09.319522 RxClkDly_Margin_A0==98 ps 10
903 17:30:09.319974 TxDqDly_Margin_A0==98 ps 10
904 17:30:09.324593 RxClkDly_Margin_A1==98 ps 10
905 17:30:09.325146 TxDqDly_Margin_A1==88 ps 9
906 17:30:09.330334 TrainedVREFDQ_A0==77
907 17:30:09.330810 TrainedVREFDQ_A1==77
908 17:30:09.331240 VrefDac_Margin_A0==22
909 17:30:09.335726 DeviceVref_Margin_A0==37
910 17:30:09.336237 VrefDac_Margin_A1==22
911 17:30:09.341436 DeviceVref_Margin_A1==37
912 17:30:09.341931
913 17:30:09.342369 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
914 17:30:09.347079
915 17:30:09.375089 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000016 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
916 17:30:09.375654 2D training succeed
917 17:30:09.380674 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
918 17:30:09.386084 auto size-- 65535DDR cs0 size: 2048MB
919 17:30:09.386565 DDR cs1 size: 2048MB
920 17:30:09.391679 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
921 17:30:09.392188 cs0 DataBus test pass
922 17:30:09.397363 cs1 DataBus test pass
923 17:30:09.397905 cs0 AddrBus test pass
924 17:30:09.398354 cs1 AddrBus test pass
925 17:30:09.398790
926 17:30:09.402943 100bdlr_step_size ps== 420
927 17:30:09.403504 result report
928 17:30:09.408549 boot times 0Enable ddr reg access
929 17:30:09.413107 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
930 17:30:09.427376 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
931 17:30:09.999404 0.0;M3 CHK:0;cm4_sp_mode 0
932 17:30:10.000145 MVN_1=0x00000000
933 17:30:10.004997 MVN_2=0x00000000
934 17:30:10.010711 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
935 17:30:10.011318 OPS=0x10
936 17:30:10.011830 ring efuse init
937 17:30:10.012372 chipver efuse init
938 17:30:10.018932 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
939 17:30:10.019585 [0.018961 Inits done]
940 17:30:10.026483 secure task start!
941 17:30:10.027094 high task start!
942 17:30:10.027584 low task start!
943 17:30:10.028100 run into bl31
944 17:30:10.033122 NOTICE: BL31: v1.3(release):4fc40b1
945 17:30:10.040952 NOTICE: BL31: Built : 15:58:17, May 22 2019
946 17:30:10.041533 NOTICE: BL31: G12A normal boot!
947 17:30:10.066353 NOTICE: BL31: BL33 decompress pass
948 17:30:10.071870 ERROR: Error initializing runtime service opteed_fast
949 17:30:11.304788
950 17:30:11.305460
951 17:30:11.313160 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
952 17:30:11.313672
953 17:30:11.314128 Model: Libre Computer AML-A311D-CC Alta
954 17:30:11.521656 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
955 17:30:11.544983 DRAM: 2 GiB (effective 3.8 GiB)
956 17:30:11.687920 Core: 408 devices, 31 uclasses, devicetree: separate
957 17:30:11.693769 WDT: Not starting watchdog@f0d0
958 17:30:11.726046 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
959 17:30:11.738517 Loading Environment from FAT... Card did not respond to voltage select! : -110
960 17:30:11.743514 ** Bad device specification mmc 0 **
961 17:30:11.753823 Card did not respond to voltage select! : -110
962 17:30:11.761529 ** Bad device specification mmc 0 **
963 17:30:11.762034 Couldn't find partition mmc 0
964 17:30:11.769842 Card did not respond to voltage select! : -110
965 17:30:11.776847 ** Bad device specification mmc 0 **
966 17:30:11.777516 Couldn't find partition mmc 0
967 17:30:11.780458 Error: could not access storage.
968 17:30:12.123112 Net: eth0: ethernet@ff3f0000
969 17:30:12.123774 starting USB...
970 17:30:12.374906 Bus usb@ff500000: Register 3000140 NbrPorts 3
971 17:30:12.375344 Starting the controller
972 17:30:12.381712 USB XHCI 1.10
973 17:30:14.245213 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
974 17:30:14.245816 bl2_stage_init 0x01
975 17:30:14.246244 bl2_stage_init 0x81
976 17:30:14.250798 hw id: 0x0000 - pwm id 0x01
977 17:30:14.251241 bl2_stage_init 0xc1
978 17:30:14.251648 bl2_stage_init 0x02
979 17:30:14.252107
980 17:30:14.256291 L0:00000000
981 17:30:14.256731 L1:20000703
982 17:30:14.257134 L2:00008067
983 17:30:14.257530 L3:14000000
984 17:30:14.259228 B2:00402000
985 17:30:14.259652 B1:e0f83180
986 17:30:14.260083
987 17:30:14.260488 TE: 58124
988 17:30:14.260886
989 17:30:14.270426 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
990 17:30:14.270873
991 17:30:14.271277 Board ID = 1
992 17:30:14.271671 Set A53 clk to 24M
993 17:30:14.272091 Set A73 clk to 24M
994 17:30:14.276006 Set clk81 to 24M
995 17:30:14.276435 A53 clk: 1200 MHz
996 17:30:14.276832 A73 clk: 1200 MHz
997 17:30:14.281629 CLK81: 166.6M
998 17:30:14.282059 smccc: 00012a92
999 17:30:14.287207 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1000 17:30:14.287636 board id: 1
1001 17:30:14.295895 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1002 17:30:14.306459 fw parse done
1003 17:30:14.312465 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1004 17:30:14.355109 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1005 17:30:14.365949 PIEI prepare done
1006 17:30:14.366491 fastboot data load
1007 17:30:14.366898 fastboot data verify
1008 17:30:14.371586 verify result: 266
1009 17:30:14.377204 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1010 17:30:14.377726 LPDDR4 probe
1011 17:30:14.378125 ddr clk to 1584MHz
1012 17:30:14.385402 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1013 17:30:14.422632
1014 17:30:14.423196 dmc_version 0001
1015 17:30:14.429338 Check phy result
1016 17:30:14.435262 INFO : End of CA training
1017 17:30:14.435702 INFO : End of initialization
1018 17:30:14.440871 INFO : Training has run successfully!
1019 17:30:14.441313 Check phy result
1020 17:30:14.446311 INFO : End of initialization
1021 17:30:14.446775 INFO : End of read enable training
1022 17:30:14.452013 INFO : End of fine write leveling
1023 17:30:14.457570 INFO : End of Write leveling coarse delay
1024 17:30:14.458030 INFO : Training has run successfully!
1025 17:30:14.458442 Check phy result
1026 17:30:14.463340 INFO : End of initialization
1027 17:30:14.463796 INFO : End of read dq deskew training
1028 17:30:14.468819 INFO : End of MPR read delay center optimization
1029 17:30:14.474361 INFO : End of write delay center optimization
1030 17:30:14.480018 INFO : End of read delay center optimization
1031 17:30:14.480474 INFO : End of max read latency training
1032 17:30:14.485440 INFO : Training has run successfully!
1033 17:30:14.485890 1D training succeed
1034 17:30:14.494687 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1035 17:30:14.542296 Check phy result
1036 17:30:14.542773 INFO : End of initialization
1037 17:30:14.564739 INFO : End of 2D read delay Voltage center optimization
1038 17:30:14.584082 INFO : End of 2D read delay Voltage center optimization
1039 17:30:14.636837 INFO : End of 2D write delay Voltage center optimization
1040 17:30:14.686197 INFO : End of 2D write delay Voltage center optimization
1041 17:30:14.691614 INFO : Training has run successfully!
1042 17:30:14.692099
1043 17:30:14.692518 channel==0
1044 17:30:14.697140 RxClkDly_Margin_A0==88 ps 9
1045 17:30:14.697583 TxDqDly_Margin_A0==98 ps 10
1046 17:30:14.702839 RxClkDly_Margin_A1==88 ps 9
1047 17:30:14.703280 TxDqDly_Margin_A1==98 ps 10
1048 17:30:14.703689 TrainedVREFDQ_A0==74
1049 17:30:14.708388 TrainedVREFDQ_A1==74
1050 17:30:14.708836 VrefDac_Margin_A0==25
1051 17:30:14.709242 DeviceVref_Margin_A0==40
1052 17:30:14.714182 VrefDac_Margin_A1==24
1053 17:30:14.714622 DeviceVref_Margin_A1==40
1054 17:30:14.715026
1055 17:30:14.715426
1056 17:30:14.719636 channel==1
1057 17:30:14.720104 RxClkDly_Margin_A0==98 ps 10
1058 17:30:14.720517 TxDqDly_Margin_A0==98 ps 10
1059 17:30:14.725122 RxClkDly_Margin_A1==88 ps 9
1060 17:30:14.725565 TxDqDly_Margin_A1==88 ps 9
1061 17:30:14.730913 TrainedVREFDQ_A0==77
1062 17:30:14.731366 TrainedVREFDQ_A1==77
1063 17:30:14.731768 VrefDac_Margin_A0==22
1064 17:30:14.736337 DeviceVref_Margin_A0==37
1065 17:30:14.736773 VrefDac_Margin_A1==24
1066 17:30:14.742074 DeviceVref_Margin_A1==37
1067 17:30:14.742521
1068 17:30:14.742928 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1069 17:30:14.743330
1070 17:30:14.775512 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000018 00000017 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
1071 17:30:14.776040 2D training succeed
1072 17:30:14.781122 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1073 17:30:14.786611 auto size-- 65535DDR cs0 size: 2048MB
1074 17:30:14.787063 DDR cs1 size: 2048MB
1075 17:30:14.792202 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1076 17:30:14.792665 cs0 DataBus test pass
1077 17:30:14.797929 cs1 DataBus test pass
1078 17:30:14.798384 cs0 AddrBus test pass
1079 17:30:14.798786 cs1 AddrBus test pass
1080 17:30:14.799183
1081 17:30:14.803400 100bdlr_step_size ps== 420
1082 17:30:14.803856 result report
1083 17:30:14.809059 boot times 0Enable ddr reg access
1084 17:30:14.814444 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1085 17:30:14.827908 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1086 17:30:15.400044 0.0;M3 CHK:0;cm4_sp_mode 0
1087 17:30:15.400691 MVN_1=0x00000000
1088 17:30:15.405347 MVN_2=0x00000000
1089 17:30:15.411104 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1090 17:30:15.411623 OPS=0x10
1091 17:30:15.412083 ring efuse init
1092 17:30:15.412535 chipver efuse init
1093 17:30:15.416715 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1094 17:30:15.422364 [0.018961 Inits done]
1095 17:30:15.422879 secure task start!
1096 17:30:15.423305 high task start!
1097 17:30:15.426968 low task start!
1098 17:30:15.427467 run into bl31
1099 17:30:15.433547 NOTICE: BL31: v1.3(release):4fc40b1
1100 17:30:15.441362 NOTICE: BL31: Built : 15:58:17, May 22 2019
1101 17:30:15.441888 NOTICE: BL31: G12A normal boot!
1102 17:30:15.467202 NOTICE: BL31: BL33 decompress pass
1103 17:30:15.472875 ERROR: Error initializing runtime service opteed_fast
1104 17:30:16.705740
1105 17:30:16.706347
1106 17:30:16.714234 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1107 17:30:16.714701
1108 17:30:16.715112 Model: Libre Computer AML-A311D-CC Alta
1109 17:30:16.922600 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1110 17:30:16.945970 DRAM: 2 GiB (effective 3.8 GiB)
1111 17:30:17.088991 Core: 408 devices, 31 uclasses, devicetree: separate
1112 17:30:17.094896 WDT: Not starting watchdog@f0d0
1113 17:30:17.127087 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1114 17:30:17.139534 Loading Environment from FAT... Card did not respond to voltage select! : -110
1115 17:30:17.144514 ** Bad device specification mmc 0 **
1116 17:30:17.154900 Card did not respond to voltage select! : -110
1117 17:30:17.162524 ** Bad device specification mmc 0 **
1118 17:30:17.163019 Couldn't find partition mmc 0
1119 17:30:17.170852 Card did not respond to voltage select! : -110
1120 17:30:17.176386 ** Bad device specification mmc 0 **
1121 17:30:17.176845 Couldn't find partition mmc 0
1122 17:30:17.181405 Error: could not access storage.
1123 17:30:17.524987 Net: eth0: ethernet@ff3f0000
1124 17:30:17.525619 starting USB...
1125 17:30:17.776769 Bus usb@ff500000: Register 3000140 NbrPorts 3
1126 17:30:17.777400 Starting the controller
1127 17:30:17.783803 USB XHCI 1.10
1128 17:30:19.340939 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1129 17:30:19.349264 scanning usb for storage devices... 0 Storage Device(s) found
1131 17:30:19.400931 Hit any key to stop autoboot: 1
1132 17:30:19.401852 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1133 17:30:19.402420 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1134 17:30:19.402876 Setting prompt string to ['=>']
1135 17:30:19.403349 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1136 17:30:19.416551 0
1137 17:30:19.417398 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1138 17:30:19.417871 Sending with 10 millisecond of delay
1140 17:30:20.552514 => setenv autoload no
1141 17:30:20.563244 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1142 17:30:20.565844 setenv autoload no
1143 17:30:20.566347 Sending with 10 millisecond of delay
1145 17:30:22.363777 => setenv initrd_high 0xffffffff
1146 17:30:22.374606 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1147 17:30:22.375474 setenv initrd_high 0xffffffff
1148 17:30:22.376194 Sending with 10 millisecond of delay
1150 17:30:23.994266 => setenv fdt_high 0xffffffff
1151 17:30:24.005083 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1152 17:30:24.006036 setenv fdt_high 0xffffffff
1153 17:30:24.006803 Sending with 10 millisecond of delay
1155 17:30:24.298914 => dhcp
1156 17:30:24.309739 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1157 17:30:24.310385 dhcp
1158 17:30:24.310661 Speed: 1000, full duplex
1159 17:30:24.310883 BOOTP broadcast 1
1160 17:30:24.317987 DHCP client bound to address 192.168.6.27 (8 ms)
1161 17:30:24.318715 Sending with 10 millisecond of delay
1163 17:30:25.995525 => setenv serverip 192.168.6.2
1164 17:30:26.006453 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1165 17:30:26.007507 setenv serverip 192.168.6.2
1166 17:30:26.008294 Sending with 10 millisecond of delay
1168 17:30:29.733296 => tftpboot 0x01080000 975787/tftp-deploy-9lpck33t/kernel/uImage
1169 17:30:29.744102 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1170 17:30:29.744960 tftpboot 0x01080000 975787/tftp-deploy-9lpck33t/kernel/uImage
1171 17:30:29.745402 Speed: 1000, full duplex
1172 17:30:29.745811 Using ethernet@ff3f0000 device
1173 17:30:29.746694 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1174 17:30:29.752299 Filename '975787/tftp-deploy-9lpck33t/kernel/uImage'.
1175 17:30:29.756364 Load address: 0x1080000
1176 17:30:30.011176 Loading: *#### UDP wrong checksum 000000ff 00003151
1177 17:30:30.061936 UDP wrong checksum 000000ff 0000bc43
1178 17:30:32.653668 ############################################## 43.6 MiB
1179 17:30:32.654306 15 MiB/s
1180 17:30:32.654784 done
1181 17:30:32.658176 Bytes transferred = 45713984 (2b98a40 hex)
1182 17:30:32.659050 Sending with 10 millisecond of delay
1184 17:30:37.348543 => tftpboot 0x08000000 975787/tftp-deploy-9lpck33t/ramdisk/ramdisk.cpio.gz.uboot
1185 17:30:37.359418 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1186 17:30:37.360395 tftpboot 0x08000000 975787/tftp-deploy-9lpck33t/ramdisk/ramdisk.cpio.gz.uboot
1187 17:30:37.360893 Speed: 1000, full duplex
1188 17:30:37.361345 Using ethernet@ff3f0000 device
1189 17:30:37.362318 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1190 17:30:37.374032 Filename '975787/tftp-deploy-9lpck33t/ramdisk/ramdisk.cpio.gz.uboot'.
1191 17:30:37.374641 Load address: 0x8000000
1192 17:30:43.941294 Loading: *#################T ################################ UDP wrong checksum 00000005 00003ebb
1193 17:30:47.674397 UDP wrong checksum 000000ff 000026ea
1194 17:30:47.691700 UDP wrong checksum 000000ff 0000bcdc
1195 17:30:48.941957 T UDP wrong checksum 00000005 00003ebb
1196 17:30:58.943889 T T UDP wrong checksum 00000005 00003ebb
1197 17:31:03.039345 UDP wrong checksum 000000ff 00003d84
1198 17:31:03.049878 UDP wrong checksum 000000ff 0000d476
1199 17:31:03.444786 UDP wrong checksum 000000ff 00001eed
1200 17:31:03.457770 UDP wrong checksum 000000ff 0000a7df
1201 17:31:18.946943 T T T T UDP wrong checksum 00000005 00003ebb
1202 17:31:33.951190 T T
1203 17:31:33.951875 Retry count exceeded; starting again
1205 17:31:33.953470 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1208 17:31:33.955408 end: 2.4 uboot-commands (duration 00:01:51) [common]
1210 17:31:33.956934 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1212 17:31:33.958020 end: 2 uboot-action (duration 00:01:51) [common]
1214 17:31:33.959657 Cleaning after the job
1215 17:31:33.960294 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975787/tftp-deploy-9lpck33t/ramdisk
1216 17:31:33.961823 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975787/tftp-deploy-9lpck33t/kernel
1217 17:31:34.009746 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975787/tftp-deploy-9lpck33t/dtb
1218 17:31:34.010588 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975787/tftp-deploy-9lpck33t/nfsrootfs
1219 17:31:34.036377 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975787/tftp-deploy-9lpck33t/modules
1220 17:31:34.039764 start: 4.1 power-off (timeout 00:00:30) [common]
1221 17:31:34.040348 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1222 17:31:34.074633 >> OK - accepted request
1223 17:31:34.076912 Returned 0 in 0 seconds
1224 17:31:34.177867 end: 4.1 power-off (duration 00:00:00) [common]
1226 17:31:34.179624 start: 4.2 read-feedback (timeout 00:10:00) [common]
1227 17:31:34.180834 Listened to connection for namespace 'common' for up to 1s
1228 17:31:35.181671 Finalising connection for namespace 'common'
1229 17:31:35.182479 Disconnecting from shell: Finalise
1230 17:31:35.183032 =>
1231 17:31:35.284139 end: 4.2 read-feedback (duration 00:00:01) [common]
1232 17:31:35.284763 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/975787
1233 17:31:38.091598 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/975787
1234 17:31:38.092237 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.