Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 17:07:41.244902 lava-dispatcher, installed at version: 2024.01
2 17:07:41.245664 start: 0 validate
3 17:07:41.246149 Start time: 2024-11-11 17:07:41.246120+00:00 (UTC)
4 17:07:41.246690 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 17:07:41.247230 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 17:07:41.289681 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 17:07:41.290247 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fmaster%2Frenesas-devel-2024-11-11-v6.12-rc7%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 17:07:41.319296 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 17:07:41.319933 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fmaster%2Frenesas-devel-2024-11-11-v6.12-rc7%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 17:07:41.354051 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 17:07:41.354553 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 17:07:41.386883 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 17:07:41.387375 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fmaster%2Frenesas-devel-2024-11-11-v6.12-rc7%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 17:07:41.424626 validate duration: 0.18
16 17:07:41.425434 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 17:07:41.425742 start: 1.1 download-retry (timeout 00:10:00) [common]
18 17:07:41.426042 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 17:07:41.426595 Not decompressing ramdisk as can be used compressed.
20 17:07:41.427024 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 17:07:41.427293 saving as /var/lib/lava/dispatcher/tmp/975707/tftp-deploy-xie32id1/ramdisk/initrd.cpio.gz
22 17:07:41.427558 total size: 5628169 (5 MB)
23 17:07:41.464336 progress 0 % (0 MB)
24 17:07:41.472118 progress 5 % (0 MB)
25 17:07:41.480251 progress 10 % (0 MB)
26 17:07:41.487464 progress 15 % (0 MB)
27 17:07:41.491888 progress 20 % (1 MB)
28 17:07:41.495640 progress 25 % (1 MB)
29 17:07:41.499763 progress 30 % (1 MB)
30 17:07:41.504123 progress 35 % (1 MB)
31 17:07:41.507839 progress 40 % (2 MB)
32 17:07:41.512070 progress 45 % (2 MB)
33 17:07:41.515823 progress 50 % (2 MB)
34 17:07:41.520054 progress 55 % (2 MB)
35 17:07:41.524188 progress 60 % (3 MB)
36 17:07:41.527916 progress 65 % (3 MB)
37 17:07:41.532108 progress 70 % (3 MB)
38 17:07:41.535870 progress 75 % (4 MB)
39 17:07:41.539856 progress 80 % (4 MB)
40 17:07:41.543537 progress 85 % (4 MB)
41 17:07:41.547620 progress 90 % (4 MB)
42 17:07:41.551510 progress 95 % (5 MB)
43 17:07:41.554818 progress 100 % (5 MB)
44 17:07:41.555462 5 MB downloaded in 0.13 s (41.97 MB/s)
45 17:07:41.556009 end: 1.1.1 http-download (duration 00:00:00) [common]
47 17:07:41.556920 end: 1.1 download-retry (duration 00:00:00) [common]
48 17:07:41.557213 start: 1.2 download-retry (timeout 00:10:00) [common]
49 17:07:41.557483 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 17:07:41.557950 downloading http://storage.kernelci.org/renesas/master/renesas-devel-2024-11-11-v6.12-rc7/arm64/defconfig/gcc-12/kernel/Image
51 17:07:41.558196 saving as /var/lib/lava/dispatcher/tmp/975707/tftp-deploy-xie32id1/kernel/Image
52 17:07:41.558406 total size: 45713920 (43 MB)
53 17:07:41.558616 No compression specified
54 17:07:41.592842 progress 0 % (0 MB)
55 17:07:41.621495 progress 5 % (2 MB)
56 17:07:41.650431 progress 10 % (4 MB)
57 17:07:41.678667 progress 15 % (6 MB)
58 17:07:41.707486 progress 20 % (8 MB)
59 17:07:41.735295 progress 25 % (10 MB)
60 17:07:41.763419 progress 30 % (13 MB)
61 17:07:41.791675 progress 35 % (15 MB)
62 17:07:41.820118 progress 40 % (17 MB)
63 17:07:41.847885 progress 45 % (19 MB)
64 17:07:41.875780 progress 50 % (21 MB)
65 17:07:41.905417 progress 55 % (24 MB)
66 17:07:41.933984 progress 60 % (26 MB)
67 17:07:41.961754 progress 65 % (28 MB)
68 17:07:41.989875 progress 70 % (30 MB)
69 17:07:42.018435 progress 75 % (32 MB)
70 17:07:42.046505 progress 80 % (34 MB)
71 17:07:42.074282 progress 85 % (37 MB)
72 17:07:42.102003 progress 90 % (39 MB)
73 17:07:42.129997 progress 95 % (41 MB)
74 17:07:42.157693 progress 100 % (43 MB)
75 17:07:42.158183 43 MB downloaded in 0.60 s (72.69 MB/s)
76 17:07:42.158650 end: 1.2.1 http-download (duration 00:00:01) [common]
78 17:07:42.159461 end: 1.2 download-retry (duration 00:00:01) [common]
79 17:07:42.159732 start: 1.3 download-retry (timeout 00:09:59) [common]
80 17:07:42.160023 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 17:07:42.160606 downloading http://storage.kernelci.org/renesas/master/renesas-devel-2024-11-11-v6.12-rc7/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 17:07:42.160891 saving as /var/lib/lava/dispatcher/tmp/975707/tftp-deploy-xie32id1/dtb/meson-g12b-a311d-libretech-cc.dtb
83 17:07:42.161102 total size: 54703 (0 MB)
84 17:07:42.161311 No compression specified
85 17:07:42.202361 progress 59 % (0 MB)
86 17:07:42.203199 progress 100 % (0 MB)
87 17:07:42.203749 0 MB downloaded in 0.04 s (1.22 MB/s)
88 17:07:42.204271 end: 1.3.1 http-download (duration 00:00:00) [common]
90 17:07:42.205095 end: 1.3 download-retry (duration 00:00:00) [common]
91 17:07:42.205359 start: 1.4 download-retry (timeout 00:09:59) [common]
92 17:07:42.205623 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 17:07:42.206066 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 17:07:42.206306 saving as /var/lib/lava/dispatcher/tmp/975707/tftp-deploy-xie32id1/nfsrootfs/full.rootfs.tar
95 17:07:42.206510 total size: 120894716 (115 MB)
96 17:07:42.206721 Using unxz to decompress xz
97 17:07:42.241469 progress 0 % (0 MB)
98 17:07:43.042362 progress 5 % (5 MB)
99 17:07:43.879680 progress 10 % (11 MB)
100 17:07:44.674679 progress 15 % (17 MB)
101 17:07:45.409408 progress 20 % (23 MB)
102 17:07:46.003387 progress 25 % (28 MB)
103 17:07:46.833659 progress 30 % (34 MB)
104 17:07:47.630268 progress 35 % (40 MB)
105 17:07:47.978212 progress 40 % (46 MB)
106 17:07:48.350821 progress 45 % (51 MB)
107 17:07:49.080602 progress 50 % (57 MB)
108 17:07:49.977194 progress 55 % (63 MB)
109 17:07:50.762853 progress 60 % (69 MB)
110 17:07:51.526600 progress 65 % (74 MB)
111 17:07:52.303688 progress 70 % (80 MB)
112 17:07:53.128445 progress 75 % (86 MB)
113 17:07:53.931754 progress 80 % (92 MB)
114 17:07:54.691770 progress 85 % (98 MB)
115 17:07:55.542939 progress 90 % (103 MB)
116 17:07:56.313654 progress 95 % (109 MB)
117 17:07:57.146118 progress 100 % (115 MB)
118 17:07:57.159634 115 MB downloaded in 14.95 s (7.71 MB/s)
119 17:07:57.160394 end: 1.4.1 http-download (duration 00:00:15) [common]
121 17:07:57.162009 end: 1.4 download-retry (duration 00:00:15) [common]
122 17:07:57.162517 start: 1.5 download-retry (timeout 00:09:44) [common]
123 17:07:57.163024 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 17:07:57.163781 downloading http://storage.kernelci.org/renesas/master/renesas-devel-2024-11-11-v6.12-rc7/arm64/defconfig/gcc-12/modules.tar.xz
125 17:07:57.164269 saving as /var/lib/lava/dispatcher/tmp/975707/tftp-deploy-xie32id1/modules/modules.tar
126 17:07:57.164671 total size: 11621176 (11 MB)
127 17:07:57.165081 Using unxz to decompress xz
128 17:07:57.209029 progress 0 % (0 MB)
129 17:07:57.278175 progress 5 % (0 MB)
130 17:07:57.352224 progress 10 % (1 MB)
131 17:07:57.447502 progress 15 % (1 MB)
132 17:07:57.539011 progress 20 % (2 MB)
133 17:07:57.618234 progress 25 % (2 MB)
134 17:07:57.693862 progress 30 % (3 MB)
135 17:07:57.771947 progress 35 % (3 MB)
136 17:07:57.843824 progress 40 % (4 MB)
137 17:07:57.919470 progress 45 % (5 MB)
138 17:07:58.004082 progress 50 % (5 MB)
139 17:07:58.085395 progress 55 % (6 MB)
140 17:07:58.167124 progress 60 % (6 MB)
141 17:07:58.246494 progress 65 % (7 MB)
142 17:07:58.326232 progress 70 % (7 MB)
143 17:07:58.403516 progress 75 % (8 MB)
144 17:07:58.485930 progress 80 % (8 MB)
145 17:07:58.565237 progress 85 % (9 MB)
146 17:07:58.647337 progress 90 % (10 MB)
147 17:07:58.720072 progress 95 % (10 MB)
148 17:07:58.797485 progress 100 % (11 MB)
149 17:07:58.810457 11 MB downloaded in 1.65 s (6.73 MB/s)
150 17:07:58.811312 end: 1.5.1 http-download (duration 00:00:02) [common]
152 17:07:58.812939 end: 1.5 download-retry (duration 00:00:02) [common]
153 17:07:58.813457 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 17:07:58.813966 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 17:08:15.355871 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/975707/extract-nfsrootfs-0nb0opcb
156 17:08:15.356503 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 17:08:15.356793 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 17:08:15.357583 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7
159 17:08:15.358055 makedir: /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin
160 17:08:15.358381 makedir: /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/tests
161 17:08:15.358695 makedir: /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/results
162 17:08:15.359024 Creating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-add-keys
163 17:08:15.359550 Creating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-add-sources
164 17:08:15.360128 Creating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-background-process-start
165 17:08:15.360697 Creating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-background-process-stop
166 17:08:15.361234 Creating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-common-functions
167 17:08:15.361741 Creating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-echo-ipv4
168 17:08:15.362227 Creating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-install-packages
169 17:08:15.362702 Creating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-installed-packages
170 17:08:15.363171 Creating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-os-build
171 17:08:15.363642 Creating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-probe-channel
172 17:08:15.364191 Creating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-probe-ip
173 17:08:15.364717 Creating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-target-ip
174 17:08:15.365193 Creating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-target-mac
175 17:08:15.365663 Creating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-target-storage
176 17:08:15.366145 Creating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-test-case
177 17:08:15.366619 Creating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-test-event
178 17:08:15.367087 Creating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-test-feedback
179 17:08:15.367623 Creating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-test-raise
180 17:08:15.368164 Creating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-test-reference
181 17:08:15.368705 Creating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-test-runner
182 17:08:15.369196 Creating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-test-set
183 17:08:15.369674 Creating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-test-shell
184 17:08:15.370157 Updating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-add-keys (debian)
185 17:08:15.370684 Updating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-add-sources (debian)
186 17:08:15.371206 Updating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-install-packages (debian)
187 17:08:15.371708 Updating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-installed-packages (debian)
188 17:08:15.372237 Updating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/bin/lava-os-build (debian)
189 17:08:15.372689 Creating /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/environment
190 17:08:15.373068 LAVA metadata
191 17:08:15.373328 - LAVA_JOB_ID=975707
192 17:08:15.373542 - LAVA_DISPATCHER_IP=192.168.6.2
193 17:08:15.373911 start: 1.6.2.1 ssh-authorize (timeout 00:09:26) [common]
194 17:08:15.374880 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 17:08:15.375201 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:26) [common]
196 17:08:15.375407 skipped lava-vland-overlay
197 17:08:15.375646 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 17:08:15.375900 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:26) [common]
199 17:08:15.376162 skipped lava-multinode-overlay
200 17:08:15.376414 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 17:08:15.376668 start: 1.6.2.4 test-definition (timeout 00:09:26) [common]
202 17:08:15.376928 Loading test definitions
203 17:08:15.377217 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:26) [common]
204 17:08:15.377440 Using /lava-975707 at stage 0
205 17:08:15.378707 uuid=975707_1.6.2.4.1 testdef=None
206 17:08:15.379046 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 17:08:15.379316 start: 1.6.2.4.2 test-overlay (timeout 00:09:26) [common]
208 17:08:15.380986 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 17:08:15.381784 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:26) [common]
211 17:08:15.383719 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 17:08:15.384577 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:26) [common]
214 17:08:15.386405 runner path: /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/0/tests/0_timesync-off test_uuid 975707_1.6.2.4.1
215 17:08:15.386986 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 17:08:15.387799 start: 1.6.2.4.5 git-repo-action (timeout 00:09:26) [common]
218 17:08:15.388061 Using /lava-975707 at stage 0
219 17:08:15.388429 Fetching tests from https://github.com/kernelci/test-definitions.git
220 17:08:15.388717 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/0/tests/1_kselftest-rtc'
221 17:08:18.784474 Running '/usr/bin/git checkout kernelci.org
222 17:08:19.231439 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
223 17:08:19.232904 uuid=975707_1.6.2.4.5 testdef=None
224 17:08:19.233249 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 17:08:19.233990 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 17:08:19.236813 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 17:08:19.237624 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 17:08:19.241340 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 17:08:19.242190 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 17:08:19.245773 runner path: /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/0/tests/1_kselftest-rtc test_uuid 975707_1.6.2.4.5
234 17:08:19.246059 BOARD='meson-g12b-a311d-libretech-cc'
235 17:08:19.246262 BRANCH='renesas'
236 17:08:19.246458 SKIPFILE='/dev/null'
237 17:08:19.246655 SKIP_INSTALL='True'
238 17:08:19.246849 TESTPROG_URL='http://storage.kernelci.org/renesas/master/renesas-devel-2024-11-11-v6.12-rc7/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 17:08:19.247049 TST_CASENAME=''
240 17:08:19.247243 TST_CMDFILES='rtc'
241 17:08:19.247773 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 17:08:19.248582 Creating lava-test-runner.conf files
244 17:08:19.248787 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/975707/lava-overlay-tp153sr7/lava-975707/0 for stage 0
245 17:08:19.249140 - 0_timesync-off
246 17:08:19.249375 - 1_kselftest-rtc
247 17:08:19.249701 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 17:08:19.249979 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 17:08:42.549023 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 17:08:42.549492 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:59) [common]
251 17:08:42.549791 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 17:08:42.550102 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 17:08:42.550402 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:59) [common]
254 17:08:43.179772 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 17:08:43.180325 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 17:08:43.180594 extracting modules file /var/lib/lava/dispatcher/tmp/975707/tftp-deploy-xie32id1/modules/modules.tar to /var/lib/lava/dispatcher/tmp/975707/extract-nfsrootfs-0nb0opcb
257 17:08:44.546943 extracting modules file /var/lib/lava/dispatcher/tmp/975707/tftp-deploy-xie32id1/modules/modules.tar to /var/lib/lava/dispatcher/tmp/975707/extract-overlay-ramdisk-ektzptbf/ramdisk
258 17:08:45.937659 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 17:08:45.938140 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 17:08:45.938416 [common] Applying overlay to NFS
261 17:08:45.938632 [common] Applying overlay /var/lib/lava/dispatcher/tmp/975707/compress-overlay-19slvx_7/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/975707/extract-nfsrootfs-0nb0opcb
262 17:08:48.685883 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 17:08:48.686351 start: 1.6.6 prepare-kernel (timeout 00:08:53) [common]
264 17:08:48.686626 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:53) [common]
265 17:08:48.686859 Converting downloaded kernel to a uImage
266 17:08:48.687169 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/975707/tftp-deploy-xie32id1/kernel/Image /var/lib/lava/dispatcher/tmp/975707/tftp-deploy-xie32id1/kernel/uImage
267 17:08:49.187954 output: Image Name:
268 17:08:49.188403 output: Created: Mon Nov 11 17:08:48 2024
269 17:08:49.188643 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 17:08:49.188863 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 17:08:49.189074 output: Load Address: 01080000
272 17:08:49.189281 output: Entry Point: 01080000
273 17:08:49.189732 output:
274 17:08:49.190122 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 17:08:49.190411 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 17:08:49.190747 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
277 17:08:49.191059 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 17:08:49.191353 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
279 17:08:49.191652 Building ramdisk /var/lib/lava/dispatcher/tmp/975707/extract-overlay-ramdisk-ektzptbf/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/975707/extract-overlay-ramdisk-ektzptbf/ramdisk
280 17:08:51.586484 >> 166829 blocks
281 17:08:59.850515 Adding RAMdisk u-boot header.
282 17:08:59.850952 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/975707/extract-overlay-ramdisk-ektzptbf/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/975707/extract-overlay-ramdisk-ektzptbf/ramdisk.cpio.gz.uboot
283 17:09:00.090002 output: Image Name:
284 17:09:00.090442 output: Created: Mon Nov 11 17:08:59 2024
285 17:09:00.090671 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 17:09:00.090884 output: Data Size: 23436129 Bytes = 22886.84 KiB = 22.35 MiB
287 17:09:00.091093 output: Load Address: 00000000
288 17:09:00.091297 output: Entry Point: 00000000
289 17:09:00.091502 output:
290 17:09:00.092160 rename /var/lib/lava/dispatcher/tmp/975707/extract-overlay-ramdisk-ektzptbf/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/975707/tftp-deploy-xie32id1/ramdisk/ramdisk.cpio.gz.uboot
291 17:09:00.092621 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
292 17:09:00.092933 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 17:09:00.093228 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 17:09:00.093477 No LXC device requested
295 17:09:00.093743 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 17:09:00.094027 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 17:09:00.094300 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 17:09:00.094519 Checking files for TFTP limit of 4294967296 bytes.
299 17:09:00.096080 end: 1 tftp-deploy (duration 00:01:19) [common]
300 17:09:00.096439 start: 2 uboot-action (timeout 00:05:00) [common]
301 17:09:00.096727 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 17:09:00.097004 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 17:09:00.097289 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 17:09:00.097595 Using kernel file from prepare-kernel: 975707/tftp-deploy-xie32id1/kernel/uImage
305 17:09:00.097938 substitutions:
306 17:09:00.098154 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 17:09:00.098362 - {DTB_ADDR}: 0x01070000
308 17:09:00.098580 - {DTB}: 975707/tftp-deploy-xie32id1/dtb/meson-g12b-a311d-libretech-cc.dtb
309 17:09:00.098788 - {INITRD}: 975707/tftp-deploy-xie32id1/ramdisk/ramdisk.cpio.gz.uboot
310 17:09:00.098990 - {KERNEL_ADDR}: 0x01080000
311 17:09:00.099190 - {KERNEL}: 975707/tftp-deploy-xie32id1/kernel/uImage
312 17:09:00.099390 - {LAVA_MAC}: None
313 17:09:00.099625 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/975707/extract-nfsrootfs-0nb0opcb
314 17:09:00.099834 - {NFS_SERVER_IP}: 192.168.6.2
315 17:09:00.100317 - {PRESEED_CONFIG}: None
316 17:09:00.100648 - {PRESEED_LOCAL}: None
317 17:09:00.100967 - {RAMDISK_ADDR}: 0x08000000
318 17:09:00.101274 - {RAMDISK}: 975707/tftp-deploy-xie32id1/ramdisk/ramdisk.cpio.gz.uboot
319 17:09:00.101504 - {ROOT_PART}: None
320 17:09:00.101711 - {ROOT}: None
321 17:09:00.101912 - {SERVER_IP}: 192.168.6.2
322 17:09:00.102122 - {TEE_ADDR}: 0x83000000
323 17:09:00.102324 - {TEE}: None
324 17:09:00.102522 Parsed boot commands:
325 17:09:00.102717 - setenv autoload no
326 17:09:00.102915 - setenv initrd_high 0xffffffff
327 17:09:00.103122 - setenv fdt_high 0xffffffff
328 17:09:00.103323 - dhcp
329 17:09:00.103517 - setenv serverip 192.168.6.2
330 17:09:00.103719 - tftpboot 0x01080000 975707/tftp-deploy-xie32id1/kernel/uImage
331 17:09:00.104075 - tftpboot 0x08000000 975707/tftp-deploy-xie32id1/ramdisk/ramdisk.cpio.gz.uboot
332 17:09:00.104323 - tftpboot 0x01070000 975707/tftp-deploy-xie32id1/dtb/meson-g12b-a311d-libretech-cc.dtb
333 17:09:00.104531 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/975707/extract-nfsrootfs-0nb0opcb,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 17:09:00.104739 - bootm 0x01080000 0x08000000 0x01070000
335 17:09:00.105010 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 17:09:00.105799 start: 2.3 connect-device (timeout 00:05:00) [common]
338 17:09:00.106030 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 17:09:00.119743 Setting prompt string to ['lava-test: # ']
340 17:09:00.120753 end: 2.3 connect-device (duration 00:00:00) [common]
341 17:09:00.121121 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 17:09:00.121429 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 17:09:00.121755 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 17:09:00.122390 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 17:09:00.181522 >> OK - accepted request
346 17:09:00.183539 Returned 0 in 0 seconds
347 17:09:00.284714 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 17:09:00.286449 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 17:09:00.287025 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 17:09:00.287578 Setting prompt string to ['Hit any key to stop autoboot']
352 17:09:00.288144 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 17:09:00.289769 Trying 192.168.56.21...
354 17:09:00.290264 Connected to conserv1.
355 17:09:00.290684 Escape character is '^]'.
356 17:09:00.291129
357 17:09:00.291566 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 17:09:00.292019
359 17:09:11.677409 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 17:09:11.677841 bl2_stage_init 0x01
361 17:09:11.678078 bl2_stage_init 0x81
362 17:09:11.682931 hw id: 0x0000 - pwm id 0x01
363 17:09:11.683242 bl2_stage_init 0xc1
364 17:09:11.683474 bl2_stage_init 0x02
365 17:09:11.683690
366 17:09:11.688393 L0:00000000
367 17:09:11.688685 L1:20000703
368 17:09:11.688907 L2:00008067
369 17:09:11.689123 L3:14000000
370 17:09:11.694099 B2:00402000
371 17:09:11.694390 B1:e0f83180
372 17:09:11.694609
373 17:09:11.694816 TE: 58167
374 17:09:11.695020
375 17:09:11.699511 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 17:09:11.699796
377 17:09:11.700075 Board ID = 1
378 17:09:11.705141 Set A53 clk to 24M
379 17:09:11.705408 Set A73 clk to 24M
380 17:09:11.705615 Set clk81 to 24M
381 17:09:11.710779 A53 clk: 1200 MHz
382 17:09:11.711034 A73 clk: 1200 MHz
383 17:09:11.711239 CLK81: 166.6M
384 17:09:11.711438 smccc: 00012abe
385 17:09:11.716455 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 17:09:11.722077 board id: 1
387 17:09:11.727945 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 17:09:11.738329 fw parse done
389 17:09:11.744283 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 17:09:11.786945 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 17:09:11.797975 PIEI prepare done
392 17:09:11.798339 fastboot data load
393 17:09:11.798565 fastboot data verify
394 17:09:11.804128 verify result: 266
395 17:09:11.809137 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 17:09:11.809533 LPDDR4 probe
397 17:09:11.809749 ddr clk to 1584MHz
398 17:09:11.817169 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 17:09:11.854418
400 17:09:11.854797 dmc_version 0001
401 17:09:11.861164 Check phy result
402 17:09:11.866930 INFO : End of CA training
403 17:09:11.867251 INFO : End of initialization
404 17:09:11.872520 INFO : Training has run successfully!
405 17:09:11.872803 Check phy result
406 17:09:11.878126 INFO : End of initialization
407 17:09:11.878411 INFO : End of read enable training
408 17:09:11.883845 INFO : End of fine write leveling
409 17:09:11.889340 INFO : End of Write leveling coarse delay
410 17:09:11.889647 INFO : Training has run successfully!
411 17:09:11.889986 Check phy result
412 17:09:11.894925 INFO : End of initialization
413 17:09:11.895217 INFO : End of read dq deskew training
414 17:09:11.900567 INFO : End of MPR read delay center optimization
415 17:09:11.906143 INFO : End of write delay center optimization
416 17:09:11.911733 INFO : End of read delay center optimization
417 17:09:11.912054 INFO : End of max read latency training
418 17:09:11.917309 INFO : Training has run successfully!
419 17:09:11.917588 1D training succeed
420 17:09:11.926496 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 17:09:11.974187 Check phy result
422 17:09:11.974547 INFO : End of initialization
423 17:09:11.996755 INFO : End of 2D read delay Voltage center optimization
424 17:09:12.017028 INFO : End of 2D read delay Voltage center optimization
425 17:09:12.069074 INFO : End of 2D write delay Voltage center optimization
426 17:09:12.118425 INFO : End of 2D write delay Voltage center optimization
427 17:09:12.124045 INFO : Training has run successfully!
428 17:09:12.124324
429 17:09:12.124540 channel==0
430 17:09:12.129546 RxClkDly_Margin_A0==88 ps 9
431 17:09:12.129816 TxDqDly_Margin_A0==98 ps 10
432 17:09:12.135140 RxClkDly_Margin_A1==88 ps 9
433 17:09:12.135406 TxDqDly_Margin_A1==88 ps 9
434 17:09:12.135617 TrainedVREFDQ_A0==74
435 17:09:12.140743 TrainedVREFDQ_A1==74
436 17:09:12.141011 VrefDac_Margin_A0==24
437 17:09:12.141220 DeviceVref_Margin_A0==40
438 17:09:12.146345 VrefDac_Margin_A1==25
439 17:09:12.146616 DeviceVref_Margin_A1==40
440 17:09:12.146826
441 17:09:12.147030
442 17:09:12.147233 channel==1
443 17:09:12.151933 RxClkDly_Margin_A0==98 ps 10
444 17:09:12.152222 TxDqDly_Margin_A0==98 ps 10
445 17:09:12.157550 RxClkDly_Margin_A1==88 ps 9
446 17:09:12.157839 TxDqDly_Margin_A1==108 ps 11
447 17:09:12.163158 TrainedVREFDQ_A0==77
448 17:09:12.163441 TrainedVREFDQ_A1==78
449 17:09:12.163653 VrefDac_Margin_A0==22
450 17:09:12.168752 DeviceVref_Margin_A0==37
451 17:09:12.169034 VrefDac_Margin_A1==24
452 17:09:12.174348 DeviceVref_Margin_A1==36
453 17:09:12.174620
454 17:09:12.174833 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 17:09:12.179934
456 17:09:12.207934 soc_vref_reg_value 0x 00000019 0000001a 00000018 00000019 00000018 00000018 00000019 00000017 00000018 00000017 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
457 17:09:12.208548 2D training succeed
458 17:09:12.213732 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 17:09:12.219327 auto size-- 65535DDR cs0 size: 2048MB
460 17:09:12.219836 DDR cs1 size: 2048MB
461 17:09:12.224915 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 17:09:12.225414 cs0 DataBus test pass
463 17:09:12.230499 cs1 DataBus test pass
464 17:09:12.230996 cs0 AddrBus test pass
465 17:09:12.231432 cs1 AddrBus test pass
466 17:09:12.231862
467 17:09:12.236100 100bdlr_step_size ps== 420
468 17:09:12.236615 result report
469 17:09:12.241683 boot times 0Enable ddr reg access
470 17:09:12.247155 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 17:09:12.260588 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 17:09:12.834069 0.0;M3 CHK:0;cm4_sp_mode 0
473 17:09:12.834495 MVN_1=0x00000000
474 17:09:12.839580 MVN_2=0x00000000
475 17:09:12.845334 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 17:09:12.845815 OPS=0x10
477 17:09:12.846065 ring efuse init
478 17:09:12.846277 chipver efuse init
479 17:09:12.850928 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 17:09:12.856514 [0.018961 Inits done]
481 17:09:12.856961 secure task start!
482 17:09:12.857298 high task start!
483 17:09:12.861086 low task start!
484 17:09:12.861378 run into bl31
485 17:09:12.867764 NOTICE: BL31: v1.3(release):4fc40b1
486 17:09:12.875538 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 17:09:12.876002 NOTICE: BL31: G12A normal boot!
488 17:09:12.900911 NOTICE: BL31: BL33 decompress pass
489 17:09:12.906569 ERROR: Error initializing runtime service opteed_fast
490 17:09:14.139434
491 17:09:14.139879
492 17:09:14.147923 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 17:09:14.148339
494 17:09:14.148562 Model: Libre Computer AML-A311D-CC Alta
495 17:09:14.356258 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 17:09:14.379638 DRAM: 2 GiB (effective 3.8 GiB)
497 17:09:14.522684 Core: 408 devices, 31 uclasses, devicetree: separate
498 17:09:14.528438 WDT: Not starting watchdog@f0d0
499 17:09:14.560708 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 17:09:14.573184 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 17:09:14.578143 ** Bad device specification mmc 0 **
502 17:09:14.588459 Card did not respond to voltage select! : -110
503 17:09:14.596131 ** Bad device specification mmc 0 **
504 17:09:14.596627 Couldn't find partition mmc 0
505 17:09:14.604500 Card did not respond to voltage select! : -110
506 17:09:14.609983 ** Bad device specification mmc 0 **
507 17:09:14.610472 Couldn't find partition mmc 0
508 17:09:14.615054 Error: could not access storage.
509 17:09:15.877612 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 17:09:15.878271 bl2_stage_init 0x01
511 17:09:15.878752 bl2_stage_init 0x81
512 17:09:15.883121 hw id: 0x0000 - pwm id 0x01
513 17:09:15.883625 bl2_stage_init 0xc1
514 17:09:15.884133 bl2_stage_init 0x02
515 17:09:15.884593
516 17:09:15.888710 L0:00000000
517 17:09:15.889184 L1:20000703
518 17:09:15.889630 L2:00008067
519 17:09:15.890069 L3:14000000
520 17:09:15.894334 B2:00402000
521 17:09:15.894871 B1:e0f83180
522 17:09:15.895341
523 17:09:15.895802 TE: 58167
524 17:09:15.896308
525 17:09:15.900021 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 17:09:15.900583
527 17:09:15.901050 Board ID = 1
528 17:09:15.905559 Set A53 clk to 24M
529 17:09:15.906061 Set A73 clk to 24M
530 17:09:15.906524 Set clk81 to 24M
531 17:09:15.911111 A53 clk: 1200 MHz
532 17:09:15.911620 A73 clk: 1200 MHz
533 17:09:15.912114 CLK81: 166.6M
534 17:09:15.912579 smccc: 00012abe
535 17:09:15.916748 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 17:09:15.922322 board id: 1
537 17:09:15.928206 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 17:09:15.938882 fw parse done
539 17:09:15.944834 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 17:09:15.987500 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 17:09:15.998343 PIEI prepare done
542 17:09:15.998862 fastboot data load
543 17:09:15.999323 fastboot data verify
544 17:09:16.004087 verify result: 266
545 17:09:16.009614 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 17:09:16.010130 LPDDR4 probe
547 17:09:16.010587 ddr clk to 1584MHz
548 17:09:16.017669 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 17:09:16.054930
550 17:09:16.055356 dmc_version 0001
551 17:09:16.061607 Check phy result
552 17:09:16.067445 INFO : End of CA training
553 17:09:16.067952 INFO : End of initialization
554 17:09:16.073063 INFO : Training has run successfully!
555 17:09:16.073433 Check phy result
556 17:09:16.078694 INFO : End of initialization
557 17:09:16.079061 INFO : End of read enable training
558 17:09:16.084422 INFO : End of fine write leveling
559 17:09:16.090020 INFO : End of Write leveling coarse delay
560 17:09:16.090597 INFO : Training has run successfully!
561 17:09:16.091067 Check phy result
562 17:09:16.095607 INFO : End of initialization
563 17:09:16.096232 INFO : End of read dq deskew training
564 17:09:16.101196 INFO : End of MPR read delay center optimization
565 17:09:16.106839 INFO : End of write delay center optimization
566 17:09:16.112402 INFO : End of read delay center optimization
567 17:09:16.112966 INFO : End of max read latency training
568 17:09:16.118025 INFO : Training has run successfully!
569 17:09:16.118594 1D training succeed
570 17:09:16.127105 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 17:09:16.174754 Check phy result
572 17:09:16.175332 INFO : End of initialization
573 17:09:16.196566 INFO : End of 2D read delay Voltage center optimization
574 17:09:16.216892 INFO : End of 2D read delay Voltage center optimization
575 17:09:16.268868 INFO : End of 2D write delay Voltage center optimization
576 17:09:16.318206 INFO : End of 2D write delay Voltage center optimization
577 17:09:16.323730 INFO : Training has run successfully!
578 17:09:16.324109
579 17:09:16.324358 channel==0
580 17:09:16.329207 RxClkDly_Margin_A0==88 ps 9
581 17:09:16.329539 TxDqDly_Margin_A0==98 ps 10
582 17:09:16.334801 RxClkDly_Margin_A1==88 ps 9
583 17:09:16.335147 TxDqDly_Margin_A1==98 ps 10
584 17:09:16.335362 TrainedVREFDQ_A0==74
585 17:09:16.340427 TrainedVREFDQ_A1==74
586 17:09:16.340780 VrefDac_Margin_A0==25
587 17:09:16.341007 DeviceVref_Margin_A0==40
588 17:09:16.346056 VrefDac_Margin_A1==25
589 17:09:16.346417 DeviceVref_Margin_A1==40
590 17:09:16.346639
591 17:09:16.346849
592 17:09:16.351658 channel==1
593 17:09:16.352018 RxClkDly_Margin_A0==98 ps 10
594 17:09:16.352253 TxDqDly_Margin_A0==88 ps 9
595 17:09:16.357206 RxClkDly_Margin_A1==98 ps 10
596 17:09:16.357674 TxDqDly_Margin_A1==88 ps 9
597 17:09:16.362812 TrainedVREFDQ_A0==76
598 17:09:16.363137 TrainedVREFDQ_A1==77
599 17:09:16.363356 VrefDac_Margin_A0==22
600 17:09:16.368431 DeviceVref_Margin_A0==38
601 17:09:16.368928 VrefDac_Margin_A1==22
602 17:09:16.374054 DeviceVref_Margin_A1==37
603 17:09:16.374549
604 17:09:16.374808 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 17:09:16.375020
606 17:09:16.407651 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
607 17:09:16.408078 2D training succeed
608 17:09:16.413206 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 17:09:16.418800 auto size-- 65535DDR cs0 size: 2048MB
610 17:09:16.419130 DDR cs1 size: 2048MB
611 17:09:16.424401 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 17:09:16.424734 cs0 DataBus test pass
613 17:09:16.430024 cs1 DataBus test pass
614 17:09:16.430358 cs0 AddrBus test pass
615 17:09:16.430581 cs1 AddrBus test pass
616 17:09:16.430796
617 17:09:16.435662 100bdlr_step_size ps== 420
618 17:09:16.436034 result report
619 17:09:16.441214 boot times 0Enable ddr reg access
620 17:09:16.446556 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 17:09:16.460912 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 17:09:17.033077 0.0;M3 CHK:0;cm4_sp_mode 0
623 17:09:17.033507 MVN_1=0x00000000
624 17:09:17.038627 MVN_2=0x00000000
625 17:09:17.044376 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 17:09:17.044690 OPS=0x10
627 17:09:17.044910 ring efuse init
628 17:09:17.045118 chipver efuse init
629 17:09:17.052775 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 17:09:17.053116 [0.018960 Inits done]
631 17:09:17.053327 secure task start!
632 17:09:17.060190 high task start!
633 17:09:17.060521 low task start!
634 17:09:17.060735 run into bl31
635 17:09:17.066854 NOTICE: BL31: v1.3(release):4fc40b1
636 17:09:17.074650 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 17:09:17.074978 NOTICE: BL31: G12A normal boot!
638 17:09:17.100056 NOTICE: BL31: BL33 decompress pass
639 17:09:17.105759 ERROR: Error initializing runtime service opteed_fast
640 17:09:18.338617
641 17:09:18.339061
642 17:09:18.347112 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 17:09:18.347630
644 17:09:18.347970 Model: Libre Computer AML-A311D-CC Alta
645 17:09:18.555411 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 17:09:18.578872 DRAM: 2 GiB (effective 3.8 GiB)
647 17:09:18.721863 Core: 408 devices, 31 uclasses, devicetree: separate
648 17:09:18.727714 WDT: Not starting watchdog@f0d0
649 17:09:18.759975 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 17:09:18.772284 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 17:09:18.777322 ** Bad device specification mmc 0 **
652 17:09:18.787747 Card did not respond to voltage select! : -110
653 17:09:18.795363 ** Bad device specification mmc 0 **
654 17:09:18.795673 Couldn't find partition mmc 0
655 17:09:18.803608 Card did not respond to voltage select! : -110
656 17:09:18.809103 ** Bad device specification mmc 0 **
657 17:09:18.809624 Couldn't find partition mmc 0
658 17:09:18.814122 Error: could not access storage.
659 17:09:19.157767 Net: eth0: ethernet@ff3f0000
660 17:09:19.158380 starting USB...
661 17:09:19.409635 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 17:09:19.410254 Starting the controller
663 17:09:19.416599 USB XHCI 1.10
664 17:09:21.129550 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 17:09:21.130239 bl2_stage_init 0x01
666 17:09:21.130721 bl2_stage_init 0x81
667 17:09:21.135232 hw id: 0x0000 - pwm id 0x01
668 17:09:21.135764 bl2_stage_init 0xc1
669 17:09:21.136281 bl2_stage_init 0x02
670 17:09:21.136736
671 17:09:21.140793 L0:00000000
672 17:09:21.141309 L1:20000703
673 17:09:21.141763 L2:00008067
674 17:09:21.142203 L3:14000000
675 17:09:21.146426 B2:00402000
676 17:09:21.146939 B1:e0f83180
677 17:09:21.147391
678 17:09:21.147836 TE: 58159
679 17:09:21.148329
680 17:09:21.151955 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 17:09:21.152499
682 17:09:21.152955 Board ID = 1
683 17:09:21.157513 Set A53 clk to 24M
684 17:09:21.158025 Set A73 clk to 24M
685 17:09:21.158472 Set clk81 to 24M
686 17:09:21.163174 A53 clk: 1200 MHz
687 17:09:21.163690 A73 clk: 1200 MHz
688 17:09:21.164181 CLK81: 166.6M
689 17:09:21.164631 smccc: 00012ab5
690 17:09:21.168769 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 17:09:21.174458 board id: 1
692 17:09:21.180283 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 17:09:21.190881 fw parse done
694 17:09:21.196939 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 17:09:21.240197 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 17:09:21.250446 PIEI prepare done
697 17:09:21.250998 fastboot data load
698 17:09:21.251467 fastboot data verify
699 17:09:21.256176 verify result: 266
700 17:09:21.261633 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 17:09:21.262164 LPDDR4 probe
702 17:09:21.262616 ddr clk to 1584MHz
703 17:09:21.269613 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 17:09:21.306957
705 17:09:21.307526 dmc_version 0001
706 17:09:21.313578 Check phy result
707 17:09:21.319417 INFO : End of CA training
708 17:09:21.319948 INFO : End of initialization
709 17:09:21.325041 INFO : Training has run successfully!
710 17:09:21.325581 Check phy result
711 17:09:21.330650 INFO : End of initialization
712 17:09:21.331216 INFO : End of read enable training
713 17:09:21.336258 INFO : End of fine write leveling
714 17:09:21.341858 INFO : End of Write leveling coarse delay
715 17:09:21.342429 INFO : Training has run successfully!
716 17:09:21.342882 Check phy result
717 17:09:21.347435 INFO : End of initialization
718 17:09:21.348022 INFO : End of read dq deskew training
719 17:09:21.353019 INFO : End of MPR read delay center optimization
720 17:09:21.358577 INFO : End of write delay center optimization
721 17:09:21.364274 INFO : End of read delay center optimization
722 17:09:21.364808 INFO : End of max read latency training
723 17:09:21.369798 INFO : Training has run successfully!
724 17:09:21.370324 1D training succeed
725 17:09:21.378961 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 17:09:21.427775 Check phy result
727 17:09:21.428479 INFO : End of initialization
728 17:09:21.449152 INFO : End of 2D read delay Voltage center optimization
729 17:09:21.469460 INFO : End of 2D read delay Voltage center optimization
730 17:09:21.521464 INFO : End of 2D write delay Voltage center optimization
731 17:09:21.570963 INFO : End of 2D write delay Voltage center optimization
732 17:09:21.576437 INFO : Training has run successfully!
733 17:09:21.576959
734 17:09:21.577421 channel==0
735 17:09:21.582082 RxClkDly_Margin_A0==88 ps 9
736 17:09:21.582598 TxDqDly_Margin_A0==98 ps 10
737 17:09:21.585426 RxClkDly_Margin_A1==88 ps 9
738 17:09:21.585939 TxDqDly_Margin_A1==88 ps 9
739 17:09:21.590925 TrainedVREFDQ_A0==74
740 17:09:21.591458 TrainedVREFDQ_A1==74
741 17:09:21.591914 VrefDac_Margin_A0==24
742 17:09:21.596600 DeviceVref_Margin_A0==40
743 17:09:21.597110 VrefDac_Margin_A1==25
744 17:09:21.602116 DeviceVref_Margin_A1==40
745 17:09:21.602635
746 17:09:21.603084
747 17:09:21.603527 channel==1
748 17:09:21.603962 RxClkDly_Margin_A0==98 ps 10
749 17:09:21.605748 TxDqDly_Margin_A0==88 ps 9
750 17:09:21.611299 RxClkDly_Margin_A1==98 ps 10
751 17:09:21.611810 TxDqDly_Margin_A1==88 ps 9
752 17:09:21.612309 TrainedVREFDQ_A0==76
753 17:09:21.616778 TrainedVREFDQ_A1==77
754 17:09:21.617291 VrefDac_Margin_A0==22
755 17:09:21.622473 DeviceVref_Margin_A0==38
756 17:09:21.622981 VrefDac_Margin_A1==22
757 17:09:21.623434 DeviceVref_Margin_A1==37
758 17:09:21.623871
759 17:09:21.628096 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 17:09:21.628601
761 17:09:21.661613 soc_vref_reg_value 0x 00000019 0000001a 00000018 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000016 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000018 dram_vref_reg_value 0x 00000060
762 17:09:21.662204 2D training succeed
763 17:09:21.667154 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 17:09:21.672723 auto size-- 65535DDR cs0 size: 2048MB
765 17:09:21.673239 DDR cs1 size: 2048MB
766 17:09:21.678345 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 17:09:21.678862 cs0 DataBus test pass
768 17:09:21.679316 cs1 DataBus test pass
769 17:09:21.683904 cs0 AddrBus test pass
770 17:09:21.684439 cs1 AddrBus test pass
771 17:09:21.684893
772 17:09:21.689529 100bdlr_step_size ps== 420
773 17:09:21.690052 result report
774 17:09:21.690500 boot times 0Enable ddr reg access
775 17:09:21.699113 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 17:09:21.712595 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 17:09:22.286309 0.0;M3 CHK:0;cm4_sp_mode 0
778 17:09:22.286950 MVN_1=0x00000000
779 17:09:22.291837 MVN_2=0x00000000
780 17:09:22.297578 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 17:09:22.298134 OPS=0x10
782 17:09:22.298574 ring efuse init
783 17:09:22.298998 chipver efuse init
784 17:09:22.303135 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 17:09:22.308715 [0.018961 Inits done]
786 17:09:22.309238 secure task start!
787 17:09:22.309673 high task start!
788 17:09:22.313322 low task start!
789 17:09:22.313826 run into bl31
790 17:09:22.319911 NOTICE: BL31: v1.3(release):4fc40b1
791 17:09:22.327733 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 17:09:22.328306 NOTICE: BL31: G12A normal boot!
793 17:09:22.353083 NOTICE: BL31: BL33 decompress pass
794 17:09:22.358773 ERROR: Error initializing runtime service opteed_fast
795 17:09:23.591755
796 17:09:23.592467
797 17:09:23.600095 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 17:09:23.600622
799 17:09:23.601087 Model: Libre Computer AML-A311D-CC Alta
800 17:09:23.808504 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 17:09:23.831887 DRAM: 2 GiB (effective 3.8 GiB)
802 17:09:23.974893 Core: 408 devices, 31 uclasses, devicetree: separate
803 17:09:23.980838 WDT: Not starting watchdog@f0d0
804 17:09:24.013029 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 17:09:24.025459 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 17:09:24.030469 ** Bad device specification mmc 0 **
807 17:09:24.040856 Card did not respond to voltage select! : -110
808 17:09:24.048493 ** Bad device specification mmc 0 **
809 17:09:24.049056 Couldn't find partition mmc 0
810 17:09:24.056816 Card did not respond to voltage select! : -110
811 17:09:24.062301 ** Bad device specification mmc 0 **
812 17:09:24.062867 Couldn't find partition mmc 0
813 17:09:24.067407 Error: could not access storage.
814 17:09:24.410980 Net: eth0: ethernet@ff3f0000
815 17:09:24.411649 starting USB...
816 17:09:24.662680 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 17:09:24.663288 Starting the controller
818 17:09:24.669620 USB XHCI 1.10
819 17:09:26.828060 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 17:09:26.828732 bl2_stage_init 0x01
821 17:09:26.829207 bl2_stage_init 0x81
822 17:09:26.833597 hw id: 0x0000 - pwm id 0x01
823 17:09:26.834153 bl2_stage_init 0xc1
824 17:09:26.834633 bl2_stage_init 0x02
825 17:09:26.835075
826 17:09:26.839086 L0:00000000
827 17:09:26.839608 L1:20000703
828 17:09:26.840096 L2:00008067
829 17:09:26.840549 L3:14000000
830 17:09:26.844785 B2:00402000
831 17:09:26.845293 B1:e0f83180
832 17:09:26.845746
833 17:09:26.846188 TE: 58167
834 17:09:26.846634
835 17:09:26.850349 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 17:09:26.850861
837 17:09:26.851315 Board ID = 1
838 17:09:26.855941 Set A53 clk to 24M
839 17:09:26.856476 Set A73 clk to 24M
840 17:09:26.856926 Set clk81 to 24M
841 17:09:26.861520 A53 clk: 1200 MHz
842 17:09:26.862021 A73 clk: 1200 MHz
843 17:09:26.862473 CLK81: 166.6M
844 17:09:26.862910 smccc: 00012abd
845 17:09:26.867110 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 17:09:26.872681 board id: 1
847 17:09:26.878615 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 17:09:26.889256 fw parse done
849 17:09:26.895231 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 17:09:26.937829 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 17:09:26.948734 PIEI prepare done
852 17:09:26.949254 fastboot data load
853 17:09:26.949706 fastboot data verify
854 17:09:26.954378 verify result: 266
855 17:09:26.959975 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 17:09:26.960521 LPDDR4 probe
857 17:09:26.960976 ddr clk to 1584MHz
858 17:09:26.967918 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 17:09:27.005250
860 17:09:27.005797 dmc_version 0001
861 17:09:27.011932 Check phy result
862 17:09:27.017777 INFO : End of CA training
863 17:09:27.018281 INFO : End of initialization
864 17:09:27.023416 INFO : Training has run successfully!
865 17:09:27.023947 Check phy result
866 17:09:27.029059 INFO : End of initialization
867 17:09:27.029584 INFO : End of read enable training
868 17:09:27.034621 INFO : End of fine write leveling
869 17:09:27.040277 INFO : End of Write leveling coarse delay
870 17:09:27.040825 INFO : Training has run successfully!
871 17:09:27.041286 Check phy result
872 17:09:27.045768 INFO : End of initialization
873 17:09:27.046278 INFO : End of read dq deskew training
874 17:09:27.051398 INFO : End of MPR read delay center optimization
875 17:09:27.057027 INFO : End of write delay center optimization
876 17:09:27.062574 INFO : End of read delay center optimization
877 17:09:27.063082 INFO : End of max read latency training
878 17:09:27.068203 INFO : Training has run successfully!
879 17:09:27.068708 1D training succeed
880 17:09:27.077344 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 17:09:27.124951 Check phy result
882 17:09:27.125484 INFO : End of initialization
883 17:09:27.146710 INFO : End of 2D read delay Voltage center optimization
884 17:09:27.167008 INFO : End of 2D read delay Voltage center optimization
885 17:09:27.219024 INFO : End of 2D write delay Voltage center optimization
886 17:09:27.268367 INFO : End of 2D write delay Voltage center optimization
887 17:09:27.273779 INFO : Training has run successfully!
888 17:09:27.274080
889 17:09:27.274296 channel==0
890 17:09:27.279502 RxClkDly_Margin_A0==88 ps 9
891 17:09:27.279855 TxDqDly_Margin_A0==98 ps 10
892 17:09:27.285093 RxClkDly_Margin_A1==88 ps 9
893 17:09:27.285583 TxDqDly_Margin_A1==98 ps 10
894 17:09:27.286010 TrainedVREFDQ_A0==74
895 17:09:27.290643 TrainedVREFDQ_A1==74
896 17:09:27.291122 VrefDac_Margin_A0==25
897 17:09:27.291557 DeviceVref_Margin_A0==40
898 17:09:27.296261 VrefDac_Margin_A1==25
899 17:09:27.296766 DeviceVref_Margin_A1==40
900 17:09:27.297184
901 17:09:27.297613
902 17:09:27.301810 channel==1
903 17:09:27.302274 RxClkDly_Margin_A0==98 ps 10
904 17:09:27.302533 TxDqDly_Margin_A0==88 ps 9
905 17:09:27.307529 RxClkDly_Margin_A1==98 ps 10
906 17:09:27.307916 TxDqDly_Margin_A1==88 ps 9
907 17:09:27.313033 TrainedVREFDQ_A0==76
908 17:09:27.313365 TrainedVREFDQ_A1==77
909 17:09:27.313614 VrefDac_Margin_A0==22
910 17:09:27.318635 DeviceVref_Margin_A0==38
911 17:09:27.318962 VrefDac_Margin_A1==22
912 17:09:27.324332 DeviceVref_Margin_A1==37
913 17:09:27.324662
914 17:09:27.324896 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 17:09:27.325116
916 17:09:27.357783 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
917 17:09:27.358198 2D training succeed
918 17:09:27.363442 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 17:09:27.368914 auto size-- 65535DDR cs0 size: 2048MB
920 17:09:27.369254 DDR cs1 size: 2048MB
921 17:09:27.374540 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 17:09:27.374928 cs0 DataBus test pass
923 17:09:27.380134 cs1 DataBus test pass
924 17:09:27.380410 cs0 AddrBus test pass
925 17:09:27.380616 cs1 AddrBus test pass
926 17:09:27.380814
927 17:09:27.385643 100bdlr_step_size ps== 420
928 17:09:27.385896 result report
929 17:09:27.391249 boot times 0Enable ddr reg access
930 17:09:27.396696 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 17:09:27.410083 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 17:09:27.983932 0.0;M3 CHK:0;cm4_sp_mode 0
933 17:09:27.984608 MVN_1=0x00000000
934 17:09:27.989353 MVN_2=0x00000000
935 17:09:27.995107 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 17:09:27.995611 OPS=0x10
937 17:09:27.996067 ring efuse init
938 17:09:27.996400 chipver efuse init
939 17:09:28.000767 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 17:09:28.006419 [0.018961 Inits done]
941 17:09:28.006934 secure task start!
942 17:09:28.007354 high task start!
943 17:09:28.010915 low task start!
944 17:09:28.011450 run into bl31
945 17:09:28.017727 NOTICE: BL31: v1.3(release):4fc40b1
946 17:09:28.025803 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 17:09:28.026447 NOTICE: BL31: G12A normal boot!
948 17:09:28.050876 NOTICE: BL31: BL33 decompress pass
949 17:09:28.056517 ERROR: Error initializing runtime service opteed_fast
950 17:09:29.289768
951 17:09:29.290220
952 17:09:29.298901 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 17:09:29.300408
954 17:09:29.300948 Model: Libre Computer AML-A311D-CC Alta
955 17:09:29.506236 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 17:09:29.529521 DRAM: 2 GiB (effective 3.8 GiB)
957 17:09:29.672682 Core: 408 devices, 31 uclasses, devicetree: separate
958 17:09:29.678327 WDT: Not starting watchdog@f0d0
959 17:09:29.710701 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 17:09:29.723240 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 17:09:29.728202 ** Bad device specification mmc 0 **
962 17:09:29.738721 Card did not respond to voltage select! : -110
963 17:09:29.746331 ** Bad device specification mmc 0 **
964 17:09:29.747143 Couldn't find partition mmc 0
965 17:09:29.754640 Card did not respond to voltage select! : -110
966 17:09:29.760240 ** Bad device specification mmc 0 **
967 17:09:29.760894 Couldn't find partition mmc 0
968 17:09:29.765166 Error: could not access storage.
969 17:09:30.108625 Net: eth0: ethernet@ff3f0000
970 17:09:30.109311 starting USB...
971 17:09:30.360575 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 17:09:30.361219 Starting the controller
973 17:09:30.367329 USB XHCI 1.10
974 17:09:32.197696 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 17:09:32.198312 bl2_stage_init 0x01
976 17:09:32.198738 bl2_stage_init 0x81
977 17:09:32.203243 hw id: 0x0000 - pwm id 0x01
978 17:09:32.203699 bl2_stage_init 0xc1
979 17:09:32.204155 bl2_stage_init 0x02
980 17:09:32.204563
981 17:09:32.208847 L0:00000000
982 17:09:32.209292 L1:20000703
983 17:09:32.209700 L2:00008067
984 17:09:32.210098 L3:14000000
985 17:09:32.214456 B2:00402000
986 17:09:32.214904 B1:e0f83180
987 17:09:32.215310
988 17:09:32.215713 TE: 58159
989 17:09:32.216158
990 17:09:32.220084 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 17:09:32.220529
992 17:09:32.220935 Board ID = 1
993 17:09:32.225639 Set A53 clk to 24M
994 17:09:32.226078 Set A73 clk to 24M
995 17:09:32.226474 Set clk81 to 24M
996 17:09:32.231218 A53 clk: 1200 MHz
997 17:09:32.231657 A73 clk: 1200 MHz
998 17:09:32.232096 CLK81: 166.6M
999 17:09:32.232497 smccc: 00012ab5
1000 17:09:32.236845 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 17:09:32.242430 board id: 1
1002 17:09:32.248315 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 17:09:32.259126 fw parse done
1004 17:09:32.264083 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 17:09:32.307621 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 17:09:32.318533 PIEI prepare done
1007 17:09:32.319062 fastboot data load
1008 17:09:32.319457 fastboot data verify
1009 17:09:32.324262 verify result: 266
1010 17:09:32.329875 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 17:09:32.330311 LPDDR4 probe
1012 17:09:32.330699 ddr clk to 1584MHz
1013 17:09:32.337821 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 17:09:32.375168
1015 17:09:32.375670 dmc_version 0001
1016 17:09:32.381757 Check phy result
1017 17:09:32.387585 INFO : End of CA training
1018 17:09:32.388054 INFO : End of initialization
1019 17:09:32.393455 INFO : Training has run successfully!
1020 17:09:32.393898 Check phy result
1021 17:09:32.398973 INFO : End of initialization
1022 17:09:32.399412 INFO : End of read enable training
1023 17:09:32.404642 INFO : End of fine write leveling
1024 17:09:32.410274 INFO : End of Write leveling coarse delay
1025 17:09:32.410714 INFO : Training has run successfully!
1026 17:09:32.411103 Check phy result
1027 17:09:32.415612 INFO : End of initialization
1028 17:09:32.416086 INFO : End of read dq deskew training
1029 17:09:32.421296 INFO : End of MPR read delay center optimization
1030 17:09:32.426852 INFO : End of write delay center optimization
1031 17:09:32.432437 INFO : End of read delay center optimization
1032 17:09:32.432880 INFO : End of max read latency training
1033 17:09:32.438219 INFO : Training has run successfully!
1034 17:09:32.438665 1D training succeed
1035 17:09:32.447602 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 17:09:32.494847 Check phy result
1037 17:09:32.495368 INFO : End of initialization
1038 17:09:32.516587 INFO : End of 2D read delay Voltage center optimization
1039 17:09:32.536760 INFO : End of 2D read delay Voltage center optimization
1040 17:09:32.588819 INFO : End of 2D write delay Voltage center optimization
1041 17:09:32.638205 INFO : End of 2D write delay Voltage center optimization
1042 17:09:32.643768 INFO : Training has run successfully!
1043 17:09:32.644266
1044 17:09:32.644680 channel==0
1045 17:09:32.649333 RxClkDly_Margin_A0==88 ps 9
1046 17:09:32.649771 TxDqDly_Margin_A0==98 ps 10
1047 17:09:32.654931 RxClkDly_Margin_A1==88 ps 9
1048 17:09:32.655374 TxDqDly_Margin_A1==98 ps 10
1049 17:09:32.655781 TrainedVREFDQ_A0==74
1050 17:09:32.660575 TrainedVREFDQ_A1==74
1051 17:09:32.661019 VrefDac_Margin_A0==25
1052 17:09:32.661421 DeviceVref_Margin_A0==40
1053 17:09:32.666144 VrefDac_Margin_A1==25
1054 17:09:32.666588 DeviceVref_Margin_A1==40
1055 17:09:32.666987
1056 17:09:32.667383
1057 17:09:32.671744 channel==1
1058 17:09:32.672207 RxClkDly_Margin_A0==98 ps 10
1059 17:09:32.672613 TxDqDly_Margin_A0==98 ps 10
1060 17:09:32.677334 RxClkDly_Margin_A1==88 ps 9
1061 17:09:32.677776 TxDqDly_Margin_A1==88 ps 9
1062 17:09:32.682940 TrainedVREFDQ_A0==77
1063 17:09:32.683382 TrainedVREFDQ_A1==77
1064 17:09:32.683784 VrefDac_Margin_A0==23
1065 17:09:32.688535 DeviceVref_Margin_A0==37
1066 17:09:32.688968 VrefDac_Margin_A1==24
1067 17:09:32.694148 DeviceVref_Margin_A1==37
1068 17:09:32.694582
1069 17:09:32.694985 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 17:09:32.695392
1071 17:09:32.727733 soc_vref_reg_value 0x 00000019 0000001a 00000018 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1072 17:09:32.728281 2D training succeed
1073 17:09:32.733327 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 17:09:32.738938 auto size-- 65535DDR cs0 size: 2048MB
1075 17:09:32.739387 DDR cs1 size: 2048MB
1076 17:09:32.744513 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 17:09:32.744962 cs0 DataBus test pass
1078 17:09:32.750165 cs1 DataBus test pass
1079 17:09:32.750612 cs0 AddrBus test pass
1080 17:09:32.751020 cs1 AddrBus test pass
1081 17:09:32.751421
1082 17:09:32.755727 100bdlr_step_size ps== 420
1083 17:09:32.756231 result report
1084 17:09:32.761335 boot times 0Enable ddr reg access
1085 17:09:32.766687 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 17:09:32.780183 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 17:09:33.353907 0.0;M3 CHK:0;cm4_sp_mode 0
1088 17:09:33.354491 MVN_1=0x00000000
1089 17:09:33.359283 MVN_2=0x00000000
1090 17:09:33.365013 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 17:09:33.365485 OPS=0x10
1092 17:09:33.365893 ring efuse init
1093 17:09:33.366303 chipver efuse init
1094 17:09:33.370627 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 17:09:33.376249 [0.018960 Inits done]
1096 17:09:33.376722 secure task start!
1097 17:09:33.377131 high task start!
1098 17:09:33.380793 low task start!
1099 17:09:33.381252 run into bl31
1100 17:09:33.387459 NOTICE: BL31: v1.3(release):4fc40b1
1101 17:09:33.395367 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 17:09:33.395846 NOTICE: BL31: G12A normal boot!
1103 17:09:33.420802 NOTICE: BL31: BL33 decompress pass
1104 17:09:33.426319 ERROR: Error initializing runtime service opteed_fast
1105 17:09:34.659397
1106 17:09:34.660310
1107 17:09:34.667737 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 17:09:34.668334
1109 17:09:34.668820 Model: Libre Computer AML-A311D-CC Alta
1110 17:09:34.876294 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 17:09:34.899573 DRAM: 2 GiB (effective 3.8 GiB)
1112 17:09:35.042629 Core: 408 devices, 31 uclasses, devicetree: separate
1113 17:09:35.048441 WDT: Not starting watchdog@f0d0
1114 17:09:35.080706 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 17:09:35.093096 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 17:09:35.098101 ** Bad device specification mmc 0 **
1117 17:09:35.108456 Card did not respond to voltage select! : -110
1118 17:09:35.116114 ** Bad device specification mmc 0 **
1119 17:09:35.116680 Couldn't find partition mmc 0
1120 17:09:35.124459 Card did not respond to voltage select! : -110
1121 17:09:35.129937 ** Bad device specification mmc 0 **
1122 17:09:35.130483 Couldn't find partition mmc 0
1123 17:09:35.134055 Error: could not access storage.
1124 17:09:35.478485 Net: eth0: ethernet@ff3f0000
1125 17:09:35.479144 starting USB...
1126 17:09:35.730397 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 17:09:35.731046 Starting the controller
1128 17:09:35.737323 USB XHCI 1.10
1129 17:09:37.294342 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 17:09:37.302748 scanning usb for storage devices... 0 Storage Device(s) found
1132 17:09:37.354548 Hit any key to stop autoboot: 1
1133 17:09:37.355538 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 17:09:37.356300 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1135 17:09:37.356889 Setting prompt string to ['=>']
1136 17:09:37.357423 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1137 17:09:37.370147 0
1138 17:09:37.371258 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 17:09:37.371800 Sending with 10 millisecond of delay
1141 17:09:38.507178 => setenv autoload no
1142 17:09:38.518063 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1143 17:09:38.523499 setenv autoload no
1144 17:09:38.524341 Sending with 10 millisecond of delay
1146 17:09:40.322312 => setenv initrd_high 0xffffffff
1147 17:09:40.333178 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1148 17:09:40.334154 setenv initrd_high 0xffffffff
1149 17:09:40.334927 Sending with 10 millisecond of delay
1151 17:09:41.952512 => setenv fdt_high 0xffffffff
1152 17:09:41.963350 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1153 17:09:41.964365 setenv fdt_high 0xffffffff
1154 17:09:41.965106 Sending with 10 millisecond of delay
1156 17:09:42.257104 => dhcp
1157 17:09:42.267885 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 17:09:42.268761 dhcp
1159 17:09:42.269198 Speed: 1000, full duplex
1160 17:09:42.269615 BOOTP broadcast 1
1161 17:09:42.278601 DHCP client bound to address 192.168.6.27 (10 ms)
1162 17:09:42.279339 Sending with 10 millisecond of delay
1164 17:09:43.956509 => setenv serverip 192.168.6.2
1165 17:09:43.967219 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1166 17:09:43.968309 setenv serverip 192.168.6.2
1167 17:09:43.969083 Sending with 10 millisecond of delay
1169 17:09:47.699076 => tftpboot 0x01080000 975707/tftp-deploy-xie32id1/kernel/uImage
1170 17:09:47.709975 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1171 17:09:47.710972 tftpboot 0x01080000 975707/tftp-deploy-xie32id1/kernel/uImage
1172 17:09:47.711484 Speed: 1000, full duplex
1173 17:09:47.712031 Using ethernet@ff3f0000 device
1174 17:09:47.712904 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 17:09:47.718336 Filename '975707/tftp-deploy-xie32id1/kernel/uImage'.
1176 17:09:47.722097 Load address: 0x1080000
1177 17:09:50.888930 Loading: *################################################## 43.6 MiB
1178 17:09:50.889353 13.8 MiB/s
1179 17:09:50.889581 done
1180 17:09:50.892500 Bytes transferred = 45713984 (2b98a40 hex)
1181 17:09:50.893030 Sending with 10 millisecond of delay
1183 17:09:55.588543 => tftpboot 0x08000000 975707/tftp-deploy-xie32id1/ramdisk/ramdisk.cpio.gz.uboot
1184 17:09:55.599397 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1185 17:09:55.600336 tftpboot 0x08000000 975707/tftp-deploy-xie32id1/ramdisk/ramdisk.cpio.gz.uboot
1186 17:09:55.600839 Speed: 1000, full duplex
1187 17:09:55.601302 Using ethernet@ff3f0000 device
1188 17:09:55.602205 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 17:09:55.610947 Filename '975707/tftp-deploy-xie32id1/ramdisk/ramdisk.cpio.gz.uboot'.
1190 17:09:55.611559 Load address: 0x8000000
1191 17:10:02.223208 Loading: *############T ##################################### UDP wrong checksum 00000005 00004654
1192 17:10:07.223014 T UDP wrong checksum 00000005 00004654
1193 17:10:17.227080 T T UDP wrong checksum 00000005 00004654
1194 17:10:33.743376 T T T UDP wrong checksum 000000ff 0000da4b
1195 17:10:33.783249 UDP wrong checksum 000000ff 0000753e
1196 17:10:36.310877 UDP wrong checksum 000000ff 0000edd5
1197 17:10:36.319364 UDP wrong checksum 000000ff 00007ac8
1198 17:10:37.231038 T UDP wrong checksum 00000005 00004654
1199 17:10:42.495029 T UDP wrong checksum 000000ff 00000705
1200 17:10:42.536914 UDP wrong checksum 000000ff 00005f79
1201 17:10:52.235201 T
1202 17:10:52.235868 Retry count exceeded; starting again
1204 17:10:52.237464 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1207 17:10:52.239493 end: 2.4 uboot-commands (duration 00:01:52) [common]
1209 17:10:52.241055 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1211 17:10:52.242198 end: 2 uboot-action (duration 00:01:52) [common]
1213 17:10:52.243919 Cleaning after the job
1214 17:10:52.244563 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975707/tftp-deploy-xie32id1/ramdisk
1215 17:10:52.245999 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975707/tftp-deploy-xie32id1/kernel
1216 17:10:52.293463 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975707/tftp-deploy-xie32id1/dtb
1217 17:10:52.294366 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975707/tftp-deploy-xie32id1/nfsrootfs
1218 17:10:52.345342 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975707/tftp-deploy-xie32id1/modules
1219 17:10:52.351866 start: 4.1 power-off (timeout 00:00:30) [common]
1220 17:10:52.352518 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1221 17:10:52.383721 >> OK - accepted request
1222 17:10:52.385561 Returned 0 in 0 seconds
1223 17:10:52.486385 end: 4.1 power-off (duration 00:00:00) [common]
1225 17:10:52.487421 start: 4.2 read-feedback (timeout 00:10:00) [common]
1226 17:10:52.488119 Listened to connection for namespace 'common' for up to 1s
1227 17:10:53.489072 Finalising connection for namespace 'common'
1228 17:10:53.489587 Disconnecting from shell: Finalise
1229 17:10:53.489899 =>
1230 17:10:53.590694 end: 4.2 read-feedback (duration 00:00:01) [common]
1231 17:10:53.591357 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/975707
1232 17:10:56.545279 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/975707
1233 17:10:56.545883 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.