Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 16:09:59.069558 lava-dispatcher, installed at version: 2024.01
2 16:09:59.070393 start: 0 validate
3 16:09:59.070821 Start time: 2024-11-11 16:09:59.070792+00:00 (UTC)
4 16:09:59.071320 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 16:09:59.071827 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 16:09:59.117665 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 16:09:59.118245 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fnext%2Frenesas-next-2024-11-11-v6.12-rc1%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 16:09:59.149872 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 16:09:59.150536 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fnext%2Frenesas-next-2024-11-11-v6.12-rc1%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 16:10:00.206202 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 16:10:00.206690 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fnext%2Frenesas-next-2024-11-11-v6.12-rc1%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 16:10:00.255650 validate duration: 1.18
14 16:10:00.257319 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 16:10:00.257746 start: 1.1 download-retry (timeout 00:10:00) [common]
16 16:10:00.258140 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 16:10:00.258987 Not decompressing ramdisk as can be used compressed.
18 16:10:00.259826 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 16:10:00.260369 saving as /var/lib/lava/dispatcher/tmp/975477/tftp-deploy-dmujxi_l/ramdisk/rootfs.cpio.gz
20 16:10:00.261054 total size: 8181887 (7 MB)
21 16:10:00.298977 progress 0 % (0 MB)
22 16:10:00.310186 progress 5 % (0 MB)
23 16:10:00.320761 progress 10 % (0 MB)
24 16:10:00.332234 progress 15 % (1 MB)
25 16:10:00.337782 progress 20 % (1 MB)
26 16:10:00.343725 progress 25 % (1 MB)
27 16:10:00.349457 progress 30 % (2 MB)
28 16:10:00.355498 progress 35 % (2 MB)
29 16:10:00.361146 progress 40 % (3 MB)
30 16:10:00.367024 progress 45 % (3 MB)
31 16:10:00.372631 progress 50 % (3 MB)
32 16:10:00.378528 progress 55 % (4 MB)
33 16:10:00.384044 progress 60 % (4 MB)
34 16:10:00.390144 progress 65 % (5 MB)
35 16:10:00.395877 progress 70 % (5 MB)
36 16:10:00.402297 progress 75 % (5 MB)
37 16:10:00.407855 progress 80 % (6 MB)
38 16:10:00.413697 progress 85 % (6 MB)
39 16:10:00.419126 progress 90 % (7 MB)
40 16:10:00.424935 progress 95 % (7 MB)
41 16:10:00.429936 progress 100 % (7 MB)
42 16:10:00.430579 7 MB downloaded in 0.17 s (46.03 MB/s)
43 16:10:00.431121 end: 1.1.1 http-download (duration 00:00:00) [common]
45 16:10:00.432012 end: 1.1 download-retry (duration 00:00:00) [common]
46 16:10:00.432311 start: 1.2 download-retry (timeout 00:10:00) [common]
47 16:10:00.432581 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 16:10:00.433041 downloading http://storage.kernelci.org/renesas/next/renesas-next-2024-11-11-v6.12-rc1/arm64/defconfig/gcc-12/kernel/Image
49 16:10:00.433283 saving as /var/lib/lava/dispatcher/tmp/975477/tftp-deploy-dmujxi_l/kernel/Image
50 16:10:00.433495 total size: 45713920 (43 MB)
51 16:10:00.433707 No compression specified
52 16:10:00.476066 progress 0 % (0 MB)
53 16:10:00.505813 progress 5 % (2 MB)
54 16:10:00.535932 progress 10 % (4 MB)
55 16:10:00.565753 progress 15 % (6 MB)
56 16:10:00.595778 progress 20 % (8 MB)
57 16:10:00.627450 progress 25 % (10 MB)
58 16:10:00.657191 progress 30 % (13 MB)
59 16:10:00.686842 progress 35 % (15 MB)
60 16:10:00.716365 progress 40 % (17 MB)
61 16:10:00.745730 progress 45 % (19 MB)
62 16:10:00.775151 progress 50 % (21 MB)
63 16:10:00.804449 progress 55 % (24 MB)
64 16:10:00.834459 progress 60 % (26 MB)
65 16:10:00.863677 progress 65 % (28 MB)
66 16:10:00.893147 progress 70 % (30 MB)
67 16:10:00.922587 progress 75 % (32 MB)
68 16:10:00.952187 progress 80 % (34 MB)
69 16:10:00.981424 progress 85 % (37 MB)
70 16:10:01.011036 progress 90 % (39 MB)
71 16:10:01.040926 progress 95 % (41 MB)
72 16:10:01.070180 progress 100 % (43 MB)
73 16:10:01.070719 43 MB downloaded in 0.64 s (68.42 MB/s)
74 16:10:01.071198 end: 1.2.1 http-download (duration 00:00:01) [common]
76 16:10:01.072033 end: 1.2 download-retry (duration 00:00:01) [common]
77 16:10:01.072320 start: 1.3 download-retry (timeout 00:09:59) [common]
78 16:10:01.072590 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 16:10:01.073044 downloading http://storage.kernelci.org/renesas/next/renesas-next-2024-11-11-v6.12-rc1/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 16:10:01.073317 saving as /var/lib/lava/dispatcher/tmp/975477/tftp-deploy-dmujxi_l/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 16:10:01.073528 total size: 53209 (0 MB)
82 16:10:01.073737 No compression specified
83 16:10:01.111050 progress 61 % (0 MB)
84 16:10:01.111911 progress 100 % (0 MB)
85 16:10:01.112496 0 MB downloaded in 0.04 s (1.30 MB/s)
86 16:10:01.112981 end: 1.3.1 http-download (duration 00:00:00) [common]
88 16:10:01.113789 end: 1.3 download-retry (duration 00:00:00) [common]
89 16:10:01.114050 start: 1.4 download-retry (timeout 00:09:59) [common]
90 16:10:01.114316 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 16:10:01.114770 downloading http://storage.kernelci.org/renesas/next/renesas-next-2024-11-11-v6.12-rc1/arm64/defconfig/gcc-12/modules.tar.xz
92 16:10:01.115012 saving as /var/lib/lava/dispatcher/tmp/975477/tftp-deploy-dmujxi_l/modules/modules.tar
93 16:10:01.115215 total size: 11608784 (11 MB)
94 16:10:01.115424 Using unxz to decompress xz
95 16:10:01.153776 progress 0 % (0 MB)
96 16:10:01.221440 progress 5 % (0 MB)
97 16:10:01.298100 progress 10 % (1 MB)
98 16:10:01.399765 progress 15 % (1 MB)
99 16:10:01.492978 progress 20 % (2 MB)
100 16:10:01.572568 progress 25 % (2 MB)
101 16:10:01.648813 progress 30 % (3 MB)
102 16:10:01.723210 progress 35 % (3 MB)
103 16:10:01.802086 progress 40 % (4 MB)
104 16:10:01.878495 progress 45 % (5 MB)
105 16:10:01.963586 progress 50 % (5 MB)
106 16:10:02.041408 progress 55 % (6 MB)
107 16:10:02.126988 progress 60 % (6 MB)
108 16:10:02.207534 progress 65 % (7 MB)
109 16:10:02.284304 progress 70 % (7 MB)
110 16:10:02.366819 progress 75 % (8 MB)
111 16:10:02.451026 progress 80 % (8 MB)
112 16:10:02.531340 progress 85 % (9 MB)
113 16:10:02.611224 progress 90 % (9 MB)
114 16:10:02.689320 progress 95 % (10 MB)
115 16:10:02.767802 progress 100 % (11 MB)
116 16:10:02.781379 11 MB downloaded in 1.67 s (6.64 MB/s)
117 16:10:02.782103 end: 1.4.1 http-download (duration 00:00:02) [common]
119 16:10:02.783728 end: 1.4 download-retry (duration 00:00:02) [common]
120 16:10:02.784323 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 16:10:02.784860 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 16:10:02.785369 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 16:10:02.785879 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 16:10:02.786879 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy
125 16:10:02.787764 makedir: /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin
126 16:10:02.788492 makedir: /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/tests
127 16:10:02.789145 makedir: /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/results
128 16:10:02.789785 Creating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin/lava-add-keys
129 16:10:02.790765 Creating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin/lava-add-sources
130 16:10:02.791729 Creating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin/lava-background-process-start
131 16:10:02.792750 Creating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin/lava-background-process-stop
132 16:10:02.793772 Creating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin/lava-common-functions
133 16:10:02.794728 Creating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin/lava-echo-ipv4
134 16:10:02.795676 Creating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin/lava-install-packages
135 16:10:02.796701 Creating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin/lava-installed-packages
136 16:10:02.797637 Creating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin/lava-os-build
137 16:10:02.798562 Creating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin/lava-probe-channel
138 16:10:02.799487 Creating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin/lava-probe-ip
139 16:10:02.800439 Creating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin/lava-target-ip
140 16:10:02.801372 Creating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin/lava-target-mac
141 16:10:02.802288 Creating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin/lava-target-storage
142 16:10:02.803245 Creating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin/lava-test-case
143 16:10:02.804222 Creating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin/lava-test-event
144 16:10:02.805148 Creating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin/lava-test-feedback
145 16:10:02.806073 Creating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin/lava-test-raise
146 16:10:02.806991 Creating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin/lava-test-reference
147 16:10:02.807918 Creating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin/lava-test-runner
148 16:10:02.808909 Creating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin/lava-test-set
149 16:10:02.809844 Creating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin/lava-test-shell
150 16:10:02.810817 Updating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin/lava-install-packages (oe)
151 16:10:02.811811 Updating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/bin/lava-installed-packages (oe)
152 16:10:02.812790 Creating /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/environment
153 16:10:02.813552 LAVA metadata
154 16:10:02.814071 - LAVA_JOB_ID=975477
155 16:10:02.814518 - LAVA_DISPATCHER_IP=192.168.6.2
156 16:10:02.815189 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 16:10:02.817043 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 16:10:02.817661 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 16:10:02.818097 skipped lava-vland-overlay
160 16:10:02.818600 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 16:10:02.819121 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 16:10:02.819561 skipped lava-multinode-overlay
163 16:10:02.820089 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 16:10:02.820620 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 16:10:02.821116 Loading test definitions
166 16:10:02.821680 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 16:10:02.822134 Using /lava-975477 at stage 0
168 16:10:02.824270 uuid=975477_1.5.2.4.1 testdef=None
169 16:10:02.824617 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 16:10:02.824917 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 16:10:02.826823 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 16:10:02.827675 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 16:10:02.830055 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 16:10:02.830973 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 16:10:02.833268 runner path: /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/0/tests/0_dmesg test_uuid 975477_1.5.2.4.1
178 16:10:02.833884 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 16:10:02.834716 Creating lava-test-runner.conf files
181 16:10:02.834938 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/975477/lava-overlay-ljrrmbiy/lava-975477/0 for stage 0
182 16:10:02.835318 - 0_dmesg
183 16:10:02.835755 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 16:10:02.836121 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 16:10:02.860504 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 16:10:02.860954 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 16:10:02.861273 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 16:10:02.861575 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 16:10:02.861872 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 16:10:03.906731 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 16:10:03.907203 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 16:10:03.907459 extracting modules file /var/lib/lava/dispatcher/tmp/975477/tftp-deploy-dmujxi_l/modules/modules.tar to /var/lib/lava/dispatcher/tmp/975477/extract-overlay-ramdisk-7zgq7zuj/ramdisk
193 16:10:05.276686 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 16:10:05.277200 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 16:10:05.277465 [common] Applying overlay /var/lib/lava/dispatcher/tmp/975477/compress-overlay-y7ep7w4x/overlay-1.5.2.5.tar.gz to ramdisk
196 16:10:05.277677 [common] Applying overlay /var/lib/lava/dispatcher/tmp/975477/compress-overlay-y7ep7w4x/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/975477/extract-overlay-ramdisk-7zgq7zuj/ramdisk
197 16:10:05.307695 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 16:10:05.308139 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 16:10:05.308416 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 16:10:05.308643 Converting downloaded kernel to a uImage
201 16:10:05.308948 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/975477/tftp-deploy-dmujxi_l/kernel/Image /var/lib/lava/dispatcher/tmp/975477/tftp-deploy-dmujxi_l/kernel/uImage
202 16:10:05.781712 output: Image Name:
203 16:10:05.782133 output: Created: Mon Nov 11 16:10:05 2024
204 16:10:05.782339 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 16:10:05.782543 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 16:10:05.782743 output: Load Address: 01080000
207 16:10:05.782941 output: Entry Point: 01080000
208 16:10:05.783137 output:
209 16:10:05.783470 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 16:10:05.783733 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 16:10:05.784037 start: 1.5.7 configure-preseed-file (timeout 00:09:54) [common]
212 16:10:05.784308 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 16:10:05.784568 start: 1.5.8 compress-ramdisk (timeout 00:09:54) [common]
214 16:10:05.784825 Building ramdisk /var/lib/lava/dispatcher/tmp/975477/extract-overlay-ramdisk-7zgq7zuj/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/975477/extract-overlay-ramdisk-7zgq7zuj/ramdisk
215 16:10:08.170990 >> 181566 blocks
216 16:10:16.679353 Adding RAMdisk u-boot header.
217 16:10:16.680248 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/975477/extract-overlay-ramdisk-7zgq7zuj/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/975477/extract-overlay-ramdisk-7zgq7zuj/ramdisk.cpio.gz.uboot
218 16:10:16.962463 output: Image Name:
219 16:10:16.962881 output: Created: Mon Nov 11 16:10:16 2024
220 16:10:16.963308 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 16:10:16.963728 output: Data Size: 26056217 Bytes = 25445.52 KiB = 24.85 MiB
222 16:10:16.964220 output: Load Address: 00000000
223 16:10:16.964633 output: Entry Point: 00000000
224 16:10:16.965034 output:
225 16:10:16.966246 rename /var/lib/lava/dispatcher/tmp/975477/extract-overlay-ramdisk-7zgq7zuj/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/975477/tftp-deploy-dmujxi_l/ramdisk/ramdisk.cpio.gz.uboot
226 16:10:16.966965 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 16:10:16.967516 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 16:10:16.968077 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 16:10:16.968547 No LXC device requested
230 16:10:16.969058 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 16:10:16.969573 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 16:10:16.970072 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 16:10:16.970491 Checking files for TFTP limit of 4294967296 bytes.
234 16:10:16.973158 end: 1 tftp-deploy (duration 00:00:17) [common]
235 16:10:16.973737 start: 2 uboot-action (timeout 00:05:00) [common]
236 16:10:16.974268 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 16:10:16.974771 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 16:10:16.975280 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 16:10:16.975816 Using kernel file from prepare-kernel: 975477/tftp-deploy-dmujxi_l/kernel/uImage
240 16:10:16.976478 substitutions:
241 16:10:16.976896 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 16:10:16.977299 - {DTB_ADDR}: 0x01070000
243 16:10:16.977699 - {DTB}: 975477/tftp-deploy-dmujxi_l/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 16:10:16.978101 - {INITRD}: 975477/tftp-deploy-dmujxi_l/ramdisk/ramdisk.cpio.gz.uboot
245 16:10:16.978499 - {KERNEL_ADDR}: 0x01080000
246 16:10:16.978893 - {KERNEL}: 975477/tftp-deploy-dmujxi_l/kernel/uImage
247 16:10:16.979288 - {LAVA_MAC}: None
248 16:10:16.979723 - {PRESEED_CONFIG}: None
249 16:10:16.980157 - {PRESEED_LOCAL}: None
250 16:10:16.980554 - {RAMDISK_ADDR}: 0x08000000
251 16:10:16.980944 - {RAMDISK}: 975477/tftp-deploy-dmujxi_l/ramdisk/ramdisk.cpio.gz.uboot
252 16:10:16.981340 - {ROOT_PART}: None
253 16:10:16.981735 - {ROOT}: None
254 16:10:16.982127 - {SERVER_IP}: 192.168.6.2
255 16:10:16.982521 - {TEE_ADDR}: 0x83000000
256 16:10:16.982910 - {TEE}: None
257 16:10:16.983301 Parsed boot commands:
258 16:10:16.983680 - setenv autoload no
259 16:10:16.984095 - setenv initrd_high 0xffffffff
260 16:10:16.984490 - setenv fdt_high 0xffffffff
261 16:10:16.984880 - dhcp
262 16:10:16.985371 - setenv serverip 192.168.6.2
263 16:10:16.985808 - tftpboot 0x01080000 975477/tftp-deploy-dmujxi_l/kernel/uImage
264 16:10:16.986211 - tftpboot 0x08000000 975477/tftp-deploy-dmujxi_l/ramdisk/ramdisk.cpio.gz.uboot
265 16:10:16.986607 - tftpboot 0x01070000 975477/tftp-deploy-dmujxi_l/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 16:10:16.987001 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 16:10:16.987403 - bootm 0x01080000 0x08000000 0x01070000
268 16:10:16.987918 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 16:10:16.989454 start: 2.3 connect-device (timeout 00:05:00) [common]
271 16:10:16.989911 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 16:10:17.004749 Setting prompt string to ['lava-test: # ']
273 16:10:17.006267 end: 2.3 connect-device (duration 00:00:00) [common]
274 16:10:17.006898 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 16:10:17.007469 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 16:10:17.008047 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 16:10:17.009234 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 16:10:17.047371 >> OK - accepted request
279 16:10:17.049924 Returned 0 in 0 seconds
280 16:10:17.151041 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 16:10:17.152769 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 16:10:17.153365 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 16:10:17.153880 Setting prompt string to ['Hit any key to stop autoboot']
285 16:10:17.154343 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 16:10:17.155936 Trying 192.168.56.21...
287 16:10:17.156456 Connected to conserv1.
288 16:10:17.156874 Escape character is '^]'.
289 16:10:17.157306
290 16:10:17.157736 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 16:10:17.158182
292 16:10:24.953580 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 16:10:24.954191 bl2_stage_init 0x01
294 16:10:24.954642 bl2_stage_init 0x81
295 16:10:24.958967 hw id: 0x0000 - pwm id 0x01
296 16:10:24.959432 bl2_stage_init 0xc1
297 16:10:24.959841 bl2_stage_init 0x02
298 16:10:24.960310
299 16:10:24.964548 L0:00000000
300 16:10:24.964980 L1:00000703
301 16:10:24.965387 L2:00008067
302 16:10:24.965789 L3:15000000
303 16:10:24.966188 S1:00000000
304 16:10:24.970234 B2:20282000
305 16:10:24.970664 B1:a0f83180
306 16:10:24.971064
307 16:10:24.971463 TE: 70579
308 16:10:24.971859
309 16:10:24.975736 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 16:10:24.976204
311 16:10:24.981472 Board ID = 1
312 16:10:24.981900 Set cpu clk to 24M
313 16:10:24.982294 Set clk81 to 24M
314 16:10:24.986934 Use GP1_pll as DSU clk.
315 16:10:24.987368 DSU clk: 1200 Mhz
316 16:10:24.987769 CPU clk: 1200 MHz
317 16:10:24.988203 Set clk81 to 166.6M
318 16:10:24.998120 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 16:10:24.998552 board id: 1
320 16:10:25.004549 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 16:10:25.015512 fw parse done
322 16:10:25.021620 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 16:10:25.064653 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 16:10:25.075719 PIEI prepare done
325 16:10:25.076197 fastboot data load
326 16:10:25.076603 fastboot data verify
327 16:10:25.081334 verify result: 266
328 16:10:25.086935 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 16:10:25.087383 LPDDR4 probe
330 16:10:25.087789 ddr clk to 1584MHz
331 16:10:25.094963 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 16:10:25.132673
333 16:10:25.133148 dmc_version 0001
334 16:10:25.139661 Check phy result
335 16:10:25.145643 INFO : End of CA training
336 16:10:25.146072 INFO : End of initialization
337 16:10:25.151310 INFO : Training has run successfully!
338 16:10:25.151732 Check phy result
339 16:10:25.156880 INFO : End of initialization
340 16:10:25.157327 INFO : End of read enable training
341 16:10:25.160219 INFO : End of fine write leveling
342 16:10:25.165778 INFO : End of Write leveling coarse delay
343 16:10:25.171314 INFO : Training has run successfully!
344 16:10:25.171729 Check phy result
345 16:10:25.172162 INFO : End of initialization
346 16:10:25.176885 INFO : End of read dq deskew training
347 16:10:25.182573 INFO : End of MPR read delay center optimization
348 16:10:25.183013 INFO : End of write delay center optimization
349 16:10:25.188103 INFO : End of read delay center optimization
350 16:10:25.193696 INFO : End of max read latency training
351 16:10:25.194113 INFO : Training has run successfully!
352 16:10:25.199314 1D training succeed
353 16:10:25.205240 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 16:10:25.253583 Check phy result
355 16:10:25.254006 INFO : End of initialization
356 16:10:25.280873 INFO : End of 2D read delay Voltage center optimization
357 16:10:25.305136 INFO : End of 2D read delay Voltage center optimization
358 16:10:25.361972 INFO : End of 2D write delay Voltage center optimization
359 16:10:25.415872 INFO : End of 2D write delay Voltage center optimization
360 16:10:25.421354 INFO : Training has run successfully!
361 16:10:25.421786
362 16:10:25.422191 channel==0
363 16:10:25.426956 RxClkDly_Margin_A0==78 ps 8
364 16:10:25.427378 TxDqDly_Margin_A0==98 ps 10
365 16:10:25.432614 RxClkDly_Margin_A1==88 ps 9
366 16:10:25.433049 TxDqDly_Margin_A1==88 ps 9
367 16:10:25.433455 TrainedVREFDQ_A0==74
368 16:10:25.438143 TrainedVREFDQ_A1==74
369 16:10:25.438577 VrefDac_Margin_A0==24
370 16:10:25.438975 DeviceVref_Margin_A0==40
371 16:10:25.443755 VrefDac_Margin_A1==23
372 16:10:25.444238 DeviceVref_Margin_A1==40
373 16:10:25.444666
374 16:10:25.445075
375 16:10:25.445473 channel==1
376 16:10:25.449349 RxClkDly_Margin_A0==88 ps 9
377 16:10:25.449775 TxDqDly_Margin_A0==88 ps 9
378 16:10:25.454957 RxClkDly_Margin_A1==78 ps 8
379 16:10:25.455377 TxDqDly_Margin_A1==78 ps 8
380 16:10:25.460601 TrainedVREFDQ_A0==75
381 16:10:25.461027 TrainedVREFDQ_A1==75
382 16:10:25.461425 VrefDac_Margin_A0==21
383 16:10:25.466148 DeviceVref_Margin_A0==39
384 16:10:25.466571 VrefDac_Margin_A1==22
385 16:10:25.466967 DeviceVref_Margin_A1==39
386 16:10:25.471743
387 16:10:25.472203 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 16:10:25.472604
389 16:10:25.505376 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000016 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000017 dram_vref_reg_value 0x 00000062
390 16:10:25.505988 2D training succeed
391 16:10:25.510947 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 16:10:25.516604 auto size-- 65535DDR cs0 size: 2048MB
393 16:10:25.517045 DDR cs1 size: 2048MB
394 16:10:25.522109 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 16:10:25.522547 cs0 DataBus test pass
396 16:10:25.527774 cs1 DataBus test pass
397 16:10:25.528275 cs0 AddrBus test pass
398 16:10:25.528687 cs1 AddrBus test pass
399 16:10:25.529091
400 16:10:25.533286 100bdlr_step_size ps== 471
401 16:10:25.533732 result report
402 16:10:25.538959 boot times 0Enable ddr reg access
403 16:10:25.544050 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 16:10:25.556998 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 16:10:26.216728 bl2z: ptr: 05129330, size: 00001e40
406 16:10:26.226298 0.0;M3 CHK:0;cm4_sp_mode 0
407 16:10:26.226766 MVN_1=0x00000000
408 16:10:26.227182 MVN_2=0x00000000
409 16:10:26.237767 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 16:10:26.238221 OPS=0x04
411 16:10:26.238632 ring efuse init
412 16:10:26.243472 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 16:10:26.243917 [0.017354 Inits done]
414 16:10:26.244366 secure task start!
415 16:10:26.251446 high task start!
416 16:10:26.251879 low task start!
417 16:10:26.252318 run into bl31
418 16:10:26.260085 NOTICE: BL31: v1.3(release):4fc40b1
419 16:10:26.267874 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 16:10:26.268355 NOTICE: BL31: G12A normal boot!
421 16:10:26.283473 NOTICE: BL31: BL33 decompress pass
422 16:10:26.289177 ERROR: Error initializing runtime service opteed_fast
423 16:10:29.005208 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 16:10:29.005849 bl2_stage_init 0x01
425 16:10:29.006324 bl2_stage_init 0x81
426 16:10:29.010659 hw id: 0x0000 - pwm id 0x01
427 16:10:29.011179 bl2_stage_init 0xc1
428 16:10:29.016340 bl2_stage_init 0x02
429 16:10:29.016889
430 16:10:29.017332 L0:00000000
431 16:10:29.017765 L1:00000703
432 16:10:29.018195 L2:00008067
433 16:10:29.018621 L3:15000000
434 16:10:29.021949 S1:00000000
435 16:10:29.022423 B2:20282000
436 16:10:29.022854 B1:a0f83180
437 16:10:29.023280
438 16:10:29.023708 TE: 71844
439 16:10:29.024177
440 16:10:29.027475 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 16:10:29.027938
442 16:10:29.033215 Board ID = 1
443 16:10:29.033675 Set cpu clk to 24M
444 16:10:29.034101 Set clk81 to 24M
445 16:10:29.038594 Use GP1_pll as DSU clk.
446 16:10:29.039064 DSU clk: 1200 Mhz
447 16:10:29.039492 CPU clk: 1200 MHz
448 16:10:29.044254 Set clk81 to 166.6M
449 16:10:29.049854 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 16:10:29.050319 board id: 1
451 16:10:29.057081 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 16:10:29.068165 fw parse done
453 16:10:29.073112 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 16:10:29.116977 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 16:10:29.128195 PIEI prepare done
456 16:10:29.128739 fastboot data load
457 16:10:29.129178 fastboot data verify
458 16:10:29.133655 verify result: 266
459 16:10:29.139339 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 16:10:29.139805 LPDDR4 probe
461 16:10:29.140285 ddr clk to 1584MHz
462 16:10:29.147288 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 16:10:29.185024
464 16:10:29.185541 dmc_version 0001
465 16:10:29.192067 Check phy result
466 16:10:29.198153 INFO : End of CA training
467 16:10:29.198654 INFO : End of initialization
468 16:10:29.203631 INFO : Training has run successfully!
469 16:10:29.204143 Check phy result
470 16:10:29.209305 INFO : End of initialization
471 16:10:29.209784 INFO : End of read enable training
472 16:10:29.212527 INFO : End of fine write leveling
473 16:10:29.218163 INFO : End of Write leveling coarse delay
474 16:10:29.223718 INFO : Training has run successfully!
475 16:10:29.224213 Check phy result
476 16:10:29.224656 INFO : End of initialization
477 16:10:29.229269 INFO : End of read dq deskew training
478 16:10:29.235006 INFO : End of MPR read delay center optimization
479 16:10:29.235474 INFO : End of write delay center optimization
480 16:10:29.240529 INFO : End of read delay center optimization
481 16:10:29.246528 INFO : End of max read latency training
482 16:10:29.246835 INFO : Training has run successfully!
483 16:10:29.251673 1D training succeed
484 16:10:29.256702 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 16:10:29.308454 Check phy result
486 16:10:29.309061 INFO : End of initialization
487 16:10:29.333342 INFO : End of 2D read delay Voltage center optimization
488 16:10:29.357801 INFO : End of 2D read delay Voltage center optimization
489 16:10:29.414204 INFO : End of 2D write delay Voltage center optimization
490 16:10:29.468133 INFO : End of 2D write delay Voltage center optimization
491 16:10:29.473632 INFO : Training has run successfully!
492 16:10:29.474120
493 16:10:29.474573 channel==0
494 16:10:29.479193 RxClkDly_Margin_A0==78 ps 8
495 16:10:29.479675 TxDqDly_Margin_A0==98 ps 10
496 16:10:29.482505 RxClkDly_Margin_A1==88 ps 9
497 16:10:29.482977 TxDqDly_Margin_A1==98 ps 10
498 16:10:29.488058 TrainedVREFDQ_A0==74
499 16:10:29.488545 TrainedVREFDQ_A1==75
500 16:10:29.493641 VrefDac_Margin_A0==23
501 16:10:29.494114 DeviceVref_Margin_A0==40
502 16:10:29.494560 VrefDac_Margin_A1==22
503 16:10:29.499202 DeviceVref_Margin_A1==39
504 16:10:29.499685
505 16:10:29.500168
506 16:10:29.500611 channel==1
507 16:10:29.501045 RxClkDly_Margin_A0==78 ps 8
508 16:10:29.504785 TxDqDly_Margin_A0==98 ps 10
509 16:10:29.505262 RxClkDly_Margin_A1==88 ps 9
510 16:10:29.510362 TxDqDly_Margin_A1==88 ps 9
511 16:10:29.510843 TrainedVREFDQ_A0==78
512 16:10:29.511287 TrainedVREFDQ_A1==75
513 16:10:29.516021 VrefDac_Margin_A0==23
514 16:10:29.516500 DeviceVref_Margin_A0==36
515 16:10:29.521586 VrefDac_Margin_A1==20
516 16:10:29.522057 DeviceVref_Margin_A1==39
517 16:10:29.522501
518 16:10:29.527253 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 16:10:29.527752
520 16:10:29.555261 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000018 00000019 00000018 00000019 00000015 00000018 00000015 00000015 00000017 00000018 0000001a 00000018 00000018 0000001c 00000018 00000016 00000016 dram_vref_reg_value 0x 00000061
521 16:10:29.560945 2D training succeed
522 16:10:29.566395 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 16:10:29.566933 auto size-- 65535DDR cs0 size: 2048MB
524 16:10:29.572016 DDR cs1 size: 2048MB
525 16:10:29.572510 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 16:10:29.577551 cs0 DataBus test pass
527 16:10:29.578024 cs1 DataBus test pass
528 16:10:29.578475 cs0 AddrBus test pass
529 16:10:29.583166 cs1 AddrBus test pass
530 16:10:29.583636
531 16:10:29.584136 100bdlr_step_size ps== 471
532 16:10:29.584604 result report
533 16:10:29.588769 boot times 0Enable ddr reg access
534 16:10:29.596427 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 16:10:29.610244 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 16:10:30.271861 bl2z: ptr: 05129330, size: 00001e40
537 16:10:30.277749 0.0;M3 CHK:0;cm4_sp_mode 0
538 16:10:30.278043 MVN_1=0x00000000
539 16:10:30.278263 MVN_2=0x00000000
540 16:10:30.288412 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 16:10:30.288716 OPS=0x04
542 16:10:30.288933 ring efuse init
543 16:10:30.291295 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 16:10:30.297473 [0.017354 Inits done]
545 16:10:30.297746 secure task start!
546 16:10:30.297961 high task start!
547 16:10:30.298184 low task start!
548 16:10:30.301752 run into bl31
549 16:10:30.310396 NOTICE: BL31: v1.3(release):4fc40b1
550 16:10:30.318270 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 16:10:30.318579 NOTICE: BL31: G12A normal boot!
552 16:10:30.333770 NOTICE: BL31: BL33 decompress pass
553 16:10:30.339447 ERROR: Error initializing runtime service opteed_fast
554 16:10:31.703935 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 16:10:31.704356 bl2_stage_init 0x01
556 16:10:31.704569 bl2_stage_init 0x81
557 16:10:31.709515 hw id: 0x0000 - pwm id 0x01
558 16:10:31.709930 bl2_stage_init 0xc1
559 16:10:31.714414 bl2_stage_init 0x02
560 16:10:31.714828
561 16:10:31.715141 L0:00000000
562 16:10:31.715367 L1:00000703
563 16:10:31.715578 L2:00008067
564 16:10:31.720037 L3:15000000
565 16:10:31.720447 S1:00000000
566 16:10:31.720752 B2:20282000
567 16:10:31.721050 B1:a0f83180
568 16:10:31.721346
569 16:10:31.721643 TE: 71956
570 16:10:31.721863
571 16:10:31.731274 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 16:10:31.731622
573 16:10:31.731857 Board ID = 1
574 16:10:31.732115 Set cpu clk to 24M
575 16:10:31.732533 Set clk81 to 24M
576 16:10:31.736806 Use GP1_pll as DSU clk.
577 16:10:31.737296 DSU clk: 1200 Mhz
578 16:10:31.737743 CPU clk: 1200 MHz
579 16:10:31.742414 Set clk81 to 166.6M
580 16:10:31.748052 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 16:10:31.748549 board id: 1
582 16:10:31.755913 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 16:10:31.766818 fw parse done
584 16:10:31.772774 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 16:10:31.815919 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 16:10:31.827005 PIEI prepare done
587 16:10:31.827521 fastboot data load
588 16:10:31.828010 fastboot data verify
589 16:10:31.832671 verify result: 266
590 16:10:31.838343 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 16:10:31.838831 LPDDR4 probe
592 16:10:31.839278 ddr clk to 1584MHz
593 16:10:31.846246 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 16:10:31.884001
595 16:10:31.884543 dmc_version 0001
596 16:10:31.891018 Check phy result
597 16:10:31.897005 INFO : End of CA training
598 16:10:31.897496 INFO : End of initialization
599 16:10:31.902613 INFO : Training has run successfully!
600 16:10:31.903110 Check phy result
601 16:10:31.908247 INFO : End of initialization
602 16:10:31.908732 INFO : End of read enable training
603 16:10:31.913808 INFO : End of fine write leveling
604 16:10:31.919402 INFO : End of Write leveling coarse delay
605 16:10:31.919886 INFO : Training has run successfully!
606 16:10:31.920379 Check phy result
607 16:10:31.924979 INFO : End of initialization
608 16:10:31.925457 INFO : End of read dq deskew training
609 16:10:31.930608 INFO : End of MPR read delay center optimization
610 16:10:31.936236 INFO : End of write delay center optimization
611 16:10:31.941786 INFO : End of read delay center optimization
612 16:10:31.942290 INFO : End of max read latency training
613 16:10:31.947428 INFO : Training has run successfully!
614 16:10:31.947924 1D training succeed
615 16:10:31.956608 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 16:10:32.004883 Check phy result
617 16:10:32.005423 INFO : End of initialization
618 16:10:32.032267 INFO : End of 2D read delay Voltage center optimization
619 16:10:32.056477 INFO : End of 2D read delay Voltage center optimization
620 16:10:32.113137 INFO : End of 2D write delay Voltage center optimization
621 16:10:32.167219 INFO : End of 2D write delay Voltage center optimization
622 16:10:32.172683 INFO : Training has run successfully!
623 16:10:32.173174
624 16:10:32.173637 channel==0
625 16:10:32.178406 RxClkDly_Margin_A0==88 ps 9
626 16:10:32.178922 TxDqDly_Margin_A0==98 ps 10
627 16:10:32.183885 RxClkDly_Margin_A1==88 ps 9
628 16:10:32.184405 TxDqDly_Margin_A1==88 ps 9
629 16:10:32.184860 TrainedVREFDQ_A0==74
630 16:10:32.189468 TrainedVREFDQ_A1==74
631 16:10:32.189946 VrefDac_Margin_A0==24
632 16:10:32.190387 DeviceVref_Margin_A0==40
633 16:10:32.195100 VrefDac_Margin_A1==23
634 16:10:32.195574 DeviceVref_Margin_A1==40
635 16:10:32.196045
636 16:10:32.196493
637 16:10:32.196933 channel==1
638 16:10:32.200669 RxClkDly_Margin_A0==78 ps 8
639 16:10:32.201153 TxDqDly_Margin_A0==98 ps 10
640 16:10:32.206244 RxClkDly_Margin_A1==88 ps 9
641 16:10:32.206726 TxDqDly_Margin_A1==88 ps 9
642 16:10:32.211917 TrainedVREFDQ_A0==78
643 16:10:32.212444 TrainedVREFDQ_A1==78
644 16:10:32.212894 VrefDac_Margin_A0==22
645 16:10:32.217473 DeviceVref_Margin_A0==36
646 16:10:32.217951 VrefDac_Margin_A1==22
647 16:10:32.223081 DeviceVref_Margin_A1==36
648 16:10:32.223562
649 16:10:32.224039 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 16:10:32.224486
651 16:10:32.256693 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000016 00000018 00000019 00000017 00000018 0000001b 00000017 00000015 00000016 dram_vref_reg_value 0x 00000062
652 16:10:32.257237 2D training succeed
653 16:10:32.262276 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 16:10:32.267846 auto size-- 65535DDR cs0 size: 2048MB
655 16:10:32.268369 DDR cs1 size: 2048MB
656 16:10:32.273485 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 16:10:32.273960 cs0 DataBus test pass
658 16:10:32.279093 cs1 DataBus test pass
659 16:10:32.279593 cs0 AddrBus test pass
660 16:10:32.280070 cs1 AddrBus test pass
661 16:10:32.280517
662 16:10:32.284670 100bdlr_step_size ps== 471
663 16:10:32.285152 result report
664 16:10:32.290268 boot times 0Enable ddr reg access
665 16:10:32.295506 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 16:10:32.309309 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 16:10:32.969395 bl2z: ptr: 05129330, size: 00001e40
668 16:10:32.976775 0.0;M3 CHK:0;cm4_sp_mode 0
669 16:10:32.977347 MVN_1=0x00000000
670 16:10:32.977819 MVN_2=0x00000000
671 16:10:32.988332 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 16:10:32.988893 OPS=0x04
673 16:10:32.989400 ring efuse init
674 16:10:32.991244 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 16:10:32.997658 [0.017354 Inits done]
676 16:10:32.998566 secure task start!
677 16:10:32.999845 high task start!
678 16:10:33.000372 low task start!
679 16:10:33.002242 run into bl31
680 16:10:33.010834 NOTICE: BL31: v1.3(release):4fc40b1
681 16:10:33.018437 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 16:10:33.019514 NOTICE: BL31: G12A normal boot!
683 16:10:33.034092 NOTICE: BL31: BL33 decompress pass
684 16:10:33.039777 ERROR: Error initializing runtime service opteed_fast
685 16:10:33.835056
686 16:10:33.835729
687 16:10:33.840534 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 16:10:33.841574
689 16:10:33.844155 Model: Libre Computer AML-S905D3-CC Solitude
690 16:10:33.991121 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 16:10:34.006750 DRAM: 2 GiB (effective 3.8 GiB)
692 16:10:34.107899 Core: 406 devices, 33 uclasses, devicetree: separate
693 16:10:34.113431 WDT: Not starting watchdog@f0d0
694 16:10:34.138323 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 16:10:34.151039 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 16:10:34.155813 ** Bad device specification mmc 0 **
697 16:10:34.165685 Card did not respond to voltage select! : -110
698 16:10:34.174132 ** Bad device specification mmc 0 **
699 16:10:34.175101 Couldn't find partition mmc 0
700 16:10:34.183216 Card did not respond to voltage select! : -110
701 16:10:34.187531 ** Bad device specification mmc 0 **
702 16:10:34.188714 Couldn't find partition mmc 0
703 16:10:34.192649 Error: could not access storage.
704 16:10:34.488963 Net: eth0: ethernet@ff3f0000
705 16:10:34.489388 starting USB...
706 16:10:34.733370 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 16:10:34.734125 Starting the controller
708 16:10:34.740412 USB XHCI 1.10
709 16:10:36.296521 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 16:10:36.304778 scanning usb for storage devices... 0 Storage Device(s) found
712 16:10:36.356465 Hit any key to stop autoboot: 1
713 16:10:36.357404 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 16:10:36.358077 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 16:10:36.358606 Setting prompt string to ['=>']
716 16:10:36.359142 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 16:10:36.370833 0
718 16:10:36.372017 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 16:10:36.473484 => setenv autoload no
721 16:10:36.474229 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
722 16:10:36.477770 setenv autoload no
724 16:10:36.578919 => setenv initrd_high 0xffffffff
725 16:10:36.579965 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
726 16:10:36.584141 setenv initrd_high 0xffffffff
728 16:10:36.685508 => setenv fdt_high 0xffffffff
729 16:10:36.686870 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
730 16:10:36.690938 setenv fdt_high 0xffffffff
732 16:10:36.792376 => dhcp
733 16:10:36.792969 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
734 16:10:36.797290 dhcp
735 16:10:38.003319 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete... done
736 16:10:38.003881 Speed: 1000, full duplex
737 16:10:38.004312 BOOTP broadcast 1
738 16:10:38.012057 DHCP client bound to address 192.168.6.21 (8 ms)
740 16:10:38.113134 => setenv serverip 192.168.6.2
741 16:10:38.113882 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
742 16:10:38.118370 setenv serverip 192.168.6.2
744 16:10:38.219624 => tftpboot 0x01080000 975477/tftp-deploy-dmujxi_l/kernel/uImage
745 16:10:38.220373 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
746 16:10:38.227035 tftpboot 0x01080000 975477/tftp-deploy-dmujxi_l/kernel/uImage
747 16:10:38.227420 Speed: 1000, full duplex
748 16:10:38.227662 Using ethernet@ff3f0000 device
749 16:10:38.232496 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
750 16:10:38.237978 Filename '975477/tftp-deploy-dmujxi_l/kernel/uImage'.
751 16:10:38.241826 Load address: 0x1080000
752 16:10:41.007603 Loading: *################################################## 43.6 MiB
753 16:10:41.008289 15.7 MiB/s
754 16:10:41.008740 done
755 16:10:41.011968 Bytes transferred = 45713984 (2b98a40 hex)
757 16:10:41.113495 => tftpboot 0x08000000 975477/tftp-deploy-dmujxi_l/ramdisk/ramdisk.cpio.gz.uboot
758 16:10:41.114111 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
759 16:10:41.120840 tftpboot 0x08000000 975477/tftp-deploy-dmujxi_l/ramdisk/ramdisk.cpio.gz.uboot
760 16:10:41.121320 Speed: 1000, full duplex
761 16:10:41.121752 Using ethernet@ff3f0000 device
762 16:10:41.126264 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
763 16:10:41.136146 Filename '975477/tftp-deploy-dmujxi_l/ramdisk/ramdisk.cpio.gz.uboot'.
764 16:10:41.136694 Load address: 0x8000000
765 16:10:42.771652 Loading: *################################################# UDP wrong checksum 00000005 0000e834
766 16:10:47.772953 T UDP wrong checksum 00000005 0000e834
767 16:10:57.774875 T T UDP wrong checksum 00000005 0000e834
768 16:11:13.558841 T T T UDP wrong checksum 000000ff 000058e0
769 16:11:13.596982 UDP wrong checksum 000000ff 0000f2d2
770 16:11:17.779268 T UDP wrong checksum 00000005 0000e834
771 16:11:37.783781 T T T
772 16:11:37.784505 Retry count exceeded; starting again
774 16:11:37.786078 end: 2.4.3 bootloader-commands (duration 00:01:01) [common]
777 16:11:37.788184 end: 2.4 uboot-commands (duration 00:01:21) [common]
779 16:11:37.790439 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
781 16:11:37.791625 end: 2 uboot-action (duration 00:01:21) [common]
783 16:11:37.793354 Cleaning after the job
784 16:11:37.793965 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975477/tftp-deploy-dmujxi_l/ramdisk
785 16:11:37.795408 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975477/tftp-deploy-dmujxi_l/kernel
786 16:11:37.826793 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975477/tftp-deploy-dmujxi_l/dtb
787 16:11:37.828380 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975477/tftp-deploy-dmujxi_l/modules
788 16:11:37.835041 start: 4.1 power-off (timeout 00:00:30) [common]
789 16:11:37.836215 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
790 16:11:37.876048 >> OK - accepted request
791 16:11:37.878064 Returned 0 in 0 seconds
792 16:11:37.979310 end: 4.1 power-off (duration 00:00:00) [common]
794 16:11:37.981223 start: 4.2 read-feedback (timeout 00:10:00) [common]
795 16:11:37.982437 Listened to connection for namespace 'common' for up to 1s
796 16:11:38.983265 Finalising connection for namespace 'common'
797 16:11:38.984113 Disconnecting from shell: Finalise
798 16:11:38.984705 =>
799 16:11:39.085902 end: 4.2 read-feedback (duration 00:00:01) [common]
800 16:11:39.086690 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/975477
801 16:11:39.348819 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/975477
802 16:11:39.349435 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.