Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 16:49:40.775616 lava-dispatcher, installed at version: 2024.01
2 16:49:40.776508 start: 0 validate
3 16:49:40.777037 Start time: 2024-11-11 16:49:40.777003+00:00 (UTC)
4 16:49:40.777766 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 16:49:40.778386 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 16:49:40.828816 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 16:49:40.829379 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fnext%2Frenesas-next-2024-11-11-v6.12-rc1%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 16:49:40.858902 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 16:49:40.859617 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fnext%2Frenesas-next-2024-11-11-v6.12-rc1%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 16:49:40.894214 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 16:49:40.894765 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 16:49:40.930164 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 16:49:40.930658 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fnext%2Frenesas-next-2024-11-11-v6.12-rc1%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 16:49:40.966610 validate duration: 0.19
16 16:49:40.967473 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 16:49:40.967798 start: 1.1 download-retry (timeout 00:10:00) [common]
18 16:49:40.968138 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 16:49:40.968743 Not decompressing ramdisk as can be used compressed.
20 16:49:40.969197 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 16:49:40.969482 saving as /var/lib/lava/dispatcher/tmp/975418/tftp-deploy-967p0fyb/ramdisk/initrd.cpio.gz
22 16:49:40.969762 total size: 5628169 (5 MB)
23 16:49:41.015372 progress 0 % (0 MB)
24 16:49:41.020031 progress 5 % (0 MB)
25 16:49:41.026141 progress 10 % (0 MB)
26 16:49:41.031427 progress 15 % (0 MB)
27 16:49:41.037070 progress 20 % (1 MB)
28 16:49:41.041983 progress 25 % (1 MB)
29 16:49:41.047209 progress 30 % (1 MB)
30 16:49:41.052786 progress 35 % (1 MB)
31 16:49:41.057883 progress 40 % (2 MB)
32 16:49:41.062921 progress 45 % (2 MB)
33 16:49:41.067368 progress 50 % (2 MB)
34 16:49:41.072413 progress 55 % (2 MB)
35 16:49:41.077440 progress 60 % (3 MB)
36 16:49:41.081840 progress 65 % (3 MB)
37 16:49:41.086663 progress 70 % (3 MB)
38 16:49:41.091037 progress 75 % (4 MB)
39 16:49:41.095918 progress 80 % (4 MB)
40 16:49:41.100342 progress 85 % (4 MB)
41 16:49:41.105126 progress 90 % (4 MB)
42 16:49:41.109588 progress 95 % (5 MB)
43 16:49:41.113577 progress 100 % (5 MB)
44 16:49:41.114403 5 MB downloaded in 0.14 s (37.12 MB/s)
45 16:49:41.115074 end: 1.1.1 http-download (duration 00:00:00) [common]
47 16:49:41.116228 end: 1.1 download-retry (duration 00:00:00) [common]
48 16:49:41.116595 start: 1.2 download-retry (timeout 00:10:00) [common]
49 16:49:41.116932 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 16:49:41.117519 downloading http://storage.kernelci.org/renesas/next/renesas-next-2024-11-11-v6.12-rc1/arm64/defconfig/gcc-12/kernel/Image
51 16:49:41.117834 saving as /var/lib/lava/dispatcher/tmp/975418/tftp-deploy-967p0fyb/kernel/Image
52 16:49:41.118090 total size: 45713920 (43 MB)
53 16:49:41.118346 No compression specified
54 16:49:41.157801 progress 0 % (0 MB)
55 16:49:41.187976 progress 5 % (2 MB)
56 16:49:41.220714 progress 10 % (4 MB)
57 16:49:41.249557 progress 15 % (6 MB)
58 16:49:41.278651 progress 20 % (8 MB)
59 16:49:41.308011 progress 25 % (10 MB)
60 16:49:41.339770 progress 30 % (13 MB)
61 16:49:41.372130 progress 35 % (15 MB)
62 16:49:41.401872 progress 40 % (17 MB)
63 16:49:41.430189 progress 45 % (19 MB)
64 16:49:41.458782 progress 50 % (21 MB)
65 16:49:41.487430 progress 55 % (24 MB)
66 16:49:41.516742 progress 60 % (26 MB)
67 16:49:41.544919 progress 65 % (28 MB)
68 16:49:41.573564 progress 70 % (30 MB)
69 16:49:41.602330 progress 75 % (32 MB)
70 16:49:41.630518 progress 80 % (34 MB)
71 16:49:41.658798 progress 85 % (37 MB)
72 16:49:41.687413 progress 90 % (39 MB)
73 16:49:41.716419 progress 95 % (41 MB)
74 16:49:41.744173 progress 100 % (43 MB)
75 16:49:41.744720 43 MB downloaded in 0.63 s (69.57 MB/s)
76 16:49:41.745196 end: 1.2.1 http-download (duration 00:00:01) [common]
78 16:49:41.746012 end: 1.2 download-retry (duration 00:00:01) [common]
79 16:49:41.746285 start: 1.3 download-retry (timeout 00:09:59) [common]
80 16:49:41.746549 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 16:49:41.747016 downloading http://storage.kernelci.org/renesas/next/renesas-next-2024-11-11-v6.12-rc1/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 16:49:41.747290 saving as /var/lib/lava/dispatcher/tmp/975418/tftp-deploy-967p0fyb/dtb/meson-g12b-a311d-libretech-cc.dtb
83 16:49:41.747498 total size: 54703 (0 MB)
84 16:49:41.747706 No compression specified
85 16:49:41.790837 progress 59 % (0 MB)
86 16:49:41.791725 progress 100 % (0 MB)
87 16:49:41.792320 0 MB downloaded in 0.04 s (1.16 MB/s)
88 16:49:41.792828 end: 1.3.1 http-download (duration 00:00:00) [common]
90 16:49:41.793657 end: 1.3 download-retry (duration 00:00:00) [common]
91 16:49:41.793924 start: 1.4 download-retry (timeout 00:09:59) [common]
92 16:49:41.794188 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 16:49:41.794658 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 16:49:41.794904 saving as /var/lib/lava/dispatcher/tmp/975418/tftp-deploy-967p0fyb/nfsrootfs/full.rootfs.tar
95 16:49:41.795111 total size: 120894716 (115 MB)
96 16:49:41.795320 Using unxz to decompress xz
97 16:49:41.828966 progress 0 % (0 MB)
98 16:49:42.768115 progress 5 % (5 MB)
99 16:49:43.669608 progress 10 % (11 MB)
100 16:49:44.615767 progress 15 % (17 MB)
101 16:49:45.488372 progress 20 % (23 MB)
102 16:49:46.186382 progress 25 % (28 MB)
103 16:49:47.162105 progress 30 % (34 MB)
104 16:49:48.099920 progress 35 % (40 MB)
105 16:49:48.498104 progress 40 % (46 MB)
106 16:49:48.880897 progress 45 % (51 MB)
107 16:49:49.607035 progress 50 % (57 MB)
108 16:49:50.496081 progress 55 % (63 MB)
109 16:49:51.283890 progress 60 % (69 MB)
110 16:49:52.044663 progress 65 % (74 MB)
111 16:49:52.822630 progress 70 % (80 MB)
112 16:49:53.647647 progress 75 % (86 MB)
113 16:49:54.442470 progress 80 % (92 MB)
114 16:49:55.208436 progress 85 % (98 MB)
115 16:49:56.068385 progress 90 % (103 MB)
116 16:49:56.848827 progress 95 % (109 MB)
117 16:49:57.690567 progress 100 % (115 MB)
118 16:49:57.704500 115 MB downloaded in 15.91 s (7.25 MB/s)
119 16:49:57.705128 end: 1.4.1 http-download (duration 00:00:16) [common]
121 16:49:57.705953 end: 1.4 download-retry (duration 00:00:16) [common]
122 16:49:57.706218 start: 1.5 download-retry (timeout 00:09:43) [common]
123 16:49:57.706480 start: 1.5.1 http-download (timeout 00:09:43) [common]
124 16:49:57.706942 downloading http://storage.kernelci.org/renesas/next/renesas-next-2024-11-11-v6.12-rc1/arm64/defconfig/gcc-12/modules.tar.xz
125 16:49:57.707185 saving as /var/lib/lava/dispatcher/tmp/975418/tftp-deploy-967p0fyb/modules/modules.tar
126 16:49:57.707391 total size: 11608784 (11 MB)
127 16:49:57.707601 Using unxz to decompress xz
128 16:49:57.759236 progress 0 % (0 MB)
129 16:49:57.827945 progress 5 % (0 MB)
130 16:49:57.906496 progress 10 % (1 MB)
131 16:49:58.006347 progress 15 % (1 MB)
132 16:49:58.099760 progress 20 % (2 MB)
133 16:49:58.179125 progress 25 % (2 MB)
134 16:49:58.255139 progress 30 % (3 MB)
135 16:49:58.329728 progress 35 % (3 MB)
136 16:49:58.408839 progress 40 % (4 MB)
137 16:49:58.485673 progress 45 % (5 MB)
138 16:49:58.572452 progress 50 % (5 MB)
139 16:49:58.650637 progress 55 % (6 MB)
140 16:49:58.736630 progress 60 % (6 MB)
141 16:49:58.817259 progress 65 % (7 MB)
142 16:49:58.894194 progress 70 % (7 MB)
143 16:49:58.976224 progress 75 % (8 MB)
144 16:49:59.060187 progress 80 % (8 MB)
145 16:49:59.140583 progress 85 % (9 MB)
146 16:49:59.219447 progress 90 % (9 MB)
147 16:49:59.297781 progress 95 % (10 MB)
148 16:49:59.376326 progress 100 % (11 MB)
149 16:49:59.388532 11 MB downloaded in 1.68 s (6.59 MB/s)
150 16:49:59.389108 end: 1.5.1 http-download (duration 00:00:02) [common]
152 16:49:59.389934 end: 1.5 download-retry (duration 00:00:02) [common]
153 16:49:59.390202 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 16:49:59.390467 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 16:50:16.029573 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/975418/extract-nfsrootfs-qo26sb3e
156 16:50:16.030181 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 16:50:16.030463 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 16:50:16.031144 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq
159 16:50:16.031605 makedir: /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin
160 16:50:16.031927 makedir: /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/tests
161 16:50:16.032269 makedir: /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/results
162 16:50:16.032596 Creating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-add-keys
163 16:50:16.033104 Creating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-add-sources
164 16:50:16.033589 Creating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-background-process-start
165 16:50:16.034063 Creating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-background-process-stop
166 16:50:16.034675 Creating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-common-functions
167 16:50:16.035222 Creating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-echo-ipv4
168 16:50:16.035691 Creating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-install-packages
169 16:50:16.036201 Creating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-installed-packages
170 16:50:16.036687 Creating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-os-build
171 16:50:16.037148 Creating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-probe-channel
172 16:50:16.037610 Creating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-probe-ip
173 16:50:16.038066 Creating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-target-ip
174 16:50:16.038519 Creating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-target-mac
175 16:50:16.038977 Creating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-target-storage
176 16:50:16.039441 Creating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-test-case
177 16:50:16.039928 Creating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-test-event
178 16:50:16.040431 Creating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-test-feedback
179 16:50:16.040895 Creating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-test-raise
180 16:50:16.041352 Creating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-test-reference
181 16:50:16.041814 Creating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-test-runner
182 16:50:16.042280 Creating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-test-set
183 16:50:16.042737 Creating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-test-shell
184 16:50:16.043200 Updating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-add-keys (debian)
185 16:50:16.043767 Updating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-add-sources (debian)
186 16:50:16.044317 Updating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-install-packages (debian)
187 16:50:16.044808 Updating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-installed-packages (debian)
188 16:50:16.045283 Updating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/bin/lava-os-build (debian)
189 16:50:16.045701 Creating /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/environment
190 16:50:16.046070 LAVA metadata
191 16:50:16.046339 - LAVA_JOB_ID=975418
192 16:50:16.046553 - LAVA_DISPATCHER_IP=192.168.6.2
193 16:50:16.046906 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 16:50:16.047922 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 16:50:16.048265 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 16:50:16.048474 skipped lava-vland-overlay
197 16:50:16.048714 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 16:50:16.048966 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 16:50:16.049184 skipped lava-multinode-overlay
200 16:50:16.049423 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 16:50:16.049669 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 16:50:16.049913 Loading test definitions
203 16:50:16.050184 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 16:50:16.050398 Using /lava-975418 at stage 0
205 16:50:16.051434 uuid=975418_1.6.2.4.1 testdef=None
206 16:50:16.051726 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 16:50:16.052002 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 16:50:16.053529 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 16:50:16.054309 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 16:50:16.056234 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 16:50:16.057054 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 16:50:16.058831 runner path: /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/0/tests/0_timesync-off test_uuid 975418_1.6.2.4.1
215 16:50:16.059349 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 16:50:16.060182 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 16:50:16.060402 Using /lava-975418 at stage 0
219 16:50:16.060742 Fetching tests from https://github.com/kernelci/test-definitions.git
220 16:50:16.061026 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/0/tests/1_kselftest-alsa'
221 16:50:19.724317 Running '/usr/bin/git checkout kernelci.org
222 16:50:20.174163 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 16:50:20.175589 uuid=975418_1.6.2.4.5 testdef=None
224 16:50:20.175930 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 16:50:20.177626 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 16:50:20.183741 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 16:50:20.185543 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 16:50:20.193518 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 16:50:20.195351 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 16:50:20.203156 runner path: /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/0/tests/1_kselftest-alsa test_uuid 975418_1.6.2.4.5
234 16:50:20.203745 BOARD='meson-g12b-a311d-libretech-cc'
235 16:50:20.204233 BRANCH='renesas'
236 16:50:20.204669 SKIPFILE='/dev/null'
237 16:50:20.205106 SKIP_INSTALL='True'
238 16:50:20.205535 TESTPROG_URL='http://storage.kernelci.org/renesas/next/renesas-next-2024-11-11-v6.12-rc1/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 16:50:20.205975 TST_CASENAME=''
240 16:50:20.206408 TST_CMDFILES='alsa'
241 16:50:20.207501 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 16:50:20.209225 Creating lava-test-runner.conf files
244 16:50:20.209669 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/975418/lava-overlay-wzsa6uhq/lava-975418/0 for stage 0
245 16:50:20.210357 - 0_timesync-off
246 16:50:20.210847 - 1_kselftest-alsa
247 16:50:20.211540 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 16:50:20.212157 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 16:50:43.650462 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 16:50:43.650903 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:57) [common]
251 16:50:43.651170 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 16:50:43.651441 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
253 16:50:43.651708 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:57) [common]
254 16:50:44.289950 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 16:50:44.290416 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 16:50:44.290670 extracting modules file /var/lib/lava/dispatcher/tmp/975418/tftp-deploy-967p0fyb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/975418/extract-nfsrootfs-qo26sb3e
257 16:50:45.858067 extracting modules file /var/lib/lava/dispatcher/tmp/975418/tftp-deploy-967p0fyb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/975418/extract-overlay-ramdisk-fyio9ur6/ramdisk
258 16:50:47.278922 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 16:50:47.279409 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 16:50:47.279700 [common] Applying overlay to NFS
261 16:50:47.279959 [common] Applying overlay /var/lib/lava/dispatcher/tmp/975418/compress-overlay-vaqnu17y/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/975418/extract-nfsrootfs-qo26sb3e
262 16:50:50.100008 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 16:50:50.100493 start: 1.6.6 prepare-kernel (timeout 00:08:51) [common]
264 16:50:50.100769 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:51) [common]
265 16:50:50.101001 Converting downloaded kernel to a uImage
266 16:50:50.101316 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/975418/tftp-deploy-967p0fyb/kernel/Image /var/lib/lava/dispatcher/tmp/975418/tftp-deploy-967p0fyb/kernel/uImage
267 16:50:50.619015 output: Image Name:
268 16:50:50.619449 output: Created: Mon Nov 11 16:50:50 2024
269 16:50:50.619660 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 16:50:50.619867 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 16:50:50.620113 output: Load Address: 01080000
272 16:50:50.620317 output: Entry Point: 01080000
273 16:50:50.620517 output:
274 16:50:50.620851 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 16:50:50.621117 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 16:50:50.621388 start: 1.6.7 configure-preseed-file (timeout 00:08:50) [common]
277 16:50:50.621641 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 16:50:50.621898 start: 1.6.8 compress-ramdisk (timeout 00:08:50) [common]
279 16:50:50.622155 Building ramdisk /var/lib/lava/dispatcher/tmp/975418/extract-overlay-ramdisk-fyio9ur6/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/975418/extract-overlay-ramdisk-fyio9ur6/ramdisk
280 16:50:52.894085 >> 166783 blocks
281 16:51:00.703593 Adding RAMdisk u-boot header.
282 16:51:00.704298 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/975418/extract-overlay-ramdisk-fyio9ur6/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/975418/extract-overlay-ramdisk-fyio9ur6/ramdisk.cpio.gz.uboot
283 16:51:00.950520 output: Image Name:
284 16:51:00.950939 output: Created: Mon Nov 11 16:51:00 2024
285 16:51:00.951152 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 16:51:00.951356 output: Data Size: 23428375 Bytes = 22879.27 KiB = 22.34 MiB
287 16:51:00.951557 output: Load Address: 00000000
288 16:51:00.951757 output: Entry Point: 00000000
289 16:51:00.951958 output:
290 16:51:00.953191 rename /var/lib/lava/dispatcher/tmp/975418/extract-overlay-ramdisk-fyio9ur6/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/975418/tftp-deploy-967p0fyb/ramdisk/ramdisk.cpio.gz.uboot
291 16:51:00.953966 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 16:51:00.954560 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 16:51:00.955135 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:40) [common]
294 16:51:00.955631 No LXC device requested
295 16:51:00.956217 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 16:51:00.956780 start: 1.8 deploy-device-env (timeout 00:08:40) [common]
297 16:51:00.957324 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 16:51:00.957773 Checking files for TFTP limit of 4294967296 bytes.
299 16:51:00.960783 end: 1 tftp-deploy (duration 00:01:20) [common]
300 16:51:00.961414 start: 2 uboot-action (timeout 00:05:00) [common]
301 16:51:00.961991 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 16:51:00.962541 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 16:51:00.963095 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 16:51:00.963671 Using kernel file from prepare-kernel: 975418/tftp-deploy-967p0fyb/kernel/uImage
305 16:51:00.964397 substitutions:
306 16:51:00.964851 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 16:51:00.965302 - {DTB_ADDR}: 0x01070000
308 16:51:00.965747 - {DTB}: 975418/tftp-deploy-967p0fyb/dtb/meson-g12b-a311d-libretech-cc.dtb
309 16:51:00.966195 - {INITRD}: 975418/tftp-deploy-967p0fyb/ramdisk/ramdisk.cpio.gz.uboot
310 16:51:00.966639 - {KERNEL_ADDR}: 0x01080000
311 16:51:00.967075 - {KERNEL}: 975418/tftp-deploy-967p0fyb/kernel/uImage
312 16:51:00.967513 - {LAVA_MAC}: None
313 16:51:00.968011 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/975418/extract-nfsrootfs-qo26sb3e
314 16:51:00.968473 - {NFS_SERVER_IP}: 192.168.6.2
315 16:51:00.968908 - {PRESEED_CONFIG}: None
316 16:51:00.969342 - {PRESEED_LOCAL}: None
317 16:51:00.969776 - {RAMDISK_ADDR}: 0x08000000
318 16:51:00.970207 - {RAMDISK}: 975418/tftp-deploy-967p0fyb/ramdisk/ramdisk.cpio.gz.uboot
319 16:51:00.970640 - {ROOT_PART}: None
320 16:51:00.971069 - {ROOT}: None
321 16:51:00.971502 - {SERVER_IP}: 192.168.6.2
322 16:51:00.971934 - {TEE_ADDR}: 0x83000000
323 16:51:00.972392 - {TEE}: None
324 16:51:00.972824 Parsed boot commands:
325 16:51:00.973246 - setenv autoload no
326 16:51:00.973678 - setenv initrd_high 0xffffffff
327 16:51:00.974109 - setenv fdt_high 0xffffffff
328 16:51:00.974538 - dhcp
329 16:51:00.974965 - setenv serverip 192.168.6.2
330 16:51:00.975396 - tftpboot 0x01080000 975418/tftp-deploy-967p0fyb/kernel/uImage
331 16:51:00.975830 - tftpboot 0x08000000 975418/tftp-deploy-967p0fyb/ramdisk/ramdisk.cpio.gz.uboot
332 16:51:00.976319 - tftpboot 0x01070000 975418/tftp-deploy-967p0fyb/dtb/meson-g12b-a311d-libretech-cc.dtb
333 16:51:00.976757 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/975418/extract-nfsrootfs-qo26sb3e,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 16:51:00.977206 - bootm 0x01080000 0x08000000 0x01070000
335 16:51:00.977752 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 16:51:00.979390 start: 2.3 connect-device (timeout 00:05:00) [common]
338 16:51:00.979852 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 16:51:00.995224 Setting prompt string to ['lava-test: # ']
340 16:51:00.996879 end: 2.3 connect-device (duration 00:00:00) [common]
341 16:51:00.997548 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 16:51:00.998165 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 16:51:00.998747 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 16:51:01.000005 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 16:51:01.037820 >> OK - accepted request
346 16:51:01.039964 Returned 0 in 0 seconds
347 16:51:01.141164 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 16:51:01.142853 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 16:51:01.143447 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 16:51:01.144033 Setting prompt string to ['Hit any key to stop autoboot']
352 16:51:01.144528 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 16:51:01.146201 Trying 192.168.56.21...
354 16:51:01.146706 Connected to conserv1.
355 16:51:01.147158 Escape character is '^]'.
356 16:51:01.147605
357 16:51:01.148084 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 16:51:01.148548
359 16:51:13.122834 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 16:51:13.123539 bl2_stage_init 0x01
361 16:51:13.124110 bl2_stage_init 0x81
362 16:51:13.128049 hw id: 0x0000 - pwm id 0x01
363 16:51:13.128623 bl2_stage_init 0xc1
364 16:51:13.129106 bl2_stage_init 0x02
365 16:51:13.129571
366 16:51:13.133841 L0:00000000
367 16:51:13.134391 L1:20000703
368 16:51:13.134875 L2:00008067
369 16:51:13.135341 L3:14000000
370 16:51:13.136908 B2:00402000
371 16:51:13.137187 B1:e0f83180
372 16:51:13.137392
373 16:51:13.137596 TE: 58167
374 16:51:13.137791
375 16:51:13.147817 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 16:51:13.148741
377 16:51:13.150264 Board ID = 1
378 16:51:13.151121 Set A53 clk to 24M
379 16:51:13.152403 Set A73 clk to 24M
380 16:51:13.153213 Set clk81 to 24M
381 16:51:13.153466 A53 clk: 1200 MHz
382 16:51:13.153665 A73 clk: 1200 MHz
383 16:51:13.158312 CLK81: 166.6M
384 16:51:13.160066 smccc: 00012abd
385 16:51:13.163386 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 16:51:13.166788 board id: 1
387 16:51:13.173643 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 16:51:13.183867 fw parse done
389 16:51:13.190780 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 16:51:13.232666 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 16:51:13.243763 PIEI prepare done
392 16:51:13.245550 fastboot data load
393 16:51:13.246059 fastboot data verify
394 16:51:13.248561 verify result: 266
395 16:51:13.254353 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 16:51:13.254863 LPDDR4 probe
397 16:51:13.255305 ddr clk to 1584MHz
398 16:51:13.262146 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 16:51:13.299383
400 16:51:13.299946 dmc_version 0001
401 16:51:13.306164 Check phy result
402 16:51:13.311957 INFO : End of CA training
403 16:51:13.312553 INFO : End of initialization
404 16:51:13.317559 INFO : Training has run successfully!
405 16:51:13.317898 Check phy result
406 16:51:13.323042 INFO : End of initialization
407 16:51:13.323369 INFO : End of read enable training
408 16:51:13.328833 INFO : End of fine write leveling
409 16:51:13.334365 INFO : End of Write leveling coarse delay
410 16:51:13.334926 INFO : Training has run successfully!
411 16:51:13.335401 Check phy result
412 16:51:13.339899 INFO : End of initialization
413 16:51:13.340311 INFO : End of read dq deskew training
414 16:51:13.345550 INFO : End of MPR read delay center optimization
415 16:51:13.351347 INFO : End of write delay center optimization
416 16:51:13.356736 INFO : End of read delay center optimization
417 16:51:13.357337 INFO : End of max read latency training
418 16:51:13.362415 INFO : Training has run successfully!
419 16:51:13.362962 1D training succeed
420 16:51:13.371563 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 16:51:13.420116 Check phy result
422 16:51:13.420736 INFO : End of initialization
423 16:51:13.440899 INFO : End of 2D read delay Voltage center optimization
424 16:51:13.461191 INFO : End of 2D read delay Voltage center optimization
425 16:51:13.513232 INFO : End of 2D write delay Voltage center optimization
426 16:51:13.562576 INFO : End of 2D write delay Voltage center optimization
427 16:51:13.568118 INFO : Training has run successfully!
428 16:51:13.568616
429 16:51:13.569025 channel==0
430 16:51:13.573790 RxClkDly_Margin_A0==88 ps 9
431 16:51:13.574272 TxDqDly_Margin_A0==98 ps 10
432 16:51:13.577078 RxClkDly_Margin_A1==88 ps 9
433 16:51:13.577561 TxDqDly_Margin_A1==98 ps 10
434 16:51:13.582770 TrainedVREFDQ_A0==74
435 16:51:13.583296 TrainedVREFDQ_A1==74
436 16:51:13.583715 VrefDac_Margin_A0==25
437 16:51:13.588386 DeviceVref_Margin_A0==40
438 16:51:13.588868 VrefDac_Margin_A1==25
439 16:51:13.593766 DeviceVref_Margin_A1==40
440 16:51:13.594116
441 16:51:13.594351
442 16:51:13.594568 channel==1
443 16:51:13.594782 RxClkDly_Margin_A0==98 ps 10
444 16:51:13.599394 TxDqDly_Margin_A0==98 ps 10
445 16:51:13.599715 RxClkDly_Margin_A1==98 ps 10
446 16:51:13.605061 TxDqDly_Margin_A1==88 ps 9
447 16:51:13.605409 TrainedVREFDQ_A0==77
448 16:51:13.605633 TrainedVREFDQ_A1==77
449 16:51:13.610632 VrefDac_Margin_A0==22
450 16:51:13.610975 DeviceVref_Margin_A0==37
451 16:51:13.616414 VrefDac_Margin_A1==22
452 16:51:13.616766 DeviceVref_Margin_A1==37
453 16:51:13.616972
454 16:51:13.621830 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 16:51:13.622134
456 16:51:13.649629 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
457 16:51:13.655274 2D training succeed
458 16:51:13.660822 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 16:51:13.661062 auto size-- 65535DDR cs0 size: 2048MB
460 16:51:13.666400 DDR cs1 size: 2048MB
461 16:51:13.666642 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 16:51:13.672229 cs0 DataBus test pass
463 16:51:13.672487 cs1 DataBus test pass
464 16:51:13.672687 cs0 AddrBus test pass
465 16:51:13.677654 cs1 AddrBus test pass
466 16:51:13.677904
467 16:51:13.678393 100bdlr_step_size ps== 420
468 16:51:13.678843 result report
469 16:51:13.683296 boot times 0Enable ddr reg access
470 16:51:13.691002 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 16:51:13.704476 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 16:51:14.277509 0.0;M3 CHK:0;cm4_sp_mode 0
473 16:51:14.277936 MVN_1=0x00000000
474 16:51:14.282966 MVN_2=0x00000000
475 16:51:14.288721 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 16:51:14.289026 OPS=0x10
477 16:51:14.289261 ring efuse init
478 16:51:14.289485 chipver efuse init
479 16:51:14.294382 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 16:51:14.300018 [0.018961 Inits done]
481 16:51:14.300317 secure task start!
482 16:51:14.300553 high task start!
483 16:51:14.304500 low task start!
484 16:51:14.304810 run into bl31
485 16:51:14.311220 NOTICE: BL31: v1.3(release):4fc40b1
486 16:51:14.318968 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 16:51:14.319314 NOTICE: BL31: G12A normal boot!
488 16:51:14.344382 NOTICE: BL31: BL33 decompress pass
489 16:51:14.349986 ERROR: Error initializing runtime service opteed_fast
490 16:51:15.582877
491 16:51:15.583757
492 16:51:15.591310 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 16:51:15.591969
494 16:51:15.592610 Model: Libre Computer AML-A311D-CC Alta
495 16:51:15.799809 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 16:51:15.823120 DRAM: 2 GiB (effective 3.8 GiB)
497 16:51:15.966067 Core: 408 devices, 31 uclasses, devicetree: separate
498 16:51:15.971967 WDT: Not starting watchdog@f0d0
499 16:51:16.004272 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 16:51:16.016687 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 16:51:16.021738 ** Bad device specification mmc 0 **
502 16:51:16.032042 Card did not respond to voltage select! : -110
503 16:51:16.039556 ** Bad device specification mmc 0 **
504 16:51:16.040217 Couldn't find partition mmc 0
505 16:51:16.047931 Card did not respond to voltage select! : -110
506 16:51:16.053452 ** Bad device specification mmc 0 **
507 16:51:16.054107 Couldn't find partition mmc 0
508 16:51:16.058573 Error: could not access storage.
509 16:51:17.322324 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 16:51:17.323160 bl2_stage_init 0x01
511 16:51:17.323747 bl2_stage_init 0x81
512 16:51:17.327811 hw id: 0x0000 - pwm id 0x01
513 16:51:17.328515 bl2_stage_init 0xc1
514 16:51:17.329080 bl2_stage_init 0x02
515 16:51:17.329631
516 16:51:17.333466 L0:00000000
517 16:51:17.334090 L1:20000703
518 16:51:17.334674 L2:00008067
519 16:51:17.335233 L3:14000000
520 16:51:17.339069 B2:00402000
521 16:51:17.339677 B1:e0f83180
522 16:51:17.340289
523 16:51:17.340855 TE: 58124
524 16:51:17.341417
525 16:51:17.344620 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 16:51:17.345239
527 16:51:17.345804 Board ID = 1
528 16:51:17.350252 Set A53 clk to 24M
529 16:51:17.350859 Set A73 clk to 24M
530 16:51:17.351418 Set clk81 to 24M
531 16:51:17.355849 A53 clk: 1200 MHz
532 16:51:17.356478 A73 clk: 1200 MHz
533 16:51:17.357030 CLK81: 166.6M
534 16:51:17.357582 smccc: 00012a92
535 16:51:17.361454 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 16:51:17.367001 board id: 1
537 16:51:17.372937 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 16:51:17.383686 fw parse done
539 16:51:17.389493 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 16:51:17.432152 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 16:51:17.442997 PIEI prepare done
542 16:51:17.443602 fastboot data load
543 16:51:17.444214 fastboot data verify
544 16:51:17.448641 verify result: 266
545 16:51:17.454273 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 16:51:17.454872 LPDDR4 probe
547 16:51:17.455428 ddr clk to 1584MHz
548 16:51:17.462252 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 16:51:17.499521
550 16:51:17.500192 dmc_version 0001
551 16:51:17.506184 Check phy result
552 16:51:17.512078 INFO : End of CA training
553 16:51:17.512685 INFO : End of initialization
554 16:51:17.517699 INFO : Training has run successfully!
555 16:51:17.518291 Check phy result
556 16:51:17.523285 INFO : End of initialization
557 16:51:17.523890 INFO : End of read enable training
558 16:51:17.529153 INFO : End of fine write leveling
559 16:51:17.534473 INFO : End of Write leveling coarse delay
560 16:51:17.535075 INFO : Training has run successfully!
561 16:51:17.535638 Check phy result
562 16:51:17.540118 INFO : End of initialization
563 16:51:17.540707 INFO : End of read dq deskew training
564 16:51:17.545670 INFO : End of MPR read delay center optimization
565 16:51:17.551317 INFO : End of write delay center optimization
566 16:51:17.556886 INFO : End of read delay center optimization
567 16:51:17.557478 INFO : End of max read latency training
568 16:51:17.562508 INFO : Training has run successfully!
569 16:51:17.563110 1D training succeed
570 16:51:17.571742 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 16:51:17.619277 Check phy result
572 16:51:17.619896 INFO : End of initialization
573 16:51:17.641893 INFO : End of 2D read delay Voltage center optimization
574 16:51:17.662262 INFO : End of 2D read delay Voltage center optimization
575 16:51:17.714288 INFO : End of 2D write delay Voltage center optimization
576 16:51:17.763658 INFO : End of 2D write delay Voltage center optimization
577 16:51:17.769153 INFO : Training has run successfully!
578 16:51:17.769767
579 16:51:17.770337 channel==0
580 16:51:17.774822 RxClkDly_Margin_A0==88 ps 9
581 16:51:17.775415 TxDqDly_Margin_A0==98 ps 10
582 16:51:17.780454 RxClkDly_Margin_A1==88 ps 9
583 16:51:17.781107 TxDqDly_Margin_A1==98 ps 10
584 16:51:17.781659 TrainedVREFDQ_A0==74
585 16:51:17.786031 TrainedVREFDQ_A1==74
586 16:51:17.786665 VrefDac_Margin_A0==25
587 16:51:17.787252 DeviceVref_Margin_A0==40
588 16:51:17.791571 VrefDac_Margin_A1==25
589 16:51:17.792209 DeviceVref_Margin_A1==40
590 16:51:17.792799
591 16:51:17.793382
592 16:51:17.797177 channel==1
593 16:51:17.797785 RxClkDly_Margin_A0==98 ps 10
594 16:51:17.798363 TxDqDly_Margin_A0==98 ps 10
595 16:51:17.802820 RxClkDly_Margin_A1==88 ps 9
596 16:51:17.803431 TxDqDly_Margin_A1==88 ps 9
597 16:51:17.808340 TrainedVREFDQ_A0==77
598 16:51:17.808961 TrainedVREFDQ_A1==77
599 16:51:17.809545 VrefDac_Margin_A0==22
600 16:51:17.814002 DeviceVref_Margin_A0==37
601 16:51:17.814620 VrefDac_Margin_A1==24
602 16:51:17.819539 DeviceVref_Margin_A1==37
603 16:51:17.820187
604 16:51:17.820797 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 16:51:17.821393
606 16:51:17.853195 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000017 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
607 16:51:17.853753 2D training succeed
608 16:51:17.858817 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 16:51:17.864364 auto size-- 65535DDR cs0 size: 2048MB
610 16:51:17.864852 DDR cs1 size: 2048MB
611 16:51:17.869952 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 16:51:17.870421 cs0 DataBus test pass
613 16:51:17.875544 cs1 DataBus test pass
614 16:51:17.876052 cs0 AddrBus test pass
615 16:51:17.876493 cs1 AddrBus test pass
616 16:51:17.876925
617 16:51:17.881147 100bdlr_step_size ps== 420
618 16:51:17.881624 result report
619 16:51:17.886805 boot times 0Enable ddr reg access
620 16:51:17.892071 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 16:51:17.905589 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 16:51:18.479232 0.0;M3 CHK:0;cm4_sp_mode 0
623 16:51:18.479853 MVN_1=0x00000000
624 16:51:18.484657 MVN_2=0x00000000
625 16:51:18.490436 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 16:51:18.490911 OPS=0x10
627 16:51:18.491347 ring efuse init
628 16:51:18.491771 chipver efuse init
629 16:51:18.496058 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 16:51:18.501650 [0.018961 Inits done]
631 16:51:18.502111 secure task start!
632 16:51:18.502540 high task start!
633 16:51:18.506222 low task start!
634 16:51:18.506678 run into bl31
635 16:51:18.512870 NOTICE: BL31: v1.3(release):4fc40b1
636 16:51:18.520676 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 16:51:18.521140 NOTICE: BL31: G12A normal boot!
638 16:51:18.546006 NOTICE: BL31: BL33 decompress pass
639 16:51:18.551670 ERROR: Error initializing runtime service opteed_fast
640 16:51:19.784783
641 16:51:19.785405
642 16:51:19.793206 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 16:51:19.793685
644 16:51:19.794121 Model: Libre Computer AML-A311D-CC Alta
645 16:51:20.001660 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 16:51:20.025071 DRAM: 2 GiB (effective 3.8 GiB)
647 16:51:20.167871 Core: 408 devices, 31 uclasses, devicetree: separate
648 16:51:20.173795 WDT: Not starting watchdog@f0d0
649 16:51:20.205997 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 16:51:20.218580 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 16:51:20.223477 ** Bad device specification mmc 0 **
652 16:51:20.233787 Card did not respond to voltage select! : -110
653 16:51:20.241465 ** Bad device specification mmc 0 **
654 16:51:20.241926 Couldn't find partition mmc 0
655 16:51:20.249759 Card did not respond to voltage select! : -110
656 16:51:20.255325 ** Bad device specification mmc 0 **
657 16:51:20.255804 Couldn't find partition mmc 0
658 16:51:20.260347 Error: could not access storage.
659 16:51:20.602906 Net: eth0: ethernet@ff3f0000
660 16:51:20.603458 starting USB...
661 16:51:20.854710 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 16:51:20.855212 Starting the controller
663 16:51:20.861666 USB XHCI 1.10
664 16:51:22.571342 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 16:51:22.572045 bl2_stage_init 0x01
666 16:51:22.572511 bl2_stage_init 0x81
667 16:51:22.576973 hw id: 0x0000 - pwm id 0x01
668 16:51:22.577450 bl2_stage_init 0xc1
669 16:51:22.577887 bl2_stage_init 0x02
670 16:51:22.578320
671 16:51:22.582545 L0:00000000
672 16:51:22.583009 L1:20000703
673 16:51:22.583444 L2:00008067
674 16:51:22.583869 L3:14000000
675 16:51:22.588065 B2:00402000
676 16:51:22.588533 B1:e0f83180
677 16:51:22.588969
678 16:51:22.589400 TE: 58124
679 16:51:22.589831
680 16:51:22.593742 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 16:51:22.594209
682 16:51:22.594643 Board ID = 1
683 16:51:22.599299 Set A53 clk to 24M
684 16:51:22.599764 Set A73 clk to 24M
685 16:51:22.600227 Set clk81 to 24M
686 16:51:22.604942 A53 clk: 1200 MHz
687 16:51:22.605403 A73 clk: 1200 MHz
688 16:51:22.605836 CLK81: 166.6M
689 16:51:22.606266 smccc: 00012a92
690 16:51:22.610600 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 16:51:22.616144 board id: 1
692 16:51:22.621938 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 16:51:22.632779 fw parse done
694 16:51:22.638669 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 16:51:22.681195 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 16:51:22.692085 PIEI prepare done
697 16:51:22.692545 fastboot data load
698 16:51:22.692980 fastboot data verify
699 16:51:22.697665 verify result: 266
700 16:51:22.703282 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 16:51:22.703740 LPDDR4 probe
702 16:51:22.704201 ddr clk to 1584MHz
703 16:51:22.711324 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 16:51:22.748633
705 16:51:22.749097 dmc_version 0001
706 16:51:22.755186 Check phy result
707 16:51:22.761088 INFO : End of CA training
708 16:51:22.761540 INFO : End of initialization
709 16:51:22.766635 INFO : Training has run successfully!
710 16:51:22.767089 Check phy result
711 16:51:22.772247 INFO : End of initialization
712 16:51:22.772701 INFO : End of read enable training
713 16:51:22.775524 INFO : End of fine write leveling
714 16:51:22.781092 INFO : End of Write leveling coarse delay
715 16:51:22.786726 INFO : Training has run successfully!
716 16:51:22.787211 Check phy result
717 16:51:22.787645 INFO : End of initialization
718 16:51:22.792297 INFO : End of read dq deskew training
719 16:51:22.797934 INFO : End of MPR read delay center optimization
720 16:51:22.798390 INFO : End of write delay center optimization
721 16:51:22.803536 INFO : End of read delay center optimization
722 16:51:22.809094 INFO : End of max read latency training
723 16:51:22.809557 INFO : Training has run successfully!
724 16:51:22.814691 1D training succeed
725 16:51:22.820651 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 16:51:22.868242 Check phy result
727 16:51:22.868707 INFO : End of initialization
728 16:51:22.889914 INFO : End of 2D read delay Voltage center optimization
729 16:51:22.910003 INFO : End of 2D read delay Voltage center optimization
730 16:51:22.960943 INFO : End of 2D write delay Voltage center optimization
731 16:51:23.011213 INFO : End of 2D write delay Voltage center optimization
732 16:51:23.016790 INFO : Training has run successfully!
733 16:51:23.017255
734 16:51:23.017695 channel==0
735 16:51:23.022360 RxClkDly_Margin_A0==88 ps 9
736 16:51:23.022817 TxDqDly_Margin_A0==98 ps 10
737 16:51:23.025699 RxClkDly_Margin_A1==88 ps 9
738 16:51:23.026160 TxDqDly_Margin_A1==88 ps 9
739 16:51:23.031327 TrainedVREFDQ_A0==74
740 16:51:23.031794 TrainedVREFDQ_A1==74
741 16:51:23.032268 VrefDac_Margin_A0==25
742 16:51:23.036921 DeviceVref_Margin_A0==40
743 16:51:23.037380 VrefDac_Margin_A1==25
744 16:51:23.042506 DeviceVref_Margin_A1==40
745 16:51:23.042977
746 16:51:23.043414
747 16:51:23.043844 channel==1
748 16:51:23.044306 RxClkDly_Margin_A0==98 ps 10
749 16:51:23.048107 TxDqDly_Margin_A0==98 ps 10
750 16:51:23.048576 RxClkDly_Margin_A1==98 ps 10
751 16:51:23.053653 TxDqDly_Margin_A1==88 ps 9
752 16:51:23.054114 TrainedVREFDQ_A0==77
753 16:51:23.054547 TrainedVREFDQ_A1==77
754 16:51:23.059329 VrefDac_Margin_A0==22
755 16:51:23.059782 DeviceVref_Margin_A0==37
756 16:51:23.064851 VrefDac_Margin_A1==22
757 16:51:23.065310 DeviceVref_Margin_A1==37
758 16:51:23.065738
759 16:51:23.070464 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 16:51:23.070922
761 16:51:23.098411 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
762 16:51:23.103970 2D training succeed
763 16:51:23.109591 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 16:51:23.110057 auto size-- 65535DDR cs0 size: 2048MB
765 16:51:23.115147 DDR cs1 size: 2048MB
766 16:51:23.115608 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 16:51:23.120765 cs0 DataBus test pass
768 16:51:23.121225 cs1 DataBus test pass
769 16:51:23.121655 cs0 AddrBus test pass
770 16:51:23.126330 cs1 AddrBus test pass
771 16:51:23.126785
772 16:51:23.127215 100bdlr_step_size ps== 420
773 16:51:23.127656 result report
774 16:51:23.131932 boot times 0Enable ddr reg access
775 16:51:23.139480 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 16:51:23.153046 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 16:51:23.724989 0.0;M3 CHK:0;cm4_sp_mode 0
778 16:51:23.725619 MVN_1=0x00000000
779 16:51:23.730579 MVN_2=0x00000000
780 16:51:23.736315 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 16:51:23.736838 OPS=0x10
782 16:51:23.737271 ring efuse init
783 16:51:23.737691 chipver efuse init
784 16:51:23.744506 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 16:51:23.744983 [0.018961 Inits done]
786 16:51:23.752072 secure task start!
787 16:51:23.752535 high task start!
788 16:51:23.752960 low task start!
789 16:51:23.753385 run into bl31
790 16:51:23.758695 NOTICE: BL31: v1.3(release):4fc40b1
791 16:51:23.766620 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 16:51:23.767085 NOTICE: BL31: G12A normal boot!
793 16:51:23.791943 NOTICE: BL31: BL33 decompress pass
794 16:51:23.797611 ERROR: Error initializing runtime service opteed_fast
795 16:51:25.030508
796 16:51:25.030939
797 16:51:25.038907 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 16:51:25.039467
799 16:51:25.039935 Model: Libre Computer AML-A311D-CC Alta
800 16:51:25.247301 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 16:51:25.270849 DRAM: 2 GiB (effective 3.8 GiB)
802 16:51:25.413683 Core: 408 devices, 31 uclasses, devicetree: separate
803 16:51:25.419581 WDT: Not starting watchdog@f0d0
804 16:51:25.451843 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 16:51:25.464252 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 16:51:25.469227 ** Bad device specification mmc 0 **
807 16:51:25.479569 Card did not respond to voltage select! : -110
808 16:51:25.487262 ** Bad device specification mmc 0 **
809 16:51:25.487745 Couldn't find partition mmc 0
810 16:51:25.495583 Card did not respond to voltage select! : -110
811 16:51:25.501099 ** Bad device specification mmc 0 **
812 16:51:25.501577 Couldn't find partition mmc 0
813 16:51:25.506178 Error: could not access storage.
814 16:51:25.848681 Net: eth0: ethernet@ff3f0000
815 16:51:25.849239 starting USB...
816 16:51:26.100467 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 16:51:26.101074 Starting the controller
818 16:51:26.110456 USB XHCI 1.10
819 16:51:28.271314 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 16:51:28.271955 bl2_stage_init 0x01
821 16:51:28.272502 bl2_stage_init 0x81
822 16:51:28.276879 hw id: 0x0000 - pwm id 0x01
823 16:51:28.277362 bl2_stage_init 0xc1
824 16:51:28.277816 bl2_stage_init 0x02
825 16:51:28.278259
826 16:51:28.282452 L0:00000000
827 16:51:28.282923 L1:20000703
828 16:51:28.283364 L2:00008067
829 16:51:28.283803 L3:14000000
830 16:51:28.288092 B2:00402000
831 16:51:28.288565 B1:e0f83180
832 16:51:28.289009
833 16:51:28.289451 TE: 58124
834 16:51:28.289898
835 16:51:28.293690 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 16:51:28.294165
837 16:51:28.294609 Board ID = 1
838 16:51:28.299273 Set A53 clk to 24M
839 16:51:28.299743 Set A73 clk to 24M
840 16:51:28.300221 Set clk81 to 24M
841 16:51:28.304973 A53 clk: 1200 MHz
842 16:51:28.305445 A73 clk: 1200 MHz
843 16:51:28.305889 CLK81: 166.6M
844 16:51:28.306327 smccc: 00012a92
845 16:51:28.310580 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 16:51:28.316512 board id: 1
847 16:51:28.322284 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 16:51:28.332663 fw parse done
849 16:51:28.338618 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 16:51:28.381206 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 16:51:28.392161 PIEI prepare done
852 16:51:28.392723 fastboot data load
853 16:51:28.393194 fastboot data verify
854 16:51:28.397779 verify result: 266
855 16:51:28.403371 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 16:51:28.403915 LPDDR4 probe
857 16:51:28.404428 ddr clk to 1584MHz
858 16:51:28.411456 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 16:51:28.448631
860 16:51:28.449188 dmc_version 0001
861 16:51:28.455398 Check phy result
862 16:51:28.461156 INFO : End of CA training
863 16:51:28.461688 INFO : End of initialization
864 16:51:28.466808 INFO : Training has run successfully!
865 16:51:28.467336 Check phy result
866 16:51:28.472384 INFO : End of initialization
867 16:51:28.472914 INFO : End of read enable training
868 16:51:28.477982 INFO : End of fine write leveling
869 16:51:28.483607 INFO : End of Write leveling coarse delay
870 16:51:28.484176 INFO : Training has run successfully!
871 16:51:28.484681 Check phy result
872 16:51:28.489245 INFO : End of initialization
873 16:51:28.489783 INFO : End of read dq deskew training
874 16:51:28.494841 INFO : End of MPR read delay center optimization
875 16:51:28.500424 INFO : End of write delay center optimization
876 16:51:28.505949 INFO : End of read delay center optimization
877 16:51:28.506470 INFO : End of max read latency training
878 16:51:28.511579 INFO : Training has run successfully!
879 16:51:28.512148 1D training succeed
880 16:51:28.520768 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 16:51:28.568305 Check phy result
882 16:51:28.568842 INFO : End of initialization
883 16:51:28.590134 INFO : End of 2D read delay Voltage center optimization
884 16:51:28.610305 INFO : End of 2D read delay Voltage center optimization
885 16:51:28.662316 INFO : End of 2D write delay Voltage center optimization
886 16:51:28.711777 INFO : End of 2D write delay Voltage center optimization
887 16:51:28.717493 INFO : Training has run successfully!
888 16:51:28.718023
889 16:51:28.718485 channel==0
890 16:51:28.723010 RxClkDly_Margin_A0==88 ps 9
891 16:51:28.723544 TxDqDly_Margin_A0==98 ps 10
892 16:51:28.728454 RxClkDly_Margin_A1==88 ps 9
893 16:51:28.728989 TxDqDly_Margin_A1==98 ps 10
894 16:51:28.729474 TrainedVREFDQ_A0==74
895 16:51:28.734225 TrainedVREFDQ_A1==74
896 16:51:28.734779 VrefDac_Margin_A0==25
897 16:51:28.735236 DeviceVref_Margin_A0==40
898 16:51:28.739802 VrefDac_Margin_A1==25
899 16:51:28.740372 DeviceVref_Margin_A1==40
900 16:51:28.740810
901 16:51:28.741235
902 16:51:28.745443 channel==1
903 16:51:28.745950 RxClkDly_Margin_A0==98 ps 10
904 16:51:28.746378 TxDqDly_Margin_A0==88 ps 9
905 16:51:28.750890 RxClkDly_Margin_A1==98 ps 10
906 16:51:28.751397 TxDqDly_Margin_A1==88 ps 9
907 16:51:28.756512 TrainedVREFDQ_A0==77
908 16:51:28.757046 TrainedVREFDQ_A1==77
909 16:51:28.757481 VrefDac_Margin_A0==22
910 16:51:28.762179 DeviceVref_Margin_A0==37
911 16:51:28.762689 VrefDac_Margin_A1==22
912 16:51:28.767688 DeviceVref_Margin_A1==37
913 16:51:28.768229
914 16:51:28.768664 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 16:51:28.769093
916 16:51:28.801417 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
917 16:51:28.801978 2D training succeed
918 16:51:28.806926 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 16:51:28.812532 auto size-- 65535DDR cs0 size: 2048MB
920 16:51:28.813046 DDR cs1 size: 2048MB
921 16:51:28.818181 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 16:51:28.818694 cs0 DataBus test pass
923 16:51:28.823716 cs1 DataBus test pass
924 16:51:28.824262 cs0 AddrBus test pass
925 16:51:28.824694 cs1 AddrBus test pass
926 16:51:28.825115
927 16:51:28.829287 100bdlr_step_size ps== 420
928 16:51:28.829812 result report
929 16:51:28.834918 boot times 0Enable ddr reg access
930 16:51:28.840283 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 16:51:28.853649 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 16:51:29.427275 0.0;M3 CHK:0;cm4_sp_mode 0
933 16:51:29.427950 MVN_1=0x00000000
934 16:51:29.432849 MVN_2=0x00000000
935 16:51:29.438609 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 16:51:29.439140 OPS=0x10
937 16:51:29.439602 ring efuse init
938 16:51:29.440085 chipver efuse init
939 16:51:29.444198 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 16:51:29.449737 [0.018961 Inits done]
941 16:51:29.450270 secure task start!
942 16:51:29.450730 high task start!
943 16:51:29.454476 low task start!
944 16:51:29.455002 run into bl31
945 16:51:29.461050 NOTICE: BL31: v1.3(release):4fc40b1
946 16:51:29.468869 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 16:51:29.469394 NOTICE: BL31: G12A normal boot!
948 16:51:29.494209 NOTICE: BL31: BL33 decompress pass
949 16:51:29.499911 ERROR: Error initializing runtime service opteed_fast
950 16:51:30.732697
951 16:51:30.733309
952 16:51:30.741903 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 16:51:30.742426
954 16:51:30.742902 Model: Libre Computer AML-A311D-CC Alta
955 16:51:30.949508 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 16:51:30.972922 DRAM: 2 GiB (effective 3.8 GiB)
957 16:51:31.115909 Core: 408 devices, 31 uclasses, devicetree: separate
958 16:51:31.122069 WDT: Not starting watchdog@f0d0
959 16:51:31.154065 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 16:51:31.166714 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 16:51:31.171799 ** Bad device specification mmc 0 **
962 16:51:31.181891 Card did not respond to voltage select! : -110
963 16:51:31.189560 ** Bad device specification mmc 0 **
964 16:51:31.190089 Couldn't find partition mmc 0
965 16:51:31.197912 Card did not respond to voltage select! : -110
966 16:51:31.203466 ** Bad device specification mmc 0 **
967 16:51:31.204019 Couldn't find partition mmc 0
968 16:51:31.208500 Error: could not access storage.
969 16:51:31.550979 Net: eth0: ethernet@ff3f0000
970 16:51:31.551604 starting USB...
971 16:51:31.802801 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 16:51:31.803388 Starting the controller
973 16:51:31.809903 USB XHCI 1.10
974 16:51:33.671207 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 16:51:33.671839 bl2_stage_init 0x01
976 16:51:33.672358 bl2_stage_init 0x81
977 16:51:33.676858 hw id: 0x0000 - pwm id 0x01
978 16:51:33.677377 bl2_stage_init 0xc1
979 16:51:33.677831 bl2_stage_init 0x02
980 16:51:33.678273
981 16:51:33.682435 L0:00000000
982 16:51:33.682945 L1:20000703
983 16:51:33.683393 L2:00008067
984 16:51:33.683833 L3:14000000
985 16:51:33.688088 B2:00402000
986 16:51:33.688601 B1:e0f83180
987 16:51:33.689049
988 16:51:33.689485 TE: 58124
989 16:51:33.689921
990 16:51:33.693649 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 16:51:33.694166
992 16:51:33.694613 Board ID = 1
993 16:51:33.699239 Set A53 clk to 24M
994 16:51:33.699749 Set A73 clk to 24M
995 16:51:33.700235 Set clk81 to 24M
996 16:51:33.704836 A53 clk: 1200 MHz
997 16:51:33.705347 A73 clk: 1200 MHz
998 16:51:33.705795 CLK81: 166.6M
999 16:51:33.706230 smccc: 00012a91
1000 16:51:33.710458 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 16:51:33.716055 board id: 1
1002 16:51:33.721632 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 16:51:33.732545 fw parse done
1004 16:51:33.738615 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 16:51:33.781146 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 16:51:33.792052 PIEI prepare done
1007 16:51:33.792555 fastboot data load
1008 16:51:33.792989 fastboot data verify
1009 16:51:33.797705 verify result: 266
1010 16:51:33.803272 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 16:51:33.803771 LPDDR4 probe
1012 16:51:33.804235 ddr clk to 1584MHz
1013 16:51:33.811295 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 16:51:33.848585
1015 16:51:33.849092 dmc_version 0001
1016 16:51:33.855413 Check phy result
1017 16:51:33.861275 INFO : End of CA training
1018 16:51:33.861801 INFO : End of initialization
1019 16:51:33.866909 INFO : Training has run successfully!
1020 16:51:33.867420 Check phy result
1021 16:51:33.872382 INFO : End of initialization
1022 16:51:33.872892 INFO : End of read enable training
1023 16:51:33.878057 INFO : End of fine write leveling
1024 16:51:33.883671 INFO : End of Write leveling coarse delay
1025 16:51:33.884213 INFO : Training has run successfully!
1026 16:51:33.884671 Check phy result
1027 16:51:33.889219 INFO : End of initialization
1028 16:51:33.889726 INFO : End of read dq deskew training
1029 16:51:33.894777 INFO : End of MPR read delay center optimization
1030 16:51:33.900428 INFO : End of write delay center optimization
1031 16:51:33.905961 INFO : End of read delay center optimization
1032 16:51:33.906472 INFO : End of max read latency training
1033 16:51:33.911650 INFO : Training has run successfully!
1034 16:51:33.912201 1D training succeed
1035 16:51:33.920853 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 16:51:33.968224 Check phy result
1037 16:51:33.968744 INFO : End of initialization
1038 16:51:33.989996 INFO : End of 2D read delay Voltage center optimization
1039 16:51:34.010183 INFO : End of 2D read delay Voltage center optimization
1040 16:51:34.062159 INFO : End of 2D write delay Voltage center optimization
1041 16:51:34.111539 INFO : End of 2D write delay Voltage center optimization
1042 16:51:34.117181 INFO : Training has run successfully!
1043 16:51:34.117691
1044 16:51:34.118145 channel==0
1045 16:51:34.122777 RxClkDly_Margin_A0==88 ps 9
1046 16:51:34.123309 TxDqDly_Margin_A0==98 ps 10
1047 16:51:34.128393 RxClkDly_Margin_A1==88 ps 9
1048 16:51:34.128904 TxDqDly_Margin_A1==98 ps 10
1049 16:51:34.129362 TrainedVREFDQ_A0==74
1050 16:51:34.133985 TrainedVREFDQ_A1==74
1051 16:51:34.134493 VrefDac_Margin_A0==25
1052 16:51:34.134940 DeviceVref_Margin_A0==40
1053 16:51:34.139554 VrefDac_Margin_A1==25
1054 16:51:34.140087 DeviceVref_Margin_A1==40
1055 16:51:34.140534
1056 16:51:34.140971
1057 16:51:34.145218 channel==1
1058 16:51:34.145735 RxClkDly_Margin_A0==98 ps 10
1059 16:51:34.146186 TxDqDly_Margin_A0==98 ps 10
1060 16:51:34.150800 RxClkDly_Margin_A1==98 ps 10
1061 16:51:34.151308 TxDqDly_Margin_A1==88 ps 9
1062 16:51:34.156422 TrainedVREFDQ_A0==77
1063 16:51:34.156926 TrainedVREFDQ_A1==77
1064 16:51:34.157375 VrefDac_Margin_A0==22
1065 16:51:34.161994 DeviceVref_Margin_A0==37
1066 16:51:34.162497 VrefDac_Margin_A1==22
1067 16:51:34.167572 DeviceVref_Margin_A1==37
1068 16:51:34.168104
1069 16:51:34.168552 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 16:51:34.173176
1071 16:51:34.201147 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1072 16:51:34.201688 2D training succeed
1073 16:51:34.206711 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 16:51:34.212396 auto size-- 65535DDR cs0 size: 2048MB
1075 16:51:34.212905 DDR cs1 size: 2048MB
1076 16:51:34.217961 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 16:51:34.218464 cs0 DataBus test pass
1078 16:51:34.223562 cs1 DataBus test pass
1079 16:51:34.224096 cs0 AddrBus test pass
1080 16:51:34.224551 cs1 AddrBus test pass
1081 16:51:34.224994
1082 16:51:34.229216 100bdlr_step_size ps== 420
1083 16:51:34.229740 result report
1084 16:51:34.234797 boot times 0Enable ddr reg access
1085 16:51:34.240266 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 16:51:34.253651 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 16:51:34.827342 0.0;M3 CHK:0;cm4_sp_mode 0
1088 16:51:34.827953 MVN_1=0x00000000
1089 16:51:34.832992 MVN_2=0x00000000
1090 16:51:34.838684 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 16:51:34.839188 OPS=0x10
1092 16:51:34.839643 ring efuse init
1093 16:51:34.840119 chipver efuse init
1094 16:51:34.844266 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 16:51:34.849939 [0.018961 Inits done]
1096 16:51:34.850443 secure task start!
1097 16:51:34.850891 high task start!
1098 16:51:34.854482 low task start!
1099 16:51:34.854988 run into bl31
1100 16:51:34.861228 NOTICE: BL31: v1.3(release):4fc40b1
1101 16:51:34.867969 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 16:51:34.868513 NOTICE: BL31: G12A normal boot!
1103 16:51:34.894856 NOTICE: BL31: BL33 decompress pass
1104 16:51:34.900559 ERROR: Error initializing runtime service opteed_fast
1105 16:51:36.133299
1106 16:51:36.133697
1107 16:51:36.141566 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 16:51:36.141942
1109 16:51:36.142250 Model: Libre Computer AML-A311D-CC Alta
1110 16:51:36.350074 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 16:51:36.372877 DRAM: 2 GiB (effective 3.8 GiB)
1112 16:51:36.516379 Core: 408 devices, 31 uclasses, devicetree: separate
1113 16:51:36.522298 WDT: Not starting watchdog@f0d0
1114 16:51:36.554477 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 16:51:36.567020 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 16:51:36.571969 ** Bad device specification mmc 0 **
1117 16:51:36.582304 Card did not respond to voltage select! : -110
1118 16:51:36.589972 ** Bad device specification mmc 0 **
1119 16:51:36.590251 Couldn't find partition mmc 0
1120 16:51:36.598275 Card did not respond to voltage select! : -110
1121 16:51:36.603800 ** Bad device specification mmc 0 **
1122 16:51:36.604080 Couldn't find partition mmc 0
1123 16:51:36.608872 Error: could not access storage.
1124 16:51:36.952371 Net: eth0: ethernet@ff3f0000
1125 16:51:36.952699 starting USB...
1126 16:51:37.204150 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 16:51:37.204644 Starting the controller
1128 16:51:37.211128 USB XHCI 1.10
1129 16:51:38.765224 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 16:51:38.773630 scanning usb for storage devices... 0 Storage Device(s) found
1132 16:51:38.825364 Hit any key to stop autoboot: 1
1133 16:51:38.826314 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1134 16:51:38.826979 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1135 16:51:38.827476 Setting prompt string to ['=>']
1136 16:51:38.828041 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1137 16:51:38.841102 0
1138 16:51:38.842072 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 16:51:38.842628 Sending with 10 millisecond of delay
1141 16:51:39.977871 => setenv autoload no
1142 16:51:39.988766 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1143 16:51:39.994347 setenv autoload no
1144 16:51:39.995201 Sending with 10 millisecond of delay
1146 16:51:41.794514 => setenv initrd_high 0xffffffff
1147 16:51:41.805504 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1148 16:51:41.806599 setenv initrd_high 0xffffffff
1149 16:51:41.807469 Sending with 10 millisecond of delay
1151 16:51:43.425189 => setenv fdt_high 0xffffffff
1152 16:51:43.436031 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1153 16:51:43.436911 setenv fdt_high 0xffffffff
1154 16:51:43.437655 Sending with 10 millisecond of delay
1156 16:51:43.729656 => dhcp
1157 16:51:43.740516 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1158 16:51:43.741460 dhcp
1159 16:51:43.741942 Speed: 1000, full duplex
1160 16:51:43.742409 BOOTP broadcast 1
1161 16:51:43.915802 DHCP client bound to address 192.168.6.27 (174 ms)
1162 16:51:43.916752 Sending with 10 millisecond of delay
1164 16:51:45.594029 => setenv serverip 192.168.6.2
1165 16:51:45.604851 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
1166 16:51:45.605780 setenv serverip 192.168.6.2
1167 16:51:45.606534 Sending with 10 millisecond of delay
1169 16:51:49.332085 => tftpboot 0x01080000 975418/tftp-deploy-967p0fyb/kernel/uImage
1170 16:51:49.342694 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1171 16:51:49.343306 tftpboot 0x01080000 975418/tftp-deploy-967p0fyb/kernel/uImage
1172 16:51:49.343548 Speed: 1000, full duplex
1173 16:51:49.343758 Using ethernet@ff3f0000 device
1174 16:51:49.345445 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 16:51:49.351024 Filename '975418/tftp-deploy-967p0fyb/kernel/uImage'.
1176 16:51:49.354830 Load address: 0x1080000
1177 16:51:51.860531 Loading: *########################################## UDP wrong checksum 000000ff 0000ac34
1178 16:51:51.910974 # UDP wrong checksum 000000ff 00003727
1179 16:51:52.275866 ####### 43.6 MiB
1180 16:51:52.276549 14.9 MiB/s
1181 16:51:52.277020 done
1182 16:51:52.280224 Bytes transferred = 45713984 (2b98a40 hex)
1183 16:51:52.281022 Sending with 10 millisecond of delay
1185 16:51:56.970012 => tftpboot 0x08000000 975418/tftp-deploy-967p0fyb/ramdisk/ramdisk.cpio.gz.uboot
1186 16:51:56.980816 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1187 16:51:56.981744 tftpboot 0x08000000 975418/tftp-deploy-967p0fyb/ramdisk/ramdisk.cpio.gz.uboot
1188 16:51:56.982209 Speed: 1000, full duplex
1189 16:51:56.982651 Using ethernet@ff3f0000 device
1190 16:51:56.983444 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1191 16:51:56.992146 Filename '975418/tftp-deploy-967p0fyb/ramdisk/ramdisk.cpio.gz.uboot'.
1192 16:51:56.992659 Load address: 0x8000000
1193 16:52:03.706118 Loading: *#################T ################################ UDP wrong checksum 00000005 000048c7
1194 16:52:08.707340 T UDP wrong checksum 00000005 000048c7
1195 16:52:10.326444 UDP wrong checksum 000000ff 00008033
1196 16:52:10.351740 UDP wrong checksum 000000ff 00001726
1197 16:52:18.709374 T T UDP wrong checksum 00000005 000048c7
1198 16:52:22.073910 UDP wrong checksum 000000ff 00008a6a
1199 16:52:22.114257 UDP wrong checksum 000000ff 00001d5d
1200 16:52:37.935497 T T T UDP wrong checksum 000000ff 00009409
1201 16:52:37.947854 UDP wrong checksum 000000ff 00001cfc
1202 16:52:38.713343 T UDP wrong checksum 00000005 000048c7
1203 16:52:53.717515 T T
1204 16:52:53.718193 Retry count exceeded; starting again
1206 16:52:53.719778 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1209 16:52:53.721982 end: 2.4 uboot-commands (duration 00:01:53) [common]
1211 16:52:53.723526 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1213 16:52:53.724759 end: 2 uboot-action (duration 00:01:53) [common]
1215 16:52:53.726403 Cleaning after the job
1216 16:52:53.726994 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975418/tftp-deploy-967p0fyb/ramdisk
1217 16:52:53.728383 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975418/tftp-deploy-967p0fyb/kernel
1218 16:52:53.760788 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975418/tftp-deploy-967p0fyb/dtb
1219 16:52:53.762144 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975418/tftp-deploy-967p0fyb/nfsrootfs
1220 16:52:53.793360 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975418/tftp-deploy-967p0fyb/modules
1221 16:52:53.797589 start: 4.1 power-off (timeout 00:00:30) [common]
1222 16:52:53.798147 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1223 16:52:53.834614 >> OK - accepted request
1224 16:52:53.836880 Returned 0 in 0 seconds
1225 16:52:53.938148 end: 4.1 power-off (duration 00:00:00) [common]
1227 16:52:53.939876 start: 4.2 read-feedback (timeout 00:10:00) [common]
1228 16:52:53.941053 Listened to connection for namespace 'common' for up to 1s
1229 16:52:54.941508 Finalising connection for namespace 'common'
1230 16:52:54.942301 Disconnecting from shell: Finalise
1231 16:52:54.942870 =>
1232 16:52:55.044029 end: 4.2 read-feedback (duration 00:00:01) [common]
1233 16:52:55.044734 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/975418
1234 16:52:57.784007 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/975418
1235 16:52:57.784638 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.