Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 16:46:00.471439 lava-dispatcher, installed at version: 2024.01
2 16:46:00.472297 start: 0 validate
3 16:46:00.472770 Start time: 2024-11-11 16:46:00.472743+00:00 (UTC)
4 16:46:00.473312 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 16:46:00.473860 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 16:46:00.512387 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 16:46:00.512932 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fnext%2Frenesas-next-2024-11-11-v6.12-rc1%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 16:46:00.545905 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 16:46:00.546562 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fnext%2Frenesas-next-2024-11-11-v6.12-rc1%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 16:46:00.581389 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 16:46:00.581903 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 16:46:00.616402 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 16:46:00.616923 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fnext%2Frenesas-next-2024-11-11-v6.12-rc1%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 16:46:00.654573 validate duration: 0.18
16 16:46:00.655427 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 16:46:00.655750 start: 1.1 download-retry (timeout 00:10:00) [common]
18 16:46:00.656087 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 16:46:00.656698 Not decompressing ramdisk as can be used compressed.
20 16:46:00.657153 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 16:46:00.657434 saving as /var/lib/lava/dispatcher/tmp/975395/tftp-deploy-3n8jtr2m/ramdisk/initrd.cpio.gz
22 16:46:00.657705 total size: 5628169 (5 MB)
23 16:46:00.699112 progress 0 % (0 MB)
24 16:46:00.703556 progress 5 % (0 MB)
25 16:46:00.708259 progress 10 % (0 MB)
26 16:46:00.713899 progress 15 % (0 MB)
27 16:46:00.719244 progress 20 % (1 MB)
28 16:46:00.723004 progress 25 % (1 MB)
29 16:46:00.727299 progress 30 % (1 MB)
30 16:46:00.731561 progress 35 % (1 MB)
31 16:46:00.735315 progress 40 % (2 MB)
32 16:46:00.739450 progress 45 % (2 MB)
33 16:46:00.743195 progress 50 % (2 MB)
34 16:46:00.747419 progress 55 % (2 MB)
35 16:46:00.751525 progress 60 % (3 MB)
36 16:46:00.755180 progress 65 % (3 MB)
37 16:46:00.759267 progress 70 % (3 MB)
38 16:46:00.763065 progress 75 % (4 MB)
39 16:46:00.767112 progress 80 % (4 MB)
40 16:46:00.770771 progress 85 % (4 MB)
41 16:46:00.774833 progress 90 % (4 MB)
42 16:46:00.778766 progress 95 % (5 MB)
43 16:46:00.782141 progress 100 % (5 MB)
44 16:46:00.782813 5 MB downloaded in 0.13 s (42.91 MB/s)
45 16:46:00.783359 end: 1.1.1 http-download (duration 00:00:00) [common]
47 16:46:00.784309 end: 1.1 download-retry (duration 00:00:00) [common]
48 16:46:00.784625 start: 1.2 download-retry (timeout 00:10:00) [common]
49 16:46:00.784952 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 16:46:00.785463 downloading http://storage.kernelci.org/renesas/next/renesas-next-2024-11-11-v6.12-rc1/arm64/defconfig/gcc-12/kernel/Image
51 16:46:00.785744 saving as /var/lib/lava/dispatcher/tmp/975395/tftp-deploy-3n8jtr2m/kernel/Image
52 16:46:00.785974 total size: 45713920 (43 MB)
53 16:46:00.786222 No compression specified
54 16:46:00.818459 progress 0 % (0 MB)
55 16:46:00.848136 progress 5 % (2 MB)
56 16:46:00.877405 progress 10 % (4 MB)
57 16:46:00.906782 progress 15 % (6 MB)
58 16:46:00.936476 progress 20 % (8 MB)
59 16:46:00.964991 progress 25 % (10 MB)
60 16:46:00.994760 progress 30 % (13 MB)
61 16:46:01.024085 progress 35 % (15 MB)
62 16:46:01.053346 progress 40 % (17 MB)
63 16:46:01.081894 progress 45 % (19 MB)
64 16:46:01.110435 progress 50 % (21 MB)
65 16:46:01.139826 progress 55 % (24 MB)
66 16:46:01.168920 progress 60 % (26 MB)
67 16:46:01.197914 progress 65 % (28 MB)
68 16:46:01.227052 progress 70 % (30 MB)
69 16:46:01.255775 progress 75 % (32 MB)
70 16:46:01.285205 progress 80 % (34 MB)
71 16:46:01.314132 progress 85 % (37 MB)
72 16:46:01.343868 progress 90 % (39 MB)
73 16:46:01.373723 progress 95 % (41 MB)
74 16:46:01.402389 progress 100 % (43 MB)
75 16:46:01.402967 43 MB downloaded in 0.62 s (70.66 MB/s)
76 16:46:01.403451 end: 1.2.1 http-download (duration 00:00:01) [common]
78 16:46:01.404325 end: 1.2 download-retry (duration 00:00:01) [common]
79 16:46:01.404609 start: 1.3 download-retry (timeout 00:09:59) [common]
80 16:46:01.404879 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 16:46:01.405368 downloading http://storage.kernelci.org/renesas/next/renesas-next-2024-11-11-v6.12-rc1/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 16:46:01.405652 saving as /var/lib/lava/dispatcher/tmp/975395/tftp-deploy-3n8jtr2m/dtb/meson-g12b-a311d-libretech-cc.dtb
83 16:46:01.405862 total size: 54703 (0 MB)
84 16:46:01.406072 No compression specified
85 16:46:01.449727 progress 59 % (0 MB)
86 16:46:01.450590 progress 100 % (0 MB)
87 16:46:01.451153 0 MB downloaded in 0.05 s (1.15 MB/s)
88 16:46:01.451698 end: 1.3.1 http-download (duration 00:00:00) [common]
90 16:46:01.452679 end: 1.3 download-retry (duration 00:00:00) [common]
91 16:46:01.452961 start: 1.4 download-retry (timeout 00:09:59) [common]
92 16:46:01.453230 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 16:46:01.453720 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 16:46:01.453973 saving as /var/lib/lava/dispatcher/tmp/975395/tftp-deploy-3n8jtr2m/nfsrootfs/full.rootfs.tar
95 16:46:01.454181 total size: 120894716 (115 MB)
96 16:46:01.454394 Using unxz to decompress xz
97 16:46:01.492534 progress 0 % (0 MB)
98 16:46:02.337881 progress 5 % (5 MB)
99 16:46:03.181820 progress 10 % (11 MB)
100 16:46:03.979511 progress 15 % (17 MB)
101 16:46:04.720989 progress 20 % (23 MB)
102 16:46:05.318460 progress 25 % (28 MB)
103 16:46:06.153069 progress 30 % (34 MB)
104 16:46:06.945538 progress 35 % (40 MB)
105 16:46:07.295091 progress 40 % (46 MB)
106 16:46:07.670168 progress 45 % (51 MB)
107 16:46:08.408842 progress 50 % (57 MB)
108 16:46:09.291423 progress 55 % (63 MB)
109 16:46:10.073567 progress 60 % (69 MB)
110 16:46:10.831145 progress 65 % (74 MB)
111 16:46:11.611390 progress 70 % (80 MB)
112 16:46:12.441187 progress 75 % (86 MB)
113 16:46:13.228805 progress 80 % (92 MB)
114 16:46:13.991754 progress 85 % (98 MB)
115 16:46:14.970346 progress 90 % (103 MB)
116 16:46:15.792232 progress 95 % (109 MB)
117 16:46:16.629868 progress 100 % (115 MB)
118 16:46:16.642410 115 MB downloaded in 15.19 s (7.59 MB/s)
119 16:46:16.643347 end: 1.4.1 http-download (duration 00:00:15) [common]
121 16:46:16.645143 end: 1.4 download-retry (duration 00:00:15) [common]
122 16:46:16.645707 start: 1.5 download-retry (timeout 00:09:44) [common]
123 16:46:16.646262 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 16:46:16.647139 downloading http://storage.kernelci.org/renesas/next/renesas-next-2024-11-11-v6.12-rc1/arm64/defconfig/gcc-12/modules.tar.xz
125 16:46:16.647638 saving as /var/lib/lava/dispatcher/tmp/975395/tftp-deploy-3n8jtr2m/modules/modules.tar
126 16:46:16.648119 total size: 11608784 (11 MB)
127 16:46:16.648579 Using unxz to decompress xz
128 16:46:16.694321 progress 0 % (0 MB)
129 16:46:16.760282 progress 5 % (0 MB)
130 16:46:16.834477 progress 10 % (1 MB)
131 16:46:16.931998 progress 15 % (1 MB)
132 16:46:17.024552 progress 20 % (2 MB)
133 16:46:17.103955 progress 25 % (2 MB)
134 16:46:17.180181 progress 30 % (3 MB)
135 16:46:17.254874 progress 35 % (3 MB)
136 16:46:17.332338 progress 40 % (4 MB)
137 16:46:17.409304 progress 45 % (5 MB)
138 16:46:17.494738 progress 50 % (5 MB)
139 16:46:17.573074 progress 55 % (6 MB)
140 16:46:17.658164 progress 60 % (6 MB)
141 16:46:17.739045 progress 65 % (7 MB)
142 16:46:17.815633 progress 70 % (7 MB)
143 16:46:17.897736 progress 75 % (8 MB)
144 16:46:17.981087 progress 80 % (8 MB)
145 16:46:18.061257 progress 85 % (9 MB)
146 16:46:18.139784 progress 90 % (9 MB)
147 16:46:18.218540 progress 95 % (10 MB)
148 16:46:18.297150 progress 100 % (11 MB)
149 16:46:18.308784 11 MB downloaded in 1.66 s (6.67 MB/s)
150 16:46:18.309430 end: 1.5.1 http-download (duration 00:00:02) [common]
152 16:46:18.310264 end: 1.5 download-retry (duration 00:00:02) [common]
153 16:46:18.310535 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 16:46:18.310802 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 16:46:36.004741 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/975395/extract-nfsrootfs-vhm_tqr9
156 16:46:36.005351 end: 1.6.1 extract-nfsrootfs (duration 00:00:18) [common]
157 16:46:36.005648 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 16:46:36.006257 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f
159 16:46:36.006703 makedir: /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin
160 16:46:36.007041 makedir: /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/tests
161 16:46:36.007382 makedir: /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/results
162 16:46:36.007754 Creating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-add-keys
163 16:46:36.008474 Creating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-add-sources
164 16:46:36.009609 Creating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-background-process-start
165 16:46:36.010317 Creating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-background-process-stop
166 16:46:36.010927 Creating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-common-functions
167 16:46:36.011476 Creating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-echo-ipv4
168 16:46:36.012045 Creating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-install-packages
169 16:46:36.012623 Creating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-installed-packages
170 16:46:36.013147 Creating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-os-build
171 16:46:36.013662 Creating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-probe-channel
172 16:46:36.014172 Creating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-probe-ip
173 16:46:36.014677 Creating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-target-ip
174 16:46:36.015191 Creating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-target-mac
175 16:46:36.015703 Creating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-target-storage
176 16:46:36.016271 Creating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-test-case
177 16:46:36.016824 Creating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-test-event
178 16:46:36.017346 Creating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-test-feedback
179 16:46:36.017856 Creating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-test-raise
180 16:46:36.018360 Creating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-test-reference
181 16:46:36.018958 Creating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-test-runner
182 16:46:36.019492 Creating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-test-set
183 16:46:36.020028 Creating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-test-shell
184 16:46:36.020589 Updating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-add-keys (debian)
185 16:46:36.021221 Updating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-add-sources (debian)
186 16:46:36.021810 Updating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-install-packages (debian)
187 16:46:36.022984 Updating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-installed-packages (debian)
188 16:46:36.023611 Updating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/bin/lava-os-build (debian)
189 16:46:36.024126 Creating /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/environment
190 16:46:36.024546 LAVA metadata
191 16:46:36.024816 - LAVA_JOB_ID=975395
192 16:46:36.025037 - LAVA_DISPATCHER_IP=192.168.6.2
193 16:46:36.025423 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 16:46:36.026619 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 16:46:36.026974 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 16:46:36.027185 skipped lava-vland-overlay
197 16:46:36.027428 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 16:46:36.027686 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 16:46:36.027907 skipped lava-multinode-overlay
200 16:46:36.028198 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 16:46:36.028456 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 16:46:36.028719 Loading test definitions
203 16:46:36.029006 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 16:46:36.029228 Using /lava-975395 at stage 0
205 16:46:36.030436 uuid=975395_1.6.2.4.1 testdef=None
206 16:46:36.030772 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 16:46:36.031042 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 16:46:36.032724 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 16:46:36.033539 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 16:46:36.035813 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 16:46:36.036696 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 16:46:36.038926 runner path: /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/0/tests/0_timesync-off test_uuid 975395_1.6.2.4.1
215 16:46:36.039609 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 16:46:36.040536 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 16:46:36.040770 Using /lava-975395 at stage 0
219 16:46:36.041185 Fetching tests from https://github.com/kernelci/test-definitions.git
220 16:46:36.041506 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/0/tests/1_kselftest-dt'
221 16:46:39.708901 Running '/usr/bin/git checkout kernelci.org
222 16:46:40.151706 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
223 16:46:40.153220 uuid=975395_1.6.2.4.5 testdef=None
224 16:46:40.153596 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 16:46:40.154369 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 16:46:40.157288 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 16:46:40.158139 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:20) [common]
230 16:46:40.162063 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 16:46:40.162978 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:20) [common]
233 16:46:40.166791 runner path: /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/0/tests/1_kselftest-dt test_uuid 975395_1.6.2.4.5
234 16:46:40.167097 BOARD='meson-g12b-a311d-libretech-cc'
235 16:46:40.167315 BRANCH='renesas'
236 16:46:40.167521 SKIPFILE='/dev/null'
237 16:46:40.167724 SKIP_INSTALL='True'
238 16:46:40.167925 TESTPROG_URL='http://storage.kernelci.org/renesas/next/renesas-next-2024-11-11-v6.12-rc1/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 16:46:40.168152 TST_CASENAME=''
240 16:46:40.168358 TST_CMDFILES='dt'
241 16:46:40.168966 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 16:46:40.169786 Creating lava-test-runner.conf files
244 16:46:40.170002 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/975395/lava-overlay-tljygk2f/lava-975395/0 for stage 0
245 16:46:40.170386 - 0_timesync-off
246 16:46:40.170644 - 1_kselftest-dt
247 16:46:40.171003 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 16:46:40.171302 start: 1.6.2.5 compress-overlay (timeout 00:09:20) [common]
249 16:47:03.956294 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
250 16:47:03.956760 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:57) [common]
251 16:47:03.957029 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 16:47:03.957302 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
253 16:47:03.957567 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:57) [common]
254 16:47:04.633316 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 16:47:04.633793 start: 1.6.4 extract-modules (timeout 00:08:56) [common]
256 16:47:04.634050 extracting modules file /var/lib/lava/dispatcher/tmp/975395/tftp-deploy-3n8jtr2m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/975395/extract-nfsrootfs-vhm_tqr9
257 16:47:06.200248 extracting modules file /var/lib/lava/dispatcher/tmp/975395/tftp-deploy-3n8jtr2m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/975395/extract-overlay-ramdisk-th1i_a8j/ramdisk
258 16:47:07.624244 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 16:47:07.624741 start: 1.6.5 apply-overlay-tftp (timeout 00:08:53) [common]
260 16:47:07.625023 [common] Applying overlay to NFS
261 16:47:07.625242 [common] Applying overlay /var/lib/lava/dispatcher/tmp/975395/compress-overlay-4ntk6zv2/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/975395/extract-nfsrootfs-vhm_tqr9
262 16:47:10.438283 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 16:47:10.438758 start: 1.6.6 prepare-kernel (timeout 00:08:50) [common]
264 16:47:10.439034 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:50) [common]
265 16:47:10.439265 Converting downloaded kernel to a uImage
266 16:47:10.439579 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/975395/tftp-deploy-3n8jtr2m/kernel/Image /var/lib/lava/dispatcher/tmp/975395/tftp-deploy-3n8jtr2m/kernel/uImage
267 16:47:10.946321 output: Image Name:
268 16:47:10.946747 output: Created: Mon Nov 11 16:47:10 2024
269 16:47:10.946954 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 16:47:10.947156 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 16:47:10.947356 output: Load Address: 01080000
272 16:47:10.947553 output: Entry Point: 01080000
273 16:47:10.947751 output:
274 16:47:10.948114 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 16:47:10.948393 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 16:47:10.948663 start: 1.6.7 configure-preseed-file (timeout 00:08:50) [common]
277 16:47:10.948918 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 16:47:10.949174 start: 1.6.8 compress-ramdisk (timeout 00:08:50) [common]
279 16:47:10.949444 Building ramdisk /var/lib/lava/dispatcher/tmp/975395/extract-overlay-ramdisk-th1i_a8j/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/975395/extract-overlay-ramdisk-th1i_a8j/ramdisk
280 16:47:13.125801 >> 166783 blocks
281 16:47:21.750510 Adding RAMdisk u-boot header.
282 16:47:21.751194 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/975395/extract-overlay-ramdisk-th1i_a8j/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/975395/extract-overlay-ramdisk-th1i_a8j/ramdisk.cpio.gz.uboot
283 16:47:22.607914 output: Image Name:
284 16:47:22.608639 output: Created: Mon Nov 11 16:47:21 2024
285 16:47:22.609100 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 16:47:22.609546 output: Data Size: 23428935 Bytes = 22879.82 KiB = 22.34 MiB
287 16:47:22.609984 output: Load Address: 00000000
288 16:47:22.610424 output: Entry Point: 00000000
289 16:47:22.610860 output:
290 16:47:22.612153 rename /var/lib/lava/dispatcher/tmp/975395/extract-overlay-ramdisk-th1i_a8j/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/975395/tftp-deploy-3n8jtr2m/ramdisk/ramdisk.cpio.gz.uboot
291 16:47:22.612933 end: 1.6.8 compress-ramdisk (duration 00:00:12) [common]
292 16:47:22.613532 end: 1.6 prepare-tftp-overlay (duration 00:01:04) [common]
293 16:47:22.614144 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:38) [common]
294 16:47:22.614632 No LXC device requested
295 16:47:22.615175 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 16:47:22.615729 start: 1.8 deploy-device-env (timeout 00:08:38) [common]
297 16:47:22.616311 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 16:47:22.616763 Checking files for TFTP limit of 4294967296 bytes.
299 16:47:22.619725 end: 1 tftp-deploy (duration 00:01:22) [common]
300 16:47:22.620391 start: 2 uboot-action (timeout 00:05:00) [common]
301 16:47:22.620970 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 16:47:22.621515 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 16:47:22.622069 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 16:47:22.622647 Using kernel file from prepare-kernel: 975395/tftp-deploy-3n8jtr2m/kernel/uImage
305 16:47:22.623333 substitutions:
306 16:47:22.623780 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 16:47:22.624262 - {DTB_ADDR}: 0x01070000
308 16:47:22.624707 - {DTB}: 975395/tftp-deploy-3n8jtr2m/dtb/meson-g12b-a311d-libretech-cc.dtb
309 16:47:22.625153 - {INITRD}: 975395/tftp-deploy-3n8jtr2m/ramdisk/ramdisk.cpio.gz.uboot
310 16:47:22.625592 - {KERNEL_ADDR}: 0x01080000
311 16:47:22.626026 - {KERNEL}: 975395/tftp-deploy-3n8jtr2m/kernel/uImage
312 16:47:22.626457 - {LAVA_MAC}: None
313 16:47:22.626952 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/975395/extract-nfsrootfs-vhm_tqr9
314 16:47:22.627391 - {NFS_SERVER_IP}: 192.168.6.2
315 16:47:22.627822 - {PRESEED_CONFIG}: None
316 16:47:22.628337 - {PRESEED_LOCAL}: None
317 16:47:22.628776 - {RAMDISK_ADDR}: 0x08000000
318 16:47:22.629204 - {RAMDISK}: 975395/tftp-deploy-3n8jtr2m/ramdisk/ramdisk.cpio.gz.uboot
319 16:47:22.629636 - {ROOT_PART}: None
320 16:47:22.630063 - {ROOT}: None
321 16:47:22.630490 - {SERVER_IP}: 192.168.6.2
322 16:47:22.630916 - {TEE_ADDR}: 0x83000000
323 16:47:22.631340 - {TEE}: None
324 16:47:22.631765 Parsed boot commands:
325 16:47:22.632214 - setenv autoload no
326 16:47:22.632646 - setenv initrd_high 0xffffffff
327 16:47:22.633072 - setenv fdt_high 0xffffffff
328 16:47:22.633496 - dhcp
329 16:47:22.633918 - setenv serverip 192.168.6.2
330 16:47:22.634345 - tftpboot 0x01080000 975395/tftp-deploy-3n8jtr2m/kernel/uImage
331 16:47:22.634775 - tftpboot 0x08000000 975395/tftp-deploy-3n8jtr2m/ramdisk/ramdisk.cpio.gz.uboot
332 16:47:22.635205 - tftpboot 0x01070000 975395/tftp-deploy-3n8jtr2m/dtb/meson-g12b-a311d-libretech-cc.dtb
333 16:47:22.635635 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/975395/extract-nfsrootfs-vhm_tqr9,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 16:47:22.636104 - bootm 0x01080000 0x08000000 0x01070000
335 16:47:22.636651 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 16:47:22.638267 start: 2.3 connect-device (timeout 00:05:00) [common]
338 16:47:22.638724 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 16:47:22.654457 Setting prompt string to ['lava-test: # ']
340 16:47:22.656137 end: 2.3 connect-device (duration 00:00:00) [common]
341 16:47:22.656815 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 16:47:22.657437 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 16:47:22.658028 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 16:47:22.659266 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 16:47:22.694828 >> OK - accepted request
346 16:47:22.696947 Returned 0 in 0 seconds
347 16:47:22.798102 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 16:47:22.799820 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 16:47:22.800478 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 16:47:22.801026 Setting prompt string to ['Hit any key to stop autoboot']
352 16:47:22.801518 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 16:47:22.803284 Trying 192.168.56.21...
354 16:47:22.803830 Connected to conserv1.
355 16:47:22.804354 Escape character is '^]'.
356 16:47:22.804809
357 16:47:22.805265 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 16:47:22.805744
359 16:47:33.989421 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 16:47:33.990073 bl2_stage_init 0x01
361 16:47:33.990555 bl2_stage_init 0x81
362 16:47:33.995040 hw id: 0x0000 - pwm id 0x01
363 16:47:33.995624 bl2_stage_init 0xc1
364 16:47:33.996148 bl2_stage_init 0x02
365 16:47:33.996605
366 16:47:34.000439 L0:00000000
367 16:47:34.000948 L1:20000703
368 16:47:34.001404 L2:00008067
369 16:47:34.001852 L3:14000000
370 16:47:34.003340 B2:00402000
371 16:47:34.003825 B1:e0f83180
372 16:47:34.004310
373 16:47:34.004746 TE: 58167
374 16:47:34.005182
375 16:47:34.014561 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 16:47:34.015030
377 16:47:34.015463 Board ID = 1
378 16:47:34.015891 Set A53 clk to 24M
379 16:47:34.016383 Set A73 clk to 24M
380 16:47:34.020349 Set clk81 to 24M
381 16:47:34.020868 A53 clk: 1200 MHz
382 16:47:34.021304 A73 clk: 1200 MHz
383 16:47:34.025798 CLK81: 166.6M
384 16:47:34.026340 smccc: 00012abe
385 16:47:34.031332 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 16:47:34.031855 board id: 1
387 16:47:34.039893 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 16:47:34.050478 fw parse done
389 16:47:34.056501 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 16:47:34.098981 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 16:47:34.109816 PIEI prepare done
392 16:47:34.110275 fastboot data load
393 16:47:34.110709 fastboot data verify
394 16:47:34.115562 verify result: 266
395 16:47:34.121189 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 16:47:34.121666 LPDDR4 probe
397 16:47:34.122121 ddr clk to 1584MHz
398 16:47:34.129101 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 16:47:34.166387
400 16:47:34.166913 dmc_version 0001
401 16:47:34.173009 Check phy result
402 16:47:34.178970 INFO : End of CA training
403 16:47:34.179443 INFO : End of initialization
404 16:47:34.184535 INFO : Training has run successfully!
405 16:47:34.185018 Check phy result
406 16:47:34.190207 INFO : End of initialization
407 16:47:34.190675 INFO : End of read enable training
408 16:47:34.195695 INFO : End of fine write leveling
409 16:47:34.201291 INFO : End of Write leveling coarse delay
410 16:47:34.201758 INFO : Training has run successfully!
411 16:47:34.202204 Check phy result
412 16:47:34.206958 INFO : End of initialization
413 16:47:34.207426 INFO : End of read dq deskew training
414 16:47:34.212496 INFO : End of MPR read delay center optimization
415 16:47:34.218233 INFO : End of write delay center optimization
416 16:47:34.223715 INFO : End of read delay center optimization
417 16:47:34.224238 INFO : End of max read latency training
418 16:47:34.229316 INFO : Training has run successfully!
419 16:47:34.229790 1D training succeed
420 16:47:34.238529 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 16:47:34.286036 Check phy result
422 16:47:34.286511 INFO : End of initialization
423 16:47:34.308735 INFO : End of 2D read delay Voltage center optimization
424 16:47:34.328964 INFO : End of 2D read delay Voltage center optimization
425 16:47:34.381136 INFO : End of 2D write delay Voltage center optimization
426 16:47:34.430313 INFO : End of 2D write delay Voltage center optimization
427 16:47:34.435873 INFO : Training has run successfully!
428 16:47:34.436412
429 16:47:34.436885 channel==0
430 16:47:34.441454 RxClkDly_Margin_A0==88 ps 9
431 16:47:34.441950 TxDqDly_Margin_A0==98 ps 10
432 16:47:34.447053 RxClkDly_Margin_A1==88 ps 9
433 16:47:34.447527 TxDqDly_Margin_A1==98 ps 10
434 16:47:34.448011 TrainedVREFDQ_A0==74
435 16:47:34.452627 TrainedVREFDQ_A1==74
436 16:47:34.453119 VrefDac_Margin_A0==25
437 16:47:34.453570 DeviceVref_Margin_A0==40
438 16:47:34.458230 VrefDac_Margin_A1==25
439 16:47:34.458702 DeviceVref_Margin_A1==40
440 16:47:34.459148
441 16:47:34.459595
442 16:47:34.463873 channel==1
443 16:47:34.464374 RxClkDly_Margin_A0==98 ps 10
444 16:47:34.464823 TxDqDly_Margin_A0==98 ps 10
445 16:47:34.469475 RxClkDly_Margin_A1==88 ps 9
446 16:47:34.469949 TxDqDly_Margin_A1==88 ps 9
447 16:47:34.475035 TrainedVREFDQ_A0==77
448 16:47:34.475513 TrainedVREFDQ_A1==77
449 16:47:34.475962 VrefDac_Margin_A0==22
450 16:47:34.480641 DeviceVref_Margin_A0==37
451 16:47:34.481115 VrefDac_Margin_A1==24
452 16:47:34.486221 DeviceVref_Margin_A1==37
453 16:47:34.486698
454 16:47:34.487145 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 16:47:34.487590
456 16:47:34.519897 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 0000001a 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
457 16:47:34.520499 2D training succeed
458 16:47:34.525476 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 16:47:34.531019 auto size-- 65535DDR cs0 size: 2048MB
460 16:47:34.531494 DDR cs1 size: 2048MB
461 16:47:34.536653 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 16:47:34.537129 cs0 DataBus test pass
463 16:47:34.542282 cs1 DataBus test pass
464 16:47:34.542749 cs0 AddrBus test pass
465 16:47:34.543198 cs1 AddrBus test pass
466 16:47:34.543635
467 16:47:34.547888 100bdlr_step_size ps== 420
468 16:47:34.548404 result report
469 16:47:34.553428 boot times 0Enable ddr reg access
470 16:47:34.558821 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 16:47:34.572342 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 16:47:35.146007 0.0;M3 CHK:0;cm4_sp_mode 0
473 16:47:35.146661 MVN_1=0x00000000
474 16:47:35.151446 MVN_2=0x00000000
475 16:47:35.157284 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 16:47:35.157777 OPS=0x10
477 16:47:35.158231 ring efuse init
478 16:47:35.158672 chipver efuse init
479 16:47:35.162771 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 16:47:35.168465 [0.018961 Inits done]
481 16:47:35.168951 secure task start!
482 16:47:35.169397 high task start!
483 16:47:35.172978 low task start!
484 16:47:35.173445 run into bl31
485 16:47:35.179660 NOTICE: BL31: v1.3(release):4fc40b1
486 16:47:35.187445 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 16:47:35.187927 NOTICE: BL31: G12A normal boot!
488 16:47:35.212790 NOTICE: BL31: BL33 decompress pass
489 16:47:35.218492 ERROR: Error initializing runtime service opteed_fast
490 16:47:36.451484
491 16:47:36.452204
492 16:47:36.459748 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 16:47:36.460270
494 16:47:36.460733 Model: Libre Computer AML-A311D-CC Alta
495 16:47:36.668249 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 16:47:36.691577 DRAM: 2 GiB (effective 3.8 GiB)
497 16:47:36.834542 Core: 408 devices, 31 uclasses, devicetree: separate
498 16:47:36.840458 WDT: Not starting watchdog@f0d0
499 16:47:36.872713 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 16:47:36.885161 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 16:47:36.890202 ** Bad device specification mmc 0 **
502 16:47:36.900546 Card did not respond to voltage select! : -110
503 16:47:36.908157 ** Bad device specification mmc 0 **
504 16:47:36.908628 Couldn't find partition mmc 0
505 16:47:36.916528 Card did not respond to voltage select! : -110
506 16:47:36.922029 ** Bad device specification mmc 0 **
507 16:47:36.922515 Couldn't find partition mmc 0
508 16:47:36.927043 Error: could not access storage.
509 16:47:38.189598 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 16:47:38.190257 bl2_stage_init 0x01
511 16:47:38.190736 bl2_stage_init 0x81
512 16:47:38.195121 hw id: 0x0000 - pwm id 0x01
513 16:47:38.195623 bl2_stage_init 0xc1
514 16:47:38.196125 bl2_stage_init 0x02
515 16:47:38.196584
516 16:47:38.200686 L0:00000000
517 16:47:38.201162 L1:20000703
518 16:47:38.201609 L2:00008067
519 16:47:38.202054 L3:14000000
520 16:47:38.206312 B2:00402000
521 16:47:38.206787 B1:e0f83180
522 16:47:38.207236
523 16:47:38.207683 TE: 58159
524 16:47:38.208164
525 16:47:38.211905 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 16:47:38.212418
527 16:47:38.212872 Board ID = 1
528 16:47:38.217503 Set A53 clk to 24M
529 16:47:38.217994 Set A73 clk to 24M
530 16:47:38.218446 Set clk81 to 24M
531 16:47:38.223143 A53 clk: 1200 MHz
532 16:47:38.223614 A73 clk: 1200 MHz
533 16:47:38.224089 CLK81: 166.6M
534 16:47:38.224536 smccc: 00012ab5
535 16:47:38.228813 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 16:47:38.234390 board id: 1
537 16:47:38.240368 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 16:47:38.250950 fw parse done
539 16:47:38.256873 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 16:47:38.299567 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 16:47:38.310399 PIEI prepare done
542 16:47:38.310903 fastboot data load
543 16:47:38.311362 fastboot data verify
544 16:47:38.316077 verify result: 266
545 16:47:38.321581 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 16:47:38.322061 LPDDR4 probe
547 16:47:38.322508 ddr clk to 1584MHz
548 16:47:38.329549 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 16:47:38.366983
550 16:47:38.367500 dmc_version 0001
551 16:47:38.373570 Check phy result
552 16:47:38.379445 INFO : End of CA training
553 16:47:38.379921 INFO : End of initialization
554 16:47:38.384964 INFO : Training has run successfully!
555 16:47:38.385437 Check phy result
556 16:47:38.390547 INFO : End of initialization
557 16:47:38.391009 INFO : End of read enable training
558 16:47:38.396304 INFO : End of fine write leveling
559 16:47:38.401840 INFO : End of Write leveling coarse delay
560 16:47:38.402602 INFO : Training has run successfully!
561 16:47:38.403138 Check phy result
562 16:47:38.407417 INFO : End of initialization
563 16:47:38.407972 INFO : End of read dq deskew training
564 16:47:38.413046 INFO : End of MPR read delay center optimization
565 16:47:38.418614 INFO : End of write delay center optimization
566 16:47:38.424244 INFO : End of read delay center optimization
567 16:47:38.424731 INFO : End of max read latency training
568 16:47:38.429797 INFO : Training has run successfully!
569 16:47:38.430277 1D training succeed
570 16:47:38.439009 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 16:47:38.486633 Check phy result
572 16:47:38.487140 INFO : End of initialization
573 16:47:38.508244 INFO : End of 2D read delay Voltage center optimization
574 16:47:38.527491 INFO : End of 2D read delay Voltage center optimization
575 16:47:38.579366 INFO : End of 2D write delay Voltage center optimization
576 16:47:38.628667 INFO : End of 2D write delay Voltage center optimization
577 16:47:38.634192 INFO : Training has run successfully!
578 16:47:38.634679
579 16:47:38.635136 channel==0
580 16:47:38.639802 RxClkDly_Margin_A0==88 ps 9
581 16:47:38.640315 TxDqDly_Margin_A0==98 ps 10
582 16:47:38.645380 RxClkDly_Margin_A1==88 ps 9
583 16:47:38.645852 TxDqDly_Margin_A1==88 ps 9
584 16:47:38.646305 TrainedVREFDQ_A0==74
585 16:47:38.650985 TrainedVREFDQ_A1==74
586 16:47:38.651460 VrefDac_Margin_A0==25
587 16:47:38.651907 DeviceVref_Margin_A0==40
588 16:47:38.656626 VrefDac_Margin_A1==25
589 16:47:38.657096 DeviceVref_Margin_A1==40
590 16:47:38.657542
591 16:47:38.657991
592 16:47:38.658436 channel==1
593 16:47:38.662110 RxClkDly_Margin_A0==88 ps 9
594 16:47:38.662584 TxDqDly_Margin_A0==98 ps 10
595 16:47:38.667837 RxClkDly_Margin_A1==88 ps 9
596 16:47:38.668342 TxDqDly_Margin_A1==88 ps 9
597 16:47:38.673392 TrainedVREFDQ_A0==77
598 16:47:38.673864 TrainedVREFDQ_A1==77
599 16:47:38.674312 VrefDac_Margin_A0==23
600 16:47:38.678965 DeviceVref_Margin_A0==37
601 16:47:38.679436 VrefDac_Margin_A1==24
602 16:47:38.684561 DeviceVref_Margin_A1==37
603 16:47:38.685033
604 16:47:38.685481 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 16:47:38.685926
606 16:47:38.718217 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000019 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
607 16:47:38.718734 2D training succeed
608 16:47:38.723893 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 16:47:38.729324 auto size-- 65535DDR cs0 size: 2048MB
610 16:47:38.729799 DDR cs1 size: 2048MB
611 16:47:38.734977 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 16:47:38.735455 cs0 DataBus test pass
613 16:47:38.740604 cs1 DataBus test pass
614 16:47:38.741094 cs0 AddrBus test pass
615 16:47:38.741544 cs1 AddrBus test pass
616 16:47:38.741985
617 16:47:38.746144 100bdlr_step_size ps== 420
618 16:47:38.746632 result report
619 16:47:38.751827 boot times 0Enable ddr reg access
620 16:47:38.756986 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 16:47:38.770391 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 16:47:39.342844 0.0;M3 CHK:0;cm4_sp_mode 0
623 16:47:39.343525 MVN_1=0x00000000
624 16:47:39.348264 MVN_2=0x00000000
625 16:47:39.353978 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 16:47:39.354530 OPS=0x10
627 16:47:39.354994 ring efuse init
628 16:47:39.355471 chipver efuse init
629 16:47:39.362160 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 16:47:39.362707 [0.018961 Inits done]
631 16:47:39.363141 secure task start!
632 16:47:39.369526 high task start!
633 16:47:39.370002 low task start!
634 16:47:39.370436 run into bl31
635 16:47:39.376196 NOTICE: BL31: v1.3(release):4fc40b1
636 16:47:39.384052 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 16:47:39.384527 NOTICE: BL31: G12A normal boot!
638 16:47:39.409328 NOTICE: BL31: BL33 decompress pass
639 16:47:39.415035 ERROR: Error initializing runtime service opteed_fast
640 16:47:40.648086
641 16:47:40.648724
642 16:47:40.656305 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 16:47:40.656805
644 16:47:40.657264 Model: Libre Computer AML-A311D-CC Alta
645 16:47:40.864390 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 16:47:40.888289 DRAM: 2 GiB (effective 3.8 GiB)
647 16:47:41.031118 Core: 408 devices, 31 uclasses, devicetree: separate
648 16:47:41.037034 WDT: Not starting watchdog@f0d0
649 16:47:41.069355 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 16:47:41.081726 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 16:47:41.086623 ** Bad device specification mmc 0 **
652 16:47:41.096943 Card did not respond to voltage select! : -110
653 16:47:41.104604 ** Bad device specification mmc 0 **
654 16:47:41.105099 Couldn't find partition mmc 0
655 16:47:41.112961 Card did not respond to voltage select! : -110
656 16:47:41.118585 ** Bad device specification mmc 0 **
657 16:47:41.119084 Couldn't find partition mmc 0
658 16:47:41.123085 Error: could not access storage.
659 16:47:41.467107 Net: eth0: ethernet@ff3f0000
660 16:47:41.467759 starting USB...
661 16:47:41.718946 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 16:47:41.719507 Starting the controller
663 16:47:41.725135 USB XHCI 1.10
664 16:47:43.441549 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 16:47:43.442201 bl2_stage_init 0x01
666 16:47:43.442686 bl2_stage_init 0x81
667 16:47:43.447077 hw id: 0x0000 - pwm id 0x01
668 16:47:43.447566 bl2_stage_init 0xc1
669 16:47:43.448103 bl2_stage_init 0x02
670 16:47:43.448568
671 16:47:43.452860 L0:00000000
672 16:47:43.453344 L1:20000703
673 16:47:43.453798 L2:00008067
674 16:47:43.454242 L3:14000000
675 16:47:43.455801 B2:00402000
676 16:47:43.456316 B1:e0f83180
677 16:47:43.456766
678 16:47:43.457215 TE: 58167
679 16:47:43.457664
680 16:47:43.466936 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 16:47:43.467437
682 16:47:43.467892 Board ID = 1
683 16:47:43.468379 Set A53 clk to 24M
684 16:47:43.468822 Set A73 clk to 24M
685 16:47:43.472341 Set clk81 to 24M
686 16:47:43.472828 A53 clk: 1200 MHz
687 16:47:43.473277 A73 clk: 1200 MHz
688 16:47:43.476325 CLK81: 166.6M
689 16:47:43.476808 smccc: 00012abe
690 16:47:43.481884 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 16:47:43.482379 board id: 1
692 16:47:43.492251 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 16:47:43.502675 fw parse done
694 16:47:43.508582 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 16:47:43.551240 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 16:47:43.562187 PIEI prepare done
697 16:47:43.562682 fastboot data load
698 16:47:43.563147 fastboot data verify
699 16:47:43.567764 verify result: 266
700 16:47:43.573378 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 16:47:43.573864 LPDDR4 probe
702 16:47:43.574317 ddr clk to 1584MHz
703 16:47:43.581363 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 16:47:43.618605
705 16:47:43.619121 dmc_version 0001
706 16:47:43.625241 Check phy result
707 16:47:43.631115 INFO : End of CA training
708 16:47:43.631594 INFO : End of initialization
709 16:47:43.636754 INFO : Training has run successfully!
710 16:47:43.637235 Check phy result
711 16:47:43.642356 INFO : End of initialization
712 16:47:43.642854 INFO : End of read enable training
713 16:47:43.645690 INFO : End of fine write leveling
714 16:47:43.651256 INFO : End of Write leveling coarse delay
715 16:47:43.656885 INFO : Training has run successfully!
716 16:47:43.657357 Check phy result
717 16:47:43.657809 INFO : End of initialization
718 16:47:43.662510 INFO : End of read dq deskew training
719 16:47:43.668029 INFO : End of MPR read delay center optimization
720 16:47:43.668506 INFO : End of write delay center optimization
721 16:47:43.673677 INFO : End of read delay center optimization
722 16:47:43.679300 INFO : End of max read latency training
723 16:47:43.679776 INFO : Training has run successfully!
724 16:47:43.684901 1D training succeed
725 16:47:43.690734 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 16:47:43.738320 Check phy result
727 16:47:43.738828 INFO : End of initialization
728 16:47:43.760912 INFO : End of 2D read delay Voltage center optimization
729 16:47:43.781186 INFO : End of 2D read delay Voltage center optimization
730 16:47:43.833169 INFO : End of 2D write delay Voltage center optimization
731 16:47:43.882580 INFO : End of 2D write delay Voltage center optimization
732 16:47:43.888204 INFO : Training has run successfully!
733 16:47:43.888686
734 16:47:43.889141 channel==0
735 16:47:43.893691 RxClkDly_Margin_A0==88 ps 9
736 16:47:43.894172 TxDqDly_Margin_A0==98 ps 10
737 16:47:43.899301 RxClkDly_Margin_A1==88 ps 9
738 16:47:43.899773 TxDqDly_Margin_A1==98 ps 10
739 16:47:43.900273 TrainedVREFDQ_A0==74
740 16:47:43.904921 TrainedVREFDQ_A1==74
741 16:47:43.905414 VrefDac_Margin_A0==25
742 16:47:43.905864 DeviceVref_Margin_A0==40
743 16:47:43.910554 VrefDac_Margin_A1==26
744 16:47:43.911026 DeviceVref_Margin_A1==40
745 16:47:43.911477
746 16:47:43.911924
747 16:47:43.916126 channel==1
748 16:47:43.916630 RxClkDly_Margin_A0==98 ps 10
749 16:47:43.917089 TxDqDly_Margin_A0==88 ps 9
750 16:47:43.921670 RxClkDly_Margin_A1==88 ps 9
751 16:47:43.922154 TxDqDly_Margin_A1==98 ps 10
752 16:47:43.927331 TrainedVREFDQ_A0==76
753 16:47:43.927856 TrainedVREFDQ_A1==77
754 16:47:43.928359 VrefDac_Margin_A0==22
755 16:47:43.932896 DeviceVref_Margin_A0==38
756 16:47:43.933386 VrefDac_Margin_A1==24
757 16:47:43.938572 DeviceVref_Margin_A1==37
758 16:47:43.939057
759 16:47:43.939514 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 16:47:43.939964
761 16:47:43.972130 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000017 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
762 16:47:43.972699 2D training succeed
763 16:47:43.977749 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 16:47:43.983351 auto size-- 65535DDR cs0 size: 2048MB
765 16:47:43.983855 DDR cs1 size: 2048MB
766 16:47:43.988884 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 16:47:43.989392 cs0 DataBus test pass
768 16:47:43.994591 cs1 DataBus test pass
769 16:47:43.995086 cs0 AddrBus test pass
770 16:47:43.995539 cs1 AddrBus test pass
771 16:47:43.996025
772 16:47:44.000208 100bdlr_step_size ps== 420
773 16:47:44.000717 result report
774 16:47:44.005754 boot times 0Enable ddr reg access
775 16:47:44.011017 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 16:47:44.024515 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 16:47:44.599884 0.0;M3 CHK:0;cm4_sp_mode 0
778 16:47:44.600598 MVN_1=0x00000000
779 16:47:44.604403 MVN_2=0x00000000
780 16:47:44.611731 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 16:47:44.612381 OPS=0x10
782 16:47:44.612832 ring efuse init
783 16:47:44.613266 chipver efuse init
784 16:47:44.615383 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 16:47:44.620809 [0.018961 Inits done]
786 16:47:44.621409 secure task start!
787 16:47:44.621875 high task start!
788 16:47:44.624582 low task start!
789 16:47:44.625097 run into bl31
790 16:47:44.631905 NOTICE: BL31: v1.3(release):4fc40b1
791 16:47:44.639697 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 16:47:44.640229 NOTICE: BL31: G12A normal boot!
793 16:47:44.665081 NOTICE: BL31: BL33 decompress pass
794 16:47:44.670756 ERROR: Error initializing runtime service opteed_fast
795 16:47:45.903649
796 16:47:45.904358
797 16:47:45.912014 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 16:47:45.912516
799 16:47:45.912973 Model: Libre Computer AML-A311D-CC Alta
800 16:47:46.120391 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 16:47:46.143876 DRAM: 2 GiB (effective 3.8 GiB)
802 16:47:46.286898 Core: 408 devices, 31 uclasses, devicetree: separate
803 16:47:46.292673 WDT: Not starting watchdog@f0d0
804 16:47:46.324915 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 16:47:46.337385 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 16:47:46.342467 ** Bad device specification mmc 0 **
807 16:47:46.352884 Card did not respond to voltage select! : -110
808 16:47:46.360324 ** Bad device specification mmc 0 **
809 16:47:46.360819 Couldn't find partition mmc 0
810 16:47:46.368864 Card did not respond to voltage select! : -110
811 16:47:46.374269 ** Bad device specification mmc 0 **
812 16:47:46.374770 Couldn't find partition mmc 0
813 16:47:46.379251 Error: could not access storage.
814 16:47:46.722782 Net: eth0: ethernet@ff3f0000
815 16:47:46.723342 starting USB...
816 16:47:46.974598 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 16:47:46.975129 Starting the controller
818 16:47:46.981541 USB XHCI 1.10
819 16:47:49.140031 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 16:47:49.140698 bl2_stage_init 0x01
821 16:47:49.141170 bl2_stage_init 0x81
822 16:47:49.145708 hw id: 0x0000 - pwm id 0x01
823 16:47:49.146197 bl2_stage_init 0xc1
824 16:47:49.146659 bl2_stage_init 0x02
825 16:47:49.147106
826 16:47:49.151091 L0:00000000
827 16:47:49.151569 L1:20000703
828 16:47:49.152047 L2:00008067
829 16:47:49.152497 L3:14000000
830 16:47:49.156901 B2:00402000
831 16:47:49.157379 B1:e0f83180
832 16:47:49.157825
833 16:47:49.158271 TE: 58124
834 16:47:49.158722
835 16:47:49.162518 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 16:47:49.163001
837 16:47:49.163452 Board ID = 1
838 16:47:49.168068 Set A53 clk to 24M
839 16:47:49.168554 Set A73 clk to 24M
840 16:47:49.169000 Set clk81 to 24M
841 16:47:49.174015 A53 clk: 1200 MHz
842 16:47:49.174487 A73 clk: 1200 MHz
843 16:47:49.174941 CLK81: 166.6M
844 16:47:49.175382 smccc: 00012a91
845 16:47:49.179182 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 16:47:49.184728 board id: 1
847 16:47:49.190745 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 16:47:49.201224 fw parse done
849 16:47:49.207067 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 16:47:49.249730 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 16:47:49.260587 PIEI prepare done
852 16:47:49.261069 fastboot data load
853 16:47:49.261521 fastboot data verify
854 16:47:49.266314 verify result: 266
855 16:47:49.271934 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 16:47:49.272451 LPDDR4 probe
857 16:47:49.272903 ddr clk to 1584MHz
858 16:47:49.279815 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 16:47:49.317052
860 16:47:49.317553 dmc_version 0001
861 16:47:49.323737 Check phy result
862 16:47:49.329680 INFO : End of CA training
863 16:47:49.330174 INFO : End of initialization
864 16:47:49.335300 INFO : Training has run successfully!
865 16:47:49.335785 Check phy result
866 16:47:49.340996 INFO : End of initialization
867 16:47:49.341486 INFO : End of read enable training
868 16:47:49.346570 INFO : End of fine write leveling
869 16:47:49.352058 INFO : End of Write leveling coarse delay
870 16:47:49.352558 INFO : Training has run successfully!
871 16:47:49.353015 Check phy result
872 16:47:49.357614 INFO : End of initialization
873 16:47:49.358103 INFO : End of read dq deskew training
874 16:47:49.363294 INFO : End of MPR read delay center optimization
875 16:47:49.368853 INFO : End of write delay center optimization
876 16:47:49.374435 INFO : End of read delay center optimization
877 16:47:49.374920 INFO : End of max read latency training
878 16:47:49.380061 INFO : Training has run successfully!
879 16:47:49.380563 1D training succeed
880 16:47:49.389366 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 16:47:49.436878 Check phy result
882 16:47:49.437423 INFO : End of initialization
883 16:47:49.458699 INFO : End of 2D read delay Voltage center optimization
884 16:47:49.477937 INFO : End of 2D read delay Voltage center optimization
885 16:47:49.530919 INFO : End of 2D write delay Voltage center optimization
886 16:47:49.580392 INFO : End of 2D write delay Voltage center optimization
887 16:47:49.585819 INFO : Training has run successfully!
888 16:47:49.586293
889 16:47:49.586749 channel==0
890 16:47:49.591455 RxClkDly_Margin_A0==88 ps 9
891 16:47:49.591930 TxDqDly_Margin_A0==98 ps 10
892 16:47:49.596950 RxClkDly_Margin_A1==88 ps 9
893 16:47:49.597429 TxDqDly_Margin_A1==98 ps 10
894 16:47:49.597885 TrainedVREFDQ_A0==74
895 16:47:49.602627 TrainedVREFDQ_A1==75
896 16:47:49.603105 VrefDac_Margin_A0==25
897 16:47:49.603570 DeviceVref_Margin_A0==40
898 16:47:49.608275 VrefDac_Margin_A1==25
899 16:47:49.608789 DeviceVref_Margin_A1==39
900 16:47:49.609224
901 16:47:49.609657
902 16:47:49.615161 channel==1
903 16:47:49.615703 RxClkDly_Margin_A0==98 ps 10
904 16:47:49.616202 TxDqDly_Margin_A0==88 ps 9
905 16:47:49.619500 RxClkDly_Margin_A1==88 ps 9
906 16:47:49.620047 TxDqDly_Margin_A1==108 ps 11
907 16:47:49.625004 TrainedVREFDQ_A0==76
908 16:47:49.625497 TrainedVREFDQ_A1==78
909 16:47:49.625931 VrefDac_Margin_A0==22
910 16:47:49.630705 DeviceVref_Margin_A0==38
911 16:47:49.631169 VrefDac_Margin_A1==24
912 16:47:49.636228 DeviceVref_Margin_A1==36
913 16:47:49.636690
914 16:47:49.637123 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 16:47:49.641770
916 16:47:49.669782 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000018 dram_vref_reg_value 0x 00000060
917 16:47:49.670315 2D training succeed
918 16:47:49.675564 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 16:47:49.681000 auto size-- 65535DDR cs0 size: 2048MB
920 16:47:49.681462 DDR cs1 size: 2048MB
921 16:47:49.686565 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 16:47:49.687029 cs0 DataBus test pass
923 16:47:49.692255 cs1 DataBus test pass
924 16:47:49.692716 cs0 AddrBus test pass
925 16:47:49.693148 cs1 AddrBus test pass
926 16:47:49.693572
927 16:47:49.697777 100bdlr_step_size ps== 420
928 16:47:49.698247 result report
929 16:47:49.703395 boot times 0Enable ddr reg access
930 16:47:49.708948 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 16:47:49.722488 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 16:47:50.295920 0.0;M3 CHK:0;cm4_sp_mode 0
933 16:47:50.296601 MVN_1=0x00000000
934 16:47:50.301349 MVN_2=0x00000000
935 16:47:50.307175 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 16:47:50.307674 OPS=0x10
937 16:47:50.308162 ring efuse init
938 16:47:50.308615 chipver efuse init
939 16:47:50.312803 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 16:47:50.318369 [0.018961 Inits done]
941 16:47:50.318854 secure task start!
942 16:47:50.319301 high task start!
943 16:47:50.322946 low task start!
944 16:47:50.323433 run into bl31
945 16:47:50.329612 NOTICE: BL31: v1.3(release):4fc40b1
946 16:47:50.337438 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 16:47:50.337933 NOTICE: BL31: G12A normal boot!
948 16:47:50.362914 NOTICE: BL31: BL33 decompress pass
949 16:47:50.368431 ERROR: Error initializing runtime service opteed_fast
950 16:47:51.601323
951 16:47:51.602012
952 16:47:51.609751 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 16:47:51.610379
954 16:47:51.610896 Model: Libre Computer AML-A311D-CC Alta
955 16:47:51.818297 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 16:47:51.841695 DRAM: 2 GiB (effective 3.8 GiB)
957 16:47:51.984542 Core: 408 devices, 31 uclasses, devicetree: separate
958 16:47:51.990461 WDT: Not starting watchdog@f0d0
959 16:47:52.022650 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 16:47:52.035170 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 16:47:52.040212 ** Bad device specification mmc 0 **
962 16:47:52.050492 Card did not respond to voltage select! : -110
963 16:47:52.058072 ** Bad device specification mmc 0 **
964 16:47:52.058567 Couldn't find partition mmc 0
965 16:47:52.066436 Card did not respond to voltage select! : -110
966 16:47:52.071919 ** Bad device specification mmc 0 **
967 16:47:52.072440 Couldn't find partition mmc 0
968 16:47:52.076996 Error: could not access storage.
969 16:47:52.420507 Net: eth0: ethernet@ff3f0000
970 16:47:52.421092 starting USB...
971 16:47:52.672266 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 16:47:52.672801 Starting the controller
973 16:47:52.679273 USB XHCI 1.10
974 16:47:54.539900 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 16:47:54.540604 bl2_stage_init 0x01
976 16:47:54.541077 bl2_stage_init 0x81
977 16:47:54.545669 hw id: 0x0000 - pwm id 0x01
978 16:47:54.546157 bl2_stage_init 0xc1
979 16:47:54.546615 bl2_stage_init 0x02
980 16:47:54.547063
981 16:47:54.550873 L0:00000000
982 16:47:54.551360 L1:20000703
983 16:47:54.551813 L2:00008067
984 16:47:54.552308 L3:14000000
985 16:47:54.556491 B2:00402000
986 16:47:54.556973 B1:e0f83180
987 16:47:54.557425
988 16:47:54.557868 TE: 58124
989 16:47:54.558315
990 16:47:54.562246 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 16:47:54.562731
992 16:47:54.563180 Board ID = 1
993 16:47:54.567795 Set A53 clk to 24M
994 16:47:54.568310 Set A73 clk to 24M
995 16:47:54.568756 Set clk81 to 24M
996 16:47:54.573372 A53 clk: 1200 MHz
997 16:47:54.573851 A73 clk: 1200 MHz
998 16:47:54.574300 CLK81: 166.6M
999 16:47:54.574741 smccc: 00012a91
1000 16:47:54.578841 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 16:47:54.584599 board id: 1
1002 16:47:54.590369 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 16:47:54.601108 fw parse done
1004 16:47:54.606927 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 16:47:54.649575 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 16:47:54.660418 PIEI prepare done
1007 16:47:54.660887 fastboot data load
1008 16:47:54.661326 fastboot data verify
1009 16:47:54.666057 verify result: 266
1010 16:47:54.671669 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 16:47:54.672184 LPDDR4 probe
1012 16:47:54.672621 ddr clk to 1584MHz
1013 16:47:54.679627 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 16:47:54.716851
1015 16:47:54.717347 dmc_version 0001
1016 16:47:54.723547 Check phy result
1017 16:47:54.729394 INFO : End of CA training
1018 16:47:54.729860 INFO : End of initialization
1019 16:47:54.735032 INFO : Training has run successfully!
1020 16:47:54.735496 Check phy result
1021 16:47:54.740582 INFO : End of initialization
1022 16:47:54.741041 INFO : End of read enable training
1023 16:47:54.746261 INFO : End of fine write leveling
1024 16:47:54.751870 INFO : End of Write leveling coarse delay
1025 16:47:54.752387 INFO : Training has run successfully!
1026 16:47:54.752842 Check phy result
1027 16:47:54.757493 INFO : End of initialization
1028 16:47:54.757972 INFO : End of read dq deskew training
1029 16:47:54.763042 INFO : End of MPR read delay center optimization
1030 16:47:54.768696 INFO : End of write delay center optimization
1031 16:47:54.774234 INFO : End of read delay center optimization
1032 16:47:54.774710 INFO : End of max read latency training
1033 16:47:54.779862 INFO : Training has run successfully!
1034 16:47:54.780391 1D training succeed
1035 16:47:54.789165 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 16:47:54.836627 Check phy result
1037 16:47:54.837121 INFO : End of initialization
1038 16:47:54.858386 INFO : End of 2D read delay Voltage center optimization
1039 16:47:54.878641 INFO : End of 2D read delay Voltage center optimization
1040 16:47:54.930673 INFO : End of 2D write delay Voltage center optimization
1041 16:47:54.980192 INFO : End of 2D write delay Voltage center optimization
1042 16:47:54.985759 INFO : Training has run successfully!
1043 16:47:54.986247
1044 16:47:54.986724 channel==0
1045 16:47:54.991291 RxClkDly_Margin_A0==88 ps 9
1046 16:47:54.991771 TxDqDly_Margin_A0==98 ps 10
1047 16:47:54.994558 RxClkDly_Margin_A1==88 ps 9
1048 16:47:54.995031 TxDqDly_Margin_A1==98 ps 10
1049 16:47:55.000195 TrainedVREFDQ_A0==74
1050 16:47:55.000693 TrainedVREFDQ_A1==74
1051 16:47:55.005772 VrefDac_Margin_A0==25
1052 16:47:55.006246 DeviceVref_Margin_A0==40
1053 16:47:55.006694 VrefDac_Margin_A1==25
1054 16:47:55.011415 DeviceVref_Margin_A1==40
1055 16:47:55.011893
1056 16:47:55.012384
1057 16:47:55.012832 channel==1
1058 16:47:55.013275 RxClkDly_Margin_A0==98 ps 10
1059 16:47:55.014757 TxDqDly_Margin_A0==88 ps 9
1060 16:47:55.020322 RxClkDly_Margin_A1==98 ps 10
1061 16:47:55.020801 TxDqDly_Margin_A1==108 ps 11
1062 16:47:55.025925 TrainedVREFDQ_A0==76
1063 16:47:55.026415 TrainedVREFDQ_A1==78
1064 16:47:55.026865 VrefDac_Margin_A0==22
1065 16:47:55.031430 DeviceVref_Margin_A0==38
1066 16:47:55.031913 VrefDac_Margin_A1==22
1067 16:47:55.032400 DeviceVref_Margin_A1==36
1068 16:47:55.032843
1069 16:47:55.040618 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 16:47:55.041109
1071 16:47:55.066470 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1072 16:47:55.072119 2D training succeed
1073 16:47:55.075463 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 16:47:55.080834 auto size-- 65535DDR cs0 size: 2048MB
1075 16:47:55.081326 DDR cs1 size: 2048MB
1076 16:47:55.086420 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 16:47:55.086898 cs0 DataBus test pass
1078 16:47:55.092106 cs1 DataBus test pass
1079 16:47:55.092583 cs0 AddrBus test pass
1080 16:47:55.093036 cs1 AddrBus test pass
1081 16:47:55.093484
1082 16:47:55.097616 100bdlr_step_size ps== 420
1083 16:47:55.098113 result report
1084 16:47:55.103205 boot times 0Enable ddr reg access
1085 16:47:55.108633 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 16:47:55.121684 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 16:47:55.695966 0.0;M3 CHK:0;cm4_sp_mode 0
1088 16:47:55.696688 MVN_1=0x00000000
1089 16:47:55.701287 MVN_2=0x00000000
1090 16:47:55.707170 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 16:47:55.707711 OPS=0x10
1092 16:47:55.708232 ring efuse init
1093 16:47:55.708690 chipver efuse init
1094 16:47:55.715433 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 16:47:55.715945 [0.018961 Inits done]
1096 16:47:55.716451 secure task start!
1097 16:47:55.722871 high task start!
1098 16:47:55.723377 low task start!
1099 16:47:55.723809 run into bl31
1100 16:47:55.729613 NOTICE: BL31: v1.3(release):4fc40b1
1101 16:47:55.737432 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 16:47:55.737914 NOTICE: BL31: G12A normal boot!
1103 16:47:55.762782 NOTICE: BL31: BL33 decompress pass
1104 16:47:55.768443 ERROR: Error initializing runtime service opteed_fast
1105 16:47:57.001270
1106 16:47:57.001896
1107 16:47:57.009690 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 16:47:57.010199
1109 16:47:57.010627 Model: Libre Computer AML-A311D-CC Alta
1110 16:47:57.218135 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 16:47:57.241537 DRAM: 2 GiB (effective 3.8 GiB)
1112 16:47:57.384444 Core: 408 devices, 31 uclasses, devicetree: separate
1113 16:47:57.390290 WDT: Not starting watchdog@f0d0
1114 16:47:57.422676 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 16:47:57.435048 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 16:47:57.440089 ** Bad device specification mmc 0 **
1117 16:47:57.450455 Card did not respond to voltage select! : -110
1118 16:47:57.458071 ** Bad device specification mmc 0 **
1119 16:47:57.458558 Couldn't find partition mmc 0
1120 16:47:57.466456 Card did not respond to voltage select! : -110
1121 16:47:57.471909 ** Bad device specification mmc 0 **
1122 16:47:57.472416 Couldn't find partition mmc 0
1123 16:47:57.476322 Error: could not access storage.
1124 16:47:57.820451 Net: eth0: ethernet@ff3f0000
1125 16:47:57.821023 starting USB...
1126 16:47:58.072335 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 16:47:58.072929 Starting the controller
1128 16:47:58.079260 USB XHCI 1.10
1129 16:47:59.633372 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 16:47:59.641605 scanning usb for storage devices... 0 Storage Device(s) found
1132 16:47:59.693146 Hit any key to stop autoboot: 1
1133 16:47:59.694021 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 16:47:59.694676 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1135 16:47:59.695219 Setting prompt string to ['=>']
1136 16:47:59.695749 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1137 16:47:59.709054 0
1138 16:47:59.709932 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 16:47:59.710411 Sending with 10 millisecond of delay
1141 16:48:00.845451 => setenv autoload no
1142 16:48:00.856219 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1143 16:48:00.861095 setenv autoload no
1144 16:48:00.861825 Sending with 10 millisecond of delay
1146 16:48:02.658656 => setenv initrd_high 0xffffffff
1147 16:48:02.669454 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1148 16:48:02.670291 setenv initrd_high 0xffffffff
1149 16:48:02.670990 Sending with 10 millisecond of delay
1151 16:48:04.287066 => setenv fdt_high 0xffffffff
1152 16:48:04.297852 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1153 16:48:04.298680 setenv fdt_high 0xffffffff
1154 16:48:04.299381 Sending with 10 millisecond of delay
1156 16:48:04.591291 => dhcp
1157 16:48:04.602084 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 16:48:04.602906 dhcp
1159 16:48:04.603341 Speed: 1000, full duplex
1160 16:48:04.603754 BOOTP broadcast 1
1161 16:48:04.610808 DHCP client bound to address 192.168.6.27 (8 ms)
1162 16:48:04.611517 Sending with 10 millisecond of delay
1164 16:48:06.287959 => setenv serverip 192.168.6.2
1165 16:48:06.298794 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1166 16:48:06.299660 setenv serverip 192.168.6.2
1167 16:48:06.300393 Sending with 10 millisecond of delay
1169 16:48:10.023719 => tftpboot 0x01080000 975395/tftp-deploy-3n8jtr2m/kernel/uImage
1170 16:48:10.034625 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1171 16:48:10.035489 tftpboot 0x01080000 975395/tftp-deploy-3n8jtr2m/kernel/uImage
1172 16:48:10.035933 Speed: 1000, full duplex
1173 16:48:10.036386 Using ethernet@ff3f0000 device
1174 16:48:10.037367 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 16:48:10.042865 Filename '975395/tftp-deploy-3n8jtr2m/kernel/uImage'.
1176 16:48:10.046729 Load address: 0x1080000
1177 16:48:12.835077 Loading: *################################################## 43.6 MiB
1178 16:48:12.835886 15.6 MiB/s
1179 16:48:12.836537 done
1180 16:48:12.838841 Bytes transferred = 45713984 (2b98a40 hex)
1181 16:48:12.839813 Sending with 10 millisecond of delay
1183 16:48:17.527807 => tftpboot 0x08000000 975395/tftp-deploy-3n8jtr2m/ramdisk/ramdisk.cpio.gz.uboot
1184 16:48:17.538594 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1185 16:48:17.539364 tftpboot 0x08000000 975395/tftp-deploy-3n8jtr2m/ramdisk/ramdisk.cpio.gz.uboot
1186 16:48:17.539811 Speed: 1000, full duplex
1187 16:48:17.540268 Using ethernet@ff3f0000 device
1188 16:48:17.541316 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 16:48:17.553239 Filename '975395/tftp-deploy-3n8jtr2m/ramdisk/ramdisk.cpio.gz.uboot'.
1190 16:48:17.553689 Load address: 0x8000000
1191 16:48:24.115175 Loading: *############################T ##################### UDP wrong checksum 00000005 0000e6b9
1192 16:48:29.116078 T UDP wrong checksum 00000005 0000e6b9
1193 16:48:39.119147 T T UDP wrong checksum 00000005 0000e6b9
1194 16:48:54.212433 T T T UDP wrong checksum 000000ff 0000278c
1195 16:48:54.223645 UDP wrong checksum 000000ff 0000be7e
1196 16:48:59.121026 UDP wrong checksum 00000005 0000e6b9
1197 16:49:12.543641 T T T UDP wrong checksum 000000ff 000021e9
1198 16:49:14.127509
1199 16:49:14.128211 Retry count exceeded; starting again
1201 16:49:14.129702 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
1204 16:49:14.131515 end: 2.4 uboot-commands (duration 00:01:51) [common]
1206 16:49:14.132911 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1208 16:49:14.133949 end: 2 uboot-action (duration 00:01:52) [common]
1210 16:49:14.135484 Cleaning after the job
1211 16:49:14.136286 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975395/tftp-deploy-3n8jtr2m/ramdisk
1212 16:49:14.137812 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975395/tftp-deploy-3n8jtr2m/kernel
1213 16:49:14.183891 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975395/tftp-deploy-3n8jtr2m/dtb
1214 16:49:14.184903 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975395/tftp-deploy-3n8jtr2m/nfsrootfs
1215 16:49:14.212470 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975395/tftp-deploy-3n8jtr2m/modules
1216 16:49:14.234292 start: 4.1 power-off (timeout 00:00:30) [common]
1217 16:49:14.234971 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1218 16:49:14.268616 >> OK - accepted request
1219 16:49:14.270723 Returned 0 in 0 seconds
1220 16:49:14.371534 end: 4.1 power-off (duration 00:00:00) [common]
1222 16:49:14.372685 start: 4.2 read-feedback (timeout 00:10:00) [common]
1223 16:49:14.373385 Listened to connection for namespace 'common' for up to 1s
1224 16:49:15.374359 Finalising connection for namespace 'common'
1225 16:49:15.374957 Disconnecting from shell: Finalise
1226 16:49:15.375316 =>
1227 16:49:15.476320 end: 4.2 read-feedback (duration 00:00:01) [common]
1228 16:49:15.477050 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/975395
1229 16:49:18.500506 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/975395
1230 16:49:18.501119 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.