Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 17:00:41.796097 lava-dispatcher, installed at version: 2024.01
2 17:00:41.796884 start: 0 validate
3 17:00:41.797358 Start time: 2024-11-11 17:00:41.797329+00:00 (UTC)
4 17:00:41.797900 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 17:00:41.798439 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 17:00:41.837481 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 17:00:41.838049 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fnext%2Frenesas-next-2024-11-11-v6.12-rc1%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 17:00:41.875290 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 17:00:41.876228 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fnext%2Frenesas-next-2024-11-11-v6.12-rc1%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 17:00:41.911425 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 17:00:41.912206 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 17:00:41.948156 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 17:00:41.948633 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frenesas%2Fnext%2Frenesas-next-2024-11-11-v6.12-rc1%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 17:00:41.987415 validate duration: 0.19
16 17:00:41.988637 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 17:00:41.989101 start: 1.1 download-retry (timeout 00:10:00) [common]
18 17:00:41.989725 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 17:00:41.990733 Not decompressing ramdisk as can be used compressed.
20 17:00:41.991533 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 17:00:41.992089 saving as /var/lib/lava/dispatcher/tmp/975512/tftp-deploy-walxjqqj/ramdisk/initrd.cpio.gz
22 17:00:41.992617 total size: 5628169 (5 MB)
23 17:00:42.034810 progress 0 % (0 MB)
24 17:00:42.044908 progress 5 % (0 MB)
25 17:00:42.054798 progress 10 % (0 MB)
26 17:00:42.063725 progress 15 % (0 MB)
27 17:00:42.068322 progress 20 % (1 MB)
28 17:00:42.071922 progress 25 % (1 MB)
29 17:00:42.075931 progress 30 % (1 MB)
30 17:00:42.079960 progress 35 % (1 MB)
31 17:00:42.083574 progress 40 % (2 MB)
32 17:00:42.087590 progress 45 % (2 MB)
33 17:00:42.091224 progress 50 % (2 MB)
34 17:00:42.095205 progress 55 % (2 MB)
35 17:00:42.099250 progress 60 % (3 MB)
36 17:00:42.102871 progress 65 % (3 MB)
37 17:00:42.106870 progress 70 % (3 MB)
38 17:00:42.110474 progress 75 % (4 MB)
39 17:00:42.114376 progress 80 % (4 MB)
40 17:00:42.117860 progress 85 % (4 MB)
41 17:00:42.121543 progress 90 % (4 MB)
42 17:00:42.125205 progress 95 % (5 MB)
43 17:00:42.128661 progress 100 % (5 MB)
44 17:00:42.129413 5 MB downloaded in 0.14 s (39.24 MB/s)
45 17:00:42.130017 end: 1.1.1 http-download (duration 00:00:00) [common]
47 17:00:42.131005 end: 1.1 download-retry (duration 00:00:00) [common]
48 17:00:42.131337 start: 1.2 download-retry (timeout 00:10:00) [common]
49 17:00:42.131640 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 17:00:42.132180 downloading http://storage.kernelci.org/renesas/next/renesas-next-2024-11-11-v6.12-rc1/arm64/defconfig/gcc-12/kernel/Image
51 17:00:42.132476 saving as /var/lib/lava/dispatcher/tmp/975512/tftp-deploy-walxjqqj/kernel/Image
52 17:00:42.132708 total size: 45713920 (43 MB)
53 17:00:42.132937 No compression specified
54 17:00:42.171125 progress 0 % (0 MB)
55 17:00:42.204769 progress 5 % (2 MB)
56 17:00:42.238794 progress 10 % (4 MB)
57 17:00:42.271457 progress 15 % (6 MB)
58 17:00:42.304112 progress 20 % (8 MB)
59 17:00:42.336086 progress 25 % (10 MB)
60 17:00:42.369869 progress 30 % (13 MB)
61 17:00:42.401818 progress 35 % (15 MB)
62 17:00:42.433930 progress 40 % (17 MB)
63 17:00:42.465821 progress 45 % (19 MB)
64 17:00:42.497788 progress 50 % (21 MB)
65 17:00:42.529967 progress 55 % (24 MB)
66 17:00:42.562412 progress 60 % (26 MB)
67 17:00:42.594477 progress 65 % (28 MB)
68 17:00:42.626452 progress 70 % (30 MB)
69 17:00:42.658766 progress 75 % (32 MB)
70 17:00:42.690889 progress 80 % (34 MB)
71 17:00:42.722774 progress 85 % (37 MB)
72 17:00:42.755565 progress 90 % (39 MB)
73 17:00:42.788528 progress 95 % (41 MB)
74 17:00:42.819703 progress 100 % (43 MB)
75 17:00:42.820409 43 MB downloaded in 0.69 s (63.40 MB/s)
76 17:00:42.821000 end: 1.2.1 http-download (duration 00:00:01) [common]
78 17:00:42.822068 end: 1.2 download-retry (duration 00:00:01) [common]
79 17:00:42.822433 start: 1.3 download-retry (timeout 00:09:59) [common]
80 17:00:42.822773 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 17:00:42.823378 downloading http://storage.kernelci.org/renesas/next/renesas-next-2024-11-11-v6.12-rc1/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 17:00:42.823728 saving as /var/lib/lava/dispatcher/tmp/975512/tftp-deploy-walxjqqj/dtb/meson-g12b-a311d-libretech-cc.dtb
83 17:00:42.824019 total size: 54703 (0 MB)
84 17:00:42.824286 No compression specified
85 17:00:42.870704 progress 59 % (0 MB)
86 17:00:42.871768 progress 100 % (0 MB)
87 17:00:42.872569 0 MB downloaded in 0.05 s (1.07 MB/s)
88 17:00:42.873230 end: 1.3.1 http-download (duration 00:00:00) [common]
90 17:00:42.874343 end: 1.3 download-retry (duration 00:00:00) [common]
91 17:00:42.874711 start: 1.4 download-retry (timeout 00:09:59) [common]
92 17:00:42.875044 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 17:00:42.875631 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 17:00:42.875968 saving as /var/lib/lava/dispatcher/tmp/975512/tftp-deploy-walxjqqj/nfsrootfs/full.rootfs.tar
95 17:00:42.876301 total size: 120894716 (115 MB)
96 17:00:42.876584 Using unxz to decompress xz
97 17:00:42.917606 progress 0 % (0 MB)
98 17:00:43.723932 progress 5 % (5 MB)
99 17:00:44.574817 progress 10 % (11 MB)
100 17:00:45.373153 progress 15 % (17 MB)
101 17:00:46.111588 progress 20 % (23 MB)
102 17:00:46.706509 progress 25 % (28 MB)
103 17:00:47.533080 progress 30 % (34 MB)
104 17:00:48.326626 progress 35 % (40 MB)
105 17:00:48.674129 progress 40 % (46 MB)
106 17:00:49.044336 progress 45 % (51 MB)
107 17:00:49.824769 progress 50 % (57 MB)
108 17:00:50.715969 progress 55 % (63 MB)
109 17:00:51.502976 progress 60 % (69 MB)
110 17:00:52.268335 progress 65 % (74 MB)
111 17:00:53.054490 progress 70 % (80 MB)
112 17:00:53.883284 progress 75 % (86 MB)
113 17:00:54.672920 progress 80 % (92 MB)
114 17:00:55.439225 progress 85 % (98 MB)
115 17:00:56.301596 progress 90 % (103 MB)
116 17:00:57.085269 progress 95 % (109 MB)
117 17:00:57.923902 progress 100 % (115 MB)
118 17:00:57.937412 115 MB downloaded in 15.06 s (7.66 MB/s)
119 17:00:57.938343 end: 1.4.1 http-download (duration 00:00:15) [common]
121 17:00:57.940010 end: 1.4 download-retry (duration 00:00:15) [common]
122 17:00:57.940561 start: 1.5 download-retry (timeout 00:09:44) [common]
123 17:00:57.941090 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 17:00:57.942005 downloading http://storage.kernelci.org/renesas/next/renesas-next-2024-11-11-v6.12-rc1/arm64/defconfig/gcc-12/modules.tar.xz
125 17:00:57.942483 saving as /var/lib/lava/dispatcher/tmp/975512/tftp-deploy-walxjqqj/modules/modules.tar
126 17:00:57.942896 total size: 11608784 (11 MB)
127 17:00:57.943319 Using unxz to decompress xz
128 17:00:57.989887 progress 0 % (0 MB)
129 17:00:58.069159 progress 5 % (0 MB)
130 17:00:58.157695 progress 10 % (1 MB)
131 17:00:58.272807 progress 15 % (1 MB)
132 17:00:58.382923 progress 20 % (2 MB)
133 17:00:58.476677 progress 25 % (2 MB)
134 17:00:58.565757 progress 30 % (3 MB)
135 17:00:58.652510 progress 35 % (3 MB)
136 17:00:58.746829 progress 40 % (4 MB)
137 17:00:58.839127 progress 45 % (5 MB)
138 17:00:58.942612 progress 50 % (5 MB)
139 17:00:59.038419 progress 55 % (6 MB)
140 17:00:59.141907 progress 60 % (6 MB)
141 17:00:59.239675 progress 65 % (7 MB)
142 17:00:59.333149 progress 70 % (7 MB)
143 17:00:59.432192 progress 75 % (8 MB)
144 17:00:59.534803 progress 80 % (8 MB)
145 17:00:59.631340 progress 85 % (9 MB)
146 17:00:59.726395 progress 90 % (9 MB)
147 17:00:59.820572 progress 95 % (10 MB)
148 17:00:59.913644 progress 100 % (11 MB)
149 17:00:59.926962 11 MB downloaded in 1.98 s (5.58 MB/s)
150 17:00:59.927847 end: 1.5.1 http-download (duration 00:00:02) [common]
152 17:00:59.929530 end: 1.5 download-retry (duration 00:00:02) [common]
153 17:00:59.930057 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 17:00:59.930571 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 17:01:16.482549 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/975512/extract-nfsrootfs-g94gbywm
156 17:01:16.483170 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 17:01:16.483459 start: 1.6.2 lava-overlay (timeout 00:09:26) [common]
158 17:01:16.484092 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh
159 17:01:16.484575 makedir: /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin
160 17:01:16.484936 makedir: /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/tests
161 17:01:16.485312 makedir: /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/results
162 17:01:16.485661 Creating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-add-keys
163 17:01:16.486199 Creating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-add-sources
164 17:01:16.486753 Creating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-background-process-start
165 17:01:16.487294 Creating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-background-process-stop
166 17:01:16.487923 Creating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-common-functions
167 17:01:16.488598 Creating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-echo-ipv4
168 17:01:16.489215 Creating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-install-packages
169 17:01:16.489750 Creating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-installed-packages
170 17:01:16.490311 Creating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-os-build
171 17:01:16.490833 Creating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-probe-channel
172 17:01:16.491322 Creating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-probe-ip
173 17:01:16.491857 Creating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-target-ip
174 17:01:16.492411 Creating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-target-mac
175 17:01:16.492925 Creating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-target-storage
176 17:01:16.493466 Creating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-test-case
177 17:01:16.493990 Creating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-test-event
178 17:01:16.494495 Creating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-test-feedback
179 17:01:16.495008 Creating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-test-raise
180 17:01:16.495494 Creating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-test-reference
181 17:01:16.496010 Creating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-test-runner
182 17:01:16.496538 Creating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-test-set
183 17:01:16.497032 Creating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-test-shell
184 17:01:16.497532 Updating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-add-keys (debian)
185 17:01:16.498091 Updating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-add-sources (debian)
186 17:01:16.498645 Updating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-install-packages (debian)
187 17:01:16.499259 Updating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-installed-packages (debian)
188 17:01:16.499789 Updating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/bin/lava-os-build (debian)
189 17:01:16.500275 Creating /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/environment
190 17:01:16.500664 LAVA metadata
191 17:01:16.500929 - LAVA_JOB_ID=975512
192 17:01:16.501145 - LAVA_DISPATCHER_IP=192.168.6.2
193 17:01:16.501524 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 17:01:16.502493 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 17:01:16.502813 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 17:01:16.503020 skipped lava-vland-overlay
197 17:01:16.503260 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 17:01:16.503514 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 17:01:16.503732 skipped lava-multinode-overlay
200 17:01:16.503974 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 17:01:16.504255 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 17:01:16.504512 Loading test definitions
203 17:01:16.504796 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 17:01:16.505015 Using /lava-975512 at stage 0
205 17:01:16.506126 uuid=975512_1.6.2.4.1 testdef=None
206 17:01:16.506445 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 17:01:16.506707 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 17:01:16.508395 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 17:01:16.509191 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 17:01:16.511295 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 17:01:16.512158 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 17:01:16.514244 runner path: /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/0/tests/0_timesync-off test_uuid 975512_1.6.2.4.1
215 17:01:16.514812 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 17:01:16.515622 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 17:01:16.515844 Using /lava-975512 at stage 0
219 17:01:16.516229 Fetching tests from https://github.com/kernelci/test-definitions.git
220 17:01:16.516524 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/0/tests/1_kselftest-rtc'
221 17:01:19.921464 Running '/usr/bin/git checkout kernelci.org
222 17:01:20.368973 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
223 17:01:20.371510 uuid=975512_1.6.2.4.5 testdef=None
224 17:01:20.372236 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 17:01:20.373872 start: 1.6.2.4.6 test-overlay (timeout 00:09:22) [common]
227 17:01:20.380173 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 17:01:20.381981 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:22) [common]
230 17:01:20.390414 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 17:01:20.392324 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:22) [common]
233 17:01:20.400182 runner path: /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/0/tests/1_kselftest-rtc test_uuid 975512_1.6.2.4.5
234 17:01:20.400773 BOARD='meson-g12b-a311d-libretech-cc'
235 17:01:20.401235 BRANCH='renesas'
236 17:01:20.401684 SKIPFILE='/dev/null'
237 17:01:20.402124 SKIP_INSTALL='True'
238 17:01:20.402562 TESTPROG_URL='http://storage.kernelci.org/renesas/next/renesas-next-2024-11-11-v6.12-rc1/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 17:01:20.403009 TST_CASENAME=''
240 17:01:20.403445 TST_CMDFILES='rtc'
241 17:01:20.404605 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 17:01:20.406330 Creating lava-test-runner.conf files
244 17:01:20.406790 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/975512/lava-overlay-cl3hkujh/lava-975512/0 for stage 0
245 17:01:20.407567 - 0_timesync-off
246 17:01:20.408148 - 1_kselftest-rtc
247 17:01:20.408886 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 17:01:20.409500 start: 1.6.2.5 compress-overlay (timeout 00:09:22) [common]
249 17:01:43.813496 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 17:01:43.813915 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 17:01:43.814177 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 17:01:43.814445 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 17:01:43.814709 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 17:01:44.473179 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 17:01:44.473665 start: 1.6.4 extract-modules (timeout 00:08:58) [common]
256 17:01:44.473917 extracting modules file /var/lib/lava/dispatcher/tmp/975512/tftp-deploy-walxjqqj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/975512/extract-nfsrootfs-g94gbywm
257 17:01:45.871211 extracting modules file /var/lib/lava/dispatcher/tmp/975512/tftp-deploy-walxjqqj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/975512/extract-overlay-ramdisk-ujza4lu5/ramdisk
258 17:01:47.391207 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 17:01:47.391697 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 17:01:47.391996 [common] Applying overlay to NFS
261 17:01:47.392223 [common] Applying overlay /var/lib/lava/dispatcher/tmp/975512/compress-overlay-u4m451ny/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/975512/extract-nfsrootfs-g94gbywm
262 17:01:50.146348 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 17:01:50.146825 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 17:01:50.147101 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 17:01:50.147334 Converting downloaded kernel to a uImage
266 17:01:50.147642 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/975512/tftp-deploy-walxjqqj/kernel/Image /var/lib/lava/dispatcher/tmp/975512/tftp-deploy-walxjqqj/kernel/uImage
267 17:01:50.663673 output: Image Name:
268 17:01:50.664177 output: Created: Mon Nov 11 17:01:50 2024
269 17:01:50.664414 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 17:01:50.664686 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 17:01:50.664942 output: Load Address: 01080000
272 17:01:50.665155 output: Entry Point: 01080000
273 17:01:50.665360 output:
274 17:01:50.665701 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:01) [common]
275 17:01:50.665980 end: 1.6.6 prepare-kernel (duration 00:00:01) [common]
276 17:01:50.666262 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 17:01:50.666527 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 17:01:50.666798 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 17:01:50.667065 Building ramdisk /var/lib/lava/dispatcher/tmp/975512/extract-overlay-ramdisk-ujza4lu5/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/975512/extract-overlay-ramdisk-ujza4lu5/ramdisk
280 17:01:52.986946 >> 166783 blocks
281 17:02:00.691328 Adding RAMdisk u-boot header.
282 17:02:00.691784 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/975512/extract-overlay-ramdisk-ujza4lu5/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/975512/extract-overlay-ramdisk-ujza4lu5/ramdisk.cpio.gz.uboot
283 17:02:00.949983 output: Image Name:
284 17:02:00.950417 output: Created: Mon Nov 11 17:02:00 2024
285 17:02:00.950627 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 17:02:00.950831 output: Data Size: 23428975 Bytes = 22879.86 KiB = 22.34 MiB
287 17:02:00.951036 output: Load Address: 00000000
288 17:02:00.951235 output: Entry Point: 00000000
289 17:02:00.951434 output:
290 17:02:00.952245 rename /var/lib/lava/dispatcher/tmp/975512/extract-overlay-ramdisk-ujza4lu5/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/975512/tftp-deploy-walxjqqj/ramdisk/ramdisk.cpio.gz.uboot
291 17:02:00.953058 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 17:02:00.953652 end: 1.6 prepare-tftp-overlay (duration 00:01:01) [common]
293 17:02:00.954233 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 17:02:00.954779 No LXC device requested
295 17:02:00.955327 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 17:02:00.955885 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 17:02:00.956478 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 17:02:00.956931 Checking files for TFTP limit of 4294967296 bytes.
299 17:02:00.959904 end: 1 tftp-deploy (duration 00:01:19) [common]
300 17:02:00.960594 start: 2 uboot-action (timeout 00:05:00) [common]
301 17:02:00.961172 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 17:02:00.961719 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 17:02:00.962272 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 17:02:00.962850 Using kernel file from prepare-kernel: 975512/tftp-deploy-walxjqqj/kernel/uImage
305 17:02:00.963541 substitutions:
306 17:02:00.964017 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 17:02:00.964472 - {DTB_ADDR}: 0x01070000
308 17:02:00.964913 - {DTB}: 975512/tftp-deploy-walxjqqj/dtb/meson-g12b-a311d-libretech-cc.dtb
309 17:02:00.965354 - {INITRD}: 975512/tftp-deploy-walxjqqj/ramdisk/ramdisk.cpio.gz.uboot
310 17:02:00.965794 - {KERNEL_ADDR}: 0x01080000
311 17:02:00.966230 - {KERNEL}: 975512/tftp-deploy-walxjqqj/kernel/uImage
312 17:02:00.966665 - {LAVA_MAC}: None
313 17:02:00.967140 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/975512/extract-nfsrootfs-g94gbywm
314 17:02:00.967582 - {NFS_SERVER_IP}: 192.168.6.2
315 17:02:00.968041 - {PRESEED_CONFIG}: None
316 17:02:00.968482 - {PRESEED_LOCAL}: None
317 17:02:00.968914 - {RAMDISK_ADDR}: 0x08000000
318 17:02:00.969339 - {RAMDISK}: 975512/tftp-deploy-walxjqqj/ramdisk/ramdisk.cpio.gz.uboot
319 17:02:00.969769 - {ROOT_PART}: None
320 17:02:00.970196 - {ROOT}: None
321 17:02:00.970620 - {SERVER_IP}: 192.168.6.2
322 17:02:00.971046 - {TEE_ADDR}: 0x83000000
323 17:02:00.971468 - {TEE}: None
324 17:02:00.971893 Parsed boot commands:
325 17:02:00.972338 - setenv autoload no
326 17:02:00.972766 - setenv initrd_high 0xffffffff
327 17:02:00.973192 - setenv fdt_high 0xffffffff
328 17:02:00.973613 - dhcp
329 17:02:00.974032 - setenv serverip 192.168.6.2
330 17:02:00.974458 - tftpboot 0x01080000 975512/tftp-deploy-walxjqqj/kernel/uImage
331 17:02:00.974887 - tftpboot 0x08000000 975512/tftp-deploy-walxjqqj/ramdisk/ramdisk.cpio.gz.uboot
332 17:02:00.975315 - tftpboot 0x01070000 975512/tftp-deploy-walxjqqj/dtb/meson-g12b-a311d-libretech-cc.dtb
333 17:02:00.975742 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/975512/extract-nfsrootfs-g94gbywm,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 17:02:00.976218 - bootm 0x01080000 0x08000000 0x01070000
335 17:02:00.976770 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 17:02:00.978392 start: 2.3 connect-device (timeout 00:05:00) [common]
338 17:02:00.978850 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 17:02:00.994407 Setting prompt string to ['lava-test: # ']
340 17:02:00.996103 end: 2.3 connect-device (duration 00:00:00) [common]
341 17:02:00.996790 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 17:02:00.997413 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 17:02:00.997993 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 17:02:00.999255 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 17:02:01.037298 >> OK - accepted request
346 17:02:01.039318 Returned 0 in 0 seconds
347 17:02:01.140575 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 17:02:01.142377 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 17:02:01.142980 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 17:02:01.143530 Setting prompt string to ['Hit any key to stop autoboot']
352 17:02:01.144065 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 17:02:01.145781 Trying 192.168.56.21...
354 17:02:01.146296 Connected to conserv1.
355 17:02:01.146749 Escape character is '^]'.
356 17:02:01.147205
357 17:02:01.147658 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 17:02:01.148191
359 17:02:13.526354 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 17:02:13.527058 bl2_stage_init 0x01
361 17:02:13.527557 bl2_stage_init 0x81
362 17:02:13.531790 hw id: 0x0000 - pwm id 0x01
363 17:02:13.532555 bl2_stage_init 0xc1
364 17:02:13.533057 bl2_stage_init 0x02
365 17:02:13.533508
366 17:02:13.537330 L0:00000000
367 17:02:13.537838 L1:20000703
368 17:02:13.538292 L2:00008067
369 17:02:13.538730 L3:14000000
370 17:02:13.540234 B2:00402000
371 17:02:13.540719 B1:e0f83180
372 17:02:13.541169
373 17:02:13.541602 TE: 58167
374 17:02:13.542036
375 17:02:13.551262 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 17:02:13.551737
377 17:02:13.552211 Board ID = 1
378 17:02:13.552636 Set A53 clk to 24M
379 17:02:13.553057 Set A73 clk to 24M
380 17:02:13.556853 Set clk81 to 24M
381 17:02:13.557318 A53 clk: 1200 MHz
382 17:02:13.557744 A73 clk: 1200 MHz
383 17:02:13.560511 CLK81: 166.6M
384 17:02:13.560971 smccc: 00012abd
385 17:02:13.566050 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 17:02:13.571686 board id: 1
387 17:02:13.576664 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 17:02:13.587333 fw parse done
389 17:02:13.593330 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 17:02:13.635934 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 17:02:13.646956 PIEI prepare done
392 17:02:13.647423 fastboot data load
393 17:02:13.647855 fastboot data verify
394 17:02:13.652495 verify result: 266
395 17:02:13.658043 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 17:02:13.658577 LPDDR4 probe
397 17:02:13.659030 ddr clk to 1584MHz
398 17:02:13.666039 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 17:02:13.703314
400 17:02:13.703814 dmc_version 0001
401 17:02:13.709981 Check phy result
402 17:02:13.715871 INFO : End of CA training
403 17:02:13.716372 INFO : End of initialization
404 17:02:13.721425 INFO : Training has run successfully!
405 17:02:13.721898 Check phy result
406 17:02:13.727019 INFO : End of initialization
407 17:02:13.727519 INFO : End of read enable training
408 17:02:13.732609 INFO : End of fine write leveling
409 17:02:13.738269 INFO : End of Write leveling coarse delay
410 17:02:13.738740 INFO : Training has run successfully!
411 17:02:13.739186 Check phy result
412 17:02:13.743857 INFO : End of initialization
413 17:02:13.744369 INFO : End of read dq deskew training
414 17:02:13.749414 INFO : End of MPR read delay center optimization
415 17:02:13.755019 INFO : End of write delay center optimization
416 17:02:13.760620 INFO : End of read delay center optimization
417 17:02:13.761114 INFO : End of max read latency training
418 17:02:13.766253 INFO : Training has run successfully!
419 17:02:13.766721 1D training succeed
420 17:02:13.775446 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 17:02:13.823084 Check phy result
422 17:02:13.823588 INFO : End of initialization
423 17:02:13.845667 INFO : End of 2D read delay Voltage center optimization
424 17:02:13.865914 INFO : End of 2D read delay Voltage center optimization
425 17:02:13.917924 INFO : End of 2D write delay Voltage center optimization
426 17:02:13.967288 INFO : End of 2D write delay Voltage center optimization
427 17:02:13.972863 INFO : Training has run successfully!
428 17:02:13.973343
429 17:02:13.973795 channel==0
430 17:02:13.978548 RxClkDly_Margin_A0==88 ps 9
431 17:02:13.979018 TxDqDly_Margin_A0==98 ps 10
432 17:02:13.984048 RxClkDly_Margin_A1==88 ps 9
433 17:02:13.984514 TxDqDly_Margin_A1==98 ps 10
434 17:02:13.984966 TrainedVREFDQ_A0==74
435 17:02:13.989820 TrainedVREFDQ_A1==74
436 17:02:13.990291 VrefDac_Margin_A0==24
437 17:02:13.990739 DeviceVref_Margin_A0==40
438 17:02:13.995240 VrefDac_Margin_A1==25
439 17:02:13.995705 DeviceVref_Margin_A1==40
440 17:02:13.996181
441 17:02:13.996626
442 17:02:14.000889 channel==1
443 17:02:14.001360 RxClkDly_Margin_A0==88 ps 9
444 17:02:14.001801 TxDqDly_Margin_A0==98 ps 10
445 17:02:14.006521 RxClkDly_Margin_A1==98 ps 10
446 17:02:14.006990 TxDqDly_Margin_A1==88 ps 9
447 17:02:14.012204 TrainedVREFDQ_A0==77
448 17:02:14.012668 TrainedVREFDQ_A1==77
449 17:02:14.013112 VrefDac_Margin_A0==22
450 17:02:14.017706 DeviceVref_Margin_A0==37
451 17:02:14.018176 VrefDac_Margin_A1==22
452 17:02:14.023243 DeviceVref_Margin_A1==37
453 17:02:14.023711
454 17:02:14.024194 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 17:02:14.024641
456 17:02:14.056890 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000018 00000018 00000016 00000018 00000016 00000017 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 17:02:14.057459 2D training succeed
458 17:02:14.062495 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 17:02:14.067942 auto size-- 65535DDR cs0 size: 2048MB
460 17:02:14.068454 DDR cs1 size: 2048MB
461 17:02:14.073614 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 17:02:14.074079 cs0 DataBus test pass
463 17:02:14.079183 cs1 DataBus test pass
464 17:02:14.079642 cs0 AddrBus test pass
465 17:02:14.080118 cs1 AddrBus test pass
466 17:02:14.080569
467 17:02:14.084795 100bdlr_step_size ps== 420
468 17:02:14.085274 result report
469 17:02:14.090380 boot times 0Enable ddr reg access
470 17:02:14.095826 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 17:02:14.109229 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 17:02:14.682304 0.0;M3 CHK:0;cm4_sp_mode 0
473 17:02:14.682959 MVN_1=0x00000000
474 17:02:14.688071 MVN_2=0x00000000
475 17:02:14.693472 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 17:02:14.693962 OPS=0x10
477 17:02:14.694393 ring efuse init
478 17:02:14.694816 chipver efuse init
479 17:02:14.699072 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 17:02:14.704688 [0.018961 Inits done]
481 17:02:14.705165 secure task start!
482 17:02:14.705577 high task start!
483 17:02:14.709233 low task start!
484 17:02:14.709705 run into bl31
485 17:02:14.715951 NOTICE: BL31: v1.3(release):4fc40b1
486 17:02:14.723771 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 17:02:14.724279 NOTICE: BL31: G12A normal boot!
488 17:02:14.750970 NOTICE: BL31: BL33 decompress pass
489 17:02:14.754683 ERROR: Error initializing runtime service opteed_fast
490 17:02:15.988117
491 17:02:15.988750
492 17:02:15.996000 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 17:02:15.996557
494 17:02:15.996986 Model: Libre Computer AML-A311D-CC Alta
495 17:02:16.204453 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 17:02:16.227800 DRAM: 2 GiB (effective 3.8 GiB)
497 17:02:16.370826 Core: 408 devices, 31 uclasses, devicetree: separate
498 17:02:16.376637 WDT: Not starting watchdog@f0d0
499 17:02:16.408899 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 17:02:16.421423 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 17:02:16.426401 ** Bad device specification mmc 0 **
502 17:02:16.436738 Card did not respond to voltage select! : -110
503 17:02:16.444401 ** Bad device specification mmc 0 **
504 17:02:16.444793 Couldn't find partition mmc 0
505 17:02:16.452726 Card did not respond to voltage select! : -110
506 17:02:16.458159 ** Bad device specification mmc 0 **
507 17:02:16.458544 Couldn't find partition mmc 0
508 17:02:16.463206 Error: could not access storage.
509 17:02:17.726434 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 17:02:17.727059 bl2_stage_init 0x01
511 17:02:17.727494 bl2_stage_init 0x81
512 17:02:17.732014 hw id: 0x0000 - pwm id 0x01
513 17:02:17.732482 bl2_stage_init 0xc1
514 17:02:17.732898 bl2_stage_init 0x02
515 17:02:17.733304
516 17:02:17.737519 L0:00000000
517 17:02:17.737949 L1:20000703
518 17:02:17.738354 L2:00008067
519 17:02:17.738752 L3:14000000
520 17:02:17.743186 B2:00402000
521 17:02:17.743616 B1:e0f83180
522 17:02:17.744052
523 17:02:17.744462 TE: 58124
524 17:02:17.744863
525 17:02:17.748724 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 17:02:17.749154
527 17:02:17.749559 Board ID = 1
528 17:02:17.754317 Set A53 clk to 24M
529 17:02:17.754745 Set A73 clk to 24M
530 17:02:17.755150 Set clk81 to 24M
531 17:02:17.759953 A53 clk: 1200 MHz
532 17:02:17.760400 A73 clk: 1200 MHz
533 17:02:17.760800 CLK81: 166.6M
534 17:02:17.761199 smccc: 00012a92
535 17:02:17.765501 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 17:02:17.771177 board id: 1
537 17:02:17.777001 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 17:02:17.787698 fw parse done
539 17:02:17.793637 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 17:02:17.836248 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 17:02:17.847193 PIEI prepare done
542 17:02:17.847614 fastboot data load
543 17:02:17.848060 fastboot data verify
544 17:02:17.852742 verify result: 266
545 17:02:17.858338 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 17:02:17.858763 LPDDR4 probe
547 17:02:17.859164 ddr clk to 1584MHz
548 17:02:17.866345 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 17:02:17.903577
550 17:02:17.904055 dmc_version 0001
551 17:02:17.910262 Check phy result
552 17:02:17.916200 INFO : End of CA training
553 17:02:17.916627 INFO : End of initialization
554 17:02:17.921727 INFO : Training has run successfully!
555 17:02:17.922149 Check phy result
556 17:02:17.927317 INFO : End of initialization
557 17:02:17.927743 INFO : End of read enable training
558 17:02:17.932999 INFO : End of fine write leveling
559 17:02:17.938584 INFO : End of Write leveling coarse delay
560 17:02:17.939104 INFO : Training has run successfully!
561 17:02:17.939531 Check phy result
562 17:02:17.944200 INFO : End of initialization
563 17:02:17.944643 INFO : End of read dq deskew training
564 17:02:17.949775 INFO : End of MPR read delay center optimization
565 17:02:17.955359 INFO : End of write delay center optimization
566 17:02:17.960981 INFO : End of read delay center optimization
567 17:02:17.961433 INFO : End of max read latency training
568 17:02:17.966558 INFO : Training has run successfully!
569 17:02:17.967014 1D training succeed
570 17:02:17.975748 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 17:02:18.022446 Check phy result
572 17:02:18.022944 INFO : End of initialization
573 17:02:18.045981 INFO : End of 2D read delay Voltage center optimization
574 17:02:18.066350 INFO : End of 2D read delay Voltage center optimization
575 17:02:18.118262 INFO : End of 2D write delay Voltage center optimization
576 17:02:18.167673 INFO : End of 2D write delay Voltage center optimization
577 17:02:18.173116 INFO : Training has run successfully!
578 17:02:18.173571
579 17:02:18.173991 channel==0
580 17:02:18.179533 RxClkDly_Margin_A0==88 ps 9
581 17:02:18.179972 TxDqDly_Margin_A0==98 ps 10
582 17:02:18.184348 RxClkDly_Margin_A1==88 ps 9
583 17:02:18.184784 TxDqDly_Margin_A1==98 ps 10
584 17:02:18.185198 TrainedVREFDQ_A0==74
585 17:02:18.189913 TrainedVREFDQ_A1==74
586 17:02:18.190361 VrefDac_Margin_A0==24
587 17:02:18.190768 DeviceVref_Margin_A0==40
588 17:02:18.195553 VrefDac_Margin_A1==25
589 17:02:18.196010 DeviceVref_Margin_A1==40
590 17:02:18.196429
591 17:02:18.196835
592 17:02:18.201125 channel==1
593 17:02:18.201562 RxClkDly_Margin_A0==98 ps 10
594 17:02:18.201965 TxDqDly_Margin_A0==88 ps 9
595 17:02:18.206751 RxClkDly_Margin_A1==98 ps 10
596 17:02:18.207191 TxDqDly_Margin_A1==88 ps 9
597 17:02:18.212277 TrainedVREFDQ_A0==76
598 17:02:18.212523 TrainedVREFDQ_A1==77
599 17:02:18.212931 VrefDac_Margin_A0==22
600 17:02:18.217949 DeviceVref_Margin_A0==38
601 17:02:18.218383 VrefDac_Margin_A1==22
602 17:02:18.223544 DeviceVref_Margin_A1==37
603 17:02:18.224003
604 17:02:18.224418 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 17:02:18.224823
606 17:02:18.257149 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000017 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
607 17:02:18.257658 2D training succeed
608 17:02:18.262687 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 17:02:18.268310 auto size-- 65535DDR cs0 size: 2048MB
610 17:02:18.268757 DDR cs1 size: 2048MB
611 17:02:18.273903 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 17:02:18.274336 cs0 DataBus test pass
613 17:02:18.279529 cs1 DataBus test pass
614 17:02:18.279962 cs0 AddrBus test pass
615 17:02:18.280301 cs1 AddrBus test pass
616 17:02:18.280513
617 17:02:18.285118 100bdlr_step_size ps== 420
618 17:02:18.285418 result report
619 17:02:18.290697 boot times 0Enable ddr reg access
620 17:02:18.296210 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 17:02:18.309583 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 17:02:18.883457 0.0;M3 CHK:0;cm4_sp_mode 0
623 17:02:18.884144 MVN_1=0x00000000
624 17:02:18.888855 MVN_2=0x00000000
625 17:02:18.894631 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 17:02:18.895144 OPS=0x10
627 17:02:18.895548 ring efuse init
628 17:02:18.895939 chipver efuse init
629 17:02:18.900247 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 17:02:18.905788 [0.018961 Inits done]
631 17:02:18.906219 secure task start!
632 17:02:18.906607 high task start!
633 17:02:18.910434 low task start!
634 17:02:18.910863 run into bl31
635 17:02:18.917021 NOTICE: BL31: v1.3(release):4fc40b1
636 17:02:18.924789 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 17:02:18.925221 NOTICE: BL31: G12A normal boot!
638 17:02:18.950223 NOTICE: BL31: BL33 decompress pass
639 17:02:18.955852 ERROR: Error initializing runtime service opteed_fast
640 17:02:20.189073
641 17:02:20.189703
642 17:02:20.197429 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 17:02:20.197897
644 17:02:20.198317 Model: Libre Computer AML-A311D-CC Alta
645 17:02:20.405942 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 17:02:20.429388 DRAM: 2 GiB (effective 3.8 GiB)
647 17:02:20.572277 Core: 408 devices, 31 uclasses, devicetree: separate
648 17:02:20.578029 WDT: Not starting watchdog@f0d0
649 17:02:20.610409 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 17:02:20.622708 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 17:02:20.627663 ** Bad device specification mmc 0 **
652 17:02:20.637986 Card did not respond to voltage select! : -110
653 17:02:20.645661 ** Bad device specification mmc 0 **
654 17:02:20.646131 Couldn't find partition mmc 0
655 17:02:20.653981 Card did not respond to voltage select! : -110
656 17:02:20.659473 ** Bad device specification mmc 0 **
657 17:02:20.659939 Couldn't find partition mmc 0
658 17:02:20.664564 Error: could not access storage.
659 17:02:21.008356 Net: eth0: ethernet@ff3f0000
660 17:02:21.009011 starting USB...
661 17:02:21.260112 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 17:02:21.260787 Starting the controller
663 17:02:21.267071 USB XHCI 1.10
664 17:02:22.975286 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 17:02:22.975725 bl2_stage_init 0x01
666 17:02:22.975956 bl2_stage_init 0x81
667 17:02:22.980784 hw id: 0x0000 - pwm id 0x01
668 17:02:22.981089 bl2_stage_init 0xc1
669 17:02:22.981307 bl2_stage_init 0x02
670 17:02:22.981524
671 17:02:22.986365 L0:00000000
672 17:02:22.986727 L1:20000703
673 17:02:22.986956 L2:00008067
674 17:02:22.987162 L3:14000000
675 17:02:22.991900 B2:00402000
676 17:02:22.992228 B1:e0f83180
677 17:02:22.992445
678 17:02:22.992664 TE: 58159
679 17:02:22.992880
680 17:02:22.997637 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 17:02:22.997954
682 17:02:22.998168 Board ID = 1
683 17:02:23.003309 Set A53 clk to 24M
684 17:02:23.003889 Set A73 clk to 24M
685 17:02:23.004423 Set clk81 to 24M
686 17:02:23.008944 A53 clk: 1200 MHz
687 17:02:23.009498 A73 clk: 1200 MHz
688 17:02:23.009967 CLK81: 166.6M
689 17:02:23.010428 smccc: 00012ab4
690 17:02:23.014464 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 17:02:23.020132 board id: 1
692 17:02:23.026120 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 17:02:23.036550 fw parse done
694 17:02:23.042527 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 17:02:23.085228 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 17:02:23.096090 PIEI prepare done
697 17:02:23.096663 fastboot data load
698 17:02:23.097140 fastboot data verify
699 17:02:23.101665 verify result: 266
700 17:02:23.107255 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 17:02:23.107817 LPDDR4 probe
702 17:02:23.108334 ddr clk to 1584MHz
703 17:02:23.115309 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 17:02:23.152536
705 17:02:23.153107 dmc_version 0001
706 17:02:23.159325 Check phy result
707 17:02:23.165079 INFO : End of CA training
708 17:02:23.165636 INFO : End of initialization
709 17:02:23.170689 INFO : Training has run successfully!
710 17:02:23.171244 Check phy result
711 17:02:23.176253 INFO : End of initialization
712 17:02:23.176809 INFO : End of read enable training
713 17:02:23.181880 INFO : End of fine write leveling
714 17:02:23.187513 INFO : End of Write leveling coarse delay
715 17:02:23.188123 INFO : Training has run successfully!
716 17:02:23.188599 Check phy result
717 17:02:23.193133 INFO : End of initialization
718 17:02:23.193691 INFO : End of read dq deskew training
719 17:02:23.198717 INFO : End of MPR read delay center optimization
720 17:02:23.204264 INFO : End of write delay center optimization
721 17:02:23.209857 INFO : End of read delay center optimization
722 17:02:23.210408 INFO : End of max read latency training
723 17:02:23.215491 INFO : Training has run successfully!
724 17:02:23.216071 1D training succeed
725 17:02:23.224659 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 17:02:23.272331 Check phy result
727 17:02:23.272923 INFO : End of initialization
728 17:02:23.294834 INFO : End of 2D read delay Voltage center optimization
729 17:02:23.315121 INFO : End of 2D read delay Voltage center optimization
730 17:02:23.367153 INFO : End of 2D write delay Voltage center optimization
731 17:02:23.416512 INFO : End of 2D write delay Voltage center optimization
732 17:02:23.422167 INFO : Training has run successfully!
733 17:02:23.422748
734 17:02:23.423219 channel==0
735 17:02:23.427653 RxClkDly_Margin_A0==88 ps 9
736 17:02:23.428273 TxDqDly_Margin_A0==98 ps 10
737 17:02:23.431018 RxClkDly_Margin_A1==88 ps 9
738 17:02:23.431588 TxDqDly_Margin_A1==98 ps 10
739 17:02:23.436553 TrainedVREFDQ_A0==74
740 17:02:23.437153 TrainedVREFDQ_A1==74
741 17:02:23.442256 VrefDac_Margin_A0==24
742 17:02:23.442876 DeviceVref_Margin_A0==40
743 17:02:23.443383 VrefDac_Margin_A1==25
744 17:02:23.447802 DeviceVref_Margin_A1==40
745 17:02:23.448360
746 17:02:23.448648
747 17:02:23.448878 channel==1
748 17:02:23.449098 RxClkDly_Margin_A0==98 ps 10
749 17:02:23.453281 TxDqDly_Margin_A0==98 ps 10
750 17:02:23.453933 RxClkDly_Margin_A1==88 ps 9
751 17:02:23.458980 TxDqDly_Margin_A1==88 ps 9
752 17:02:23.459669 TrainedVREFDQ_A0==77
753 17:02:23.460248 TrainedVREFDQ_A1==77
754 17:02:23.464373 VrefDac_Margin_A0==23
755 17:02:23.464743 DeviceVref_Margin_A0==37
756 17:02:23.470002 VrefDac_Margin_A1==24
757 17:02:23.470386 DeviceVref_Margin_A1==37
758 17:02:23.470622
759 17:02:23.475628 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 17:02:23.476032
761 17:02:23.503708 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
762 17:02:23.509263 2D training succeed
763 17:02:23.514840 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 17:02:23.515251 auto size-- 65535DDR cs0 size: 2048MB
765 17:02:23.520457 DDR cs1 size: 2048MB
766 17:02:23.520861 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 17:02:23.526053 cs0 DataBus test pass
768 17:02:23.526455 cs1 DataBus test pass
769 17:02:23.526687 cs0 AddrBus test pass
770 17:02:23.531739 cs1 AddrBus test pass
771 17:02:23.532440
772 17:02:23.532907 100bdlr_step_size ps== 420
773 17:02:23.533368 result report
774 17:02:23.537326 boot times 0Enable ddr reg access
775 17:02:23.545020 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 17:02:23.558460 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 17:02:24.132167 0.0;M3 CHK:0;cm4_sp_mode 0
778 17:02:24.132845 MVN_1=0x00000000
779 17:02:24.137594 MVN_2=0x00000000
780 17:02:24.143421 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 17:02:24.144046 OPS=0x10
782 17:02:24.144504 ring efuse init
783 17:02:24.144940 chipver efuse init
784 17:02:24.151552 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 17:02:24.152104 [0.018961 Inits done]
786 17:02:24.152547 secure task start!
787 17:02:24.159311 high task start!
788 17:02:24.159908 low task start!
789 17:02:24.160425 run into bl31
790 17:02:24.165859 NOTICE: BL31: v1.3(release):4fc40b1
791 17:02:24.173672 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 17:02:24.174273 NOTICE: BL31: G12A normal boot!
793 17:02:24.198980 NOTICE: BL31: BL33 decompress pass
794 17:02:24.204677 ERROR: Error initializing runtime service opteed_fast
795 17:02:25.439706
796 17:02:25.440152
797 17:02:25.446087 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 17:02:25.446614
799 17:02:25.447087 Model: Libre Computer AML-A311D-CC Alta
800 17:02:25.654354 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 17:02:25.678617 DRAM: 2 GiB (effective 3.8 GiB)
802 17:02:25.820835 Core: 408 devices, 31 uclasses, devicetree: separate
803 17:02:25.826777 WDT: Not starting watchdog@f0d0
804 17:02:25.859583 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 17:02:25.871299 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 17:02:25.876298 ** Bad device specification mmc 0 **
807 17:02:25.886573 Card did not respond to voltage select! : -110
808 17:02:25.894251 ** Bad device specification mmc 0 **
809 17:02:25.894782 Couldn't find partition mmc 0
810 17:02:25.902579 Card did not respond to voltage select! : -110
811 17:02:25.908061 ** Bad device specification mmc 0 **
812 17:02:25.908584 Couldn't find partition mmc 0
813 17:02:25.913265 Error: could not access storage.
814 17:02:26.256458 Net: eth0: ethernet@ff3f0000
815 17:02:26.256898 starting USB...
816 17:02:26.508371 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 17:02:26.509045 Starting the controller
818 17:02:26.515234 USB XHCI 1.10
819 17:02:28.675283 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 17:02:28.675720 bl2_stage_init 0x01
821 17:02:28.675945 bl2_stage_init 0x81
822 17:02:28.680802 hw id: 0x0000 - pwm id 0x01
823 17:02:28.681111 bl2_stage_init 0xc1
824 17:02:28.681329 bl2_stage_init 0x02
825 17:02:28.681535
826 17:02:28.686425 L0:00000000
827 17:02:28.686869 L1:20000703
828 17:02:28.687213 L2:00008067
829 17:02:28.687543 L3:14000000
830 17:02:28.692035 B2:00402000
831 17:02:28.692492 B1:e0f83180
832 17:02:28.692817
833 17:02:28.693045 TE: 58124
834 17:02:28.693253
835 17:02:28.697653 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 17:02:28.698094
837 17:02:28.698423 Board ID = 1
838 17:02:28.703223 Set A53 clk to 24M
839 17:02:28.703687 Set A73 clk to 24M
840 17:02:28.703930 Set clk81 to 24M
841 17:02:28.708819 A53 clk: 1200 MHz
842 17:02:28.709128 A73 clk: 1200 MHz
843 17:02:28.709342 CLK81: 166.6M
844 17:02:28.709545 smccc: 00012a92
845 17:02:28.714433 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 17:02:28.720028 board id: 1
847 17:02:28.725933 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 17:02:28.736588 fw parse done
849 17:02:28.742588 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 17:02:28.785109 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 17:02:28.796242 PIEI prepare done
852 17:02:28.797014 fastboot data load
853 17:02:28.797816 fastboot data verify
854 17:02:28.801693 verify result: 266
855 17:02:28.807308 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 17:02:28.807685 LPDDR4 probe
857 17:02:28.807915 ddr clk to 1584MHz
858 17:02:28.815337 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 17:02:28.852667
860 17:02:28.853264 dmc_version 0001
861 17:02:28.859252 Check phy result
862 17:02:28.865933 INFO : End of CA training
863 17:02:28.866356 INFO : End of initialization
864 17:02:28.870733 INFO : Training has run successfully!
865 17:02:28.871109 Check phy result
866 17:02:28.876316 INFO : End of initialization
867 17:02:28.876707 INFO : End of read enable training
868 17:02:28.881901 INFO : End of fine write leveling
869 17:02:28.887479 INFO : End of Write leveling coarse delay
870 17:02:28.887859 INFO : Training has run successfully!
871 17:02:28.888131 Check phy result
872 17:02:28.893086 INFO : End of initialization
873 17:02:28.893480 INFO : End of read dq deskew training
874 17:02:28.898727 INFO : End of MPR read delay center optimization
875 17:02:28.904297 INFO : End of write delay center optimization
876 17:02:28.909877 INFO : End of read delay center optimization
877 17:02:28.910264 INFO : End of max read latency training
878 17:02:28.915461 INFO : Training has run successfully!
879 17:02:28.916029 1D training succeed
880 17:02:28.924636 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 17:02:28.972531 Check phy result
882 17:02:28.973219 INFO : End of initialization
883 17:02:28.994158 INFO : End of 2D read delay Voltage center optimization
884 17:02:29.014489 INFO : End of 2D read delay Voltage center optimization
885 17:02:29.066575 INFO : End of 2D write delay Voltage center optimization
886 17:02:29.115947 INFO : End of 2D write delay Voltage center optimization
887 17:02:29.121442 INFO : Training has run successfully!
888 17:02:29.122159
889 17:02:29.122719 channel==0
890 17:02:29.127072 RxClkDly_Margin_A0==88 ps 9
891 17:02:29.127753 TxDqDly_Margin_A0==98 ps 10
892 17:02:29.132592 RxClkDly_Margin_A1==88 ps 9
893 17:02:29.133266 TxDqDly_Margin_A1==98 ps 10
894 17:02:29.133855 TrainedVREFDQ_A0==74
895 17:02:29.138197 TrainedVREFDQ_A1==75
896 17:02:29.138614 VrefDac_Margin_A0==25
897 17:02:29.138865 DeviceVref_Margin_A0==40
898 17:02:29.144027 VrefDac_Margin_A1==25
899 17:02:29.144749 DeviceVref_Margin_A1==39
900 17:02:29.145275
901 17:02:29.145785
902 17:02:29.149452 channel==1
903 17:02:29.150156 RxClkDly_Margin_A0==88 ps 9
904 17:02:29.150695 TxDqDly_Margin_A0==98 ps 10
905 17:02:29.155129 RxClkDly_Margin_A1==98 ps 10
906 17:02:29.155849 TxDqDly_Margin_A1==98 ps 10
907 17:02:29.160620 TrainedVREFDQ_A0==77
908 17:02:29.161054 TrainedVREFDQ_A1==77
909 17:02:29.161303 VrefDac_Margin_A0==22
910 17:02:29.166248 DeviceVref_Margin_A0==37
911 17:02:29.166906 VrefDac_Margin_A1==24
912 17:02:29.172022 DeviceVref_Margin_A1==37
913 17:02:29.172687
914 17:02:29.173218 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 17:02:29.177816
916 17:02:29.205477 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
917 17:02:29.206271 2D training succeed
918 17:02:29.210979 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 17:02:29.216908 auto size-- 65535DDR cs0 size: 2048MB
920 17:02:29.217984 DDR cs1 size: 2048MB
921 17:02:29.222201 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 17:02:29.222752 cs0 DataBus test pass
923 17:02:29.227815 cs1 DataBus test pass
924 17:02:29.228541 cs0 AddrBus test pass
925 17:02:29.228962 cs1 AddrBus test pass
926 17:02:29.229359
927 17:02:29.233752 100bdlr_step_size ps== 420
928 17:02:29.234586 result report
929 17:02:29.239020 boot times 0Enable ddr reg access
930 17:02:29.244443 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 17:02:29.261670 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 17:02:29.831430 0.0;M3 CHK:0;cm4_sp_mode 0
933 17:02:29.832153 MVN_1=0x00000000
934 17:02:29.836945 MVN_2=0x00000000
935 17:02:29.842608 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 17:02:29.843125 OPS=0x10
937 17:02:29.843587 ring efuse init
938 17:02:29.844070 chipver efuse init
939 17:02:29.848213 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 17:02:29.853793 [0.018961 Inits done]
941 17:02:29.854303 secure task start!
942 17:02:29.854760 high task start!
943 17:02:29.858402 low task start!
944 17:02:29.858916 run into bl31
945 17:02:29.865082 NOTICE: BL31: v1.3(release):4fc40b1
946 17:02:29.872853 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 17:02:29.873173 NOTICE: BL31: G12A normal boot!
948 17:02:29.898202 NOTICE: BL31: BL33 decompress pass
949 17:02:29.903819 ERROR: Error initializing runtime service opteed_fast
950 17:02:31.137025
951 17:02:31.137727
952 17:02:31.145547 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 17:02:31.146074
954 17:02:31.146534 Model: Libre Computer AML-A311D-CC Alta
955 17:02:31.353803 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 17:02:31.377343 DRAM: 2 GiB (effective 3.8 GiB)
957 17:02:31.520268 Core: 408 devices, 31 uclasses, devicetree: separate
958 17:02:31.526158 WDT: Not starting watchdog@f0d0
959 17:02:31.558402 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 17:02:31.570742 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 17:02:31.575949 ** Bad device specification mmc 0 **
962 17:02:31.585993 Card did not respond to voltage select! : -110
963 17:02:31.593835 ** Bad device specification mmc 0 **
964 17:02:31.594345 Couldn't find partition mmc 0
965 17:02:31.602071 Card did not respond to voltage select! : -110
966 17:02:31.607570 ** Bad device specification mmc 0 **
967 17:02:31.608113 Couldn't find partition mmc 0
968 17:02:31.612790 Error: could not access storage.
969 17:02:31.955085 Net: eth0: ethernet@ff3f0000
970 17:02:31.955758 starting USB...
971 17:02:32.206768 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 17:02:32.207171 Starting the controller
973 17:02:32.216027 USB XHCI 1.10
974 17:02:33.767954 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
975 17:02:33.776189 scanning usb for storage devices... 0 Storage Device(s) found
977 17:02:33.827208 Hit any key to stop autoboot: 1
978 17:02:33.828065 end: 2.4.2 bootloader-interrupt (duration 00:00:33) [common]
979 17:02:33.828430 start: 2.4.3 bootloader-commands (timeout 00:04:27) [common]
980 17:02:33.828687 Setting prompt string to ['=>']
981 17:02:33.828951 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:27)
982 17:02:33.833707 0
983 17:02:33.834312 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
984 17:02:33.834605 Sending with 10 millisecond of delay
986 17:02:34.969209 => setenv autoload no
987 17:02:34.980096 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
988 17:02:34.985504 setenv autoload no
989 17:02:34.986275 Sending with 10 millisecond of delay
991 17:02:36.783290 => setenv initrd_high 0xffffffff
992 17:02:36.794174 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
993 17:02:36.795106 setenv initrd_high 0xffffffff
994 17:02:36.795869 Sending with 10 millisecond of delay
996 17:02:38.412306 => setenv fdt_high 0xffffffff
997 17:02:38.423152 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
998 17:02:38.424089 setenv fdt_high 0xffffffff
999 17:02:38.424857 Sending with 10 millisecond of delay
1001 17:02:38.716754 => dhcp
1002 17:02:38.727540 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1003 17:02:38.728461 dhcp
1004 17:02:38.728939 Speed: 1000, full duplex
1005 17:02:38.729388 BOOTP broadcast 1
1006 17:02:38.940533 DHCP client bound to address 192.168.6.27 (212 ms)
1007 17:02:38.941355 Sending with 10 millisecond of delay
1009 17:02:40.618209 => setenv serverip 192.168.6.2
1010 17:02:40.630181 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1011 17:02:40.630767 setenv serverip 192.168.6.2
1012 17:02:40.631229 Sending with 10 millisecond of delay
1014 17:02:44.354151 => tftpboot 0x01080000 975512/tftp-deploy-walxjqqj/kernel/uImage
1015 17:02:44.364922 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1016 17:02:44.365469 tftpboot 0x01080000 975512/tftp-deploy-walxjqqj/kernel/uImage
1017 17:02:44.365713 Speed: 1000, full duplex
1018 17:02:44.365924 Using ethernet@ff3f0000 device
1019 17:02:44.367843 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1020 17:02:44.373761 Filename '975512/tftp-deploy-walxjqqj/kernel/uImage'.
1021 17:02:44.376977 Load address: 0x1080000
1022 17:02:47.237655 Loading: *################################################## 43.6 MiB
1023 17:02:47.238073 15.2 MiB/s
1024 17:02:47.238286 done
1025 17:02:47.241978 Bytes transferred = 45713984 (2b98a40 hex)
1026 17:02:47.242511 Sending with 10 millisecond of delay
1028 17:02:51.929720 => tftpboot 0x08000000 975512/tftp-deploy-walxjqqj/ramdisk/ramdisk.cpio.gz.uboot
1029 17:02:51.940269 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:09)
1030 17:02:51.940797 tftpboot 0x08000000 975512/tftp-deploy-walxjqqj/ramdisk/ramdisk.cpio.gz.uboot
1031 17:02:51.941039 Speed: 1000, full duplex
1032 17:02:51.941250 Using ethernet@ff3f0000 device
1033 17:02:51.942864 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1034 17:02:51.953692 Filename '975512/tftp-deploy-walxjqqj/ramdisk/ramdisk.cpio.gz.uboot'.
1035 17:02:51.954162 Load address: 0x8000000
1036 17:02:56.061996 Loading: *###################### UDP wrong checksum 000000ff 00009f54
1037 17:02:56.102500 UDP wrong checksum 000000ff 00003847
1038 17:02:58.795249 T ########################### UDP wrong checksum 00000005 0000b165
1039 17:03:03.796893 T UDP wrong checksum 00000005 0000b165
1040 17:03:13.799626 T T UDP wrong checksum 00000005 0000b165
1041 17:03:24.745489 T T UDP wrong checksum 000000ff 00003f97
1042 17:03:24.796861 UDP wrong checksum 000000ff 0000cb89
1043 17:03:33.802887 T T UDP wrong checksum 00000005 0000b165
1044 17:03:48.807844 T T
1045 17:03:48.808522 Retry count exceeded; starting again
1047 17:03:48.809961 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1050 17:03:48.811834 end: 2.4 uboot-commands (duration 00:01:48) [common]
1052 17:03:48.813277 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1054 17:03:48.814268 end: 2 uboot-action (duration 00:01:48) [common]
1056 17:03:48.815758 Cleaning after the job
1057 17:03:48.816339 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975512/tftp-deploy-walxjqqj/ramdisk
1058 17:03:48.817601 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975512/tftp-deploy-walxjqqj/kernel
1059 17:03:48.845881 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975512/tftp-deploy-walxjqqj/dtb
1060 17:03:48.847137 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975512/tftp-deploy-walxjqqj/nfsrootfs
1061 17:03:48.886689 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/975512/tftp-deploy-walxjqqj/modules
1062 17:03:48.895691 start: 4.1 power-off (timeout 00:00:30) [common]
1063 17:03:48.896429 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1064 17:03:48.931394 >> OK - accepted request
1065 17:03:48.933197 Returned 0 in 0 seconds
1066 17:03:49.033953 end: 4.1 power-off (duration 00:00:00) [common]
1068 17:03:49.035035 start: 4.2 read-feedback (timeout 00:10:00) [common]
1069 17:03:49.035718 Listened to connection for namespace 'common' for up to 1s
1070 17:03:50.035938 Finalising connection for namespace 'common'
1071 17:03:50.036717 Disconnecting from shell: Finalise
1072 17:03:50.037236 =>
1073 17:03:50.138222 end: 4.2 read-feedback (duration 00:00:01) [common]
1074 17:03:50.138805 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/975512
1075 17:03:53.147119 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/975512
1076 17:03:53.147746 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.