Boot log: beaglebone-black
- Warnings: 3
- Kernel Warnings: 101
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 15:04:50.250557 lava-dispatcher, installed at version: 2024.01
2 15:04:50.251949 start: 0 validate
3 15:04:50.252577 Start time: 2024-11-08 15:04:50.252542+00:00 (UTC)
4 15:04:50.253144 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 15:04:50.253767 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 15:04:50.297318 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 15:04:50.297919 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frobh%2Ffor-kernelci%2Fdevicetree-fixes-for-6.12-1-35-g07900b9108a8e%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 15:04:50.331406 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 15:04:50.332128 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frobh%2Ffor-kernelci%2Fdevicetree-fixes-for-6.12-1-35-g07900b9108a8e%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 15:04:50.362591 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 15:04:50.363078 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 15:04:50.398653 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 15:04:50.399187 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Frobh%2Ffor-kernelci%2Fdevicetree-fixes-for-6.12-1-35-g07900b9108a8e%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 15:04:50.454355 validate duration: 0.20
16 15:04:50.455383 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 15:04:50.455777 start: 1.1 download-retry (timeout 00:10:00) [common]
18 15:04:50.456535 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 15:04:50.457447 Not decompressing ramdisk as can be used compressed.
20 15:04:50.458201 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 15:04:50.458692 saving as /var/lib/lava/dispatcher/tmp/959812/tftp-deploy-tac2bht3/ramdisk/initrd.cpio.gz
22 15:04:50.459172 total size: 4775763 (4 MB)
23 15:04:50.501194 progress 0 % (0 MB)
24 15:04:50.507641 progress 5 % (0 MB)
25 15:04:50.511973 progress 10 % (0 MB)
26 15:04:50.516289 progress 15 % (0 MB)
27 15:04:50.520388 progress 20 % (0 MB)
28 15:04:50.524119 progress 25 % (1 MB)
29 15:04:50.527553 progress 30 % (1 MB)
30 15:04:50.531501 progress 35 % (1 MB)
31 15:04:50.534977 progress 40 % (1 MB)
32 15:04:50.538473 progress 45 % (2 MB)
33 15:04:50.541923 progress 50 % (2 MB)
34 15:04:50.546334 progress 55 % (2 MB)
35 15:04:50.550021 progress 60 % (2 MB)
36 15:04:50.553712 progress 65 % (2 MB)
37 15:04:50.557785 progress 70 % (3 MB)
38 15:04:50.561372 progress 75 % (3 MB)
39 15:04:50.565087 progress 80 % (3 MB)
40 15:04:50.568784 progress 85 % (3 MB)
41 15:04:50.572616 progress 90 % (4 MB)
42 15:04:50.575707 progress 95 % (4 MB)
43 15:04:50.578929 progress 100 % (4 MB)
44 15:04:50.579684 4 MB downloaded in 0.12 s (37.80 MB/s)
45 15:04:50.580391 end: 1.1.1 http-download (duration 00:00:00) [common]
47 15:04:50.581585 end: 1.1 download-retry (duration 00:00:00) [common]
48 15:04:50.581971 start: 1.2 download-retry (timeout 00:10:00) [common]
49 15:04:50.582331 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 15:04:50.582867 downloading http://storage.kernelci.org/robh/for-kernelci/devicetree-fixes-for-6.12-1-35-g07900b9108a8e/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 15:04:50.583209 saving as /var/lib/lava/dispatcher/tmp/959812/tftp-deploy-tac2bht3/kernel/zImage
52 15:04:50.583454 total size: 11440640 (10 MB)
53 15:04:50.583718 No compression specified
54 15:04:50.624640 progress 0 % (0 MB)
55 15:04:50.633147 progress 5 % (0 MB)
56 15:04:50.641155 progress 10 % (1 MB)
57 15:04:50.649493 progress 15 % (1 MB)
58 15:04:50.657326 progress 20 % (2 MB)
59 15:04:50.665784 progress 25 % (2 MB)
60 15:04:50.673630 progress 30 % (3 MB)
61 15:04:50.681808 progress 35 % (3 MB)
62 15:04:50.690669 progress 40 % (4 MB)
63 15:04:50.698853 progress 45 % (4 MB)
64 15:04:50.706041 progress 50 % (5 MB)
65 15:04:50.713621 progress 55 % (6 MB)
66 15:04:50.720836 progress 60 % (6 MB)
67 15:04:50.728087 progress 65 % (7 MB)
68 15:04:50.735835 progress 70 % (7 MB)
69 15:04:50.743160 progress 75 % (8 MB)
70 15:04:50.750907 progress 80 % (8 MB)
71 15:04:50.758309 progress 85 % (9 MB)
72 15:04:50.766267 progress 90 % (9 MB)
73 15:04:50.773540 progress 95 % (10 MB)
74 15:04:50.780619 progress 100 % (10 MB)
75 15:04:50.781158 10 MB downloaded in 0.20 s (55.19 MB/s)
76 15:04:50.781649 end: 1.2.1 http-download (duration 00:00:00) [common]
78 15:04:50.782505 end: 1.2 download-retry (duration 00:00:00) [common]
79 15:04:50.782786 start: 1.3 download-retry (timeout 00:10:00) [common]
80 15:04:50.783053 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 15:04:50.783523 downloading http://storage.kernelci.org/robh/for-kernelci/devicetree-fixes-for-6.12-1-35-g07900b9108a8e/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 15:04:50.783780 saving as /var/lib/lava/dispatcher/tmp/959812/tftp-deploy-tac2bht3/dtb/am335x-boneblack.dtb
83 15:04:50.784008 total size: 70568 (0 MB)
84 15:04:50.784226 No compression specified
85 15:04:50.824772 progress 46 % (0 MB)
86 15:04:50.825642 progress 92 % (0 MB)
87 15:04:50.826388 progress 100 % (0 MB)
88 15:04:50.826834 0 MB downloaded in 0.04 s (1.57 MB/s)
89 15:04:50.827347 end: 1.3.1 http-download (duration 00:00:00) [common]
91 15:04:50.828278 end: 1.3 download-retry (duration 00:00:00) [common]
92 15:04:50.828593 start: 1.4 download-retry (timeout 00:10:00) [common]
93 15:04:50.828899 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 15:04:50.829384 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 15:04:50.829669 saving as /var/lib/lava/dispatcher/tmp/959812/tftp-deploy-tac2bht3/nfsrootfs/full.rootfs.tar
96 15:04:50.829895 total size: 117747780 (112 MB)
97 15:04:50.830124 Using unxz to decompress xz
98 15:04:50.865375 progress 0 % (0 MB)
99 15:04:51.604562 progress 5 % (5 MB)
100 15:04:52.362879 progress 10 % (11 MB)
101 15:04:53.138973 progress 15 % (16 MB)
102 15:04:53.869163 progress 20 % (22 MB)
103 15:04:54.459809 progress 25 % (28 MB)
104 15:04:55.278051 progress 30 % (33 MB)
105 15:04:56.108432 progress 35 % (39 MB)
106 15:04:56.461025 progress 40 % (44 MB)
107 15:04:56.817732 progress 45 % (50 MB)
108 15:04:57.504362 progress 50 % (56 MB)
109 15:04:58.335368 progress 55 % (61 MB)
110 15:04:59.187516 progress 60 % (67 MB)
111 15:04:59.904755 progress 65 % (73 MB)
112 15:05:00.679261 progress 70 % (78 MB)
113 15:05:01.463530 progress 75 % (84 MB)
114 15:05:02.207603 progress 80 % (89 MB)
115 15:05:02.933639 progress 85 % (95 MB)
116 15:05:03.737527 progress 90 % (101 MB)
117 15:05:04.526065 progress 95 % (106 MB)
118 15:05:05.357151 progress 100 % (112 MB)
119 15:05:05.370700 112 MB downloaded in 14.54 s (7.72 MB/s)
120 15:05:05.371477 end: 1.4.1 http-download (duration 00:00:15) [common]
122 15:05:05.374365 end: 1.4 download-retry (duration 00:00:15) [common]
123 15:05:05.374698 start: 1.5 download-retry (timeout 00:09:45) [common]
124 15:05:05.374981 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 15:05:05.375606 downloading http://storage.kernelci.org/robh/for-kernelci/devicetree-fixes-for-6.12-1-35-g07900b9108a8e/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 15:05:05.375901 saving as /var/lib/lava/dispatcher/tmp/959812/tftp-deploy-tac2bht3/modules/modules.tar
127 15:05:05.378184 total size: 6607544 (6 MB)
128 15:05:05.378489 Using unxz to decompress xz
129 15:05:05.420554 progress 0 % (0 MB)
130 15:05:05.459460 progress 5 % (0 MB)
131 15:05:05.506318 progress 10 % (0 MB)
132 15:05:05.552311 progress 15 % (0 MB)
133 15:05:05.597513 progress 20 % (1 MB)
134 15:05:05.646543 progress 25 % (1 MB)
135 15:05:05.696194 progress 30 % (1 MB)
136 15:05:05.749312 progress 35 % (2 MB)
137 15:05:05.796724 progress 40 % (2 MB)
138 15:05:05.844365 progress 45 % (2 MB)
139 15:05:05.891001 progress 50 % (3 MB)
140 15:05:05.942060 progress 55 % (3 MB)
141 15:05:05.989271 progress 60 % (3 MB)
142 15:05:06.038306 progress 65 % (4 MB)
143 15:05:06.088396 progress 70 % (4 MB)
144 15:05:06.144088 progress 75 % (4 MB)
145 15:05:06.187688 progress 80 % (5 MB)
146 15:05:06.231234 progress 85 % (5 MB)
147 15:05:06.275501 progress 90 % (5 MB)
148 15:05:06.320741 progress 95 % (6 MB)
149 15:05:06.365924 progress 100 % (6 MB)
150 15:05:06.380020 6 MB downloaded in 1.00 s (6.29 MB/s)
151 15:05:06.381114 end: 1.5.1 http-download (duration 00:00:01) [common]
153 15:05:06.382942 end: 1.5 download-retry (duration 00:00:01) [common]
154 15:05:06.383539 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 15:05:06.384168 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 15:05:25.881672 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/959812/extract-nfsrootfs-lmn02c0x
157 15:05:25.882278 end: 1.6.1 extract-nfsrootfs (duration 00:00:19) [common]
158 15:05:25.882608 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
159 15:05:25.883271 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss
160 15:05:25.883779 makedir: /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin
161 15:05:25.884203 makedir: /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/tests
162 15:05:25.884593 makedir: /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/results
163 15:05:25.884961 Creating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-add-keys
164 15:05:25.885581 Creating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-add-sources
165 15:05:25.886287 Creating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-background-process-start
166 15:05:25.886896 Creating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-background-process-stop
167 15:05:25.887481 Creating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-common-functions
168 15:05:25.888038 Creating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-echo-ipv4
169 15:05:25.888599 Creating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-install-packages
170 15:05:25.889133 Creating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-installed-packages
171 15:05:25.889671 Creating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-os-build
172 15:05:25.890194 Creating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-probe-channel
173 15:05:25.890738 Creating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-probe-ip
174 15:05:25.891249 Creating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-target-ip
175 15:05:25.891754 Creating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-target-mac
176 15:05:25.892349 Creating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-target-storage
177 15:05:25.892905 Creating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-test-case
178 15:05:25.893439 Creating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-test-event
179 15:05:25.893962 Creating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-test-feedback
180 15:05:25.894519 Creating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-test-raise
181 15:05:25.895033 Creating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-test-reference
182 15:05:25.895559 Creating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-test-runner
183 15:05:25.896104 Creating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-test-set
184 15:05:25.896652 Creating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-test-shell
185 15:05:25.897197 Updating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-add-keys (debian)
186 15:05:25.897790 Updating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-add-sources (debian)
187 15:05:25.898388 Updating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-install-packages (debian)
188 15:05:25.898937 Updating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-installed-packages (debian)
189 15:05:25.899468 Updating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/bin/lava-os-build (debian)
190 15:05:25.899934 Creating /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/environment
191 15:05:25.900368 LAVA metadata
192 15:05:25.900665 - LAVA_JOB_ID=959812
193 15:05:25.900910 - LAVA_DISPATCHER_IP=192.168.6.2
194 15:05:25.901304 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
195 15:05:25.902390 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 15:05:25.902730 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
197 15:05:25.902965 skipped lava-vland-overlay
198 15:05:25.903234 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 15:05:25.903516 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
200 15:05:25.903755 skipped lava-multinode-overlay
201 15:05:25.904056 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 15:05:25.904349 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
203 15:05:25.904624 Loading test definitions
204 15:05:25.904931 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
205 15:05:25.905173 Using /lava-959812 at stage 0
206 15:05:25.906335 uuid=959812_1.6.2.4.1 testdef=None
207 15:05:25.906670 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 15:05:25.906970 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
209 15:05:25.908709 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 15:05:25.909574 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
212 15:05:25.911691 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 15:05:25.912626 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
215 15:05:25.914784 runner path: /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/0/tests/0_timesync-off test_uuid 959812_1.6.2.4.1
216 15:05:25.915408 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 15:05:25.916310 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
219 15:05:25.916570 Using /lava-959812 at stage 0
220 15:05:25.916957 Fetching tests from https://github.com/kernelci/test-definitions.git
221 15:05:25.917279 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/0/tests/1_kselftest-dt'
222 15:05:29.570205 Running '/usr/bin/git checkout kernelci.org
223 15:05:30.007950 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 15:05:30.009391 uuid=959812_1.6.2.4.5 testdef=None
225 15:05:30.009734 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 15:05:30.010504 start: 1.6.2.4.6 test-overlay (timeout 00:09:20) [common]
228 15:05:30.013410 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 15:05:30.014233 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:20) [common]
231 15:05:30.017974 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 15:05:30.018845 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:20) [common]
234 15:05:30.022472 runner path: /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/0/tests/1_kselftest-dt test_uuid 959812_1.6.2.4.5
235 15:05:30.022781 BOARD='beaglebone-black'
236 15:05:30.022989 BRANCH='robh'
237 15:05:30.023187 SKIPFILE='/dev/null'
238 15:05:30.023387 SKIP_INSTALL='True'
239 15:05:30.023581 TESTPROG_URL='http://storage.kernelci.org/robh/for-kernelci/devicetree-fixes-for-6.12-1-35-g07900b9108a8e/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 15:05:30.023784 TST_CASENAME=''
241 15:05:30.024002 TST_CMDFILES='dt'
242 15:05:30.024595 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 15:05:30.025402 Creating lava-test-runner.conf files
245 15:05:30.025607 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/959812/lava-overlay-mu1otfss/lava-959812/0 for stage 0
246 15:05:30.025960 - 0_timesync-off
247 15:05:30.026201 - 1_kselftest-dt
248 15:05:30.026529 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 15:05:30.026816 start: 1.6.2.5 compress-overlay (timeout 00:09:20) [common]
250 15:05:53.434654 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 15:05:53.435103 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:57) [common]
252 15:05:53.435371 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 15:05:53.435647 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
254 15:05:53.435916 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:57) [common]
255 15:05:53.815603 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 15:05:53.816129 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
257 15:05:53.816417 extracting modules file /var/lib/lava/dispatcher/tmp/959812/tftp-deploy-tac2bht3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/959812/extract-nfsrootfs-lmn02c0x
258 15:05:54.712863 extracting modules file /var/lib/lava/dispatcher/tmp/959812/tftp-deploy-tac2bht3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/959812/extract-overlay-ramdisk-qn5ea7of/ramdisk
259 15:05:55.652301 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 15:05:55.652802 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
261 15:05:55.653107 [common] Applying overlay to NFS
262 15:05:55.653345 [common] Applying overlay /var/lib/lava/dispatcher/tmp/959812/compress-overlay-lrzqwwx8/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/959812/extract-nfsrootfs-lmn02c0x
263 15:05:58.424038 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 15:05:58.424531 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
265 15:05:58.424834 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
266 15:05:58.425135 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 15:05:58.425408 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 15:05:58.425686 start: 1.6.7 configure-preseed-file (timeout 00:08:52) [common]
269 15:05:58.425955 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 15:05:58.426228 start: 1.6.8 compress-ramdisk (timeout 00:08:52) [common]
271 15:05:58.426508 Building ramdisk /var/lib/lava/dispatcher/tmp/959812/extract-overlay-ramdisk-qn5ea7of/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/959812/extract-overlay-ramdisk-qn5ea7of/ramdisk
272 15:05:59.417878 >> 74887 blocks
273 15:06:04.388739 Adding RAMdisk u-boot header.
274 15:06:04.389463 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/959812/extract-overlay-ramdisk-qn5ea7of/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/959812/extract-overlay-ramdisk-qn5ea7of/ramdisk.cpio.gz.uboot
275 15:06:04.552777 output: Image Name:
276 15:06:04.553230 output: Created: Fri Nov 8 15:06:04 2024
277 15:06:04.553454 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 15:06:04.553675 output: Data Size: 14792060 Bytes = 14445.37 KiB = 14.11 MiB
279 15:06:04.553888 output: Load Address: 00000000
280 15:06:04.554094 output: Entry Point: 00000000
281 15:06:04.554302 output:
282 15:06:04.554900 rename /var/lib/lava/dispatcher/tmp/959812/extract-overlay-ramdisk-qn5ea7of/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/959812/tftp-deploy-tac2bht3/ramdisk/ramdisk.cpio.gz.uboot
283 15:06:04.555344 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 15:06:04.555648 end: 1.6 prepare-tftp-overlay (duration 00:00:58) [common]
285 15:06:04.555947 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:46) [common]
286 15:06:04.556277 No LXC device requested
287 15:06:04.556625 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 15:06:04.557160 start: 1.8 deploy-device-env (timeout 00:08:46) [common]
289 15:06:04.557673 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 15:06:04.558088 Checking files for TFTP limit of 4294967296 bytes.
291 15:06:04.561091 end: 1 tftp-deploy (duration 00:01:14) [common]
292 15:06:04.561687 start: 2 uboot-action (timeout 00:05:00) [common]
293 15:06:04.562209 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 15:06:04.562701 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 15:06:04.563197 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 15:06:04.563950 substitutions:
297 15:06:04.564405 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 15:06:04.564807 - {DTB_ADDR}: 0x88000000
299 15:06:04.565203 - {DTB}: 959812/tftp-deploy-tac2bht3/dtb/am335x-boneblack.dtb
300 15:06:04.565596 - {INITRD}: 959812/tftp-deploy-tac2bht3/ramdisk/ramdisk.cpio.gz.uboot
301 15:06:04.565988 - {KERNEL_ADDR}: 0x82000000
302 15:06:04.566376 - {KERNEL}: 959812/tftp-deploy-tac2bht3/kernel/zImage
303 15:06:04.566765 - {LAVA_MAC}: None
304 15:06:04.567194 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/959812/extract-nfsrootfs-lmn02c0x
305 15:06:04.567587 - {NFS_SERVER_IP}: 192.168.6.2
306 15:06:04.567999 - {PRESEED_CONFIG}: None
307 15:06:04.568397 - {PRESEED_LOCAL}: None
308 15:06:04.568784 - {RAMDISK_ADDR}: 0x83000000
309 15:06:04.569169 - {RAMDISK}: 959812/tftp-deploy-tac2bht3/ramdisk/ramdisk.cpio.gz.uboot
310 15:06:04.569558 - {ROOT_PART}: None
311 15:06:04.569943 - {ROOT}: None
312 15:06:04.570332 - {SERVER_IP}: 192.168.6.2
313 15:06:04.570715 - {TEE_ADDR}: 0x83000000
314 15:06:04.571099 - {TEE}: None
315 15:06:04.571484 Parsed boot commands:
316 15:06:04.571856 - setenv autoload no
317 15:06:04.572265 - setenv initrd_high 0xffffffff
318 15:06:04.572652 - setenv fdt_high 0xffffffff
319 15:06:04.573030 - dhcp
320 15:06:04.573408 - setenv serverip 192.168.6.2
321 15:06:04.573786 - tftp 0x82000000 959812/tftp-deploy-tac2bht3/kernel/zImage
322 15:06:04.574169 - tftp 0x83000000 959812/tftp-deploy-tac2bht3/ramdisk/ramdisk.cpio.gz.uboot
323 15:06:04.574550 - setenv initrd_size ${filesize}
324 15:06:04.574928 - tftp 0x88000000 959812/tftp-deploy-tac2bht3/dtb/am335x-boneblack.dtb
325 15:06:04.575310 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/959812/extract-nfsrootfs-lmn02c0x,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 15:06:04.575707 - bootz 0x82000000 0x83000000 0x88000000
327 15:06:04.576219 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 15:06:04.577696 start: 2.3 connect-device (timeout 00:05:00) [common]
330 15:06:04.578110 [common] connect-device Connecting to device using 'telnet conserv1 3003'
331 15:06:04.594625 Setting prompt string to ['lava-test: # ']
332 15:06:04.596160 end: 2.3 connect-device (duration 00:00:00) [common]
333 15:06:04.596756 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 15:06:04.597291 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 15:06:04.597804 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 15:06:04.598970 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-01'
337 15:06:04.635719 >> OK - accepted request
338 15:06:04.637545 Returned 0 in 0 seconds
339 15:06:04.738702 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 15:06:04.740531 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 15:06:04.741159 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 15:06:04.741728 Setting prompt string to ['Hit any key to stop autoboot']
344 15:06:04.742685 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 15:06:04.744453 Trying 192.168.56.21...
346 15:06:04.744969 Connected to conserv1.
347 15:06:04.745425 Escape character is '^]'.
348 15:06:04.745859
349 15:06:04.746292 ser2net port telnet,3003 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.2.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 15:06:04.746735
351 15:06:12.742404
352 15:06:12.742844 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
353 15:06:12.746587 Trying to boot from MMC1
354 15:06:13.322702
355 15:06:13.323145
356 15:06:13.323407 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
357 15:06:13.323650
358 15:06:13.328174 CPU : AM335X-GP rev 2.1
359 15:06:13.328487 Model: TI AM335x BeagleBone Black
360 15:06:13.331268 DRAM: 512 MiB
361 15:06:13.414873 Core: 160 devices, 18 uclasses, devicetree: separate
362 15:06:13.425223 WDT: Started wdt@44e35000 with servicing (60s timeout)
363 15:06:16.787769 7[r[999;999H[6n8NAND:
364 15:06:16.788638 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
365 15:06:16.792028 Trying to boot from MMC1
366 15:06:17.365253
367 15:06:17.365860
368 15:06:17.366301 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
369 15:06:17.366734
370 15:06:17.370840 CPU : AM335X-GP rev 2.1
371 15:06:17.371355 Model: TI AM335x BeagleBone Black
372 15:06:17.374096 DRAM: 512 MiB
373 15:06:17.456856 Core: 160 devices, 18 uclasses, devicetree: separate
374 15:06:17.467291 WDT: Started wdt@44e35000 with servicing (60s timeout)
375 15:06:19.490501 7[r[999;999H[6n8NAND:
376 15:06:19.491138 U-Boot SPL 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
377 15:06:19.495321 Trying to boot from MMC1
378 15:06:20.068443
379 15:06:20.069099
380 15:06:20.069526 U-Boot 2022.07-rc3-dirty (May 24 2022 - 12:39:48 +0100)
381 15:06:20.069942
382 15:06:20.073626 CPU : AM335X-GP rev 2.1
383 15:06:20.074295 Model: TI AM335x BeagleBone Black
384 15:06:20.076898 DRAM: 512 MiB
385 15:06:20.160609 Core: 160 devices, 18 uclasses, devicetree: separate
386 15:06:20.170090 WDT: Started wdt@44e35000 with servicing (60s timeout)
387 15:06:20.675194 7[r[999;999H[6n8NAND: 0 MiB
388 15:06:20.685521 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
389 15:06:20.758343 Loading Environment from FAT... Unable to use mmc 0:1...
390 15:06:20.779597 <ethaddr> not set. Validating first E-fuse MAC
391 15:06:20.810057 Net: eth2: ethernet@4a100000, eth3: usb_ether
393 15:06:20.868422 Hit any key to stop autoboot: 2
394 15:06:20.869254 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
395 15:06:20.869647 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
396 15:06:20.869960 Setting prompt string to ['=>']
397 15:06:20.870278 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
398 15:06:20.878598 0
399 15:06:20.879355 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
400 15:06:20.879890 Sending with 10 millisecond of delay
402 15:06:22.014963 => setenv autoload no
403 15:06:22.025852 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
404 15:06:22.029318 setenv autoload no
405 15:06:22.030344 Sending with 10 millisecond of delay
407 15:06:23.830233 => setenv initrd_high 0xffffffff
408 15:06:23.841032 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
409 15:06:23.841926 setenv initrd_high 0xffffffff
410 15:06:23.842689 Sending with 10 millisecond of delay
412 15:06:25.459631 => setenv fdt_high 0xffffffff
413 15:06:25.470486 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
414 15:06:25.471123 setenv fdt_high 0xffffffff
415 15:06:25.471606 Sending with 10 millisecond of delay
417 15:06:25.763126 => dhcp
418 15:06:25.773964 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
419 15:06:25.774941 dhcp
420 15:06:25.776535 link up on port 0, speed 100, full duplex
421 15:06:25.777065 BOOTP broadcast 1
422 15:06:25.798244 DHCP client bound to address 192.168.6.12 (18 ms)
423 15:06:25.799134 Sending with 10 millisecond of delay
425 15:06:27.476100 => setenv serverip 192.168.6.2
426 15:06:27.486919 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:37)
427 15:06:27.487855 setenv serverip 192.168.6.2
428 15:06:27.488678 Sending with 10 millisecond of delay
430 15:06:30.972958 => tftp 0x82000000 959812/tftp-deploy-tac2bht3/kernel/zImage
431 15:06:30.983811 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
432 15:06:30.984749 tftp 0x82000000 959812/tftp-deploy-tac2bht3/kernel/zImage
433 15:06:30.985263 link up on port 0, speed 100, full duplex
434 15:06:30.989470 Using ethernet@4a100000 device
435 15:06:30.994433 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
436 15:06:30.994934 Filename '959812/tftp-deploy-tac2bht3/kernel/zImage'.
437 15:06:30.998065 Load address: 0x82000000
438 15:06:33.171292 Loading: *################################################## 10.9 MiB
439 15:06:33.171929 5 MiB/s
440 15:06:33.172503 done
441 15:06:33.175318 Bytes transferred = 11440640 (ae9200 hex)
442 15:06:33.176160 Sending with 10 millisecond of delay
444 15:06:37.624662 => tftp 0x83000000 959812/tftp-deploy-tac2bht3/ramdisk/ramdisk.cpio.gz.uboot
445 15:06:37.635541 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
446 15:06:37.636530 tftp 0x83000000 959812/tftp-deploy-tac2bht3/ramdisk/ramdisk.cpio.gz.uboot
447 15:06:37.637051 link up on port 0, speed 100, full duplex
448 15:06:37.640371 Using ethernet@4a100000 device
449 15:06:37.646012 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
450 15:06:37.653502 Filename '959812/tftp-deploy-tac2bht3/ramdisk/ramdisk.cpio.gz.uboot'.
451 15:06:37.654251 Load address: 0x83000000
452 15:06:40.697716 Loading: *################################################## 14.1 MiB
453 15:06:40.698605 4.6 MiB/s
454 15:06:40.699241 done
455 15:06:40.701870 Bytes transferred = 14792124 (e1b5bc hex)
456 15:06:40.702868 Sending with 10 millisecond of delay
458 15:06:42.561737 => setenv initrd_size ${filesize}
459 15:06:42.572708 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
460 15:06:42.573996 setenv initrd_size ${filesize}
461 15:06:42.574997 Sending with 10 millisecond of delay
463 15:06:46.722548 => tftp 0x88000000 959812/tftp-deploy-tac2bht3/dtb/am335x-boneblack.dtb
464 15:06:46.733294 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
465 15:06:46.734138 tftp 0x88000000 959812/tftp-deploy-tac2bht3/dtb/am335x-boneblack.dtb
466 15:06:46.734589 link up on port 0, speed 100, full duplex
467 15:06:46.738167 Using ethernet@4a100000 device
468 15:06:46.743817 TFTP from server 192.168.6.2; our IP address is 192.168.6.12
469 15:06:46.747100 Filename '959812/tftp-deploy-tac2bht3/dtb/am335x-boneblack.dtb'.
470 15:06:46.750872 Load address: 0x88000000
471 15:06:46.764271 Loading: *################################################## 68.9 KiB
472 15:06:46.772005 4.5 MiB/s
473 15:06:46.772545 done
474 15:06:46.772993 Bytes transferred = 70568 (113a8 hex)
475 15:06:46.773698 Sending with 10 millisecond of delay
477 15:06:59.956784 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/959812/extract-nfsrootfs-lmn02c0x,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
478 15:06:59.967365 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
479 15:06:59.967936 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/959812/extract-nfsrootfs-lmn02c0x,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
480 15:06:59.968447 Sending with 10 millisecond of delay
482 15:07:02.306424 => bootz 0x82000000 0x83000000 0x88000000
483 15:07:02.317292 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
484 15:07:02.317869 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
485 15:07:02.318958 bootz 0x82000000 0x83000000 0x88000000
486 15:07:02.319459 Kernel image @ 0x82000000 [ 0x000000 - 0xae9200 ]
487 15:07:02.320072 ## Loading init Ramdisk from Legacy Image at 83000000 ...
488 15:07:02.324970 Image Name:
489 15:07:02.325464 Created: 2024-11-08 15:06:04 UTC
490 15:07:02.328342 Image Type: ARM Linux RAMDisk Image (uncompressed)
491 15:07:02.333786 Data Size: 14792060 Bytes = 14.1 MiB
492 15:07:02.342135 Load Address: 00000000
493 15:07:02.342621 Entry Point: 00000000
494 15:07:02.510590 Verifying Checksum ... OK
495 15:07:02.511151 ## Flattened Device Tree blob at 88000000
496 15:07:02.517056 Booting using the fdt blob at 0x88000000
497 15:07:02.522042 Using Device Tree in place at 88000000, end 880143a7
498 15:07:02.535597
499 15:07:02.536148 Starting kernel ...
500 15:07:02.536619
501 15:07:02.537566 end: 2.4.3 bootloader-commands (duration 00:00:42) [common]
502 15:07:02.538228 start: 2.4.4 auto-login-action (timeout 00:04:02) [common]
503 15:07:02.538754 Setting prompt string to ['Linux version [0-9]']
504 15:07:02.539265 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
505 15:07:02.539784 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
506 15:07:03.378964 [ 0.000000] Booting Linux on physical CPU 0x0
507 15:07:03.384784 start: 2.4.4.1 login-action (timeout 00:04:01) [common]
508 15:07:03.385410 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
509 15:07:03.385930 Setting prompt string to []
510 15:07:03.386479 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
511 15:07:03.387001 Using line separator: #'\n'#
512 15:07:03.387459 No login prompt set.
513 15:07:03.387944 Parsing kernel messages
514 15:07:03.388517 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
515 15:07:03.389391 [login-action] Waiting for messages, (timeout 00:04:01)
516 15:07:03.389891 Waiting using forced prompt support (timeout 00:02:01)
517 15:07:03.401525 [ 0.000000] Linux version 6.12.0-rc1 (KernelCI@build-j368966-arm-gcc-12-multi-v7-defconfig-nmltx) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Fri Nov 8 14:42:55 UTC 2024
518 15:07:03.407381 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
519 15:07:03.412900 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
520 15:07:03.424335 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
521 15:07:03.430068 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
522 15:07:03.435929 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
523 15:07:03.436497 [ 0.000000] Memory policy: Data cache writeback
524 15:07:03.442668 [ 0.000000] efi: UEFI not found.
525 15:07:03.451212 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
526 15:07:03.451697 [ 0.000000] Zone ranges:
527 15:07:03.456844 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
528 15:07:03.462610 [ 0.000000] Normal empty
529 15:07:03.468396 [ 0.000000] HighMem empty
530 15:07:03.468880 [ 0.000000] Movable zone start for each node
531 15:07:03.474163 [ 0.000000] Early memory node ranges
532 15:07:03.479872 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
533 15:07:03.487548 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
534 15:07:03.509083 [ 0.000000] OF: reserved mem: Reserved memory: No reserved-memory node in the DT
535 15:07:03.521324 [ 0.000000] CPU: All CPU(s) started in SVC mode.
536 15:07:03.526968 [ 0.000000] AM335X ES2.1 (sgx neon)
537 15:07:03.538661 [ 0.000000] percpu: Embedded 17 pages/cpu s40844 r8192 d20596 u69632
538 15:07:03.559246 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/959812/extract-nfsrootfs-lmn02c0x,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
539 15:07:03.565122 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
540 15:07:03.576473 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
541 15:07:03.582351 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
542 15:07:03.589394 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
543 15:07:03.618408 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
544 15:07:03.624352 <6>[ 0.000000] trace event string verifier disabled
545 15:07:03.624837 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
546 15:07:03.630111 <6>[ 0.000000] rcu: RCU event tracing is enabled.
547 15:07:03.641537 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
548 15:07:03.647271 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
549 15:07:03.653557 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
550 15:07:03.669469 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
551 15:07:03.686611 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
552 15:07:03.693377 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
553 15:07:03.785115 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
554 15:07:03.796601 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
555 15:07:03.803311 <6>[ 0.008339] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
556 15:07:03.816549 <6>[ 0.019151] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
557 15:07:03.823708 <6>[ 0.033961] Console: colour dummy device 80x30
558 15:07:03.829891 Matched prompt #6: WARNING:
559 15:07:03.830433 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
560 15:07:03.835328 <3>[ 0.038857] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
561 15:07:03.838063 <3>[ 0.045927] This ensures that you still see kernel messages. Please
562 15:07:03.844379 <3>[ 0.052653] update your kernel commandline.
563 15:07:03.884999 <6>[ 0.057263] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
564 15:07:03.890639 <6>[ 0.096156] CPU: Testing write buffer coherency: ok
565 15:07:03.896642 <6>[ 0.101521] CPU0: Spectre v2: using BPIALL workaround
566 15:07:03.897146 <6>[ 0.106986] pid_max: default: 32768 minimum: 301
567 15:07:03.908077 <6>[ 0.112179] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
568 15:07:03.914961 <6>[ 0.120003] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
569 15:07:03.921083 <6>[ 0.129343] CPU0: thread -1, cpu 0, socket -1, mpidr 0
570 15:07:03.987764 <6>[ 0.189541] Setting up static identity map for 0x80300000 - 0x803000ac
571 15:07:03.993564 <6>[ 0.199156] rcu: Hierarchical SRCU implementation.
572 15:07:03.996344 <6>[ 0.204444] rcu: Max phase no-delay instances is 1000.
573 15:07:04.005638 <6>[ 0.215429] EFI services will not be available.
574 15:07:04.011310 <6>[ 0.220779] smp: Bringing up secondary CPUs ...
575 15:07:04.017133 <6>[ 0.225750] smp: Brought up 1 node, 1 CPU
576 15:07:04.022861 <6>[ 0.230235] SMP: Total of 1 processors activated (996.14 BogoMIPS).
577 15:07:04.028859 <6>[ 0.236957] CPU: All CPU(s) started in SVC mode.
578 15:07:04.048378 <6>[ 0.242157] Memory: 405996K/522240K available (16384K kernel code, 2542K rwdata, 6788K rodata, 2048K init, 429K bss, 49052K reserved, 65536K cma-reserved, 0K highmem)
579 15:07:04.048974 <6>[ 0.258428] devtmpfs: initialized
580 15:07:04.071868 <6>[ 0.275918] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
581 15:07:04.080470 <6>[ 0.284523] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
582 15:07:04.089245 <6>[ 0.294967] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
583 15:07:04.100162 <6>[ 0.307259] pinctrl core: initialized pinctrl subsystem
584 15:07:04.109424 <6>[ 0.317889] DMI not present or invalid.
585 15:07:04.117599 <6>[ 0.323736] NET: Registered PF_NETLINK/PF_ROUTE protocol family
586 15:07:04.126185 <6>[ 0.332667] DMA: preallocated 256 KiB pool for atomic coherent allocations
587 15:07:04.141483 <6>[ 0.344114] thermal_sys: Registered thermal governor 'step_wise'
588 15:07:04.142009 <6>[ 0.344286] cpuidle: using governor menu
589 15:07:04.169688 <6>[ 0.379854] No ATAGs?
590 15:07:04.174767 <6>[ 0.382496] hw-breakpoint: debug architecture 0x4 unsupported.
591 15:07:04.186442 <6>[ 0.394420] Serial: AMBA PL011 UART driver
592 15:07:04.218016 <6>[ 0.425701] iommu: Default domain type: Translated
593 15:07:04.224759 <6>[ 0.431049] iommu: DMA domain TLB invalidation policy: strict mode
594 15:07:04.250995 <5>[ 0.460392] SCSI subsystem initialized
595 15:07:04.265975 <6>[ 0.470529] usbcore: registered new interface driver usbfs
596 15:07:04.272942 <6>[ 0.476486] usbcore: registered new interface driver hub
597 15:07:04.273452 <6>[ 0.482318] usbcore: registered new device driver usb
598 15:07:04.280412 <6>[ 0.488804] pps_core: LinuxPPS API ver. 1 registered
599 15:07:04.291920 <6>[ 0.494233] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
600 15:07:04.299085 <6>[ 0.503948] PTP clock support registered
601 15:07:04.299625 <6>[ 0.508397] EDAC MC: Ver: 3.0.0
602 15:07:04.346289 <6>[ 0.553836] scmi_core: SCMI protocol bus registered
603 15:07:04.370935 <6>[ 0.580346] vgaarb: loaded
604 15:07:04.376929 <6>[ 0.584124] clocksource: Switched to clocksource dmtimer
605 15:07:04.401296 <6>[ 0.610996] NET: Registered PF_INET protocol family
606 15:07:04.414003 <6>[ 0.616700] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
607 15:07:04.419643 <6>[ 0.625532] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
608 15:07:04.431007 <6>[ 0.634458] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
609 15:07:04.436891 <6>[ 0.642702] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
610 15:07:04.448455 <6>[ 0.650986] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
611 15:07:04.454138 <6>[ 0.658704] TCP: Hash tables configured (established 4096 bind 4096)
612 15:07:04.459907 <6>[ 0.665625] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
613 15:07:04.465829 <6>[ 0.672637] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
614 15:07:04.472846 <6>[ 0.680252] NET: Registered PF_UNIX/PF_LOCAL protocol family
615 15:07:04.559521 <6>[ 0.763818] RPC: Registered named UNIX socket transport module.
616 15:07:04.560235 <6>[ 0.770249] RPC: Registered udp transport module.
617 15:07:04.565162 <6>[ 0.775380] RPC: Registered tcp transport module.
618 15:07:04.570889 <6>[ 0.780487] RPC: Registered tcp-with-tls transport module.
619 15:07:04.583918 <6>[ 0.786409] RPC: Registered tcp NFSv4.1 backchannel transport module.
620 15:07:04.584575 <6>[ 0.793317] PCI: CLS 0 bytes, default 64
621 15:07:04.590179 <5>[ 0.799107] Initialise system trusted keyrings
622 15:07:04.612085 <6>[ 0.819178] Trying to unpack rootfs image as initramfs...
623 15:07:04.691172 <6>[ 0.895050] workingset: timestamp_bits=30 max_order=17 bucket_order=0
624 15:07:04.695906 <6>[ 0.902562] squashfs: version 4.0 (2009/01/31) Phillip Lougher
625 15:07:04.734842 <5>[ 0.944812] NFS: Registering the id_resolver key type
626 15:07:04.740628 <5>[ 0.950410] Key type id_resolver registered
627 15:07:04.746297 <5>[ 0.955094] Key type id_legacy registered
628 15:07:04.752106 <6>[ 0.959538] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
629 15:07:04.760830 <6>[ 0.966737] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
630 15:07:04.830850 <5>[ 1.040798] Key type asymmetric registered
631 15:07:04.836547 <5>[ 1.045373] Asymmetric key parser 'x509' registered
632 15:07:04.848024 <6>[ 1.050800] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
633 15:07:04.848586 <6>[ 1.058714] io scheduler mq-deadline registered
634 15:07:04.853766 <6>[ 1.063648] io scheduler kyber registered
635 15:07:04.859334 <6>[ 1.068139] io scheduler bfq registered
636 15:07:04.963060 <6>[ 1.170403] ledtrig-cpu: registered to indicate activity on CPUs
637 15:07:05.241238 <6>[ 1.448498] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
638 15:07:05.278696 <6>[ 1.488712] msm_serial: driver initialized
639 15:07:05.284753 <6>[ 1.493498] SuperH (H)SCI(F) driver initialized
640 15:07:05.290725 <6>[ 1.498833] STMicroelectronics ASC driver initialized
641 15:07:05.295927 <6>[ 1.504508] STM32 USART driver initialized
642 15:07:05.407245 <6>[ 1.616756] brd: module loaded
643 15:07:05.455894 <6>[ 1.665164] loop: module loaded
644 15:07:05.483002 <6>[ 1.692238] CAN device driver interface
645 15:07:05.489703 <6>[ 1.697532] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
646 15:07:05.495606 <6>[ 1.704608] e1000e: Intel(R) PRO/1000 Network Driver
647 15:07:05.501294 <6>[ 1.709992] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
648 15:07:05.507018 <6>[ 1.716462] igb: Intel(R) Gigabit Ethernet Network Driver
649 15:07:05.515218 <6>[ 1.722285] igb: Copyright (c) 2007-2014 Intel Corporation.
650 15:07:05.527007 <6>[ 1.731537] pegasus: Pegasus/Pegasus II USB Ethernet driver
651 15:07:05.532903 <6>[ 1.737695] usbcore: registered new interface driver pegasus
652 15:07:05.535566 <6>[ 1.743818] usbcore: registered new interface driver asix
653 15:07:05.541423 <6>[ 1.749705] usbcore: registered new interface driver ax88179_178a
654 15:07:05.547188 <6>[ 1.756295] usbcore: registered new interface driver cdc_ether
655 15:07:05.552992 <6>[ 1.762590] usbcore: registered new interface driver smsc75xx
656 15:07:05.564403 <6>[ 1.768833] usbcore: registered new interface driver smsc95xx
657 15:07:05.570192 <6>[ 1.775063] usbcore: registered new interface driver net1080
658 15:07:05.576097 <6>[ 1.781194] usbcore: registered new interface driver cdc_subset
659 15:07:05.581824 <6>[ 1.787607] usbcore: registered new interface driver zaurus
660 15:07:05.586766 <6>[ 1.793652] usbcore: registered new interface driver cdc_ncm
661 15:07:05.596668 <6>[ 1.803103] usbcore: registered new interface driver usb-storage
662 15:07:05.878522 <6>[ 2.086797] i2c_dev: i2c /dev entries driver
663 15:07:05.938334 <5>[ 2.140478] cpuidle: enable-method property 'ti,am3352' found operations
664 15:07:05.944148 <6>[ 2.150111] sdhci: Secure Digital Host Controller Interface driver
665 15:07:05.952051 <6>[ 2.156885] sdhci: Copyright(c) Pierre Ossman
666 15:07:05.959379 <6>[ 2.163335] Synopsys Designware Multimedia Card Interface Driver
667 15:07:05.963818 <6>[ 2.171365] sdhci-pltfm: SDHCI platform and OF driver helper
668 15:07:06.090948 <6>[ 2.293646] usbcore: registered new interface driver usbhid
669 15:07:06.091525 <6>[ 2.299830] usbhid: USB HID core driver
670 15:07:06.133000 <6>[ 2.340764] NET: Registered PF_INET6 protocol family
671 15:07:06.175775 <6>[ 2.386041] Segment Routing with IPv6
672 15:07:06.181655 <6>[ 2.390188] In-situ OAM (IOAM) with IPv6
673 15:07:06.188365 <6>[ 2.394716] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
674 15:07:06.194093 <6>[ 2.401951] NET: Registered PF_PACKET protocol family
675 15:07:06.200199 <6>[ 2.407532] can: controller area network core
676 15:07:06.205842 <6>[ 2.412365] NET: Registered PF_CAN protocol family
677 15:07:06.206391 <6>[ 2.417595] can: raw protocol
678 15:07:06.211690 <6>[ 2.420920] can: broadcast manager protocol
679 15:07:06.218118 <6>[ 2.425517] can: netlink gateway - max_hops=1
680 15:07:06.224323 <5>[ 2.431021] Key type dns_resolver registered
681 15:07:06.230569 <6>[ 2.436086] ThumbEE CPU extension supported.
682 15:07:06.231075 <5>[ 2.440772] Registering SWP/SWPB emulation handler
683 15:07:06.240229 <3>[ 2.446472] omap_voltage_late_init: Voltage driver support not added
684 15:07:06.446140 <5>[ 2.654545] Loading compiled-in X.509 certificates
685 15:07:06.576081 <6>[ 2.773339] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
686 15:07:06.582959 <6>[ 2.790012] pinctrl-single 44e10800.pinmux: 142 pins, size 568
687 15:07:06.608843 <3>[ 2.813741] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
688 15:07:06.819153 <3>[ 3.024260] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
689 15:07:07.027452 <6>[ 3.235887] OMAP GPIO hardware version 0.1
690 15:07:07.048052 <6>[ 3.254715] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
691 15:07:07.139573 <4>[ 3.346498] at24 2-0054: supply vcc not found, using dummy regulator
692 15:07:07.174780 <4>[ 3.381003] at24 2-0055: supply vcc not found, using dummy regulator
693 15:07:07.217108 <4>[ 3.423446] at24 2-0056: supply vcc not found, using dummy regulator
694 15:07:07.251451 <4>[ 3.457814] at24 2-0057: supply vcc not found, using dummy regulator
695 15:07:07.290460 <6>[ 3.498103] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
696 15:07:07.367561 <3>[ 3.570545] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
697 15:07:07.392092 <6>[ 3.591409] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
698 15:07:07.414066 <4>[ 3.617613] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
699 15:07:07.421761 <4>[ 3.626820] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
700 15:07:07.568050 <6>[ 3.774435] omap_rng 48310000.rng: Random Number Generator ver. 20
701 15:07:07.591462 <5>[ 3.800618] random: crng init done
702 15:07:07.625104 <6>[ 3.833618] Freeing initrd memory: 14448K
703 15:07:07.639358 <6>[ 3.844197] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
704 15:07:07.692631 <6>[ 3.896553] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
705 15:07:07.698266 <4>[ 3.906881] ------------[ cut here ]------------
706 15:07:07.709904 <4>[ 3.911918] WARNING: CPU: 0 PID: 38 at drivers/base/regmap/regmap.c:1208 devm_regmap_field_alloc+0xb8/0xc4
707 15:07:07.715633 <4>[ 3.922217] invalid empty mask defined
708 15:07:07.716305 <4>[ 3.926356] Modules linked in:
709 15:07:07.721263 <4>[ 3.929779] CPU: 0 UID: 0 PID: 38 Comm: kworker/u4:4 Not tainted 6.12.0-rc1 #1
710 15:07:07.732909 <4>[ 3.937482] Hardware name: Generic AM33XX (Flattened Device Tree)
711 15:07:07.738538 <4>[ 3.944019] Workqueue: events_unbound deferred_probe_work_func
712 15:07:07.739105 <4>[ 3.950304] Call trace:
713 15:07:07.744250 <4>[ 3.950323] unwind_backtrace from show_stack+0x10/0x14
714 15:07:07.750016 <4>[ 3.958851] show_stack from dump_stack_lvl+0x68/0x74
715 15:07:07.755887 <4>[ 3.964329] dump_stack_lvl from __warn+0x7c/0x12c
716 15:07:07.761518 <4>[ 3.969545] __warn from warn_slowpath_fmt+0x124/0x190
717 15:07:07.767258 <4>[ 3.975107] warn_slowpath_fmt from devm_regmap_field_alloc+0xb8/0xc4
718 15:07:07.773023 <4>[ 3.982016] devm_regmap_field_alloc from cpsw_ale_create+0x124/0x368
719 15:07:07.784460 <4>[ 3.988937] cpsw_ale_create from cpsw_init_common+0x238/0x37c
720 15:07:07.790259 <4>[ 3.995217] cpsw_init_common from cpsw_probe+0x530/0xc60
721 15:07:07.796007 <4>[ 4.001052] cpsw_probe from platform_probe+0x5c/0xb0
722 15:07:07.801702 <4>[ 4.006530] platform_probe from really_probe+0xc8/0x2c8
723 15:07:07.807485 <4>[ 4.012274] really_probe from __driver_probe_device+0x88/0x19c
724 15:07:07.813222 <4>[ 4.018639] __driver_probe_device from driver_probe_device+0x30/0x104
725 15:07:07.818943 <4>[ 4.025630] driver_probe_device from __device_attach_driver+0x94/0x108
726 15:07:07.824870 <4>[ 4.032712] __device_attach_driver from bus_for_each_drv+0x90/0xe4
727 15:07:07.830422 <4>[ 4.039433] bus_for_each_drv from __device_attach+0xa8/0x1a4
728 15:07:07.836292 <4>[ 4.045620] __device_attach from bus_probe_device+0x88/0x8c
729 15:07:07.841889 <4>[ 4.051716] bus_probe_device from device_add+0x5a8/0x77c
730 15:07:07.853608 <4>[ 4.057543] device_add from of_platform_device_create_pdata+0x90/0xbc
731 15:07:07.859105 <4>[ 4.064546] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
732 15:07:07.865008 <4>[ 4.072789] of_platform_bus_create from of_platform_populate+0x70/0xd4
733 15:07:07.870809 <4>[ 4.079871] of_platform_populate from sysc_probe+0x100c/0x1418
734 15:07:07.876334 <4>[ 4.086243] sysc_probe from platform_probe+0x5c/0xb0
735 15:07:07.882103 <4>[ 4.091715] platform_probe from really_probe+0xc8/0x2c8
736 15:07:07.888068 <4>[ 4.097455] really_probe from __driver_probe_device+0x88/0x19c
737 15:07:07.899240 <4>[ 4.103824] __driver_probe_device from driver_probe_device+0x30/0x104
738 15:07:07.905029 <4>[ 4.110814] driver_probe_device from __device_attach_driver+0x94/0x108
739 15:07:07.910728 <4>[ 4.117895] __device_attach_driver from bus_for_each_drv+0x90/0xe4
740 15:07:07.916482 <4>[ 4.124616] bus_for_each_drv from __device_attach+0xa8/0x1a4
741 15:07:07.922206 <4>[ 4.130801] __device_attach from bus_probe_device+0x88/0x8c
742 15:07:07.927949 <4>[ 4.136897] bus_probe_device from device_add+0x5a8/0x77c
743 15:07:07.933746 <4>[ 4.142725] device_add from of_platform_device_create_pdata+0x90/0xbc
744 15:07:07.945172 <4>[ 4.149715] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
745 15:07:07.950885 <4>[ 4.157960] of_platform_bus_create from of_platform_populate+0x70/0xd4
746 15:07:07.956629 <4>[ 4.165042] of_platform_populate from simple_pm_bus_probe+0xc8/0xec
747 15:07:07.962379 <4>[ 4.171854] simple_pm_bus_probe from platform_probe+0x5c/0xb0
748 15:07:07.968126 <4>[ 4.178130] platform_probe from really_probe+0xc8/0x2c8
749 15:07:07.979543 <4>[ 4.183872] really_probe from __driver_probe_device+0x88/0x19c
750 15:07:07.985306 <4>[ 4.190237] __driver_probe_device from driver_probe_device+0x30/0x104
751 15:07:07.991173 <4>[ 4.197229] driver_probe_device from __device_attach_driver+0x94/0x108
752 15:07:07.996923 <4>[ 4.204309] __device_attach_driver from bus_for_each_drv+0x90/0xe4
753 15:07:08.002552 <4>[ 4.211031] bus_for_each_drv from __device_attach+0xa8/0x1a4
754 15:07:08.008272 <4>[ 4.217216] __device_attach from bus_probe_device+0x88/0x8c
755 15:07:08.014000 <4>[ 4.223314] bus_probe_device from device_add+0x5a8/0x77c
756 15:07:08.025474 <4>[ 4.229140] device_add from of_platform_device_create_pdata+0x90/0xbc
757 15:07:08.031203 <4>[ 4.236128] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
758 15:07:08.037016 <4>[ 4.244373] of_platform_bus_create from of_platform_populate+0x70/0xd4
759 15:07:08.042688 <4>[ 4.251455] of_platform_populate from simple_pm_bus_probe+0xc8/0xec
760 15:07:08.048529 <4>[ 4.258267] simple_pm_bus_probe from platform_probe+0x5c/0xb0
761 15:07:08.054199 <4>[ 4.264542] platform_probe from really_probe+0xc8/0x2c8
762 15:07:08.065803 <4>[ 4.270284] really_probe from __driver_probe_device+0x88/0x19c
763 15:07:08.071432 <4>[ 4.276650] __driver_probe_device from driver_probe_device+0x30/0x104
764 15:07:08.077202 <4>[ 4.283644] driver_probe_device from __device_attach_driver+0x94/0x108
765 15:07:08.083003 <4>[ 4.290726] __device_attach_driver from bus_for_each_drv+0x90/0xe4
766 15:07:08.088633 <4>[ 4.297449] bus_for_each_drv from __device_attach+0xa8/0x1a4
767 15:07:08.094429 <4>[ 4.303634] __device_attach from bus_probe_device+0x88/0x8c
768 15:07:08.100290 <4>[ 4.309731] bus_probe_device from device_add+0x5a8/0x77c
769 15:07:08.111629 <4>[ 4.315555] device_add from of_platform_device_create_pdata+0x90/0xbc
770 15:07:08.117221 <4>[ 4.322546] of_platform_device_create_pdata from of_platform_bus_create+0x194/0x36c
771 15:07:08.123067 <4>[ 4.330793] of_platform_bus_create from of_platform_populate+0x70/0xd4
772 15:07:08.128706 <4>[ 4.337874] of_platform_populate from simple_pm_bus_probe+0xc8/0xec
773 15:07:08.140244 <4>[ 4.344688] simple_pm_bus_probe from platform_probe+0x5c/0xb0
774 15:07:08.145960 <4>[ 4.350963] platform_probe from really_probe+0xc8/0x2c8
775 15:07:08.151711 <4>[ 4.356703] really_probe from __driver_probe_device+0x88/0x19c
776 15:07:08.157420 <4>[ 4.363070] __driver_probe_device from driver_probe_device+0x30/0x104
777 15:07:08.163193 <4>[ 4.370059] driver_probe_device from __device_attach_driver+0x94/0x108
778 15:07:08.168905 <4>[ 4.377139] __device_attach_driver from bus_for_each_drv+0x90/0xe4
779 15:07:08.174706 <4>[ 4.383863] bus_for_each_drv from __device_attach+0xa8/0x1a4
780 15:07:08.180366 <4>[ 4.390048] __device_attach from bus_probe_device+0x88/0x8c
781 15:07:08.192016 <4>[ 4.396143] bus_probe_device from deferred_probe_work_func+0x78/0xa4
782 15:07:08.197632 <4>[ 4.403043] deferred_probe_work_func from process_one_work+0x178/0x3c0
783 15:07:08.203389 <4>[ 4.410137] process_one_work from worker_thread+0x264/0x42c
784 15:07:08.209167 <4>[ 4.416242] worker_thread from kthread+0xe0/0xfc
785 15:07:08.214908 <4>[ 4.421369] kthread from ret_from_fork+0x14/0x28
786 15:07:08.220542 <4>[ 4.426485] Exception stack(0xe0131fb0 to 0xe0131ff8)
787 15:07:08.226404 <4>[ 4.431949] 1fa0: 00000000 00000000 00000000 00000000
788 15:07:08.237778 <4>[ 4.440633] 1fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
789 15:07:08.243550 <4>[ 4.449316] 1fe0: 00000000 00000000 00000000 00000000 00000013 00000000
790 15:07:08.249375 <4>[ 4.456504] ---[ end trace 0000000000000000 ]---
791 15:07:08.250466 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
792 15:07:08.251031 login-action: kernel 'warning'
793 15:07:08.251575 [login-action] Waiting for messages, (timeout 00:03:56)
794 15:07:08.252120 Waiting using forced prompt support (timeout 00:01:58)
795 15:07:08.255200 <6>[ 4.461594] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
796 15:07:08.261362 <6>[ 4.468887] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
797 15:07:08.272968 <6>[ 4.476491] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
798 15:07:08.284367 <6>[ 4.484631] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
799 15:07:08.291942 <6>[ 4.496261] cpsw-switch 4a100000.switch: Detected MACID = 78:a5:04:e2:4c:3d
800 15:07:08.302750 <5>[ 4.505326] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
801 15:07:08.330445 <3>[ 4.535148] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
802 15:07:08.336182 <6>[ 4.543610] edma 49000000.dma: TI EDMA DMA engine driver
803 15:07:08.407527 <3>[ 4.611469] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
804 15:07:08.422394 <6>[ 4.625950] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
805 15:07:08.435331 <3>[ 4.643049] l3-aon-clkctrl:0000:0: failed to disable
806 15:07:08.480816 <6>[ 4.685282] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
807 15:07:08.486416 <6>[ 4.694749] printk: legacy console [ttyS0] enabled
808 15:07:08.490573 <6>[ 4.694749] printk: legacy console [ttyS0] enabled
809 15:07:08.494862 <6>[ 4.705073] printk: legacy bootconsole [omap8250] disabled
810 15:07:08.503743 <6>[ 4.705073] printk: legacy bootconsole [omap8250] disabled
811 15:07:08.541266 <4>[ 4.744868] tps65217-pmic: Failed to locate of_node [id: -1]
812 15:07:08.544925 <4>[ 4.752244] tps65217-bl: Failed to locate of_node [id: -1]
813 15:07:08.561473 <6>[ 4.772054] tps65217 0-0024: TPS65217 ID 0xe version 1.2
814 15:07:08.580047 <6>[ 4.779023] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
815 15:07:08.592173 <6>[ 4.792729] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
816 15:07:08.596672 <6>[ 4.804595] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
817 15:07:08.619514 <6>[ 4.824457] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
818 15:07:08.625554 <6>[ 4.833512] sdhci-omap 48060000.mmc: Got CD GPIO
819 15:07:08.632805 <4>[ 4.838711] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
820 15:07:08.648491 <4>[ 4.852479] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
821 15:07:08.654749 <4>[ 4.861231] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
822 15:07:08.663578 <4>[ 4.869827] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
823 15:07:08.763362 <6>[ 4.969285] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
824 15:07:08.805866 <6>[ 5.011407] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
825 15:07:08.826213 <6>[ 5.030419] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
826 15:07:08.832084 <6>[ 5.039270] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
827 15:07:08.872428 <6>[ 5.073988] mmc0: new high speed SDHC card at address 1234
828 15:07:08.873020 <6>[ 5.081814] mmcblk0: mmc0:1234 SA32G 29.1 GiB
829 15:07:08.880475 <6>[ 5.090766] mmcblk0: p1
830 15:07:08.913245 <6>[ 5.115405] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
831 15:07:08.936892 <6>[ 5.138201] mmc1: new high speed MMC card at address 0001
832 15:07:08.937477 <6>[ 5.145315] mmcblk1: mmc1:0001 MMC04G 3.60 GiB
833 15:07:08.945321 <6>[ 5.153219] mmcblk1boot0: mmc1:0001 MMC04G 2.00 MiB
834 15:07:08.953538 <6>[ 5.161035] mmcblk1boot1: mmc1:0001 MMC04G 2.00 MiB
835 15:07:08.959119 <6>[ 5.168745] mmcblk1rpmb: mmc1:0001 MMC04G 128 KiB, chardev (236:0)
836 15:07:11.029851 <6>[ 7.235154] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
837 15:07:11.093886 <5>[ 7.264140] Sending DHCP requests ., OK
838 15:07:11.105230 <6>[ 7.308603] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.12
839 15:07:11.105754 <6>[ 7.316779] IP-Config: Complete:
840 15:07:11.116397 <6>[ 7.320319] device=eth0, hwaddr=78:a5:04:e2:4c:3d, ipaddr=192.168.6.12, mask=255.255.255.0, gw=192.168.6.1
841 15:07:11.122250 <6>[ 7.330836] host=192.168.6.12, domain=, nis-domain=(none)
842 15:07:11.134438 <6>[ 7.337064] bootserver=192.168.6.1, rootserver=192.168.6.2, rootpath=
843 15:07:11.134925 <6>[ 7.337098] nameserver0=10.255.253.1
844 15:07:11.140598 <6>[ 7.349668] clk: Disabling unused clocks
845 15:07:11.146372 <6>[ 7.354410] PM: genpd: Disabling unused power domains
846 15:07:11.165763 <6>[ 7.372879] Freeing unused kernel image (initmem) memory: 2048K
847 15:07:11.173393 <6>[ 7.382625] Run /init as init process
848 15:07:11.197685 Loading, please wait...
849 15:07:11.273853 Starting systemd-udevd version 252.22-1~deb12u1
850 15:07:14.320444 <4>[ 10.524368] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
851 15:07:14.541464 <4>[ 10.744696] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
852 15:07:14.735423 <6>[ 10.946062] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
853 15:07:14.745250 <6>[ 10.951737] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
854 15:07:14.896888 <6>[ 11.106057] tda998x 0-0070: found TDA19988
855 15:07:14.986141 <6>[ 11.195669] hub 1-0:1.0: USB hub found
856 15:07:15.035377 <6>[ 11.244301] hub 1-0:1.0: 1 port detected
857 15:07:17.858925 Begin: Loading essential drivers ... done.
858 15:07:17.864630 Begin: Running /scripts/init-premount ... done.
859 15:07:17.870111 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
860 15:07:17.879629 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
861 15:07:17.887714 Device /sys/class/net/eth0 found
862 15:07:17.888247 done.
863 15:07:17.964102 Begin: Waiting up to 180 secs for any network device to become available ... done.
864 15:07:18.046616 IP-Config: eth0 hardware address 78:a5:04:e2:4c:3d mtu 1500 DHCP
865 15:07:18.067632 IP-Config: eth0 guessed broadcast address 192.168.6.255
866 15:07:18.073155 IP-Config: eth0 complete (dhcp from 192.168.6.1):
867 15:07:18.078588 address: 192.168.6.12 broadcast: 192.168.6.255 netmask: 255.255.255.0
868 15:07:18.087652 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
869 15:07:18.092394 rootserver: 192.168.6.1 rootpath:
870 15:07:18.092922 filename :
871 15:07:18.235174 done.
872 15:07:18.246378 Begin: Running /scripts/nfs-bottom ... done.
873 15:07:18.309333 Begin: Running /scripts/init-bottom ... done.
874 15:07:19.917908 <30>[ 16.124624] systemd[1]: System time before build time, advancing clock.
875 15:07:20.116486 <30>[ 16.296875] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
876 15:07:20.125191 <30>[ 16.333925] systemd[1]: Detected architecture arm.
877 15:07:20.139222
878 15:07:20.139773 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
879 15:07:20.140286
880 15:07:20.167652 <30>[ 16.374881] systemd[1]: Hostname set to <debian-bookworm-armhf>.
881 15:07:22.328415 <30>[ 18.535563] systemd[1]: Queued start job for default target graphical.target.
882 15:07:22.346004 <30>[ 18.550023] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
883 15:07:22.353626 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
884 15:07:22.386302 <30>[ 18.590023] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
885 15:07:22.393772 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
886 15:07:22.423730 <30>[ 18.626821] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
887 15:07:22.430756 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
888 15:07:22.464639 <30>[ 18.667946] systemd[1]: Created slice user.slice - User and Session Slice.
889 15:07:22.471360 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
890 15:07:22.496346 <30>[ 18.695374] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
891 15:07:22.501466 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
892 15:07:22.520506 <30>[ 18.725230] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
893 15:07:22.529505 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
894 15:07:22.561520 <30>[ 18.755206] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
895 15:07:22.568015 <30>[ 18.775735] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
896 15:07:22.576035 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
897 15:07:22.599619 <30>[ 18.804629] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
898 15:07:22.607811 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
899 15:07:22.630246 <30>[ 18.834992] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
900 15:07:22.638695 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
901 15:07:22.660118 <30>[ 18.865076] systemd[1]: Reached target paths.target - Path Units.
902 15:07:22.664234 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
903 15:07:22.689976 <30>[ 18.894802] systemd[1]: Reached target remote-fs.target - Remote File Systems.
904 15:07:22.697268 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
905 15:07:22.719685 <30>[ 18.924661] systemd[1]: Reached target slices.target - Slice Units.
906 15:07:22.725184 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
907 15:07:22.750005 <30>[ 18.954960] systemd[1]: Reached target swap.target - Swaps.
908 15:07:22.754024 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
909 15:07:22.780176 <30>[ 18.984937] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
910 15:07:22.789099 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
911 15:07:22.810952 <30>[ 19.015606] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
912 15:07:22.819199 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
913 15:07:22.902335 <30>[ 19.102234] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
914 15:07:22.915316 <30>[ 19.119943] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
915 15:07:22.923078 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
916 15:07:22.952044 <30>[ 19.155942] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
917 15:07:22.958342 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
918 15:07:22.983362 <30>[ 19.187829] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
919 15:07:22.990998 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
920 15:07:23.018941 <30>[ 19.225260] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
921 15:07:23.030552 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
922 15:07:23.051514 <30>[ 19.255557] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
923 15:07:23.058944 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
924 15:07:23.086319 <30>[ 19.285997] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
925 15:07:23.105009 <30>[ 19.304599] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
926 15:07:23.152963 <30>[ 19.359448] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
927 15:07:23.182749 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
928 15:07:23.240121 <30>[ 19.446602] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
929 15:07:23.255776 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
930 15:07:23.323159 <30>[ 19.527589] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
931 15:07:23.347977 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
932 15:07:23.400756 <30>[ 19.605800] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
933 15:07:23.418712 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
934 15:07:23.469926 <30>[ 19.675400] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
935 15:07:23.490767 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
936 15:07:23.517232 <30>[ 19.723237] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
937 15:07:23.538826 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
938 15:07:23.580830 <30>[ 19.785578] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
939 15:07:23.609636 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
940 15:07:23.661211 <30>[ 19.866925] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
941 15:07:23.686878 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
942 15:07:23.740254 <30>[ 19.945958] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
943 15:07:23.757175 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
944 15:07:23.787433 <28>[ 19.986468] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
945 15:07:23.795965 <28>[ 20.000916] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
946 15:07:23.839875 <30>[ 20.046131] systemd[1]: Starting systemd-journald.service - Journal Service...
947 15:07:23.857618 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
948 15:07:23.931297 <30>[ 20.136835] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
949 15:07:23.945619 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
950 15:07:23.984779 <30>[ 20.190594] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
951 15:07:24.038924 Starting [0;1;39msystemd-network-g… units from Kernel command line...
952 15:07:24.123003 <30>[ 20.327244] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
953 15:07:24.168814 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
954 15:07:24.241113 <30>[ 20.447079] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
955 15:07:24.281266 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
956 15:07:24.339906 <30>[ 20.545893] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
957 15:07:24.378905 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
958 15:07:24.390507 <30>[ 20.596311] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
959 15:07:24.430415 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
960 15:07:24.453792 <30>[ 20.658523] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
961 15:07:24.489474 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
962 15:07:24.629472 <30>[ 20.836993] systemd[1]: modprobe@configfs.service: Deactivated successfully.
963 15:07:24.660428 <30>[ 20.865790] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
964 15:07:24.688540 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
965 15:07:24.710319 <30>[ 20.917001] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
966 15:07:24.749547 <30>[ 20.954645] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
967 15:07:24.758195 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
968 15:07:24.770220 <30>[ 20.977149] systemd[1]: modprobe@drm.service: Deactivated successfully.
969 15:07:24.799594 <30>[ 21.005876] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
970 15:07:24.828634 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
971 15:07:24.850713 <30>[ 21.055856] systemd[1]: Started systemd-journald.service - Journal Service.
972 15:07:24.857648 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
973 15:07:24.890951 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
974 15:07:24.920218 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
975 15:07:24.944477 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
976 15:07:24.982744 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
977 15:07:25.002926 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
978 15:07:25.031884 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
979 15:07:25.059693 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
980 15:07:25.119121 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
981 15:07:25.168791 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
982 15:07:25.221391 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
983 15:07:25.304922 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
984 15:07:25.356396 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
985 15:07:25.533636 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
986 15:07:25.589270 <46>[ 21.795132] systemd-journald[163]: Received client request to flush runtime journal.
987 15:07:25.680545 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
988 15:07:25.782989 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
989 15:07:26.690802 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
990 15:07:26.771601 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
991 15:07:27.392194 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
992 15:07:27.558767 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
993 15:07:27.581776 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
994 15:07:27.599524 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
995 15:07:27.670277 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
996 15:07:27.712506 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
997 15:07:28.631910 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
998 15:07:28.690413 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
999 15:07:28.985465 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1000 15:07:29.110148 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1001 15:07:29.160562 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1002 15:07:31.121905 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1003 15:07:31.329528 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1004 15:07:31.794437 <5>[ 28.000737] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1005 15:07:32.460020 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
1006 15:07:33.261266 <5>[ 29.469663] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1007 15:07:33.312947 <5>[ 29.516413] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1008 15:07:33.318707 <4>[ 29.526655] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1009 15:07:33.326690 <6>[ 29.535746] cfg80211: failed to load regulatory.db
1010 15:07:33.830650 <46>[ 30.027754] systemd-journald[163]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1011 15:07:33.975596 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1012 15:07:34.076553 <46>[ 30.276039] systemd-journald[163]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
1013 15:07:34.443838 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1014 15:07:42.909099 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1015 15:07:42.929944 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1016 15:07:42.951325 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1017 15:07:42.971406 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1018 15:07:43.044478 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1019 15:07:43.072894 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1020 15:07:43.130897 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1021 15:07:43.201928 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
1022 15:07:43.241130 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1023 15:07:43.274698 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1024 15:07:43.304006 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1025 15:07:43.346033 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1026 15:07:43.372758 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1027 15:07:43.420006 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1028 15:07:43.446789 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1029 15:07:43.480113 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1030 15:07:43.509095 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1031 15:07:43.534535 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1032 15:07:43.560704 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1033 15:07:43.582002 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1034 15:07:43.619351 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1035 15:07:43.639324 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1036 15:07:43.661136 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1037 15:07:43.729243 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1038 15:07:43.768124 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1039 15:07:43.884762 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1040 15:07:43.971327 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1041 15:07:44.032174 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1042 15:07:44.060257 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1043 15:07:44.090848 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1044 15:07:44.294509 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1045 15:07:44.368767 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1046 15:07:44.440243 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
1047 15:07:44.469258 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1048 15:07:44.488642 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1049 15:07:44.673690 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1050 15:07:45.010058 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1051 15:07:45.057253 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1052 15:07:45.086572 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1053 15:07:45.169264 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1054 15:07:45.332310 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1055 15:07:45.473649
1056 15:07:45.477608 Debian GNU/Linux 12 debian-brm-armhf login: root (automatic login)
1057 15:07:45.478126
1058 15:07:45.812809 Linux debian-bookworm-armhf 6.12.0-rc1 #1 SMP Fri Nov 8 14:42:55 UTC 2024 armv7l
1059 15:07:45.813225
1060 15:07:45.818424 The programs included with the Debian GNU/Linux system are free software;
1061 15:07:45.824020 the exact distribution terms for each program are described in the
1062 15:07:45.829491 individual files in /usr/share/doc/*/copyright.
1063 15:07:45.829799
1064 15:07:45.837692 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1065 15:07:45.838009 permitted by applicable law.
1066 15:07:50.524748 Matched prompt #10: / #
1068 15:07:50.527316 Kernel warnings or errors detected.
1069 15:07:50.527777 Setting prompt string to ['/ #']
1070 15:07:50.528392 end: 2.4.4.1 login-action (duration 00:00:47) [common]
1072 15:07:50.530921 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
1073 15:07:50.531537 start: 2.4.5 expect-shell-connection (timeout 00:03:14) [common]
1074 15:07:50.531974 Setting prompt string to ['/ #']
1075 15:07:50.532418 Forcing a shell prompt, looking for ['/ #']
1077 15:07:50.583393 / #
1078 15:07:50.584199 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1079 15:07:50.584713 Waiting using forced prompt support (timeout 00:02:30)
1080 15:07:50.589237
1081 15:07:50.595304 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1082 15:07:50.595899 start: 2.4.6 export-device-env (timeout 00:03:14) [common]
1083 15:07:50.596410 Sending with 10 millisecond of delay
1085 15:07:55.586695 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/959812/extract-nfsrootfs-lmn02c0x'
1086 15:07:55.597793 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/959812/extract-nfsrootfs-lmn02c0x'
1087 15:07:55.598775 Sending with 10 millisecond of delay
1089 15:07:57.698960 / # export NFS_SERVER_IP='192.168.6.2'
1090 15:07:57.710016 export NFS_SERVER_IP='192.168.6.2'
1091 15:07:57.711554 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1092 15:07:57.712316 end: 2.4 uboot-commands (duration 00:01:53) [common]
1093 15:07:57.713045 end: 2 uboot-action (duration 00:01:53) [common]
1094 15:07:57.713712 start: 3 lava-test-retry (timeout 00:06:53) [common]
1095 15:07:57.714395 start: 3.1 lava-test-shell (timeout 00:06:53) [common]
1096 15:07:57.714948 Using namespace: common
1098 15:07:57.816384 / # #
1099 15:07:57.817268 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1100 15:07:57.821234 #
1101 15:07:57.828142 Using /lava-959812
1103 15:07:57.929540 / # export SHELL=/bin/bash
1104 15:07:57.935304 export SHELL=/bin/bash
1106 15:07:58.042902 / # . /lava-959812/environment
1107 15:07:58.048616 . /lava-959812/environment
1109 15:07:58.162024 / # /lava-959812/bin/lava-test-runner /lava-959812/0
1110 15:07:58.163426 Test shell timeout: 10s (minimum of the action and connection timeout)
1111 15:07:58.166643 /lava-959812/bin/lava-test-runner /lava-959812/0
1112 15:07:58.600508 + export TESTRUN_ID=0_timesync-off
1113 15:07:58.607662 + TESTRUN_ID=0_timesync-off
1114 15:07:58.608653 + cd /lava-959812/0/tests/0_timesync-off
1115 15:07:58.609295 ++ cat uuid
1116 15:07:58.629438 + UUID=959812_1.6.2.4.1
1117 15:07:58.630030 + set +x
1118 15:07:58.638384 <LAVA_SIGNAL_STARTRUN 0_timesync-off 959812_1.6.2.4.1>
1119 15:07:58.639204 + systemctl stop systemd-timesyncd
1120 15:07:58.640075 Received signal: <STARTRUN> 0_timesync-off 959812_1.6.2.4.1
1121 15:07:58.640521 Starting test lava.0_timesync-off (959812_1.6.2.4.1)
1122 15:07:58.640952 Skipping test definition patterns.
1123 15:07:58.896439 + set +x
1124 15:07:58.897129 <LAVA_SIGNAL_ENDRUN 0_timesync-off 959812_1.6.2.4.1>
1125 15:07:58.897886 Received signal: <ENDRUN> 0_timesync-off 959812_1.6.2.4.1
1126 15:07:58.898522 Ending use of test pattern.
1127 15:07:58.899022 Ending test lava.0_timesync-off (959812_1.6.2.4.1), duration 0.26
1129 15:07:59.130001 + export TESTRUN_ID=1_kselftest-dt
1130 15:07:59.137757 + TESTRUN_ID=1_kselftest-dt
1131 15:07:59.138406 + cd /lava-959812/0/tests/1_kselftest-dt
1132 15:07:59.138932 ++ cat uuid
1133 15:07:59.157452 + UUID=959812_1.6.2.4.5
1134 15:07:59.158131 + set +x
1135 15:07:59.163248 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 959812_1.6.2.4.5>
1136 15:07:59.164142 + cd ./automated/linux/kselftest/
1137 15:07:59.165123 Received signal: <STARTRUN> 1_kselftest-dt 959812_1.6.2.4.5
1138 15:07:59.165723 Starting test lava.1_kselftest-dt (959812_1.6.2.4.5)
1139 15:07:59.166417 Skipping test definition patterns.
1140 15:07:59.192075 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/robh/for-kernelci/devicetree-fixes-for-6.12-1-35-g07900b9108a8e/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g robh -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1141 15:07:59.309987 INFO: install_deps skipped
1142 15:07:59.793822 --2024-11-08 15:07:59-- http://storage.kernelci.org/robh/for-kernelci/devicetree-fixes-for-6.12-1-35-g07900b9108a8e/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1143 15:07:59.806419 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1144 15:07:59.951561 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1145 15:08:00.095429 HTTP request sent, awaiting response... 200 OK
1146 15:08:00.096134 Length: 4095908 (3.9M) [application/octet-stream]
1147 15:08:00.100969 Saving to: 'kselftest_armhf.tar.gz'
1148 15:08:00.101483
1149 15:08:01.622851
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 176KB/s
kselftest_armhf.tar 4%[ ] 194.76K 338KB/s
kselftest_armhf.tar 19%[==> ] 792.85K 929KB/s
kselftest_armhf.tar 56%[==========> ] 2.20M 2.09MB/s
kselftest_armhf.tar 89%[================> ] 3.51M 2.56MB/s
kselftest_armhf.tar 100%[===================>] 3.91M 2.57MB/s in 1.5s
1150 15:08:01.623476
1151 15:08:02.240974 2024-11-08 15:08:01 (2.57 MB/s) - 'kselftest_armhf.tar.gz' saved [4095908/4095908]
1152 15:08:02.241602
1153 15:08:14.394108 skiplist:
1154 15:08:14.394723 ========================================
1155 15:08:14.399854 ========================================
1156 15:08:14.495099 dt:test_unprobed_devices.sh
1157 15:08:14.530045 ============== Tests to run ===============
1158 15:08:14.537176 dt:test_unprobed_devices.sh
1159 15:08:14.541152 ===========End Tests to run ===============
1160 15:08:14.549484 shardfile-dt pass
1161 15:08:14.800777 <12>[ 71.012979] kselftest: Running tests in dt
1162 15:08:14.827720 TAP version 13
1163 15:08:14.852421 1..1
1164 15:08:14.906340 # timeout set to 45
1165 15:08:14.907234 # selftests: dt: test_unprobed_devices.sh
1166 15:08:15.745666 # TAP version 13
1167 15:08:40.729956 # 1..257
1168 15:08:40.906532 # ok 1 / # SKIP
1169 15:08:40.927229 # ok 2 /clk_mcasp0
1170 15:08:40.999041 # ok 3 /clk_mcasp0_fixed # SKIP
1171 15:08:41.068930 # ok 4 /cpus/cpu@0 # SKIP
1172 15:08:41.140100 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1173 15:08:41.163269 # ok 6 /fixedregulator0
1174 15:08:41.183446 # ok 7 /leds
1175 15:08:41.204494 # ok 8 /ocp
1176 15:08:41.223344 # ok 9 /ocp/interconnect@44c00000
1177 15:08:41.250452 # ok 10 /ocp/interconnect@44c00000/segment@0
1178 15:08:41.280080 # ok 11 /ocp/interconnect@44c00000/segment@100000
1179 15:08:41.297775 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1180 15:08:41.367424 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1181 15:08:41.387579 # ok 14 /ocp/interconnect@44c00000/segment@200000
1182 15:08:41.414349 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1183 15:08:41.515586 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1184 15:08:41.589770 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1185 15:08:41.661277 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1186 15:08:41.732472 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1187 15:08:41.804545 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1188 15:08:41.875073 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1189 15:08:41.946039 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1190 15:08:42.021099 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1191 15:08:42.092444 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1192 15:08:42.163828 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1193 15:08:42.234290 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1194 15:08:42.305055 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1195 15:08:42.380914 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1196 15:08:42.454394 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1197 15:08:42.524251 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1198 15:08:42.593622 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1199 15:08:42.665032 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1200 15:08:42.741281 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1201 15:08:42.813245 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1202 15:08:42.884808 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1203 15:08:42.952625 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1204 15:08:43.027157 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1205 15:08:43.095116 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1206 15:08:43.167619 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1207 15:08:43.239503 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1208 15:08:43.310671 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1209 15:08:43.382537 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1210 15:08:43.454139 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1211 15:08:43.525900 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1212 15:08:43.596016 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1213 15:08:43.672587 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1214 15:08:43.744257 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1215 15:08:43.815570 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1216 15:08:43.883689 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1217 15:08:43.962956 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1218 15:08:44.028466 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1219 15:08:44.100273 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1220 15:08:44.171869 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1221 15:08:44.243861 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1222 15:08:44.315777 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1223 15:08:44.387091 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1224 15:08:44.459584 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1225 15:08:44.531251 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1226 15:08:44.602943 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1227 15:08:44.677800 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1228 15:08:44.751738 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1229 15:08:44.825478 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1230 15:08:44.895584 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1231 15:08:44.966492 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1232 15:08:45.042118 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1233 15:08:45.114805 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1234 15:08:45.186151 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1235 15:08:45.253400 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1236 15:08:45.332789 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1237 15:08:45.402581 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1238 15:08:45.475022 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1239 15:08:45.547061 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1240 15:08:45.623105 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1241 15:08:45.712490 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1242 15:08:45.793651 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1243 15:08:45.865529 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1244 15:08:45.939754 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1245 15:08:46.017251 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1246 15:08:46.095163 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1247 15:08:46.165654 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1248 15:08:46.234881 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1249 15:08:46.326457 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1250 15:08:46.390982 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1251 15:08:46.464783 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1252 15:08:46.535878 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1253 15:08:46.633043 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1254 15:08:46.710456 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1255 15:08:46.782954 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1256 15:08:46.856344 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1257 15:08:46.924735 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1258 15:08:46.993617 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1259 15:08:47.071744 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1260 15:08:47.138988 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1261 15:08:47.210624 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1262 15:08:47.230829 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1263 15:08:47.258995 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1264 15:08:47.283148 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1265 15:08:47.304220 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1266 15:08:47.325391 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1267 15:08:47.349583 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1268 15:08:47.380838 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1269 15:08:47.401115 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1270 15:08:47.502662 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1271 15:08:47.527245 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1272 15:08:47.551025 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1273 15:08:47.574766 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1274 15:08:47.680362 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1275 15:08:47.754610 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1276 15:08:47.826174 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1277 15:08:47.902666 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1278 15:08:47.974607 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1279 15:08:48.041912 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1280 15:08:48.112045 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1281 15:08:48.184268 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1282 15:08:48.256222 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1283 15:08:48.326856 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1284 15:08:48.404561 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1285 15:08:48.476692 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1286 15:08:48.546985 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1287 15:08:48.617712 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1288 15:08:48.688321 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1289 15:08:48.761497 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1290 15:08:48.783666 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1291 15:08:48.853589 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1292 15:08:48.927762 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1293 15:08:48.995623 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1294 15:08:49.017290 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1295 15:08:49.088892 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1296 15:08:49.110516 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1297 15:08:49.181253 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1298 15:08:49.203806 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1299 15:08:49.227910 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1300 15:08:49.252046 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1301 15:08:49.279387 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1302 15:08:49.301411 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1303 15:08:49.322567 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1304 15:08:49.352235 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1305 15:08:49.426337 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1306 15:08:49.441924 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1307 15:08:49.465750 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1308 15:08:49.536864 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1309 15:08:49.609090 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1310 15:08:49.629975 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1311 15:08:49.734140 # not ok 144 /ocp/interconnect@47c00000
1312 15:08:49.801092 # not ok 145 /ocp/interconnect@47c00000/segment@0
1313 15:08:49.826176 # ok 146 /ocp/interconnect@48000000
1314 15:08:49.849755 # ok 147 /ocp/interconnect@48000000/segment@0
1315 15:08:49.870009 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1316 15:08:49.893289 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1317 15:08:49.920516 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1318 15:08:49.941955 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1319 15:08:49.963347 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1320 15:08:49.991857 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1321 15:08:50.011664 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1322 15:08:50.086012 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1323 15:08:50.158030 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1324 15:08:50.179586 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1325 15:08:50.202355 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1326 15:08:50.222901 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1327 15:08:50.246396 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1328 15:08:50.271683 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1329 15:08:50.297402 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1330 15:08:50.315909 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1331 15:08:50.342552 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1332 15:08:50.363373 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1333 15:08:50.392363 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1334 15:08:50.411121 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1335 15:08:50.434639 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1336 15:08:50.456760 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1337 15:08:50.480285 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1338 15:08:50.507383 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1339 15:08:50.531954 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1340 15:08:50.551071 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1341 15:08:50.580958 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1342 15:08:50.600355 # ok 175 /ocp/interconnect@48000000/segment@100000
1343 15:08:50.622760 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1344 15:08:50.646898 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1345 15:08:50.720380 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1346 15:08:50.803948 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1347 15:08:50.875276 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1348 15:08:50.948378 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1349 15:08:51.018413 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1350 15:08:51.091417 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1351 15:08:51.161068 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1352 15:08:51.234984 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1353 15:08:51.254369 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1354 15:08:51.277299 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1355 15:08:51.300427 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1356 15:08:51.322921 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1357 15:08:51.348849 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1358 15:08:51.377483 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1359 15:08:51.400348 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1360 15:08:51.422421 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1361 15:08:51.443698 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1362 15:08:51.466983 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1363 15:08:51.491811 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1364 15:08:51.518570 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1365 15:08:51.539588 # ok 198 /ocp/interconnect@48000000/segment@200000
1366 15:08:51.561866 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1367 15:08:51.632142 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1368 15:08:51.652306 # ok 201 /ocp/interconnect@48000000/segment@300000
1369 15:08:51.676256 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1370 15:08:51.701999 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1371 15:08:51.724609 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1372 15:08:51.747227 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1373 15:08:51.771820 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1374 15:08:51.797751 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1375 15:08:51.869485 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1376 15:08:51.887484 # ok 209 /ocp/interconnect@4a000000
1377 15:08:51.909740 # ok 210 /ocp/interconnect@4a000000/segment@0
1378 15:08:51.934234 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1379 15:08:51.960627 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1380 15:08:51.983283 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1381 15:08:52.003484 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1382 15:08:52.078811 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1383 15:08:52.183800 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1384 15:08:52.249438 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1385 15:08:52.353169 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1386 15:08:52.422980 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1387 15:08:52.493989 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1388 15:08:52.591367 # not ok 221 /ocp/interconnect@4b140000
1389 15:08:52.663849 # not ok 222 /ocp/interconnect@4b140000/segment@0
1390 15:08:52.733624 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1391 15:08:52.755159 # ok 224 /ocp/target-module@40300000
1392 15:08:52.779711 # ok 225 /ocp/target-module@40300000/sram@0
1393 15:08:52.849119 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1394 15:08:52.921531 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1395 15:08:52.945024 # ok 228 /ocp/target-module@47400000
1396 15:08:52.969327 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1397 15:08:52.990035 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1398 15:08:53.014230 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1399 15:08:53.036696 # ok 232 /ocp/target-module@47400000/usb@1400
1400 15:08:53.059802 # ok 233 /ocp/target-module@47400000/usb@1800
1401 15:08:53.079517 # ok 234 /ocp/target-module@47810000
1402 15:08:53.102984 # ok 235 /ocp/target-module@49000000
1403 15:08:53.122443 # ok 236 /ocp/target-module@49000000/dma@0
1404 15:08:53.149213 # ok 237 /ocp/target-module@49800000
1405 15:08:53.168687 # ok 238 /ocp/target-module@49800000/dma@0
1406 15:08:53.194234 # ok 239 /ocp/target-module@49900000
1407 15:08:53.219680 # ok 240 /ocp/target-module@49900000/dma@0
1408 15:08:53.248136 # ok 241 /ocp/target-module@49a00000
1409 15:08:53.266609 # ok 242 /ocp/target-module@49a00000/dma@0
1410 15:08:53.288973 # ok 243 /ocp/target-module@4c000000
1411 15:08:53.359915 # not ok 244 /ocp/target-module@4c000000/emif@0
1412 15:08:53.384995 # ok 245 /ocp/target-module@50000000
1413 15:08:53.406614 # ok 246 /ocp/target-module@53100000
1414 15:08:53.473624 # not ok 247 /ocp/target-module@53100000/sham@0
1415 15:08:53.498559 # ok 248 /ocp/target-module@53500000
1416 15:08:53.565809 # not ok 249 /ocp/target-module@53500000/aes@0
1417 15:08:53.589014 # ok 250 /ocp/target-module@56000000
1418 15:08:53.694833 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1419 15:08:53.762623 # ok 252 /opp-table # SKIP
1420 15:08:53.827937 # ok 253 /soc # SKIP
1421 15:08:53.852361 # ok 254 /sound
1422 15:08:53.875847 # ok 255 /target-module@4b000000
1423 15:08:53.900281 # ok 256 /target-module@4b000000/target-module@140000
1424 15:08:53.916705 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1425 15:08:53.925212 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1426 15:08:53.932556 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1427 15:08:56.248301 dt_test_unprobed_devices_sh_ skip
1428 15:08:56.254196 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1429 15:08:56.259402 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1430 15:08:56.259754 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1431 15:08:56.265059 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1432 15:08:56.270608 dt_test_unprobed_devices_sh_fixedregulator0 pass
1433 15:08:56.276258 dt_test_unprobed_devices_sh_leds pass
1434 15:08:56.276801 dt_test_unprobed_devices_sh_ocp pass
1435 15:08:56.281833 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1436 15:08:56.287481 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1437 15:08:56.293061 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1438 15:08:56.304170 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1439 15:08:56.309876 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1440 15:08:56.315530 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1441 15:08:56.326642 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1442 15:08:56.332242 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1443 15:08:56.343589 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1444 15:08:56.354964 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1445 15:08:56.366030 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1446 15:08:56.371768 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1447 15:08:56.382883 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1448 15:08:56.394077 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1449 15:08:56.405328 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1450 15:08:56.416474 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1451 15:08:56.422456 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1452 15:08:56.433270 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1453 15:08:56.444603 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1454 15:08:56.455720 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1455 15:08:56.466911 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1456 15:08:56.472483 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1457 15:08:56.483694 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1458 15:08:56.494786 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1459 15:08:56.506002 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1460 15:08:56.511684 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1461 15:08:56.522948 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1462 15:08:56.533999 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1463 15:08:56.545215 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1464 15:08:56.556427 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1465 15:08:56.562275 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1466 15:08:56.573811 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1467 15:08:56.584426 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1468 15:08:56.595724 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1469 15:08:56.606812 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1470 15:08:56.618179 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1471 15:08:56.629273 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1472 15:08:56.640493 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1473 15:08:56.651666 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1474 15:08:56.662832 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1475 15:08:56.674042 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1476 15:08:56.685210 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1477 15:08:56.696393 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1478 15:08:56.707656 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1479 15:08:56.719314 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1480 15:08:56.730018 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1481 15:08:56.741156 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1482 15:08:56.752352 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1483 15:08:56.763416 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1484 15:08:56.774715 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1485 15:08:56.785900 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1486 15:08:56.797053 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1487 15:08:56.808484 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1488 15:08:56.819650 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1489 15:08:56.830872 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1490 15:08:56.842079 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1491 15:08:56.847809 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1492 15:08:56.858944 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1493 15:08:56.870033 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1494 15:08:56.881247 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1495 15:08:56.892405 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1496 15:08:56.903724 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1497 15:08:56.914854 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1498 15:08:56.926023 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1499 15:08:56.937218 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1500 15:08:56.948550 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1501 15:08:56.959589 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1502 15:08:56.970827 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1503 15:08:56.981954 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1504 15:08:56.993190 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1505 15:08:57.004427 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1506 15:08:57.015590 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1507 15:08:57.026865 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1508 15:08:57.037960 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1509 15:08:57.043595 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1510 15:08:57.054856 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1511 15:08:57.065935 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1512 15:08:57.077134 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1513 15:08:57.088339 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1514 15:08:57.093939 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1515 15:08:57.110744 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1516 15:08:57.121890 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1517 15:08:57.127501 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1518 15:08:57.144267 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1519 15:08:57.155452 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1520 15:08:57.166630 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1521 15:08:57.172296 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1522 15:08:57.183472 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1523 15:08:57.194736 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1524 15:08:57.200292 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1525 15:08:57.211437 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1526 15:08:57.222667 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1527 15:08:57.228314 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1528 15:08:57.239412 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1529 15:08:57.245026 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1530 15:08:57.256228 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1531 15:08:57.267378 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1532 15:08:57.278577 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1533 15:08:57.289865 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1534 15:08:57.300960 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1535 15:08:57.312135 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1536 15:08:57.323342 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1537 15:08:57.334537 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1538 15:08:57.345769 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1539 15:08:57.356948 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1540 15:08:57.368149 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1541 15:08:57.379213 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1542 15:08:57.396232 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1543 15:08:57.407241 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1544 15:08:57.418473 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1545 15:08:57.429654 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1546 15:08:57.440912 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1547 15:08:57.457641 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1548 15:08:57.468879 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1549 15:08:57.480070 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1550 15:08:57.491212 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1551 15:08:57.496895 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1552 15:08:57.507908 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1553 15:08:57.519227 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1554 15:08:57.524812 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1555 15:08:57.536030 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1556 15:08:57.541649 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1557 15:08:57.552895 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1558 15:08:57.558463 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1559 15:08:57.569571 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1560 15:08:57.575207 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1561 15:08:57.586335 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1562 15:08:57.592065 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1563 15:08:57.603137 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1564 15:08:57.614368 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1565 15:08:57.625458 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1566 15:08:57.636902 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1567 15:08:57.647960 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1568 15:08:57.653566 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1569 15:08:57.664882 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1570 15:08:57.670353 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1571 15:08:57.676036 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1572 15:08:57.681613 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1573 15:08:57.687160 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1574 15:08:57.693062 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1575 15:08:57.703889 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1576 15:08:57.709517 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1577 15:08:57.714977 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1578 15:08:57.726255 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1579 15:08:57.731952 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1580 15:08:57.743115 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1581 15:08:57.748745 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1582 15:08:57.760029 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1583 15:08:57.765457 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1584 15:08:57.776723 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1585 15:08:57.782344 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1586 15:08:57.793449 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1587 15:08:57.799127 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1588 15:08:57.810318 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1589 15:08:57.815929 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1590 15:08:57.827014 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1591 15:08:57.832560 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1592 15:08:57.838264 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1593 15:08:57.849356 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1594 15:08:57.854976 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1595 15:08:57.866211 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1596 15:08:57.871802 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1597 15:08:57.882908 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1598 15:08:57.888538 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1599 15:08:57.899765 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1600 15:08:57.905397 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1601 15:08:57.910993 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1602 15:08:57.922173 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1603 15:08:57.927783 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1604 15:08:57.938951 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1605 15:08:57.950132 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1606 15:08:57.961280 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1607 15:08:57.972412 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1608 15:08:57.983675 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1609 15:08:57.994989 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1610 15:08:58.006054 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1611 15:08:58.017476 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1612 15:08:58.023098 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1613 15:08:58.034138 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1614 15:08:58.039738 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1615 15:08:58.051010 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1616 15:08:58.056524 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1617 15:08:58.067695 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1618 15:08:58.073265 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1619 15:08:58.084525 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1620 15:08:58.090395 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1621 15:08:58.101682 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1622 15:08:58.106807 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1623 15:08:58.117977 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1624 15:08:58.123716 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1625 15:08:58.134860 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1626 15:08:58.140464 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1627 15:08:58.145930 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1628 15:08:58.157142 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1629 15:08:58.162679 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1630 15:08:58.173915 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1631 15:08:58.179531 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1632 15:08:58.190723 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1633 15:08:58.196285 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1634 15:08:58.207492 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1635 15:08:58.213112 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1636 15:08:58.218758 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1637 15:08:58.224255 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1638 15:08:58.235401 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1639 15:08:58.246674 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1640 15:08:58.252338 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1641 15:08:58.258397 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1642 15:08:58.268978 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1643 15:08:58.280314 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1644 15:08:58.291386 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1645 15:08:58.302650 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1646 15:08:58.308242 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1647 15:08:58.313829 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1648 15:08:58.319528 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1649 15:08:58.325062 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1650 15:08:58.330630 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1651 15:08:58.336249 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1652 15:08:58.347456 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1653 15:08:58.353180 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1654 15:08:58.358687 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1655 15:08:58.364328 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1656 15:08:58.369981 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1657 15:08:58.381196 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1658 15:08:58.386701 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1659 15:08:58.392362 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1660 15:08:58.397848 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1661 15:08:58.403488 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1662 15:08:58.409113 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1663 15:08:58.414801 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1664 15:08:58.420333 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1665 15:08:58.426067 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1666 15:08:58.431529 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1667 15:08:58.437126 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1668 15:08:58.442646 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1669 15:08:58.448274 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1670 15:08:58.453934 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1671 15:08:58.459497 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1672 15:08:58.465043 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1673 15:08:58.470639 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1674 15:08:58.476284 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1675 15:08:58.481948 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1676 15:08:58.487483 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1677 15:08:58.493038 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1678 15:08:58.493580 dt_test_unprobed_devices_sh_opp-table skip
1679 15:08:58.498656 dt_test_unprobed_devices_sh_soc skip
1680 15:08:58.504248 dt_test_unprobed_devices_sh_sound pass
1681 15:08:58.509935 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1682 15:08:58.515464 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1683 15:08:58.521069 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1684 15:08:58.526662 dt_test_unprobed_devices_sh fail
1685 15:08:58.527183 + ../../utils/send-to-lava.sh ./output/result.txt
1686 15:08:58.532284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1687 15:08:58.533393 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1689 15:08:58.540435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1690 15:08:58.541310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1692 15:08:58.614571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1693 15:08:58.615519 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1695 15:08:58.704204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1696 15:08:58.705124 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1698 15:08:58.788188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1699 15:08:58.789020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1701 15:08:58.874610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1702 15:08:58.875399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1704 15:08:58.964201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1705 15:08:58.965143 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1707 15:08:59.056610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1708 15:08:59.057560 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1710 15:08:59.145846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1711 15:08:59.146777 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1713 15:08:59.240856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1714 15:08:59.241907 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1716 15:08:59.327137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1717 15:08:59.327800 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1719 15:08:59.419792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1720 15:08:59.420749 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1722 15:08:59.510840 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1723 15:08:59.511810 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1725 15:08:59.596669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1726 15:08:59.597640 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1728 15:08:59.687877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1729 15:08:59.688816 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1731 15:08:59.780968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1732 15:08:59.781806 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1734 15:08:59.866331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1735 15:08:59.867153 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1737 15:08:59.957449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1738 15:08:59.958377 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1740 15:09:00.052089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1741 15:09:00.053112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1743 15:09:00.141956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1744 15:09:00.142875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1746 15:09:00.227457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1747 15:09:00.228157 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1749 15:09:00.313277 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1750 15:09:00.313984 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1752 15:09:00.406077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1753 15:09:00.406785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1755 15:09:00.499976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1756 15:09:00.500690 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1758 15:09:00.589902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1759 15:09:00.590596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1761 15:09:00.683099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1762 15:09:00.683826 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1764 15:09:00.770015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1765 15:09:00.771549 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1767 15:09:00.853728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1768 15:09:00.854683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1770 15:09:00.938758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1771 15:09:00.939700 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1773 15:09:01.027393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1774 15:09:01.028133 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1776 15:09:01.126291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1777 15:09:01.127334 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1779 15:09:01.230228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1780 15:09:01.230935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1782 15:09:01.321903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1783 15:09:01.324037 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1785 15:09:01.417443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1786 15:09:01.418117 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1788 15:09:01.515564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1789 15:09:01.516501 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1791 15:09:01.604991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1792 15:09:01.605991 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1794 15:09:01.697817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1795 15:09:01.698621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1797 15:09:01.798091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1798 15:09:01.798829 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1800 15:09:01.897413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1801 15:09:01.898218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1803 15:09:02.262071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1804 15:09:02.262717 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1806 15:09:02.365665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1807 15:09:02.366302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1809 15:09:02.459062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1810 15:09:02.459951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1812 15:09:02.550839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1813 15:09:02.551710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1815 15:09:02.641523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1816 15:09:02.642354 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1818 15:09:02.733324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1819 15:09:02.734209 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1821 15:09:02.821433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1822 15:09:02.822306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1824 15:09:02.913299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1825 15:09:02.914169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1827 15:09:03.003742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1828 15:09:03.004655 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1830 15:09:03.087907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1831 15:09:03.088825 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1833 15:09:03.180301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1834 15:09:03.181148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1836 15:09:03.269946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1837 15:09:03.270795 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1839 15:09:03.360976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1840 15:09:03.361807 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1842 15:09:03.453002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1843 15:09:03.453957 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1845 15:09:03.543278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1846 15:09:03.543967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1848 15:09:03.627659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1849 15:09:03.628306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1851 15:09:03.717045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1852 15:09:03.717889 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1854 15:09:03.801895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1855 15:09:03.802751 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1857 15:09:03.891730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1858 15:09:03.892719 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1860 15:09:03.976146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1861 15:09:03.977015 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1863 15:09:04.069013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1864 15:09:04.070000 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1866 15:09:04.160996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1867 15:09:04.161871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1869 15:09:04.253823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1870 15:09:04.254746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1872 15:09:04.339838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1873 15:09:04.340772 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1875 15:09:04.455138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1876 15:09:04.456082 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1878 15:09:04.548303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1879 15:09:04.549111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1881 15:09:04.637159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1882 15:09:04.637838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1884 15:09:04.732637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1885 15:09:04.733528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1887 15:09:04.824592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1888 15:09:04.825246 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1890 15:09:04.915102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1891 15:09:04.915723 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1893 15:09:05.000682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1894 15:09:05.001740 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1896 15:09:05.091851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1897 15:09:05.092757 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1899 15:09:05.177496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1900 15:09:05.178390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1902 15:09:05.269230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1903 15:09:05.269913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1905 15:09:05.360736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1906 15:09:05.361374 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1908 15:09:05.451609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1909 15:09:05.452269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1911 15:09:05.545301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1912 15:09:05.546239 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1914 15:09:05.637307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1915 15:09:05.638183 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1917 15:09:05.727116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1918 15:09:05.728018 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1920 15:09:05.818625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1921 15:09:05.819506 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1923 15:09:05.912152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1924 15:09:05.912822 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1926 15:09:06.002313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1927 15:09:06.003302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1929 15:09:06.088217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1930 15:09:06.089063 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1932 15:09:06.178479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1933 15:09:06.179232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1935 15:09:06.269659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1936 15:09:06.270779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1938 15:09:06.361881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1939 15:09:06.362930 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1941 15:09:06.451395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1942 15:09:06.452541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1944 15:09:06.536476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1945 15:09:06.537504 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1947 15:09:06.629180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1948 15:09:06.629905 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1950 15:09:06.722890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1951 15:09:06.723548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1953 15:09:06.812823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1954 15:09:06.813653 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1956 15:09:06.897938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1957 15:09:06.898608 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1959 15:09:06.986265 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1960 15:09:06.986905 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1962 15:09:07.073300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1963 15:09:07.074012 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1965 15:09:07.163688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1966 15:09:07.164378 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1968 15:09:07.251644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1969 15:09:07.252280 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1971 15:09:07.338750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1972 15:09:07.339367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1974 15:09:07.430781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1975 15:09:07.431393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1977 15:09:07.520491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1978 15:09:07.521131 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1980 15:09:07.604312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1981 15:09:07.604941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1983 15:09:07.694771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1984 15:09:07.695456 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1986 15:09:07.779208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1987 15:09:07.779809 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1989 15:09:07.869338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1990 15:09:07.869941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1992 15:09:07.952887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1993 15:09:07.953485 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1995 15:09:08.043949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1996 15:09:08.044668 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1998 15:09:08.130071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1999 15:09:08.130692 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
2001 15:09:08.221591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
2002 15:09:08.222274 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
2004 15:09:08.312780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
2005 15:09:08.313392 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
2007 15:09:08.403561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
2008 15:09:08.404512 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
2010 15:09:08.490702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
2011 15:09:08.491612 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
2013 15:09:08.575100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
2014 15:09:08.576054 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
2016 15:09:08.665552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
2017 15:09:08.666464 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
2019 15:09:08.753714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
2020 15:09:08.754603 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
2022 15:09:08.838984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
2023 15:09:08.839852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
2025 15:09:08.926631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
2026 15:09:08.927500 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
2028 15:09:09.023269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
2029 15:09:09.024031 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
2031 15:09:09.111939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
2032 15:09:09.113382 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
2034 15:09:09.196065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
2035 15:09:09.196963 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
2037 15:09:09.278589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
2038 15:09:09.283970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
2040 15:09:09.362976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
2041 15:09:09.364871 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
2043 15:09:09.453085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
2044 15:09:09.454399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
2046 15:09:09.541745 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
2048 15:09:09.543410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
2049 15:09:09.629627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
2051 15:09:09.631597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
2052 15:09:09.715689 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
2054 15:09:09.718029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
2055 15:09:09.802842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
2056 15:09:09.803658 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
2058 15:09:09.893049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
2059 15:09:09.893718 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
2061 15:09:09.975234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
2062 15:09:09.975954 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
2064 15:09:10.067068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
2065 15:09:10.068088 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
2067 15:09:10.156484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
2068 15:09:10.157146 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
2070 15:09:10.242647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
2071 15:09:10.243298 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
2073 15:09:10.331868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
2074 15:09:10.333152 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
2076 15:09:10.417028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
2077 15:09:10.417723 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
2079 15:09:10.510323 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
2080 15:09:10.511252 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
2082 15:09:10.601248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
2083 15:09:10.602162 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
2085 15:09:10.687215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
2086 15:09:10.688106 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
2088 15:09:10.781259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
2089 15:09:10.782166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
2091 15:09:10.870535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
2092 15:09:10.871370 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
2094 15:09:10.955864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
2095 15:09:10.956829 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
2097 15:09:11.049364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
2098 15:09:11.050261 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
2100 15:09:11.140614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
2101 15:09:11.141521 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2103 15:09:11.229389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2104 15:09:11.230287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2106 15:09:11.315264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2107 15:09:11.316637 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2109 15:09:11.402522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2110 15:09:11.403251 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2112 15:09:11.493876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2113 15:09:11.494762 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2115 15:09:11.577930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2116 15:09:11.578916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2118 15:09:11.664960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2119 15:09:11.665838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2121 15:09:11.758076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2122 15:09:11.759224 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2124 15:09:11.843216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2125 15:09:11.844156 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2127 15:09:11.934782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2128 15:09:11.935732 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2130 15:09:12.021810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2131 15:09:12.022801 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2133 15:09:12.107194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2134 15:09:12.107855 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2136 15:09:12.193133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2137 15:09:12.194022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2139 15:09:12.279413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2140 15:09:12.280465 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2142 15:09:12.371463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2143 15:09:12.372108 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2145 15:09:12.457360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2146 15:09:12.458001 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2148 15:09:12.548581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2149 15:09:12.549218 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2151 15:09:12.633923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2152 15:09:12.634826 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2154 15:09:12.720714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2155 15:09:12.721372 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2157 15:09:12.810447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2158 15:09:12.811101 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2160 15:09:12.896546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2161 15:09:12.897197 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2163 15:09:12.986153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2164 15:09:12.987030 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2166 15:09:13.072148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2167 15:09:13.073035 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2169 15:09:13.161550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2170 15:09:13.162180 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2172 15:09:13.251745 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2173 15:09:13.252419 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2175 15:09:13.334955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2176 15:09:13.335613 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2178 15:09:13.420762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2179 15:09:13.421421 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2181 15:09:13.510138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2182 15:09:13.510771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2184 15:09:13.595117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2185 15:09:13.595737 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2187 15:09:13.686484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2188 15:09:13.687167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2190 15:09:13.779335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2191 15:09:13.780151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2193 15:09:13.869999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2194 15:09:13.870887 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2196 15:09:13.957374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2197 15:09:13.958282 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2199 15:09:14.049299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2200 15:09:14.050203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2202 15:09:14.138509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2203 15:09:14.139425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2205 15:09:14.229501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2206 15:09:14.230386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2208 15:09:14.321252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2209 15:09:14.322142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2211 15:09:14.404206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2212 15:09:14.405230 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2214 15:09:14.501498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2215 15:09:14.502873 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2217 15:09:14.603545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2218 15:09:14.604689 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2220 15:09:14.694878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2221 15:09:14.695854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2223 15:09:14.786347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2224 15:09:14.787277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2226 15:09:14.872472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2227 15:09:14.873400 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2229 15:09:14.963856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2230 15:09:14.965087 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2232 15:09:15.050563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2233 15:09:15.051497 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2235 15:09:15.140264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2236 15:09:15.140944 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2238 15:09:15.230009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2239 15:09:15.230647 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2241 15:09:15.320954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2242 15:09:15.321877 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2244 15:09:15.401723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2245 15:09:15.402391 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2247 15:09:15.488673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2248 15:09:15.489328 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2250 15:09:15.581018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2251 15:09:15.581670 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2253 15:09:15.668380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2254 15:09:15.669066 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2256 15:09:15.759346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2257 15:09:15.760072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2259 15:09:15.849841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2260 15:09:15.850570 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2262 15:09:15.933620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2263 15:09:15.934264 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2265 15:09:16.026943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2266 15:09:16.027655 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2268 15:09:16.110523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2269 15:09:16.111212 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2271 15:09:16.200712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2272 15:09:16.201342 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2274 15:09:16.284651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2275 15:09:16.285294 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2277 15:09:16.374671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2278 15:09:16.375646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2280 15:09:16.458290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2281 15:09:16.459236 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2283 15:09:16.545261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2284 15:09:16.546206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2286 15:09:16.634861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2287 15:09:16.635473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2289 15:09:16.719226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2290 15:09:16.720172 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2292 15:09:16.811508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2293 15:09:16.812507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2295 15:09:16.898126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2296 15:09:16.899074 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2298 15:09:16.989458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2299 15:09:16.990367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2301 15:09:17.082816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2302 15:09:17.083737 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2304 15:09:17.167678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2305 15:09:17.168328 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2307 15:09:17.258748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2308 15:09:17.259379 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2310 15:09:17.344774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2311 15:09:17.345417 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2313 15:09:17.431696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2314 15:09:17.432579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2316 15:09:17.517766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2317 15:09:17.518506 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2319 15:09:17.603592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2320 15:09:17.604248 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2322 15:09:17.689752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2323 15:09:17.690385 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2325 15:09:17.779584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2326 15:09:17.780730 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2328 15:09:17.861144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2329 15:09:17.862043 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2331 15:09:17.945703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2332 15:09:17.946580 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2334 15:09:18.036588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2335 15:09:18.037396 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2337 15:09:18.123638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2338 15:09:18.124305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2340 15:09:18.208978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2341 15:09:18.209603 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2343 15:09:18.295379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2344 15:09:18.296033 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2346 15:09:18.386907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2347 15:09:18.387543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2349 15:09:18.475000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2350 15:09:18.475660 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2352 15:09:18.567397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2353 15:09:18.568392 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2355 15:09:18.657242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2356 15:09:18.658199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2358 15:09:18.741427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2359 15:09:18.742450 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2361 15:09:18.833098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2362 15:09:18.834015 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2364 15:09:18.932449 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2365 15:09:18.933108 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2367 15:09:19.014390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2369 15:09:19.017481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2370 15:09:19.105223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2371 15:09:19.105979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2373 15:09:19.191466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2374 15:09:19.192102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2376 15:09:19.275313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2377 15:09:19.275947 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2379 15:09:19.365843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2380 15:09:19.366464 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2382 15:09:19.450005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2383 15:09:19.450671 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2385 15:09:19.540158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2386 15:09:19.540793 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2388 15:09:19.629847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2389 15:09:19.630728 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2391 15:09:19.712594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2392 15:09:19.713409 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2394 15:09:19.797518 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2395 15:09:19.798362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2397 15:09:19.880287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2398 15:09:19.881129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2400 15:09:19.964671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2401 15:09:19.965525 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2403 15:09:20.049833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2404 15:09:20.050672 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2406 15:09:20.141150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2407 15:09:20.141977 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2409 15:09:20.231152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2410 15:09:20.232048 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2412 15:09:20.317496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2413 15:09:20.318328 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2415 15:09:20.407004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2416 15:09:20.407885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2418 15:09:20.502579 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2419 15:09:20.503456 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2421 15:09:20.587933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2422 15:09:20.588832 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2424 15:09:20.677537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2425 15:09:20.678368 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2427 15:09:20.762128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2428 15:09:20.762948 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2430 15:09:20.851892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2431 15:09:20.852785 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2433 15:09:20.937433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2434 15:09:20.938319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2436 15:09:21.026690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2437 15:09:21.027586 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2439 15:09:21.111649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2440 15:09:21.112564 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2442 15:09:21.198964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2443 15:09:21.199857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2445 15:09:21.284033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2446 15:09:21.284970 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2448 15:09:21.375951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2449 15:09:21.376854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2451 15:09:21.467182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2452 15:09:21.468077 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2454 15:09:21.552411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2455 15:09:21.553273 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2457 15:09:21.636482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2458 15:09:21.637353 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2460 15:09:21.717239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2461 15:09:21.717846 + set +x
2462 15:09:21.718511 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2464 15:09:21.723185 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 959812_1.6.2.4.5>
2465 15:09:21.723673 <LAVA_TEST_RUNNER EXIT>
2466 15:09:21.724356 Received signal: <ENDRUN> 1_kselftest-dt 959812_1.6.2.4.5
2467 15:09:21.724798 Ending use of test pattern.
2468 15:09:21.725203 Ending test lava.1_kselftest-dt (959812_1.6.2.4.5), duration 82.56
2470 15:09:21.726673 ok: lava_test_shell seems to have completed
2471 15:09:21.739497 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2472 15:09:21.741430 end: 3.1 lava-test-shell (duration 00:01:24) [common]
2473 15:09:21.741962 end: 3 lava-test-retry (duration 00:01:24) [common]
2474 15:09:21.742506 start: 4 finalize (timeout 00:05:29) [common]
2475 15:09:21.743042 start: 4.1 power-off (timeout 00:00:30) [common]
2476 15:09:21.744033 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-01'
2477 15:09:21.779101 >> OK - accepted request
2478 15:09:21.781250 Returned 0 in 0 seconds
2479 15:09:21.882119 end: 4.1 power-off (duration 00:00:00) [common]
2481 15:09:21.883134 start: 4.2 read-feedback (timeout 00:05:29) [common]
2482 15:09:21.883798 Listened to connection for namespace 'common' for up to 1s
2483 15:09:21.884468 Listened to connection for namespace 'common' for up to 1s
2484 15:09:22.883883 Finalising connection for namespace 'common'
2485 15:09:22.884403 Disconnecting from shell: Finalise
2486 15:09:22.884690 / #
2487 15:09:22.985381 end: 4.2 read-feedback (duration 00:00:01) [common]
2488 15:09:22.985887 end: 4 finalize (duration 00:00:01) [common]
2489 15:09:22.986258 Cleaning after the job
2490 15:09:22.986644 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/959812/tftp-deploy-tac2bht3/ramdisk
2491 15:09:22.988196 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/959812/tftp-deploy-tac2bht3/kernel
2492 15:09:22.989348 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/959812/tftp-deploy-tac2bht3/dtb
2493 15:09:22.990085 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/959812/tftp-deploy-tac2bht3/nfsrootfs
2494 15:09:23.008911 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/959812/tftp-deploy-tac2bht3/modules
2495 15:09:23.013006 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/959812
2496 15:09:26.198107 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/959812
2497 15:09:26.198707 Job finished correctly