Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 10:01:30.733611 lava-dispatcher, installed at version: 2024.01
2 10:01:30.734385 start: 0 validate
3 10:01:30.734857 Start time: 2024-11-02 10:01:30.734827+00:00 (UTC)
4 10:01:30.735391 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 10:01:30.735922 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 10:01:30.770988 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 10:01:30.771509 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc5-608-g0c049b492970f%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 10:01:30.794713 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 10:01:30.795293 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc5-608-g0c049b492970f%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 10:01:30.817197 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 10:01:30.817940 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 10:01:30.840349 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 10:01:30.840800 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc5-608-g0c049b492970f%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 10:01:30.871630 validate duration: 0.14
16 10:01:30.872506 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 10:01:30.872823 start: 1.1 download-retry (timeout 00:10:00) [common]
18 10:01:30.873108 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 10:01:30.873682 Not decompressing ramdisk as can be used compressed.
20 10:01:30.874116 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 10:01:30.874385 saving as /var/lib/lava/dispatcher/tmp/927468/tftp-deploy-ucj6ozrr/ramdisk/initrd.cpio.gz
22 10:01:30.874647 total size: 4775763 (4 MB)
23 10:01:30.903156 progress 0 % (0 MB)
24 10:01:30.906696 progress 5 % (0 MB)
25 10:01:30.909728 progress 10 % (0 MB)
26 10:01:30.912719 progress 15 % (0 MB)
27 10:01:30.916126 progress 20 % (0 MB)
28 10:01:30.919081 progress 25 % (1 MB)
29 10:01:30.921997 progress 30 % (1 MB)
30 10:01:30.925225 progress 35 % (1 MB)
31 10:01:30.928192 progress 40 % (1 MB)
32 10:01:30.931183 progress 45 % (2 MB)
33 10:01:30.934052 progress 50 % (2 MB)
34 10:01:30.937190 progress 55 % (2 MB)
35 10:01:30.940004 progress 60 % (2 MB)
36 10:01:30.942764 progress 65 % (2 MB)
37 10:01:30.945860 progress 70 % (3 MB)
38 10:01:30.948657 progress 75 % (3 MB)
39 10:01:30.951422 progress 80 % (3 MB)
40 10:01:30.954255 progress 85 % (3 MB)
41 10:01:30.957340 progress 90 % (4 MB)
42 10:01:30.960098 progress 95 % (4 MB)
43 10:01:30.962930 progress 100 % (4 MB)
44 10:01:30.963534 4 MB downloaded in 0.09 s (51.25 MB/s)
45 10:01:30.964077 end: 1.1.1 http-download (duration 00:00:00) [common]
47 10:01:30.964936 end: 1.1 download-retry (duration 00:00:00) [common]
48 10:01:30.965236 start: 1.2 download-retry (timeout 00:10:00) [common]
49 10:01:30.965515 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 10:01:30.966005 downloading http://storage.kernelci.org/tip/master/v6.12-rc5-608-g0c049b492970f/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 10:01:30.966259 saving as /var/lib/lava/dispatcher/tmp/927468/tftp-deploy-ucj6ozrr/kernel/zImage
52 10:01:30.966495 total size: 11457024 (10 MB)
53 10:01:30.966713 No compression specified
54 10:01:30.999190 progress 0 % (0 MB)
55 10:01:31.005947 progress 5 % (0 MB)
56 10:01:31.012604 progress 10 % (1 MB)
57 10:01:31.019508 progress 15 % (1 MB)
58 10:01:31.026072 progress 20 % (2 MB)
59 10:01:31.032922 progress 25 % (2 MB)
60 10:01:31.039602 progress 30 % (3 MB)
61 10:01:31.046845 progress 35 % (3 MB)
62 10:01:31.053420 progress 40 % (4 MB)
63 10:01:31.060315 progress 45 % (4 MB)
64 10:01:31.066868 progress 50 % (5 MB)
65 10:01:31.073783 progress 55 % (6 MB)
66 10:01:31.080394 progress 60 % (6 MB)
67 10:01:31.087319 progress 65 % (7 MB)
68 10:01:31.093892 progress 70 % (7 MB)
69 10:01:31.100796 progress 75 % (8 MB)
70 10:01:31.107324 progress 80 % (8 MB)
71 10:01:31.114011 progress 85 % (9 MB)
72 10:01:31.120247 progress 90 % (9 MB)
73 10:01:31.126828 progress 95 % (10 MB)
74 10:01:31.133084 progress 100 % (10 MB)
75 10:01:31.133712 10 MB downloaded in 0.17 s (65.35 MB/s)
76 10:01:31.134250 end: 1.2.1 http-download (duration 00:00:00) [common]
78 10:01:31.135113 end: 1.2 download-retry (duration 00:00:00) [common]
79 10:01:31.135419 start: 1.3 download-retry (timeout 00:10:00) [common]
80 10:01:31.135702 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 10:01:31.136192 downloading http://storage.kernelci.org/tip/master/v6.12-rc5-608-g0c049b492970f/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 10:01:31.136488 saving as /var/lib/lava/dispatcher/tmp/927468/tftp-deploy-ucj6ozrr/dtb/am335x-boneblack.dtb
83 10:01:31.136709 total size: 70568 (0 MB)
84 10:01:31.136931 No compression specified
85 10:01:31.170948 progress 46 % (0 MB)
86 10:01:31.171767 progress 92 % (0 MB)
87 10:01:31.172510 progress 100 % (0 MB)
88 10:01:31.172925 0 MB downloaded in 0.04 s (1.86 MB/s)
89 10:01:31.173404 end: 1.3.1 http-download (duration 00:00:00) [common]
91 10:01:31.174295 end: 1.3 download-retry (duration 00:00:00) [common]
92 10:01:31.174590 start: 1.4 download-retry (timeout 00:10:00) [common]
93 10:01:31.174874 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 10:01:31.175361 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 10:01:31.175643 saving as /var/lib/lava/dispatcher/tmp/927468/tftp-deploy-ucj6ozrr/nfsrootfs/full.rootfs.tar
96 10:01:31.175875 total size: 117747780 (112 MB)
97 10:01:31.176106 Using unxz to decompress xz
98 10:01:31.209120 progress 0 % (0 MB)
99 10:01:31.923276 progress 5 % (5 MB)
100 10:01:32.656604 progress 10 % (11 MB)
101 10:01:33.416511 progress 15 % (16 MB)
102 10:01:34.124259 progress 20 % (22 MB)
103 10:01:34.696407 progress 25 % (28 MB)
104 10:01:35.501053 progress 30 % (33 MB)
105 10:01:36.294185 progress 35 % (39 MB)
106 10:01:36.642640 progress 40 % (44 MB)
107 10:01:36.994113 progress 45 % (50 MB)
108 10:01:37.645547 progress 50 % (56 MB)
109 10:01:38.445381 progress 55 % (61 MB)
110 10:01:39.162832 progress 60 % (67 MB)
111 10:01:39.871263 progress 65 % (73 MB)
112 10:01:40.631352 progress 70 % (78 MB)
113 10:01:41.374029 progress 75 % (84 MB)
114 10:01:42.093757 progress 80 % (89 MB)
115 10:01:42.793618 progress 85 % (95 MB)
116 10:01:43.564861 progress 90 % (101 MB)
117 10:01:44.304663 progress 95 % (106 MB)
118 10:01:45.103381 progress 100 % (112 MB)
119 10:01:45.115547 112 MB downloaded in 13.94 s (8.06 MB/s)
120 10:01:45.116093 end: 1.4.1 http-download (duration 00:00:14) [common]
122 10:01:45.116918 end: 1.4 download-retry (duration 00:00:14) [common]
123 10:01:45.117181 start: 1.5 download-retry (timeout 00:09:46) [common]
124 10:01:45.117440 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 10:01:45.118092 downloading http://storage.kernelci.org/tip/master/v6.12-rc5-608-g0c049b492970f/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 10:01:45.118568 saving as /var/lib/lava/dispatcher/tmp/927468/tftp-deploy-ucj6ozrr/modules/modules.tar
127 10:01:45.118969 total size: 6604052 (6 MB)
128 10:01:45.119376 Using unxz to decompress xz
129 10:01:45.152106 progress 0 % (0 MB)
130 10:01:45.188689 progress 5 % (0 MB)
131 10:01:45.230752 progress 10 % (0 MB)
132 10:01:45.273418 progress 15 % (0 MB)
133 10:01:45.316987 progress 20 % (1 MB)
134 10:01:45.359444 progress 25 % (1 MB)
135 10:01:45.400978 progress 30 % (1 MB)
136 10:01:45.443792 progress 35 % (2 MB)
137 10:01:45.487011 progress 40 % (2 MB)
138 10:01:45.529858 progress 45 % (2 MB)
139 10:01:45.572016 progress 50 % (3 MB)
140 10:01:45.614011 progress 55 % (3 MB)
141 10:01:45.656150 progress 60 % (3 MB)
142 10:01:45.701658 progress 65 % (4 MB)
143 10:01:45.744253 progress 70 % (4 MB)
144 10:01:45.788475 progress 75 % (4 MB)
145 10:01:45.833902 progress 80 % (5 MB)
146 10:01:45.876848 progress 85 % (5 MB)
147 10:01:45.920212 progress 90 % (5 MB)
148 10:01:45.966230 progress 95 % (6 MB)
149 10:01:46.008584 progress 100 % (6 MB)
150 10:01:46.020977 6 MB downloaded in 0.90 s (6.98 MB/s)
151 10:01:46.021556 end: 1.5.1 http-download (duration 00:00:01) [common]
153 10:01:46.023042 end: 1.5 download-retry (duration 00:00:01) [common]
154 10:01:46.023563 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 10:01:46.024074 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 10:02:02.120879 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/927468/extract-nfsrootfs-ih3gcxnl
157 10:02:02.121484 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 10:02:02.121765 start: 1.6.2 lava-overlay (timeout 00:09:29) [common]
159 10:02:02.122437 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3
160 10:02:02.122862 makedir: /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin
161 10:02:02.123181 makedir: /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/tests
162 10:02:02.123482 makedir: /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/results
163 10:02:02.123813 Creating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-add-keys
164 10:02:02.124334 Creating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-add-sources
165 10:02:02.124831 Creating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-background-process-start
166 10:02:02.125353 Creating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-background-process-stop
167 10:02:02.125909 Creating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-common-functions
168 10:02:02.126416 Creating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-echo-ipv4
169 10:02:02.126924 Creating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-install-packages
170 10:02:02.127505 Creating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-installed-packages
171 10:02:02.127994 Creating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-os-build
172 10:02:02.128461 Creating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-probe-channel
173 10:02:02.128929 Creating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-probe-ip
174 10:02:02.129395 Creating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-target-ip
175 10:02:02.129888 Creating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-target-mac
176 10:02:02.130380 Creating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-target-storage
177 10:02:02.130876 Creating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-test-case
178 10:02:02.131371 Creating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-test-event
179 10:02:02.131836 Creating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-test-feedback
180 10:02:02.132302 Creating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-test-raise
181 10:02:02.132768 Creating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-test-reference
182 10:02:02.133234 Creating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-test-runner
183 10:02:02.133708 Creating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-test-set
184 10:02:02.134235 Creating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-test-shell
185 10:02:02.134741 Updating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-add-keys (debian)
186 10:02:02.135262 Updating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-add-sources (debian)
187 10:02:02.135757 Updating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-install-packages (debian)
188 10:02:02.136259 Updating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-installed-packages (debian)
189 10:02:02.136742 Updating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/bin/lava-os-build (debian)
190 10:02:02.137167 Creating /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/environment
191 10:02:02.137526 LAVA metadata
192 10:02:02.137777 - LAVA_JOB_ID=927468
193 10:02:02.138029 - LAVA_DISPATCHER_IP=192.168.6.3
194 10:02:02.138388 start: 1.6.2.1 ssh-authorize (timeout 00:09:29) [common]
195 10:02:02.139297 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 10:02:02.139600 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:29) [common]
197 10:02:02.139804 skipped lava-vland-overlay
198 10:02:02.140041 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 10:02:02.140293 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:29) [common]
200 10:02:02.140509 skipped lava-multinode-overlay
201 10:02:02.140753 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 10:02:02.141001 start: 1.6.2.4 test-definition (timeout 00:09:29) [common]
203 10:02:02.141242 Loading test definitions
204 10:02:02.141511 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:29) [common]
205 10:02:02.141746 Using /lava-927468 at stage 0
206 10:02:02.142850 uuid=927468_1.6.2.4.1 testdef=None
207 10:02:02.143143 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 10:02:02.143400 start: 1.6.2.4.2 test-overlay (timeout 00:09:29) [common]
209 10:02:02.144983 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 10:02:02.145764 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:29) [common]
212 10:02:02.147741 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 10:02:02.148550 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:29) [common]
215 10:02:02.150361 runner path: /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/0/tests/0_timesync-off test_uuid 927468_1.6.2.4.1
216 10:02:02.150907 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 10:02:02.151710 start: 1.6.2.4.5 git-repo-action (timeout 00:09:29) [common]
219 10:02:02.151948 Using /lava-927468 at stage 0
220 10:02:02.152298 Fetching tests from https://github.com/kernelci/test-definitions.git
221 10:02:02.152579 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/0/tests/1_kselftest-dt'
222 10:02:05.581688 Running '/usr/bin/git checkout kernelci.org
223 10:02:06.033847 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 10:02:06.036474 uuid=927468_1.6.2.4.5 testdef=None
225 10:02:06.037112 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 10:02:06.038617 start: 1.6.2.4.6 test-overlay (timeout 00:09:25) [common]
228 10:02:06.047609 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 10:02:06.049272 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:25) [common]
231 10:02:06.061309 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 10:02:06.063155 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:25) [common]
234 10:02:06.077043 runner path: /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/0/tests/1_kselftest-dt test_uuid 927468_1.6.2.4.5
235 10:02:06.077693 BOARD='beaglebone-black'
236 10:02:06.078216 BRANCH='tip'
237 10:02:06.078667 SKIPFILE='/dev/null'
238 10:02:06.079102 SKIP_INSTALL='True'
239 10:02:06.079505 TESTPROG_URL='http://storage.kernelci.org/tip/master/v6.12-rc5-608-g0c049b492970f/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 10:02:06.079907 TST_CASENAME=''
241 10:02:06.080329 TST_CMDFILES='dt'
242 10:02:06.081560 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 10:02:06.083252 Creating lava-test-runner.conf files
245 10:02:06.083655 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/927468/lava-overlay-gk6wcy_3/lava-927468/0 for stage 0
246 10:02:06.086091 - 0_timesync-off
247 10:02:06.086491 - 1_kselftest-dt
248 10:02:06.086896 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 10:02:06.087204 start: 1.6.2.5 compress-overlay (timeout 00:09:25) [common]
250 10:02:29.474199 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 10:02:29.474613 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:01) [common]
252 10:02:29.474874 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 10:02:29.475142 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 10:02:29.475404 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:01) [common]
255 10:02:29.829935 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 10:02:29.830416 start: 1.6.4 extract-modules (timeout 00:09:01) [common]
257 10:02:29.830669 extracting modules file /var/lib/lava/dispatcher/tmp/927468/tftp-deploy-ucj6ozrr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/927468/extract-nfsrootfs-ih3gcxnl
258 10:02:30.724714 extracting modules file /var/lib/lava/dispatcher/tmp/927468/tftp-deploy-ucj6ozrr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/927468/extract-overlay-ramdisk-47a5i7pg/ramdisk
259 10:02:31.634404 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 10:02:31.634845 start: 1.6.5 apply-overlay-tftp (timeout 00:08:59) [common]
261 10:02:31.635139 [common] Applying overlay to NFS
262 10:02:31.635372 [common] Applying overlay /var/lib/lava/dispatcher/tmp/927468/compress-overlay-h7p5vppb/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/927468/extract-nfsrootfs-ih3gcxnl
263 10:02:34.373714 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 10:02:34.374214 start: 1.6.6 prepare-kernel (timeout 00:08:56) [common]
265 10:02:34.374490 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:56) [common]
266 10:02:34.374769 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 10:02:34.375022 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 10:02:34.375277 start: 1.6.7 configure-preseed-file (timeout 00:08:56) [common]
269 10:02:34.375524 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 10:02:34.375778 start: 1.6.8 compress-ramdisk (timeout 00:08:56) [common]
271 10:02:34.376029 Building ramdisk /var/lib/lava/dispatcher/tmp/927468/extract-overlay-ramdisk-47a5i7pg/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/927468/extract-overlay-ramdisk-47a5i7pg/ramdisk
272 10:02:35.342990 >> 74900 blocks
273 10:02:39.908065 Adding RAMdisk u-boot header.
274 10:02:39.908988 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/927468/extract-overlay-ramdisk-47a5i7pg/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/927468/extract-overlay-ramdisk-47a5i7pg/ramdisk.cpio.gz.uboot
275 10:02:40.067987 output: Image Name:
276 10:02:40.068405 output: Created: Sat Nov 2 10:02:39 2024
277 10:02:40.068614 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 10:02:40.068816 output: Data Size: 14793701 Bytes = 14446.97 KiB = 14.11 MiB
279 10:02:40.069016 output: Load Address: 00000000
280 10:02:40.069213 output: Entry Point: 00000000
281 10:02:40.069410 output:
282 10:02:40.070247 rename /var/lib/lava/dispatcher/tmp/927468/extract-overlay-ramdisk-47a5i7pg/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/927468/tftp-deploy-ucj6ozrr/ramdisk/ramdisk.cpio.gz.uboot
283 10:02:40.070972 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 10:02:40.071514 end: 1.6 prepare-tftp-overlay (duration 00:00:54) [common]
285 10:02:40.072034 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:51) [common]
286 10:02:40.072486 No LXC device requested
287 10:02:40.072979 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 10:02:40.073481 start: 1.8 deploy-device-env (timeout 00:08:51) [common]
289 10:02:40.074005 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 10:02:40.074421 Checking files for TFTP limit of 4294967296 bytes.
291 10:02:40.077065 end: 1 tftp-deploy (duration 00:01:09) [common]
292 10:02:40.077628 start: 2 uboot-action (timeout 00:05:00) [common]
293 10:02:40.078192 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 10:02:40.078682 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 10:02:40.079173 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 10:02:40.079908 substitutions:
297 10:02:40.080317 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 10:02:40.080715 - {DTB_ADDR}: 0x88000000
299 10:02:40.081108 - {DTB}: 927468/tftp-deploy-ucj6ozrr/dtb/am335x-boneblack.dtb
300 10:02:40.081497 - {INITRD}: 927468/tftp-deploy-ucj6ozrr/ramdisk/ramdisk.cpio.gz.uboot
301 10:02:40.081917 - {KERNEL_ADDR}: 0x82000000
302 10:02:40.082307 - {KERNEL}: 927468/tftp-deploy-ucj6ozrr/kernel/zImage
303 10:02:40.082693 - {LAVA_MAC}: None
304 10:02:40.083116 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/927468/extract-nfsrootfs-ih3gcxnl
305 10:02:40.083511 - {NFS_SERVER_IP}: 192.168.6.3
306 10:02:40.083896 - {PRESEED_CONFIG}: None
307 10:02:40.084282 - {PRESEED_LOCAL}: None
308 10:02:40.084665 - {RAMDISK_ADDR}: 0x83000000
309 10:02:40.085044 - {RAMDISK}: 927468/tftp-deploy-ucj6ozrr/ramdisk/ramdisk.cpio.gz.uboot
310 10:02:40.085430 - {ROOT_PART}: None
311 10:02:40.085826 - {ROOT}: None
312 10:02:40.086217 - {SERVER_IP}: 192.168.6.3
313 10:02:40.086597 - {TEE_ADDR}: 0x83000000
314 10:02:40.086977 - {TEE}: None
315 10:02:40.087359 Parsed boot commands:
316 10:02:40.087728 - setenv autoload no
317 10:02:40.088110 - setenv initrd_high 0xffffffff
318 10:02:40.088490 - setenv fdt_high 0xffffffff
319 10:02:40.088867 - dhcp
320 10:02:40.089245 - setenv serverip 192.168.6.3
321 10:02:40.089624 - tftp 0x82000000 927468/tftp-deploy-ucj6ozrr/kernel/zImage
322 10:02:40.090032 - tftp 0x83000000 927468/tftp-deploy-ucj6ozrr/ramdisk/ramdisk.cpio.gz.uboot
323 10:02:40.090417 - setenv initrd_size ${filesize}
324 10:02:40.090793 - tftp 0x88000000 927468/tftp-deploy-ucj6ozrr/dtb/am335x-boneblack.dtb
325 10:02:40.091172 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/927468/extract-nfsrootfs-ih3gcxnl,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 10:02:40.091563 - bootz 0x82000000 0x83000000 0x88000000
327 10:02:40.092046 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 10:02:40.093496 start: 2.3 connect-device (timeout 00:05:00) [common]
330 10:02:40.093934 [common] connect-device Connecting to device using 'telnet conserv3 3002'
331 10:02:40.107537 Setting prompt string to ['lava-test: # ']
332 10:02:40.109006 end: 2.3 connect-device (duration 00:00:00) [common]
333 10:02:40.109589 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 10:02:40.110184 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 10:02:40.110709 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 10:02:40.111861 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-05'
337 10:02:40.147364 >> OK - accepted request
338 10:02:40.149424 Returned 0 in 0 seconds
339 10:02:40.250582 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 10:02:40.252195 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 10:02:40.252749 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 10:02:40.253269 Setting prompt string to ['Hit any key to stop autoboot']
344 10:02:40.253732 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 10:02:40.255346 Trying 192.168.56.22...
346 10:02:40.255829 Connected to conserv3.
347 10:02:40.256246 Escape character is '^]'.
348 10:02:40.256655
349 10:02:40.257070 ser2net port telnet,3002 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 10:02:40.257478
351 10:02:49.277871
352 10:02:49.284720 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
353 10:02:49.285159 Trying to boot from MMC1
354 10:02:53.340897
355 10:02:53.347790 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
356 10:02:53.348262 Trying to boot from MMC1
357 10:02:56.030144
358 10:02:56.037285 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
359 10:02:56.037744 Trying to boot from MMC1
360 10:02:56.620114
361 10:02:56.620582
362 10:02:56.625799 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
363 10:02:56.626283
364 10:02:56.626705 CPU : AM335X-GP rev 2.0
365 10:02:56.630952 Model: TI AM335x BeagleBone Black
366 10:02:56.631382 DRAM: 512 MiB
367 10:02:56.710636 Core: 160 devices, 18 uclasses, devicetree: separate
368 10:02:56.724678 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
369 10:02:57.125537 NAND: 0 MiB
370 10:02:57.135688 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
371 10:02:57.263460 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
372 10:02:57.284851 <ethaddr> not set. Validating first E-fuse MAC
373 10:02:57.315261 Net: eth2: ethernet@4a100000, eth3: usb_ether
375 10:02:57.373769 Hit any key to stop autoboot: 2
376 10:02:57.374617 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
377 10:02:57.375208 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
378 10:02:57.375686 Setting prompt string to ['=>']
379 10:02:57.376167 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
380 10:02:57.383678 0
381 10:02:57.384525 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
382 10:02:57.385029 Sending with 10 millisecond of delay
384 10:02:58.519495 => setenv autoload no
385 10:02:58.530218 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
386 10:02:58.535156 setenv autoload no
387 10:02:58.535893 Sending with 10 millisecond of delay
389 10:03:00.332377 => setenv initrd_high 0xffffffff
390 10:03:00.343125 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
391 10:03:00.343977 setenv initrd_high 0xffffffff
392 10:03:00.344676 Sending with 10 millisecond of delay
394 10:03:01.960648 => setenv fdt_high 0xffffffff
395 10:03:01.971426 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
396 10:03:01.972273 setenv fdt_high 0xffffffff
397 10:03:01.972976 Sending with 10 millisecond of delay
399 10:03:02.264728 => dhcp
400 10:03:02.275466 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
401 10:03:02.276306 dhcp
402 10:03:02.278230 link up on port 0, speed 100, full duplex
403 10:03:02.278692 BOOTP broadcast 1
404 10:03:02.529675 BOOTP broadcast 2
405 10:03:03.031648 BOOTP broadcast 3
406 10:03:04.033742 BOOTP broadcast 4
407 10:03:04.124188 DHCP client bound to address 192.168.6.8 (1843 ms)
408 10:03:04.125072 Sending with 10 millisecond of delay
410 10:03:05.817484 => setenv serverip 192.168.6.3
411 10:03:05.829985 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:34)
412 10:03:05.832396 setenv serverip 192.168.6.3
413 10:03:05.834089 Sending with 10 millisecond of delay
415 10:03:09.327477 => tftp 0x82000000 927468/tftp-deploy-ucj6ozrr/kernel/zImage
416 10:03:09.338339 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:31)
417 10:03:09.339325 tftp 0x82000000 927468/tftp-deploy-ucj6ozrr/kernel/zImage
418 10:03:09.339804 link up on port 0, speed 100, full duplex
419 10:03:09.343275 Using ethernet@4a100000 device
420 10:03:09.349716 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
421 10:03:09.350248 Filename '927468/tftp-deploy-ucj6ozrr/kernel/zImage'.
422 10:03:09.352148 Load address: 0x82000000
423 10:03:11.526038 Loading: *################################################## 10.9 MiB
424 10:03:11.526506 5 MiB/s
425 10:03:11.526753 done
426 10:03:11.530029 Bytes transferred = 11457024 (aed200 hex)
427 10:03:11.530746 Sending with 10 millisecond of delay
429 10:03:15.980228 => tftp 0x83000000 927468/tftp-deploy-ucj6ozrr/ramdisk/ramdisk.cpio.gz.uboot
430 10:03:15.990863 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
431 10:03:15.991509 tftp 0x83000000 927468/tftp-deploy-ucj6ozrr/ramdisk/ramdisk.cpio.gz.uboot
432 10:03:15.991781 link up on port 0, speed 100, full duplex
433 10:03:15.995987 Using ethernet@4a100000 device
434 10:03:16.001502 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
435 10:03:16.004880 Filename '927468/tftp-deploy-ucj6ozrr/ramdisk/ramdisk.cpio.gz.uboot'.
436 10:03:16.009849 Load address: 0x83000000
437 10:03:18.680518 Loading: *################################################## 14.1 MiB
438 10:03:18.681148 5.3 MiB/s
439 10:03:18.681558 done
440 10:03:18.684825 Bytes transferred = 14793765 (e1bc25 hex)
441 10:03:18.685601 Sending with 10 millisecond of delay
443 10:03:20.544973 => setenv initrd_size ${filesize}
444 10:03:20.555724 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
445 10:03:20.556349 setenv initrd_size ${filesize}
446 10:03:20.556831 Sending with 10 millisecond of delay
448 10:03:24.704045 => tftp 0x88000000 927468/tftp-deploy-ucj6ozrr/dtb/am335x-boneblack.dtb
449 10:03:24.714702 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
450 10:03:24.715255 tftp 0x88000000 927468/tftp-deploy-ucj6ozrr/dtb/am335x-boneblack.dtb
451 10:03:24.715493 link up on port 0, speed 100, full duplex
452 10:03:24.719448 Using ethernet@4a100000 device
453 10:03:24.725199 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
454 10:03:24.735829 Filename '927468/tftp-deploy-ucj6ozrr/dtb/am335x-boneblack.dtb'.
455 10:03:24.736190 Load address: 0x88000000
456 10:03:24.746217 Loading: *################################################## 68.9 KiB
457 10:03:24.746559 4.8 MiB/s
458 10:03:24.754218 done
459 10:03:24.754540 Bytes transferred = 70568 (113a8 hex)
460 10:03:24.754986 Sending with 10 millisecond of delay
462 10:03:37.940770 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/927468/extract-nfsrootfs-ih3gcxnl,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
463 10:03:37.951698 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:02)
464 10:03:37.952654 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/927468/extract-nfsrootfs-ih3gcxnl,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
465 10:03:37.953376 Sending with 10 millisecond of delay
467 10:03:40.294178 => bootz 0x82000000 0x83000000 0x88000000
468 10:03:40.305441 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
469 10:03:40.306339 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:00)
470 10:03:40.307759 bootz 0x82000000 0x83000000 0x88000000
471 10:03:40.308849 Kernel image @ 0x82000000 [ 0x000000 - 0xaed200 ]
472 10:03:40.309513 ## Loading init Ramdisk from Legacy Image at 83000000 ...
473 10:03:40.313335 Image Name:
474 10:03:40.313632 Created: 2024-11-02 10:02:39 UTC
475 10:03:40.322243 Image Type: ARM Linux RAMDisk Image (uncompressed)
476 10:03:40.322584 Data Size: 14793701 Bytes = 14.1 MiB
477 10:03:40.330271 Load Address: 00000000
478 10:03:40.330594 Entry Point: 00000000
479 10:03:40.498577 Verifying Checksum ... OK
480 10:03:40.499007 ## Flattened Device Tree blob at 88000000
481 10:03:40.505041 Booting using the fdt blob at 0x88000000
482 10:03:40.505380 Working FDT set to 88000000
483 10:03:40.510543 Using Device Tree in place at 88000000, end 880143a7
484 10:03:40.515039 Working FDT set to 88000000
485 10:03:40.528592
486 10:03:40.529158 Starting kernel ...
487 10:03:40.529637
488 10:03:40.530632 end: 2.4.3 bootloader-commands (duration 00:00:43) [common]
489 10:03:40.531302 start: 2.4.4 auto-login-action (timeout 00:04:00) [common]
490 10:03:40.531819 Setting prompt string to ['Linux version [0-9]']
491 10:03:40.532086 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
492 10:03:40.532334 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
493 10:03:41.370279 [ 0.000000] Booting Linux on physical CPU 0x0
494 10:03:41.375961 start: 2.4.4.1 login-action (timeout 00:03:59) [common]
495 10:03:41.376586 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
496 10:03:41.376885 Setting prompt string to []
497 10:03:41.377146 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
498 10:03:41.377385 Using line separator: #'\n'#
499 10:03:41.377605 No login prompt set.
500 10:03:41.377866 Parsing kernel messages
501 10:03:41.378086 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
502 10:03:41.378564 [login-action] Waiting for messages, (timeout 00:03:59)
503 10:03:41.378825 Waiting using forced prompt support (timeout 00:01:59)
504 10:03:41.390278 [ 0.000000] Linux version 6.12.0-rc5 (KernelCI@build-j359884-arm-gcc-12-multi-v7-defconfig-sct6s) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Sat Nov 2 09:41:15 UTC 2024
505 10:03:41.406178 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
506 10:03:41.406770 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
507 10:03:41.410379 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
508 10:03:41.416199 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
509 10:03:41.421905 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
510 10:03:41.435701 [ 0.000000] Memory policy: Data cache writeback
511 10:03:41.436145 [ 0.000000] efi: UEFI not found.
512 10:03:41.440157 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
513 10:03:41.452637 [ 0.000000] Zone ranges:
514 10:03:41.453220 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
515 10:03:41.453469 [ 0.000000] Normal empty
516 10:03:41.457547 [ 0.000000] HighMem empty
517 10:03:41.463284 [ 0.000000] Movable zone start for each node
518 10:03:41.463749 [ 0.000000] Early memory node ranges
519 10:03:41.468949 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
520 10:03:41.478948 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
521 10:03:41.504245 [ 0.000000] CPU: All CPU(s) started in SVC mode.
522 10:03:41.509848 [ 0.000000] AM335X ES2.0 (sgx neon)
523 10:03:41.521510 [ 0.000000] percpu: Embedded 17 pages/cpu s40908 r8192 d20532 u69632
524 10:03:41.539170 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/927468/extract-nfsrootfs-ih3gcxnl,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
525 10:03:41.550742 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
526 10:03:41.556461 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
527 10:03:41.562166 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
528 10:03:41.571278 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
529 10:03:41.601277 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
530 10:03:41.607226 <6>[ 0.000000] trace event string verifier disabled
531 10:03:41.607545 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
532 10:03:41.615264 <6>[ 0.000000] rcu: RCU event tracing is enabled.
533 10:03:41.621025 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
534 10:03:41.626926 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
535 10:03:41.632478 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
536 10:03:41.644109 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
537 10:03:41.652496 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1.
538 10:03:41.667483 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
539 10:03:41.684867 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
540 10:03:41.690671 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
541 10:03:41.784679 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
542 10:03:41.796125 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
543 10:03:41.802877 <6>[ 0.008339] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
544 10:03:41.816007 <6>[ 0.019139] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
545 10:03:41.823349 <6>[ 0.033951] Console: colour dummy device 80x30
546 10:03:41.829867 Matched prompt #6: WARNING:
547 10:03:41.830842 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
548 10:03:41.834910 <3>[ 0.038851] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
549 10:03:41.840574 <3>[ 0.045923] This ensures that you still see kernel messages. Please
550 10:03:41.843791 <3>[ 0.052650] update your kernel commandline.
551 10:03:41.884499 <6>[ 0.057260] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
552 10:03:41.890285 <6>[ 0.096148] CPU: Testing write buffer coherency: ok
553 10:03:41.896184 <6>[ 0.101517] CPU0: Spectre v2: using BPIALL workaround
554 10:03:41.896744 <6>[ 0.106983] pid_max: default: 32768 minimum: 301
555 10:03:41.907670 <6>[ 0.112176] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
556 10:03:41.914471 <6>[ 0.120004] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
557 10:03:41.921596 <6>[ 0.129341] CPU0: thread -1, cpu 0, socket -1, mpidr 0
558 10:03:41.987339 <6>[ 0.189656] Setting up static identity map for 0x80300000 - 0x803000ac
559 10:03:41.993170 <6>[ 0.199250] rcu: Hierarchical SRCU implementation.
560 10:03:41.996802 <6>[ 0.204535] rcu: Max phase no-delay instances is 1000.
561 10:03:42.005118 <6>[ 0.215472] EFI services will not be available.
562 10:03:42.010940 <6>[ 0.220805] smp: Bringing up secondary CPUs ...
563 10:03:42.016713 <6>[ 0.225776] smp: Brought up 1 node, 1 CPU
564 10:03:42.022702 <6>[ 0.230262] SMP: Total of 1 processors activated (996.14 BogoMIPS).
565 10:03:42.028495 <6>[ 0.236982] CPU: All CPU(s) started in SVC mode.
566 10:03:42.048891 <6>[ 0.242185] Memory: 405996K/522240K available (16384K kernel code, 2543K rwdata, 6788K rodata, 2048K init, 430K bss, 49052K reserved, 65536K cma-reserved, 0K highmem)
567 10:03:42.049803 <6>[ 0.258465] devtmpfs: initialized
568 10:03:42.071223 <6>[ 0.275750] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
569 10:03:42.082659 <6>[ 0.284352] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
570 10:03:42.088612 <6>[ 0.294796] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
571 10:03:42.099353 <6>[ 0.307098] pinctrl core: initialized pinctrl subsystem
572 10:03:42.108643 <6>[ 0.317733] DMI not present or invalid.
573 10:03:42.116911 <6>[ 0.323579] NET: Registered PF_NETLINK/PF_ROUTE protocol family
574 10:03:42.126499 <6>[ 0.332511] DMA: preallocated 256 KiB pool for atomic coherent allocations
575 10:03:42.141600 <6>[ 0.343949] thermal_sys: Registered thermal governor 'step_wise'
576 10:03:42.142704 <6>[ 0.344118] cpuidle: using governor menu
577 10:03:42.169237 <6>[ 0.379903] No ATAGs?
578 10:03:42.175427 <6>[ 0.382545] hw-breakpoint: debug architecture 0x4 unsupported.
579 10:03:42.185492 <6>[ 0.394431] Serial: AMBA PL011 UART driver
580 10:03:42.215170 <6>[ 0.425659] iommu: Default domain type: Translated
581 10:03:42.224210 <6>[ 0.431008] iommu: DMA domain TLB invalidation policy: strict mode
582 10:03:42.251267 <5>[ 0.460353] SCSI subsystem initialized
583 10:03:42.265517 <6>[ 0.470474] usbcore: registered new interface driver usbfs
584 10:03:42.272414 <6>[ 0.476437] usbcore: registered new interface driver hub
585 10:03:42.273343 <6>[ 0.482261] usbcore: registered new device driver usb
586 10:03:42.278156 <6>[ 0.488756] pps_core: LinuxPPS API ver. 1 registered
587 10:03:42.289696 <6>[ 0.494185] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
588 10:03:42.298378 <6>[ 0.503895] PTP clock support registered
589 10:03:42.298917 <6>[ 0.508340] EDAC MC: Ver: 3.0.0
590 10:03:42.345793 <6>[ 0.553767] scmi_core: SCMI protocol bus registered
591 10:03:42.370304 <6>[ 0.580303] vgaarb: loaded
592 10:03:42.376411 <6>[ 0.584077] clocksource: Switched to clocksource dmtimer
593 10:03:42.400702 <6>[ 0.611034] NET: Registered PF_INET protocol family
594 10:03:42.413314 <6>[ 0.616736] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
595 10:03:42.419136 <6>[ 0.625581] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
596 10:03:42.430543 <6>[ 0.634506] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
597 10:03:42.436270 <6>[ 0.642747] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
598 10:03:42.447917 <6>[ 0.651033] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
599 10:03:42.453703 <6>[ 0.658750] TCP: Hash tables configured (established 4096 bind 4096)
600 10:03:42.459515 <6>[ 0.665683] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
601 10:03:42.465439 <6>[ 0.672691] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
602 10:03:42.472331 <6>[ 0.680303] NET: Registered PF_UNIX/PF_LOCAL protocol family
603 10:03:42.558991 <6>[ 0.763952] RPC: Registered named UNIX socket transport module.
604 10:03:42.559611 <6>[ 0.770385] RPC: Registered udp transport module.
605 10:03:42.564708 <6>[ 0.775519] RPC: Registered tcp transport module.
606 10:03:42.570433 <6>[ 0.780625] RPC: Registered tcp-with-tls transport module.
607 10:03:42.583560 <6>[ 0.786549] RPC: Registered tcp NFSv4.1 backchannel transport module.
608 10:03:42.585084 <6>[ 0.793458] PCI: CLS 0 bytes, default 64
609 10:03:42.590710 <5>[ 0.799266] Initialise system trusted keyrings
610 10:03:42.611825 <6>[ 0.819354] Trying to unpack rootfs image as initramfs...
611 10:03:42.690147 <6>[ 0.894518] workingset: timestamp_bits=30 max_order=17 bucket_order=0
612 10:03:42.694768 <6>[ 0.902025] squashfs: version 4.0 (2009/01/31) Phillip Lougher
613 10:03:42.734366 <5>[ 0.944809] NFS: Registering the id_resolver key type
614 10:03:42.740064 <5>[ 0.950413] Key type id_resolver registered
615 10:03:42.745862 <5>[ 0.955104] Key type id_legacy registered
616 10:03:42.751583 <6>[ 0.959550] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
617 10:03:42.761162 <6>[ 0.966750] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
618 10:03:42.830413 <5>[ 1.040880] Key type asymmetric registered
619 10:03:42.836118 <5>[ 1.045462] Asymmetric key parser 'x509' registered
620 10:03:42.847530 <6>[ 1.050881] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
621 10:03:42.848434 <6>[ 1.058796] io scheduler mq-deadline registered
622 10:03:42.853354 <6>[ 1.063725] io scheduler kyber registered
623 10:03:42.858943 <6>[ 1.068209] io scheduler bfq registered
624 10:03:42.963178 <6>[ 1.170106] ledtrig-cpu: registered to indicate activity on CPUs
625 10:03:43.252693 <6>[ 1.459405] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
626 10:03:43.298021 <6>[ 1.508509] msm_serial: driver initialized
627 10:03:43.304040 <6>[ 1.513303] SuperH (H)SCI(F) driver initialized
628 10:03:43.310002 <6>[ 1.518614] STMicroelectronics ASC driver initialized
629 10:03:43.315164 <6>[ 1.524280] STM32 USART driver initialized
630 10:03:43.429248 <6>[ 1.639168] brd: module loaded
631 10:03:43.465026 <6>[ 1.674806] loop: module loaded
632 10:03:43.505908 <6>[ 1.715838] CAN device driver interface
633 10:03:43.512622 <6>[ 1.720872] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
634 10:03:43.518302 <6>[ 1.728054] e1000e: Intel(R) PRO/1000 Network Driver
635 10:03:43.524246 <6>[ 1.733440] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
636 10:03:43.530057 <6>[ 1.739906] igb: Intel(R) Gigabit Ethernet Network Driver
637 10:03:43.538310 <6>[ 1.745757] igb: Copyright (c) 2007-2014 Intel Corporation.
638 10:03:43.550400 <6>[ 1.755398] pegasus: Pegasus/Pegasus II USB Ethernet driver
639 10:03:43.556369 <6>[ 1.761468] usbcore: registered new interface driver pegasus
640 10:03:43.562010 <6>[ 1.767657] usbcore: registered new interface driver asix
641 10:03:43.567729 <6>[ 1.773515] usbcore: registered new interface driver ax88179_178a
642 10:03:43.573577 <6>[ 1.780115] usbcore: registered new interface driver cdc_ether
643 10:03:43.579289 <6>[ 1.786441] usbcore: registered new interface driver smsc75xx
644 10:03:43.585152 <6>[ 1.792649] usbcore: registered new interface driver smsc95xx
645 10:03:43.590825 <6>[ 1.798883] usbcore: registered new interface driver net1080
646 10:03:43.596524 <6>[ 1.805023] usbcore: registered new interface driver cdc_subset
647 10:03:43.602687 <6>[ 1.811412] usbcore: registered new interface driver zaurus
648 10:03:43.610016 <6>[ 1.817478] usbcore: registered new interface driver cdc_ncm
649 10:03:43.620397 <6>[ 1.827368] usbcore: registered new interface driver usb-storage
650 10:03:43.911713 <6>[ 2.120125] i2c_dev: i2c /dev entries driver
651 10:03:43.958628 <5>[ 2.161005] cpuidle: enable-method property 'ti,am3352' found operations
652 10:03:43.964574 <6>[ 2.170696] sdhci: Secure Digital Host Controller Interface driver
653 10:03:43.972063 <6>[ 2.177486] sdhci: Copyright(c) Pierre Ossman
654 10:03:43.979913 <6>[ 2.184171] Synopsys Designware Multimedia Card Interface Driver
655 10:03:43.985016 <6>[ 2.192244] sdhci-pltfm: SDHCI platform and OF driver helper
656 10:03:44.121895 <6>[ 2.325200] usbcore: registered new interface driver usbhid
657 10:03:44.122318 <6>[ 2.331244] usbhid: USB HID core driver
658 10:03:44.173056 <6>[ 2.381035] NET: Registered PF_INET6 protocol family
659 10:03:44.204576 <6>[ 2.415282] Segment Routing with IPv6
660 10:03:44.210403 <6>[ 2.419430] In-situ OAM (IOAM) with IPv6
661 10:03:44.217909 <6>[ 2.423830] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
662 10:03:44.224676 <6>[ 2.431203] NET: Registered PF_PACKET protocol family
663 10:03:44.230477 <6>[ 2.436758] can: controller area network core
664 10:03:44.230984 <6>[ 2.441587] NET: Registered PF_CAN protocol family
665 10:03:44.236347 <6>[ 2.446811] can: raw protocol
666 10:03:44.242107 <6>[ 2.450139] can: broadcast manager protocol
667 10:03:44.248964 <6>[ 2.454733] can: netlink gateway - max_hops=1
668 10:03:44.249454 <5>[ 2.460207] Key type dns_resolver registered
669 10:03:44.254748 <6>[ 2.465292] ThumbEE CPU extension supported.
670 10:03:44.260956 <5>[ 2.469983] Registering SWP/SWPB emulation handler
671 10:03:44.269649 <3>[ 2.475671] omap_voltage_late_init: Voltage driver support not added
672 10:03:44.475534 <5>[ 2.683671] Loading compiled-in X.509 certificates
673 10:03:44.594894 <6>[ 2.792636] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
674 10:03:44.602091 <6>[ 2.809317] pinctrl-single 44e10800.pinmux: 142 pins, size 568
675 10:03:44.628383 <3>[ 2.832951] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
676 10:03:44.841610 <3>[ 3.046075] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
677 10:03:45.026120 <6>[ 3.235047] OMAP GPIO hardware version 0.1
678 10:03:45.046695 <6>[ 3.253638] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
679 10:03:45.149380 <4>[ 3.356073] at24 2-0054: supply vcc not found, using dummy regulator
680 10:03:45.189464 <4>[ 3.396149] at24 2-0055: supply vcc not found, using dummy regulator
681 10:03:45.223060 <4>[ 3.429783] at24 2-0056: supply vcc not found, using dummy regulator
682 10:03:45.262756 <4>[ 3.469449] at24 2-0057: supply vcc not found, using dummy regulator
683 10:03:45.300801 <6>[ 3.508556] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
684 10:03:45.376636 <3>[ 3.580057] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
685 10:03:45.400299 <6>[ 3.600900] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
686 10:03:45.422980 <4>[ 3.627013] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
687 10:03:45.430754 <4>[ 3.636175] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
688 10:03:45.557850 <6>[ 3.764710] omap_rng 48310000.rng: Random Number Generator ver. 20
689 10:03:45.580306 <5>[ 3.790924] random: crng init done
690 10:03:45.641940 <6>[ 3.852311] Freeing initrd memory: 14448K
691 10:03:45.651693 <6>[ 3.857028] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
692 10:03:45.700094 <6>[ 3.904598] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
693 10:03:45.705944 <6>[ 3.914932] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
694 10:03:45.717654 <6>[ 3.922204] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
695 10:03:45.723484 <6>[ 3.929697] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
696 10:03:45.735055 <6>[ 3.937827] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
697 10:03:45.742446 <6>[ 3.949461] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:00:92
698 10:03:45.755521 <5>[ 3.958480] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
699 10:03:45.783135 <3>[ 3.988146] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
700 10:03:45.788925 <6>[ 3.996711] edma 49000000.dma: TI EDMA DMA engine driver
701 10:03:45.859836 <3>[ 4.063983] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
702 10:03:45.874489 <6>[ 4.078396] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
703 10:03:45.887389 <3>[ 4.095489] l3-aon-clkctrl:0000:0: failed to disable
704 10:03:45.930314 <6>[ 4.135218] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
705 10:03:45.935994 <6>[ 4.144685] printk: legacy console [ttyS0] enabled
706 10:03:45.941731 <6>[ 4.144685] printk: legacy console [ttyS0] enabled
707 10:03:45.947360 <6>[ 4.155015] printk: legacy bootconsole [omap8250] disabled
708 10:03:45.953169 <6>[ 4.155015] printk: legacy bootconsole [omap8250] disabled
709 10:03:46.000823 <4>[ 4.204823] tps65217-pmic: Failed to locate of_node [id: -1]
710 10:03:46.004534 <4>[ 4.212195] tps65217-bl: Failed to locate of_node [id: -1]
711 10:03:46.020872 <6>[ 4.231800] tps65217 0-0024: TPS65217 ID 0xe version 1.2
712 10:03:46.039205 <6>[ 4.238732] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
713 10:03:46.050916 <6>[ 4.252414] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
714 10:03:46.056788 <6>[ 4.264309] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
715 10:03:46.078659 <6>[ 4.283901] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
716 10:03:46.084563 <6>[ 4.293092] sdhci-omap 48060000.mmc: Got CD GPIO
717 10:03:46.091699 <4>[ 4.298249] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
718 10:03:46.107272 <4>[ 4.311914] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
719 10:03:46.113721 <4>[ 4.320550] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
720 10:03:46.123581 <4>[ 4.329200] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
721 10:03:46.222379 <6>[ 4.428712] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
722 10:03:46.270474 <6>[ 4.474886] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
723 10:03:46.278536 <6>[ 4.483279] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
724 10:03:46.285275 <6>[ 4.492058] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
725 10:03:46.359159 <6>[ 4.566958] mmc1: new high speed MMC card at address 0001
726 10:03:46.367555 <6>[ 4.576175] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
727 10:03:46.381193 <6>[ 4.583265] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
728 10:03:46.387243 <6>[ 4.596651] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
729 10:03:46.396179 <6>[ 4.604618] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
730 10:03:46.412087 <6>[ 4.619243] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
731 10:03:46.462147 <6>[ 4.663632] mmc0: new high speed SDHC card at address aaaa
732 10:03:46.462582 <6>[ 4.671070] mmcblk0: mmc0:aaaa SU16G 14.8 GiB
733 10:03:46.493746 <6>[ 4.702418] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 >
734 10:03:48.550302 <6>[ 6.755126] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
735 10:03:48.703749 <5>[ 6.794093] Sending DHCP requests ., OK
736 10:03:48.715146 <6>[ 6.918735] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.8
737 10:03:48.715682 <6>[ 6.926849] IP-Config: Complete:
738 10:03:48.726614 <6>[ 6.930392] device=eth0, hwaddr=90:59:af:5b:00:92, ipaddr=192.168.6.8, mask=255.255.255.0, gw=192.168.6.1
739 10:03:48.732382 <6>[ 6.940909] host=192.168.6.8, domain=, nis-domain=(none)
740 10:03:48.738035 <6>[ 6.947095] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
741 10:03:48.744623 <6>[ 6.947132] nameserver0=10.255.253.1
742 10:03:48.750681 <6>[ 6.959724] clk: Disabling unused clocks
743 10:03:48.756280 <6>[ 6.964449] PM: genpd: Disabling unused power domains
744 10:03:48.775810 <6>[ 6.983054] Freeing unused kernel image (initmem) memory: 2048K
745 10:03:48.783446 <6>[ 6.992927] Run /init as init process
746 10:03:48.808182 Loading, please wait...
747 10:03:48.883447 Starting systemd-udevd version 252.22-1~deb12u1
748 10:03:51.935605 <4>[ 10.139217] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
749 10:03:52.051835 <4>[ 10.255501] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
750 10:03:52.263763 <6>[ 10.474786] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
751 10:03:52.273434 <6>[ 10.480463] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
752 10:03:52.529261 <6>[ 10.738922] hub 1-0:1.0: USB hub found
753 10:03:52.605422 <6>[ 10.814291] hub 1-0:1.0: 1 port detected
754 10:03:52.638108 <6>[ 10.847433] tda998x 0-0070: found TDA19988
755 10:03:55.785180 Begin: Loading essential drivers ... done.
756 10:03:55.790945 Begin: Running /scripts/init-premount ... done.
757 10:03:55.796416 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
758 10:03:55.811244 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
759 10:03:55.811827 Device /sys/class/net/eth0 found
760 10:03:55.812319 done.
761 10:03:55.871010 Begin: Waiting up to 180 secs for any network device to become available ... done.
762 10:03:55.935326 IP-Config: eth0 hardware address 90:59:af:5b:00:92 mtu 1500 DHCP
763 10:03:56.031844 IP-Config: eth0 guessed broadcast address 192.168.6.255
764 10:03:56.037374 IP-Config: eth0 complete (dhcp from 192.168.6.1):
765 10:03:56.043132 address: 192.168.6.8 broadcast: 192.168.6.255 netmask: 255.255.255.0
766 10:03:56.054237 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
767 10:03:56.054815 rootserver: 192.168.6.1 rootpath:
768 10:03:56.057871 filename :
769 10:03:56.134614 done.
770 10:03:56.145364 Begin: Running /scripts/nfs-bottom ... done.
771 10:03:56.219878 Begin: Running /scripts/init-bottom ... done.
772 10:03:57.713013 <30>[ 15.919912] systemd[1]: System time before build time, advancing clock.
773 10:03:57.904599 <30>[ 16.085206] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
774 10:03:57.913532 <30>[ 16.122030] systemd[1]: Detected architecture arm.
775 10:03:57.927407
776 10:03:57.927852 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
777 10:03:57.928118
778 10:03:57.957062 <30>[ 16.164490] systemd[1]: Hostname set to <debian-bookworm-armhf>.
779 10:04:00.095848 <30>[ 18.302061] systemd[1]: Queued start job for default target graphical.target.
780 10:04:00.112918 <30>[ 18.317143] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
781 10:04:00.120552 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
782 10:04:00.142517 <30>[ 18.347100] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
783 10:04:00.151087 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
784 10:04:00.172964 <30>[ 18.377482] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
785 10:04:00.181382 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
786 10:04:00.201476 <30>[ 18.406113] systemd[1]: Created slice user.slice - User and Session Slice.
787 10:04:00.208150 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
788 10:04:00.236578 <30>[ 18.435541] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
789 10:04:00.242602 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
790 10:04:00.260517 <30>[ 18.465235] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
791 10:04:00.269476 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
792 10:04:00.301514 <30>[ 18.495248] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
793 10:04:00.307933 <30>[ 18.515757] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
794 10:04:00.316440 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
795 10:04:00.339508 <30>[ 18.544553] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
796 10:04:00.347890 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
797 10:04:00.370210 <30>[ 18.574871] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
798 10:04:00.378641 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
799 10:04:00.400206 <30>[ 18.605150] systemd[1]: Reached target paths.target - Path Units.
800 10:04:00.405329 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
801 10:04:00.429860 <30>[ 18.634732] systemd[1]: Reached target remote-fs.target - Remote File Systems.
802 10:04:00.437212 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
803 10:04:00.459777 <30>[ 18.664630] systemd[1]: Reached target slices.target - Slice Units.
804 10:04:00.465178 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
805 10:04:00.489950 <30>[ 18.694896] systemd[1]: Reached target swap.target - Swaps.
806 10:04:00.494083 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
807 10:04:00.520131 <30>[ 18.724867] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
808 10:04:00.528059 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
809 10:04:00.551086 <30>[ 18.755607] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
810 10:04:00.559153 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
811 10:04:00.638081 <30>[ 18.838812] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
812 10:04:00.651492 <30>[ 18.856212] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
813 10:04:00.659918 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
814 10:04:00.682890 <30>[ 18.886836] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
815 10:04:00.690227 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
816 10:04:00.712486 <30>[ 18.917224] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
817 10:04:00.720409 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
818 10:04:00.745501 <30>[ 18.949057] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
819 10:04:00.751005 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
820 10:04:00.782310 <30>[ 18.985824] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
821 10:04:00.789873 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
822 10:04:00.817041 <30>[ 19.015866] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
823 10:04:00.835668 <30>[ 19.034423] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
824 10:04:00.879927 <30>[ 19.084775] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
825 10:04:00.887402 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
826 10:04:00.920845 <30>[ 19.126328] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
827 10:04:00.953428 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
828 10:04:01.003131 <30>[ 19.207718] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
829 10:04:01.024929 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
830 10:04:01.073039 <30>[ 19.278250] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
831 10:04:01.098638 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
832 10:04:01.149932 <30>[ 19.355448] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
833 10:04:01.178452 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
834 10:04:01.229973 <30>[ 19.436935] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
835 10:04:01.256537 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
836 10:04:01.311177 <30>[ 19.516020] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
837 10:04:01.328912 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
838 10:04:01.390177 <30>[ 19.596044] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
839 10:04:01.409699 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
840 10:04:01.443337 <30>[ 19.649283] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
841 10:04:01.465104 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
842 10:04:01.496831 <28>[ 19.696481] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
843 10:04:01.505291 <28>[ 19.710357] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
844 10:04:01.549166 <30>[ 19.755546] systemd[1]: Starting systemd-journald.service - Journal Service...
845 10:04:01.568212 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
846 10:04:01.650320 <30>[ 19.855933] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
847 10:04:01.663463 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
848 10:04:01.705490 <30>[ 19.911278] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
849 10:04:01.759798 Starting [0;1;39msystemd-network-g… units from Kernel command line...
850 10:04:01.825558 <30>[ 20.029875] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
851 10:04:01.869695 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
852 10:04:01.933471 <30>[ 20.138594] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
853 10:04:01.981639 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
854 10:04:02.050082 <30>[ 20.256000] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
855 10:04:02.091700 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
856 10:04:02.098370 <30>[ 20.305824] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
857 10:04:02.139527 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
858 10:04:02.170822 <30>[ 20.375540] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
859 10:04:02.202933 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
860 10:04:02.382334 <30>[ 20.589667] systemd[1]: modprobe@configfs.service: Deactivated successfully.
861 10:04:02.419802 <30>[ 20.625671] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
862 10:04:02.439983 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
863 10:04:02.466904 <30>[ 20.673451] systemd[1]: Started systemd-journald.service - Journal Service.
864 10:04:02.489504 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
865 10:04:02.521140 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
866 10:04:02.545134 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
867 10:04:02.581877 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
868 10:04:02.604527 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
869 10:04:02.644016 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
870 10:04:02.673184 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
871 10:04:02.702057 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
872 10:04:02.739454 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
873 10:04:02.764276 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
874 10:04:02.829096 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
875 10:04:02.871492 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
876 10:04:02.936219 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
877 10:04:03.014183 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
878 10:04:03.101979 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
879 10:04:03.222153 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
880 10:04:03.270036 <46>[ 21.475838] systemd-journald[165]: Received client request to flush runtime journal.
881 10:04:03.330709 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
882 10:04:03.889802 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
883 10:04:04.532700 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
884 10:04:04.599854 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
885 10:04:04.955620 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
886 10:04:05.150817 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
887 10:04:05.179523 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
888 10:04:05.199475 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
889 10:04:05.262177 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
890 10:04:05.317070 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
891 10:04:06.196664 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
892 10:04:06.264918 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
893 10:04:06.692261 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
894 10:04:06.815581 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
895 10:04:06.894309 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
896 10:04:08.842630 [[0m[0;31m* [0m] (1 of 5) Job systemd-update-utmp.service/start running (8s / no limit)
897 10:04:08.886149 M
[K[[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
898 10:04:08.925128 [K<5>[ 27.131129] cfg80211: Loading compiled-in X.509 certificates for regulatory database
899 10:04:09.179907 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
900 10:04:09.926681 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
901 10:04:10.008739 <5>[ 28.216821] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
902 10:04:10.091085 <5>[ 28.297568] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
903 10:04:10.104094 <4>[ 28.309962] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
904 10:04:10.110029 <6>[ 28.319113] cfg80211: failed to load regulatory.db
905 10:04:11.195928 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
906 10:04:11.322380 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - N<46>[ 29.518121] systemd-journald[165]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
907 10:04:11.325948 etwork Time Synchronization.
908 10:04:11.467444 <46>[ 29.666683] systemd-journald[165]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
909 10:04:20.804343 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
910 10:04:20.833642 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
911 10:04:20.860558 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
912 10:04:20.881172 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
913 10:04:20.953554 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
914 10:04:21.031590 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
915 10:04:21.092945 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
916 10:04:21.137419 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
917 10:04:21.204049 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
918 10:04:21.240380 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
919 10:04:21.265074 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
920 10:04:21.294881 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
921 10:04:21.336079 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
922 10:04:21.367078 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
923 10:04:21.402670 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
924 10:04:21.416212 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
925 10:04:21.452431 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
926 10:04:21.489479 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
927 10:04:21.510095 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
928 10:04:21.529263 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
929 10:04:21.559750 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
930 10:04:21.579139 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
931 10:04:21.605714 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
932 10:04:21.679438 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
933 10:04:21.732804 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
934 10:04:21.834585 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
935 10:04:21.911139 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
936 10:04:21.960146 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
937 10:04:21.991534 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
938 10:04:22.028449 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
939 10:04:22.225846 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
940 10:04:22.300451 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
941 10:04:22.361469 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
942 10:04:22.378761 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
943 10:04:22.390713 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
944 10:04:22.616786 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
945 10:04:22.975830 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
946 10:04:23.026489 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
947 10:04:23.054179 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
948 10:04:23.143605 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
949 10:04:23.321038 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
950 10:04:23.436193
951 10:04:23.439631 Debian GNU/Linux 12 dworm-armhf login: root (automatic login)
952 10:04:23.440116
953 10:04:23.749184 Linux debian-bookworm-armhf 6.12.0-rc5 #1 SMP Sat Nov 2 09:41:15 UTC 2024 armv7l
954 10:04:23.749783
955 10:04:23.754925 The programs included with the Debian GNU/Linux system are free software;
956 10:04:23.760382 the exact distribution terms for each program are described in the
957 10:04:23.766159 individual files in /usr/share/doc/*/copyright.
958 10:04:23.766674
959 10:04:23.774053 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
960 10:04:23.774582 permitted by applicable law.
961 10:04:28.806477 Unable to match end of the kernel message
963 10:04:28.808014 Setting prompt string to ['/ #']
964 10:04:28.808582 end: 2.4.4.1 login-action (duration 00:00:47) [common]
966 10:04:28.810018 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
967 10:04:28.810590 start: 2.4.5 expect-shell-connection (timeout 00:03:11) [common]
968 10:04:28.811047 Setting prompt string to ['/ #']
969 10:04:28.811472 Forcing a shell prompt, looking for ['/ #']
971 10:04:28.862456 / #
972 10:04:28.863162 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
973 10:04:28.863630 Waiting using forced prompt support (timeout 00:02:30)
974 10:04:28.869560
975 10:04:28.874499 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
976 10:04:28.875175 start: 2.4.6 export-device-env (timeout 00:03:11) [common]
977 10:04:28.875720 Sending with 10 millisecond of delay
979 10:04:33.863671 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/927468/extract-nfsrootfs-ih3gcxnl'
980 10:04:33.874335 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/927468/extract-nfsrootfs-ih3gcxnl'
981 10:04:33.875118 Sending with 10 millisecond of delay
983 10:04:35.972447 / # export NFS_SERVER_IP='192.168.6.3'
984 10:04:35.983391 export NFS_SERVER_IP='192.168.6.3'
985 10:04:35.986283 end: 2.4.6 export-device-env (duration 00:00:07) [common]
986 10:04:35.986649 end: 2.4 uboot-commands (duration 00:01:56) [common]
987 10:04:35.986968 end: 2 uboot-action (duration 00:01:56) [common]
988 10:04:35.987260 start: 3 lava-test-retry (timeout 00:06:55) [common]
989 10:04:35.987581 start: 3.1 lava-test-shell (timeout 00:06:55) [common]
990 10:04:35.987835 Using namespace: common
992 10:04:36.088528 / # #
993 10:04:36.089175 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
994 10:04:36.093728 #
995 10:04:36.098783 Using /lava-927468
997 10:04:36.200041 / # export SHELL=/bin/bash
998 10:04:36.204445 export SHELL=/bin/bash
1000 10:04:36.312487 / # . /lava-927468/environment
1001 10:04:36.317368 . /lava-927468/environment
1003 10:04:36.430471 / # /lava-927468/bin/lava-test-runner /lava-927468/0
1004 10:04:36.431373 Test shell timeout: 10s (minimum of the action and connection timeout)
1005 10:04:36.436022 /lava-927468/bin/lava-test-runner /lava-927468/0
1006 10:04:36.818910 + export TESTRUN_ID=0_timesync-off
1007 10:04:36.825880 + TESTRUN_ID=0_timesync-off
1008 10:04:36.826408 + cd /lava-927468/0/tests/0_timesync-off
1009 10:04:36.826881 ++ cat uuid
1010 10:04:36.842890 + UUID=927468_1.6.2.4.1
1011 10:04:36.843414 + set +x
1012 10:04:36.851370 <LAVA_SIGNAL_STARTRUN 0_timesync-off 927468_1.6.2.4.1>
1013 10:04:36.851883 + systemctl stop systemd-timesyncd
1014 10:04:36.852638 Received signal: <STARTRUN> 0_timesync-off 927468_1.6.2.4.1
1015 10:04:36.853121 Starting test lava.0_timesync-off (927468_1.6.2.4.1)
1016 10:04:36.853700 Skipping test definition patterns.
1017 10:04:37.166837 + set +x
1018 10:04:37.167389 <LAVA_SIGNAL_ENDRUN 0_timesync-off 927468_1.6.2.4.1>
1019 10:04:37.168119 Received signal: <ENDRUN> 0_timesync-off 927468_1.6.2.4.1
1020 10:04:37.168653 Ending use of test pattern.
1021 10:04:37.169104 Ending test lava.0_timesync-off (927468_1.6.2.4.1), duration 0.32
1023 10:04:37.327621 + export TESTRUN_ID=1_kselftest-dt
1024 10:04:37.334556 + TESTRUN_ID=1_kselftest-dt
1025 10:04:37.335081 + cd /lava-927468/0/tests/1_kselftest-dt
1026 10:04:37.335548 ++ cat uuid
1027 10:04:37.351140 + UUID=927468_1.6.2.4.5
1028 10:04:37.351654 + set +x
1029 10:04:37.356734 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 927468_1.6.2.4.5>
1030 10:04:37.357248 + cd ./automated/linux/kselftest/
1031 10:04:37.357975 Received signal: <STARTRUN> 1_kselftest-dt 927468_1.6.2.4.5
1032 10:04:37.358456 Starting test lava.1_kselftest-dt (927468_1.6.2.4.5)
1033 10:04:37.359008 Skipping test definition patterns.
1034 10:04:37.383021 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/tip/master/v6.12-rc5-608-g0c049b492970f/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g tip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1035 10:04:37.494991 INFO: install_deps skipped
1036 10:04:38.044136 --2024-11-02 10:04:38-- http://storage.kernelci.org/tip/master/v6.12-rc5-608-g0c049b492970f/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1037 10:04:38.073902 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1038 10:04:38.210650 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1039 10:04:38.347275 HTTP request sent, awaiting response... 200 OK
1040 10:04:38.347842 Length: 4111880 (3.9M) [application/octet-stream]
1041 10:04:38.352860 Saving to: 'kselftest_armhf.tar.gz'
1042 10:04:38.353376
1043 10:04:39.844564
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 186KB/s
kselftest_armhf.tar 5%[> ] 218.67K 407KB/s
kselftest_armhf.tar 19%[==> ] 780.20K 972KB/s
kselftest_armhf.tar 26%[====> ] 1.04M 953KB/s
kselftest_armhf.tar 78%[==============> ] 3.06M 2.13MB/s
kselftest_armhf.tar 100%[===================>] 3.92M 2.63MB/s in 1.5s
1044 10:04:39.845258
1045 10:04:40.558770 2024-11-02 10:04:39 (2.63 MB/s) - 'kselftest_armhf.tar.gz' saved [4111880/4111880]
1046 10:04:40.559443
1047 10:04:55.534324 skiplist:
1048 10:04:55.534763 ========================================
1049 10:04:55.540026 ========================================
1050 10:04:55.649894 dt:test_unprobed_devices.sh
1051 10:04:55.686150 ============== Tests to run ===============
1052 10:04:55.694387 dt:test_unprobed_devices.sh
1053 10:04:55.698252 ===========End Tests to run ===============
1054 10:04:55.708017 shardfile-dt pass
1055 10:04:55.956368 <12>[ 74.168110] kselftest: Running tests in dt
1056 10:04:55.985729 TAP version 13
1057 10:04:56.010058 1..1
1058 10:04:56.064621 # timeout set to 45
1059 10:04:56.065028 # selftests: dt: test_unprobed_devices.sh
1060 10:04:56.896525 # TAP version 13
1061 10:05:21.788598 # 1..257
1062 10:05:21.967555 # ok 1 / # SKIP
1063 10:05:21.995737 # ok 2 /clk_mcasp0
1064 10:05:22.064367 # ok 3 /clk_mcasp0_fixed # SKIP
1065 10:05:22.132878 # ok 4 /cpus/cpu@0 # SKIP
1066 10:05:22.207430 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1067 10:05:22.227480 # ok 6 /fixedregulator0
1068 10:05:22.243480 # ok 7 /leds
1069 10:05:22.269724 # ok 8 /ocp
1070 10:05:22.298793 # ok 9 /ocp/interconnect@44c00000
1071 10:05:22.315768 # ok 10 /ocp/interconnect@44c00000/segment@0
1072 10:05:22.338136 # ok 11 /ocp/interconnect@44c00000/segment@100000
1073 10:05:22.368042 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1074 10:05:22.434412 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1075 10:05:22.454984 # ok 14 /ocp/interconnect@44c00000/segment@200000
1076 10:05:22.480210 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1077 10:05:22.585693 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1078 10:05:22.662151 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1079 10:05:22.733138 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1080 10:05:22.815517 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1081 10:05:22.886910 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1082 10:05:22.954572 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1083 10:05:23.025483 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1084 10:05:23.101768 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1085 10:05:23.169146 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1086 10:05:23.244960 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1087 10:05:23.315623 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1088 10:05:23.383376 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1089 10:05:23.455978 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1090 10:05:23.529326 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1091 10:05:23.598920 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1092 10:05:23.674655 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1093 10:05:23.744771 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1094 10:05:23.816712 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1095 10:05:23.884508 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1096 10:05:23.958101 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1097 10:05:24.029598 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1098 10:05:24.101439 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1099 10:05:24.174232 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1100 10:05:24.245934 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1101 10:05:24.367262 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1102 10:05:24.439331 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1103 10:05:24.518976 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1104 10:05:24.586811 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1105 10:05:24.661259 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1106 10:05:24.734324 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1107 10:05:24.805239 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1108 10:05:24.875596 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1109 10:05:24.943538 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1110 10:05:25.014380 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1111 10:05:25.086824 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1112 10:05:25.161939 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1113 10:05:25.233285 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1114 10:05:25.302070 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1115 10:05:25.373345 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1116 10:05:25.444712 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1117 10:05:25.521506 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1118 10:05:25.590418 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1119 10:05:25.662445 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1120 10:05:25.734323 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1121 10:05:25.805266 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1122 10:05:25.881580 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1123 10:05:25.953680 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1124 10:05:26.025593 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1125 10:05:26.097532 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1126 10:05:26.163599 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1127 10:05:26.237907 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1128 10:05:26.308579 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1129 10:05:26.385885 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1130 10:05:26.456888 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1131 10:05:26.525697 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1132 10:05:26.601351 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1133 10:05:26.676550 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1134 10:05:26.746038 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1135 10:05:26.820400 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1136 10:05:26.888233 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1137 10:05:26.965674 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1138 10:05:27.037540 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1139 10:05:27.107574 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1140 10:05:27.176528 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1141 10:05:27.256255 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1142 10:05:27.325749 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1143 10:05:27.397524 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1144 10:05:27.464728 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1145 10:05:27.542892 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1146 10:05:27.608476 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1147 10:05:27.680942 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1148 10:05:27.752395 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1149 10:05:27.827001 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1150 10:05:27.897934 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1151 10:05:27.969882 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1152 10:05:28.039003 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1153 10:05:28.113284 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1154 10:05:28.183831 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1155 10:05:28.255739 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1156 10:05:28.277577 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1157 10:05:28.301159 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1158 10:05:28.327412 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1159 10:05:28.349550 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1160 10:05:28.373040 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1161 10:05:28.397313 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1162 10:05:28.420729 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1163 10:05:28.442794 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1164 10:05:28.547811 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1165 10:05:28.572017 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1166 10:05:28.600391 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1167 10:05:28.625332 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1168 10:05:28.725875 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1169 10:05:28.804280 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1170 10:05:28.871753 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1171 10:05:28.944076 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1172 10:05:29.018026 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1173 10:05:29.094567 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1174 10:05:29.166701 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1175 10:05:29.237627 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1176 10:05:29.306653 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1177 10:05:29.385683 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1178 10:05:29.452559 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1179 10:05:29.524547 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1180 10:05:29.594653 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1181 10:05:29.670005 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1182 10:05:29.741313 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1183 10:05:29.818089 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1184 10:05:29.835206 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1185 10:05:29.905279 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1186 10:05:29.974007 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1187 10:05:30.046777 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1188 10:05:30.068592 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1189 10:05:30.143790 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1190 10:05:30.164150 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1191 10:05:30.233503 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1192 10:05:30.255995 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1193 10:05:30.280127 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1194 10:05:30.302588 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1195 10:05:30.327457 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1196 10:05:30.349567 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1197 10:05:30.374785 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1198 10:05:30.404402 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1199 10:05:30.478330 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1200 10:05:30.503622 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1201 10:05:30.520246 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1202 10:05:30.591686 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1203 10:05:30.662751 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1204 10:05:30.683790 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1205 10:05:30.784113 # not ok 144 /ocp/interconnect@47c00000
1206 10:05:30.854659 # not ok 145 /ocp/interconnect@47c00000/segment@0
1207 10:05:30.879436 # ok 146 /ocp/interconnect@48000000
1208 10:05:30.902279 # ok 147 /ocp/interconnect@48000000/segment@0
1209 10:05:30.927418 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1210 10:05:30.947122 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1211 10:05:30.970996 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1212 10:05:30.994522 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1213 10:05:31.017930 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1214 10:05:31.044828 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1215 10:05:31.070158 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1216 10:05:31.143033 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1217 10:05:31.215348 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1218 10:05:31.232674 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1219 10:05:31.256988 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1220 10:05:31.278293 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1221 10:05:31.304750 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1222 10:05:31.325617 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1223 10:05:31.349663 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1224 10:05:31.371931 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1225 10:05:31.400654 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1226 10:05:31.423146 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1227 10:05:31.444588 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1228 10:05:31.470233 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1229 10:05:31.493451 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1230 10:05:31.518887 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1231 10:05:31.536533 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1232 10:05:31.560048 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1233 10:05:31.585677 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1234 10:05:31.607831 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1235 10:05:31.631971 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1236 10:05:31.656054 # ok 175 /ocp/interconnect@48000000/segment@100000
1237 10:05:31.678014 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1238 10:05:31.704086 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1239 10:05:31.774112 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1240 10:05:31.846984 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1241 10:05:31.915912 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1242 10:05:31.988362 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1243 10:05:32.057683 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1244 10:05:32.130703 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1245 10:05:32.199291 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1246 10:05:32.271436 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1247 10:05:32.291773 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1248 10:05:32.315460 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1249 10:05:32.343661 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1250 10:05:32.364327 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1251 10:05:32.386632 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1252 10:05:32.414491 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1253 10:05:32.434244 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1254 10:05:32.457377 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1255 10:05:32.479757 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1256 10:05:32.504324 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1257 10:05:32.526360 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1258 10:05:32.550477 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1259 10:05:32.569886 # ok 198 /ocp/interconnect@48000000/segment@200000
1260 10:05:32.599792 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1261 10:05:32.684960 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1262 10:05:32.702132 # ok 201 /ocp/interconnect@48000000/segment@300000
1263 10:05:32.726485 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1264 10:05:32.750188 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1265 10:05:32.773610 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1266 10:05:32.796811 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1267 10:05:32.820281 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1268 10:05:32.843687 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1269 10:05:32.918963 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1270 10:05:32.938464 # ok 209 /ocp/interconnect@4a000000
1271 10:05:32.962139 # ok 210 /ocp/interconnect@4a000000/segment@0
1272 10:05:32.982469 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1273 10:05:33.011005 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1274 10:05:33.035478 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1275 10:05:33.061071 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1276 10:05:33.133535 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1277 10:05:33.235244 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1278 10:05:33.307416 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1279 10:05:33.405508 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1280 10:05:33.479937 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1281 10:05:33.548377 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1282 10:05:33.646263 # not ok 221 /ocp/interconnect@4b140000
1283 10:05:33.721460 # not ok 222 /ocp/interconnect@4b140000/segment@0
1284 10:05:33.792581 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1285 10:05:33.808864 # ok 224 /ocp/target-module@40300000
1286 10:05:33.833290 # ok 225 /ocp/target-module@40300000/sram@0
1287 10:05:33.910058 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1288 10:05:33.981337 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1289 10:05:34.001379 # ok 228 /ocp/target-module@47400000
1290 10:05:34.020571 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1291 10:05:34.043816 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1292 10:05:34.070406 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1293 10:05:34.092273 # ok 232 /ocp/target-module@47400000/usb@1400
1294 10:05:34.111309 # ok 233 /ocp/target-module@47400000/usb@1800
1295 10:05:34.136087 # ok 234 /ocp/target-module@47810000
1296 10:05:34.159988 # ok 235 /ocp/target-module@49000000
1297 10:05:34.181877 # ok 236 /ocp/target-module@49000000/dma@0
1298 10:05:34.205370 # ok 237 /ocp/target-module@49800000
1299 10:05:34.224393 # ok 238 /ocp/target-module@49800000/dma@0
1300 10:05:34.249683 # ok 239 /ocp/target-module@49900000
1301 10:05:34.270844 # ok 240 /ocp/target-module@49900000/dma@0
1302 10:05:34.290281 # ok 241 /ocp/target-module@49a00000
1303 10:05:34.313777 # ok 242 /ocp/target-module@49a00000/dma@0
1304 10:05:34.339061 # ok 243 /ocp/target-module@4c000000
1305 10:05:34.410662 # not ok 244 /ocp/target-module@4c000000/emif@0
1306 10:05:34.427677 # ok 245 /ocp/target-module@50000000
1307 10:05:34.451385 # ok 246 /ocp/target-module@53100000
1308 10:05:34.521333 # not ok 247 /ocp/target-module@53100000/sham@0
1309 10:05:34.547362 # ok 248 /ocp/target-module@53500000
1310 10:05:34.618038 # not ok 249 /ocp/target-module@53500000/aes@0
1311 10:05:34.639978 # ok 250 /ocp/target-module@56000000
1312 10:05:34.738863 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1313 10:05:34.810474 # ok 252 /opp-table # SKIP
1314 10:05:34.879928 # ok 253 /soc # SKIP
1315 10:05:34.900949 # ok 254 /sound
1316 10:05:34.928141 # ok 255 /target-module@4b000000
1317 10:05:34.952782 # ok 256 /target-module@4b000000/target-module@140000
1318 10:05:34.969783 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1319 10:05:34.978286 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1320 10:05:34.986085 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1321 10:05:37.230867 dt_test_unprobed_devices_sh_ skip
1322 10:05:37.236331 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1323 10:05:37.241948 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1324 10:05:37.242251 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1325 10:05:37.250971 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1326 10:05:37.251284 dt_test_unprobed_devices_sh_fixedregulator0 pass
1327 10:05:37.256486 dt_test_unprobed_devices_sh_leds pass
1328 10:05:37.262178 dt_test_unprobed_devices_sh_ocp pass
1329 10:05:37.265551 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1330 10:05:37.270959 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1331 10:05:37.276499 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1332 10:05:37.285917 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1333 10:05:37.291506 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1334 10:05:37.302667 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1335 10:05:37.308185 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1336 10:05:37.319423 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1337 10:05:37.324995 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1338 10:05:37.336203 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1339 10:05:37.347410 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1340 10:05:37.358667 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1341 10:05:37.364297 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1342 10:05:37.375456 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1343 10:05:37.386700 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1344 10:05:37.398015 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1345 10:05:37.409110 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1346 10:05:37.414713 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1347 10:05:37.425935 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1348 10:05:37.437081 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1349 10:05:37.448275 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1350 10:05:37.453931 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1351 10:05:37.465075 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1352 10:05:37.476224 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1353 10:05:37.487483 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1354 10:05:37.493062 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1355 10:05:37.504275 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1356 10:05:37.515469 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1357 10:05:37.526627 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1358 10:05:37.537874 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1359 10:05:37.548999 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1360 10:05:37.554609 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1361 10:05:37.565787 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1362 10:05:37.576991 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1363 10:05:37.588246 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1364 10:05:37.599466 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1365 10:05:37.610555 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1366 10:05:37.621740 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1367 10:05:37.632908 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1368 10:05:37.644120 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1369 10:05:37.655336 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1370 10:05:37.667051 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1371 10:05:37.677788 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1372 10:05:37.688929 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1373 10:05:37.700174 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1374 10:05:37.711272 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1375 10:05:37.722556 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1376 10:05:37.733879 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1377 10:05:37.744951 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1378 10:05:37.756106 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1379 10:05:37.767443 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1380 10:05:37.778580 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1381 10:05:37.789711 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1382 10:05:37.801374 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1383 10:05:37.812067 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1384 10:05:37.823203 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1385 10:05:37.834495 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1386 10:05:37.840012 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1387 10:05:37.856740 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1388 10:05:37.862425 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1389 10:05:37.873608 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1390 10:05:37.884834 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1391 10:05:37.895947 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1392 10:05:37.907211 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1393 10:05:37.918401 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1394 10:05:37.929581 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1395 10:05:37.940733 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1396 10:05:37.951932 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1397 10:05:37.963133 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1398 10:05:37.974345 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1399 10:05:37.985595 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1400 10:05:37.996665 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1401 10:05:38.007848 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1402 10:05:38.019097 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1403 10:05:38.030308 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1404 10:05:38.035874 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1405 10:05:38.047074 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1406 10:05:38.058209 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1407 10:05:38.069587 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1408 10:05:38.080603 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1409 10:05:38.091823 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1410 10:05:38.102996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1411 10:05:38.114206 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1412 10:05:38.125374 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1413 10:05:38.136631 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1414 10:05:38.147742 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1415 10:05:38.158996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1416 10:05:38.164611 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1417 10:05:38.175691 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1418 10:05:38.186989 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1419 10:05:38.192622 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1420 10:05:38.203719 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1421 10:05:38.214884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1422 10:05:38.220587 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1423 10:05:38.231724 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1424 10:05:38.237406 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1425 10:05:38.248604 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1426 10:05:38.259645 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1427 10:05:38.270864 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1428 10:05:38.282049 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1429 10:05:38.293235 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1430 10:05:38.304441 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1431 10:05:38.315653 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1432 10:05:38.326823 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1433 10:05:38.338071 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1434 10:05:38.354810 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1435 10:05:38.366041 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1436 10:05:38.377158 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1437 10:05:38.388364 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1438 10:05:38.399631 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1439 10:05:38.410778 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1440 10:05:38.427622 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1441 10:05:38.438702 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1442 10:05:38.449920 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1443 10:05:38.461112 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1444 10:05:38.472378 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1445 10:05:38.483497 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1446 10:05:38.489078 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1447 10:05:38.500291 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1448 10:05:38.505908 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1449 10:05:38.517182 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1450 10:05:38.522716 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1451 10:05:38.534020 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1452 10:05:38.539508 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1453 10:05:38.550649 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1454 10:05:38.556235 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1455 10:05:38.567496 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1456 10:05:38.578729 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1457 10:05:38.584259 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1458 10:05:38.595467 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1459 10:05:38.606670 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1460 10:05:38.617776 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1461 10:05:38.628942 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1462 10:05:38.640181 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1463 10:05:38.645829 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1464 10:05:38.651441 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1465 10:05:38.656962 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1466 10:05:38.662680 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1467 10:05:38.668143 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1468 10:05:38.673733 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1469 10:05:38.684919 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1470 10:05:38.690703 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1471 10:05:38.701915 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1472 10:05:38.707329 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1473 10:05:38.718525 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1474 10:05:38.724083 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1475 10:05:38.729738 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1476 10:05:38.740864 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1477 10:05:38.746558 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1478 10:05:38.757653 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1479 10:05:38.763270 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1480 10:05:38.774448 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1481 10:05:38.780019 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1482 10:05:38.791859 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1483 10:05:38.797125 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1484 10:05:38.808235 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1485 10:05:38.813758 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1486 10:05:38.825136 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1487 10:05:38.830587 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1488 10:05:38.842199 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1489 10:05:38.847536 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1490 10:05:38.854141 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1491 10:05:38.864026 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1492 10:05:38.869712 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1493 10:05:38.880825 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1494 10:05:38.886502 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1495 10:05:38.897582 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1496 10:05:38.903113 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1497 10:05:38.914225 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1498 10:05:38.919920 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1499 10:05:38.936686 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1500 10:05:38.942314 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1501 10:05:38.953466 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1502 10:05:38.964688 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1503 10:05:38.975857 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1504 10:05:38.987066 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1505 10:05:38.998205 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1506 10:05:39.009404 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1507 10:05:39.015038 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1508 10:05:39.026256 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1509 10:05:39.031837 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1510 10:05:39.042980 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1511 10:05:39.048703 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1512 10:05:39.059800 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1513 10:05:39.065418 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1514 10:05:39.076660 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1515 10:05:39.082203 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1516 10:05:39.093427 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1517 10:05:39.098976 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1518 10:05:39.104703 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1519 10:05:39.115721 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1520 10:05:39.121327 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1521 10:05:39.126969 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1522 10:05:39.138143 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1523 10:05:39.143759 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1524 10:05:39.154889 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1525 10:05:39.160529 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1526 10:05:39.171687 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1527 10:05:39.177281 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1528 10:05:39.188495 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1529 10:05:39.194120 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1530 10:05:39.199719 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1531 10:05:39.205280 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1532 10:05:39.216430 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1533 10:05:39.227716 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1534 10:05:39.233236 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1535 10:05:39.244488 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1536 10:05:39.250107 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1537 10:05:39.261260 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1538 10:05:39.272469 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1539 10:05:39.283709 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1540 10:05:39.289198 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1541 10:05:39.294874 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1542 10:05:39.306103 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1543 10:05:39.311728 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1544 10:05:39.317339 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1545 10:05:39.323025 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1546 10:05:39.328583 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1547 10:05:39.334166 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1548 10:05:39.339820 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1549 10:05:39.345400 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1550 10:05:39.356584 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1551 10:05:39.362215 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1552 10:05:39.367862 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1553 10:05:39.373449 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1554 10:05:39.379018 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1555 10:05:39.384616 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1556 10:05:39.390217 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1557 10:05:39.395852 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1558 10:05:39.401434 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1559 10:05:39.407055 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1560 10:05:39.412633 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1561 10:05:39.418215 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1562 10:05:39.423898 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1563 10:05:39.429495 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1564 10:05:39.435100 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1565 10:05:39.440830 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1566 10:05:39.446252 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1567 10:05:39.451849 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1568 10:05:39.457486 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1569 10:05:39.463150 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1570 10:05:39.468688 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1571 10:05:39.474260 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1572 10:05:39.479888 dt_test_unprobed_devices_sh_opp-table skip
1573 10:05:39.480564 dt_test_unprobed_devices_sh_soc skip
1574 10:05:39.485468 dt_test_unprobed_devices_sh_sound pass
1575 10:05:39.491077 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1576 10:05:39.496707 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1577 10:05:39.502311 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1578 10:05:39.507882 dt_test_unprobed_devices_sh fail
1579 10:05:39.513477 + ../../utils/send-to-lava.sh ./output/result.txt
1580 10:05:39.514681 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1582 10:05:39.521469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1583 10:05:39.526028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1584 10:05:39.527077 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1586 10:05:39.616952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1587 10:05:39.618005 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1589 10:05:39.709936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1590 10:05:39.710764 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1592 10:05:39.799205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1593 10:05:39.800038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1595 10:05:39.890400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1596 10:05:39.891246 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1598 10:05:39.983044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1599 10:05:39.983891 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1601 10:05:40.084451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1602 10:05:40.085302 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1604 10:05:40.185975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1605 10:05:40.186767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1607 10:05:40.280075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1608 10:05:40.280965 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1610 10:05:40.376314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1611 10:05:40.377194 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1613 10:05:40.470268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1614 10:05:40.471507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1616 10:05:40.561155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1617 10:05:40.562024 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1619 10:05:40.653229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1620 10:05:40.654110 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1622 10:05:40.739961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1623 10:05:40.740820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1625 10:05:40.835211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1626 10:05:40.836231 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1628 10:05:40.928037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1629 10:05:40.928901 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1631 10:05:41.020914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1632 10:05:41.021758 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1634 10:05:41.120249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1635 10:05:41.121152 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1637 10:05:41.212644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1638 10:05:41.213941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1640 10:05:41.305452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1641 10:05:41.306558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1643 10:05:41.395983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1644 10:05:41.397111 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1646 10:05:41.489637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1647 10:05:41.490627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1649 10:05:41.583059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1650 10:05:41.584142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1652 10:05:41.674123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1653 10:05:41.675256 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1655 10:05:41.770431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1656 10:05:41.771634 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1658 10:05:41.865408 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1659 10:05:41.866340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1661 10:05:41.956069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1662 10:05:41.956913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1664 10:05:42.048911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1665 10:05:42.049746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1667 10:05:42.143102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1668 10:05:42.143921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1670 10:05:42.234289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1671 10:05:42.235088 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1673 10:05:42.325508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1674 10:05:42.326381 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1676 10:05:42.418066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1677 10:05:42.418909 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1679 10:05:42.511291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1680 10:05:42.512133 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1682 10:05:42.603501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1683 10:05:42.604331 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1685 10:05:42.695354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1686 10:05:42.696199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1688 10:05:42.785940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1689 10:05:42.786783 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1691 10:05:42.879538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1692 10:05:42.880336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1694 10:05:42.972514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1695 10:05:42.973352 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1697 10:05:43.064800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1698 10:05:43.065680 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1700 10:05:43.157328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1701 10:05:43.158225 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1703 10:05:43.282760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1704 10:05:43.283700 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1706 10:05:43.389187 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1707 10:05:43.390198 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1709 10:05:43.501362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1710 10:05:43.503814 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1712 10:05:43.623269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1713 10:05:43.624235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1715 10:05:43.746832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1716 10:05:43.747494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1718 10:05:43.850550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1719 10:05:43.851210 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1721 10:05:43.942411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1722 10:05:43.943048 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1724 10:05:44.035582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1725 10:05:44.036206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1727 10:05:44.126762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1728 10:05:44.127386 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1730 10:05:44.216754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1731 10:05:44.217376 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1733 10:05:44.307811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1734 10:05:44.308443 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1736 10:05:44.400503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1737 10:05:44.401150 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1739 10:05:44.492266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1740 10:05:44.492911 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1742 10:05:44.584424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1743 10:05:44.585042 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1745 10:05:44.675160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1746 10:05:44.675843 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1748 10:05:44.765915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1749 10:05:44.766562 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1751 10:05:44.856653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1752 10:05:44.857286 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1754 10:05:44.947682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1755 10:05:44.948311 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1757 10:05:45.049620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1758 10:05:45.050271 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1760 10:05:45.150432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1761 10:05:45.151066 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1763 10:05:45.244446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1764 10:05:45.245078 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1766 10:05:45.335541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1767 10:05:45.336469 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1769 10:05:45.427571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1770 10:05:45.428621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1772 10:05:45.520755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1773 10:05:45.521694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1775 10:05:45.612142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1776 10:05:45.613032 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1778 10:05:45.704373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1779 10:05:45.705235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1781 10:05:45.795598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1782 10:05:45.796438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1784 10:05:45.886082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1785 10:05:45.886923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1787 10:05:45.976531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1788 10:05:45.977390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1790 10:05:46.069641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1791 10:05:46.070530 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1793 10:05:46.162378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1794 10:05:46.163251 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1796 10:05:46.253281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1797 10:05:46.254235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1799 10:05:46.343012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1800 10:05:46.343847 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1802 10:05:46.435067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1803 10:05:46.435907 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1805 10:05:46.526380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1806 10:05:46.527001 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1808 10:05:46.618358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1809 10:05:46.619292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1811 10:05:46.710201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1812 10:05:46.711065 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1814 10:05:46.803097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1815 10:05:46.803961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1817 10:05:46.896247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1818 10:05:46.897104 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1820 10:05:46.989077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1821 10:05:46.989911 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1823 10:05:47.083234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1824 10:05:47.084072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1826 10:05:47.176118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1827 10:05:47.176971 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1829 10:05:47.266147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1830 10:05:47.266993 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1832 10:05:47.359480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1833 10:05:47.360384 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1835 10:05:47.452140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1836 10:05:47.452967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1838 10:05:47.544362 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1839 10:05:47.545260 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1841 10:05:47.644970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1842 10:05:47.645872 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1844 10:05:47.746239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1845 10:05:47.747072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1847 10:05:48.054425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1848 10:05:48.055299 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1850 10:05:48.056767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1851 10:05:48.057347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1852 10:05:48.058159 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1854 10:05:48.059571 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1856 10:05:48.137141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1857 10:05:48.137988 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1859 10:05:48.227815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1860 10:05:48.228651 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1862 10:05:48.320325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1863 10:05:48.321136 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1865 10:05:48.409917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1866 10:05:48.410766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1868 10:05:48.501318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1869 10:05:48.502179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1871 10:05:48.593857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1872 10:05:48.594647 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1874 10:05:48.684467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1875 10:05:48.685279 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1877 10:05:48.778174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1878 10:05:48.778985 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1880 10:05:48.870336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1881 10:05:48.871141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1883 10:05:48.964178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1884 10:05:48.964968 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1886 10:05:49.054650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1887 10:05:49.055495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1889 10:05:49.147789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1890 10:05:49.148611 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1892 10:05:49.250894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1893 10:05:49.251699 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1895 10:05:49.342634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1896 10:05:49.343449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1898 10:05:49.434811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1899 10:05:49.435606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1901 10:05:49.524320 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1902 10:05:49.525117 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1904 10:05:49.617703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1905 10:05:49.618537 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1907 10:05:49.709068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1908 10:05:49.709921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1910 10:05:49.804239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1911 10:05:49.805069 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1913 10:05:49.905918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1914 10:05:49.906756 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1916 10:05:50.007479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1917 10:05:50.008305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1919 10:05:50.101925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1920 10:05:50.102738 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1922 10:05:50.203497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1923 10:05:50.204305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1925 10:05:50.304783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1926 10:05:50.305573 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1928 10:05:50.406638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1929 10:05:50.407433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1931 10:05:50.507908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1932 10:05:50.508697 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1934 10:05:50.598106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1935 10:05:50.598916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1937 10:05:50.690640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1938 10:05:50.691437 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1940 10:05:50.790572 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1942 10:05:50.792910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1943 10:05:50.892361 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1945 10:05:50.895673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1946 10:05:50.994487 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1948 10:05:50.997744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1949 10:05:51.090062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1950 10:05:51.090864 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1952 10:05:51.182569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1953 10:05:51.183373 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1955 10:05:51.272155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1956 10:05:51.272951 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1958 10:05:51.364655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1959 10:05:51.365458 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1961 10:05:51.457443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1962 10:05:51.458285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1964 10:05:51.551440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1965 10:05:51.552267 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1967 10:05:51.643129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1968 10:05:51.643958 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1970 10:05:51.735787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1971 10:05:51.736600 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1973 10:05:51.828214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1974 10:05:51.829045 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1976 10:05:51.921658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1977 10:05:51.922507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1979 10:05:52.022669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1980 10:05:52.023502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1982 10:05:52.116229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1983 10:05:52.117069 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1985 10:05:52.212346 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1986 10:05:52.213208 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1988 10:05:52.305102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1989 10:05:52.305974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1991 10:05:52.408490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1992 10:05:52.409402 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1994 10:05:52.505925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
1995 10:05:52.506779 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
1997 10:05:52.595721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
1998 10:05:52.596635 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2000 10:05:52.689005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2001 10:05:52.689922 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2003 10:05:52.782868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2004 10:05:52.783745 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2006 10:05:52.875575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2007 10:05:52.876413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2009 10:05:52.966122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2010 10:05:52.966972 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2012 10:05:53.057957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2013 10:05:53.058766 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2015 10:05:53.159921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2016 10:05:53.160749 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2018 10:05:53.251946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2019 10:05:53.252767 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2021 10:05:53.344687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2022 10:05:53.345488 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2024 10:05:53.440902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2025 10:05:53.441712 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2027 10:05:53.532878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2028 10:05:53.533713 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2030 10:05:53.625333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2031 10:05:53.626216 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2033 10:05:53.720096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2034 10:05:53.720923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2036 10:05:53.812434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2037 10:05:53.813252 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2039 10:05:53.904598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2040 10:05:53.905408 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2042 10:05:53.996382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2043 10:05:53.997195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2045 10:05:54.089047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2046 10:05:54.089914 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2048 10:05:54.212682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2049 10:05:54.213641 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2051 10:05:54.321927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2052 10:05:54.322842 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2054 10:05:54.414053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2055 10:05:54.414918 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2057 10:05:54.506037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2058 10:05:54.506921 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2060 10:05:54.600296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2061 10:05:54.601161 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2063 10:05:54.692627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2064 10:05:54.693477 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2066 10:05:54.784671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2067 10:05:54.785539 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2069 10:05:54.876962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2070 10:05:54.877866 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2072 10:05:54.970953 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2073 10:05:54.971820 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2075 10:05:55.063550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2076 10:05:55.064445 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2078 10:05:55.155215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2079 10:05:55.156109 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2081 10:05:55.247584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2082 10:05:55.248449 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2084 10:05:55.340641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2085 10:05:55.341556 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2087 10:05:55.443459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2088 10:05:55.444373 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2090 10:05:55.531363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2091 10:05:55.532269 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2093 10:05:55.622193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2094 10:05:55.623002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2096 10:05:55.715327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2097 10:05:55.716132 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2099 10:05:55.807551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2100 10:05:55.808360 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2102 10:05:55.901483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2103 10:05:55.902393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2105 10:05:55.991738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2106 10:05:55.992551 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2108 10:05:56.086932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2109 10:05:56.087746 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2111 10:05:56.181061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2112 10:05:56.181931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2114 10:05:56.419472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2115 10:05:56.420333 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2117 10:05:56.524807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2118 10:05:56.525724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2120 10:05:56.660472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2121 10:05:56.661369 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2123 10:05:56.765374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2124 10:05:56.766331 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2126 10:05:56.862645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2127 10:05:56.863538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2129 10:05:56.956524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2130 10:05:56.957451 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2132 10:05:57.045144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2133 10:05:57.046071 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2135 10:05:57.138110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2136 10:05:57.139020 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2138 10:05:57.227483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2139 10:05:57.228396 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2141 10:05:57.320357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2142 10:05:57.321316 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2144 10:05:57.412592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2145 10:05:57.413512 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2147 10:05:57.509051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2148 10:05:57.510849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2150 10:05:57.646473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2151 10:05:57.647433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2153 10:05:57.746101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2154 10:05:57.747014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2156 10:05:57.837715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2157 10:05:57.838612 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2159 10:05:57.940328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2160 10:05:57.941179 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2162 10:05:58.032736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2163 10:05:58.033573 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2165 10:05:58.123478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2166 10:05:58.124306 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2168 10:05:58.209709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2169 10:05:58.210576 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2171 10:05:58.302033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2172 10:05:58.302823 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2174 10:05:58.391683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2175 10:05:58.392518 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2177 10:05:58.484853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2178 10:05:58.485695 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2180 10:05:58.576757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2181 10:05:58.577614 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2183 10:05:58.666917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2184 10:05:58.667794 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2186 10:05:58.761428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2187 10:05:58.762304 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2189 10:05:58.853511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2190 10:05:58.854400 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2192 10:05:58.947776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2193 10:05:58.948640 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2195 10:05:59.042562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2196 10:05:59.043442 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2198 10:05:59.135996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2199 10:05:59.136929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2201 10:05:59.228709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2202 10:05:59.229593 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2204 10:05:59.321683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2205 10:05:59.322549 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2207 10:05:59.408190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2208 10:05:59.408995 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2210 10:05:59.499783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2211 10:05:59.500580 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2213 10:05:59.595073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2214 10:05:59.595911 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2216 10:05:59.689624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2217 10:05:59.690454 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2219 10:05:59.782667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2220 10:05:59.783466 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2222 10:05:59.866869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2223 10:05:59.867667 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2225 10:05:59.961035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2226 10:05:59.961933 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2228 10:06:00.053117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2229 10:06:00.054009 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2231 10:06:00.141409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2232 10:06:00.142319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2234 10:06:00.233293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2235 10:06:00.234213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2237 10:06:00.324731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2238 10:06:00.325650 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2240 10:06:00.417414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2241 10:06:00.418393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2243 10:06:00.507060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2244 10:06:00.507946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2246 10:06:00.600102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2247 10:06:00.600748 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2249 10:06:00.691513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2250 10:06:00.692390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2252 10:06:00.782081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2253 10:06:00.782974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2255 10:06:00.879779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2256 10:06:00.880643 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2258 10:06:00.983194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2259 10:06:00.984096 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2261 10:06:01.077275 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2263 10:06:01.080445 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2264 10:06:01.178146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2265 10:06:01.179041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2267 10:06:01.274894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2268 10:06:01.275800 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2270 10:06:01.369172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2271 10:06:01.370203 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2273 10:06:01.464887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2274 10:06:01.465834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2276 10:06:01.557956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2277 10:06:01.558881 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2279 10:06:01.674412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2280 10:06:01.675094 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2282 10:06:01.781425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2283 10:06:01.782129 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2285 10:06:01.878855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2286 10:06:01.879719 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2288 10:06:01.974612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2289 10:06:01.975240 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2291 10:06:02.076182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2292 10:06:02.077064 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2294 10:06:02.168384 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2295 10:06:02.169262 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2297 10:06:02.260544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2298 10:06:02.261515 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2300 10:06:02.365324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2301 10:06:02.366690 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2303 10:06:02.460000 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2304 10:06:02.460798 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2306 10:06:02.551942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2307 10:06:02.552580 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2309 10:06:02.646671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2310 10:06:02.647502 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2312 10:06:02.743621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2313 10:06:02.744444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2315 10:06:02.845691 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2316 10:06:02.846517 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2318 10:06:02.942578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2319 10:06:02.943191 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2321 10:06:03.035643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2322 10:06:03.036274 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2324 10:06:03.129903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2325 10:06:03.130711 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2327 10:06:03.221782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2328 10:06:03.222475 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2330 10:06:03.312354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2331 10:06:03.313284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2333 10:06:03.406146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2334 10:06:03.407121 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2336 10:06:03.496289 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2337 10:06:03.497157 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2339 10:06:03.588126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2340 10:06:03.589028 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2342 10:06:03.682608 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2343 10:06:03.683528 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2345 10:06:03.775230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2346 10:06:03.776096 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2348 10:06:03.870033 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2349 10:06:03.870885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2351 10:06:03.971315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2352 10:06:03.972163 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2354 10:06:04.069492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2355 10:06:04.070137 + set +x
2356 10:06:04.070855 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2358 10:06:04.073796 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 927468_1.6.2.4.5>
2359 10:06:04.074604 Received signal: <ENDRUN> 1_kselftest-dt 927468_1.6.2.4.5
2360 10:06:04.075098 Ending use of test pattern.
2361 10:06:04.075535 Ending test lava.1_kselftest-dt (927468_1.6.2.4.5), duration 86.72
2363 10:06:04.081083 <LAVA_TEST_RUNNER EXIT>
2364 10:06:04.081880 ok: lava_test_shell seems to have completed
2365 10:06:04.096117 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2366 10:06:04.098263 end: 3.1 lava-test-shell (duration 00:01:28) [common]
2367 10:06:04.098869 end: 3 lava-test-retry (duration 00:01:28) [common]
2368 10:06:04.099457 start: 4 finalize (timeout 00:05:27) [common]
2369 10:06:04.100049 start: 4.1 power-off (timeout 00:00:30) [common]
2370 10:06:04.101130 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-05'
2371 10:06:04.135804 >> OK - accepted request
2372 10:06:04.137921 Returned 0 in 0 seconds
2373 10:06:04.239195 end: 4.1 power-off (duration 00:00:00) [common]
2375 10:06:04.240971 start: 4.2 read-feedback (timeout 00:05:27) [common]
2376 10:06:04.242257 Listened to connection for namespace 'common' for up to 1s
2377 10:06:04.243195 Listened to connection for namespace 'common' for up to 1s
2378 10:06:05.241988 Finalising connection for namespace 'common'
2379 10:06:05.242462 Disconnecting from shell: Finalise
2380 10:06:05.242769 / #
2381 10:06:05.343580 end: 4.2 read-feedback (duration 00:00:01) [common]
2382 10:06:05.344414 end: 4 finalize (duration 00:00:01) [common]
2383 10:06:05.345135 Cleaning after the job
2384 10:06:05.345798 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927468/tftp-deploy-ucj6ozrr/ramdisk
2385 10:06:05.348691 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927468/tftp-deploy-ucj6ozrr/kernel
2386 10:06:05.355843 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927468/tftp-deploy-ucj6ozrr/dtb
2387 10:06:05.357258 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927468/tftp-deploy-ucj6ozrr/nfsrootfs
2388 10:06:05.417752 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927468/tftp-deploy-ucj6ozrr/modules
2389 10:06:05.421755 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/927468
2390 10:06:08.644680 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/927468
2391 10:06:08.645221 Job finished correctly