Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 10:33:40.906737 lava-dispatcher, installed at version: 2024.01
2 10:33:40.907489 start: 0 validate
3 10:33:40.907967 Start time: 2024-11-02 10:33:40.907938+00:00 (UTC)
4 10:33:40.908546 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 10:33:40.909085 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 10:33:40.953400 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 10:33:40.953952 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc5-608-g0c049b492970f%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 10:33:40.981236 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 10:33:40.981883 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc5-608-g0c049b492970f%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 10:33:41.014291 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 10:33:41.014740 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc5-608-g0c049b492970f%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 10:33:41.052168 validate duration: 0.14
14 10:33:41.053026 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 10:33:41.053366 start: 1.1 download-retry (timeout 00:10:00) [common]
16 10:33:41.053682 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 10:33:41.054292 Not decompressing ramdisk as can be used compressed.
18 10:33:41.054745 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 10:33:41.055036 saving as /var/lib/lava/dispatcher/tmp/927571/tftp-deploy-mc63zsv0/ramdisk/rootfs.cpio.gz
20 10:33:41.055325 total size: 47897469 (45 MB)
21 10:33:41.093488 progress 0 % (0 MB)
22 10:33:41.124530 progress 5 % (2 MB)
23 10:33:41.155461 progress 10 % (4 MB)
24 10:33:41.187132 progress 15 % (6 MB)
25 10:33:41.218957 progress 20 % (9 MB)
26 10:33:41.250263 progress 25 % (11 MB)
27 10:33:41.281627 progress 30 % (13 MB)
28 10:33:41.313051 progress 35 % (16 MB)
29 10:33:41.344641 progress 40 % (18 MB)
30 10:33:41.375949 progress 45 % (20 MB)
31 10:33:41.407437 progress 50 % (22 MB)
32 10:33:41.438917 progress 55 % (25 MB)
33 10:33:41.470660 progress 60 % (27 MB)
34 10:33:41.502037 progress 65 % (29 MB)
35 10:33:41.533377 progress 70 % (32 MB)
36 10:33:41.564851 progress 75 % (34 MB)
37 10:33:41.596301 progress 80 % (36 MB)
38 10:33:41.627555 progress 85 % (38 MB)
39 10:33:41.659077 progress 90 % (41 MB)
40 10:33:41.690299 progress 95 % (43 MB)
41 10:33:41.721066 progress 100 % (45 MB)
42 10:33:41.721793 45 MB downloaded in 0.67 s (68.54 MB/s)
43 10:33:41.722364 end: 1.1.1 http-download (duration 00:00:01) [common]
45 10:33:41.723264 end: 1.1 download-retry (duration 00:00:01) [common]
46 10:33:41.723560 start: 1.2 download-retry (timeout 00:09:59) [common]
47 10:33:41.723835 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 10:33:41.724335 downloading http://storage.kernelci.org/tip/master/v6.12-rc5-608-g0c049b492970f/arm64/defconfig/gcc-12/kernel/Image
49 10:33:41.724591 saving as /var/lib/lava/dispatcher/tmp/927571/tftp-deploy-mc63zsv0/kernel/Image
50 10:33:41.724802 total size: 45713920 (43 MB)
51 10:33:41.725014 No compression specified
52 10:33:41.767173 progress 0 % (0 MB)
53 10:33:41.795349 progress 5 % (2 MB)
54 10:33:41.823292 progress 10 % (4 MB)
55 10:33:41.851291 progress 15 % (6 MB)
56 10:33:41.879134 progress 20 % (8 MB)
57 10:33:41.907096 progress 25 % (10 MB)
58 10:33:41.935020 progress 30 % (13 MB)
59 10:33:41.963102 progress 35 % (15 MB)
60 10:33:41.991165 progress 40 % (17 MB)
61 10:33:42.019034 progress 45 % (19 MB)
62 10:33:42.046953 progress 50 % (21 MB)
63 10:33:42.075019 progress 55 % (24 MB)
64 10:33:42.103376 progress 60 % (26 MB)
65 10:33:42.130928 progress 65 % (28 MB)
66 10:33:42.158980 progress 70 % (30 MB)
67 10:33:42.187002 progress 75 % (32 MB)
68 10:33:42.215407 progress 80 % (34 MB)
69 10:33:42.242975 progress 85 % (37 MB)
70 10:33:42.270971 progress 90 % (39 MB)
71 10:33:42.298965 progress 95 % (41 MB)
72 10:33:42.326618 progress 100 % (43 MB)
73 10:33:42.327118 43 MB downloaded in 0.60 s (72.38 MB/s)
74 10:33:42.327607 end: 1.2.1 http-download (duration 00:00:01) [common]
76 10:33:42.328468 end: 1.2 download-retry (duration 00:00:01) [common]
77 10:33:42.328746 start: 1.3 download-retry (timeout 00:09:59) [common]
78 10:33:42.329015 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 10:33:42.329484 downloading http://storage.kernelci.org/tip/master/v6.12-rc5-608-g0c049b492970f/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 10:33:42.329765 saving as /var/lib/lava/dispatcher/tmp/927571/tftp-deploy-mc63zsv0/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 10:33:42.329977 total size: 53209 (0 MB)
82 10:33:42.330187 No compression specified
83 10:33:42.368253 progress 61 % (0 MB)
84 10:33:42.369093 progress 100 % (0 MB)
85 10:33:42.369626 0 MB downloaded in 0.04 s (1.28 MB/s)
86 10:33:42.370105 end: 1.3.1 http-download (duration 00:00:00) [common]
88 10:33:42.370930 end: 1.3 download-retry (duration 00:00:00) [common]
89 10:33:42.371195 start: 1.4 download-retry (timeout 00:09:59) [common]
90 10:33:42.371462 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 10:33:42.371912 downloading http://storage.kernelci.org/tip/master/v6.12-rc5-608-g0c049b492970f/arm64/defconfig/gcc-12/modules.tar.xz
92 10:33:42.372186 saving as /var/lib/lava/dispatcher/tmp/927571/tftp-deploy-mc63zsv0/modules/modules.tar
93 10:33:42.372393 total size: 11597080 (11 MB)
94 10:33:42.372605 Using unxz to decompress xz
95 10:33:42.414242 progress 0 % (0 MB)
96 10:33:42.483543 progress 5 % (0 MB)
97 10:33:42.557351 progress 10 % (1 MB)
98 10:33:42.636245 progress 15 % (1 MB)
99 10:33:42.712062 progress 20 % (2 MB)
100 10:33:42.788273 progress 25 % (2 MB)
101 10:33:42.868472 progress 30 % (3 MB)
102 10:33:42.939742 progress 35 % (3 MB)
103 10:33:43.017698 progress 40 % (4 MB)
104 10:33:43.103936 progress 45 % (5 MB)
105 10:33:43.179391 progress 50 % (5 MB)
106 10:33:43.262732 progress 55 % (6 MB)
107 10:33:43.343382 progress 60 % (6 MB)
108 10:33:43.427507 progress 65 % (7 MB)
109 10:33:43.503236 progress 70 % (7 MB)
110 10:33:43.583866 progress 75 % (8 MB)
111 10:33:43.664994 progress 80 % (8 MB)
112 10:33:43.739450 progress 85 % (9 MB)
113 10:33:43.810851 progress 90 % (9 MB)
114 10:33:43.908508 progress 95 % (10 MB)
115 10:33:43.999004 progress 100 % (11 MB)
116 10:33:44.013201 11 MB downloaded in 1.64 s (6.74 MB/s)
117 10:33:44.013812 end: 1.4.1 http-download (duration 00:00:02) [common]
119 10:33:44.014668 end: 1.4 download-retry (duration 00:00:02) [common]
120 10:33:44.014949 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 10:33:44.015223 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 10:33:44.015479 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 10:33:44.015741 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 10:33:44.016755 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj
125 10:33:44.017615 makedir: /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin
126 10:33:44.018265 makedir: /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/tests
127 10:33:44.018883 makedir: /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/results
128 10:33:44.019508 Creating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin/lava-add-keys
129 10:33:44.020503 Creating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin/lava-add-sources
130 10:33:44.021589 Creating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin/lava-background-process-start
131 10:33:44.022597 Creating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin/lava-background-process-stop
132 10:33:44.023603 Creating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin/lava-common-functions
133 10:33:44.024583 Creating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin/lava-echo-ipv4
134 10:33:44.025509 Creating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin/lava-install-packages
135 10:33:44.026412 Creating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin/lava-installed-packages
136 10:33:44.027450 Creating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin/lava-os-build
137 10:33:44.028419 Creating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin/lava-probe-channel
138 10:33:44.029343 Creating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin/lava-probe-ip
139 10:33:44.030249 Creating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin/lava-target-ip
140 10:33:44.031142 Creating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin/lava-target-mac
141 10:33:44.032067 Creating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin/lava-target-storage
142 10:33:44.033143 Creating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin/lava-test-case
143 10:33:44.034073 Creating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin/lava-test-event
144 10:33:44.034993 Creating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin/lava-test-feedback
145 10:33:44.035896 Creating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin/lava-test-raise
146 10:33:44.036846 Creating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin/lava-test-reference
147 10:33:44.037749 Creating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin/lava-test-runner
148 10:33:44.038818 Creating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin/lava-test-set
149 10:33:44.039766 Creating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin/lava-test-shell
150 10:33:44.040777 Updating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin/lava-install-packages (oe)
151 10:33:44.041771 Updating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/bin/lava-installed-packages (oe)
152 10:33:44.042610 Creating /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/environment
153 10:33:44.043338 LAVA metadata
154 10:33:44.044024 - LAVA_JOB_ID=927571
155 10:33:44.044488 - LAVA_DISPATCHER_IP=192.168.6.2
156 10:33:44.045151 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 10:33:44.046918 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 10:33:44.047541 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 10:33:44.047961 skipped lava-vland-overlay
160 10:33:44.048491 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 10:33:44.049011 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 10:33:44.049593 skipped lava-multinode-overlay
163 10:33:44.050106 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 10:33:44.050623 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 10:33:44.051108 Loading test definitions
166 10:33:44.051658 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 10:33:44.052113 Using /lava-927571 at stage 0
168 10:33:44.053298 uuid=927571_1.5.2.4.1 testdef=None
169 10:33:44.053645 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 10:33:44.053928 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 10:33:44.055801 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 10:33:44.056684 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 10:33:44.058881 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 10:33:44.059795 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 10:33:44.062061 runner path: /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/0/tests/0_igt-gpu-panfrost test_uuid 927571_1.5.2.4.1
178 10:33:44.062657 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 10:33:44.063518 Creating lava-test-runner.conf files
181 10:33:44.063734 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/927571/lava-overlay-uh6268jj/lava-927571/0 for stage 0
182 10:33:44.064105 - 0_igt-gpu-panfrost
183 10:33:44.064495 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 10:33:44.064796 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 10:33:44.088577 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 10:33:44.088989 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 10:33:44.089263 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 10:33:44.089534 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 10:33:44.089805 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 10:33:50.899190 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 10:33:50.900087 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 10:33:50.900575 extracting modules file /var/lib/lava/dispatcher/tmp/927571/tftp-deploy-mc63zsv0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/927571/extract-overlay-ramdisk-7ocbsfav/ramdisk
193 10:33:52.316184 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 10:33:52.316640 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
195 10:33:52.316930 [common] Applying overlay /var/lib/lava/dispatcher/tmp/927571/compress-overlay-6v7q6tv7/overlay-1.5.2.5.tar.gz to ramdisk
196 10:33:52.317150 [common] Applying overlay /var/lib/lava/dispatcher/tmp/927571/compress-overlay-6v7q6tv7/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/927571/extract-overlay-ramdisk-7ocbsfav/ramdisk
197 10:33:52.346886 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 10:33:52.347271 start: 1.5.6 prepare-kernel (timeout 00:09:49) [common]
199 10:33:52.347547 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:49) [common]
200 10:33:52.347777 Converting downloaded kernel to a uImage
201 10:33:52.348101 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/927571/tftp-deploy-mc63zsv0/kernel/Image /var/lib/lava/dispatcher/tmp/927571/tftp-deploy-mc63zsv0/kernel/uImage
202 10:33:52.801311 output: Image Name:
203 10:33:52.801711 output: Created: Sat Nov 2 10:33:52 2024
204 10:33:52.801925 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 10:33:52.802134 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 10:33:52.802340 output: Load Address: 01080000
207 10:33:52.802544 output: Entry Point: 01080000
208 10:33:52.802746 output:
209 10:33:52.803074 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 10:33:52.803343 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 10:33:52.803614 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 10:33:52.803869 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 10:33:52.804178 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 10:33:52.804440 Building ramdisk /var/lib/lava/dispatcher/tmp/927571/extract-overlay-ramdisk-7ocbsfav/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/927571/extract-overlay-ramdisk-7ocbsfav/ramdisk
215 10:33:59.478577 >> 502411 blocks
216 10:34:20.285680 Adding RAMdisk u-boot header.
217 10:34:20.286356 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/927571/extract-overlay-ramdisk-7ocbsfav/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/927571/extract-overlay-ramdisk-7ocbsfav/ramdisk.cpio.gz.uboot
218 10:34:20.969274 output: Image Name:
219 10:34:20.969699 output: Created: Sat Nov 2 10:34:20 2024
220 10:34:20.969911 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 10:34:20.970115 output: Data Size: 65708639 Bytes = 64168.59 KiB = 62.66 MiB
222 10:34:20.970317 output: Load Address: 00000000
223 10:34:20.970517 output: Entry Point: 00000000
224 10:34:20.970715 output:
225 10:34:20.971390 rename /var/lib/lava/dispatcher/tmp/927571/extract-overlay-ramdisk-7ocbsfav/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/927571/tftp-deploy-mc63zsv0/ramdisk/ramdisk.cpio.gz.uboot
226 10:34:20.971812 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 10:34:20.972298 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 10:34:20.972888 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 10:34:20.973410 No LXC device requested
230 10:34:20.973959 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 10:34:20.974515 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 10:34:20.975052 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 10:34:20.975503 Checking files for TFTP limit of 4294967296 bytes.
234 10:34:20.978432 end: 1 tftp-deploy (duration 00:00:40) [common]
235 10:34:20.979056 start: 2 uboot-action (timeout 00:05:00) [common]
236 10:34:20.979626 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 10:34:20.980217 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 10:34:20.980779 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 10:34:20.981350 Using kernel file from prepare-kernel: 927571/tftp-deploy-mc63zsv0/kernel/uImage
240 10:34:20.982030 substitutions:
241 10:34:20.982484 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 10:34:20.982925 - {DTB_ADDR}: 0x01070000
243 10:34:20.983366 - {DTB}: 927571/tftp-deploy-mc63zsv0/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 10:34:20.983807 - {INITRD}: 927571/tftp-deploy-mc63zsv0/ramdisk/ramdisk.cpio.gz.uboot
245 10:34:20.984280 - {KERNEL_ADDR}: 0x01080000
246 10:34:20.984716 - {KERNEL}: 927571/tftp-deploy-mc63zsv0/kernel/uImage
247 10:34:20.985154 - {LAVA_MAC}: None
248 10:34:20.985629 - {PRESEED_CONFIG}: None
249 10:34:20.986063 - {PRESEED_LOCAL}: None
250 10:34:20.986495 - {RAMDISK_ADDR}: 0x08000000
251 10:34:20.986921 - {RAMDISK}: 927571/tftp-deploy-mc63zsv0/ramdisk/ramdisk.cpio.gz.uboot
252 10:34:20.987355 - {ROOT_PART}: None
253 10:34:20.987781 - {ROOT}: None
254 10:34:20.988243 - {SERVER_IP}: 192.168.6.2
255 10:34:20.988677 - {TEE_ADDR}: 0x83000000
256 10:34:20.989108 - {TEE}: None
257 10:34:20.989536 Parsed boot commands:
258 10:34:20.989951 - setenv autoload no
259 10:34:20.990379 - setenv initrd_high 0xffffffff
260 10:34:20.990805 - setenv fdt_high 0xffffffff
261 10:34:20.991231 - dhcp
262 10:34:20.991658 - setenv serverip 192.168.6.2
263 10:34:20.992105 - tftpboot 0x01080000 927571/tftp-deploy-mc63zsv0/kernel/uImage
264 10:34:20.992538 - tftpboot 0x08000000 927571/tftp-deploy-mc63zsv0/ramdisk/ramdisk.cpio.gz.uboot
265 10:34:20.992968 - tftpboot 0x01070000 927571/tftp-deploy-mc63zsv0/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 10:34:20.993400 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 10:34:20.993834 - bootm 0x01080000 0x08000000 0x01070000
268 10:34:20.994375 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 10:34:20.996023 start: 2.3 connect-device (timeout 00:05:00) [common]
271 10:34:20.996514 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 10:34:21.011688 Setting prompt string to ['lava-test: # ']
273 10:34:21.013309 end: 2.3 connect-device (duration 00:00:00) [common]
274 10:34:21.013949 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 10:34:21.014546 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 10:34:21.015115 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 10:34:21.016396 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 10:34:21.057991 >> OK - accepted request
279 10:34:21.060315 Returned 0 in 0 seconds
280 10:34:21.161517 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 10:34:21.163249 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 10:34:21.163865 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 10:34:21.164474 Setting prompt string to ['Hit any key to stop autoboot']
285 10:34:21.164969 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 10:34:21.166669 Trying 192.168.56.21...
287 10:34:21.167181 Connected to conserv1.
288 10:34:21.167642 Escape character is '^]'.
289 10:34:21.168127
290 10:34:21.168593 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 10:34:21.169055
292 10:34:29.079600 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 10:34:29.080316 bl2_stage_init 0x01
294 10:34:29.080817 bl2_stage_init 0x81
295 10:34:29.085152 hw id: 0x0000 - pwm id 0x01
296 10:34:29.085669 bl2_stage_init 0xc1
297 10:34:29.088946 bl2_stage_init 0x02
298 10:34:29.089443
299 10:34:29.089908 L0:00000000
300 10:34:29.090361 L1:00000703
301 10:34:29.094519 L2:00008067
302 10:34:29.094993 L3:15000000
303 10:34:29.095457 S1:00000000
304 10:34:29.095906 B2:20282000
305 10:34:29.096388 B1:a0f83180
306 10:34:29.096828
307 10:34:29.100114 TE: 72502
308 10:34:29.100589
309 10:34:29.105607 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 10:34:29.106078
311 10:34:29.106526 Board ID = 1
312 10:34:29.106965 Set cpu clk to 24M
313 10:34:29.111351 Set clk81 to 24M
314 10:34:29.111817 Use GP1_pll as DSU clk.
315 10:34:29.112298 DSU clk: 1200 Mhz
316 10:34:29.116881 CPU clk: 1200 MHz
317 10:34:29.117356 Set clk81 to 166.6M
318 10:34:29.122456 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 10:34:29.122926 board id: 1
320 10:34:29.131430 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 10:34:29.142052 fw parse done
322 10:34:29.148063 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 10:34:29.190789 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 10:34:29.201633 PIEI prepare done
325 10:34:29.202100 fastboot data load
326 10:34:29.202550 fastboot data verify
327 10:34:29.207222 verify result: 266
328 10:34:29.212815 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 10:34:29.213292 LPDDR4 probe
330 10:34:29.213738 ddr clk to 1584MHz
331 10:34:29.220805 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 10:34:29.258064
333 10:34:29.258530 dmc_version 0001
334 10:34:29.264803 Check phy result
335 10:34:29.270715 INFO : End of CA training
336 10:34:29.271182 INFO : End of initialization
337 10:34:29.276312 INFO : Training has run successfully!
338 10:34:29.276787 Check phy result
339 10:34:29.281900 INFO : End of initialization
340 10:34:29.282365 INFO : End of read enable training
341 10:34:29.285208 INFO : End of fine write leveling
342 10:34:29.290679 INFO : End of Write leveling coarse delay
343 10:34:29.296331 INFO : Training has run successfully!
344 10:34:29.296795 Check phy result
345 10:34:29.297238 INFO : End of initialization
346 10:34:29.301946 INFO : End of read dq deskew training
347 10:34:29.307559 INFO : End of MPR read delay center optimization
348 10:34:29.308055 INFO : End of write delay center optimization
349 10:34:29.313141 INFO : End of read delay center optimization
350 10:34:29.318676 INFO : End of max read latency training
351 10:34:29.319138 INFO : Training has run successfully!
352 10:34:29.324354 1D training succeed
353 10:34:29.330335 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 10:34:29.377754 Check phy result
355 10:34:29.378222 INFO : End of initialization
356 10:34:29.400110 INFO : End of 2D read delay Voltage center optimization
357 10:34:29.419259 INFO : End of 2D read delay Voltage center optimization
358 10:34:29.471132 INFO : End of 2D write delay Voltage center optimization
359 10:34:29.520417 INFO : End of 2D write delay Voltage center optimization
360 10:34:29.525911 INFO : Training has run successfully!
361 10:34:29.526376
362 10:34:29.526826 channel==0
363 10:34:29.531516 RxClkDly_Margin_A0==78 ps 8
364 10:34:29.531976 TxDqDly_Margin_A0==88 ps 9
365 10:34:29.537132 RxClkDly_Margin_A1==78 ps 8
366 10:34:29.537607 TxDqDly_Margin_A1==98 ps 10
367 10:34:29.538054 TrainedVREFDQ_A0==74
368 10:34:29.542714 TrainedVREFDQ_A1==75
369 10:34:29.543185 VrefDac_Margin_A0==24
370 10:34:29.543627 DeviceVref_Margin_A0==40
371 10:34:29.548412 VrefDac_Margin_A1==23
372 10:34:29.548875 DeviceVref_Margin_A1==39
373 10:34:29.549317
374 10:34:29.549758
375 10:34:29.550195 channel==1
376 10:34:29.553901 RxClkDly_Margin_A0==88 ps 9
377 10:34:29.554373 TxDqDly_Margin_A0==98 ps 10
378 10:34:29.559565 RxClkDly_Margin_A1==78 ps 8
379 10:34:29.560065 TxDqDly_Margin_A1==88 ps 9
380 10:34:29.565550 TrainedVREFDQ_A0==78
381 10:34:29.566021 TrainedVREFDQ_A1==75
382 10:34:29.566466 VrefDac_Margin_A0==22
383 10:34:29.570724 DeviceVref_Margin_A0==36
384 10:34:29.571186 VrefDac_Margin_A1==22
385 10:34:29.576416 DeviceVref_Margin_A1==39
386 10:34:29.576878
387 10:34:29.577326 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 10:34:29.577765
389 10:34:29.609923 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000017 00000019 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
390 10:34:29.610458 2D training succeed
391 10:34:29.615524 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 10:34:29.621112 auto size-- 65535DDR cs0 size: 2048MB
393 10:34:29.621579 DDR cs1 size: 2048MB
394 10:34:29.626720 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 10:34:29.627197 cs0 DataBus test pass
396 10:34:29.632318 cs1 DataBus test pass
397 10:34:29.632781 cs0 AddrBus test pass
398 10:34:29.633220 cs1 AddrBus test pass
399 10:34:29.633654
400 10:34:29.637918 100bdlr_step_size ps== 478
401 10:34:29.638393 result report
402 10:34:29.643525 boot times 0Enable ddr reg access
403 10:34:29.648699 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 10:34:29.662525 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 10:34:30.317393 bl2z: ptr: 05129330, size: 00001e40
406 10:34:30.325006 0.0;M3 CHK:0;cm4_sp_mode 0
407 10:34:30.325501 MVN_1=0x00000000
408 10:34:30.325945 MVN_2=0x00000000
409 10:34:30.336493 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 10:34:30.336963 OPS=0x04
411 10:34:30.337414 ring efuse init
412 10:34:30.342118 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 10:34:30.342590 [0.017310 Inits done]
414 10:34:30.343032 secure task start!
415 10:34:30.349659 high task start!
416 10:34:30.350126 low task start!
417 10:34:30.350572 run into bl31
418 10:34:30.358261 NOTICE: BL31: v1.3(release):4fc40b1
419 10:34:30.366074 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 10:34:30.366549 NOTICE: BL31: G12A normal boot!
421 10:34:30.381565 NOTICE: BL31: BL33 decompress pass
422 10:34:30.387270 ERROR: Error initializing runtime service opteed_fast
423 10:34:33.128041 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 10:34:33.128692 bl2_stage_init 0x01
425 10:34:33.129164 bl2_stage_init 0x81
426 10:34:33.133601 hw id: 0x0000 - pwm id 0x01
427 10:34:33.134111 bl2_stage_init 0xc1
428 10:34:33.139213 bl2_stage_init 0x02
429 10:34:33.139745
430 10:34:33.140232 L0:00000000
431 10:34:33.140659 L1:00000703
432 10:34:33.141083 L2:00008067
433 10:34:33.141505 L3:15000000
434 10:34:33.144822 S1:00000000
435 10:34:33.145281 B2:20282000
436 10:34:33.145709 B1:a0f83180
437 10:34:33.146130
438 10:34:33.146558 TE: 69929
439 10:34:33.146986
440 10:34:33.150378 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 10:34:33.150841
442 10:34:33.155975 Board ID = 1
443 10:34:33.156458 Set cpu clk to 24M
444 10:34:33.156886 Set clk81 to 24M
445 10:34:33.161566 Use GP1_pll as DSU clk.
446 10:34:33.162020 DSU clk: 1200 Mhz
447 10:34:33.162446 CPU clk: 1200 MHz
448 10:34:33.167187 Set clk81 to 166.6M
449 10:34:33.172812 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 10:34:33.173263 board id: 1
451 10:34:33.179954 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 10:34:33.190638 fw parse done
453 10:34:33.196604 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 10:34:33.239233 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 10:34:33.250257 PIEI prepare done
456 10:34:33.250704 fastboot data load
457 10:34:33.251129 fastboot data verify
458 10:34:33.255802 verify result: 266
459 10:34:33.261407 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 10:34:33.261864 LPDDR4 probe
461 10:34:33.262286 ddr clk to 1584MHz
462 10:34:33.269404 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 10:34:33.306625
464 10:34:33.307087 dmc_version 0001
465 10:34:33.313313 Check phy result
466 10:34:33.319233 INFO : End of CA training
467 10:34:33.319685 INFO : End of initialization
468 10:34:33.324928 INFO : Training has run successfully!
469 10:34:33.325394 Check phy result
470 10:34:33.330420 INFO : End of initialization
471 10:34:33.330888 INFO : End of read enable training
472 10:34:33.336075 INFO : End of fine write leveling
473 10:34:33.341630 INFO : End of Write leveling coarse delay
474 10:34:33.342099 INFO : Training has run successfully!
475 10:34:33.342546 Check phy result
476 10:34:33.347212 INFO : End of initialization
477 10:34:33.347675 INFO : End of read dq deskew training
478 10:34:33.352822 INFO : End of MPR read delay center optimization
479 10:34:33.358425 INFO : End of write delay center optimization
480 10:34:33.364090 INFO : End of read delay center optimization
481 10:34:33.364558 INFO : End of max read latency training
482 10:34:33.369635 INFO : Training has run successfully!
483 10:34:33.370097 1D training succeed
484 10:34:33.378809 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 10:34:33.426370 Check phy result
486 10:34:33.426837 INFO : End of initialization
487 10:34:33.448753 INFO : End of 2D read delay Voltage center optimization
488 10:34:33.467894 INFO : End of 2D read delay Voltage center optimization
489 10:34:33.519750 INFO : End of 2D write delay Voltage center optimization
490 10:34:33.568956 INFO : End of 2D write delay Voltage center optimization
491 10:34:33.574550 INFO : Training has run successfully!
492 10:34:33.575017
493 10:34:33.575462 channel==0
494 10:34:33.580160 RxClkDly_Margin_A0==78 ps 8
495 10:34:33.580628 TxDqDly_Margin_A0==88 ps 9
496 10:34:33.585733 RxClkDly_Margin_A1==78 ps 8
497 10:34:33.586195 TxDqDly_Margin_A1==98 ps 10
498 10:34:33.586644 TrainedVREFDQ_A0==74
499 10:34:33.591306 TrainedVREFDQ_A1==75
500 10:34:33.591776 VrefDac_Margin_A0==23
501 10:34:33.592270 DeviceVref_Margin_A0==40
502 10:34:33.596951 VrefDac_Margin_A1==22
503 10:34:33.597432 DeviceVref_Margin_A1==39
504 10:34:33.597878
505 10:34:33.598322
506 10:34:33.598762 channel==1
507 10:34:33.602537 RxClkDly_Margin_A0==78 ps 8
508 10:34:33.603001 TxDqDly_Margin_A0==98 ps 10
509 10:34:33.608148 RxClkDly_Margin_A1==78 ps 8
510 10:34:33.608619 TxDqDly_Margin_A1==88 ps 9
511 10:34:33.613719 TrainedVREFDQ_A0==78
512 10:34:33.614186 TrainedVREFDQ_A1==75
513 10:34:33.614632 VrefDac_Margin_A0==22
514 10:34:33.619328 DeviceVref_Margin_A0==36
515 10:34:33.619790 VrefDac_Margin_A1==22
516 10:34:33.624953 DeviceVref_Margin_A1==39
517 10:34:33.625415
518 10:34:33.625859 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 10:34:33.626297
520 10:34:33.658522 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000018 00000016 00000016 dram_vref_reg_value 0x 00000061
521 10:34:33.659030 2D training succeed
522 10:34:33.664149 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 10:34:33.669703 auto size-- 65535DDR cs0 size: 2048MB
524 10:34:33.670169 DDR cs1 size: 2048MB
525 10:34:33.675331 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 10:34:33.675794 cs0 DataBus test pass
527 10:34:33.680963 cs1 DataBus test pass
528 10:34:33.681426 cs0 AddrBus test pass
529 10:34:33.681869 cs1 AddrBus test pass
530 10:34:33.682306
531 10:34:33.686531 100bdlr_step_size ps== 478
532 10:34:33.687002 result report
533 10:34:33.692138 boot times 0Enable ddr reg access
534 10:34:33.697307 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 10:34:33.711155 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 10:34:34.366210 bl2z: ptr: 05129330, size: 00001e40
537 10:34:34.372158 0.0;M3 CHK:0;cm4_sp_mode 0
538 10:34:34.372644 MVN_1=0x00000000
539 10:34:34.373087 MVN_2=0x00000000
540 10:34:34.383524 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 10:34:34.384041 OPS=0x04
542 10:34:34.384503 ring efuse init
543 10:34:34.386615 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 10:34:34.392111 [0.017319 Inits done]
545 10:34:34.392578 secure task start!
546 10:34:34.393020 high task start!
547 10:34:34.393455 low task start!
548 10:34:34.396361 run into bl31
549 10:34:34.404969 NOTICE: BL31: v1.3(release):4fc40b1
550 10:34:34.412844 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 10:34:34.413318 NOTICE: BL31: G12A normal boot!
552 10:34:34.428391 NOTICE: BL31: BL33 decompress pass
553 10:34:34.434146 ERROR: Error initializing runtime service opteed_fast
554 10:34:35.827711 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 10:34:35.828263 bl2_stage_init 0x01
556 10:34:35.828723 bl2_stage_init 0x81
557 10:34:35.833167 hw id: 0x0000 - pwm id 0x01
558 10:34:35.833642 bl2_stage_init 0xc1
559 10:34:35.838834 bl2_stage_init 0x02
560 10:34:35.839303
561 10:34:35.839750 L0:00000000
562 10:34:35.840226 L1:00000703
563 10:34:35.840666 L2:00008067
564 10:34:35.841098 L3:15000000
565 10:34:35.844461 S1:00000000
566 10:34:35.844928 B2:20282000
567 10:34:35.845367 B1:a0f83180
568 10:34:35.845798
569 10:34:35.846228 TE: 70542
570 10:34:35.846663
571 10:34:35.849993 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 10:34:35.850469
573 10:34:35.855556 Board ID = 1
574 10:34:35.856054 Set cpu clk to 24M
575 10:34:35.856500 Set clk81 to 24M
576 10:34:35.861230 Use GP1_pll as DSU clk.
577 10:34:35.861696 DSU clk: 1200 Mhz
578 10:34:35.862138 CPU clk: 1200 MHz
579 10:34:35.866742 Set clk81 to 166.6M
580 10:34:35.872342 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 10:34:35.872808 board id: 1
582 10:34:35.879563 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 10:34:35.890255 fw parse done
584 10:34:35.896220 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 10:34:35.938863 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 10:34:35.949781 PIEI prepare done
587 10:34:35.950242 fastboot data load
588 10:34:35.950690 fastboot data verify
589 10:34:35.955369 verify result: 266
590 10:34:35.960958 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 10:34:35.961425 LPDDR4 probe
592 10:34:35.961865 ddr clk to 1584MHz
593 10:34:35.968952 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 10:34:36.006202
595 10:34:36.006676 dmc_version 0001
596 10:34:36.012877 Check phy result
597 10:34:36.018832 INFO : End of CA training
598 10:34:36.019300 INFO : End of initialization
599 10:34:36.024437 INFO : Training has run successfully!
600 10:34:36.024908 Check phy result
601 10:34:36.029980 INFO : End of initialization
602 10:34:36.030443 INFO : End of read enable training
603 10:34:36.033388 INFO : End of fine write leveling
604 10:34:36.040837 INFO : End of Write leveling coarse delay
605 10:34:36.041318 INFO : Training has run successfully!
606 10:34:36.041767 Check phy result
607 10:34:36.046488 INFO : End of initialization
608 10:34:36.052029 INFO : End of read dq deskew training
609 10:34:36.052495 INFO : End of MPR read delay center optimization
610 10:34:36.057612 INFO : End of write delay center optimization
611 10:34:36.063220 INFO : End of read delay center optimization
612 10:34:36.063697 INFO : End of max read latency training
613 10:34:36.068822 INFO : Training has run successfully!
614 10:34:36.069292 1D training succeed
615 10:34:36.078381 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 10:34:36.125939 Check phy result
617 10:34:36.126408 INFO : End of initialization
618 10:34:36.148339 INFO : End of 2D read delay Voltage center optimization
619 10:34:36.167458 INFO : End of 2D read delay Voltage center optimization
620 10:34:36.219357 INFO : End of 2D write delay Voltage center optimization
621 10:34:36.268573 INFO : End of 2D write delay Voltage center optimization
622 10:34:36.274191 INFO : Training has run successfully!
623 10:34:36.274659
624 10:34:36.275121 channel==0
625 10:34:36.279724 RxClkDly_Margin_A0==78 ps 8
626 10:34:36.280241 TxDqDly_Margin_A0==98 ps 10
627 10:34:36.283025 RxClkDly_Margin_A1==78 ps 8
628 10:34:36.283488 TxDqDly_Margin_A1==88 ps 9
629 10:34:36.288608 TrainedVREFDQ_A0==74
630 10:34:36.289081 TrainedVREFDQ_A1==74
631 10:34:36.289527 VrefDac_Margin_A0==23
632 10:34:36.294193 DeviceVref_Margin_A0==40
633 10:34:36.294658 VrefDac_Margin_A1==23
634 10:34:36.299795 DeviceVref_Margin_A1==40
635 10:34:36.300289
636 10:34:36.300732
637 10:34:36.301168 channel==1
638 10:34:36.301600 RxClkDly_Margin_A0==78 ps 8
639 10:34:36.303259 TxDqDly_Margin_A0==98 ps 10
640 10:34:36.308727 RxClkDly_Margin_A1==78 ps 8
641 10:34:36.309196 TxDqDly_Margin_A1==88 ps 9
642 10:34:36.309641 TrainedVREFDQ_A0==78
643 10:34:36.314472 TrainedVREFDQ_A1==77
644 10:34:36.314938 VrefDac_Margin_A0==22
645 10:34:36.319922 DeviceVref_Margin_A0==36
646 10:34:36.320414 VrefDac_Margin_A1==22
647 10:34:36.320860 DeviceVref_Margin_A1==37
648 10:34:36.321300
649 10:34:36.328929 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 10:34:36.329400
651 10:34:36.354763 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000017 00000018 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
652 10:34:36.360370 2D training succeed
653 10:34:36.363857 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 10:34:36.369463 auto size-- 65535DDR cs0 size: 2048MB
655 10:34:36.369928 DDR cs1 size: 2048MB
656 10:34:36.375074 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 10:34:36.375540 cs0 DataBus test pass
658 10:34:36.380666 cs1 DataBus test pass
659 10:34:36.381135 cs0 AddrBus test pass
660 10:34:36.381575 cs1 AddrBus test pass
661 10:34:36.382006
662 10:34:36.386306 100bdlr_step_size ps== 478
663 10:34:36.386789 result report
664 10:34:36.391855 boot times 0Enable ddr reg access
665 10:34:36.396779 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 10:34:36.410633 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 10:34:37.065570 bl2z: ptr: 05129330, size: 00001e40
668 10:34:37.073224 0.0;M3 CHK:0;cm4_sp_mode 0
669 10:34:37.073723 MVN_1=0x00000000
670 10:34:37.074174 MVN_2=0x00000000
671 10:34:37.084719 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 10:34:37.085198 OPS=0x04
673 10:34:37.085648 ring efuse init
674 10:34:37.090418 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 10:34:37.090896 [0.017319 Inits done]
676 10:34:37.091341 secure task start!
677 10:34:37.098487 high task start!
678 10:34:37.098961 low task start!
679 10:34:37.099405 run into bl31
680 10:34:37.107033 NOTICE: BL31: v1.3(release):4fc40b1
681 10:34:37.114850 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 10:34:37.115322 NOTICE: BL31: G12A normal boot!
683 10:34:37.130400 NOTICE: BL31: BL33 decompress pass
684 10:34:37.136084 ERROR: Error initializing runtime service opteed_fast
685 10:34:37.931390
686 10:34:37.931895
687 10:34:37.936839 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 10:34:37.937317
689 10:34:37.940342 Model: Libre Computer AML-S905D3-CC Solitude
690 10:34:38.087304 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 10:34:38.102746 DRAM: 2 GiB (effective 3.8 GiB)
692 10:34:38.203632 Core: 406 devices, 33 uclasses, devicetree: separate
693 10:34:38.209649 WDT: Not starting watchdog@f0d0
694 10:34:38.234661 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 10:34:38.246893 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 10:34:38.251877 ** Bad device specification mmc 0 **
697 10:34:38.261919 Card did not respond to voltage select! : -110
698 10:34:38.269634 ** Bad device specification mmc 0 **
699 10:34:38.270090 Couldn't find partition mmc 0
700 10:34:38.277907 Card did not respond to voltage select! : -110
701 10:34:38.283424 ** Bad device specification mmc 0 **
702 10:34:38.283880 Couldn't find partition mmc 0
703 10:34:38.288472 Error: could not access storage.
704 10:34:38.585904 Net: eth0: ethernet@ff3f0000
705 10:34:38.586421 starting USB...
706 10:34:38.830591 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 10:34:38.831086 Starting the controller
708 10:34:38.837556 USB XHCI 1.10
709 10:34:40.394038 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 10:34:40.402233 scanning usb for storage devices... 0 Storage Device(s) found
712 10:34:40.453767 Hit any key to stop autoboot: 1
713 10:34:40.454606 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 10:34:40.455249 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 10:34:40.455767 Setting prompt string to ['=>']
716 10:34:40.456338 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 10:34:40.468256 0
718 10:34:40.469195 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 10:34:40.570456 => setenv autoload no
721 10:34:40.571195 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
722 10:34:40.576494 setenv autoload no
724 10:34:40.678058 => setenv initrd_high 0xffffffff
725 10:34:40.678749 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
726 10:34:40.683033 setenv initrd_high 0xffffffff
728 10:34:40.784578 => setenv fdt_high 0xffffffff
729 10:34:40.785300 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
730 10:34:40.789542 setenv fdt_high 0xffffffff
732 10:34:40.891079 => dhcp
733 10:34:40.891792 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
734 10:34:40.895812 dhcp
735 10:34:41.451530 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 10:34:41.452212 Speed: 1000, full duplex
737 10:34:41.452685 BOOTP broadcast 1
738 10:34:41.460321 DHCP client bound to address 192.168.6.21 (8 ms)
740 10:34:41.561855 => setenv serverip 192.168.6.2
741 10:34:41.562536 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
742 10:34:41.567156 setenv serverip 192.168.6.2
744 10:34:41.668708 => tftpboot 0x01080000 927571/tftp-deploy-mc63zsv0/kernel/uImage
745 10:34:41.669399 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
746 10:34:41.676113 tftpboot 0x01080000 927571/tftp-deploy-mc63zsv0/kernel/uImage
747 10:34:41.676620 Speed: 1000, full duplex
748 10:34:41.677073 Using ethernet@ff3f0000 device
749 10:34:41.681696 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
750 10:34:41.687245 Filename '927571/tftp-deploy-mc63zsv0/kernel/uImage'.
751 10:34:41.691065 Load address: 0x1080000
752 10:34:42.158145 Loading: *######## UDP wrong checksum 000000ff 00008793
753 10:34:42.247335 # UDP wrong checksum 000000ff 00001886
754 10:34:43.947901 ############################## UDP wrong checksum 00000005 00001fec
755 10:34:44.549990 ########### 43.6 MiB
756 10:34:44.550613 15.2 MiB/s
757 10:34:44.551041 done
758 10:34:44.554562 Bytes transferred = 45713984 (2b98a40 hex)
760 10:34:44.656075 => tftpboot 0x08000000 927571/tftp-deploy-mc63zsv0/ramdisk/ramdisk.cpio.gz.uboot
761 10:34:44.656984 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
762 10:34:44.663714 tftpboot 0x08000000 927571/tftp-deploy-mc63zsv0/ramdisk/ramdisk.cpio.gz.uboot
763 10:34:44.664259 Speed: 1000, full duplex
764 10:34:44.664683 Using ethernet@ff3f0000 device
765 10:34:44.669245 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
766 10:34:44.678843 Filename '927571/tftp-deploy-mc63zsv0/ramdisk/ramdisk.cpio.gz.uboot'.
767 10:34:44.679144 Load address: 0x8000000
768 10:34:54.200224 Loading: *###########################T ###################### UDP wrong checksum 0000000f 00007016
769 10:34:59.200476 T UDP wrong checksum 0000000f 00007016
770 10:35:09.202646 T T UDP wrong checksum 0000000f 00007016
771 10:35:29.206618 T T T T UDP wrong checksum 0000000f 00007016
772 10:35:44.210335 T T
773 10:35:44.210978 Retry count exceeded; starting again
775 10:35:44.212463 end: 2.4.3 bootloader-commands (duration 00:01:04) [common]
778 10:35:44.214329 end: 2.4 uboot-commands (duration 00:01:23) [common]
780 10:35:44.215702 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
782 10:35:44.216802 end: 2 uboot-action (duration 00:01:23) [common]
784 10:35:44.218291 Cleaning after the job
785 10:35:44.218832 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927571/tftp-deploy-mc63zsv0/ramdisk
786 10:35:44.219936 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927571/tftp-deploy-mc63zsv0/kernel
787 10:35:44.263570 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927571/tftp-deploy-mc63zsv0/dtb
788 10:35:44.264413 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/927571/tftp-deploy-mc63zsv0/modules
789 10:35:44.284371 start: 4.1 power-off (timeout 00:00:30) [common]
790 10:35:44.285037 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
791 10:35:44.318521 >> OK - accepted request
792 10:35:44.320479 Returned 0 in 0 seconds
793 10:35:44.421615 end: 4.1 power-off (duration 00:00:00) [common]
795 10:35:44.423276 start: 4.2 read-feedback (timeout 00:10:00) [common]
796 10:35:44.424426 Listened to connection for namespace 'common' for up to 1s
797 10:35:45.425181 Finalising connection for namespace 'common'
798 10:35:45.425903 Disconnecting from shell: Finalise
799 10:35:45.426407 =>
800 10:35:45.527351 end: 4.2 read-feedback (duration 00:00:01) [common]
801 10:35:45.528044 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/927571
802 10:35:46.164225 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/927571
803 10:35:46.164850 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.