Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 08:35:47.998307 lava-dispatcher, installed at version: 2024.01
2 08:35:47.999097 start: 0 validate
3 08:35:47.999562 Start time: 2024-11-04 08:35:47.999532+00:00 (UTC)
4 08:35:48.000156 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 08:35:48.000704 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 08:35:48.042109 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 08:35:48.042658 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-328-gf46306bca74bb%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 08:35:48.079720 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 08:35:48.080524 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-328-gf46306bca74bb%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 08:35:48.113950 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 08:35:48.114775 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-328-gf46306bca74bb%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 08:35:48.152285 validate duration: 0.15
14 08:35:48.153126 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 08:35:48.153469 start: 1.1 download-retry (timeout 00:10:00) [common]
16 08:35:48.153774 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 08:35:48.154372 Not decompressing ramdisk as can be used compressed.
18 08:35:48.154808 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 08:35:48.155056 saving as /var/lib/lava/dispatcher/tmp/933546/tftp-deploy-xje3o1jg/ramdisk/rootfs.cpio.gz
20 08:35:48.155319 total size: 8181887 (7 MB)
21 08:35:48.196139 progress 0 % (0 MB)
22 08:35:48.202329 progress 5 % (0 MB)
23 08:35:48.208038 progress 10 % (0 MB)
24 08:35:48.214086 progress 15 % (1 MB)
25 08:35:48.219487 progress 20 % (1 MB)
26 08:35:48.225309 progress 25 % (1 MB)
27 08:35:48.230689 progress 30 % (2 MB)
28 08:35:48.236393 progress 35 % (2 MB)
29 08:35:48.241665 progress 40 % (3 MB)
30 08:35:48.247368 progress 45 % (3 MB)
31 08:35:48.252942 progress 50 % (3 MB)
32 08:35:48.258627 progress 55 % (4 MB)
33 08:35:48.263938 progress 60 % (4 MB)
34 08:35:48.269619 progress 65 % (5 MB)
35 08:35:48.274891 progress 70 % (5 MB)
36 08:35:48.280655 progress 75 % (5 MB)
37 08:35:48.285892 progress 80 % (6 MB)
38 08:35:48.291549 progress 85 % (6 MB)
39 08:35:48.296770 progress 90 % (7 MB)
40 08:35:48.302279 progress 95 % (7 MB)
41 08:35:48.307417 progress 100 % (7 MB)
42 08:35:48.308119 7 MB downloaded in 0.15 s (51.07 MB/s)
43 08:35:48.308699 end: 1.1.1 http-download (duration 00:00:00) [common]
45 08:35:48.309624 end: 1.1 download-retry (duration 00:00:00) [common]
46 08:35:48.309940 start: 1.2 download-retry (timeout 00:10:00) [common]
47 08:35:48.310223 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 08:35:48.310716 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-328-gf46306bca74bb/arm64/defconfig/gcc-12/kernel/Image
49 08:35:48.310974 saving as /var/lib/lava/dispatcher/tmp/933546/tftp-deploy-xje3o1jg/kernel/Image
50 08:35:48.311192 total size: 45713920 (43 MB)
51 08:35:48.311410 No compression specified
52 08:35:48.350369 progress 0 % (0 MB)
53 08:35:48.377891 progress 5 % (2 MB)
54 08:35:48.405268 progress 10 % (4 MB)
55 08:35:48.433601 progress 15 % (6 MB)
56 08:35:48.460765 progress 20 % (8 MB)
57 08:35:48.487530 progress 25 % (10 MB)
58 08:35:48.514612 progress 30 % (13 MB)
59 08:35:48.541808 progress 35 % (15 MB)
60 08:35:48.569012 progress 40 % (17 MB)
61 08:35:48.595965 progress 45 % (19 MB)
62 08:35:48.623268 progress 50 % (21 MB)
63 08:35:48.650569 progress 55 % (24 MB)
64 08:35:48.678101 progress 60 % (26 MB)
65 08:35:48.704822 progress 65 % (28 MB)
66 08:35:48.731865 progress 70 % (30 MB)
67 08:35:48.759144 progress 75 % (32 MB)
68 08:35:48.786940 progress 80 % (34 MB)
69 08:35:48.813787 progress 85 % (37 MB)
70 08:35:48.841045 progress 90 % (39 MB)
71 08:35:48.868631 progress 95 % (41 MB)
72 08:35:48.895449 progress 100 % (43 MB)
73 08:35:48.895970 43 MB downloaded in 0.58 s (74.55 MB/s)
74 08:35:48.896497 end: 1.2.1 http-download (duration 00:00:01) [common]
76 08:35:48.897324 end: 1.2 download-retry (duration 00:00:01) [common]
77 08:35:48.897603 start: 1.3 download-retry (timeout 00:09:59) [common]
78 08:35:48.897868 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 08:35:48.898351 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-328-gf46306bca74bb/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 08:35:48.898657 saving as /var/lib/lava/dispatcher/tmp/933546/tftp-deploy-xje3o1jg/dtb/meson-g12b-a311d-libretech-cc.dtb
81 08:35:48.898869 total size: 54703 (0 MB)
82 08:35:48.899080 No compression specified
83 08:35:48.946130 progress 59 % (0 MB)
84 08:35:48.946979 progress 100 % (0 MB)
85 08:35:48.947534 0 MB downloaded in 0.05 s (1.07 MB/s)
86 08:35:48.948030 end: 1.3.1 http-download (duration 00:00:00) [common]
88 08:35:48.948867 end: 1.3 download-retry (duration 00:00:00) [common]
89 08:35:48.949129 start: 1.4 download-retry (timeout 00:09:59) [common]
90 08:35:48.949391 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 08:35:48.949856 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-328-gf46306bca74bb/arm64/defconfig/gcc-12/modules.tar.xz
92 08:35:48.950128 saving as /var/lib/lava/dispatcher/tmp/933546/tftp-deploy-xje3o1jg/modules/modules.tar
93 08:35:48.950337 total size: 11614628 (11 MB)
94 08:35:48.950550 Using unxz to decompress xz
95 08:35:48.988569 progress 0 % (0 MB)
96 08:35:49.054333 progress 5 % (0 MB)
97 08:35:49.127402 progress 10 % (1 MB)
98 08:35:49.222265 progress 15 % (1 MB)
99 08:35:49.313294 progress 20 % (2 MB)
100 08:35:49.393260 progress 25 % (2 MB)
101 08:35:49.467938 progress 30 % (3 MB)
102 08:35:49.545646 progress 35 % (3 MB)
103 08:35:49.617391 progress 40 % (4 MB)
104 08:35:49.692415 progress 45 % (5 MB)
105 08:35:49.778334 progress 50 % (5 MB)
106 08:35:49.855301 progress 55 % (6 MB)
107 08:35:49.939933 progress 60 % (6 MB)
108 08:35:50.019916 progress 65 % (7 MB)
109 08:35:50.099673 progress 70 % (7 MB)
110 08:35:50.177656 progress 75 % (8 MB)
111 08:35:50.260527 progress 80 % (8 MB)
112 08:35:50.341155 progress 85 % (9 MB)
113 08:35:50.423592 progress 90 % (10 MB)
114 08:35:50.496872 progress 95 % (10 MB)
115 08:35:50.573400 progress 100 % (11 MB)
116 08:35:50.585412 11 MB downloaded in 1.64 s (6.77 MB/s)
117 08:35:50.586008 end: 1.4.1 http-download (duration 00:00:02) [common]
119 08:35:50.586842 end: 1.4 download-retry (duration 00:00:02) [common]
120 08:35:50.587122 start: 1.5 prepare-tftp-overlay (timeout 00:09:58) [common]
121 08:35:50.587393 start: 1.5.1 extract-nfsrootfs (timeout 00:09:58) [common]
122 08:35:50.587646 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 08:35:50.587907 start: 1.5.2 lava-overlay (timeout 00:09:58) [common]
124 08:35:50.588903 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc
125 08:35:50.589769 makedir: /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin
126 08:35:50.590437 makedir: /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/tests
127 08:35:50.591074 makedir: /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/results
128 08:35:50.591710 Creating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin/lava-add-keys
129 08:35:50.592726 Creating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin/lava-add-sources
130 08:35:50.593665 Creating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin/lava-background-process-start
131 08:35:50.594606 Creating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin/lava-background-process-stop
132 08:35:50.595583 Creating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin/lava-common-functions
133 08:35:50.596541 Creating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin/lava-echo-ipv4
134 08:35:50.597474 Creating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin/lava-install-packages
135 08:35:50.598385 Creating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin/lava-installed-packages
136 08:35:50.599263 Creating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin/lava-os-build
137 08:35:50.600185 Creating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin/lava-probe-channel
138 08:35:50.601088 Creating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin/lava-probe-ip
139 08:35:50.601984 Creating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin/lava-target-ip
140 08:35:50.602873 Creating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin/lava-target-mac
141 08:35:50.603754 Creating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin/lava-target-storage
142 08:35:50.604718 Creating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin/lava-test-case
143 08:35:50.605638 Creating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin/lava-test-event
144 08:35:50.606524 Creating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin/lava-test-feedback
145 08:35:50.607408 Creating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin/lava-test-raise
146 08:35:50.608320 Creating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin/lava-test-reference
147 08:35:50.609223 Creating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin/lava-test-runner
148 08:35:50.610144 Creating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin/lava-test-set
149 08:35:50.611027 Creating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin/lava-test-shell
150 08:35:50.611947 Updating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin/lava-install-packages (oe)
151 08:35:50.612989 Updating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/bin/lava-installed-packages (oe)
152 08:35:50.613824 Creating /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/environment
153 08:35:50.614526 LAVA metadata
154 08:35:50.615013 - LAVA_JOB_ID=933546
155 08:35:50.615441 - LAVA_DISPATCHER_IP=192.168.6.2
156 08:35:50.616141 start: 1.5.2.1 ssh-authorize (timeout 00:09:58) [common]
157 08:35:50.617934 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 08:35:50.618538 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:58) [common]
159 08:35:50.618946 skipped lava-vland-overlay
160 08:35:50.619435 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 08:35:50.620280 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:58) [common]
162 08:35:50.620775 skipped lava-multinode-overlay
163 08:35:50.621268 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 08:35:50.621775 start: 1.5.2.4 test-definition (timeout 00:09:58) [common]
165 08:35:50.622252 Loading test definitions
166 08:35:50.622799 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:58) [common]
167 08:35:50.623235 Using /lava-933546 at stage 0
168 08:35:50.624826 uuid=933546_1.5.2.4.1 testdef=None
169 08:35:50.625157 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 08:35:50.625435 start: 1.5.2.4.2 test-overlay (timeout 00:09:58) [common]
171 08:35:50.627420 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 08:35:50.628304 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:58) [common]
174 08:35:50.630599 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 08:35:50.631633 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:58) [common]
177 08:35:50.633920 runner path: /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/0/tests/0_dmesg test_uuid 933546_1.5.2.4.1
178 08:35:50.634514 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 08:35:50.635304 Creating lava-test-runner.conf files
181 08:35:50.635511 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/933546/lava-overlay-4exsi7oc/lava-933546/0 for stage 0
182 08:35:50.635843 - 0_dmesg
183 08:35:50.636226 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 08:35:50.636518 start: 1.5.2.5 compress-overlay (timeout 00:09:58) [common]
185 08:35:50.660485 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 08:35:50.660874 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 08:35:50.661143 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 08:35:50.661411 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 08:35:50.661676 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 08:35:51.570153 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 08:35:51.570594 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
192 08:35:51.570845 extracting modules file /var/lib/lava/dispatcher/tmp/933546/tftp-deploy-xje3o1jg/modules/modules.tar to /var/lib/lava/dispatcher/tmp/933546/extract-overlay-ramdisk-fpw8eb6r/ramdisk
193 08:35:52.890660 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 08:35:52.891160 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 08:35:52.891448 [common] Applying overlay /var/lib/lava/dispatcher/tmp/933546/compress-overlay-br16muk2/overlay-1.5.2.5.tar.gz to ramdisk
196 08:35:52.891670 [common] Applying overlay /var/lib/lava/dispatcher/tmp/933546/compress-overlay-br16muk2/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/933546/extract-overlay-ramdisk-fpw8eb6r/ramdisk
197 08:35:52.922072 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 08:35:52.922524 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 08:35:52.922830 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 08:35:52.923078 Converting downloaded kernel to a uImage
201 08:35:52.923414 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/933546/tftp-deploy-xje3o1jg/kernel/Image /var/lib/lava/dispatcher/tmp/933546/tftp-deploy-xje3o1jg/kernel/uImage
202 08:35:53.400213 output: Image Name:
203 08:35:53.400615 output: Created: Mon Nov 4 08:35:52 2024
204 08:35:53.400823 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 08:35:53.401025 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 08:35:53.401222 output: Load Address: 01080000
207 08:35:53.401417 output: Entry Point: 01080000
208 08:35:53.401611 output:
209 08:35:53.401935 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 08:35:53.402195 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 08:35:53.402460 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 08:35:53.402711 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 08:35:53.402963 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 08:35:53.403228 Building ramdisk /var/lib/lava/dispatcher/tmp/933546/extract-overlay-ramdisk-fpw8eb6r/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/933546/extract-overlay-ramdisk-fpw8eb6r/ramdisk
215 08:35:55.750659 >> 181607 blocks
216 08:36:04.274273 Adding RAMdisk u-boot header.
217 08:36:04.274929 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/933546/extract-overlay-ramdisk-fpw8eb6r/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/933546/extract-overlay-ramdisk-fpw8eb6r/ramdisk.cpio.gz.uboot
218 08:36:04.548382 output: Image Name:
219 08:36:04.548812 output: Created: Mon Nov 4 08:36:04 2024
220 08:36:04.549022 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 08:36:04.549228 output: Data Size: 26063631 Bytes = 25452.76 KiB = 24.86 MiB
222 08:36:04.549429 output: Load Address: 00000000
223 08:36:04.549626 output: Entry Point: 00000000
224 08:36:04.549822 output:
225 08:36:04.550518 rename /var/lib/lava/dispatcher/tmp/933546/extract-overlay-ramdisk-fpw8eb6r/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/933546/tftp-deploy-xje3o1jg/ramdisk/ramdisk.cpio.gz.uboot
226 08:36:04.550956 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 08:36:04.551257 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 08:36:04.551547 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:44) [common]
229 08:36:04.551800 No LXC device requested
230 08:36:04.552184 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 08:36:04.552714 start: 1.7 deploy-device-env (timeout 00:09:44) [common]
232 08:36:04.553204 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 08:36:04.553612 Checking files for TFTP limit of 4294967296 bytes.
234 08:36:04.556292 end: 1 tftp-deploy (duration 00:00:16) [common]
235 08:36:04.556862 start: 2 uboot-action (timeout 00:05:00) [common]
236 08:36:04.557379 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 08:36:04.557871 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 08:36:04.558366 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 08:36:04.558889 Using kernel file from prepare-kernel: 933546/tftp-deploy-xje3o1jg/kernel/uImage
240 08:36:04.559489 substitutions:
241 08:36:04.559894 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 08:36:04.560328 - {DTB_ADDR}: 0x01070000
243 08:36:04.560727 - {DTB}: 933546/tftp-deploy-xje3o1jg/dtb/meson-g12b-a311d-libretech-cc.dtb
244 08:36:04.561124 - {INITRD}: 933546/tftp-deploy-xje3o1jg/ramdisk/ramdisk.cpio.gz.uboot
245 08:36:04.561521 - {KERNEL_ADDR}: 0x01080000
246 08:36:04.561912 - {KERNEL}: 933546/tftp-deploy-xje3o1jg/kernel/uImage
247 08:36:04.562306 - {LAVA_MAC}: None
248 08:36:04.562738 - {PRESEED_CONFIG}: None
249 08:36:04.563129 - {PRESEED_LOCAL}: None
250 08:36:04.563517 - {RAMDISK_ADDR}: 0x08000000
251 08:36:04.563902 - {RAMDISK}: 933546/tftp-deploy-xje3o1jg/ramdisk/ramdisk.cpio.gz.uboot
252 08:36:04.564322 - {ROOT_PART}: None
253 08:36:04.564711 - {ROOT}: None
254 08:36:04.565099 - {SERVER_IP}: 192.168.6.2
255 08:36:04.565489 - {TEE_ADDR}: 0x83000000
256 08:36:04.565877 - {TEE}: None
257 08:36:04.566264 Parsed boot commands:
258 08:36:04.566643 - setenv autoload no
259 08:36:04.567029 - setenv initrd_high 0xffffffff
260 08:36:04.567416 - setenv fdt_high 0xffffffff
261 08:36:04.567800 - dhcp
262 08:36:04.568211 - setenv serverip 192.168.6.2
263 08:36:04.568596 - tftpboot 0x01080000 933546/tftp-deploy-xje3o1jg/kernel/uImage
264 08:36:04.568983 - tftpboot 0x08000000 933546/tftp-deploy-xje3o1jg/ramdisk/ramdisk.cpio.gz.uboot
265 08:36:04.569368 - tftpboot 0x01070000 933546/tftp-deploy-xje3o1jg/dtb/meson-g12b-a311d-libretech-cc.dtb
266 08:36:04.569757 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 08:36:04.570150 - bootm 0x01080000 0x08000000 0x01070000
268 08:36:04.570635 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 08:36:04.572133 start: 2.3 connect-device (timeout 00:05:00) [common]
271 08:36:04.572579 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 08:36:04.587427 Setting prompt string to ['lava-test: # ']
273 08:36:04.588970 end: 2.3 connect-device (duration 00:00:00) [common]
274 08:36:04.589564 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 08:36:04.590107 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 08:36:04.590715 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 08:36:04.591827 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 08:36:04.628982 >> OK - accepted request
279 08:36:04.631210 Returned 0 in 0 seconds
280 08:36:04.732318 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 08:36:04.733852 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 08:36:04.734406 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 08:36:04.734911 Setting prompt string to ['Hit any key to stop autoboot']
285 08:36:04.735364 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 08:36:04.736950 Trying 192.168.56.21...
287 08:36:04.737429 Connected to conserv1.
288 08:36:04.737829 Escape character is '^]'.
289 08:36:04.738246
290 08:36:04.738665 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 08:36:04.739092
292 08:36:16.541297 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 08:36:16.541972 bl2_stage_init 0x01
294 08:36:16.542445 bl2_stage_init 0x81
295 08:36:16.546706 hw id: 0x0000 - pwm id 0x01
296 08:36:16.547267 bl2_stage_init 0xc1
297 08:36:16.547703 bl2_stage_init 0x02
298 08:36:16.548180
299 08:36:16.552356 L0:00000000
300 08:36:16.552839 L1:20000703
301 08:36:16.553235 L2:00008067
302 08:36:16.553627 L3:14000000
303 08:36:16.555163 B2:00402000
304 08:36:16.555597 B1:e0f83180
305 08:36:16.556015
306 08:36:16.556417 TE: 58159
307 08:36:16.556812
308 08:36:16.566346 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 08:36:16.566896
310 08:36:16.567334 Board ID = 1
311 08:36:16.567763 Set A53 clk to 24M
312 08:36:16.568233 Set A73 clk to 24M
313 08:36:16.572036 Set clk81 to 24M
314 08:36:16.572537 A53 clk: 1200 MHz
315 08:36:16.572958 A73 clk: 1200 MHz
316 08:36:16.575510 CLK81: 166.6M
317 08:36:16.576013 smccc: 00012ab5
318 08:36:16.581056 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 08:36:16.586706 board id: 1
320 08:36:16.591829 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 08:36:16.602282 fw parse done
322 08:36:16.608341 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 08:36:16.650224 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 08:36:16.661857 PIEI prepare done
325 08:36:16.662378 fastboot data load
326 08:36:16.662786 fastboot data verify
327 08:36:16.667368 verify result: 266
328 08:36:16.673069 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 08:36:16.673581 LPDDR4 probe
330 08:36:16.673995 ddr clk to 1584MHz
331 08:36:16.680961 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 08:36:16.718465
333 08:36:16.719017 dmc_version 0001
334 08:36:16.724896 Check phy result
335 08:36:16.730796 INFO : End of CA training
336 08:36:16.731252 INFO : End of initialization
337 08:36:16.736418 INFO : Training has run successfully!
338 08:36:16.736852 Check phy result
339 08:36:16.742017 INFO : End of initialization
340 08:36:16.742448 INFO : End of read enable training
341 08:36:16.747596 INFO : End of fine write leveling
342 08:36:16.753248 INFO : End of Write leveling coarse delay
343 08:36:16.753679 INFO : Training has run successfully!
344 08:36:16.754086 Check phy result
345 08:36:16.758779 INFO : End of initialization
346 08:36:16.759206 INFO : End of read dq deskew training
347 08:36:16.764392 INFO : End of MPR read delay center optimization
348 08:36:16.770042 INFO : End of write delay center optimization
349 08:36:16.775578 INFO : End of read delay center optimization
350 08:36:16.776052 INFO : End of max read latency training
351 08:36:16.781295 INFO : Training has run successfully!
352 08:36:16.781727 1D training succeed
353 08:36:16.790375 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 08:36:16.837982 Check phy result
355 08:36:16.838510 INFO : End of initialization
356 08:36:16.859630 INFO : End of 2D read delay Voltage center optimization
357 08:36:16.881013 INFO : End of 2D read delay Voltage center optimization
358 08:36:16.932982 INFO : End of 2D write delay Voltage center optimization
359 08:36:16.982369 INFO : End of 2D write delay Voltage center optimization
360 08:36:16.987741 INFO : Training has run successfully!
361 08:36:16.988234
362 08:36:16.988647 channel==0
363 08:36:16.993461 RxClkDly_Margin_A0==88 ps 9
364 08:36:16.993903 TxDqDly_Margin_A0==108 ps 11
365 08:36:16.999060 RxClkDly_Margin_A1==88 ps 9
366 08:36:16.999499 TxDqDly_Margin_A1==98 ps 10
367 08:36:16.999910 TrainedVREFDQ_A0==74
368 08:36:17.004708 TrainedVREFDQ_A1==74
369 08:36:17.005146 VrefDac_Margin_A0==25
370 08:36:17.010268 DeviceVref_Margin_A0==40
371 08:36:17.010703 VrefDac_Margin_A1==26
372 08:36:17.011110 DeviceVref_Margin_A1==40
373 08:36:17.011514
374 08:36:17.011915
375 08:36:17.015776 channel==1
376 08:36:17.016248 RxClkDly_Margin_A0==98 ps 10
377 08:36:17.016664 TxDqDly_Margin_A0==98 ps 10
378 08:36:17.021310 RxClkDly_Margin_A1==88 ps 9
379 08:36:17.021752 TxDqDly_Margin_A1==88 ps 9
380 08:36:17.026953 TrainedVREFDQ_A0==77
381 08:36:17.027407 TrainedVREFDQ_A1==77
382 08:36:17.027819 VrefDac_Margin_A0==22
383 08:36:17.032572 DeviceVref_Margin_A0==37
384 08:36:17.033014 VrefDac_Margin_A1==24
385 08:36:17.038337 DeviceVref_Margin_A1==37
386 08:36:17.038773
387 08:36:17.039189 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 08:36:17.043784
389 08:36:17.071855 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000016 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
390 08:36:17.072437 2D training succeed
391 08:36:17.077445 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 08:36:17.083075 auto size-- 65535DDR cs0 size: 2048MB
393 08:36:17.083526 DDR cs1 size: 2048MB
394 08:36:17.088920 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 08:36:17.089408 cs0 DataBus test pass
396 08:36:17.094248 cs1 DataBus test pass
397 08:36:17.094718 cs0 AddrBus test pass
398 08:36:17.095127 cs1 AddrBus test pass
399 08:36:17.095527
400 08:36:17.099802 100bdlr_step_size ps== 420
401 08:36:17.100291 result report
402 08:36:17.105568 boot times 0Enable ddr reg access
403 08:36:17.110826 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 08:36:17.124323 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 08:36:17.697979 0.0;M3 CHK:0;cm4_sp_mode 0
406 08:36:17.698443 MVN_1=0x00000000
407 08:36:17.703403 MVN_2=0x00000000
408 08:36:17.709284 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 08:36:17.709577 OPS=0x10
410 08:36:17.709801 ring efuse init
411 08:36:17.710017 chipver efuse init
412 08:36:17.714748 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 08:36:17.720326 [0.018960 Inits done]
414 08:36:17.720619 secure task start!
415 08:36:17.720843 high task start!
416 08:36:17.724921 low task start!
417 08:36:17.725207 run into bl31
418 08:36:17.731577 NOTICE: BL31: v1.3(release):4fc40b1
419 08:36:17.739401 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 08:36:17.739710 NOTICE: BL31: G12A normal boot!
421 08:36:17.764850 NOTICE: BL31: BL33 decompress pass
422 08:36:17.770540 ERROR: Error initializing runtime service opteed_fast
423 08:36:19.003562
424 08:36:19.004011
425 08:36:19.011757 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 08:36:19.012065
427 08:36:19.012289 Model: Libre Computer AML-A311D-CC Alta
428 08:36:19.220344 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 08:36:19.243625 DRAM: 2 GiB (effective 3.8 GiB)
430 08:36:19.386647 Core: 408 devices, 31 uclasses, devicetree: separate
431 08:36:19.392436 WDT: Not starting watchdog@f0d0
432 08:36:19.424807 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 08:36:19.437183 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 08:36:19.442186 ** Bad device specification mmc 0 **
435 08:36:19.452721 Card did not respond to voltage select! : -110
436 08:36:19.460162 ** Bad device specification mmc 0 **
437 08:36:19.460512 Couldn't find partition mmc 0
438 08:36:19.468571 Card did not respond to voltage select! : -110
439 08:36:19.474008 ** Bad device specification mmc 0 **
440 08:36:19.474483 Couldn't find partition mmc 0
441 08:36:19.479052 Error: could not access storage.
442 08:36:20.741594 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 08:36:20.742203 bl2_stage_init 0x01
444 08:36:20.742639 bl2_stage_init 0x81
445 08:36:20.747071 hw id: 0x0000 - pwm id 0x01
446 08:36:20.747523 bl2_stage_init 0xc1
447 08:36:20.747941 bl2_stage_init 0x02
448 08:36:20.748395
449 08:36:20.752770 L0:00000000
450 08:36:20.753213 L1:20000703
451 08:36:20.753626 L2:00008067
452 08:36:20.754031 L3:14000000
453 08:36:20.755532 B2:00402000
454 08:36:20.755965 B1:e0f83180
455 08:36:20.756402
456 08:36:20.756812 TE: 58158
457 08:36:20.757220
458 08:36:20.766757 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 08:36:20.767213
460 08:36:20.767626 Board ID = 1
461 08:36:20.768063 Set A53 clk to 24M
462 08:36:20.768476 Set A73 clk to 24M
463 08:36:20.772363 Set clk81 to 24M
464 08:36:20.772812 A53 clk: 1200 MHz
465 08:36:20.773219 A73 clk: 1200 MHz
466 08:36:20.777861 CLK81: 166.6M
467 08:36:20.778301 smccc: 00012ab5
468 08:36:20.783502 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 08:36:20.783953 board id: 1
470 08:36:20.789088 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 08:36:20.802783 fw parse done
472 08:36:20.808810 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 08:36:20.851344 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 08:36:20.862282 PIEI prepare done
475 08:36:20.862736 fastboot data load
476 08:36:20.863154 fastboot data verify
477 08:36:20.867887 verify result: 266
478 08:36:20.873544 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 08:36:20.873988 LPDDR4 probe
480 08:36:20.874400 ddr clk to 1584MHz
481 08:36:20.881473 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 08:36:20.918779
483 08:36:20.919252 dmc_version 0001
484 08:36:20.925681 Check phy result
485 08:36:20.931293 INFO : End of CA training
486 08:36:20.931732 INFO : End of initialization
487 08:36:20.936854 INFO : Training has run successfully!
488 08:36:20.937295 Check phy result
489 08:36:20.942546 INFO : End of initialization
490 08:36:20.942988 INFO : End of read enable training
491 08:36:20.945783 INFO : End of fine write leveling
492 08:36:20.951510 INFO : End of Write leveling coarse delay
493 08:36:20.956973 INFO : Training has run successfully!
494 08:36:20.957418 Check phy result
495 08:36:20.957825 INFO : End of initialization
496 08:36:20.962580 INFO : End of read dq deskew training
497 08:36:20.968208 INFO : End of MPR read delay center optimization
498 08:36:20.968653 INFO : End of write delay center optimization
499 08:36:20.973807 INFO : End of read delay center optimization
500 08:36:20.979359 INFO : End of max read latency training
501 08:36:20.979799 INFO : Training has run successfully!
502 08:36:20.984968 1D training succeed
503 08:36:20.990841 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 08:36:21.038473 Check phy result
505 08:36:21.038995 INFO : End of initialization
506 08:36:21.060180 INFO : End of 2D read delay Voltage center optimization
507 08:36:21.080374 INFO : End of 2D read delay Voltage center optimization
508 08:36:21.132651 INFO : End of 2D write delay Voltage center optimization
509 08:36:21.181902 INFO : End of 2D write delay Voltage center optimization
510 08:36:21.187347 INFO : Training has run successfully!
511 08:36:21.187800
512 08:36:21.188266 channel==0
513 08:36:21.192943 RxClkDly_Margin_A0==88 ps 9
514 08:36:21.193385 TxDqDly_Margin_A0==98 ps 10
515 08:36:21.198574 RxClkDly_Margin_A1==88 ps 9
516 08:36:21.199014 TxDqDly_Margin_A1==98 ps 10
517 08:36:21.199431 TrainedVREFDQ_A0==74
518 08:36:21.204171 TrainedVREFDQ_A1==74
519 08:36:21.204623 VrefDac_Margin_A0==25
520 08:36:21.205032 DeviceVref_Margin_A0==40
521 08:36:21.209802 VrefDac_Margin_A1==25
522 08:36:21.210248 DeviceVref_Margin_A1==40
523 08:36:21.210658
524 08:36:21.211063
525 08:36:21.215355 channel==1
526 08:36:21.215788 RxClkDly_Margin_A0==98 ps 10
527 08:36:21.216233 TxDqDly_Margin_A0==88 ps 9
528 08:36:21.220968 RxClkDly_Margin_A1==88 ps 9
529 08:36:21.221420 TxDqDly_Margin_A1==88 ps 9
530 08:36:21.226556 TrainedVREFDQ_A0==76
531 08:36:21.227006 TrainedVREFDQ_A1==77
532 08:36:21.227418 VrefDac_Margin_A0==22
533 08:36:21.232159 DeviceVref_Margin_A0==38
534 08:36:21.232598 VrefDac_Margin_A1==24
535 08:36:21.237827 DeviceVref_Margin_A1==37
536 08:36:21.238273
537 08:36:21.238683 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 08:36:21.239087
539 08:36:21.271397 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
540 08:36:21.271920 2D training succeed
541 08:36:21.276955 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 08:36:21.282618 auto size-- 65535DDR cs0 size: 2048MB
543 08:36:21.283075 DDR cs1 size: 2048MB
544 08:36:21.288146 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 08:36:21.288597 cs0 DataBus test pass
546 08:36:21.293863 cs1 DataBus test pass
547 08:36:21.294318 cs0 AddrBus test pass
548 08:36:21.294731 cs1 AddrBus test pass
549 08:36:21.295141
550 08:36:21.299453 100bdlr_step_size ps== 420
551 08:36:21.299917 result report
552 08:36:21.304960 boot times 0Enable ddr reg access
553 08:36:21.310189 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 08:36:21.323686 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 08:36:21.897561 0.0;M3 CHK:0;cm4_sp_mode 0
556 08:36:21.898149 MVN_1=0x00000000
557 08:36:21.902932 MVN_2=0x00000000
558 08:36:21.908659 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 08:36:21.909163 OPS=0x10
560 08:36:21.909596 ring efuse init
561 08:36:21.910016 chipver efuse init
562 08:36:21.914332 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 08:36:21.919883 [0.018961 Inits done]
564 08:36:21.920431 secure task start!
565 08:36:21.920839 high task start!
566 08:36:21.924464 low task start!
567 08:36:21.924900 run into bl31
568 08:36:21.931099 NOTICE: BL31: v1.3(release):4fc40b1
569 08:36:21.938973 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 08:36:21.939404 NOTICE: BL31: G12A normal boot!
571 08:36:21.964284 NOTICE: BL31: BL33 decompress pass
572 08:36:21.969979 ERROR: Error initializing runtime service opteed_fast
573 08:36:23.203029
574 08:36:23.203616
575 08:36:23.211348 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 08:36:23.211822
577 08:36:23.212281 Model: Libre Computer AML-A311D-CC Alta
578 08:36:23.419925 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 08:36:23.443424 DRAM: 2 GiB (effective 3.8 GiB)
580 08:36:23.586436 Core: 408 devices, 31 uclasses, devicetree: separate
581 08:36:23.591825 WDT: Not starting watchdog@f0d0
582 08:36:23.624373 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 08:36:23.636799 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 08:36:23.641846 ** Bad device specification mmc 0 **
585 08:36:23.652028 Card did not respond to voltage select! : -110
586 08:36:23.659819 ** Bad device specification mmc 0 **
587 08:36:23.660477 Couldn't find partition mmc 0
588 08:36:23.668108 Card did not respond to voltage select! : -110
589 08:36:23.673492 ** Bad device specification mmc 0 **
590 08:36:23.673956 Couldn't find partition mmc 0
591 08:36:23.678697 Error: could not access storage.
592 08:36:24.022224 Net: eth0: ethernet@ff3f0000
593 08:36:24.022823 starting USB...
594 08:36:24.274043 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 08:36:24.274642 Starting the controller
596 08:36:24.280989 USB XHCI 1.10
597 08:36:25.990129 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 08:36:25.990753 bl2_stage_init 0x01
599 08:36:25.991188 bl2_stage_init 0x81
600 08:36:25.995743 hw id: 0x0000 - pwm id 0x01
601 08:36:25.996283 bl2_stage_init 0xc1
602 08:36:25.996704 bl2_stage_init 0x02
603 08:36:25.997112
604 08:36:26.001229 L0:00000000
605 08:36:26.001672 L1:20000703
606 08:36:26.002087 L2:00008067
607 08:36:26.002494 L3:14000000
608 08:36:26.006836 B2:00402000
609 08:36:26.007275 B1:e0f83180
610 08:36:26.007684
611 08:36:26.008127 TE: 58159
612 08:36:26.008541
613 08:36:26.012496 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 08:36:26.012990
615 08:36:26.013405 Board ID = 1
616 08:36:26.018114 Set A53 clk to 24M
617 08:36:26.018569 Set A73 clk to 24M
618 08:36:26.018980 Set clk81 to 24M
619 08:36:26.023684 A53 clk: 1200 MHz
620 08:36:26.024153 A73 clk: 1200 MHz
621 08:36:26.024559 CLK81: 166.6M
622 08:36:26.024961 smccc: 00012ab5
623 08:36:26.029222 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 08:36:26.034875 board id: 1
625 08:36:26.039875 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 08:36:26.051494 fw parse done
627 08:36:26.057369 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 08:36:26.100041 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 08:36:26.110895 PIEI prepare done
630 08:36:26.111398 fastboot data load
631 08:36:26.111855 fastboot data verify
632 08:36:26.116596 verify result: 266
633 08:36:26.122169 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 08:36:26.122613 LPDDR4 probe
635 08:36:26.123021 ddr clk to 1584MHz
636 08:36:26.130128 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 08:36:26.167368
638 08:36:26.167834 dmc_version 0001
639 08:36:26.174052 Check phy result
640 08:36:26.179932 INFO : End of CA training
641 08:36:26.180404 INFO : End of initialization
642 08:36:26.185546 INFO : Training has run successfully!
643 08:36:26.185985 Check phy result
644 08:36:26.191157 INFO : End of initialization
645 08:36:26.191598 INFO : End of read enable training
646 08:36:26.194548 INFO : End of fine write leveling
647 08:36:26.200172 INFO : End of Write leveling coarse delay
648 08:36:26.205737 INFO : Training has run successfully!
649 08:36:26.206175 Check phy result
650 08:36:26.206581 INFO : End of initialization
651 08:36:26.211330 INFO : End of read dq deskew training
652 08:36:26.216959 INFO : End of MPR read delay center optimization
653 08:36:26.217457 INFO : End of write delay center optimization
654 08:36:26.222552 INFO : End of read delay center optimization
655 08:36:26.228193 INFO : End of max read latency training
656 08:36:26.228633 INFO : Training has run successfully!
657 08:36:26.233738 1D training succeed
658 08:36:26.239626 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 08:36:26.287104 Check phy result
660 08:36:26.287574 INFO : End of initialization
661 08:36:26.308825 INFO : End of 2D read delay Voltage center optimization
662 08:36:26.329092 INFO : End of 2D read delay Voltage center optimization
663 08:36:26.381125 INFO : End of 2D write delay Voltage center optimization
664 08:36:26.430667 INFO : End of 2D write delay Voltage center optimization
665 08:36:26.436080 INFO : Training has run successfully!
666 08:36:26.436530
667 08:36:26.436946 channel==0
668 08:36:26.441673 RxClkDly_Margin_A0==88 ps 9
669 08:36:26.442114 TxDqDly_Margin_A0==98 ps 10
670 08:36:26.447334 RxClkDly_Margin_A1==88 ps 9
671 08:36:26.447806 TxDqDly_Margin_A1==98 ps 10
672 08:36:26.448280 TrainedVREFDQ_A0==74
673 08:36:26.452876 TrainedVREFDQ_A1==74
674 08:36:26.453336 VrefDac_Margin_A0==25
675 08:36:26.453745 DeviceVref_Margin_A0==40
676 08:36:26.458594 VrefDac_Margin_A1==25
677 08:36:26.459044 DeviceVref_Margin_A1==40
678 08:36:26.459451
679 08:36:26.459854
680 08:36:26.464101 channel==1
681 08:36:26.464542 RxClkDly_Margin_A0==98 ps 10
682 08:36:26.464946 TxDqDly_Margin_A0==88 ps 9
683 08:36:26.469667 RxClkDly_Margin_A1==88 ps 9
684 08:36:26.470109 TxDqDly_Margin_A1==88 ps 9
685 08:36:26.475319 TrainedVREFDQ_A0==77
686 08:36:26.475760 TrainedVREFDQ_A1==77
687 08:36:26.476203 VrefDac_Margin_A0==22
688 08:36:26.480860 DeviceVref_Margin_A0==37
689 08:36:26.481297 VrefDac_Margin_A1==24
690 08:36:26.486691 DeviceVref_Margin_A1==37
691 08:36:26.487124
692 08:36:26.487541 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 08:36:26.488006
694 08:36:26.520087 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 0000001a 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
695 08:36:26.520649 2D training succeed
696 08:36:26.525652 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 08:36:26.531272 auto size-- 65535DDR cs0 size: 2048MB
698 08:36:26.531713 DDR cs1 size: 2048MB
699 08:36:26.536838 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 08:36:26.537290 cs0 DataBus test pass
701 08:36:26.542595 cs1 DataBus test pass
702 08:36:26.543067 cs0 AddrBus test pass
703 08:36:26.543482 cs1 AddrBus test pass
704 08:36:26.543884
705 08:36:26.548056 100bdlr_step_size ps== 420
706 08:36:26.548505 result report
707 08:36:26.553628 boot times 0Enable ddr reg access
708 08:36:26.558914 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 08:36:26.571559 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 08:36:27.146112 0.0;M3 CHK:0;cm4_sp_mode 0
711 08:36:27.146757 MVN_1=0x00000000
712 08:36:27.151667 MVN_2=0x00000000
713 08:36:27.157306 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 08:36:27.157865 OPS=0x10
715 08:36:27.158269 ring efuse init
716 08:36:27.158663 chipver efuse init
717 08:36:27.162867 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 08:36:27.168624 [0.018960 Inits done]
719 08:36:27.169205 secure task start!
720 08:36:27.169603 high task start!
721 08:36:27.173654 low task start!
722 08:36:27.174103 run into bl31
723 08:36:27.179785 NOTICE: BL31: v1.3(release):4fc40b1
724 08:36:27.187499 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 08:36:27.187956 NOTICE: BL31: G12A normal boot!
726 08:36:27.212934 NOTICE: BL31: BL33 decompress pass
727 08:36:27.218633 ERROR: Error initializing runtime service opteed_fast
728 08:36:28.573893
729 08:36:28.574332
730 08:36:28.576236 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 08:36:28.576643
732 08:36:28.577020 Model: Libre Computer AML-A311D-CC Alta
733 08:36:28.668204 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 08:36:28.690667 DRAM: 2 GiB (effective 3.8 GiB)
735 08:36:28.834653 Core: 408 devices, 31 uclasses, devicetree: separate
736 08:36:28.840522 WDT: Not starting watchdog@f0d0
737 08:36:28.872783 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 08:36:28.885190 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 08:36:28.890190 ** Bad device specification mmc 0 **
740 08:36:28.900593 Card did not respond to voltage select! : -110
741 08:36:28.908263 ** Bad device specification mmc 0 **
742 08:36:28.908847 Couldn't find partition mmc 0
743 08:36:28.916646 Card did not respond to voltage select! : -110
744 08:36:28.922065 ** Bad device specification mmc 0 **
745 08:36:28.922603 Couldn't find partition mmc 0
746 08:36:28.927175 Error: could not access storage.
747 08:36:29.270603 Net: eth0: ethernet@ff3f0000
748 08:36:29.271187 starting USB...
749 08:36:29.522492 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 08:36:29.523107 Starting the controller
751 08:36:29.529398 USB XHCI 1.10
752 08:36:31.690437 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 08:36:31.691052 bl2_stage_init 0x01
754 08:36:31.691480 bl2_stage_init 0x81
755 08:36:31.696034 hw id: 0x0000 - pwm id 0x01
756 08:36:31.696551 bl2_stage_init 0xc1
757 08:36:31.696978 bl2_stage_init 0x02
758 08:36:31.697391
759 08:36:31.701566 L0:00000000
760 08:36:31.702059 L1:20000703
761 08:36:31.702476 L2:00008067
762 08:36:31.702882 L3:14000000
763 08:36:31.707209 B2:00402000
764 08:36:31.707691 B1:e0f83180
765 08:36:31.708157
766 08:36:31.708576 TE: 58159
767 08:36:31.708988
768 08:36:31.712732 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 08:36:31.713221
770 08:36:31.713670 Board ID = 1
771 08:36:31.718292 Set A53 clk to 24M
772 08:36:31.718783 Set A73 clk to 24M
773 08:36:31.719199 Set clk81 to 24M
774 08:36:31.723918 A53 clk: 1200 MHz
775 08:36:31.724469 A73 clk: 1200 MHz
776 08:36:31.724885 CLK81: 166.6M
777 08:36:31.725288 smccc: 00012ab5
778 08:36:31.729535 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 08:36:31.735138 board id: 1
780 08:36:31.741016 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 08:36:31.751670 fw parse done
782 08:36:31.757641 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 08:36:31.801406 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 08:36:31.811125 PIEI prepare done
785 08:36:31.811609 fastboot data load
786 08:36:31.812062 fastboot data verify
787 08:36:31.816794 verify result: 266
788 08:36:31.822397 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 08:36:31.822874 LPDDR4 probe
790 08:36:31.823288 ddr clk to 1584MHz
791 08:36:31.830437 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 08:36:31.867626
793 08:36:31.868170 dmc_version 0001
794 08:36:31.874054 Check phy result
795 08:36:31.880277 INFO : End of CA training
796 08:36:31.880759 INFO : End of initialization
797 08:36:31.885748 INFO : Training has run successfully!
798 08:36:31.886225 Check phy result
799 08:36:31.891342 INFO : End of initialization
800 08:36:31.891818 INFO : End of read enable training
801 08:36:31.896990 INFO : End of fine write leveling
802 08:36:31.902593 INFO : End of Write leveling coarse delay
803 08:36:31.903067 INFO : Training has run successfully!
804 08:36:31.903481 Check phy result
805 08:36:31.908241 INFO : End of initialization
806 08:36:31.908717 INFO : End of read dq deskew training
807 08:36:31.913750 INFO : End of MPR read delay center optimization
808 08:36:31.919346 INFO : End of write delay center optimization
809 08:36:31.924953 INFO : End of read delay center optimization
810 08:36:31.925428 INFO : End of max read latency training
811 08:36:31.930595 INFO : Training has run successfully!
812 08:36:31.931069 1D training succeed
813 08:36:31.939707 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 08:36:31.987387 Check phy result
815 08:36:31.987918 INFO : End of initialization
816 08:36:32.009179 INFO : End of 2D read delay Voltage center optimization
817 08:36:32.029507 INFO : End of 2D read delay Voltage center optimization
818 08:36:32.081571 INFO : End of 2D write delay Voltage center optimization
819 08:36:32.130935 INFO : End of 2D write delay Voltage center optimization
820 08:36:32.136493 INFO : Training has run successfully!
821 08:36:32.136974
822 08:36:32.137397 channel==0
823 08:36:32.142181 RxClkDly_Margin_A0==88 ps 9
824 08:36:32.142665 TxDqDly_Margin_A0==98 ps 10
825 08:36:32.145431 RxClkDly_Margin_A1==88 ps 9
826 08:36:32.145905 TxDqDly_Margin_A1==88 ps 9
827 08:36:32.150891 TrainedVREFDQ_A0==74
828 08:36:32.151366 TrainedVREFDQ_A1==74
829 08:36:32.151792 VrefDac_Margin_A0==25
830 08:36:32.156576 DeviceVref_Margin_A0==40
831 08:36:32.157075 VrefDac_Margin_A1==25
832 08:36:32.162057 DeviceVref_Margin_A1==40
833 08:36:32.162559
834 08:36:32.162956
835 08:36:32.163346 channel==1
836 08:36:32.163730 RxClkDly_Margin_A0==98 ps 10
837 08:36:32.167728 TxDqDly_Margin_A0==98 ps 10
838 08:36:32.168223 RxClkDly_Margin_A1==98 ps 10
839 08:36:32.173303 TxDqDly_Margin_A1==88 ps 9
840 08:36:32.173771 TrainedVREFDQ_A0==77
841 08:36:32.174169 TrainedVREFDQ_A1==77
842 08:36:32.178915 VrefDac_Margin_A0==22
843 08:36:32.179378 DeviceVref_Margin_A0==37
844 08:36:32.184521 VrefDac_Margin_A1==24
845 08:36:32.184988 DeviceVref_Margin_A1==37
846 08:36:32.185379
847 08:36:32.190029 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 08:36:32.190492
849 08:36:32.217878 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
850 08:36:32.223519 2D training succeed
851 08:36:32.229132 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 08:36:32.229604 auto size-- 65535DDR cs0 size: 2048MB
853 08:36:32.234714 DDR cs1 size: 2048MB
854 08:36:32.235172 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 08:36:32.240318 cs0 DataBus test pass
856 08:36:32.240787 cs1 DataBus test pass
857 08:36:32.241182 cs0 AddrBus test pass
858 08:36:32.245966 cs1 AddrBus test pass
859 08:36:32.246425
860 08:36:32.246817 100bdlr_step_size ps== 420
861 08:36:32.247212 result report
862 08:36:32.251551 boot times 0Enable ddr reg access
863 08:36:32.259274 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 08:36:32.272679 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 08:36:32.846318 0.0;M3 CHK:0;cm4_sp_mode 0
866 08:36:32.846926 MVN_1=0x00000000
867 08:36:32.851850 MVN_2=0x00000000
868 08:36:32.857598 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 08:36:32.858086 OPS=0x10
870 08:36:32.858509 ring efuse init
871 08:36:32.858914 chipver efuse init
872 08:36:32.865854 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 08:36:32.866346 [0.018961 Inits done]
874 08:36:32.866756 secure task start!
875 08:36:32.873403 high task start!
876 08:36:32.873880 low task start!
877 08:36:32.874292 run into bl31
878 08:36:32.880031 NOTICE: BL31: v1.3(release):4fc40b1
879 08:36:32.887821 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 08:36:32.888341 NOTICE: BL31: G12A normal boot!
881 08:36:32.913163 NOTICE: BL31: BL33 decompress pass
882 08:36:32.918844 ERROR: Error initializing runtime service opteed_fast
883 08:36:34.151654
884 08:36:34.152334
885 08:36:34.160207 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 08:36:34.160991
887 08:36:34.161683 Model: Libre Computer AML-A311D-CC Alta
888 08:36:34.368618 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 08:36:34.391971 DRAM: 2 GiB (effective 3.8 GiB)
890 08:36:34.534861 Core: 408 devices, 31 uclasses, devicetree: separate
891 08:36:34.540970 WDT: Not starting watchdog@f0d0
892 08:36:34.573112 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 08:36:34.585688 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 08:36:34.590531 ** Bad device specification mmc 0 **
895 08:36:34.600843 Card did not respond to voltage select! : -110
896 08:36:34.608565 ** Bad device specification mmc 0 **
897 08:36:34.609067 Couldn't find partition mmc 0
898 08:36:34.616856 Card did not respond to voltage select! : -110
899 08:36:34.622362 ** Bad device specification mmc 0 **
900 08:36:34.622865 Couldn't find partition mmc 0
901 08:36:34.627413 Error: could not access storage.
902 08:36:34.969866 Net: eth0: ethernet@ff3f0000
903 08:36:34.970452 starting USB...
904 08:36:35.221721 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 08:36:35.222318 Starting the controller
906 08:36:35.228724 USB XHCI 1.10
907 08:36:37.090007 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
908 08:36:37.090592 bl2_stage_init 0x01
909 08:36:37.091026 bl2_stage_init 0x81
910 08:36:37.095451 hw id: 0x0000 - pwm id 0x01
911 08:36:37.095932 bl2_stage_init 0xc1
912 08:36:37.096405 bl2_stage_init 0x02
913 08:36:37.096827
914 08:36:37.101045 L0:00000000
915 08:36:37.101526 L1:20000703
916 08:36:37.101948 L2:00008067
917 08:36:37.102354 L3:14000000
918 08:36:37.106676 B2:00402000
919 08:36:37.107163 B1:e0f83180
920 08:36:37.107587
921 08:36:37.108033 TE: 58150
922 08:36:37.108451
923 08:36:37.112312 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
924 08:36:37.112797
925 08:36:37.113223 Board ID = 1
926 08:36:37.117928 Set A53 clk to 24M
927 08:36:37.118404 Set A73 clk to 24M
928 08:36:37.118823 Set clk81 to 24M
929 08:36:37.123444 A53 clk: 1200 MHz
930 08:36:37.123910 A73 clk: 1200 MHz
931 08:36:37.124359 CLK81: 166.6M
932 08:36:37.124763 smccc: 00012aac
933 08:36:37.129115 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
934 08:36:37.134741 board id: 1
935 08:36:37.140529 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
936 08:36:37.151259 fw parse done
937 08:36:37.157219 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
938 08:36:37.199897 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
939 08:36:37.210701 PIEI prepare done
940 08:36:37.211180 fastboot data load
941 08:36:37.211577 fastboot data verify
942 08:36:37.216552 verify result: 266
943 08:36:37.222228 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
944 08:36:37.222698 LPDDR4 probe
945 08:36:37.223090 ddr clk to 1584MHz
946 08:36:37.230098 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
947 08:36:37.267403
948 08:36:37.267945 dmc_version 0001
949 08:36:37.274105 Check phy result
950 08:36:37.279910 INFO : End of CA training
951 08:36:37.280425 INFO : End of initialization
952 08:36:37.285497 INFO : Training has run successfully!
953 08:36:37.285971 Check phy result
954 08:36:37.291313 INFO : End of initialization
955 08:36:37.291834 INFO : End of read enable training
956 08:36:37.294505 INFO : End of fine write leveling
957 08:36:37.300010 INFO : End of Write leveling coarse delay
958 08:36:37.305642 INFO : Training has run successfully!
959 08:36:37.306120 Check phy result
960 08:36:37.306556 INFO : End of initialization
961 08:36:37.311282 INFO : End of read dq deskew training
962 08:36:37.316571 INFO : End of MPR read delay center optimization
963 08:36:37.317064 INFO : End of write delay center optimization
964 08:36:37.322198 INFO : End of read delay center optimization
965 08:36:37.327873 INFO : End of max read latency training
966 08:36:37.328405 INFO : Training has run successfully!
967 08:36:37.333425 1D training succeed
968 08:36:37.339313 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
969 08:36:37.386872 Check phy result
970 08:36:37.387406 INFO : End of initialization
971 08:36:37.408525 INFO : End of 2D read delay Voltage center optimization
972 08:36:37.428618 INFO : End of 2D read delay Voltage center optimization
973 08:36:37.480642 INFO : End of 2D write delay Voltage center optimization
974 08:36:37.529843 INFO : End of 2D write delay Voltage center optimization
975 08:36:37.535431 INFO : Training has run successfully!
976 08:36:37.535946
977 08:36:37.536409 channel==0
978 08:36:37.541018 RxClkDly_Margin_A0==88 ps 9
979 08:36:37.541512 TxDqDly_Margin_A0==98 ps 10
980 08:36:37.546586 RxClkDly_Margin_A1==88 ps 9
981 08:36:37.547068 TxDqDly_Margin_A1==98 ps 10
982 08:36:37.547487 TrainedVREFDQ_A0==74
983 08:36:37.552262 TrainedVREFDQ_A1==74
984 08:36:37.552766 VrefDac_Margin_A0==25
985 08:36:37.553177 DeviceVref_Margin_A0==40
986 08:36:37.557813 VrefDac_Margin_A1==25
987 08:36:37.558292 DeviceVref_Margin_A1==40
988 08:36:37.558702
989 08:36:37.559109
990 08:36:37.563399 channel==1
991 08:36:37.563873 RxClkDly_Margin_A0==98 ps 10
992 08:36:37.564322 TxDqDly_Margin_A0==88 ps 9
993 08:36:37.569101 RxClkDly_Margin_A1==98 ps 10
994 08:36:37.569583 TxDqDly_Margin_A1==88 ps 9
995 08:36:37.574582 TrainedVREFDQ_A0==76
996 08:36:37.575110 TrainedVREFDQ_A1==77
997 08:36:37.575517 VrefDac_Margin_A0==22
998 08:36:37.580265 DeviceVref_Margin_A0==38
999 08:36:37.580773 VrefDac_Margin_A1==22
1000 08:36:37.585770 DeviceVref_Margin_A1==37
1001 08:36:37.586251
1002 08:36:37.586663 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1003 08:36:37.587067
1004 08:36:37.619379 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1005 08:36:37.619975 2D training succeed
1006 08:36:37.625135 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1007 08:36:37.630607 auto size-- 65535DDR cs0 size: 2048MB
1008 08:36:37.631097 DDR cs1 size: 2048MB
1009 08:36:37.636257 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1010 08:36:37.636750 cs0 DataBus test pass
1011 08:36:37.641804 cs1 DataBus test pass
1012 08:36:37.642294 cs0 AddrBus test pass
1013 08:36:37.642706 cs1 AddrBus test pass
1014 08:36:37.643113
1015 08:36:37.647439 100bdlr_step_size ps== 420
1016 08:36:37.647943 result report
1017 08:36:37.653127 boot times 0Enable ddr reg access
1018 08:36:37.658352 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1019 08:36:37.671751 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1020 08:36:38.243687 0.0;M3 CHK:0;cm4_sp_mode 0
1021 08:36:38.244374 MVN_1=0x00000000
1022 08:36:38.249252 MVN_2=0x00000000
1023 08:36:38.255095 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1024 08:36:38.255606 OPS=0x10
1025 08:36:38.256095 ring efuse init
1026 08:36:38.256539 chipver efuse init
1027 08:36:38.260829 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1028 08:36:38.266256 [0.018961 Inits done]
1029 08:36:38.266795 secure task start!
1030 08:36:38.267258 high task start!
1031 08:36:38.270813 low task start!
1032 08:36:38.271334 run into bl31
1033 08:36:38.277481 NOTICE: BL31: v1.3(release):4fc40b1
1034 08:36:38.285279 NOTICE: BL31: Built : 15:58:17, May 22 2019
1035 08:36:38.285800 NOTICE: BL31: G12A normal boot!
1036 08:36:38.310616 NOTICE: BL31: BL33 decompress pass
1037 08:36:38.316324 ERROR: Error initializing runtime service opteed_fast
1038 08:36:39.549256
1039 08:36:39.549911
1040 08:36:39.557649 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1041 08:36:39.558183
1042 08:36:39.558627 Model: Libre Computer AML-A311D-CC Alta
1043 08:36:39.766632 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1044 08:36:39.789514 DRAM: 2 GiB (effective 3.8 GiB)
1045 08:36:39.932479 Core: 408 devices, 31 uclasses, devicetree: separate
1046 08:36:39.938459 WDT: Not starting watchdog@f0d0
1047 08:36:39.970671 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1048 08:36:39.982978 Loading Environment from FAT... Card did not respond to voltage select! : -110
1049 08:36:39.988068 ** Bad device specification mmc 0 **
1050 08:36:39.998464 Card did not respond to voltage select! : -110
1051 08:36:40.006115 ** Bad device specification mmc 0 **
1052 08:36:40.006736 Couldn't find partition mmc 0
1053 08:36:40.014378 Card did not respond to voltage select! : -110
1054 08:36:40.019888 ** Bad device specification mmc 0 **
1055 08:36:40.020544 Couldn't find partition mmc 0
1056 08:36:40.025797 Error: could not access storage.
1057 08:36:40.367483 Net: eth0: ethernet@ff3f0000
1058 08:36:40.368148 starting USB...
1059 08:36:40.619168 Bus usb@ff500000: Register 3000140 NbrPorts 3
1060 08:36:40.619775 Starting the controller
1061 08:36:40.626157 USB XHCI 1.10
1062 08:36:42.180175 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1063 08:36:42.188530 scanning usb for storage devices... 0 Storage Device(s) found
1065 08:36:42.240232 Hit any key to stop autoboot: 1
1066 08:36:42.241199 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1067 08:36:42.241955 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1068 08:36:42.242429 Setting prompt string to ['=>']
1069 08:36:42.242901 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1070 08:36:42.256233 0
1071 08:36:42.257380 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1072 08:36:42.258010 Sending with 10 millisecond of delay
1074 08:36:43.393972 => setenv autoload no
1075 08:36:43.404860 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1076 08:36:43.410526 setenv autoload no
1077 08:36:43.411628 Sending with 10 millisecond of delay
1079 08:36:45.210483 => setenv initrd_high 0xffffffff
1080 08:36:45.221566 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1081 08:36:45.222651 setenv initrd_high 0xffffffff
1082 08:36:45.223468 Sending with 10 millisecond of delay
1084 08:36:46.846463 => setenv fdt_high 0xffffffff
1085 08:36:46.857097 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1086 08:36:46.857783 setenv fdt_high 0xffffffff
1087 08:36:46.858259 Sending with 10 millisecond of delay
1089 08:36:47.150803 => dhcp
1090 08:36:47.161595 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1091 08:36:47.162494 dhcp
1092 08:36:47.162940 Speed: 1000, full duplex
1093 08:36:47.163348 BOOTP broadcast 1
1094 08:36:47.170344 DHCP client bound to address 192.168.6.27 (8 ms)
1095 08:36:47.171185 Sending with 10 millisecond of delay
1097 08:36:48.849523 => setenv serverip 192.168.6.2
1098 08:36:48.860432 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1099 08:36:48.861487 setenv serverip 192.168.6.2
1100 08:36:48.862289 Sending with 10 millisecond of delay
1102 08:36:52.588574 => tftpboot 0x01080000 933546/tftp-deploy-xje3o1jg/kernel/uImage
1103 08:36:52.599376 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1104 08:36:52.600294 tftpboot 0x01080000 933546/tftp-deploy-xje3o1jg/kernel/uImage
1105 08:36:52.600788 Speed: 1000, full duplex
1106 08:36:52.601247 Using ethernet@ff3f0000 device
1107 08:36:52.602233 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1108 08:36:52.607626 Filename '933546/tftp-deploy-xje3o1jg/kernel/uImage'.
1109 08:36:52.611766 Load address: 0x1080000
1110 08:36:55.634694 Loading: *################################################## 43.6 MiB
1111 08:36:55.635382 14.4 MiB/s
1112 08:36:55.635941 done
1113 08:36:55.638034 Bytes transferred = 45713984 (2b98a40 hex)
1114 08:36:55.638849 Sending with 10 millisecond of delay
1116 08:37:00.326723 => tftpboot 0x08000000 933546/tftp-deploy-xje3o1jg/ramdisk/ramdisk.cpio.gz.uboot
1117 08:37:00.337518 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1118 08:37:00.338408 tftpboot 0x08000000 933546/tftp-deploy-xje3o1jg/ramdisk/ramdisk.cpio.gz.uboot
1119 08:37:00.338899 Speed: 1000, full duplex
1120 08:37:00.339360 Using ethernet@ff3f0000 device
1121 08:37:00.340427 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1122 08:37:00.351432 Filename '933546/tftp-deploy-xje3o1jg/ramdisk/ramdisk.cpio.gz.uboot'.
1123 08:37:00.351964 Load address: 0x8000000
1124 08:37:04.810640 Loading: *########### UDP wrong checksum 000000ff 0000b72e
1125 08:37:04.911918 UDP wrong checksum 000000ff 00005021
1126 08:37:05.608496 UDP wrong checksum 000000ff 0000cac5
1127 08:37:07.688641 T ###################################### UDP wrong checksum 00000005 0000a492
1128 08:37:12.689150 T UDP wrong checksum 00000005 0000a492
1129 08:37:22.691483 T T UDP wrong checksum 00000005 0000a492
1130 08:37:42.695325 T T T T UDP wrong checksum 00000005 0000a492
1131 08:37:57.699262 T T
1132 08:37:57.699947 Retry count exceeded; starting again
1134 08:37:57.701607 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1137 08:37:57.703665 end: 2.4 uboot-commands (duration 00:01:53) [common]
1139 08:37:57.705305 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1141 08:37:57.706489 end: 2 uboot-action (duration 00:01:53) [common]
1143 08:37:57.708192 Cleaning after the job
1144 08:37:57.708831 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933546/tftp-deploy-xje3o1jg/ramdisk
1145 08:37:57.710040 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933546/tftp-deploy-xje3o1jg/kernel
1146 08:37:57.759528 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933546/tftp-deploy-xje3o1jg/dtb
1147 08:37:57.760351 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933546/tftp-deploy-xje3o1jg/modules
1148 08:37:57.782211 start: 4.1 power-off (timeout 00:00:30) [common]
1149 08:37:57.782890 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1150 08:37:57.817792 >> OK - accepted request
1151 08:37:57.819890 Returned 0 in 0 seconds
1152 08:37:57.921160 end: 4.1 power-off (duration 00:00:00) [common]
1154 08:37:57.922945 start: 4.2 read-feedback (timeout 00:10:00) [common]
1155 08:37:57.924120 Listened to connection for namespace 'common' for up to 1s
1156 08:37:58.924159 Finalising connection for namespace 'common'
1157 08:37:58.924941 Disconnecting from shell: Finalise
1158 08:37:58.925505 =>
1159 08:37:59.026545 end: 4.2 read-feedback (duration 00:00:01) [common]
1160 08:37:59.027277 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/933546
1161 08:37:59.327492 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/933546
1162 08:37:59.328357 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.