Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 08:38:28.323492 lava-dispatcher, installed at version: 2024.01
2 08:38:28.324339 start: 0 validate
3 08:38:28.324830 Start time: 2024-11-04 08:38:28.324801+00:00 (UTC)
4 08:38:28.325413 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 08:38:28.325986 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 08:38:28.363669 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 08:38:28.364240 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-328-gf46306bca74bb%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 08:38:28.394633 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 08:38:28.395249 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-328-gf46306bca74bb%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 08:38:28.434024 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 08:38:28.434757 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 08:38:28.471075 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 08:38:28.471563 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-328-gf46306bca74bb%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 08:38:28.515140 validate duration: 0.19
16 08:38:28.516657 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 08:38:28.517268 start: 1.1 download-retry (timeout 00:10:00) [common]
18 08:38:28.517866 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 08:38:28.518830 Not decompressing ramdisk as can be used compressed.
20 08:38:28.519578 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 08:38:28.520124 saving as /var/lib/lava/dispatcher/tmp/933560/tftp-deploy-q36k5rji/ramdisk/initrd.cpio.gz
22 08:38:28.520645 total size: 5628182 (5 MB)
23 08:38:28.562835 progress 0 % (0 MB)
24 08:38:28.570545 progress 5 % (0 MB)
25 08:38:28.578621 progress 10 % (0 MB)
26 08:38:28.585911 progress 15 % (0 MB)
27 08:38:28.593650 progress 20 % (1 MB)
28 08:38:28.598447 progress 25 % (1 MB)
29 08:38:28.602506 progress 30 % (1 MB)
30 08:38:28.606570 progress 35 % (1 MB)
31 08:38:28.610244 progress 40 % (2 MB)
32 08:38:28.614250 progress 45 % (2 MB)
33 08:38:28.617888 progress 50 % (2 MB)
34 08:38:28.621987 progress 55 % (2 MB)
35 08:38:28.625978 progress 60 % (3 MB)
36 08:38:28.629646 progress 65 % (3 MB)
37 08:38:28.633735 progress 70 % (3 MB)
38 08:38:28.637431 progress 75 % (4 MB)
39 08:38:28.641398 progress 80 % (4 MB)
40 08:38:28.644991 progress 85 % (4 MB)
41 08:38:28.649038 progress 90 % (4 MB)
42 08:38:28.652979 progress 95 % (5 MB)
43 08:38:28.656362 progress 100 % (5 MB)
44 08:38:28.657029 5 MB downloaded in 0.14 s (39.36 MB/s)
45 08:38:28.657580 end: 1.1.1 http-download (duration 00:00:00) [common]
47 08:38:28.658502 end: 1.1 download-retry (duration 00:00:00) [common]
48 08:38:28.658813 start: 1.2 download-retry (timeout 00:10:00) [common]
49 08:38:28.659096 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 08:38:28.659557 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-328-gf46306bca74bb/arm64/defconfig/gcc-12/kernel/Image
51 08:38:28.659807 saving as /var/lib/lava/dispatcher/tmp/933560/tftp-deploy-q36k5rji/kernel/Image
52 08:38:28.660046 total size: 45713920 (43 MB)
53 08:38:28.660270 No compression specified
54 08:38:28.698937 progress 0 % (0 MB)
55 08:38:28.727422 progress 5 % (2 MB)
56 08:38:28.755264 progress 10 % (4 MB)
57 08:38:28.783003 progress 15 % (6 MB)
58 08:38:28.810939 progress 20 % (8 MB)
59 08:38:28.838155 progress 25 % (10 MB)
60 08:38:28.866486 progress 30 % (13 MB)
61 08:38:28.894296 progress 35 % (15 MB)
62 08:38:28.922019 progress 40 % (17 MB)
63 08:38:28.949608 progress 45 % (19 MB)
64 08:38:28.977444 progress 50 % (21 MB)
65 08:38:29.005412 progress 55 % (24 MB)
66 08:38:29.033027 progress 60 % (26 MB)
67 08:38:29.060587 progress 65 % (28 MB)
68 08:38:29.088294 progress 70 % (30 MB)
69 08:38:29.116136 progress 75 % (32 MB)
70 08:38:29.144414 progress 80 % (34 MB)
71 08:38:29.171748 progress 85 % (37 MB)
72 08:38:29.199670 progress 90 % (39 MB)
73 08:38:29.227462 progress 95 % (41 MB)
74 08:38:29.254680 progress 100 % (43 MB)
75 08:38:29.255203 43 MB downloaded in 0.60 s (73.25 MB/s)
76 08:38:29.255694 end: 1.2.1 http-download (duration 00:00:01) [common]
78 08:38:29.256560 end: 1.2 download-retry (duration 00:00:01) [common]
79 08:38:29.256857 start: 1.3 download-retry (timeout 00:09:59) [common]
80 08:38:29.257138 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 08:38:29.257616 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-328-gf46306bca74bb/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 08:38:29.257894 saving as /var/lib/lava/dispatcher/tmp/933560/tftp-deploy-q36k5rji/dtb/meson-g12b-a311d-libretech-cc.dtb
83 08:38:29.258109 total size: 54703 (0 MB)
84 08:38:29.258324 No compression specified
85 08:38:29.296704 progress 59 % (0 MB)
86 08:38:29.297533 progress 100 % (0 MB)
87 08:38:29.298078 0 MB downloaded in 0.04 s (1.31 MB/s)
88 08:38:29.298541 end: 1.3.1 http-download (duration 00:00:00) [common]
90 08:38:29.299355 end: 1.3 download-retry (duration 00:00:00) [common]
91 08:38:29.299619 start: 1.4 download-retry (timeout 00:09:59) [common]
92 08:38:29.299883 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 08:38:29.300393 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 08:38:29.300641 saving as /var/lib/lava/dispatcher/tmp/933560/tftp-deploy-q36k5rji/nfsrootfs/full.rootfs.tar
95 08:38:29.300845 total size: 107552908 (102 MB)
96 08:38:29.301055 Using unxz to decompress xz
97 08:38:29.343909 progress 0 % (0 MB)
98 08:38:29.982330 progress 5 % (5 MB)
99 08:38:30.701946 progress 10 % (10 MB)
100 08:38:31.424970 progress 15 % (15 MB)
101 08:38:32.184582 progress 20 % (20 MB)
102 08:38:32.754074 progress 25 % (25 MB)
103 08:38:33.372708 progress 30 % (30 MB)
104 08:38:34.106332 progress 35 % (35 MB)
105 08:38:34.453997 progress 40 % (41 MB)
106 08:38:34.885731 progress 45 % (46 MB)
107 08:38:35.578647 progress 50 % (51 MB)
108 08:38:36.260163 progress 55 % (56 MB)
109 08:38:37.019694 progress 60 % (61 MB)
110 08:38:37.774463 progress 65 % (66 MB)
111 08:38:38.505492 progress 70 % (71 MB)
112 08:38:39.320990 progress 75 % (76 MB)
113 08:38:40.004436 progress 80 % (82 MB)
114 08:38:40.725024 progress 85 % (87 MB)
115 08:38:41.471252 progress 90 % (92 MB)
116 08:38:42.184204 progress 95 % (97 MB)
117 08:38:42.932177 progress 100 % (102 MB)
118 08:38:42.943866 102 MB downloaded in 13.64 s (7.52 MB/s)
119 08:38:42.944904 end: 1.4.1 http-download (duration 00:00:14) [common]
121 08:38:42.946717 end: 1.4 download-retry (duration 00:00:14) [common]
122 08:38:42.947287 start: 1.5 download-retry (timeout 00:09:46) [common]
123 08:38:42.947850 start: 1.5.1 http-download (timeout 00:09:46) [common]
124 08:38:42.948824 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-328-gf46306bca74bb/arm64/defconfig/gcc-12/modules.tar.xz
125 08:38:42.949343 saving as /var/lib/lava/dispatcher/tmp/933560/tftp-deploy-q36k5rji/modules/modules.tar
126 08:38:42.949790 total size: 11614628 (11 MB)
127 08:38:42.950252 Using unxz to decompress xz
128 08:38:42.989529 progress 0 % (0 MB)
129 08:38:43.068253 progress 5 % (0 MB)
130 08:38:43.156326 progress 10 % (1 MB)
131 08:38:43.270950 progress 15 % (1 MB)
132 08:38:43.381353 progress 20 % (2 MB)
133 08:38:43.476131 progress 25 % (2 MB)
134 08:38:43.553789 progress 30 % (3 MB)
135 08:38:43.632528 progress 35 % (3 MB)
136 08:38:43.705005 progress 40 % (4 MB)
137 08:38:43.781013 progress 45 % (5 MB)
138 08:38:43.865133 progress 50 % (5 MB)
139 08:38:43.942481 progress 55 % (6 MB)
140 08:38:44.027447 progress 60 % (6 MB)
141 08:38:44.107717 progress 65 % (7 MB)
142 08:38:44.187891 progress 70 % (7 MB)
143 08:38:44.265671 progress 75 % (8 MB)
144 08:38:44.348637 progress 80 % (8 MB)
145 08:38:44.428924 progress 85 % (9 MB)
146 08:38:44.512865 progress 90 % (10 MB)
147 08:38:44.586886 progress 95 % (10 MB)
148 08:38:44.663799 progress 100 % (11 MB)
149 08:38:44.675659 11 MB downloaded in 1.73 s (6.42 MB/s)
150 08:38:44.676654 end: 1.5.1 http-download (duration 00:00:02) [common]
152 08:38:44.678406 end: 1.5 download-retry (duration 00:00:02) [common]
153 08:38:44.678986 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
154 08:38:44.679587 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
155 08:38:54.499660 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/933560/extract-nfsrootfs-x6scdy91
156 08:38:54.500332 end: 1.6.1 extract-nfsrootfs (duration 00:00:10) [common]
157 08:38:54.500688 start: 1.6.2 lava-overlay (timeout 00:09:34) [common]
158 08:38:54.501810 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u
159 08:38:54.502623 makedir: /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin
160 08:38:54.503226 makedir: /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/tests
161 08:38:54.503692 makedir: /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/results
162 08:38:54.504277 Creating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin/lava-add-keys
163 08:38:54.505146 Creating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin/lava-add-sources
164 08:38:54.505827 Creating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin/lava-background-process-start
165 08:38:54.506429 Creating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin/lava-background-process-stop
166 08:38:54.507052 Creating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin/lava-common-functions
167 08:38:54.507897 Creating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin/lava-echo-ipv4
168 08:38:54.508804 Creating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin/lava-install-packages
169 08:38:54.509718 Creating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin/lava-installed-packages
170 08:38:54.510463 Creating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin/lava-os-build
171 08:38:54.511299 Creating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin/lava-probe-channel
172 08:38:54.511961 Creating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin/lava-probe-ip
173 08:38:54.512605 Creating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin/lava-target-ip
174 08:38:54.513163 Creating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin/lava-target-mac
175 08:38:54.513864 Creating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin/lava-target-storage
176 08:38:54.514729 Creating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin/lava-test-case
177 08:38:54.515585 Creating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin/lava-test-event
178 08:38:54.516356 Creating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin/lava-test-feedback
179 08:38:54.517119 Creating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin/lava-test-raise
180 08:38:54.517970 Creating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin/lava-test-reference
181 08:38:54.518587 Creating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin/lava-test-runner
182 08:38:54.519156 Creating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin/lava-test-set
183 08:38:54.519859 Creating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin/lava-test-shell
184 08:38:54.520591 Updating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin/lava-install-packages (oe)
185 08:38:54.521203 Updating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/bin/lava-installed-packages (oe)
186 08:38:54.521880 Creating /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/environment
187 08:38:54.522566 LAVA metadata
188 08:38:54.522948 - LAVA_JOB_ID=933560
189 08:38:54.523215 - LAVA_DISPATCHER_IP=192.168.6.2
190 08:38:54.523629 start: 1.6.2.1 ssh-authorize (timeout 00:09:34) [common]
191 08:38:54.525070 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 08:38:54.525508 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:34) [common]
193 08:38:54.525839 skipped lava-vland-overlay
194 08:38:54.526187 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 08:38:54.526563 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:34) [common]
196 08:38:54.526885 skipped lava-multinode-overlay
197 08:38:54.527172 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 08:38:54.527433 start: 1.6.2.4 test-definition (timeout 00:09:34) [common]
199 08:38:54.527694 Loading test definitions
200 08:38:54.528004 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:34) [common]
201 08:38:54.528235 Using /lava-933560 at stage 0
202 08:38:54.529477 uuid=933560_1.6.2.4.1 testdef=None
203 08:38:54.529789 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 08:38:54.530051 start: 1.6.2.4.2 test-overlay (timeout 00:09:34) [common]
205 08:38:54.531897 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 08:38:54.532827 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:34) [common]
208 08:38:54.535750 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 08:38:54.537166 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:34) [common]
211 08:38:54.540309 runner path: /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/0/tests/0_dmesg test_uuid 933560_1.6.2.4.1
212 08:38:54.541021 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 08:38:54.541833 Creating lava-test-runner.conf files
215 08:38:54.542038 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/933560/lava-overlay-qjrm_b7u/lava-933560/0 for stage 0
216 08:38:54.542414 - 0_dmesg
217 08:38:54.542811 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 08:38:54.543101 start: 1.6.2.5 compress-overlay (timeout 00:09:34) [common]
219 08:38:54.565285 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 08:38:54.565703 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:34) [common]
221 08:38:54.565967 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 08:38:54.566239 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 08:38:54.566508 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
224 08:38:55.272878 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 08:38:55.273389 start: 1.6.4 extract-modules (timeout 00:09:33) [common]
226 08:38:55.273683 extracting modules file /var/lib/lava/dispatcher/tmp/933560/tftp-deploy-q36k5rji/modules/modules.tar to /var/lib/lava/dispatcher/tmp/933560/extract-nfsrootfs-x6scdy91
227 08:38:56.666626 extracting modules file /var/lib/lava/dispatcher/tmp/933560/tftp-deploy-q36k5rji/modules/modules.tar to /var/lib/lava/dispatcher/tmp/933560/extract-overlay-ramdisk-fz2zg2r1/ramdisk
228 08:38:58.204021 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 08:38:58.204530 start: 1.6.5 apply-overlay-tftp (timeout 00:09:30) [common]
230 08:38:58.204817 [common] Applying overlay to NFS
231 08:38:58.205038 [common] Applying overlay /var/lib/lava/dispatcher/tmp/933560/compress-overlay-qwad38dh/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/933560/extract-nfsrootfs-x6scdy91
232 08:38:58.247408 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 08:38:58.247873 start: 1.6.6 prepare-kernel (timeout 00:09:30) [common]
234 08:38:58.248208 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:30) [common]
235 08:38:58.248512 Converting downloaded kernel to a uImage
236 08:38:58.248997 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/933560/tftp-deploy-q36k5rji/kernel/Image /var/lib/lava/dispatcher/tmp/933560/tftp-deploy-q36k5rji/kernel/uImage
237 08:38:58.730130 output: Image Name:
238 08:38:58.730564 output: Created: Mon Nov 4 08:38:58 2024
239 08:38:58.730777 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 08:38:58.730983 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 08:38:58.731184 output: Load Address: 01080000
242 08:38:58.731384 output: Entry Point: 01080000
243 08:38:58.731583 output:
244 08:38:58.731920 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 08:38:58.732241 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 08:38:58.732515 start: 1.6.7 configure-preseed-file (timeout 00:09:30) [common]
247 08:38:58.732773 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 08:38:58.733037 start: 1.6.8 compress-ramdisk (timeout 00:09:30) [common]
249 08:38:58.733295 Building ramdisk /var/lib/lava/dispatcher/tmp/933560/extract-overlay-ramdisk-fz2zg2r1/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/933560/extract-overlay-ramdisk-fz2zg2r1/ramdisk
250 08:39:00.959331 >> 166824 blocks
251 08:39:08.701264 Adding RAMdisk u-boot header.
252 08:39:08.701706 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/933560/extract-overlay-ramdisk-fz2zg2r1/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/933560/extract-overlay-ramdisk-fz2zg2r1/ramdisk.cpio.gz.uboot
253 08:39:08.987748 output: Image Name:
254 08:39:08.988222 output: Created: Mon Nov 4 08:39:08 2024
255 08:39:08.988464 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 08:39:08.988684 output: Data Size: 23432419 Bytes = 22883.22 KiB = 22.35 MiB
257 08:39:08.988898 output: Load Address: 00000000
258 08:39:08.989110 output: Entry Point: 00000000
259 08:39:08.989318 output:
260 08:39:08.992112 rename /var/lib/lava/dispatcher/tmp/933560/extract-overlay-ramdisk-fz2zg2r1/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/933560/tftp-deploy-q36k5rji/ramdisk/ramdisk.cpio.gz.uboot
261 08:39:08.992828 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 08:39:08.993170 end: 1.6 prepare-tftp-overlay (duration 00:00:24) [common]
263 08:39:08.993477 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
264 08:39:08.993989 No LXC device requested
265 08:39:08.994290 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 08:39:08.994581 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
267 08:39:08.994857 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 08:39:08.995086 Checking files for TFTP limit of 4294967296 bytes.
269 08:39:08.997127 end: 1 tftp-deploy (duration 00:00:40) [common]
270 08:39:08.997502 start: 2 uboot-action (timeout 00:05:00) [common]
271 08:39:08.997801 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 08:39:08.998077 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 08:39:08.998357 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 08:39:08.998664 Using kernel file from prepare-kernel: 933560/tftp-deploy-q36k5rji/kernel/uImage
275 08:39:08.999020 substitutions:
276 08:39:08.999247 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 08:39:08.999465 - {DTB_ADDR}: 0x01070000
278 08:39:08.999676 - {DTB}: 933560/tftp-deploy-q36k5rji/dtb/meson-g12b-a311d-libretech-cc.dtb
279 08:39:08.999886 - {INITRD}: 933560/tftp-deploy-q36k5rji/ramdisk/ramdisk.cpio.gz.uboot
280 08:39:09.000137 - {KERNEL_ADDR}: 0x01080000
281 08:39:09.000353 - {KERNEL}: 933560/tftp-deploy-q36k5rji/kernel/uImage
282 08:39:09.000563 - {LAVA_MAC}: None
283 08:39:09.000803 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/933560/extract-nfsrootfs-x6scdy91
284 08:39:09.001024 - {NFS_SERVER_IP}: 192.168.6.2
285 08:39:09.001235 - {PRESEED_CONFIG}: None
286 08:39:09.001447 - {PRESEED_LOCAL}: None
287 08:39:09.001654 - {RAMDISK_ADDR}: 0x08000000
288 08:39:09.001860 - {RAMDISK}: 933560/tftp-deploy-q36k5rji/ramdisk/ramdisk.cpio.gz.uboot
289 08:39:09.002069 - {ROOT_PART}: None
290 08:39:09.002283 - {ROOT}: None
291 08:39:09.002493 - {SERVER_IP}: 192.168.6.2
292 08:39:09.002698 - {TEE_ADDR}: 0x83000000
293 08:39:09.002901 - {TEE}: None
294 08:39:09.003107 Parsed boot commands:
295 08:39:09.003309 - setenv autoload no
296 08:39:09.003515 - setenv initrd_high 0xffffffff
297 08:39:09.003721 - setenv fdt_high 0xffffffff
298 08:39:09.003927 - dhcp
299 08:39:09.004170 - setenv serverip 192.168.6.2
300 08:39:09.004376 - tftpboot 0x01080000 933560/tftp-deploy-q36k5rji/kernel/uImage
301 08:39:09.004583 - tftpboot 0x08000000 933560/tftp-deploy-q36k5rji/ramdisk/ramdisk.cpio.gz.uboot
302 08:39:09.004791 - tftpboot 0x01070000 933560/tftp-deploy-q36k5rji/dtb/meson-g12b-a311d-libretech-cc.dtb
303 08:39:09.004996 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/933560/extract-nfsrootfs-x6scdy91,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 08:39:09.005207 - bootm 0x01080000 0x08000000 0x01070000
305 08:39:09.005504 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 08:39:09.006314 start: 2.3 connect-device (timeout 00:05:00) [common]
308 08:39:09.006553 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 08:39:09.019054 Setting prompt string to ['lava-test: # ']
310 08:39:09.020056 end: 2.3 connect-device (duration 00:00:00) [common]
311 08:39:09.020463 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 08:39:09.020806 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 08:39:09.021095 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 08:39:09.021751 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 08:39:09.074498 >> OK - accepted request
316 08:39:09.076853 Returned 0 in 0 seconds
317 08:39:09.178135 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 08:39:09.179290 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 08:39:09.179681 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 08:39:09.180045 Setting prompt string to ['Hit any key to stop autoboot']
322 08:39:09.180327 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 08:39:09.181267 Trying 192.168.56.21...
324 08:39:09.181564 Connected to conserv1.
325 08:39:09.181827 Escape character is '^]'.
326 08:39:09.182088
327 08:39:09.182355 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 08:39:09.182613
329 08:39:21.521284 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
330 08:39:21.521734 bl2_stage_init 0x81
331 08:39:21.526795 hw id: 0x0000 - pwm id 0x01
332 08:39:21.527134 bl2_stage_init 0xc1
333 08:39:21.527348 bl2_stage_init 0x02
334 08:39:21.527551
335 08:39:21.532314 L0:00000000
336 08:39:21.532842 L1:20000703
337 08:39:21.533256 L2:00008067
338 08:39:21.533658 L3:14000000
339 08:39:21.534059 B2:00402000
340 08:39:21.535247 B1:e0f83180
341 08:39:21.535699
342 08:39:21.536170 TE: 58150
343 08:39:21.536577
344 08:39:21.546425 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
345 08:39:21.546892
346 08:39:21.547289 Board ID = 1
347 08:39:21.547681 Set A53 clk to 24M
348 08:39:21.548099 Set A73 clk to 24M
349 08:39:21.552020 Set clk81 to 24M
350 08:39:21.552470 A53 clk: 1200 MHz
351 08:39:21.552859 A73 clk: 1200 MHz
352 08:39:21.557652 CLK81: 166.6M
353 08:39:21.558085 smccc: 00012aac
354 08:39:21.563282 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
355 08:39:21.563739 board id: 1
356 08:39:21.571943 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
357 08:39:21.582225 fw parse done
358 08:39:21.588169 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
359 08:39:21.630742 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
360 08:39:21.641660 PIEI prepare done
361 08:39:21.642121 fastboot data load
362 08:39:21.642516 fastboot data verify
363 08:39:21.647328 verify result: 266
364 08:39:21.652940 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
365 08:39:21.653400 LPDDR4 probe
366 08:39:21.653792 ddr clk to 1584MHz
367 08:39:21.660962 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
368 08:39:21.698196
369 08:39:21.698649 dmc_version 0001
370 08:39:21.704846 Check phy result
371 08:39:21.710697 INFO : End of CA training
372 08:39:21.711127 INFO : End of initialization
373 08:39:21.716323 INFO : Training has run successfully!
374 08:39:21.716755 Check phy result
375 08:39:21.721926 INFO : End of initialization
376 08:39:21.722357 INFO : End of read enable training
377 08:39:21.727603 INFO : End of fine write leveling
378 08:39:21.733120 INFO : End of Write leveling coarse delay
379 08:39:21.733560 INFO : Training has run successfully!
380 08:39:21.733954 Check phy result
381 08:39:21.738682 INFO : End of initialization
382 08:39:21.739112 INFO : End of read dq deskew training
383 08:39:21.744279 INFO : End of MPR read delay center optimization
384 08:39:21.749889 INFO : End of write delay center optimization
385 08:39:21.755661 INFO : End of read delay center optimization
386 08:39:21.756144 INFO : End of max read latency training
387 08:39:21.761140 INFO : Training has run successfully!
388 08:39:21.761579 1D training succeed
389 08:39:21.770282 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 08:39:21.817931 Check phy result
391 08:39:21.818444 INFO : End of initialization
392 08:39:21.840303 INFO : End of 2D read delay Voltage center optimization
393 08:39:21.860429 INFO : End of 2D read delay Voltage center optimization
394 08:39:21.912341 INFO : End of 2D write delay Voltage center optimization
395 08:39:21.961591 INFO : End of 2D write delay Voltage center optimization
396 08:39:21.967138 INFO : Training has run successfully!
397 08:39:21.967584
398 08:39:21.968024 channel==0
399 08:39:21.972776 RxClkDly_Margin_A0==88 ps 9
400 08:39:21.973218 TxDqDly_Margin_A0==98 ps 10
401 08:39:21.978339 RxClkDly_Margin_A1==88 ps 9
402 08:39:21.978769 TxDqDly_Margin_A1==88 ps 9
403 08:39:21.979165 TrainedVREFDQ_A0==74
404 08:39:21.983924 TrainedVREFDQ_A1==74
405 08:39:21.984383 VrefDac_Margin_A0==24
406 08:39:21.984772 DeviceVref_Margin_A0==40
407 08:39:21.989530 VrefDac_Margin_A1==24
408 08:39:21.989956 DeviceVref_Margin_A1==40
409 08:39:21.990342
410 08:39:21.990730
411 08:39:21.991117 channel==1
412 08:39:21.995134 RxClkDly_Margin_A0==88 ps 9
413 08:39:21.995561 TxDqDly_Margin_A0==98 ps 10
414 08:39:22.000735 RxClkDly_Margin_A1==98 ps 10
415 08:39:22.001167 TxDqDly_Margin_A1==88 ps 9
416 08:39:22.006343 TrainedVREFDQ_A0==77
417 08:39:22.006779 TrainedVREFDQ_A1==77
418 08:39:22.007169 VrefDac_Margin_A0==22
419 08:39:22.011933 DeviceVref_Margin_A0==37
420 08:39:22.012395 VrefDac_Margin_A1==24
421 08:39:22.017530 DeviceVref_Margin_A1==37
422 08:39:22.017956
423 08:39:22.018343 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
424 08:39:22.018729
425 08:39:22.051163 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000017 00000018 00000015 00000018 00000018 00000017 00000018 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
426 08:39:22.051880 2D training succeed
427 08:39:22.056846 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
428 08:39:22.062440 auto size-- 65535DDR cs0 size: 2048MB
429 08:39:22.063023 DDR cs1 size: 2048MB
430 08:39:22.068054 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
431 08:39:22.068598 cs0 DataBus test pass
432 08:39:22.073631 cs1 DataBus test pass
433 08:39:22.074156 cs0 AddrBus test pass
434 08:39:22.074599 cs1 AddrBus test pass
435 08:39:22.075032
436 08:39:22.079198 100bdlr_step_size ps== 420
437 08:39:22.079732 result report
438 08:39:22.084782 boot times 0Enable ddr reg access
439 08:39:22.090079 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
440 08:39:22.103496 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
441 08:39:22.675447 0.0;M3 CHK:0;cm4_sp_mode 0
442 08:39:22.675876 MVN_1=0x00000000
443 08:39:22.680890 MVN_2=0x00000000
444 08:39:22.686637 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
445 08:39:22.686960 OPS=0x10
446 08:39:22.687183 ring efuse init
447 08:39:22.687388 chipver efuse init
448 08:39:22.692276 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
449 08:39:22.697868 [0.018960 Inits done]
450 08:39:22.698206 secure task start!
451 08:39:22.698445 high task start!
452 08:39:22.702449 low task start!
453 08:39:22.702783 run into bl31
454 08:39:22.709065 NOTICE: BL31: v1.3(release):4fc40b1
455 08:39:22.716894 NOTICE: BL31: Built : 15:58:17, May 22 2019
456 08:39:22.717237 NOTICE: BL31: G12A normal boot!
457 08:39:22.742234 NOTICE: BL31: BL33 decompress pass
458 08:39:22.747892 ERROR: Error initializing runtime service opteed_fast
459 08:39:23.982351
460 08:39:23.983317
461 08:39:23.989150 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
462 08:39:23.989520
463 08:39:23.989771 Model: Libre Computer AML-A311D-CC Alta
464 08:39:24.197653 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
465 08:39:24.221043 DRAM: 2 GiB (effective 3.8 GiB)
466 08:39:24.363975 Core: 408 devices, 31 uclasses, devicetree: separate
467 08:39:24.370109 WDT: Not starting watchdog@f0d0
468 08:39:24.403235 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
469 08:39:24.414734 Loading Environment from FAT... Card did not respond to voltage select! : -110
470 08:39:24.419699 ** Bad device specification mmc 0 **
471 08:39:24.430034 Card did not respond to voltage select! : -110
472 08:39:24.437709 ** Bad device specification mmc 0 **
473 08:39:24.438098 Couldn't find partition mmc 0
474 08:39:24.448585 Card did not respond to voltage select! : -110
475 08:39:24.453128 ** Bad device specification mmc 0 **
476 08:39:24.453566 Couldn't find partition mmc 0
477 08:39:24.456384 Error: could not access storage.
478 08:39:25.721596 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
479 08:39:25.722012 bl2_stage_init 0x01
480 08:39:25.722241 bl2_stage_init 0x81
481 08:39:25.727135 hw id: 0x0000 - pwm id 0x01
482 08:39:25.727452 bl2_stage_init 0xc1
483 08:39:25.727686 bl2_stage_init 0x02
484 08:39:25.727899
485 08:39:25.732546 L0:00000000
486 08:39:25.732804 L1:20000703
487 08:39:25.733015 L2:00008067
488 08:39:25.733225 L3:14000000
489 08:39:25.738129 B2:00402000
490 08:39:25.738428 B1:e0f83180
491 08:39:25.738631
492 08:39:25.738830 TE: 58167
493 08:39:25.739027
494 08:39:25.743714 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
495 08:39:25.744016
496 08:39:25.744232 Board ID = 1
497 08:39:25.749417 Set A53 clk to 24M
498 08:39:25.749768 Set A73 clk to 24M
499 08:39:25.749997 Set clk81 to 24M
500 08:39:25.755051 A53 clk: 1200 MHz
501 08:39:25.755424 A73 clk: 1200 MHz
502 08:39:25.755885 CLK81: 166.6M
503 08:39:25.756376 smccc: 00012abd
504 08:39:25.760557 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
505 08:39:25.766149 board id: 1
506 08:39:25.772203 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
507 08:39:25.782826 fw parse done
508 08:39:25.788943 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
509 08:39:25.831325 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
510 08:39:25.842182 PIEI prepare done
511 08:39:25.842694 fastboot data load
512 08:39:25.843154 fastboot data verify
513 08:39:25.848615 verify result: 266
514 08:39:25.853473 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
515 08:39:25.853963 LPDDR4 probe
516 08:39:25.854409 ddr clk to 1584MHz
517 08:39:25.861450 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
518 08:39:25.898705
519 08:39:25.899214 dmc_version 0001
520 08:39:25.905385 Check phy result
521 08:39:25.911241 INFO : End of CA training
522 08:39:25.911727 INFO : End of initialization
523 08:39:25.916838 INFO : Training has run successfully!
524 08:39:25.917320 Check phy result
525 08:39:25.922482 INFO : End of initialization
526 08:39:25.923007 INFO : End of read enable training
527 08:39:25.928066 INFO : End of fine write leveling
528 08:39:25.933685 INFO : End of Write leveling coarse delay
529 08:39:25.934175 INFO : Training has run successfully!
530 08:39:25.934624 Check phy result
531 08:39:25.939252 INFO : End of initialization
532 08:39:25.939728 INFO : End of read dq deskew training
533 08:39:25.944840 INFO : End of MPR read delay center optimization
534 08:39:25.950442 INFO : End of write delay center optimization
535 08:39:25.956066 INFO : End of read delay center optimization
536 08:39:25.956563 INFO : End of max read latency training
537 08:39:25.961665 INFO : Training has run successfully!
538 08:39:25.962143 1D training succeed
539 08:39:25.970835 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 08:39:26.018466 Check phy result
541 08:39:26.018967 INFO : End of initialization
542 08:39:26.040404 INFO : End of 2D read delay Voltage center optimization
543 08:39:26.060477 INFO : End of 2D read delay Voltage center optimization
544 08:39:26.112507 INFO : End of 2D write delay Voltage center optimization
545 08:39:26.161855 INFO : End of 2D write delay Voltage center optimization
546 08:39:26.167297 INFO : Training has run successfully!
547 08:39:26.167793
548 08:39:26.168294 channel==0
549 08:39:26.172934 RxClkDly_Margin_A0==88 ps 9
550 08:39:26.173437 TxDqDly_Margin_A0==98 ps 10
551 08:39:26.178488 RxClkDly_Margin_A1==88 ps 9
552 08:39:26.178967 TxDqDly_Margin_A1==88 ps 9
553 08:39:26.179418 TrainedVREFDQ_A0==74
554 08:39:26.184189 TrainedVREFDQ_A1==74
555 08:39:26.184684 VrefDac_Margin_A0==25
556 08:39:26.185135 DeviceVref_Margin_A0==40
557 08:39:26.189705 VrefDac_Margin_A1==25
558 08:39:26.190180 DeviceVref_Margin_A1==40
559 08:39:26.190617
560 08:39:26.191057
561 08:39:26.191494 channel==1
562 08:39:26.195292 RxClkDly_Margin_A0==98 ps 10
563 08:39:26.195772 TxDqDly_Margin_A0==98 ps 10
564 08:39:26.200946 RxClkDly_Margin_A1==98 ps 10
565 08:39:26.201424 TxDqDly_Margin_A1==88 ps 9
566 08:39:26.206491 TrainedVREFDQ_A0==77
567 08:39:26.206973 TrainedVREFDQ_A1==77
568 08:39:26.207417 VrefDac_Margin_A0==22
569 08:39:26.212166 DeviceVref_Margin_A0==37
570 08:39:26.212650 VrefDac_Margin_A1==22
571 08:39:26.217689 DeviceVref_Margin_A1==37
572 08:39:26.218182
573 08:39:26.218632 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
574 08:39:26.219072
575 08:39:26.251331 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
576 08:39:26.251945 2D training succeed
577 08:39:26.256923 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
578 08:39:26.262500 auto size-- 65535DDR cs0 size: 2048MB
579 08:39:26.262985 DDR cs1 size: 2048MB
580 08:39:26.268189 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
581 08:39:26.268676 cs0 DataBus test pass
582 08:39:26.273730 cs1 DataBus test pass
583 08:39:26.274206 cs0 AddrBus test pass
584 08:39:26.274652 cs1 AddrBus test pass
585 08:39:26.275087
586 08:39:26.279307 100bdlr_step_size ps== 420
587 08:39:26.279797 result report
588 08:39:26.284904 boot times 0Enable ddr reg access
589 08:39:26.290249 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
590 08:39:26.303747 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
591 08:39:26.878117 0.0;M3 CHK:0;cm4_sp_mode 0
592 08:39:26.878781 MVN_1=0x00000000
593 08:39:26.883123 MVN_2=0x00000000
594 08:39:26.888905 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
595 08:39:26.889429 OPS=0x10
596 08:39:26.889911 ring efuse init
597 08:39:26.890369 chipver efuse init
598 08:39:26.897469 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
599 08:39:26.898025 [0.018961 Inits done]
600 08:39:26.898462 secure task start!
601 08:39:26.904683 high task start!
602 08:39:26.905159 low task start!
603 08:39:26.905590 run into bl31
604 08:39:26.911293 NOTICE: BL31: v1.3(release):4fc40b1
605 08:39:26.919146 NOTICE: BL31: Built : 15:58:17, May 22 2019
606 08:39:26.919623 NOTICE: BL31: G12A normal boot!
607 08:39:26.944578 NOTICE: BL31: BL33 decompress pass
608 08:39:26.950097 ERROR: Error initializing runtime service opteed_fast
609 08:39:28.183319
610 08:39:28.184053
611 08:39:28.191409 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
612 08:39:28.191904
613 08:39:28.192415 Model: Libre Computer AML-A311D-CC Alta
614 08:39:28.399932 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
615 08:39:28.423268 DRAM: 2 GiB (effective 3.8 GiB)
616 08:39:28.566308 Core: 408 devices, 31 uclasses, devicetree: separate
617 08:39:28.572054 WDT: Not starting watchdog@f0d0
618 08:39:28.604294 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
619 08:39:28.616776 Loading Environment from FAT... Card did not respond to voltage select! : -110
620 08:39:28.621716 ** Bad device specification mmc 0 **
621 08:39:28.632046 Card did not respond to voltage select! : -110
622 08:39:28.639692 ** Bad device specification mmc 0 **
623 08:39:28.640225 Couldn't find partition mmc 0
624 08:39:28.648061 Card did not respond to voltage select! : -110
625 08:39:28.653670 ** Bad device specification mmc 0 **
626 08:39:28.654155 Couldn't find partition mmc 0
627 08:39:28.658685 Error: could not access storage.
628 08:39:29.001216 Net: eth0: ethernet@ff3f0000
629 08:39:29.001650 starting USB...
630 08:39:29.252980 Bus usb@ff500000: Register 3000140 NbrPorts 3
631 08:39:29.253561 Starting the controller
632 08:39:29.259885 USB XHCI 1.10
633 08:39:30.972630 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
634 08:39:30.973045 bl2_stage_init 0x01
635 08:39:30.973277 bl2_stage_init 0x81
636 08:39:30.978237 hw id: 0x0000 - pwm id 0x01
637 08:39:30.978554 bl2_stage_init 0xc1
638 08:39:30.978778 bl2_stage_init 0x02
639 08:39:30.978989
640 08:39:30.983621 L0:00000000
641 08:39:30.984067 L1:20000703
642 08:39:30.984413 L2:00008067
643 08:39:30.984743 L3:14000000
644 08:39:30.986703 B2:00402000
645 08:39:30.987099 B1:e0f83180
646 08:39:30.987429
647 08:39:30.987670 TE: 58159
648 08:39:30.987883
649 08:39:30.998245 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
650 08:39:30.998590
651 08:39:30.998808 Board ID = 1
652 08:39:30.999012 Set A53 clk to 24M
653 08:39:30.999212 Set A73 clk to 24M
654 08:39:31.003573 Set clk81 to 24M
655 08:39:31.004029 A53 clk: 1200 MHz
656 08:39:31.004381 A73 clk: 1200 MHz
657 08:39:31.007306 CLK81: 166.6M
658 08:39:31.007723 smccc: 00012ab4
659 08:39:31.012860 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
660 08:39:31.013296 board id: 1
661 08:39:31.023329 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
662 08:39:31.033705 fw parse done
663 08:39:31.039642 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
664 08:39:31.082257 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
665 08:39:31.093232 PIEI prepare done
666 08:39:31.093543 fastboot data load
667 08:39:31.093767 fastboot data verify
668 08:39:31.098889 verify result: 266
669 08:39:31.104399 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
670 08:39:31.104820 LPDDR4 probe
671 08:39:31.105060 ddr clk to 1584MHz
672 08:39:31.112368 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
673 08:39:31.149653
674 08:39:31.150149 dmc_version 0001
675 08:39:31.156318 Check phy result
676 08:39:31.162185 INFO : End of CA training
677 08:39:31.162476 INFO : End of initialization
678 08:39:31.167892 INFO : Training has run successfully!
679 08:39:31.168363 Check phy result
680 08:39:31.173378 INFO : End of initialization
681 08:39:31.173664 INFO : End of read enable training
682 08:39:31.178990 INFO : End of fine write leveling
683 08:39:31.184584 INFO : End of Write leveling coarse delay
684 08:39:31.184871 INFO : Training has run successfully!
685 08:39:31.185082 Check phy result
686 08:39:31.190186 INFO : End of initialization
687 08:39:31.190607 INFO : End of read dq deskew training
688 08:39:31.195877 INFO : End of MPR read delay center optimization
689 08:39:31.201428 INFO : End of write delay center optimization
690 08:39:31.206999 INFO : End of read delay center optimization
691 08:39:31.207506 INFO : End of max read latency training
692 08:39:31.212559 INFO : Training has run successfully!
693 08:39:31.213077 1D training succeed
694 08:39:31.221782 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 08:39:31.269444 Check phy result
696 08:39:31.270026 INFO : End of initialization
697 08:39:31.291155 INFO : End of 2D read delay Voltage center optimization
698 08:39:31.311382 INFO : End of 2D read delay Voltage center optimization
699 08:39:31.363419 INFO : End of 2D write delay Voltage center optimization
700 08:39:31.412756 INFO : End of 2D write delay Voltage center optimization
701 08:39:31.418292 INFO : Training has run successfully!
702 08:39:31.418796
703 08:39:31.419258 channel==0
704 08:39:31.423896 RxClkDly_Margin_A0==88 ps 9
705 08:39:31.424448 TxDqDly_Margin_A0==98 ps 10
706 08:39:31.429490 RxClkDly_Margin_A1==88 ps 9
707 08:39:31.429996 TxDqDly_Margin_A1==98 ps 10
708 08:39:31.430458 TrainedVREFDQ_A0==74
709 08:39:31.435094 TrainedVREFDQ_A1==74
710 08:39:31.435597 VrefDac_Margin_A0==25
711 08:39:31.436082 DeviceVref_Margin_A0==40
712 08:39:31.440702 VrefDac_Margin_A1==24
713 08:39:31.441202 DeviceVref_Margin_A1==40
714 08:39:31.441656
715 08:39:31.442101
716 08:39:31.446290 channel==1
717 08:39:31.446791 RxClkDly_Margin_A0==98 ps 10
718 08:39:31.447247 TxDqDly_Margin_A0==88 ps 9
719 08:39:31.451900 RxClkDly_Margin_A1==88 ps 9
720 08:39:31.452424 TxDqDly_Margin_A1==88 ps 9
721 08:39:31.457470 TrainedVREFDQ_A0==76
722 08:39:31.457971 TrainedVREFDQ_A1==77
723 08:39:31.458429 VrefDac_Margin_A0==22
724 08:39:31.463089 DeviceVref_Margin_A0==38
725 08:39:31.463591 VrefDac_Margin_A1==24
726 08:39:31.468685 DeviceVref_Margin_A1==37
727 08:39:31.469184
728 08:39:31.469638 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
729 08:39:31.470086
730 08:39:31.502283 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
731 08:39:31.502828 2D training succeed
732 08:39:31.507910 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
733 08:39:31.513477 auto size-- 65535DDR cs0 size: 2048MB
734 08:39:31.513980 DDR cs1 size: 2048MB
735 08:39:31.519112 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
736 08:39:31.519613 cs0 DataBus test pass
737 08:39:31.524687 cs1 DataBus test pass
738 08:39:31.525185 cs0 AddrBus test pass
739 08:39:31.525641 cs1 AddrBus test pass
740 08:39:31.526088
741 08:39:31.530275 100bdlr_step_size ps== 420
742 08:39:31.530787 result report
743 08:39:31.535932 boot times 0Enable ddr reg access
744 08:39:31.541138 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
745 08:39:31.554629 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
746 08:39:32.128346 0.0;M3 CHK:0;cm4_sp_mode 0
747 08:39:32.128773 MVN_1=0x00000000
748 08:39:32.133857 MVN_2=0x00000000
749 08:39:32.139572 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
750 08:39:32.140179 OPS=0x10
751 08:39:32.140645 ring efuse init
752 08:39:32.141083 chipver efuse init
753 08:39:32.145149 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
754 08:39:32.150804 [0.018961 Inits done]
755 08:39:32.151344 secure task start!
756 08:39:32.151791 high task start!
757 08:39:32.155349 low task start!
758 08:39:32.155902 run into bl31
759 08:39:32.162039 NOTICE: BL31: v1.3(release):4fc40b1
760 08:39:32.169831 NOTICE: BL31: Built : 15:58:17, May 22 2019
761 08:39:32.170385 NOTICE: BL31: G12A normal boot!
762 08:39:32.195174 NOTICE: BL31: BL33 decompress pass
763 08:39:32.200845 ERROR: Error initializing runtime service opteed_fast
764 08:39:33.433770
765 08:39:33.434198
766 08:39:33.442255 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
767 08:39:33.442611
768 08:39:33.442835 Model: Libre Computer AML-A311D-CC Alta
769 08:39:33.650631 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
770 08:39:33.673949 DRAM: 2 GiB (effective 3.8 GiB)
771 08:39:33.817030 Core: 408 devices, 31 uclasses, devicetree: separate
772 08:39:33.822842 WDT: Not starting watchdog@f0d0
773 08:39:33.855173 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
774 08:39:33.867591 Loading Environment from FAT... Card did not respond to voltage select! : -110
775 08:39:33.872531 ** Bad device specification mmc 0 **
776 08:39:33.882880 Card did not respond to voltage select! : -110
777 08:39:33.890536 ** Bad device specification mmc 0 **
778 08:39:33.890897 Couldn't find partition mmc 0
779 08:39:33.898856 Card did not respond to voltage select! : -110
780 08:39:33.904358 ** Bad device specification mmc 0 **
781 08:39:33.904821 Couldn't find partition mmc 0
782 08:39:33.909433 Error: could not access storage.
783 08:39:34.253028 Net: eth0: ethernet@ff3f0000
784 08:39:34.253447 starting USB...
785 08:39:34.504859 Bus usb@ff500000: Register 3000140 NbrPorts 3
786 08:39:34.505280 Starting the controller
787 08:39:34.511784 USB XHCI 1.10
788 08:39:36.672474 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
789 08:39:36.672910 bl2_stage_init 0x01
790 08:39:36.673172 bl2_stage_init 0x81
791 08:39:36.677437 hw id: 0x0000 - pwm id 0x01
792 08:39:36.677904 bl2_stage_init 0xc1
793 08:39:36.678310 bl2_stage_init 0x02
794 08:39:36.678705
795 08:39:36.683310 L0:00000000
796 08:39:36.683768 L1:20000703
797 08:39:36.684113 L2:00008067
798 08:39:36.684377 L3:14000000
799 08:39:36.686290 B2:00402000
800 08:39:36.686616 B1:e0f83180
801 08:39:36.686863
802 08:39:36.687122 TE: 58124
803 08:39:36.687369
804 08:39:36.697340 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
805 08:39:36.697727
806 08:39:36.697985 Board ID = 1
807 08:39:36.698224 Set A53 clk to 24M
808 08:39:36.698453 Set A73 clk to 24M
809 08:39:36.703119 Set clk81 to 24M
810 08:39:36.703619 A53 clk: 1200 MHz
811 08:39:36.704067 A73 clk: 1200 MHz
812 08:39:36.708340 CLK81: 166.6M
813 08:39:36.708845 smccc: 00012a92
814 08:39:36.713847 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
815 08:39:36.714347 board id: 1
816 08:39:36.722566 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
817 08:39:36.733161 fw parse done
818 08:39:36.739165 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
819 08:39:36.781645 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
820 08:39:36.792565 PIEI prepare done
821 08:39:36.793058 fastboot data load
822 08:39:36.793359 fastboot data verify
823 08:39:36.798146 verify result: 266
824 08:39:36.803746 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
825 08:39:36.804132 LPDDR4 probe
826 08:39:36.804586 ddr clk to 1584MHz
827 08:39:36.811923 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
828 08:39:36.849117
829 08:39:36.849658 dmc_version 0001
830 08:39:36.855800 Check phy result
831 08:39:36.861699 INFO : End of CA training
832 08:39:36.862190 INFO : End of initialization
833 08:39:36.867228 INFO : Training has run successfully!
834 08:39:36.867717 Check phy result
835 08:39:36.872869 INFO : End of initialization
836 08:39:36.873360 INFO : End of read enable training
837 08:39:36.876200 INFO : End of fine write leveling
838 08:39:36.881706 INFO : End of Write leveling coarse delay
839 08:39:36.887293 INFO : Training has run successfully!
840 08:39:36.887804 Check phy result
841 08:39:36.888269 INFO : End of initialization
842 08:39:36.892903 INFO : End of read dq deskew training
843 08:39:36.898505 INFO : End of MPR read delay center optimization
844 08:39:36.899004 INFO : End of write delay center optimization
845 08:39:36.904142 INFO : End of read delay center optimization
846 08:39:36.909707 INFO : End of max read latency training
847 08:39:36.910194 INFO : Training has run successfully!
848 08:39:36.915298 1D training succeed
849 08:39:36.921301 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 08:39:36.968890 Check phy result
851 08:39:36.969436 INFO : End of initialization
852 08:39:36.990462 INFO : End of 2D read delay Voltage center optimization
853 08:39:37.010565 INFO : End of 2D read delay Voltage center optimization
854 08:39:37.062440 INFO : End of 2D write delay Voltage center optimization
855 08:39:37.111731 INFO : End of 2D write delay Voltage center optimization
856 08:39:37.117340 INFO : Training has run successfully!
857 08:39:37.117838
858 08:39:37.118255 channel==0
859 08:39:37.122907 RxClkDly_Margin_A0==88 ps 9
860 08:39:37.123395 TxDqDly_Margin_A0==98 ps 10
861 08:39:37.126214 RxClkDly_Margin_A1==88 ps 9
862 08:39:37.126696 TxDqDly_Margin_A1==88 ps 9
863 08:39:37.131820 TrainedVREFDQ_A0==74
864 08:39:37.132355 TrainedVREFDQ_A1==74
865 08:39:37.132793 VrefDac_Margin_A0==25
866 08:39:37.137430 DeviceVref_Margin_A0==40
867 08:39:37.137954 VrefDac_Margin_A1==24
868 08:39:37.142962 DeviceVref_Margin_A1==40
869 08:39:37.143483
870 08:39:37.143869
871 08:39:37.144290 channel==1
872 08:39:37.144674 RxClkDly_Margin_A0==88 ps 9
873 08:39:37.148594 TxDqDly_Margin_A0==98 ps 10
874 08:39:37.149081 RxClkDly_Margin_A1==88 ps 9
875 08:39:37.154133 TxDqDly_Margin_A1==98 ps 10
876 08:39:37.154612 TrainedVREFDQ_A0==77
877 08:39:37.155000 TrainedVREFDQ_A1==77
878 08:39:37.159710 VrefDac_Margin_A0==22
879 08:39:37.160212 DeviceVref_Margin_A0==37
880 08:39:37.165321 VrefDac_Margin_A1==24
881 08:39:37.165786 DeviceVref_Margin_A1==37
882 08:39:37.166175
883 08:39:37.170973 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
884 08:39:37.171445
885 08:39:37.198906 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
886 08:39:37.204543 2D training succeed
887 08:39:37.209973 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
888 08:39:37.210444 auto size-- 65535DDR cs0 size: 2048MB
889 08:39:37.215586 DDR cs1 size: 2048MB
890 08:39:37.216100 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
891 08:39:37.221213 cs0 DataBus test pass
892 08:39:37.221680 cs1 DataBus test pass
893 08:39:37.222069 cs0 AddrBus test pass
894 08:39:37.226824 cs1 AddrBus test pass
895 08:39:37.227304
896 08:39:37.227696 100bdlr_step_size ps== 420
897 08:39:37.228122 result report
898 08:39:37.232406 boot times 0Enable ddr reg access
899 08:39:37.240117 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
900 08:39:37.253463 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
901 08:39:37.825529 0.0;M3 CHK:0;cm4_sp_mode 0
902 08:39:37.826138 MVN_1=0x00000000
903 08:39:37.831023 MVN_2=0x00000000
904 08:39:37.836782 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
905 08:39:37.837263 OPS=0x10
906 08:39:37.837674 ring efuse init
907 08:39:37.838068 chipver efuse init
908 08:39:37.842393 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
909 08:39:37.847973 [0.018960 Inits done]
910 08:39:37.848512 secure task start!
911 08:39:37.848923 high task start!
912 08:39:37.852567 low task start!
913 08:39:37.853044 run into bl31
914 08:39:37.859212 NOTICE: BL31: v1.3(release):4fc40b1
915 08:39:37.867028 NOTICE: BL31: Built : 15:58:17, May 22 2019
916 08:39:37.867513 NOTICE: BL31: G12A normal boot!
917 08:39:37.892429 NOTICE: BL31: BL33 decompress pass
918 08:39:37.898110 ERROR: Error initializing runtime service opteed_fast
919 08:39:39.131005
920 08:39:39.131611
921 08:39:39.139392 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
922 08:39:39.139898
923 08:39:39.140357 Model: Libre Computer AML-A311D-CC Alta
924 08:39:39.347841 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
925 08:39:39.371327 DRAM: 2 GiB (effective 3.8 GiB)
926 08:39:39.514226 Core: 408 devices, 31 uclasses, devicetree: separate
927 08:39:39.520100 WDT: Not starting watchdog@f0d0
928 08:39:39.552307 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
929 08:39:39.564743 Loading Environment from FAT... Card did not respond to voltage select! : -110
930 08:39:39.569777 ** Bad device specification mmc 0 **
931 08:39:39.580196 Card did not respond to voltage select! : -110
932 08:39:39.594093 ** Bad device specification mmc 0 **
933 08:39:39.594749 Couldn't find partition mmc 0
934 08:39:39.599921 Card did not respond to voltage select! : -110
935 08:39:39.600255 ** Bad device specification mmc 0 **
936 08:39:39.606706 Couldn't find partition mmc 0
937 08:39:39.607221 Error: could not access storage.
938 08:39:39.948990 Net: eth0: ethernet@ff3f0000
939 08:39:39.949405 starting USB...
940 08:39:40.200863 Bus usb@ff500000: Register 3000140 NbrPorts 3
941 08:39:40.201298 Starting the controller
942 08:39:40.207811 USB XHCI 1.10
943 08:39:42.071771 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
944 08:39:42.072564 bl2_stage_init 0x01
945 08:39:42.072789 bl2_stage_init 0x81
946 08:39:42.077641 hw id: 0x0000 - pwm id 0x01
947 08:39:42.078053 bl2_stage_init 0xc1
948 08:39:42.078264 bl2_stage_init 0x02
949 08:39:42.078464
950 08:39:42.082835 L0:00000000
951 08:39:42.083246 L1:20000703
952 08:39:42.084597 L2:00008067
953 08:39:42.085094 L3:14000000
954 08:39:42.088508 B2:00402000
955 08:39:42.089115 B1:e0f83180
956 08:39:42.089596
957 08:39:42.090075 TE: 58124
958 08:39:42.090548
959 08:39:42.094121 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
960 08:39:42.094733
961 08:39:42.095224 Board ID = 1
962 08:39:42.099614 Set A53 clk to 24M
963 08:39:42.100238 Set A73 clk to 24M
964 08:39:42.100716 Set clk81 to 24M
965 08:39:42.105256 A53 clk: 1200 MHz
966 08:39:42.105847 A73 clk: 1200 MHz
967 08:39:42.106312 CLK81: 166.6M
968 08:39:42.106824 smccc: 00012a92
969 08:39:42.110828 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
970 08:39:42.116411 board id: 1
971 08:39:42.122316 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
972 08:39:42.132924 fw parse done
973 08:39:42.138935 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
974 08:39:42.181518 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
975 08:39:42.192385 PIEI prepare done
976 08:39:42.192868 fastboot data load
977 08:39:42.193303 fastboot data verify
978 08:39:42.198080 verify result: 266
979 08:39:42.203668 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
980 08:39:42.204188 LPDDR4 probe
981 08:39:42.204620 ddr clk to 1584MHz
982 08:39:42.211868 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
983 08:39:42.249086
984 08:39:42.249576 dmc_version 0001
985 08:39:42.255731 Check phy result
986 08:39:42.261598 INFO : End of CA training
987 08:39:42.262074 INFO : End of initialization
988 08:39:42.267183 INFO : Training has run successfully!
989 08:39:42.267699 Check phy result
990 08:39:42.272741 INFO : End of initialization
991 08:39:42.273262 INFO : End of read enable training
992 08:39:42.276168 INFO : End of fine write leveling
993 08:39:42.281718 INFO : End of Write leveling coarse delay
994 08:39:42.287373 INFO : Training has run successfully!
995 08:39:42.287858 Check phy result
996 08:39:42.288354 INFO : End of initialization
997 08:39:42.292878 INFO : End of read dq deskew training
998 08:39:42.298646 INFO : End of MPR read delay center optimization
999 08:39:42.299137 INFO : End of write delay center optimization
1000 08:39:42.304137 INFO : End of read delay center optimization
1001 08:39:42.309719 INFO : End of max read latency training
1002 08:39:42.310204 INFO : Training has run successfully!
1003 08:39:42.315223 1D training succeed
1004 08:39:42.321081 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 08:39:42.368666 Check phy result
1006 08:39:42.369167 INFO : End of initialization
1007 08:39:42.391190 INFO : End of 2D read delay Voltage center optimization
1008 08:39:42.411493 INFO : End of 2D read delay Voltage center optimization
1009 08:39:42.463541 INFO : End of 2D write delay Voltage center optimization
1010 08:39:42.512961 INFO : End of 2D write delay Voltage center optimization
1011 08:39:42.518625 INFO : Training has run successfully!
1012 08:39:42.519127
1013 08:39:42.519590 channel==0
1014 08:39:42.524210 RxClkDly_Margin_A0==88 ps 9
1015 08:39:42.524720 TxDqDly_Margin_A0==98 ps 10
1016 08:39:42.527596 RxClkDly_Margin_A1==88 ps 9
1017 08:39:42.528113 TxDqDly_Margin_A1==98 ps 10
1018 08:39:42.533049 TrainedVREFDQ_A0==74
1019 08:39:42.533540 TrainedVREFDQ_A1==74
1020 08:39:42.533999 VrefDac_Margin_A0==24
1021 08:39:42.538673 DeviceVref_Margin_A0==40
1022 08:39:42.539163 VrefDac_Margin_A1==24
1023 08:39:42.544277 DeviceVref_Margin_A1==40
1024 08:39:42.544771
1025 08:39:42.545225
1026 08:39:42.545667 channel==1
1027 08:39:42.546106 RxClkDly_Margin_A0==98 ps 10
1028 08:39:42.547804 TxDqDly_Margin_A0==88 ps 9
1029 08:39:42.553326 RxClkDly_Margin_A1==98 ps 10
1030 08:39:42.553813 TxDqDly_Margin_A1==88 ps 9
1031 08:39:42.554270 TrainedVREFDQ_A0==75
1032 08:39:42.558955 TrainedVREFDQ_A1==77
1033 08:39:42.559450 VrefDac_Margin_A0==22
1034 08:39:42.564657 DeviceVref_Margin_A0==38
1035 08:39:42.565150 VrefDac_Margin_A1==22
1036 08:39:42.565598 DeviceVref_Margin_A1==37
1037 08:39:42.566033
1038 08:39:42.573664 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1039 08:39:42.574156
1040 08:39:42.599446 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 0000005f
1041 08:39:42.604994 2D training succeed
1042 08:39:42.608626 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1043 08:39:42.613958 auto size-- 65535DDR cs0 size: 2048MB
1044 08:39:42.614444 DDR cs1 size: 2048MB
1045 08:39:42.619539 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1046 08:39:42.620057 cs0 DataBus test pass
1047 08:39:42.625155 cs1 DataBus test pass
1048 08:39:42.625644 cs0 AddrBus test pass
1049 08:39:42.626090 cs1 AddrBus test pass
1050 08:39:42.626532
1051 08:39:42.630751 100bdlr_step_size ps== 420
1052 08:39:42.631251 result report
1053 08:39:42.636346 boot times 0Enable ddr reg access
1054 08:39:42.641326 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1055 08:39:42.654840 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1056 08:39:43.228644 0.0;M3 CHK:0;cm4_sp_mode 0
1057 08:39:43.229277 MVN_1=0x00000000
1058 08:39:43.234027 MVN_2=0x00000000
1059 08:39:43.239762 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1060 08:39:43.240297 OPS=0x10
1061 08:39:43.240726 ring efuse init
1062 08:39:43.241137 chipver efuse init
1063 08:39:43.245424 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1064 08:39:43.250950 [0.018961 Inits done]
1065 08:39:43.251425 secure task start!
1066 08:39:43.251835 high task start!
1067 08:39:43.255647 low task start!
1068 08:39:43.256149 run into bl31
1069 08:39:43.262212 NOTICE: BL31: v1.3(release):4fc40b1
1070 08:39:43.270028 NOTICE: BL31: Built : 15:58:17, May 22 2019
1071 08:39:43.270524 NOTICE: BL31: G12A normal boot!
1072 08:39:43.295372 NOTICE: BL31: BL33 decompress pass
1073 08:39:43.301052 ERROR: Error initializing runtime service opteed_fast
1074 08:39:44.533883
1075 08:39:44.534486
1076 08:39:44.542360 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1077 08:39:44.542864
1078 08:39:44.543286 Model: Libre Computer AML-A311D-CC Alta
1079 08:39:44.750768 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1080 08:39:44.774163 DRAM: 2 GiB (effective 3.8 GiB)
1081 08:39:44.917061 Core: 408 devices, 31 uclasses, devicetree: separate
1082 08:39:44.922983 WDT: Not starting watchdog@f0d0
1083 08:39:44.955190 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1084 08:39:44.967659 Loading Environment from FAT... Card did not respond to voltage select! : -110
1085 08:39:44.972677 ** Bad device specification mmc 0 **
1086 08:39:44.983005 Card did not respond to voltage select! : -110
1087 08:39:44.990628 ** Bad device specification mmc 0 **
1088 08:39:44.991126 Couldn't find partition mmc 0
1089 08:39:44.999005 Card did not respond to voltage select! : -110
1090 08:39:45.004521 ** Bad device specification mmc 0 **
1091 08:39:45.005008 Couldn't find partition mmc 0
1092 08:39:45.009567 Error: could not access storage.
1093 08:39:45.352037 Net: eth0: ethernet@ff3f0000
1094 08:39:45.352637 starting USB...
1095 08:39:45.603844 Bus usb@ff500000: Register 3000140 NbrPorts 3
1096 08:39:45.604501 Starting the controller
1097 08:39:45.610942 USB XHCI 1.10
1098 08:39:47.167883 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1099 08:39:47.176231 scanning usb for storage devices... 0 Storage Device(s) found
1101 08:39:47.227333 Hit any key to stop autoboot: 1
1102 08:39:47.227949 end: 2.4.2 bootloader-interrupt (duration 00:00:38) [common]
1103 08:39:47.228355 start: 2.4.3 bootloader-commands (timeout 00:04:22) [common]
1104 08:39:47.228656 Setting prompt string to ['=>']
1105 08:39:47.228951 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:22)
1106 08:39:47.233585 0
1107 08:39:47.234208 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1108 08:39:47.234519 Sending with 10 millisecond of delay
1110 08:39:48.369166 => setenv autoload no
1111 08:39:48.380050 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1112 08:39:48.385432 setenv autoload no
1113 08:39:48.386236 Sending with 10 millisecond of delay
1115 08:39:50.183698 => setenv initrd_high 0xffffffff
1116 08:39:50.194541 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1117 08:39:50.195201 setenv initrd_high 0xffffffff
1118 08:39:50.195729 Sending with 10 millisecond of delay
1120 08:39:51.812259 => setenv fdt_high 0xffffffff
1121 08:39:51.823024 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1122 08:39:51.823557 setenv fdt_high 0xffffffff
1123 08:39:51.824069 Sending with 10 millisecond of delay
1125 08:39:52.115542 => dhcp
1126 08:39:52.126234 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1127 08:39:52.127244 dhcp
1128 08:39:52.127747 Speed: 1000, full duplex
1129 08:39:52.128273 BOOTP broadcast 1
1130 08:39:52.135889 DHCP client bound to address 192.168.6.27 (10 ms)
1131 08:39:52.136694 Sending with 10 millisecond of delay
1133 08:39:53.813750 => setenv serverip 192.168.6.2
1134 08:39:53.824367 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:15)
1135 08:39:53.824976 setenv serverip 192.168.6.2
1136 08:39:53.825490 Sending with 10 millisecond of delay
1138 08:39:57.549557 => tftpboot 0x01080000 933560/tftp-deploy-q36k5rji/kernel/uImage
1139 08:39:57.560345 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
1140 08:39:57.561144 tftpboot 0x01080000 933560/tftp-deploy-q36k5rji/kernel/uImage
1141 08:39:57.561591 Speed: 1000, full duplex
1142 08:39:57.562001 Using ethernet@ff3f0000 device
1143 08:39:57.563092 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1144 08:39:57.568705 Filename '933560/tftp-deploy-q36k5rji/kernel/uImage'.
1145 08:39:57.572413 Load address: 0x1080000
1146 08:40:00.581673 Loading: *################################################## 43.6 MiB
1147 08:40:00.582346 14.5 MiB/s
1148 08:40:00.582830 done
1149 08:40:00.585888 Bytes transferred = 45713984 (2b98a40 hex)
1150 08:40:00.586667 Sending with 10 millisecond of delay
1152 08:40:05.276148 => tftpboot 0x08000000 933560/tftp-deploy-q36k5rji/ramdisk/ramdisk.cpio.gz.uboot
1153 08:40:05.286947 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:04)
1154 08:40:05.287773 tftpboot 0x08000000 933560/tftp-deploy-q36k5rji/ramdisk/ramdisk.cpio.gz.uboot
1155 08:40:05.288264 Speed: 1000, full duplex
1156 08:40:05.288684 Using ethernet@ff3f0000 device
1157 08:40:05.289644 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1158 08:40:05.301484 Filename '933560/tftp-deploy-q36k5rji/ramdisk/ramdisk.cpio.gz.uboot'.
1159 08:40:05.302002 Load address: 0x8000000
1160 08:40:12.192321 Loading: *##################T ############################### UDP wrong checksum 00000005 0000a2f9
1161 08:40:15.275553 UDP wrong checksum 000000ff 0000e723
1162 08:40:15.285671 UDP wrong checksum 000000ff 0000a267
1163 08:40:15.290143 UDP wrong checksum 000000ff 00007016
1164 08:40:15.297022 UDP wrong checksum 000000ff 0000365a
1165 08:40:17.189019 T UDP wrong checksum 00000005 0000a2f9
1166 08:40:27.190850 T T UDP wrong checksum 00000005 0000a2f9
1167 08:40:47.195823 T T T T UDP wrong checksum 00000005 0000a2f9
1168 08:40:48.071049 UDP wrong checksum 000000ff 000093ca
1169 08:40:48.152301 UDP wrong checksum 000000ff 00002cbd
1170 08:41:02.199894 T T
1171 08:41:02.200538 Retry count exceeded; starting again
1173 08:41:02.201990 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1176 08:41:02.203844 end: 2.4 uboot-commands (duration 00:01:53) [common]
1178 08:41:02.205310 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1180 08:41:02.206385 end: 2 uboot-action (duration 00:01:53) [common]
1182 08:41:02.207896 Cleaning after the job
1183 08:41:02.208472 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933560/tftp-deploy-q36k5rji/ramdisk
1184 08:41:02.209592 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933560/tftp-deploy-q36k5rji/kernel
1185 08:41:02.237567 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933560/tftp-deploy-q36k5rji/dtb
1186 08:41:02.238837 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933560/tftp-deploy-q36k5rji/nfsrootfs
1187 08:41:02.333186 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933560/tftp-deploy-q36k5rji/modules
1188 08:41:02.355127 start: 4.1 power-off (timeout 00:00:30) [common]
1189 08:41:02.355820 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1190 08:41:02.387850 >> OK - accepted request
1191 08:41:02.390070 Returned 0 in 0 seconds
1192 08:41:02.490875 end: 4.1 power-off (duration 00:00:00) [common]
1194 08:41:02.491868 start: 4.2 read-feedback (timeout 00:10:00) [common]
1195 08:41:02.492562 Listened to connection for namespace 'common' for up to 1s
1196 08:41:03.493508 Finalising connection for namespace 'common'
1197 08:41:03.493960 Disconnecting from shell: Finalise
1198 08:41:03.494241 =>
1199 08:41:03.594925 end: 4.2 read-feedback (duration 00:00:01) [common]
1200 08:41:03.595540 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/933560
1201 08:41:05.437130 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/933560
1202 08:41:05.437765 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.