Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 08:45:08.605082 lava-dispatcher, installed at version: 2024.01
2 08:45:08.605901 start: 0 validate
3 08:45:08.606400 Start time: 2024-11-04 08:45:08.606369+00:00 (UTC)
4 08:45:08.606967 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 08:45:08.607541 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 08:45:08.647701 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 08:45:08.648279 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-328-gf46306bca74bb%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 08:45:08.682051 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 08:45:08.682694 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-328-gf46306bca74bb%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 08:45:08.714428 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 08:45:08.714964 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-328-gf46306bca74bb%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 08:45:08.755242 validate duration: 0.15
14 08:45:08.756515 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 08:45:08.756936 start: 1.1 download-retry (timeout 00:10:00) [common]
16 08:45:08.757289 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 08:45:08.757978 Not decompressing ramdisk as can be used compressed.
18 08:45:08.758472 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 08:45:08.758757 saving as /var/lib/lava/dispatcher/tmp/933552/tftp-deploy-8rcog5y3/ramdisk/rootfs.cpio.gz
20 08:45:08.759049 total size: 47897469 (45 MB)
21 08:45:08.793501 progress 0 % (0 MB)
22 08:45:08.830717 progress 5 % (2 MB)
23 08:45:08.868638 progress 10 % (4 MB)
24 08:45:08.905852 progress 15 % (6 MB)
25 08:45:08.943828 progress 20 % (9 MB)
26 08:45:08.981025 progress 25 % (11 MB)
27 08:45:09.017927 progress 30 % (13 MB)
28 08:45:09.055286 progress 35 % (16 MB)
29 08:45:09.092075 progress 40 % (18 MB)
30 08:45:09.128547 progress 45 % (20 MB)
31 08:45:09.164983 progress 50 % (22 MB)
32 08:45:09.202156 progress 55 % (25 MB)
33 08:45:09.238950 progress 60 % (27 MB)
34 08:45:09.275328 progress 65 % (29 MB)
35 08:45:09.311734 progress 70 % (32 MB)
36 08:45:09.348212 progress 75 % (34 MB)
37 08:45:09.384733 progress 80 % (36 MB)
38 08:45:09.421402 progress 85 % (38 MB)
39 08:45:09.458576 progress 90 % (41 MB)
40 08:45:09.495935 progress 95 % (43 MB)
41 08:45:09.531631 progress 100 % (45 MB)
42 08:45:09.532568 45 MB downloaded in 0.77 s (59.05 MB/s)
43 08:45:09.533241 end: 1.1.1 http-download (duration 00:00:01) [common]
45 08:45:09.534313 end: 1.1 download-retry (duration 00:00:01) [common]
46 08:45:09.534659 start: 1.2 download-retry (timeout 00:09:59) [common]
47 08:45:09.534988 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 08:45:09.535559 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-328-gf46306bca74bb/arm64/defconfig/gcc-12/kernel/Image
49 08:45:09.535854 saving as /var/lib/lava/dispatcher/tmp/933552/tftp-deploy-8rcog5y3/kernel/Image
50 08:45:09.536145 total size: 45713920 (43 MB)
51 08:45:09.536403 No compression specified
52 08:45:09.578997 progress 0 % (0 MB)
53 08:45:09.612168 progress 5 % (2 MB)
54 08:45:09.645102 progress 10 % (4 MB)
55 08:45:09.678016 progress 15 % (6 MB)
56 08:45:09.711168 progress 20 % (8 MB)
57 08:45:09.743863 progress 25 % (10 MB)
58 08:45:09.776596 progress 30 % (13 MB)
59 08:45:09.810079 progress 35 % (15 MB)
60 08:45:09.845375 progress 40 % (17 MB)
61 08:45:09.878314 progress 45 % (19 MB)
62 08:45:09.911162 progress 50 % (21 MB)
63 08:45:09.943901 progress 55 % (24 MB)
64 08:45:09.977123 progress 60 % (26 MB)
65 08:45:10.009571 progress 65 % (28 MB)
66 08:45:10.042803 progress 70 % (30 MB)
67 08:45:10.076775 progress 75 % (32 MB)
68 08:45:10.110109 progress 80 % (34 MB)
69 08:45:10.142553 progress 85 % (37 MB)
70 08:45:10.175468 progress 90 % (39 MB)
71 08:45:10.208900 progress 95 % (41 MB)
72 08:45:10.241447 progress 100 % (43 MB)
73 08:45:10.242098 43 MB downloaded in 0.71 s (61.76 MB/s)
74 08:45:10.242679 end: 1.2.1 http-download (duration 00:00:01) [common]
76 08:45:10.243663 end: 1.2 download-retry (duration 00:00:01) [common]
77 08:45:10.244025 start: 1.3 download-retry (timeout 00:09:59) [common]
78 08:45:10.244369 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 08:45:10.244926 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-328-gf46306bca74bb/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 08:45:10.245259 saving as /var/lib/lava/dispatcher/tmp/933552/tftp-deploy-8rcog5y3/dtb/meson-g12b-a311d-libretech-cc.dtb
81 08:45:10.245518 total size: 54703 (0 MB)
82 08:45:10.245773 No compression specified
83 08:45:10.290544 progress 59 % (0 MB)
84 08:45:10.291570 progress 100 % (0 MB)
85 08:45:10.292296 0 MB downloaded in 0.05 s (1.12 MB/s)
86 08:45:10.292900 end: 1.3.1 http-download (duration 00:00:00) [common]
88 08:45:10.293879 end: 1.3 download-retry (duration 00:00:00) [common]
89 08:45:10.294197 start: 1.4 download-retry (timeout 00:09:58) [common]
90 08:45:10.294511 start: 1.4.1 http-download (timeout 00:09:58) [common]
91 08:45:10.295064 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-328-gf46306bca74bb/arm64/defconfig/gcc-12/modules.tar.xz
92 08:45:10.295345 saving as /var/lib/lava/dispatcher/tmp/933552/tftp-deploy-8rcog5y3/modules/modules.tar
93 08:45:10.295595 total size: 11614628 (11 MB)
94 08:45:10.295855 Using unxz to decompress xz
95 08:45:10.338554 progress 0 % (0 MB)
96 08:45:10.405110 progress 5 % (0 MB)
97 08:45:10.480192 progress 10 % (1 MB)
98 08:45:10.576466 progress 15 % (1 MB)
99 08:45:10.669318 progress 20 % (2 MB)
100 08:45:10.749171 progress 25 % (2 MB)
101 08:45:10.824899 progress 30 % (3 MB)
102 08:45:10.904583 progress 35 % (3 MB)
103 08:45:10.977856 progress 40 % (4 MB)
104 08:45:11.054503 progress 45 % (5 MB)
105 08:45:11.139336 progress 50 % (5 MB)
106 08:45:11.217264 progress 55 % (6 MB)
107 08:45:11.303072 progress 60 % (6 MB)
108 08:45:11.384060 progress 65 % (7 MB)
109 08:45:11.464913 progress 70 % (7 MB)
110 08:45:11.544297 progress 75 % (8 MB)
111 08:45:11.629767 progress 80 % (8 MB)
112 08:45:11.710721 progress 85 % (9 MB)
113 08:45:11.794332 progress 90 % (10 MB)
114 08:45:11.868569 progress 95 % (10 MB)
115 08:45:11.946008 progress 100 % (11 MB)
116 08:45:11.958075 11 MB downloaded in 1.66 s (6.66 MB/s)
117 08:45:11.958711 end: 1.4.1 http-download (duration 00:00:02) [common]
119 08:45:11.959535 end: 1.4 download-retry (duration 00:00:02) [common]
120 08:45:11.959806 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 08:45:11.960246 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 08:45:11.960751 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 08:45:11.961266 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 08:45:11.962240 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd
125 08:45:11.963066 makedir: /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin
126 08:45:11.963695 makedir: /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/tests
127 08:45:11.964347 makedir: /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/results
128 08:45:11.964956 Creating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin/lava-add-keys
129 08:45:11.965904 Creating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin/lava-add-sources
130 08:45:11.966815 Creating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin/lava-background-process-start
131 08:45:11.967750 Creating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin/lava-background-process-stop
132 08:45:11.968764 Creating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin/lava-common-functions
133 08:45:11.969671 Creating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin/lava-echo-ipv4
134 08:45:11.970552 Creating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin/lava-install-packages
135 08:45:11.971408 Creating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin/lava-installed-packages
136 08:45:11.972304 Creating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin/lava-os-build
137 08:45:11.973181 Creating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin/lava-probe-channel
138 08:45:11.974049 Creating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin/lava-probe-ip
139 08:45:11.975324 Creating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin/lava-target-ip
140 08:45:11.976297 Creating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin/lava-target-mac
141 08:45:11.977184 Creating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin/lava-target-storage
142 08:45:11.978075 Creating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin/lava-test-case
143 08:45:11.978957 Creating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin/lava-test-event
144 08:45:11.979835 Creating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin/lava-test-feedback
145 08:45:11.980761 Creating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin/lava-test-raise
146 08:45:11.981641 Creating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin/lava-test-reference
147 08:45:11.982511 Creating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin/lava-test-runner
148 08:45:11.983381 Creating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin/lava-test-set
149 08:45:11.984284 Creating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin/lava-test-shell
150 08:45:11.985204 Updating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin/lava-install-packages (oe)
151 08:45:11.986151 Updating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/bin/lava-installed-packages (oe)
152 08:45:11.986963 Creating /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/environment
153 08:45:11.987686 LAVA metadata
154 08:45:11.988203 - LAVA_JOB_ID=933552
155 08:45:11.988631 - LAVA_DISPATCHER_IP=192.168.6.2
156 08:45:11.989303 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 08:45:11.991092 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 08:45:11.991680 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 08:45:11.992158 skipped lava-vland-overlay
160 08:45:11.992661 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 08:45:11.993168 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 08:45:11.993594 skipped lava-multinode-overlay
163 08:45:11.994076 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 08:45:11.994576 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 08:45:11.995051 Loading test definitions
166 08:45:11.995593 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 08:45:11.996079 Using /lava-933552 at stage 0
168 08:45:11.997312 uuid=933552_1.5.2.4.1 testdef=None
169 08:45:11.997668 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 08:45:11.997986 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 08:45:11.999754 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 08:45:12.000593 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 08:45:12.002786 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 08:45:12.003646 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 08:45:12.005786 runner path: /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/0/tests/0_igt-gpu-panfrost test_uuid 933552_1.5.2.4.1
178 08:45:12.006355 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 08:45:12.007164 Creating lava-test-runner.conf files
181 08:45:12.007370 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/933552/lava-overlay-y34_inyd/lava-933552/0 for stage 0
182 08:45:12.007713 - 0_igt-gpu-panfrost
183 08:45:12.008086 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 08:45:12.008376 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 08:45:12.031779 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 08:45:12.032253 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 08:45:12.032521 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 08:45:12.032790 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 08:45:12.033055 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 08:45:18.856558 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 08:45:18.857023 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 08:45:18.857268 extracting modules file /var/lib/lava/dispatcher/tmp/933552/tftp-deploy-8rcog5y3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/933552/extract-overlay-ramdisk-2iy8hizd/ramdisk
193 08:45:20.261689 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 08:45:20.262165 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 08:45:20.262443 [common] Applying overlay /var/lib/lava/dispatcher/tmp/933552/compress-overlay-z2m08wwh/overlay-1.5.2.5.tar.gz to ramdisk
196 08:45:20.262660 [common] Applying overlay /var/lib/lava/dispatcher/tmp/933552/compress-overlay-z2m08wwh/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/933552/extract-overlay-ramdisk-2iy8hizd/ramdisk
197 08:45:20.292549 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 08:45:20.292963 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 08:45:20.293235 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 08:45:20.293463 Converting downloaded kernel to a uImage
201 08:45:20.293779 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/933552/tftp-deploy-8rcog5y3/kernel/Image /var/lib/lava/dispatcher/tmp/933552/tftp-deploy-8rcog5y3/kernel/uImage
202 08:45:20.740337 output: Image Name:
203 08:45:20.740753 output: Created: Mon Nov 4 08:45:20 2024
204 08:45:20.740960 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 08:45:20.741164 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 08:45:20.741365 output: Load Address: 01080000
207 08:45:20.741565 output: Entry Point: 01080000
208 08:45:20.741764 output:
209 08:45:20.742091 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 08:45:20.742356 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 08:45:20.742622 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 08:45:20.742872 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 08:45:20.743129 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 08:45:20.743389 Building ramdisk /var/lib/lava/dispatcher/tmp/933552/extract-overlay-ramdisk-2iy8hizd/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/933552/extract-overlay-ramdisk-2iy8hizd/ramdisk
215 08:45:27.320093 >> 502411 blocks
216 08:45:48.139115 Adding RAMdisk u-boot header.
217 08:45:48.139562 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/933552/extract-overlay-ramdisk-2iy8hizd/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/933552/extract-overlay-ramdisk-2iy8hizd/ramdisk.cpio.gz.uboot
218 08:45:48.812851 output: Image Name:
219 08:45:48.813501 output: Created: Mon Nov 4 08:45:48 2024
220 08:45:48.813951 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 08:45:48.814384 output: Data Size: 65714377 Bytes = 64174.20 KiB = 62.67 MiB
222 08:45:48.814818 output: Load Address: 00000000
223 08:45:48.815241 output: Entry Point: 00000000
224 08:45:48.815651 output:
225 08:45:48.816685 rename /var/lib/lava/dispatcher/tmp/933552/extract-overlay-ramdisk-2iy8hizd/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/933552/tftp-deploy-8rcog5y3/ramdisk/ramdisk.cpio.gz.uboot
226 08:45:48.817415 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 08:45:48.817988 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 08:45:48.818547 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 08:45:48.819023 No LXC device requested
230 08:45:48.819547 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 08:45:48.820114 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 08:45:48.820646 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 08:45:48.821079 Checking files for TFTP limit of 4294967296 bytes.
234 08:45:48.823841 end: 1 tftp-deploy (duration 00:00:40) [common]
235 08:45:48.824529 start: 2 uboot-action (timeout 00:05:00) [common]
236 08:45:48.825102 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 08:45:48.825647 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 08:45:48.826188 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 08:45:48.826753 Using kernel file from prepare-kernel: 933552/tftp-deploy-8rcog5y3/kernel/uImage
240 08:45:48.827420 substitutions:
241 08:45:48.827863 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 08:45:48.828325 - {DTB_ADDR}: 0x01070000
243 08:45:48.828748 - {DTB}: 933552/tftp-deploy-8rcog5y3/dtb/meson-g12b-a311d-libretech-cc.dtb
244 08:45:48.829168 - {INITRD}: 933552/tftp-deploy-8rcog5y3/ramdisk/ramdisk.cpio.gz.uboot
245 08:45:48.829580 - {KERNEL_ADDR}: 0x01080000
246 08:45:48.829984 - {KERNEL}: 933552/tftp-deploy-8rcog5y3/kernel/uImage
247 08:45:48.830398 - {LAVA_MAC}: None
248 08:45:48.830851 - {PRESEED_CONFIG}: None
249 08:45:48.831270 - {PRESEED_LOCAL}: None
250 08:45:48.831676 - {RAMDISK_ADDR}: 0x08000000
251 08:45:48.832111 - {RAMDISK}: 933552/tftp-deploy-8rcog5y3/ramdisk/ramdisk.cpio.gz.uboot
252 08:45:48.832527 - {ROOT_PART}: None
253 08:45:48.832933 - {ROOT}: None
254 08:45:48.833346 - {SERVER_IP}: 192.168.6.2
255 08:45:48.833766 - {TEE_ADDR}: 0x83000000
256 08:45:48.834173 - {TEE}: None
257 08:45:48.834582 Parsed boot commands:
258 08:45:48.834978 - setenv autoload no
259 08:45:48.835388 - setenv initrd_high 0xffffffff
260 08:45:48.835797 - setenv fdt_high 0xffffffff
261 08:45:48.836240 - dhcp
262 08:45:48.836653 - setenv serverip 192.168.6.2
263 08:45:48.837062 - tftpboot 0x01080000 933552/tftp-deploy-8rcog5y3/kernel/uImage
264 08:45:48.837472 - tftpboot 0x08000000 933552/tftp-deploy-8rcog5y3/ramdisk/ramdisk.cpio.gz.uboot
265 08:45:48.837878 - tftpboot 0x01070000 933552/tftp-deploy-8rcog5y3/dtb/meson-g12b-a311d-libretech-cc.dtb
266 08:45:48.838287 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 08:45:48.838700 - bootm 0x01080000 0x08000000 0x01070000
268 08:45:48.839246 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 08:45:48.840991 start: 2.3 connect-device (timeout 00:05:00) [common]
271 08:45:48.841505 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 08:45:48.856564 Setting prompt string to ['lava-test: # ']
273 08:45:48.858117 end: 2.3 connect-device (duration 00:00:00) [common]
274 08:45:48.858786 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 08:45:48.859380 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 08:45:48.859952 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 08:45:48.861221 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 08:45:48.897718 >> OK - accepted request
279 08:45:48.899943 Returned 0 in 0 seconds
280 08:45:49.001186 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 08:45:49.002844 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 08:45:49.003423 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 08:45:49.003937 Setting prompt string to ['Hit any key to stop autoboot']
285 08:45:49.004449 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 08:45:49.006070 Trying 192.168.56.21...
287 08:45:49.006566 Connected to conserv1.
288 08:45:49.007019 Escape character is '^]'.
289 08:45:49.007467
290 08:45:49.007920 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 08:45:49.008400
292 08:45:59.643970 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 08:45:59.644678 bl2_stage_init 0x01
294 08:45:59.645166 bl2_stage_init 0x81
295 08:45:59.649540 hw id: 0x0000 - pwm id 0x01
296 08:45:59.650144 bl2_stage_init 0xc1
297 08:45:59.650598 bl2_stage_init 0x02
298 08:45:59.651075
299 08:45:59.654965 L0:00000000
300 08:45:59.655470 L1:20000703
301 08:45:59.655880 L2:00008067
302 08:45:59.656319 L3:14000000
303 08:45:59.660760 B2:00402000
304 08:45:59.661256 B1:e0f83180
305 08:45:59.661663
306 08:45:59.662060 TE: 58124
307 08:45:59.662445
308 08:45:59.666165 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 08:45:59.666640
310 08:45:59.667039 Board ID = 1
311 08:45:59.671762 Set A53 clk to 24M
312 08:45:59.672265 Set A73 clk to 24M
313 08:45:59.672669 Set clk81 to 24M
314 08:45:59.677345 A53 clk: 1200 MHz
315 08:45:59.677807 A73 clk: 1200 MHz
316 08:45:59.678199 CLK81: 166.6M
317 08:45:59.678582 smccc: 00012a92
318 08:45:59.682984 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 08:45:59.688757 board id: 1
320 08:45:59.694465 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 08:45:59.705080 fw parse done
322 08:45:59.711004 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 08:45:59.753705 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 08:45:59.764607 PIEI prepare done
325 08:45:59.765048 fastboot data load
326 08:45:59.765443 fastboot data verify
327 08:45:59.770066 verify result: 266
328 08:45:59.775659 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 08:45:59.776182 LPDDR4 probe
330 08:45:59.776581 ddr clk to 1584MHz
331 08:45:59.783706 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 08:45:59.820948
333 08:45:59.821516 dmc_version 0001
334 08:45:59.827694 Check phy result
335 08:45:59.833495 INFO : End of CA training
336 08:45:59.834015 INFO : End of initialization
337 08:45:59.839094 INFO : Training has run successfully!
338 08:45:59.839606 Check phy result
339 08:45:59.844759 INFO : End of initialization
340 08:45:59.845366 INFO : End of read enable training
341 08:45:59.850366 INFO : End of fine write leveling
342 08:45:59.855922 INFO : End of Write leveling coarse delay
343 08:45:59.856511 INFO : Training has run successfully!
344 08:45:59.856944 Check phy result
345 08:45:59.861508 INFO : End of initialization
346 08:45:59.862023 INFO : End of read dq deskew training
347 08:45:59.867101 INFO : End of MPR read delay center optimization
348 08:45:59.872678 INFO : End of write delay center optimization
349 08:45:59.878317 INFO : End of read delay center optimization
350 08:45:59.878858 INFO : End of max read latency training
351 08:45:59.883922 INFO : Training has run successfully!
352 08:45:59.884434 1D training succeed
353 08:45:59.893078 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 08:45:59.940845 Check phy result
355 08:45:59.941403 INFO : End of initialization
356 08:45:59.962535 INFO : End of 2D read delay Voltage center optimization
357 08:45:59.982705 INFO : End of 2D read delay Voltage center optimization
358 08:46:00.034893 INFO : End of 2D write delay Voltage center optimization
359 08:46:00.084144 INFO : End of 2D write delay Voltage center optimization
360 08:46:00.089780 INFO : Training has run successfully!
361 08:46:00.090301
362 08:46:00.090720 channel==0
363 08:46:00.095269 RxClkDly_Margin_A0==88 ps 9
364 08:46:00.095732 TxDqDly_Margin_A0==98 ps 10
365 08:46:00.100888 RxClkDly_Margin_A1==88 ps 9
366 08:46:00.101341 TxDqDly_Margin_A1==98 ps 10
367 08:46:00.101755 TrainedVREFDQ_A0==74
368 08:46:00.106527 TrainedVREFDQ_A1==74
369 08:46:00.107001 VrefDac_Margin_A0==25
370 08:46:00.107406 DeviceVref_Margin_A0==40
371 08:46:00.112034 VrefDac_Margin_A1==25
372 08:46:00.112557 DeviceVref_Margin_A1==40
373 08:46:00.112980
374 08:46:00.113385
375 08:46:00.117786 channel==1
376 08:46:00.118251 RxClkDly_Margin_A0==88 ps 9
377 08:46:00.118657 TxDqDly_Margin_A0==88 ps 9
378 08:46:00.123264 RxClkDly_Margin_A1==98 ps 10
379 08:46:00.123645 TxDqDly_Margin_A1==88 ps 9
380 08:46:00.128884 TrainedVREFDQ_A0==76
381 08:46:00.129508 TrainedVREFDQ_A1==77
382 08:46:00.129986 VrefDac_Margin_A0==22
383 08:46:00.134529 DeviceVref_Margin_A0==38
384 08:46:00.135061 VrefDac_Margin_A1==22
385 08:46:00.140010 DeviceVref_Margin_A1==37
386 08:46:00.140576
387 08:46:00.141066 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 08:46:00.141524
389 08:46:00.173857 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 08:46:00.174553 2D training succeed
391 08:46:00.179291 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 08:46:00.184737 auto size-- 65535DDR cs0 size: 2048MB
393 08:46:00.185218 DDR cs1 size: 2048MB
394 08:46:00.190476 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 08:46:00.191024 cs0 DataBus test pass
396 08:46:00.195931 cs1 DataBus test pass
397 08:46:00.196503 cs0 AddrBus test pass
398 08:46:00.196969 cs1 AddrBus test pass
399 08:46:00.197417
400 08:46:00.201677 100bdlr_step_size ps== 420
401 08:46:00.202214 result report
402 08:46:00.207125 boot times 0Enable ddr reg access
403 08:46:00.212448 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 08:46:00.225918 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 08:46:00.799664 0.0;M3 CHK:0;cm4_sp_mode 0
406 08:46:00.800373 MVN_1=0x00000000
407 08:46:00.805060 MVN_2=0x00000000
408 08:46:00.810793 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 08:46:00.811284 OPS=0x10
410 08:46:00.811738 ring efuse init
411 08:46:00.812225 chipver efuse init
412 08:46:00.819022 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 08:46:00.819523 [0.018961 Inits done]
414 08:46:00.826600 secure task start!
415 08:46:00.827127 high task start!
416 08:46:00.827577 low task start!
417 08:46:00.828048 run into bl31
418 08:46:00.833248 NOTICE: BL31: v1.3(release):4fc40b1
419 08:46:00.841039 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 08:46:00.841536 NOTICE: BL31: G12A normal boot!
421 08:46:00.866417 NOTICE: BL31: BL33 decompress pass
422 08:46:00.872092 ERROR: Error initializing runtime service opteed_fast
423 08:46:02.104932
424 08:46:02.105427
425 08:46:02.113291 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 08:46:02.113573
427 08:46:02.113795 Model: Libre Computer AML-A311D-CC Alta
428 08:46:02.321862 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 08:46:02.345149 DRAM: 2 GiB (effective 3.8 GiB)
430 08:46:02.488292 Core: 408 devices, 31 uclasses, devicetree: separate
431 08:46:02.493982 WDT: Not starting watchdog@f0d0
432 08:46:02.526277 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 08:46:02.538835 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 08:46:02.543719 ** Bad device specification mmc 0 **
435 08:46:02.554039 Card did not respond to voltage select! : -110
436 08:46:02.561681 ** Bad device specification mmc 0 **
437 08:46:02.562283 Couldn't find partition mmc 0
438 08:46:02.570102 Card did not respond to voltage select! : -110
439 08:46:02.575601 ** Bad device specification mmc 0 **
440 08:46:02.576128 Couldn't find partition mmc 0
441 08:46:02.580585 Error: could not access storage.
442 08:46:03.844121 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
443 08:46:03.844800 bl2_stage_init 0x81
444 08:46:03.849622 hw id: 0x0000 - pwm id 0x01
445 08:46:03.850132 bl2_stage_init 0xc1
446 08:46:03.850591 bl2_stage_init 0x02
447 08:46:03.851035
448 08:46:03.855201 L0:00000000
449 08:46:03.855684 L1:20000703
450 08:46:03.856162 L2:00008067
451 08:46:03.856606 L3:14000000
452 08:46:03.857042 B2:00402000
453 08:46:03.858031 B1:e0f83180
454 08:46:03.858492
455 08:46:03.858929 TE: 58150
456 08:46:03.859367
457 08:46:03.869184 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 08:46:03.869667
459 08:46:03.870117 Board ID = 1
460 08:46:03.870556 Set A53 clk to 24M
461 08:46:03.870989 Set A73 clk to 24M
462 08:46:03.874800 Set clk81 to 24M
463 08:46:03.875284 A53 clk: 1200 MHz
464 08:46:03.875729 A73 clk: 1200 MHz
465 08:46:03.880399 CLK81: 166.6M
466 08:46:03.880873 smccc: 00012aac
467 08:46:03.886029 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 08:46:03.886494 board id: 1
469 08:46:03.894607 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 08:46:03.905241 fw parse done
471 08:46:03.911217 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 08:46:03.953864 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 08:46:03.964803 PIEI prepare done
474 08:46:03.965297 fastboot data load
475 08:46:03.965754 fastboot data verify
476 08:46:03.970433 verify result: 266
477 08:46:03.976115 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 08:46:03.976593 LPDDR4 probe
479 08:46:03.977039 ddr clk to 1584MHz
480 08:46:03.984017 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 08:46:04.021303
482 08:46:04.021900 dmc_version 0001
483 08:46:04.027946 Check phy result
484 08:46:04.033781 INFO : End of CA training
485 08:46:04.034285 INFO : End of initialization
486 08:46:04.039386 INFO : Training has run successfully!
487 08:46:04.039862 Check phy result
488 08:46:04.045126 INFO : End of initialization
489 08:46:04.045619 INFO : End of read enable training
490 08:46:04.050598 INFO : End of fine write leveling
491 08:46:04.056208 INFO : End of Write leveling coarse delay
492 08:46:04.056687 INFO : Training has run successfully!
493 08:46:04.057135 Check phy result
494 08:46:04.061782 INFO : End of initialization
495 08:46:04.062260 INFO : End of read dq deskew training
496 08:46:04.067392 INFO : End of MPR read delay center optimization
497 08:46:04.073119 INFO : End of write delay center optimization
498 08:46:04.078570 INFO : End of read delay center optimization
499 08:46:04.079055 INFO : End of max read latency training
500 08:46:04.084215 INFO : Training has run successfully!
501 08:46:04.084690 1D training succeed
502 08:46:04.093375 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 08:46:04.140974 Check phy result
504 08:46:04.141485 INFO : End of initialization
505 08:46:04.162534 INFO : End of 2D read delay Voltage center optimization
506 08:46:04.182638 INFO : End of 2D read delay Voltage center optimization
507 08:46:04.234666 INFO : End of 2D write delay Voltage center optimization
508 08:46:04.283817 INFO : End of 2D write delay Voltage center optimization
509 08:46:04.289355 INFO : Training has run successfully!
510 08:46:04.289839
511 08:46:04.290292 channel==0
512 08:46:04.294956 RxClkDly_Margin_A0==88 ps 9
513 08:46:04.295445 TxDqDly_Margin_A0==98 ps 10
514 08:46:04.300561 RxClkDly_Margin_A1==88 ps 9
515 08:46:04.301032 TxDqDly_Margin_A1==88 ps 9
516 08:46:04.301481 TrainedVREFDQ_A0==74
517 08:46:04.306139 TrainedVREFDQ_A1==74
518 08:46:04.306623 VrefDac_Margin_A0==25
519 08:46:04.307066 DeviceVref_Margin_A0==40
520 08:46:04.311807 VrefDac_Margin_A1==25
521 08:46:04.312330 DeviceVref_Margin_A1==40
522 08:46:04.312789
523 08:46:04.313236
524 08:46:04.313676 channel==1
525 08:46:04.317381 RxClkDly_Margin_A0==98 ps 10
526 08:46:04.317854 TxDqDly_Margin_A0==88 ps 9
527 08:46:04.322967 RxClkDly_Margin_A1==98 ps 10
528 08:46:04.323439 TxDqDly_Margin_A1==88 ps 9
529 08:46:04.328557 TrainedVREFDQ_A0==76
530 08:46:04.329036 TrainedVREFDQ_A1==77
531 08:46:04.329484 VrefDac_Margin_A0==22
532 08:46:04.334166 DeviceVref_Margin_A0==38
533 08:46:04.334635 VrefDac_Margin_A1==22
534 08:46:04.339758 DeviceVref_Margin_A1==37
535 08:46:04.340248
536 08:46:04.340694 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 08:46:04.341133
538 08:46:04.373364 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 00000019 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
539 08:46:04.373938 2D training succeed
540 08:46:04.378928 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 08:46:04.384532 auto size-- 65535DDR cs0 size: 2048MB
542 08:46:04.385008 DDR cs1 size: 2048MB
543 08:46:04.390157 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 08:46:04.390635 cs0 DataBus test pass
545 08:46:04.395758 cs1 DataBus test pass
546 08:46:04.396275 cs0 AddrBus test pass
547 08:46:04.396723 cs1 AddrBus test pass
548 08:46:04.397158
549 08:46:04.401359 100bdlr_step_size ps== 420
550 08:46:04.401842 result report
551 08:46:04.406961 boot times 0Enable ddr reg access
552 08:46:04.412252 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 08:46:04.425681 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 08:46:04.997680 0.0;M3 CHK:0;cm4_sp_mode 0
555 08:46:04.998347 MVN_1=0x00000000
556 08:46:05.003205 MVN_2=0x00000000
557 08:46:05.008948 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 08:46:05.009462 OPS=0x10
559 08:46:05.009921 ring efuse init
560 08:46:05.010384 chipver efuse init
561 08:46:05.014544 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 08:46:05.020200 [0.018961 Inits done]
563 08:46:05.020670 secure task start!
564 08:46:05.021100 high task start!
565 08:46:05.024739 low task start!
566 08:46:05.025321 run into bl31
567 08:46:05.031409 NOTICE: BL31: v1.3(release):4fc40b1
568 08:46:05.039162 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 08:46:05.039674 NOTICE: BL31: G12A normal boot!
570 08:46:05.064567 NOTICE: BL31: BL33 decompress pass
571 08:46:05.070334 ERROR: Error initializing runtime service opteed_fast
572 08:46:06.303333
573 08:46:06.304036
574 08:46:06.311802 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 08:46:06.312434
576 08:46:06.312856 Model: Libre Computer AML-A311D-CC Alta
577 08:46:06.520275 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 08:46:06.543669 DRAM: 2 GiB (effective 3.8 GiB)
579 08:46:06.687397 Core: 408 devices, 31 uclasses, devicetree: separate
580 08:46:06.693303 WDT: Not starting watchdog@f0d0
581 08:46:06.724834 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 08:46:06.737127 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 08:46:06.742207 ** Bad device specification mmc 0 **
584 08:46:06.752640 Card did not respond to voltage select! : -110
585 08:46:06.760149 ** Bad device specification mmc 0 **
586 08:46:06.760547 Couldn't find partition mmc 0
587 08:46:06.768558 Card did not respond to voltage select! : -110
588 08:46:06.773862 ** Bad device specification mmc 0 **
589 08:46:06.774430 Couldn't find partition mmc 0
590 08:46:06.778936 Error: could not access storage.
591 08:46:07.121623 Net: eth0: ethernet@ff3f0000
592 08:46:07.122294 starting USB...
593 08:46:07.373300 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 08:46:07.373732 Starting the controller
595 08:46:07.380206 USB XHCI 1.10
596 08:46:09.094357 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
597 08:46:09.094783 bl2_stage_init 0x81
598 08:46:09.099904 hw id: 0x0000 - pwm id 0x01
599 08:46:09.100291 bl2_stage_init 0xc1
600 08:46:09.100593 bl2_stage_init 0x02
601 08:46:09.100885
602 08:46:09.105461 L0:00000000
603 08:46:09.105712 L1:20000703
604 08:46:09.105922 L2:00008067
605 08:46:09.106121 L3:14000000
606 08:46:09.106316 B2:00402000
607 08:46:09.108322 B1:e0f83180
608 08:46:09.108657
609 08:46:09.108958 TE: 58150
610 08:46:09.109274
611 08:46:09.119494 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
612 08:46:09.119863
613 08:46:09.120210 Board ID = 1
614 08:46:09.120513 Set A53 clk to 24M
615 08:46:09.120810 Set A73 clk to 24M
616 08:46:09.125028 Set clk81 to 24M
617 08:46:09.125400 A53 clk: 1200 MHz
618 08:46:09.125649 A73 clk: 1200 MHz
619 08:46:09.130641 CLK81: 166.6M
620 08:46:09.130914 smccc: 00012aab
621 08:46:09.136146 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
622 08:46:09.136442 board id: 1
623 08:46:09.144953 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
624 08:46:09.155453 fw parse done
625 08:46:09.161447 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
626 08:46:09.204100 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
627 08:46:09.214989 PIEI prepare done
628 08:46:09.215259 fastboot data load
629 08:46:09.215471 fastboot data verify
630 08:46:09.220600 verify result: 266
631 08:46:09.226117 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
632 08:46:09.226480 LPDDR4 probe
633 08:46:09.226797 ddr clk to 1584MHz
634 08:46:09.234121 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
635 08:46:09.271372
636 08:46:09.271674 dmc_version 0001
637 08:46:09.278194 Check phy result
638 08:46:09.284180 INFO : End of CA training
639 08:46:09.284794 INFO : End of initialization
640 08:46:09.289712 INFO : Training has run successfully!
641 08:46:09.290295 Check phy result
642 08:46:09.295265 INFO : End of initialization
643 08:46:09.295827 INFO : End of read enable training
644 08:46:09.298548 INFO : End of fine write leveling
645 08:46:09.304066 INFO : End of Write leveling coarse delay
646 08:46:09.309743 INFO : Training has run successfully!
647 08:46:09.310293 Check phy result
648 08:46:09.310752 INFO : End of initialization
649 08:46:09.315271 INFO : End of read dq deskew training
650 08:46:09.321083 INFO : End of MPR read delay center optimization
651 08:46:09.321675 INFO : End of write delay center optimization
652 08:46:09.326452 INFO : End of read delay center optimization
653 08:46:09.332103 INFO : End of max read latency training
654 08:46:09.332660 INFO : Training has run successfully!
655 08:46:09.337703 1D training succeed
656 08:46:09.343649 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
657 08:46:09.391246 Check phy result
658 08:46:09.391810 INFO : End of initialization
659 08:46:09.413017 INFO : End of 2D read delay Voltage center optimization
660 08:46:09.433359 INFO : End of 2D read delay Voltage center optimization
661 08:46:09.485219 INFO : End of 2D write delay Voltage center optimization
662 08:46:09.534525 INFO : End of 2D write delay Voltage center optimization
663 08:46:09.540208 INFO : Training has run successfully!
664 08:46:09.540567
665 08:46:09.540835 channel==0
666 08:46:09.545734 RxClkDly_Margin_A0==88 ps 9
667 08:46:09.546221 TxDqDly_Margin_A0==98 ps 10
668 08:46:09.549040 RxClkDly_Margin_A1==88 ps 9
669 08:46:09.549513 TxDqDly_Margin_A1==98 ps 10
670 08:46:09.554498 TrainedVREFDQ_A0==74
671 08:46:09.554989 TrainedVREFDQ_A1==74
672 08:46:09.560178 VrefDac_Margin_A0==25
673 08:46:09.560531 DeviceVref_Margin_A0==40
674 08:46:09.560798 VrefDac_Margin_A1==25
675 08:46:09.565769 DeviceVref_Margin_A1==40
676 08:46:09.566264
677 08:46:09.566698
678 08:46:09.567111 channel==1
679 08:46:09.567544 RxClkDly_Margin_A0==98 ps 10
680 08:46:09.571404 TxDqDly_Margin_A0==98 ps 10
681 08:46:09.571751 RxClkDly_Margin_A1==98 ps 10
682 08:46:09.576973 TxDqDly_Margin_A1==108 ps 11
683 08:46:09.577334 TrainedVREFDQ_A0==77
684 08:46:09.577596 TrainedVREFDQ_A1==78
685 08:46:09.582516 VrefDac_Margin_A0==22
686 08:46:09.582996 DeviceVref_Margin_A0==37
687 08:46:09.588208 VrefDac_Margin_A1==22
688 08:46:09.588704 DeviceVref_Margin_A1==36
689 08:46:09.589138
690 08:46:09.593771 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
691 08:46:09.594151
692 08:46:09.621757 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
693 08:46:09.627331 2D training succeed
694 08:46:09.632870 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
695 08:46:09.633219 auto size-- 65535DDR cs0 size: 2048MB
696 08:46:09.638447 DDR cs1 size: 2048MB
697 08:46:09.638938 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
698 08:46:09.644054 cs0 DataBus test pass
699 08:46:09.644401 cs1 DataBus test pass
700 08:46:09.644659 cs0 AddrBus test pass
701 08:46:09.649680 cs1 AddrBus test pass
702 08:46:09.650165
703 08:46:09.650593 100bdlr_step_size ps== 432
704 08:46:09.655231 result report
705 08:46:09.655718 boot times 0Enable ddr reg access
706 08:46:09.663372 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
707 08:46:09.676742 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
708 08:46:10.250455 0.0;M3 CHK:0;cm4_sp_mode 0
709 08:46:10.251151 MVN_1=0x00000000
710 08:46:10.256116 MVN_2=0x00000000
711 08:46:10.261840 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
712 08:46:10.262478 OPS=0x10
713 08:46:10.262936 ring efuse init
714 08:46:10.263369 chipver efuse init
715 08:46:10.267249 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
716 08:46:10.272794 [0.018961 Inits done]
717 08:46:10.273342 secure task start!
718 08:46:10.273778 high task start!
719 08:46:10.277358 low task start!
720 08:46:10.277891 run into bl31
721 08:46:10.284012 NOTICE: BL31: v1.3(release):4fc40b1
722 08:46:10.291816 NOTICE: BL31: Built : 15:58:17, May 22 2019
723 08:46:10.292393 NOTICE: BL31: G12A normal boot!
724 08:46:10.317153 NOTICE: BL31: BL33 decompress pass
725 08:46:10.322812 ERROR: Error initializing runtime service opteed_fast
726 08:46:11.555759
727 08:46:11.556441
728 08:46:11.564203 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
729 08:46:11.564720
730 08:46:11.565158 Model: Libre Computer AML-A311D-CC Alta
731 08:46:11.772569 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
732 08:46:11.795977 DRAM: 2 GiB (effective 3.8 GiB)
733 08:46:11.938958 Core: 408 devices, 31 uclasses, devicetree: separate
734 08:46:11.944773 WDT: Not starting watchdog@f0d0
735 08:46:11.977024 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
736 08:46:11.989479 Loading Environment from FAT... Card did not respond to voltage select! : -110
737 08:46:11.994491 ** Bad device specification mmc 0 **
738 08:46:12.004806 Card did not respond to voltage select! : -110
739 08:46:12.012444 ** Bad device specification mmc 0 **
740 08:46:12.012946 Couldn't find partition mmc 0
741 08:46:12.020792 Card did not respond to voltage select! : -110
742 08:46:12.026311 ** Bad device specification mmc 0 **
743 08:46:12.026826 Couldn't find partition mmc 0
744 08:46:12.031367 Error: could not access storage.
745 08:46:12.373860 Net: eth0: ethernet@ff3f0000
746 08:46:12.374469 starting USB...
747 08:46:12.625684 Bus usb@ff500000: Register 3000140 NbrPorts 3
748 08:46:12.626263 Starting the controller
749 08:46:12.632616 USB XHCI 1.10
750 08:46:14.794286 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
751 08:46:14.794970 bl2_stage_init 0x01
752 08:46:14.795448 bl2_stage_init 0x81
753 08:46:14.800018 hw id: 0x0000 - pwm id 0x01
754 08:46:14.800558 bl2_stage_init 0xc1
755 08:46:14.801018 bl2_stage_init 0x02
756 08:46:14.801468
757 08:46:14.805534 L0:00000000
758 08:46:14.806045 L1:20000703
759 08:46:14.806502 L2:00008067
760 08:46:14.806948 L3:14000000
761 08:46:14.811081 B2:00402000
762 08:46:14.811606 B1:e0f83180
763 08:46:14.812101
764 08:46:14.812563 TE: 58167
765 08:46:14.813009
766 08:46:14.816763 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
767 08:46:14.817293
768 08:46:14.817748 Board ID = 1
769 08:46:14.822364 Set A53 clk to 24M
770 08:46:14.822879 Set A73 clk to 24M
771 08:46:14.823333 Set clk81 to 24M
772 08:46:14.827948 A53 clk: 1200 MHz
773 08:46:14.828490 A73 clk: 1200 MHz
774 08:46:14.828942 CLK81: 166.6M
775 08:46:14.829382 smccc: 00012abe
776 08:46:14.833454 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
777 08:46:14.839031 board id: 1
778 08:46:14.845075 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
779 08:46:14.855589 fw parse done
780 08:46:14.861521 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
781 08:46:14.904151 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
782 08:46:14.915009 PIEI prepare done
783 08:46:14.915536 fastboot data load
784 08:46:14.916040 fastboot data verify
785 08:46:14.920804 verify result: 266
786 08:46:14.926330 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
787 08:46:14.926851 LPDDR4 probe
788 08:46:14.927305 ddr clk to 1584MHz
789 08:46:14.934240 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
790 08:46:14.971571
791 08:46:14.972160 dmc_version 0001
792 08:46:14.978297 Check phy result
793 08:46:14.984156 INFO : End of CA training
794 08:46:14.984685 INFO : End of initialization
795 08:46:14.989743 INFO : Training has run successfully!
796 08:46:14.990242 Check phy result
797 08:46:14.995348 INFO : End of initialization
798 08:46:14.995850 INFO : End of read enable training
799 08:46:15.000982 INFO : End of fine write leveling
800 08:46:15.006475 INFO : End of Write leveling coarse delay
801 08:46:15.006975 INFO : Training has run successfully!
802 08:46:15.007424 Check phy result
803 08:46:15.012125 INFO : End of initialization
804 08:46:15.012619 INFO : End of read dq deskew training
805 08:46:15.017765 INFO : End of MPR read delay center optimization
806 08:46:15.023264 INFO : End of write delay center optimization
807 08:46:15.028883 INFO : End of read delay center optimization
808 08:46:15.029178 INFO : End of max read latency training
809 08:46:15.034461 INFO : Training has run successfully!
810 08:46:15.034850 1D training succeed
811 08:46:15.043774 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
812 08:46:15.091341 Check phy result
813 08:46:15.091740 INFO : End of initialization
814 08:46:15.112920 INFO : End of 2D read delay Voltage center optimization
815 08:46:15.133024 INFO : End of 2D read delay Voltage center optimization
816 08:46:15.184976 INFO : End of 2D write delay Voltage center optimization
817 08:46:15.234282 INFO : End of 2D write delay Voltage center optimization
818 08:46:15.239764 INFO : Training has run successfully!
819 08:46:15.240132
820 08:46:15.240357 channel==0
821 08:46:15.245339 RxClkDly_Margin_A0==88 ps 9
822 08:46:15.245753 TxDqDly_Margin_A0==98 ps 10
823 08:46:15.248776 RxClkDly_Margin_A1==88 ps 9
824 08:46:15.249163 TxDqDly_Margin_A1==88 ps 9
825 08:46:15.254345 TrainedVREFDQ_A0==74
826 08:46:15.256097 TrainedVREFDQ_A1==74
827 08:46:15.256777 VrefDac_Margin_A0==24
828 08:46:15.259967 DeviceVref_Margin_A0==40
829 08:46:15.260588 VrefDac_Margin_A1==25
830 08:46:15.265534 DeviceVref_Margin_A1==40
831 08:46:15.266120
832 08:46:15.266640
833 08:46:15.267147 channel==1
834 08:46:15.267645 RxClkDly_Margin_A0==98 ps 10
835 08:46:15.271189 TxDqDly_Margin_A0==88 ps 9
836 08:46:15.271768 RxClkDly_Margin_A1==88 ps 9
837 08:46:15.276831 TxDqDly_Margin_A1==98 ps 10
838 08:46:15.277500 TrainedVREFDQ_A0==77
839 08:46:15.278017 TrainedVREFDQ_A1==78
840 08:46:15.282365 VrefDac_Margin_A0==22
841 08:46:15.282996 DeviceVref_Margin_A0==37
842 08:46:15.287902 VrefDac_Margin_A1==24
843 08:46:15.288540 DeviceVref_Margin_A1==36
844 08:46:15.289061
845 08:46:15.293496 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
846 08:46:15.294082
847 08:46:15.321513 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
848 08:46:15.327085 2D training succeed
849 08:46:15.332729 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
850 08:46:15.333307 auto size-- 65535DDR cs0 size: 2048MB
851 08:46:15.338267 DDR cs1 size: 2048MB
852 08:46:15.338840 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
853 08:46:15.343868 cs0 DataBus test pass
854 08:46:15.344490 cs1 DataBus test pass
855 08:46:15.345000 cs0 AddrBus test pass
856 08:46:15.349493 cs1 AddrBus test pass
857 08:46:15.350069
858 08:46:15.350587 100bdlr_step_size ps== 432
859 08:46:15.351102 result report
860 08:46:15.355092 boot times 0Enable ddr reg access
861 08:46:15.362531 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
862 08:46:15.375957 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
863 08:46:15.948027 0.0;M3 CHK:0;cm4_sp_mode 0
864 08:46:15.948848 MVN_1=0x00000000
865 08:46:15.953375 MVN_2=0x00000000
866 08:46:15.959139 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
867 08:46:15.959768 OPS=0x10
868 08:46:15.960366 ring efuse init
869 08:46:15.960900 chipver efuse init
870 08:46:15.964901 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
871 08:46:15.970530 [0.018961 Inits done]
872 08:46:15.971138 secure task start!
873 08:46:15.971668 high task start!
874 08:46:15.975081 low task start!
875 08:46:15.975661 run into bl31
876 08:46:15.981764 NOTICE: BL31: v1.3(release):4fc40b1
877 08:46:15.989515 NOTICE: BL31: Built : 15:58:17, May 22 2019
878 08:46:15.990175 NOTICE: BL31: G12A normal boot!
879 08:46:16.014849 NOTICE: BL31: BL33 decompress pass
880 08:46:16.020581 ERROR: Error initializing runtime service opteed_fast
881 08:46:17.253583
882 08:46:17.254377
883 08:46:17.261894 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
884 08:46:17.262491
885 08:46:17.263042 Model: Libre Computer AML-A311D-CC Alta
886 08:46:17.470353 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
887 08:46:17.493690 DRAM: 2 GiB (effective 3.8 GiB)
888 08:46:17.636701 Core: 408 devices, 31 uclasses, devicetree: separate
889 08:46:17.642535 WDT: Not starting watchdog@f0d0
890 08:46:17.674796 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
891 08:46:17.687271 Loading Environment from FAT... Card did not respond to voltage select! : -110
892 08:46:17.692241 ** Bad device specification mmc 0 **
893 08:46:17.702566 Card did not respond to voltage select! : -110
894 08:46:17.710201 ** Bad device specification mmc 0 **
895 08:46:17.710809 Couldn't find partition mmc 0
896 08:46:17.718558 Card did not respond to voltage select! : -110
897 08:46:17.724096 ** Bad device specification mmc 0 **
898 08:46:17.724691 Couldn't find partition mmc 0
899 08:46:17.729113 Error: could not access storage.
900 08:46:18.071600 Net: eth0: ethernet@ff3f0000
901 08:46:18.072412 starting USB...
902 08:46:18.323519 Bus usb@ff500000: Register 3000140 NbrPorts 3
903 08:46:18.324372 Starting the controller
904 08:46:18.330463 USB XHCI 1.10
905 08:46:19.884688 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
906 08:46:19.892690 scanning usb for storage devices... 0 Storage Device(s) found
908 08:46:19.944596 Hit any key to stop autoboot: 1
909 08:46:19.945609 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
910 08:46:19.946374 start: 2.4.3 bootloader-commands (timeout 00:04:29) [common]
911 08:46:19.946992 Setting prompt string to ['=>']
912 08:46:19.947606 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:29)
913 08:46:19.960185 0
914 08:46:19.961252 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
915 08:46:19.961919 Sending with 10 millisecond of delay
917 08:46:21.097286 => setenv autoload no
918 08:46:21.108101 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:28)
919 08:46:21.113013 setenv autoload no
920 08:46:21.113727 Sending with 10 millisecond of delay
922 08:46:22.910910 => setenv initrd_high 0xffffffff
923 08:46:22.921886 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
924 08:46:22.922930 setenv initrd_high 0xffffffff
925 08:46:22.923796 Sending with 10 millisecond of delay
927 08:46:24.540561 => setenv fdt_high 0xffffffff
928 08:46:24.551530 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
929 08:46:24.552560 setenv fdt_high 0xffffffff
930 08:46:24.553420 Sending with 10 millisecond of delay
932 08:46:24.845628 => dhcp
933 08:46:24.856596 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
934 08:46:24.857611 dhcp
935 08:46:24.858171 Speed: 1000, full duplex
936 08:46:24.858705 BOOTP broadcast 1
937 08:46:24.865064 DHCP client bound to address 192.168.6.27 (8 ms)
938 08:46:24.865906 Sending with 10 millisecond of delay
940 08:46:26.542566 => setenv serverip 192.168.6.2
941 08:46:26.553573 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
942 08:46:26.554697 setenv serverip 192.168.6.2
943 08:46:26.555529 Sending with 10 millisecond of delay
945 08:46:30.279097 => tftpboot 0x01080000 933552/tftp-deploy-8rcog5y3/kernel/uImage
946 08:46:30.289885 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
947 08:46:30.290719 tftpboot 0x01080000 933552/tftp-deploy-8rcog5y3/kernel/uImage
948 08:46:30.291163 Speed: 1000, full duplex
949 08:46:30.291573 Using ethernet@ff3f0000 device
950 08:46:30.292613 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
951 08:46:30.298198 Filename '933552/tftp-deploy-8rcog5y3/kernel/uImage'.
952 08:46:30.302031 Load address: 0x1080000
953 08:46:31.426204 Loading: *#################### UDP wrong checksum 000000ff 0000be77
954 08:46:31.495789 # UDP wrong checksum 000000ff 0000436a
955 08:46:31.597306 ## UDP wrong checksum 000000ff 0000fc5a
956 08:46:31.641787 # UDP wrong checksum 000000ff 0000964d
957 08:46:33.082195 ########################## 43.6 MiB
958 08:46:33.082800 15.7 MiB/s
959 08:46:33.083219 done
960 08:46:33.086561 Bytes transferred = 45713984 (2b98a40 hex)
961 08:46:33.087281 Sending with 10 millisecond of delay
963 08:46:37.773307 => tftpboot 0x08000000 933552/tftp-deploy-8rcog5y3/ramdisk/ramdisk.cpio.gz.uboot
964 08:46:37.784068 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
965 08:46:37.784894 tftpboot 0x08000000 933552/tftp-deploy-8rcog5y3/ramdisk/ramdisk.cpio.gz.uboot
966 08:46:37.785316 Speed: 1000, full duplex
967 08:46:37.785713 Using ethernet@ff3f0000 device
968 08:46:37.786517 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
969 08:46:37.798126 Filename '933552/tftp-deploy-8rcog5y3/ramdisk/ramdisk.cpio.gz.uboot'.
970 08:46:37.798603 Load address: 0x8000000
971 08:46:46.807447 Loading: *########T ######################################### UDP wrong checksum 0000000f 0000c5a0
972 08:46:51.807608 T UDP wrong checksum 0000000f 0000c5a0
973 08:47:01.808521 T T UDP wrong checksum 0000000f 0000c5a0
974 08:47:21.813447 T T T T UDP wrong checksum 0000000f 0000c5a0
975 08:47:25.295320 UDP wrong checksum 000000ff 0000d667
976 08:47:25.300600 UDP wrong checksum 000000ff 0000645a
977 08:47:32.449345 T T UDP wrong checksum 000000ff 00009487
978 08:47:32.466621 UDP wrong checksum 000000ff 00001d7a
979 08:47:36.816792
980 08:47:36.817664 Retry count exceeded; starting again
982 08:47:36.819771 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
985 08:47:36.822775 end: 2.4 uboot-commands (duration 00:01:48) [common]
987 08:47:36.824736 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
989 08:47:36.827143 end: 2 uboot-action (duration 00:01:48) [common]
991 08:47:36.829337 Cleaning after the job
992 08:47:36.830110 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933552/tftp-deploy-8rcog5y3/ramdisk
993 08:47:36.832116 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933552/tftp-deploy-8rcog5y3/kernel
994 08:47:36.882125 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933552/tftp-deploy-8rcog5y3/dtb
995 08:47:36.883199 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933552/tftp-deploy-8rcog5y3/modules
996 08:47:36.911208 start: 4.1 power-off (timeout 00:00:30) [common]
997 08:47:36.912047 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
998 08:47:36.950935 >> OK - accepted request
999 08:47:36.953169 Returned 0 in 0 seconds
1000 08:47:37.054495 end: 4.1 power-off (duration 00:00:00) [common]
1002 08:47:37.055779 start: 4.2 read-feedback (timeout 00:10:00) [common]
1003 08:47:37.056672 Listened to connection for namespace 'common' for up to 1s
1004 08:47:38.057009 Finalising connection for namespace 'common'
1005 08:47:38.057940 Disconnecting from shell: Finalise
1006 08:47:38.059665 =>
1007 08:47:38.161053 end: 4.2 read-feedback (duration 00:00:01) [common]
1008 08:47:38.162049 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/933552
1009 08:47:38.861231 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/933552
1010 08:47:38.861926 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.