Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 1
- Kernel Warnings: 8
- Errors: 0
- Boot result: PASS
- Kernel Errors: 6
1 08:31:08.761050 lava-dispatcher, installed at version: 2024.01
2 08:31:08.761838 start: 0 validate
3 08:31:08.762271 Start time: 2024-11-04 08:31:08.762243+00:00 (UTC)
4 08:31:08.762760 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 08:31:08.763258 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 08:31:08.799967 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 08:31:08.800555 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-328-gf46306bca74bb%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 08:31:08.829068 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 08:31:08.829675 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-328-gf46306bca74bb%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 08:31:17.911940 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 08:31:17.912485 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 08:31:17.943255 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 08:31:17.943742 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-328-gf46306bca74bb%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 08:31:19.996297 validate duration: 11.23
16 08:31:19.997139 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 08:31:19.997482 start: 1.1 download-retry (timeout 00:10:00) [common]
18 08:31:19.997811 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 08:31:19.998400 Not decompressing ramdisk as can be used compressed.
20 08:31:19.998862 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 08:31:19.999185 saving as /var/lib/lava/dispatcher/tmp/933468/tftp-deploy-8t0m58g2/ramdisk/initrd.cpio.gz
22 08:31:19.999620 total size: 5628169 (5 MB)
23 08:31:20.051334 progress 0 % (0 MB)
24 08:31:20.059147 progress 5 % (0 MB)
25 08:31:20.067416 progress 10 % (0 MB)
26 08:31:20.072437 progress 15 % (0 MB)
27 08:31:20.080742 progress 20 % (1 MB)
28 08:31:20.086128 progress 25 % (1 MB)
29 08:31:20.090248 progress 30 % (1 MB)
30 08:31:20.094320 progress 35 % (1 MB)
31 08:31:20.098027 progress 40 % (2 MB)
32 08:31:20.102205 progress 45 % (2 MB)
33 08:31:20.106396 progress 50 % (2 MB)
34 08:31:20.110966 progress 55 % (2 MB)
35 08:31:20.115370 progress 60 % (3 MB)
36 08:31:20.118995 progress 65 % (3 MB)
37 08:31:20.123058 progress 70 % (3 MB)
38 08:31:20.126816 progress 75 % (4 MB)
39 08:31:20.130866 progress 80 % (4 MB)
40 08:31:20.134519 progress 85 % (4 MB)
41 08:31:20.138555 progress 90 % (4 MB)
42 08:31:20.142513 progress 95 % (5 MB)
43 08:31:20.145841 progress 100 % (5 MB)
44 08:31:20.146537 5 MB downloaded in 0.15 s (36.54 MB/s)
45 08:31:20.147087 end: 1.1.1 http-download (duration 00:00:00) [common]
47 08:31:20.148005 end: 1.1 download-retry (duration 00:00:00) [common]
48 08:31:20.148318 start: 1.2 download-retry (timeout 00:10:00) [common]
49 08:31:20.148596 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 08:31:20.149109 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-328-gf46306bca74bb/arm64/defconfig/gcc-12/kernel/Image
51 08:31:20.149426 saving as /var/lib/lava/dispatcher/tmp/933468/tftp-deploy-8t0m58g2/kernel/Image
52 08:31:20.149638 total size: 45713920 (43 MB)
53 08:31:20.149855 No compression specified
54 08:31:20.193321 progress 0 % (0 MB)
55 08:31:20.221491 progress 5 % (2 MB)
56 08:31:20.250758 progress 10 % (4 MB)
57 08:31:20.279168 progress 15 % (6 MB)
58 08:31:20.306757 progress 20 % (8 MB)
59 08:31:20.334010 progress 25 % (10 MB)
60 08:31:20.361593 progress 30 % (13 MB)
61 08:31:20.391305 progress 35 % (15 MB)
62 08:31:20.420765 progress 40 % (17 MB)
63 08:31:20.447964 progress 45 % (19 MB)
64 08:31:20.475625 progress 50 % (21 MB)
65 08:31:20.503397 progress 55 % (24 MB)
66 08:31:20.534194 progress 60 % (26 MB)
67 08:31:20.564322 progress 65 % (28 MB)
68 08:31:20.593400 progress 70 % (30 MB)
69 08:31:20.622533 progress 75 % (32 MB)
70 08:31:20.651565 progress 80 % (34 MB)
71 08:31:20.681856 progress 85 % (37 MB)
72 08:31:20.710624 progress 90 % (39 MB)
73 08:31:20.740980 progress 95 % (41 MB)
74 08:31:20.768248 progress 100 % (43 MB)
75 08:31:20.768791 43 MB downloaded in 0.62 s (70.41 MB/s)
76 08:31:20.769263 end: 1.2.1 http-download (duration 00:00:01) [common]
78 08:31:20.770075 end: 1.2 download-retry (duration 00:00:01) [common]
79 08:31:20.770348 start: 1.3 download-retry (timeout 00:09:59) [common]
80 08:31:20.770610 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 08:31:20.771084 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-328-gf46306bca74bb/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 08:31:20.771355 saving as /var/lib/lava/dispatcher/tmp/933468/tftp-deploy-8t0m58g2/dtb/meson-g12b-a311d-libretech-cc.dtb
83 08:31:20.771563 total size: 54703 (0 MB)
84 08:31:20.771771 No compression specified
85 08:31:20.805370 progress 59 % (0 MB)
86 08:31:20.806206 progress 100 % (0 MB)
87 08:31:20.806763 0 MB downloaded in 0.04 s (1.48 MB/s)
88 08:31:20.807235 end: 1.3.1 http-download (duration 00:00:00) [common]
90 08:31:20.808135 end: 1.3 download-retry (duration 00:00:00) [common]
91 08:31:20.808417 start: 1.4 download-retry (timeout 00:09:59) [common]
92 08:31:20.808684 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 08:31:20.809158 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 08:31:20.809401 saving as /var/lib/lava/dispatcher/tmp/933468/tftp-deploy-8t0m58g2/nfsrootfs/full.rootfs.tar
95 08:31:20.809601 total size: 120894716 (115 MB)
96 08:31:20.809813 Using unxz to decompress xz
97 08:31:20.843053 progress 0 % (0 MB)
98 08:31:21.643565 progress 5 % (5 MB)
99 08:31:22.493335 progress 10 % (11 MB)
100 08:31:23.300834 progress 15 % (17 MB)
101 08:31:24.040908 progress 20 % (23 MB)
102 08:31:24.633055 progress 25 % (28 MB)
103 08:31:25.464417 progress 30 % (34 MB)
104 08:31:26.268010 progress 35 % (40 MB)
105 08:31:26.663511 progress 40 % (46 MB)
106 08:31:27.093818 progress 45 % (51 MB)
107 08:31:27.864565 progress 50 % (57 MB)
108 08:31:28.758527 progress 55 % (63 MB)
109 08:31:29.550040 progress 60 % (69 MB)
110 08:31:30.312916 progress 65 % (74 MB)
111 08:31:31.103070 progress 70 % (80 MB)
112 08:31:32.088504 progress 75 % (86 MB)
113 08:31:33.021731 progress 80 % (92 MB)
114 08:31:33.896446 progress 85 % (98 MB)
115 08:31:34.790085 progress 90 % (103 MB)
116 08:31:35.588841 progress 95 % (109 MB)
117 08:31:36.430864 progress 100 % (115 MB)
118 08:31:36.443552 115 MB downloaded in 15.63 s (7.37 MB/s)
119 08:31:36.444198 end: 1.4.1 http-download (duration 00:00:16) [common]
121 08:31:36.445087 end: 1.4 download-retry (duration 00:00:16) [common]
122 08:31:36.445370 start: 1.5 download-retry (timeout 00:09:44) [common]
123 08:31:36.445640 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 08:31:36.446116 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-328-gf46306bca74bb/arm64/defconfig/gcc-12/modules.tar.xz
125 08:31:36.446370 saving as /var/lib/lava/dispatcher/tmp/933468/tftp-deploy-8t0m58g2/modules/modules.tar
126 08:31:36.446578 total size: 11614628 (11 MB)
127 08:31:36.446793 Using unxz to decompress xz
128 08:31:36.484807 progress 0 % (0 MB)
129 08:31:36.552572 progress 5 % (0 MB)
130 08:31:36.627303 progress 10 % (1 MB)
131 08:31:36.724241 progress 15 % (1 MB)
132 08:31:36.816919 progress 20 % (2 MB)
133 08:31:36.896620 progress 25 % (2 MB)
134 08:31:36.972485 progress 30 % (3 MB)
135 08:31:37.051551 progress 35 % (3 MB)
136 08:31:37.124395 progress 40 % (4 MB)
137 08:31:37.201295 progress 45 % (5 MB)
138 08:31:37.287146 progress 50 % (5 MB)
139 08:31:37.364603 progress 55 % (6 MB)
140 08:31:37.449976 progress 60 % (6 MB)
141 08:31:37.530558 progress 65 % (7 MB)
142 08:31:37.611209 progress 70 % (7 MB)
143 08:31:37.689798 progress 75 % (8 MB)
144 08:31:37.774695 progress 80 % (8 MB)
145 08:31:37.854721 progress 85 % (9 MB)
146 08:31:37.937713 progress 90 % (10 MB)
147 08:31:38.011523 progress 95 % (10 MB)
148 08:31:38.088694 progress 100 % (11 MB)
149 08:31:38.100635 11 MB downloaded in 1.65 s (6.70 MB/s)
150 08:31:38.101233 end: 1.5.1 http-download (duration 00:00:02) [common]
152 08:31:38.102056 end: 1.5 download-retry (duration 00:00:02) [common]
153 08:31:38.102324 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 08:31:38.102590 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 08:31:55.872530 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/933468/extract-nfsrootfs-ycl9qdu0
156 08:31:55.873137 end: 1.6.1 extract-nfsrootfs (duration 00:00:18) [common]
157 08:31:55.873423 start: 1.6.2 lava-overlay (timeout 00:09:24) [common]
158 08:31:55.874039 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281
159 08:31:55.874458 makedir: /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin
160 08:31:55.874780 makedir: /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/tests
161 08:31:55.875087 makedir: /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/results
162 08:31:55.875416 Creating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-add-keys
163 08:31:55.875949 Creating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-add-sources
164 08:31:55.876487 Creating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-background-process-start
165 08:31:55.877035 Creating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-background-process-stop
166 08:31:55.877631 Creating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-common-functions
167 08:31:55.878132 Creating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-echo-ipv4
168 08:31:55.878613 Creating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-install-packages
169 08:31:55.879082 Creating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-installed-packages
170 08:31:55.879568 Creating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-os-build
171 08:31:55.880061 Creating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-probe-channel
172 08:31:55.880547 Creating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-probe-ip
173 08:31:55.881015 Creating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-target-ip
174 08:31:55.881477 Creating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-target-mac
175 08:31:55.881949 Creating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-target-storage
176 08:31:55.882427 Creating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-test-case
177 08:31:55.882889 Creating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-test-event
178 08:31:55.883345 Creating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-test-feedback
179 08:31:55.883804 Creating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-test-raise
180 08:31:55.884305 Creating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-test-reference
181 08:31:55.884802 Creating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-test-runner
182 08:31:55.885318 Creating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-test-set
183 08:31:55.885792 Creating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-test-shell
184 08:31:55.886265 Updating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-add-keys (debian)
185 08:31:55.886784 Updating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-add-sources (debian)
186 08:31:55.887275 Updating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-install-packages (debian)
187 08:31:55.887757 Updating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-installed-packages (debian)
188 08:31:55.888275 Updating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/bin/lava-os-build (debian)
189 08:31:55.888704 Creating /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/environment
190 08:31:55.889062 LAVA metadata
191 08:31:55.889317 - LAVA_JOB_ID=933468
192 08:31:55.889530 - LAVA_DISPATCHER_IP=192.168.6.2
193 08:31:55.889882 start: 1.6.2.1 ssh-authorize (timeout 00:09:24) [common]
194 08:31:55.890816 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 08:31:55.891120 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:24) [common]
196 08:31:55.891325 skipped lava-vland-overlay
197 08:31:55.891562 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 08:31:55.891812 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:24) [common]
199 08:31:55.892064 skipped lava-multinode-overlay
200 08:31:55.892317 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 08:31:55.892567 start: 1.6.2.4 test-definition (timeout 00:09:24) [common]
202 08:31:55.892812 Loading test definitions
203 08:31:55.893084 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:24) [common]
204 08:31:55.893299 Using /lava-933468 at stage 0
205 08:31:55.894415 uuid=933468_1.6.2.4.1 testdef=None
206 08:31:55.894715 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 08:31:55.894975 start: 1.6.2.4.2 test-overlay (timeout 00:09:24) [common]
208 08:31:55.896570 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 08:31:55.897348 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:24) [common]
211 08:31:55.899223 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 08:31:55.900101 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:24) [common]
214 08:31:55.901893 runner path: /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/0/tests/0_timesync-off test_uuid 933468_1.6.2.4.1
215 08:31:55.902418 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 08:31:55.903218 start: 1.6.2.4.5 git-repo-action (timeout 00:09:24) [common]
218 08:31:55.903438 Using /lava-933468 at stage 0
219 08:31:55.903778 Fetching tests from https://github.com/kernelci/test-definitions.git
220 08:31:55.904086 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/0/tests/1_kselftest-alsa'
221 08:31:59.346271 Running '/usr/bin/git checkout kernelci.org
222 08:31:59.660045 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 08:31:59.661446 uuid=933468_1.6.2.4.5 testdef=None
224 08:31:59.661783 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 08:31:59.662521 start: 1.6.2.4.6 test-overlay (timeout 00:09:20) [common]
227 08:31:59.665325 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 08:31:59.666131 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:20) [common]
230 08:31:59.669769 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 08:31:59.670619 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:20) [common]
233 08:31:59.674143 runner path: /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/0/tests/1_kselftest-alsa test_uuid 933468_1.6.2.4.5
234 08:31:59.674425 BOARD='meson-g12b-a311d-libretech-cc'
235 08:31:59.674629 BRANCH='tip'
236 08:31:59.674822 SKIPFILE='/dev/null'
237 08:31:59.675017 SKIP_INSTALL='True'
238 08:31:59.675211 TESTPROG_URL='http://storage.kernelci.org/tip/master/v6.12-rc6-328-gf46306bca74bb/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 08:31:59.675408 TST_CASENAME=''
240 08:31:59.675601 TST_CMDFILES='alsa'
241 08:31:59.676150 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 08:31:59.676937 Creating lava-test-runner.conf files
244 08:31:59.677140 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/933468/lava-overlay-14a9t281/lava-933468/0 for stage 0
245 08:31:59.677503 - 0_timesync-off
246 08:31:59.677743 - 1_kselftest-alsa
247 08:31:59.678069 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 08:31:59.678345 start: 1.6.2.5 compress-overlay (timeout 00:09:20) [common]
249 08:32:23.812197 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
250 08:32:23.812609 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:56) [common]
251 08:32:23.812871 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 08:32:23.813141 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
253 08:32:23.813406 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:56) [common]
254 08:32:24.434907 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 08:32:24.435417 start: 1.6.4 extract-modules (timeout 00:08:56) [common]
256 08:32:24.435669 extracting modules file /var/lib/lava/dispatcher/tmp/933468/tftp-deploy-8t0m58g2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/933468/extract-nfsrootfs-ycl9qdu0
257 08:32:25.793134 extracting modules file /var/lib/lava/dispatcher/tmp/933468/tftp-deploy-8t0m58g2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/933468/extract-overlay-ramdisk-5ua4eiai/ramdisk
258 08:32:27.190435 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 08:32:27.191056 start: 1.6.5 apply-overlay-tftp (timeout 00:08:53) [common]
260 08:32:27.191422 [common] Applying overlay to NFS
261 08:32:27.191706 [common] Applying overlay /var/lib/lava/dispatcher/tmp/933468/compress-overlay-04onu5x1/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/933468/extract-nfsrootfs-ycl9qdu0
262 08:32:30.242119 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 08:32:30.242571 start: 1.6.6 prepare-kernel (timeout 00:08:50) [common]
264 08:32:30.242844 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:50) [common]
265 08:32:30.243075 Converting downloaded kernel to a uImage
266 08:32:30.243383 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/933468/tftp-deploy-8t0m58g2/kernel/Image /var/lib/lava/dispatcher/tmp/933468/tftp-deploy-8t0m58g2/kernel/uImage
267 08:32:30.691868 output: Image Name:
268 08:32:30.692462 output: Created: Mon Nov 4 08:32:30 2024
269 08:32:30.692673 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 08:32:30.692875 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 08:32:30.693074 output: Load Address: 01080000
272 08:32:30.693272 output: Entry Point: 01080000
273 08:32:30.693469 output:
274 08:32:30.693798 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 08:32:30.694065 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 08:32:30.694334 start: 1.6.7 configure-preseed-file (timeout 00:08:49) [common]
277 08:32:30.694589 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 08:32:30.694844 start: 1.6.8 compress-ramdisk (timeout 00:08:49) [common]
279 08:32:30.695100 Building ramdisk /var/lib/lava/dispatcher/tmp/933468/extract-overlay-ramdisk-5ua4eiai/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/933468/extract-overlay-ramdisk-5ua4eiai/ramdisk
280 08:32:32.998961 >> 166824 blocks
281 08:32:41.240955 Adding RAMdisk u-boot header.
282 08:32:41.241609 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/933468/extract-overlay-ramdisk-5ua4eiai/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/933468/extract-overlay-ramdisk-5ua4eiai/ramdisk.cpio.gz.uboot
283 08:32:41.538468 output: Image Name:
284 08:32:41.538881 output: Created: Mon Nov 4 08:32:41 2024
285 08:32:41.539090 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 08:32:41.539293 output: Data Size: 23433334 Bytes = 22884.12 KiB = 22.35 MiB
287 08:32:41.539494 output: Load Address: 00000000
288 08:32:41.539692 output: Entry Point: 00000000
289 08:32:41.539892 output:
290 08:32:41.540852 rename /var/lib/lava/dispatcher/tmp/933468/extract-overlay-ramdisk-5ua4eiai/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/933468/tftp-deploy-8t0m58g2/ramdisk/ramdisk.cpio.gz.uboot
291 08:32:41.541562 end: 1.6.8 compress-ramdisk (duration 00:00:11) [common]
292 08:32:41.542103 end: 1.6 prepare-tftp-overlay (duration 00:01:03) [common]
293 08:32:41.542622 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:38) [common]
294 08:32:41.543086 No LXC device requested
295 08:32:41.543580 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 08:32:41.544117 start: 1.8 deploy-device-env (timeout 00:08:38) [common]
297 08:32:41.544618 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 08:32:41.545031 Checking files for TFTP limit of 4294967296 bytes.
299 08:32:41.547656 end: 1 tftp-deploy (duration 00:01:22) [common]
300 08:32:41.548251 start: 2 uboot-action (timeout 00:05:00) [common]
301 08:32:41.548771 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 08:32:41.549261 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 08:32:41.549754 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 08:32:41.550275 Using kernel file from prepare-kernel: 933468/tftp-deploy-8t0m58g2/kernel/uImage
305 08:32:41.550894 substitutions:
306 08:32:41.551297 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 08:32:41.551694 - {DTB_ADDR}: 0x01070000
308 08:32:41.552116 - {DTB}: 933468/tftp-deploy-8t0m58g2/dtb/meson-g12b-a311d-libretech-cc.dtb
309 08:32:41.552513 - {INITRD}: 933468/tftp-deploy-8t0m58g2/ramdisk/ramdisk.cpio.gz.uboot
310 08:32:41.552905 - {KERNEL_ADDR}: 0x01080000
311 08:32:41.553294 - {KERNEL}: 933468/tftp-deploy-8t0m58g2/kernel/uImage
312 08:32:41.553681 - {LAVA_MAC}: None
313 08:32:41.554102 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/933468/extract-nfsrootfs-ycl9qdu0
314 08:32:41.554494 - {NFS_SERVER_IP}: 192.168.6.2
315 08:32:41.554880 - {PRESEED_CONFIG}: None
316 08:32:41.555263 - {PRESEED_LOCAL}: None
317 08:32:41.555646 - {RAMDISK_ADDR}: 0x08000000
318 08:32:41.556053 - {RAMDISK}: 933468/tftp-deploy-8t0m58g2/ramdisk/ramdisk.cpio.gz.uboot
319 08:32:41.556445 - {ROOT_PART}: None
320 08:32:41.556828 - {ROOT}: None
321 08:32:41.557207 - {SERVER_IP}: 192.168.6.2
322 08:32:41.557587 - {TEE_ADDR}: 0x83000000
323 08:32:41.557968 - {TEE}: None
324 08:32:41.558347 Parsed boot commands:
325 08:32:41.558720 - setenv autoload no
326 08:32:41.559100 - setenv initrd_high 0xffffffff
327 08:32:41.559477 - setenv fdt_high 0xffffffff
328 08:32:41.559852 - dhcp
329 08:32:41.560255 - setenv serverip 192.168.6.2
330 08:32:41.560636 - tftpboot 0x01080000 933468/tftp-deploy-8t0m58g2/kernel/uImage
331 08:32:41.561020 - tftpboot 0x08000000 933468/tftp-deploy-8t0m58g2/ramdisk/ramdisk.cpio.gz.uboot
332 08:32:41.561401 - tftpboot 0x01070000 933468/tftp-deploy-8t0m58g2/dtb/meson-g12b-a311d-libretech-cc.dtb
333 08:32:41.561785 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/933468/extract-nfsrootfs-ycl9qdu0,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 08:32:41.562181 - bootm 0x01080000 0x08000000 0x01070000
335 08:32:41.562664 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 08:32:41.564149 start: 2.3 connect-device (timeout 00:05:00) [common]
338 08:32:41.564563 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 08:32:41.578314 Setting prompt string to ['lava-test: # ']
340 08:32:41.579800 end: 2.3 connect-device (duration 00:00:00) [common]
341 08:32:41.580450 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 08:32:41.581001 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 08:32:41.581513 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 08:32:41.582619 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 08:32:41.616397 >> OK - accepted request
346 08:32:41.618534 Returned 0 in 0 seconds
347 08:32:41.719613 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 08:32:41.721223 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 08:32:41.721762 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 08:32:41.722254 Setting prompt string to ['Hit any key to stop autoboot']
352 08:32:41.722690 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 08:32:41.724257 Trying 192.168.56.21...
354 08:32:41.724731 Connected to conserv1.
355 08:32:41.725141 Escape character is '^]'.
356 08:32:41.725549
357 08:32:41.725954 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 08:32:41.726363
359 08:32:53.447169 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 08:32:53.447755 bl2_stage_init 0x01
361 08:32:53.448243 bl2_stage_init 0x81
362 08:32:53.452771 hw id: 0x0000 - pwm id 0x01
363 08:32:53.453273 bl2_stage_init 0xc1
364 08:32:53.453693 bl2_stage_init 0x02
365 08:32:53.454147
366 08:32:53.458280 L0:00000000
367 08:32:53.458735 L1:20000703
368 08:32:53.459144 L2:00008067
369 08:32:53.459541 L3:14000000
370 08:32:53.461171 B2:00402000
371 08:32:53.461606 B1:e0f83180
372 08:32:53.461991
373 08:32:53.462375 TE: 58124
374 08:32:53.462757
375 08:32:53.472427 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 08:32:53.472853
377 08:32:53.473238 Board ID = 1
378 08:32:53.473617 Set A53 clk to 24M
379 08:32:53.473995 Set A73 clk to 24M
380 08:32:53.477959 Set clk81 to 24M
381 08:32:53.478376 A53 clk: 1200 MHz
382 08:32:53.478762 A73 clk: 1200 MHz
383 08:32:53.483565 CLK81: 166.6M
384 08:32:53.483973 smccc: 00012a92
385 08:32:53.489171 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 08:32:53.489592 board id: 1
387 08:32:53.497760 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 08:32:53.508440 fw parse done
389 08:32:53.514512 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 08:32:53.557035 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 08:32:53.567942 PIEI prepare done
392 08:32:53.568389 fastboot data load
393 08:32:53.568773 fastboot data verify
394 08:32:53.573593 verify result: 266
395 08:32:53.579174 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 08:32:53.579632 LPDDR4 probe
397 08:32:53.580070 ddr clk to 1584MHz
398 08:32:53.587126 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 08:32:53.624400
400 08:32:53.624841 dmc_version 0001
401 08:32:53.631084 Check phy result
402 08:32:53.637025 INFO : End of CA training
403 08:32:53.637447 INFO : End of initialization
404 08:32:53.642556 INFO : Training has run successfully!
405 08:32:53.642972 Check phy result
406 08:32:53.648196 INFO : End of initialization
407 08:32:53.648613 INFO : End of read enable training
408 08:32:53.653773 INFO : End of fine write leveling
409 08:32:53.659472 INFO : End of Write leveling coarse delay
410 08:32:53.659889 INFO : Training has run successfully!
411 08:32:53.660318 Check phy result
412 08:32:53.664927 INFO : End of initialization
413 08:32:53.665346 INFO : End of read dq deskew training
414 08:32:53.670565 INFO : End of MPR read delay center optimization
415 08:32:53.676183 INFO : End of write delay center optimization
416 08:32:53.681754 INFO : End of read delay center optimization
417 08:32:53.682197 INFO : End of max read latency training
418 08:32:53.687353 INFO : Training has run successfully!
419 08:32:53.687789 1D training succeed
420 08:32:53.696599 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 08:32:53.744146 Check phy result
422 08:32:53.744604 INFO : End of initialization
423 08:32:53.766744 INFO : End of 2D read delay Voltage center optimization
424 08:32:53.786945 INFO : End of 2D read delay Voltage center optimization
425 08:32:53.839028 INFO : End of 2D write delay Voltage center optimization
426 08:32:53.888407 INFO : End of 2D write delay Voltage center optimization
427 08:32:53.893943 INFO : Training has run successfully!
428 08:32:53.894372
429 08:32:53.894772 channel==0
430 08:32:53.899554 RxClkDly_Margin_A0==88 ps 9
431 08:32:53.899975 TxDqDly_Margin_A0==98 ps 10
432 08:32:53.905200 RxClkDly_Margin_A1==88 ps 9
433 08:32:53.905616 TxDqDly_Margin_A1==98 ps 10
434 08:32:53.906013 TrainedVREFDQ_A0==74
435 08:32:53.910755 TrainedVREFDQ_A1==74
436 08:32:53.911197 VrefDac_Margin_A0==25
437 08:32:53.911597 DeviceVref_Margin_A0==40
438 08:32:53.916367 VrefDac_Margin_A1==25
439 08:32:53.916789 DeviceVref_Margin_A1==40
440 08:32:53.917182
441 08:32:53.917573
442 08:32:53.921964 channel==1
443 08:32:53.922382 RxClkDly_Margin_A0==98 ps 10
444 08:32:53.922777 TxDqDly_Margin_A0==98 ps 10
445 08:32:53.927561 RxClkDly_Margin_A1==98 ps 10
446 08:32:53.928015 TxDqDly_Margin_A1==88 ps 9
447 08:32:53.933121 TrainedVREFDQ_A0==77
448 08:32:53.933542 TrainedVREFDQ_A1==77
449 08:32:53.933939 VrefDac_Margin_A0==22
450 08:32:53.938735 DeviceVref_Margin_A0==37
451 08:32:53.939153 VrefDac_Margin_A1==23
452 08:32:53.944356 DeviceVref_Margin_A1==37
453 08:32:53.944783
454 08:32:53.945184 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 08:32:53.949941
456 08:32:53.977957 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
457 08:32:53.978441 2D training succeed
458 08:32:53.983552 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 08:32:53.989137 auto size-- 65535DDR cs0 size: 2048MB
460 08:32:53.989556 DDR cs1 size: 2048MB
461 08:32:53.994754 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 08:32:53.995169 cs0 DataBus test pass
463 08:32:54.000336 cs1 DataBus test pass
464 08:32:54.000756 cs0 AddrBus test pass
465 08:32:54.001154 cs1 AddrBus test pass
466 08:32:54.001543
467 08:32:54.005964 100bdlr_step_size ps== 420
468 08:32:54.006398 result report
469 08:32:54.011576 boot times 0Enable ddr reg access
470 08:32:54.016988 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 08:32:54.030445 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 08:32:54.603651 0.0;M3 CHK:0;cm4_sp_mode 0
473 08:32:54.604356 MVN_1=0x00000000
474 08:32:54.609063 MVN_2=0x00000000
475 08:32:54.614867 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 08:32:54.615307 OPS=0x10
477 08:32:54.615715 ring efuse init
478 08:32:54.616143 chipver efuse init
479 08:32:54.623110 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 08:32:54.623557 [0.018961 Inits done]
481 08:32:54.623954 secure task start!
482 08:32:54.630648 high task start!
483 08:32:54.631109 low task start!
484 08:32:54.631514 run into bl31
485 08:32:54.637156 NOTICE: BL31: v1.3(release):4fc40b1
486 08:32:54.645164 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 08:32:54.645642 NOTICE: BL31: G12A normal boot!
488 08:32:54.670432 NOTICE: BL31: BL33 decompress pass
489 08:32:54.676171 ERROR: Error initializing runtime service opteed_fast
490 08:32:55.909236
491 08:32:55.909864
492 08:32:55.917464 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 08:32:55.917923
494 08:32:55.918352 Model: Libre Computer AML-A311D-CC Alta
495 08:32:56.125878 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 08:32:56.149317 DRAM: 2 GiB (effective 3.8 GiB)
497 08:32:56.292268 Core: 408 devices, 31 uclasses, devicetree: separate
498 08:32:56.298086 WDT: Not starting watchdog@f0d0
499 08:32:56.330309 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 08:32:56.342770 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 08:32:56.347728 ** Bad device specification mmc 0 **
502 08:32:56.358098 Card did not respond to voltage select! : -110
503 08:32:56.365695 ** Bad device specification mmc 0 **
504 08:32:56.366158 Couldn't find partition mmc 0
505 08:32:56.374079 Card did not respond to voltage select! : -110
506 08:32:56.379614 ** Bad device specification mmc 0 **
507 08:32:56.380085 Couldn't find partition mmc 0
508 08:32:56.384663 Error: could not access storage.
509 08:32:57.647824 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 08:32:57.648481 bl2_stage_init 0x01
511 08:32:57.648907 bl2_stage_init 0x81
512 08:32:57.653349 hw id: 0x0000 - pwm id 0x01
513 08:32:57.653783 bl2_stage_init 0xc1
514 08:32:57.654189 bl2_stage_init 0x02
515 08:32:57.654586
516 08:32:57.658957 L0:00000000
517 08:32:57.659372 L1:20000703
518 08:32:57.659766 L2:00008067
519 08:32:57.660192 L3:14000000
520 08:32:57.661845 B2:00402000
521 08:32:57.662278 B1:e0f83180
522 08:32:57.662679
523 08:32:57.663077 TE: 58124
524 08:32:57.663467
525 08:32:57.673016 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 08:32:57.673458
527 08:32:57.673865 Board ID = 1
528 08:32:57.674259 Set A53 clk to 24M
529 08:32:57.674648 Set A73 clk to 24M
530 08:32:57.678688 Set clk81 to 24M
531 08:32:57.679119 A53 clk: 1200 MHz
532 08:32:57.679520 A73 clk: 1200 MHz
533 08:32:57.684166 CLK81: 166.6M
534 08:32:57.684616 smccc: 00012a92
535 08:32:57.689772 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 08:32:57.690294 board id: 1
537 08:32:57.698444 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 08:32:57.709121 fw parse done
539 08:32:57.715010 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 08:32:57.757635 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 08:32:57.768476 PIEI prepare done
542 08:32:57.768916 fastboot data load
543 08:32:57.769324 fastboot data verify
544 08:32:57.774120 verify result: 266
545 08:32:57.779725 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 08:32:57.780355 LPDDR4 probe
547 08:32:57.780771 ddr clk to 1584MHz
548 08:32:57.787699 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 08:32:57.825000
550 08:32:57.825504 dmc_version 0001
551 08:32:57.831684 Check phy result
552 08:32:57.837543 INFO : End of CA training
553 08:32:57.837960 INFO : End of initialization
554 08:32:57.843153 INFO : Training has run successfully!
555 08:32:57.843574 Check phy result
556 08:32:57.848691 INFO : End of initialization
557 08:32:57.849112 INFO : End of read enable training
558 08:32:57.854277 INFO : End of fine write leveling
559 08:32:57.860017 INFO : End of Write leveling coarse delay
560 08:32:57.860434 INFO : Training has run successfully!
561 08:32:57.860830 Check phy result
562 08:32:57.865555 INFO : End of initialization
563 08:32:57.865982 INFO : End of read dq deskew training
564 08:32:57.871188 INFO : End of MPR read delay center optimization
565 08:32:57.876698 INFO : End of write delay center optimization
566 08:32:57.882333 INFO : End of read delay center optimization
567 08:32:57.882762 INFO : End of max read latency training
568 08:32:57.888012 INFO : Training has run successfully!
569 08:32:57.888433 1D training succeed
570 08:32:57.897305 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 08:32:57.944690 Check phy result
572 08:32:57.945144 INFO : End of initialization
573 08:32:57.967270 INFO : End of 2D read delay Voltage center optimization
574 08:32:57.987252 INFO : End of 2D read delay Voltage center optimization
575 08:32:58.039332 INFO : End of 2D write delay Voltage center optimization
576 08:32:58.088445 INFO : End of 2D write delay Voltage center optimization
577 08:32:58.094021 INFO : Training has run successfully!
578 08:32:58.094450
579 08:32:58.094853 channel==0
580 08:32:58.099616 RxClkDly_Margin_A0==88 ps 9
581 08:32:58.100066 TxDqDly_Margin_A0==98 ps 10
582 08:32:58.102966 RxClkDly_Margin_A1==88 ps 9
583 08:32:58.103393 TxDqDly_Margin_A1==88 ps 9
584 08:32:58.108587 TrainedVREFDQ_A0==74
585 08:32:58.109016 TrainedVREFDQ_A1==74
586 08:32:58.109418 VrefDac_Margin_A0==25
587 08:32:58.114270 DeviceVref_Margin_A0==40
588 08:32:58.114690 VrefDac_Margin_A1==25
589 08:32:58.119711 DeviceVref_Margin_A1==40
590 08:32:58.120162
591 08:32:58.120567
592 08:32:58.120957 channel==1
593 08:32:58.121344 RxClkDly_Margin_A0==98 ps 10
594 08:32:58.125349 TxDqDly_Margin_A0==98 ps 10
595 08:32:58.125780 RxClkDly_Margin_A1==88 ps 9
596 08:32:58.130972 TxDqDly_Margin_A1==88 ps 9
597 08:32:58.131404 TrainedVREFDQ_A0==77
598 08:32:58.131808 TrainedVREFDQ_A1==77
599 08:32:58.136515 VrefDac_Margin_A0==23
600 08:32:58.136935 DeviceVref_Margin_A0==37
601 08:32:58.142247 VrefDac_Margin_A1==24
602 08:32:58.142669 DeviceVref_Margin_A1==37
603 08:32:58.143068
604 08:32:58.147676 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 08:32:58.148145
606 08:32:58.175666 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
607 08:32:58.181294 2D training succeed
608 08:32:58.186981 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 08:32:58.187415 auto size-- 65535DDR cs0 size: 2048MB
610 08:32:58.192491 DDR cs1 size: 2048MB
611 08:32:58.192917 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 08:32:58.198185 cs0 DataBus test pass
613 08:32:58.198630 cs1 DataBus test pass
614 08:32:58.199036 cs0 AddrBus test pass
615 08:32:58.203683 cs1 AddrBus test pass
616 08:32:58.204134
617 08:32:58.204538 100bdlr_step_size ps== 420
618 08:32:58.204938 result report
619 08:32:58.209270 boot times 0Enable ddr reg access
620 08:32:58.216857 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 08:32:58.230319 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 08:32:58.802505 0.0;M3 CHK:0;cm4_sp_mode 0
623 08:32:58.803081 MVN_1=0x00000000
624 08:32:58.807959 MVN_2=0x00000000
625 08:32:58.813681 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 08:32:58.814139 OPS=0x10
627 08:32:58.814542 ring efuse init
628 08:32:58.814941 chipver efuse init
629 08:32:58.822057 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 08:32:58.822552 [0.018961 Inits done]
631 08:32:58.822937 secure task start!
632 08:32:58.829438 high task start!
633 08:32:58.829859 low task start!
634 08:32:58.830243 run into bl31
635 08:32:58.836166 NOTICE: BL31: v1.3(release):4fc40b1
636 08:32:58.844018 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 08:32:58.844443 NOTICE: BL31: G12A normal boot!
638 08:32:58.869327 NOTICE: BL31: BL33 decompress pass
639 08:32:58.874958 ERROR: Error initializing runtime service opteed_fast
640 08:33:00.107916
641 08:33:00.108541
642 08:33:00.116261 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 08:33:00.116706
644 08:33:00.117110 Model: Libre Computer AML-A311D-CC Alta
645 08:33:00.324708 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 08:33:00.348204 DRAM: 2 GiB (effective 3.8 GiB)
647 08:33:00.491167 Core: 408 devices, 31 uclasses, devicetree: separate
648 08:33:00.496989 WDT: Not starting watchdog@f0d0
649 08:33:00.529211 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 08:33:00.541714 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 08:33:00.546677 ** Bad device specification mmc 0 **
652 08:33:00.557026 Card did not respond to voltage select! : -110
653 08:33:00.564689 ** Bad device specification mmc 0 **
654 08:33:00.565124 Couldn't find partition mmc 0
655 08:33:00.573037 Card did not respond to voltage select! : -110
656 08:33:00.578594 ** Bad device specification mmc 0 **
657 08:33:00.579020 Couldn't find partition mmc 0
658 08:33:00.583690 Error: could not access storage.
659 08:33:00.927134 Net: eth0: ethernet@ff3f0000
660 08:33:00.927693 starting USB...
661 08:33:01.178906 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 08:33:01.179413 Starting the controller
663 08:33:01.185901 USB XHCI 1.10
664 08:33:02.899426 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 08:33:02.900092 bl2_stage_init 0x01
666 08:33:02.900529 bl2_stage_init 0x81
667 08:33:02.905025 hw id: 0x0000 - pwm id 0x01
668 08:33:02.905480 bl2_stage_init 0xc1
669 08:33:02.905892 bl2_stage_init 0x02
670 08:33:02.906296
671 08:33:02.910668 L0:00000000
672 08:33:02.911101 L1:20000703
673 08:33:02.911507 L2:00008067
674 08:33:02.911902 L3:14000000
675 08:33:02.916276 B2:00402000
676 08:33:02.916712 B1:e0f83180
677 08:33:02.917115
678 08:33:02.917515 TE: 58159
679 08:33:02.917910
680 08:33:02.921934 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 08:33:02.922370
682 08:33:02.922774 Board ID = 1
683 08:33:02.927374 Set A53 clk to 24M
684 08:33:02.927810 Set A73 clk to 24M
685 08:33:02.928251 Set clk81 to 24M
686 08:33:02.933110 A53 clk: 1200 MHz
687 08:33:02.933545 A73 clk: 1200 MHz
688 08:33:02.933945 CLK81: 166.6M
689 08:33:02.934340 smccc: 00012ab5
690 08:33:02.938624 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 08:33:02.944163 board id: 1
692 08:33:02.950264 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 08:33:02.960786 fw parse done
694 08:33:02.966618 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 08:33:03.009276 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 08:33:03.020170 PIEI prepare done
697 08:33:03.020609 fastboot data load
698 08:33:03.021021 fastboot data verify
699 08:33:03.025879 verify result: 266
700 08:33:03.031380 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 08:33:03.031815 LPDDR4 probe
702 08:33:03.032271 ddr clk to 1584MHz
703 08:33:03.039464 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 08:33:03.076667
705 08:33:03.077123 dmc_version 0001
706 08:33:03.083383 Check phy result
707 08:33:03.089254 INFO : End of CA training
708 08:33:03.089689 INFO : End of initialization
709 08:33:03.094896 INFO : Training has run successfully!
710 08:33:03.095324 Check phy result
711 08:33:03.100391 INFO : End of initialization
712 08:33:03.100825 INFO : End of read enable training
713 08:33:03.106021 INFO : End of fine write leveling
714 08:33:03.111672 INFO : End of Write leveling coarse delay
715 08:33:03.112124 INFO : Training has run successfully!
716 08:33:03.112527 Check phy result
717 08:33:03.117235 INFO : End of initialization
718 08:33:03.117663 INFO : End of read dq deskew training
719 08:33:03.122950 INFO : End of MPR read delay center optimization
720 08:33:03.128374 INFO : End of write delay center optimization
721 08:33:03.134020 INFO : End of read delay center optimization
722 08:33:03.134446 INFO : End of max read latency training
723 08:33:03.139631 INFO : Training has run successfully!
724 08:33:03.140091 1D training succeed
725 08:33:03.148988 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 08:33:03.196383 Check phy result
727 08:33:03.196827 INFO : End of initialization
728 08:33:03.218985 INFO : End of 2D read delay Voltage center optimization
729 08:33:03.238403 INFO : End of 2D read delay Voltage center optimization
730 08:33:03.291376 INFO : End of 2D write delay Voltage center optimization
731 08:33:03.340680 INFO : End of 2D write delay Voltage center optimization
732 08:33:03.346259 INFO : Training has run successfully!
733 08:33:03.346692
734 08:33:03.347094 channel==0
735 08:33:03.351897 RxClkDly_Margin_A0==88 ps 9
736 08:33:03.352364 TxDqDly_Margin_A0==98 ps 10
737 08:33:03.357407 RxClkDly_Margin_A1==88 ps 9
738 08:33:03.357836 TxDqDly_Margin_A1==98 ps 10
739 08:33:03.358238 TrainedVREFDQ_A0==74
740 08:33:03.363075 TrainedVREFDQ_A1==74
741 08:33:03.363500 VrefDac_Margin_A0==25
742 08:33:03.363894 DeviceVref_Margin_A0==40
743 08:33:03.368677 VrefDac_Margin_A1==25
744 08:33:03.369103 DeviceVref_Margin_A1==40
745 08:33:03.369501
746 08:33:03.369894
747 08:33:03.374244 channel==1
748 08:33:03.374674 RxClkDly_Margin_A0==98 ps 10
749 08:33:03.375069 TxDqDly_Margin_A0==88 ps 9
750 08:33:03.379893 RxClkDly_Margin_A1==98 ps 10
751 08:33:03.380352 TxDqDly_Margin_A1==98 ps 10
752 08:33:03.385444 TrainedVREFDQ_A0==75
753 08:33:03.385869 TrainedVREFDQ_A1==77
754 08:33:03.386270 VrefDac_Margin_A0==22
755 08:33:03.391068 DeviceVref_Margin_A0==38
756 08:33:03.391487 VrefDac_Margin_A1==23
757 08:33:03.396622 DeviceVref_Margin_A1==37
758 08:33:03.397057
759 08:33:03.397460 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 08:33:03.402206
761 08:33:03.430297 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000017 00000016 00000018 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
762 08:33:03.430918 2D training succeed
763 08:33:03.436122 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 08:33:03.441606 auto size-- 65535DDR cs0 size: 2048MB
765 08:33:03.442143 DDR cs1 size: 2048MB
766 08:33:03.447241 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 08:33:03.447806 cs0 DataBus test pass
768 08:33:03.452810 cs1 DataBus test pass
769 08:33:03.453340 cs0 AddrBus test pass
770 08:33:03.453757 cs1 AddrBus test pass
771 08:33:03.454160
772 08:33:03.458603 100bdlr_step_size ps== 420
773 08:33:03.459200 result report
774 08:33:03.464120 boot times 0Enable ddr reg access
775 08:33:03.469439 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 08:33:03.482846 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 08:33:04.056653 0.0;M3 CHK:0;cm4_sp_mode 0
778 08:33:04.057205 MVN_1=0x00000000
779 08:33:04.061940 MVN_2=0x00000000
780 08:33:04.067789 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 08:33:04.068334 OPS=0x10
782 08:33:04.068734 ring efuse init
783 08:33:04.069118 chipver efuse init
784 08:33:04.073273 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 08:33:04.078906 [0.018961 Inits done]
786 08:33:04.079356 secure task start!
787 08:33:04.079744 high task start!
788 08:33:04.083522 low task start!
789 08:33:04.083975 run into bl31
790 08:33:04.090048 NOTICE: BL31: v1.3(release):4fc40b1
791 08:33:04.098041 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 08:33:04.098503 NOTICE: BL31: G12A normal boot!
793 08:33:04.123799 NOTICE: BL31: BL33 decompress pass
794 08:33:04.128256 ERROR: Error initializing runtime service opteed_fast
795 08:33:05.361754
796 08:33:05.362370
797 08:33:05.370239 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 08:33:05.370727
799 08:33:05.371146 Model: Libre Computer AML-A311D-CC Alta
800 08:33:05.577832 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 08:33:05.601930 DRAM: 2 GiB (effective 3.8 GiB)
802 08:33:05.744896 Core: 408 devices, 31 uclasses, devicetree: separate
803 08:33:05.749859 WDT: Not starting watchdog@f0d0
804 08:33:05.783071 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 08:33:05.795485 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 08:33:05.800531 ** Bad device specification mmc 0 **
807 08:33:05.810819 Card did not respond to voltage select! : -110
808 08:33:05.818463 ** Bad device specification mmc 0 **
809 08:33:05.818930 Couldn't find partition mmc 0
810 08:33:05.826827 Card did not respond to voltage select! : -110
811 08:33:05.832360 ** Bad device specification mmc 0 **
812 08:33:05.832831 Couldn't find partition mmc 0
813 08:33:05.837398 Error: could not access storage.
814 08:33:06.179803 Net: eth0: ethernet@ff3f0000
815 08:33:06.180372 starting USB...
816 08:33:06.431678 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 08:33:06.432269 Starting the controller
818 08:33:06.438655 USB XHCI 1.10
819 08:33:08.598108 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 08:33:08.598759 bl2_stage_init 0x01
821 08:33:08.599186 bl2_stage_init 0x81
822 08:33:08.603549 hw id: 0x0000 - pwm id 0x01
823 08:33:08.604148 bl2_stage_init 0xc1
824 08:33:08.604574 bl2_stage_init 0x02
825 08:33:08.604978
826 08:33:08.609187 L0:00000000
827 08:33:08.609710 L1:20000703
828 08:33:08.610119 L2:00008067
829 08:33:08.610524 L3:14000000
830 08:33:08.614713 B2:00402000
831 08:33:08.615221 B1:e0f83180
832 08:33:08.615627
833 08:33:08.616069 TE: 58167
834 08:33:08.616486
835 08:33:08.620352 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 08:33:08.620916
837 08:33:08.621337 Board ID = 1
838 08:33:08.625861 Set A53 clk to 24M
839 08:33:08.626367 Set A73 clk to 24M
840 08:33:08.626783 Set clk81 to 24M
841 08:33:08.631453 A53 clk: 1200 MHz
842 08:33:08.632056 A73 clk: 1200 MHz
843 08:33:08.632881 CLK81: 166.6M
844 08:33:08.633323 smccc: 00012abe
845 08:33:08.637061 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 08:33:08.642785 board id: 1
847 08:33:08.648573 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 08:33:08.659232 fw parse done
849 08:33:08.665244 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 08:33:08.707736 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 08:33:08.718947 PIEI prepare done
852 08:33:08.719495 fastboot data load
853 08:33:08.719760 fastboot data verify
854 08:33:08.724343 verify result: 266
855 08:33:08.729922 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 08:33:08.730324 LPDDR4 probe
857 08:33:08.730574 ddr clk to 1584MHz
858 08:33:08.737859 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 08:33:08.775162
860 08:33:08.775774 dmc_version 0001
861 08:33:08.781823 Check phy result
862 08:33:08.787686 INFO : End of CA training
863 08:33:08.788111 INFO : End of initialization
864 08:33:08.793370 INFO : Training has run successfully!
865 08:33:08.793776 Check phy result
866 08:33:08.799181 INFO : End of initialization
867 08:33:08.799614 INFO : End of read enable training
868 08:33:08.802205 INFO : End of fine write leveling
869 08:33:08.807822 INFO : End of Write leveling coarse delay
870 08:33:08.813344 INFO : Training has run successfully!
871 08:33:08.813920 Check phy result
872 08:33:08.814213 INFO : End of initialization
873 08:33:08.818956 INFO : End of read dq deskew training
874 08:33:08.824556 INFO : End of MPR read delay center optimization
875 08:33:08.824963 INFO : End of write delay center optimization
876 08:33:08.830219 INFO : End of read delay center optimization
877 08:33:08.835759 INFO : End of max read latency training
878 08:33:08.836188 INFO : Training has run successfully!
879 08:33:08.841285 1D training succeed
880 08:33:08.847297 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 08:33:08.894888 Check phy result
882 08:33:08.895313 INFO : End of initialization
883 08:33:08.916643 INFO : End of 2D read delay Voltage center optimization
884 08:33:08.936892 INFO : End of 2D read delay Voltage center optimization
885 08:33:08.989852 INFO : End of 2D write delay Voltage center optimization
886 08:33:09.039197 INFO : End of 2D write delay Voltage center optimization
887 08:33:09.044669 INFO : Training has run successfully!
888 08:33:09.045074
889 08:33:09.045294 channel==0
890 08:33:09.050396 RxClkDly_Margin_A0==88 ps 9
891 08:33:09.050797 TxDqDly_Margin_A0==98 ps 10
892 08:33:09.053665 RxClkDly_Margin_A1==88 ps 9
893 08:33:09.054023 TxDqDly_Margin_A1==98 ps 10
894 08:33:09.059186 TrainedVREFDQ_A0==74
895 08:33:09.059580 TrainedVREFDQ_A1==74
896 08:33:09.064776 VrefDac_Margin_A0==25
897 08:33:09.065496 DeviceVref_Margin_A0==40
898 08:33:09.065969 VrefDac_Margin_A1==25
899 08:33:09.070364 DeviceVref_Margin_A1==40
900 08:33:09.071032
901 08:33:09.071497
902 08:33:09.072041 channel==1
903 08:33:09.072638 RxClkDly_Margin_A0==88 ps 9
904 08:33:09.075960 TxDqDly_Margin_A0==88 ps 9
905 08:33:09.076534 RxClkDly_Margin_A1==98 ps 10
906 08:33:09.081519 TxDqDly_Margin_A1==98 ps 10
907 08:33:09.082072 TrainedVREFDQ_A0==77
908 08:33:09.082513 TrainedVREFDQ_A1==77
909 08:33:09.087273 VrefDac_Margin_A0==23
910 08:33:09.087922 DeviceVref_Margin_A0==37
911 08:33:09.092706 VrefDac_Margin_A1==22
912 08:33:09.093334 DeviceVref_Margin_A1==37
913 08:33:09.093811
914 08:33:09.098313 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 08:33:09.098939
916 08:33:09.126298 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000018 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
917 08:33:09.131851 2D training succeed
918 08:33:09.137504 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 08:33:09.138058 auto size-- 65535DDR cs0 size: 2048MB
920 08:33:09.143128 DDR cs1 size: 2048MB
921 08:33:09.143634 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 08:33:09.148675 cs0 DataBus test pass
923 08:33:09.149950 cs1 DataBus test pass
924 08:33:09.150390 cs0 AddrBus test pass
925 08:33:09.154263 cs1 AddrBus test pass
926 08:33:09.154761
927 08:33:09.155256 100bdlr_step_size ps== 420
928 08:33:09.155735 result report
929 08:33:09.160064 boot times 0Enable ddr reg access
930 08:33:09.166853 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 08:33:09.181081 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 08:33:09.754786 0.0;M3 CHK:0;cm4_sp_mode 0
933 08:33:09.755211 MVN_1=0x00000000
934 08:33:09.760255 MVN_2=0x00000000
935 08:33:09.765897 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 08:33:09.766221 OPS=0x10
937 08:33:09.766450 ring efuse init
938 08:33:09.766672 chipver efuse init
939 08:33:09.771531 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 08:33:09.777232 [0.018961 Inits done]
941 08:33:09.777555 secure task start!
942 08:33:09.777766 high task start!
943 08:33:09.781892 low task start!
944 08:33:09.782200 run into bl31
945 08:33:09.788437 NOTICE: BL31: v1.3(release):4fc40b1
946 08:33:09.796324 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 08:33:09.796868 NOTICE: BL31: G12A normal boot!
948 08:33:09.821548 NOTICE: BL31: BL33 decompress pass
949 08:33:09.827308 ERROR: Error initializing runtime service opteed_fast
950 08:33:11.060034
951 08:33:11.060432
952 08:33:11.067446 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 08:33:11.067856
954 08:33:11.068238 Model: Libre Computer AML-A311D-CC Alta
955 08:33:11.276077 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 08:33:11.299401 DRAM: 2 GiB (effective 3.8 GiB)
957 08:33:11.443302 Core: 408 devices, 31 uclasses, devicetree: separate
958 08:33:11.449013 WDT: Not starting watchdog@f0d0
959 08:33:11.481501 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 08:33:11.493930 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 08:33:11.498083 ** Bad device specification mmc 0 **
962 08:33:11.509204 Card did not respond to voltage select! : -110
963 08:33:11.515923 ** Bad device specification mmc 0 **
964 08:33:11.516280 Couldn't find partition mmc 0
965 08:33:11.525232 Card did not respond to voltage select! : -110
966 08:33:11.530676 ** Bad device specification mmc 0 **
967 08:33:11.531122 Couldn't find partition mmc 0
968 08:33:11.535817 Error: could not access storage.
969 08:33:11.878386 Net: eth0: ethernet@ff3f0000
970 08:33:11.878829 starting USB...
971 08:33:12.130266 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 08:33:12.130965 Starting the controller
973 08:33:12.137147 USB XHCI 1.10
974 08:33:13.691195 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
975 08:33:13.699356 scanning usb for storage devices... 0 Storage Device(s) found
977 08:33:13.750982 Hit any key to stop autoboot: 1
978 08:33:13.751948 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
979 08:33:13.752637 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
980 08:33:13.753190 Setting prompt string to ['=>']
981 08:33:13.753764 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
982 08:33:13.766845 0
983 08:33:13.767827 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
984 08:33:13.768616 Sending with 10 millisecond of delay
986 08:33:14.903556 => setenv autoload no
987 08:33:14.914451 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
988 08:33:14.919753 setenv autoload no
989 08:33:14.920548 Sending with 10 millisecond of delay
991 08:33:16.718713 => setenv initrd_high 0xffffffff
992 08:33:16.729563 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
993 08:33:16.730477 setenv initrd_high 0xffffffff
994 08:33:16.731230 Sending with 10 millisecond of delay
996 08:33:18.347552 => setenv fdt_high 0xffffffff
997 08:33:18.358409 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
998 08:33:18.359293 setenv fdt_high 0xffffffff
999 08:33:18.360075 Sending with 10 millisecond of delay
1001 08:33:18.651943 => dhcp
1002 08:33:18.662719 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
1003 08:33:18.663588 dhcp
1004 08:33:18.664098 Speed: 1000, full duplex
1005 08:33:18.664550 BOOTP broadcast 1
1006 08:33:18.671069 DHCP client bound to address 192.168.6.27 (8 ms)
1007 08:33:18.671828 Sending with 10 millisecond of delay
1009 08:33:20.348575 => setenv serverip 192.168.6.2
1010 08:33:20.359389 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1011 08:33:20.360377 setenv serverip 192.168.6.2
1012 08:33:20.361129 Sending with 10 millisecond of delay
1014 08:33:24.084821 => tftpboot 0x01080000 933468/tftp-deploy-8t0m58g2/kernel/uImage
1015 08:33:24.095669 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1016 08:33:24.096663 tftpboot 0x01080000 933468/tftp-deploy-8t0m58g2/kernel/uImage
1017 08:33:24.097201 Speed: 1000, full duplex
1018 08:33:24.097692 Using ethernet@ff3f0000 device
1019 08:33:24.098569 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1020 08:33:24.103941 Filename '933468/tftp-deploy-8t0m58g2/kernel/uImage'.
1021 08:33:24.108031 Load address: 0x1080000
1022 08:33:26.944636 Loading: *################################################## 43.6 MiB
1023 08:33:26.945282 15.4 MiB/s
1024 08:33:26.945757 done
1025 08:33:26.949028 Bytes transferred = 45713984 (2b98a40 hex)
1026 08:33:26.949874 Sending with 10 millisecond of delay
1028 08:33:31.638239 => tftpboot 0x08000000 933468/tftp-deploy-8t0m58g2/ramdisk/ramdisk.cpio.gz.uboot
1029 08:33:31.649016 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1030 08:33:31.649825 tftpboot 0x08000000 933468/tftp-deploy-8t0m58g2/ramdisk/ramdisk.cpio.gz.uboot
1031 08:33:31.650269 Speed: 1000, full duplex
1032 08:33:31.650677 Using ethernet@ff3f0000 device
1033 08:33:31.651780 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1034 08:33:31.660450 Filename '933468/tftp-deploy-8t0m58g2/ramdisk/ramdisk.cpio.gz.uboot'.
1035 08:33:31.660928 Load address: 0x8000000
1036 08:33:38.165563 Loading: *######################T ############################ 22.3 MiB
1037 08:33:38.166150 3.4 MiB/s
1038 08:33:38.166569 done
1039 08:33:38.169907 Bytes transferred = 23433398 (16590b6 hex)
1040 08:33:38.170662 Sending with 10 millisecond of delay
1042 08:33:43.340110 => tftpboot 0x01070000 933468/tftp-deploy-8t0m58g2/dtb/meson-g12b-a311d-libretech-cc.dtb
1043 08:33:43.350886 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:58)
1044 08:33:43.351687 tftpboot 0x01070000 933468/tftp-deploy-8t0m58g2/dtb/meson-g12b-a311d-libretech-cc.dtb
1045 08:33:43.352197 Speed: 1000, full duplex
1046 08:33:43.352617 Using ethernet@ff3f0000 device
1047 08:33:43.355970 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1048 08:33:43.363441 Filename '933468/tftp-deploy-8t0m58g2/dtb/meson-g12b-a311d-libretech-cc.dtb'.
1049 08:33:43.373954 Load address: 0x1070000
1050 08:33:43.386120 Loading: *################################################## 53.4 KiB
1051 08:33:43.386589 2.9 MiB/s
1052 08:33:43.387002 done
1053 08:33:43.390929 Bytes transferred = 54703 (d5af hex)
1054 08:33:43.391640 Sending with 10 millisecond of delay
1056 08:33:56.694028 => setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/933468/extract-nfsrootfs-ycl9qdu0,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1057 08:33:56.704833 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:45)
1058 08:33:56.705687 setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/933468/extract-nfsrootfs-ycl9qdu0,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
1059 08:33:56.706387 Sending with 10 millisecond of delay
1061 08:33:59.044458 => bootm 0x01080000 0x08000000 0x01070000
1062 08:33:59.055237 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1063 08:33:59.055767 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:42)
1064 08:33:59.056777 bootm 0x01080000 0x08000000 0x01070000
1065 08:33:59.057215 ## Booting kernel from Legacy Image at 01080000 ...
1066 08:33:59.060115 Image Name:
1067 08:33:59.065662 Image Type: AArch64 Linux Kernel Image (uncompressed)
1068 08:33:59.066099 Data Size: 45713920 Bytes = 43.6 MiB
1069 08:33:59.067800 Load Address: 01080000
1070 08:33:59.073588 Entry Point: 01080000
1071 08:33:59.266594 Verifying Checksum ... OK
1072 08:33:59.267109 ## Loading init Ramdisk from Legacy Image at 08000000 ...
1073 08:33:59.271838 Image Name:
1074 08:33:59.277443 Image Type: AArch64 Linux RAMDisk Image (uncompressed)
1075 08:33:59.277890 Data Size: 23433334 Bytes = 22.3 MiB
1076 08:33:59.282825 Load Address: 00000000
1077 08:33:59.283265 Entry Point: 00000000
1078 08:33:59.385068 Verifying Checksum ... OK
1079 08:33:59.385588 ## Flattened Device Tree blob at 01070000
1080 08:33:59.390555 Booting using the fdt blob at 0x1070000
1081 08:33:59.390990 Working FDT set to 1070000
1082 08:33:59.395012 Loading Kernel Image
1083 08:33:59.546697 Loading Ramdisk to 7e9a6000, end 7ffff076 ... OK
1084 08:33:59.554732 Loading Device Tree to 000000007e995000, end 000000007e9a55ae ... OK
1085 08:33:59.555205 Working FDT set to 7e995000
1086 08:33:59.555621
1087 08:33:59.556555 end: 2.4.3 bootloader-commands (duration 00:00:46) [common]
1088 08:33:59.557151 start: 2.4.4 auto-login-action (timeout 00:03:42) [common]
1089 08:33:59.557617 Setting prompt string to ['Linux version [0-9]']
1090 08:33:59.558067 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1091 08:33:59.558529 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
1092 08:33:59.559548 Starting kernel ...
1093 08:33:59.560040
1094 08:33:59.594793 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
1095 08:33:59.595763 start: 2.4.4.1 login-action (timeout 00:03:42) [common]
1096 08:33:59.596337 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
1097 08:33:59.596804 Setting prompt string to []
1098 08:33:59.597285 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
1099 08:33:59.597741 Using line separator: #'\n'#
1100 08:33:59.598147 No login prompt set.
1101 08:33:59.598570 Parsing kernel messages
1102 08:33:59.598963 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
1103 08:33:59.599772 [login-action] Waiting for messages, (timeout 00:03:42)
1104 08:33:59.600255 Waiting using forced prompt support (timeout 00:01:51)
1105 08:33:59.611376 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j361670-arm64-gcc-12-defconfig-rf6vt) (aarch64-linux-gnu-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP PREEMPT Mon Nov 4 08:13:19 UTC 2024
1106 08:33:59.616883 [ 0.000000] KASLR disabled due to lack of seed
1107 08:33:59.622491 [ 0.000000] Machine model: Libre Computer AML-A311D-CC Alta
1108 08:33:59.627823 [ 0.000000] efi: UEFI not found.
1109 08:33:59.633521 [ 0.000000] [Firmware Bug]: Kernel image misaligned at boot, please fix your bootloader!
1110 08:33:59.638789 [ 0.000000] Reserved memory: created CMA memory pool at 0x00000000e4c00000, size 256 MiB
1111 08:33:59.649812 [ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
1112 08:33:59.660849 [ 0.000000] OF: reserved mem: 0x00000000e4c00000..0x00000000f4bfffff (262144 KiB) map reusable linux,cma
1113 08:33:59.666405 [ 0.000000] OF: reserved mem: 0x0000000005000000..0x00000000052fffff (3072 KiB) nomap non-reusable secmon@5000000
1114 08:33:59.677387 [ 0.000000] OF: reserved mem: 0x0000000005300000..0x00000000072fffff (32768 KiB) nomap non-reusable secmon@5300000
1115 08:33:59.688455 [ 0.000000] earlycon: meson0 at MMIO 0x00000000ff803000 (options '115200n8')
1116 08:33:59.693954 [ 0.000000] printk: legacy bootconsole [meson0] enabled
1117 08:33:59.699492 [ 0.000000] NUMA: Faking a node at [mem 0x0000000000000000-0x00000000f4e5afff]
1118 08:33:59.705040 [ 0.000000] NODE_DATA(0) allocated [mem 0xe4666a80-0xe46690bf]
1119 08:33:59.705513 [ 0.000000] Zone ranges:
1120 08:33:59.710587 [ 0.000000] DMA [mem 0x0000000000000000-0x00000000f4e5afff]
1121 08:33:59.716137 [ 0.000000] DMA32 empty
1122 08:33:59.716591 [ 0.000000] Normal empty
1123 08:33:59.721547 [ 0.000000] Movable zone start for each node
1124 08:33:59.727074 [ 0.000000] Early memory node ranges
1125 08:33:59.732644 [ 0.000000] node 0: [mem 0x0000000000000000-0x0000000004ffffff]
1126 08:33:59.738292 [ 0.000000] node 0: [mem 0x0000000005000000-0x00000000072fffff]
1127 08:33:59.743881 [ 0.000000] node 0: [mem 0x0000000007300000-0x00000000f4e5afff]
1128 08:33:59.749199 [ 0.000000] Initmem setup node 0 [mem 0x0000000000000000-0x00000000f4e5afff]
1129 08:33:59.776665 [ 0.000000] On node 0, zone DMA: 12709 pages in unavailable ranges
1130 08:33:59.782134 [ 0.000000] psci: probing for conduit method from DT.
1131 08:33:59.782647 [ 0.000000] psci: PSCIv1.0 detected in firmware.
1132 08:33:59.791160 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
1133 08:33:59.791618 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
1134 08:33:59.796636 [ 0.000000] psci: SMC Calling Convention v1.1
1135 08:33:59.802162 [ 0.000000] percpu: Embedded 25 pages/cpu s61656 r8192 d32552 u102400
1136 08:33:59.811224 [ 0.000000] Detected VIPT I-cache on CPU0
1137 08:33:59.811660 [ 0.000000] CPU features: detected: ARM erratum 845719
1138 08:33:59.816735 [ 0.000000] alternatives: applying boot alternatives
1139 08:33:59.838860 [ 0.000000] Kernel command line: console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/933468/extract-nfsrootfs-ycl9qdu0,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
1140 08:33:59.849870 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
1141 08:33:59.855413 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
1142 08:33:59.860890 <6>[ 0.000000] Fallback order for Node 0: 0
1143 08:33:59.866422 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1003099
1144 08:33:59.871939 <6>[ 0.000000] Policy zone: DMA
1145 08:33:59.877575 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
1146 08:33:59.882994 <6>[ 0.000000] software IO TLB: SWIOTLB bounce buffer size adjusted to 3MB
1147 08:33:59.888533 <6>[ 0.000000] software IO TLB: area num 8.
1148 08:33:59.895225 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000dfc00000-0x00000000e0000000] (4MB)
1149 08:33:59.942736 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=6, Nodes=1
1150 08:33:59.948195 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
1151 08:33:59.953686 <6>[ 0.000000] rcu: RCU event tracing is enabled.
1152 08:33:59.959260 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=512 to nr_cpu_ids=6.
1153 08:33:59.964729 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
1154 08:33:59.970214 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
1155 08:33:59.975751 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
1156 08:33:59.981372 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=6
1157 08:33:59.992353 <6>[ 0.000000] RCU Tasks: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1158 08:34:00.003419 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=6.
1159 08:34:00.008862 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
1160 08:34:00.014395 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
1161 08:34:00.014845 <6>[ 0.000000] GIC: Using split EOI/Deactivate mode
1162 08:34:00.024265 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
1163 08:34:00.037037 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
1164 08:34:00.046033 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
1165 08:34:00.051441 <6>[ 0.000000] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
1166 08:34:00.057050 <6>[ 0.008799] Console: colour dummy device 80x25
1167 08:34:00.071573 <6>[ 0.012942] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
1168 08:34:00.072194 <6>[ 0.023295] pid_max: default: 32768 minimum: 301
1169 08:34:00.077099 <6>[ 0.028191] LSM: initializing lsm=capability
1170 08:34:00.088203 <6>[ 0.032734] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1171 08:34:00.093622 <6>[ 0.040212] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
1172 08:34:00.099153 <6>[ 0.052303] rcu: Hierarchical SRCU implementation.
1173 08:34:00.104675 <6>[ 0.053215] rcu: Max phase no-delay instances is 1000.
1174 08:34:00.110233 <6>[ 0.058904] Timer migration: 1 hierarchy levels; 8 children per group; 1 crossnode level
1175 08:34:00.115711 <6>[ 0.071576] EFI services will not be available.
1176 08:34:00.121220 <6>[ 0.072092] smp: Bringing up secondary CPUs ...
1177 08:34:00.126748 <6>[ 0.077171] Detected VIPT I-cache on CPU1
1178 08:34:00.132272 <6>[ 0.077291] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
1179 08:34:00.137774 <6>[ 0.078646] CPU features: detected: Spectre-v2
1180 08:34:00.143408 <6>[ 0.078660] CPU features: detected: Spectre-v4
1181 08:34:00.148827 <6>[ 0.078665] CPU features: detected: Spectre-BHB
1182 08:34:00.154433 <6>[ 0.078670] CPU features: detected: ARM erratum 858921
1183 08:34:00.154999 <6>[ 0.078678] Detected VIPT I-cache on CPU2
1184 08:34:00.165411 <6>[ 0.078752] arch_timer: Enabling local workaround for ARM erratum 858921
1185 08:34:00.170959 <6>[ 0.078769] arch_timer: CPU2: Trapping CNTVCT access
1186 08:34:00.176431 <6>[ 0.078779] CPU2: Booted secondary processor 0x0000000100 [0x410fd092]
1187 08:34:00.181912 <6>[ 0.079553] Detected VIPT I-cache on CPU3
1188 08:34:00.187442 <6>[ 0.079598] arch_timer: Enabling local workaround for ARM erratum 858921
1189 08:34:00.192953 <6>[ 0.079607] arch_timer: CPU3: Trapping CNTVCT access
1190 08:34:00.198492 <6>[ 0.079614] CPU3: Booted secondary processor 0x0000000101 [0x410fd092]
1191 08:34:00.204050 <6>[ 0.080334] Detected VIPT I-cache on CPU4
1192 08:34:00.209610 <6>[ 0.080380] arch_timer: Enabling local workaround for ARM erratum 858921
1193 08:34:00.215091 <6>[ 0.080389] arch_timer: CPU4: Trapping CNTVCT access
1194 08:34:00.220614 <6>[ 0.080397] CPU4: Booted secondary processor 0x0000000102 [0x410fd092]
1195 08:34:00.226204 <6>[ 0.081149] Detected VIPT I-cache on CPU5
1196 08:34:00.231622 <6>[ 0.081197] arch_timer: Enabling local workaround for ARM erratum 858921
1197 08:34:00.237186 <6>[ 0.081206] arch_timer: CPU5: Trapping CNTVCT access
1198 08:34:00.242665 <6>[ 0.081213] CPU5: Booted secondary processor 0x0000000103 [0x410fd092]
1199 08:34:00.248205 <6>[ 0.081337] smp: Brought up 1 node, 6 CPUs
1200 08:34:00.253714 <6>[ 0.203226] SMP: Total of 6 processors activated.
1201 08:34:00.259242 <6>[ 0.208131] CPU: All CPU(s) started at EL2
1202 08:34:00.264739 <6>[ 0.212475] CPU features: detected: 32-bit EL0 Support
1203 08:34:00.270275 <6>[ 0.217788] CPU features: detected: 32-bit EL1 Support
1204 08:34:00.275786 <6>[ 0.223149] CPU features: detected: CRC32 instructions
1205 08:34:00.281438 <6>[ 0.228544] alternatives: applying system-wide alternatives
1206 08:34:00.292437 <6>[ 0.235729] Memory: 3557432K/4012396K available (17280K kernel code, 4898K rwdata, 11880K rodata, 10432K init, 742K bss, 187800K reserved, 262144K cma-reserved)
1207 08:34:00.299241 <6>[ 0.250080] devtmpfs: initialized
1208 08:34:00.310314 <6>[ 0.259242] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
1209 08:34:00.315810 <6>[ 0.263599] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
1210 08:34:00.321449 <6>[ 0.274421] 21392 pages in range for non-PLT usage
1211 08:34:00.326849 <6>[ 0.274431] 512912 pages in range for PLT usage
1212 08:34:00.332453 <6>[ 0.275958] pinctrl core: initialized pinctrl subsystem
1213 08:34:00.337864 <6>[ 0.288022] DMI not present or invalid.
1214 08:34:00.343447 <6>[ 0.292341] NET: Registered PF_NETLINK/PF_ROUTE protocol family
1215 08:34:00.348923 <6>[ 0.297069] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
1216 08:34:00.354476 <6>[ 0.303850] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
1217 08:34:00.365479 <6>[ 0.311950] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
1218 08:34:00.370999 <6>[ 0.319429] audit: initializing netlink subsys (disabled)
1219 08:34:00.376519 <5>[ 0.325191] audit: type=2000 audit(0.244:1): state=initialized audit_enabled=0 res=1
1220 08:34:00.387540 <6>[ 0.326691] thermal_sys: Registered thermal governor 'step_wise'
1221 08:34:00.393093 <6>[ 0.332939] thermal_sys: Registered thermal governor 'power_allocator'
1222 08:34:00.398623 <6>[ 0.339196] cpuidle: using governor menu
1223 08:34:00.404121 <6>[ 0.350176] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
1224 08:34:00.409654 <6>[ 0.357111] ASID allocator initialised with 65536 entries
1225 08:34:00.417911 <6>[ 0.364661] Serial: AMBA PL011 UART driver
1226 08:34:00.423231 <6>[ 0.375234] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1227 08:34:00.439298 <6>[ 0.390646] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /soc/vpu@ff900000
1228 08:34:00.450316 <6>[ 0.393306] platform ff900000.vpu: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1229 08:34:00.455821 <6>[ 0.406428] platform ff900000.vpu: Fixed dependency cycle(s) with /cvbs-connector
1230 08:34:00.461442 <6>[ 0.409686] platform cvbs-connector: Fixed dependency cycle(s) with /soc/vpu@ff900000
1231 08:34:00.472487 <6>[ 0.418112] platform ff600000.hdmi-tx: Fixed dependency cycle(s) with /hdmi-connector
1232 08:34:00.477914 <6>[ 0.425735] platform hdmi-connector: Fixed dependency cycle(s) with /soc/bus@ff600000/hdmi-tx@0
1233 08:34:00.488952 <6>[ 0.439336] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
1234 08:34:00.494520 <6>[ 0.441554] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
1235 08:34:00.500140 <6>[ 0.448035] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
1236 08:34:00.505545 <6>[ 0.455013] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
1237 08:34:00.516578 <6>[ 0.461482] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
1238 08:34:00.522074 <6>[ 0.468467] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
1239 08:34:00.527584 <6>[ 0.474936] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
1240 08:34:00.533109 <6>[ 0.481921] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
1241 08:34:00.538620 <6>[ 0.489937] ACPI: Interpreter disabled.
1242 08:34:00.544252 <6>[ 0.495358] iommu: Default domain type: Translated
1243 08:34:00.549673 <6>[ 0.497454] iommu: DMA domain TLB invalidation policy: strict mode
1244 08:34:00.555256 <5>[ 0.504142] SCSI subsystem initialized
1245 08:34:00.560785 <6>[ 0.508061] usbcore: registered new interface driver usbfs
1246 08:34:00.566274 <6>[ 0.513512] usbcore: registered new interface driver hub
1247 08:34:00.571799 <6>[ 0.519031] usbcore: registered new device driver usb
1248 08:34:00.577281 <6>[ 0.525309] pps_core: LinuxPPS API ver. 1 registered
1249 08:34:00.582777 <6>[ 0.529449] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
1250 08:34:00.588323 <6>[ 0.538768] PTP clock support registered
1251 08:34:00.593837 <6>[ 0.543010] EDAC MC: Ver: 3.0.0
1252 08:34:00.599457 <6>[ 0.546664] scmi_core: SCMI protocol bus registered
1253 08:34:00.600072 <6>[ 0.552330] FPGA manager framework
1254 08:34:00.604897 <6>[ 0.555030] Advanced Linux Sound Architecture Driver Initialized.
1255 08:34:00.610506 <6>[ 0.561975] vgaarb: loaded
1256 08:34:00.615944 <6>[ 0.564535] clocksource: Switched to clocksource arch_sys_counter
1257 08:34:00.621495 <5>[ 0.570690] VFS: Disk quotas dquot_6.6.0
1258 08:34:00.626966 <6>[ 0.574664] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
1259 08:34:00.632520 <6>[ 0.581873] pnp: PnP ACPI: disabled
1260 08:34:00.638031 <6>[ 0.590278] NET: Registered PF_INET protocol family
1261 08:34:00.643576 <6>[ 0.590693] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
1262 08:34:00.654573 <6>[ 0.600862] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
1263 08:34:00.660072 <6>[ 0.606867] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
1264 08:34:00.671171 <6>[ 0.614763] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
1265 08:34:00.676639 <6>[ 0.622997] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
1266 08:34:00.682187 <6>[ 0.630795] TCP: Hash tables configured (established 32768 bind 32768)
1267 08:34:00.687696 <6>[ 0.637269] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
1268 08:34:00.698752 <6>[ 0.644115] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
1269 08:34:00.704242 <6>[ 0.651542] NET: Registered PF_UNIX/PF_LOCAL protocol family
1270 08:34:00.709786 <6>[ 0.657643] RPC: Registered named UNIX socket transport module.
1271 08:34:00.715322 <6>[ 0.663403] RPC: Registered udp transport module.
1272 08:34:00.720812 <6>[ 0.668312] RPC: Registered tcp transport module.
1273 08:34:00.726347 <6>[ 0.673226] RPC: Registered tcp-with-tls transport module.
1274 08:34:00.731877 <6>[ 0.678919] RPC: Registered tcp NFSv4.1 backchannel transport module.
1275 08:34:00.737385 <6>[ 0.685567] PCI: CLS 0 bytes, default 64
1276 08:34:00.737962 <6>[ 0.689835] Unpacking initramfs...
1277 08:34:00.742888 <6>[ 0.695930] kvm [1]: nv: 554 coarse grained trap handlers
1278 08:34:00.748496 <6>[ 0.699236] kvm [1]: IPA Size Limit: 40 bits
1279 08:34:00.753935 <6>[ 0.704875] kvm [1]: vgic interrupt IRQ9
1280 08:34:00.759562 <6>[ 0.707576] kvm [1]: Hyp nVHE mode initialized successfully
1281 08:34:00.764975 <5>[ 0.714582] Initialise system trusted keyrings
1282 08:34:00.770528 <6>[ 0.718192] workingset: timestamp_bits=42 max_order=20 bucket_order=0
1283 08:34:00.776051 <6>[ 0.725083] squashfs: version 4.0 (2009/01/31) Phillip Lougher
1284 08:34:00.781632 <5>[ 0.730949] NFS: Registering the id_resolver key type
1285 08:34:00.787053 <5>[ 0.735969] Key type id_resolver registered
1286 08:34:00.792576 <5>[ 0.740332] Key type id_legacy registered
1287 08:34:00.798092 <6>[ 0.744589] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
1288 08:34:00.803618 <6>[ 0.751458] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
1289 08:34:00.811001 <6>[ 0.759237] 9p: Installing v9fs 9p2000 file system support
1290 08:34:00.849136 <5>[ 0.805970] Key type asymmetric registered
1291 08:34:00.854622 <5>[ 0.806013] Asymmetric key parser 'x509' registered
1292 08:34:00.865670 <6>[ 0.809871] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
1293 08:34:00.866280 <6>[ 0.817393] io scheduler mq-deadline registered
1294 08:34:00.871194 <6>[ 0.822132] io scheduler kyber registered
1295 08:34:00.876732 <6>[ 0.826398] io scheduler bfq registered
1296 08:34:00.883133 <6>[ 0.832344] irq_meson_gpio: 100 to 8 gpio interrupt mux initialized
1297 08:34:00.899585 <6>[ 0.852600] ledtrig-cpu: registered to indicate activity on CPUs
1298 08:34:00.932001 <6>[ 0.883883] soc soc0: Amlogic Meson G12B (A311D) Revision 29:b (10:2) Detected
1299 08:34:00.951712 <6>[ 0.897391] Serial: 8250/16550 driver, 4 ports<6>[ 0.901962] ff803000.serial: ttyAML0 at MMIO 0xff803000 (irq = 14, base_baud = 1500000) is a meson_uart
1300 08:34:00.957305 <6>[ 0.911582] printk: legacy console [ttyAML0] enabled
1301 08:34:00.962775 <6>[ 0.911582] printk: legacy console [ttyAML0] enabled
1302 08:34:00.968355 <6>[ 0.916378] printk: legacy bootconsole [meson0] disabled
1303 08:34:00.973872 <6>[ 0.916378] printk: legacy bootconsole [meson0] disabled
1304 08:34:00.979558 <6>[ 0.929358] msm_serial: driver initialized
1305 08:34:00.984963 <6>[ 0.932303] SuperH (H)SCI(F) driver initialized
1306 08:34:00.985550 <6>[ 0.936838] STM32 USART driver initialized
1307 08:34:00.990576 <5>[ 0.943037] random: crng init done
1308 08:34:00.997619 <6>[ 0.948718] loop: module loaded
1309 08:34:00.998223 <6>[ 0.949986] megasas: 07.727.03.00-rc1
1310 08:34:01.003185 <6>[ 0.958972] tun: Universal TUN/TAP device driver, 1.6
1311 08:34:01.008714 <6>[ 0.960161] thunder_xcv, ver 1.0
1312 08:34:01.014290 <6>[ 0.962159] thunder_bgx, ver 1.0
1313 08:34:01.014872 <6>[ 0.965613] nicpf, ver 1.0
1314 08:34:01.019833 <6>[ 0.970209] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
1315 08:34:01.025335 <6>[ 0.975997] hns3: Copyright (c) 2017 Huawei Corporation.
1316 08:34:01.030865 <6>[ 0.981585] hclge is initializing
1317 08:34:01.036660 <6>[ 0.985131] e1000: Intel(R) PRO/1000 Network Driver
1318 08:34:01.042009 <6>[ 0.990202] e1000: Copyright (c) 1999-2006 Intel Corporation.
1319 08:34:01.047544 <6>[ 0.996221] e1000e: Intel(R) PRO/1000 Network Driver
1320 08:34:01.053060 <6>[ 1.001382] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
1321 08:34:01.058650 <6>[ 1.007561] igb: Intel(R) Gigabit Ethernet Network Driver
1322 08:34:01.064220 <6>[ 1.013169] igb: Copyright (c) 2007-2014 Intel Corporation.
1323 08:34:01.069743 <6>[ 1.019000] igbvf: Intel(R) Gigabit Virtual Function Network Driver
1324 08:34:01.075298 <6>[ 1.025474] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
1325 08:34:01.080865 <6>[ 1.032244] sky2: driver version 1.30
1326 08:34:01.086438 <6>[ 1.037341] VFIO - User Level meta-driver version: 0.3
1327 08:34:01.091975 <6>[ 1.044821] usbcore: registered new interface driver usb-storage
1328 08:34:01.097940 <6>[ 1.050866] i2c_dev: i2c /dev entries driver
1329 08:34:01.110786 <6>[ 1.062032] sdhci: Secure Digital Host Controller Interface driver
1330 08:34:01.111413 <6>[ 1.062831] sdhci: Copyright(c) Pierre Ossman
1331 08:34:01.121823 <6>[ 1.068548] Synopsys Designware Multimedia Card Interface Driver
1332 08:34:01.127340 <6>[ 1.075077] sdhci-pltfm: SDHCI platform and OF driver helper
1333 08:34:01.127944 <6>[ 1.082759] meson-sm: secure-monitor enabled
1334 08:34:01.140249 <6>[ 1.085237] usbcore: registered new interface driver usbhid
1335 08:34:01.140844 <6>[ 1.089882] usbhid: USB HID core driver
1336 08:34:01.147749 <6>[ 1.104629] NET: Registered PF_PACKET protocol family
1337 08:34:01.153398 <6>[ 1.104724] 9pnet: Installing 9P2000 support
1338 08:34:01.160455 <5>[ 1.108873] Key type dns_resolver registered
1339 08:34:01.167885 <6>[ 1.120444] registered taskstats version 1
1340 08:34:01.168542 <5>[ 1.120623] Loading compiled-in X.509 certificates
1341 08:34:01.174564 <6>[ 1.129245] Demotion targets for Node 0: null
1342 08:34:01.215484 <6>[ 1.172114] dwc3-meson-g12a ffe09000.usb: USB2 ports: 2
1343 08:34:01.220852 <6>[ 1.172159] dwc3-meson-g12a ffe09000.usb: USB3 ports: 1
1344 08:34:01.229858 <4>[ 1.182375] dwc2 ff400000.usb: supply vusb_d not found, using dummy regulator
1345 08:34:01.235402 <4>[ 1.184931] dwc2 ff400000.usb: supply vusb_a not found, using dummy regulator
1346 08:34:01.246619 <6>[ 1.192507] dwc2 ff400000.usb: EPs: 7, dedicated fifos, 712 entries in SPRAM
1347 08:34:01.252098 <6>[ 1.201814] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1348 08:34:01.257616 <6>[ 1.205192] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 1
1349 08:34:01.268690 <6>[ 1.213181] xhci-hcd xhci-hcd.0.auto: hcc params 0x0228fe6c hci version 0x110 quirks 0x0000808000000010
1350 08:34:01.274222 <6>[ 1.222720] xhci-hcd xhci-hcd.0.auto: irq 16, io mem 0xff500000
1351 08:34:01.279786 <6>[ 1.228938] xhci-hcd xhci-hcd.0.auto: xHCI Host Controller
1352 08:34:01.290856 <6>[ 1.234563] xhci-hcd xhci-hcd.0.auto: new USB bus registered, assigned bus number 2
1353 08:34:01.296440 <6>[ 1.242448] xhci-hcd xhci-hcd.0.auto: Host supports USB 3.0 SuperSpeed
1354 08:34:01.297051 <6>[ 1.249727] hub 1-0:1.0: USB hub found
1355 08:34:01.301957 <6>[ 1.253212] hub 1-0:1.0: 2 ports detected
1356 08:34:01.313065 <6>[ 1.259253] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
1357 08:34:01.313686 <6>[ 1.266167] hub 2-0:1.0: USB hub found
1358 08:34:01.320192 <6>[ 1.269763] hub 2-0:1.0: 1 port detected
1359 08:34:01.345289 <6>[ 1.300376] meson-gx-mmc ffe05000.mmc: Got CD GPIO
1360 08:34:01.357279 <6>[ 1.311675] meson-gx-mmc ffe07000.mmc: allocated mmc-pwrseq
1361 08:34:01.393693 <6>[ 1.346663] Trying to probe devices needed for running init ...
1362 08:34:01.552101 <6>[ 1.504570] usb 1-1: new high-speed USB device number 2 using xhci-hcd
1363 08:34:01.688744 <6>[ 1.639896] mmc0: new ultra high speed SDR104 SDXC card at address e624
1364 08:34:01.694307 <6>[ 1.642101] mmcblk0: mmc0:e624 SD64G 59.5 GiB
1365 08:34:01.694871 <6>[ 1.648008] Freeing initrd memory: 22884K
1366 08:34:01.697803 <6>[ 1.648196] mmcblk0: p1
1367 08:34:01.740794 <6>[ 1.697513] hub 1-1:1.0: USB hub found
1368 08:34:01.746585 <6>[ 1.697876] hub 1-1:1.0: 4 ports detected
1369 08:34:01.808222 <6>[ 1.760676] usb 2-1: new SuperSpeed USB device number 2 using xhci-hcd
1370 08:34:01.853388 <6>[ 1.810177] hub 2-1:1.0: USB hub found
1371 08:34:01.859163 <6>[ 1.810998] hub 2-1:1.0: 4 ports detected
1372 08:34:13.691806 <6>[ 13.648600] clk: Disabling unused clocks
1373 08:34:13.697267 <6>[ 13.648767] PM: genpd: Disabling unused power domains
1374 08:34:13.704621 <6>[ 13.652461] ALSA device list:
1375 08:34:13.705154 <6>[ 13.655660] No soundcards found.
1376 08:34:13.711027 <6>[ 13.667990] Freeing unused kernel memory: 10432K
1377 08:34:13.716423 <6>[ 13.668096] Run /init as init process
1378 08:34:13.722186 Loading, please wait...
1379 08:34:13.753841 Starting systemd-udevd version 252.22-1~deb12u1
1380 08:34:14.170239 <6>[ 14.126953] mc: Linux media interface: v0.10
1381 08:34:14.175656 <6>[ 14.131350] videodev: Linux video capture interface: v2.00
1382 08:34:14.184628 <6>[ 14.135373] meson8b-dwmac ff3f0000.ethernet: IRQ eth_wake_irq not found
1383 08:34:14.190091 <6>[ 14.138456] meson8b-dwmac ff3f0000.ethernet: IRQ eth_lpi not found
1384 08:34:14.195619 <6>[ 14.144855] meson8b-dwmac ff3f0000.ethernet: IRQ sfty not found
1385 08:34:14.201158 <6>[ 14.151155] meson8b-dwmac ff3f0000.ethernet: PTP uses main clock
1386 08:34:14.212362 <6>[ 14.157890] meson8b-dwmac ff3f0000.ethernet: User ID: 0x11, Synopsys ID: 0x37
1387 08:34:14.217886 <6>[ 14.164655] meson8b-dwmac ff3f0000.ethernet: DWMAC1000
1388 08:34:14.223423 <6>[ 14.170078] meson8b-dwmac ff3f0000.ethernet: DMA HW capability register supported
1389 08:34:14.228947 <6>[ 14.177789] meson8b-dwmac ff3f0000.ethernet: RX Checksum Offload Engine supported
1390 08:34:14.234424 <6>[ 14.185497] meson8b-dwmac ff3f0000.ethernet: COE Type 2
1391 08:34:14.245504 <6>[ 14.190952] meson8b-dwmac ff3f0000.ethernet: TX Checksum insertion supported
1392 08:34:14.251153 <6>[ 14.191373] meson-vrtc ff8000a8.rtc: registered as rtc0
1393 08:34:14.256775 <6>[ 14.198234] meson8b-dwmac ff3f0000.ethernet: Wake-Up On Lan supported
1394 08:34:14.262305 <6>[ 14.200675] meson8b-dwmac ff3f0000.ethernet: Normal descriptors
1395 08:34:14.273494 <6>[ 14.211195] meson-vrtc ff8000a8.rtc: setting system clock to 1970-01-01T00:00:14 UTC (14)
1396 08:34:14.278968 <6>[ 14.216557] meson8b-dwmac ff3f0000.ethernet: Ring mode enabled
1397 08:34:14.284577 <3>[ 14.226456] debugfs: Directory 'ff800280.cec' with parent 'regmap' already present!
1398 08:34:14.295591 <6>[ 14.231027] meson8b-dwmac ff3f0000.ethernet: Enable RX Mitigation via HW Watchdog Timer
1399 08:34:14.301007 <4>[ 14.237233] meson-pwm ff802000.pwm: using obsolete compatible, please consider updating dt
1400 08:34:14.334459 <4>[ 14.285614] meson_vdec: module is from the staging directory, the quality is unknown, you have been warned.
1401 08:34:14.339938 <6>[ 14.292326] meson-drm ff900000.vpu: Queued 2 outputs on vpu
1402 08:34:14.345457 <6>[ 14.296966] Registered IR keymap rc-empty
1403 08:34:14.356579 <6>[ 14.305555] rc rc0: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0
1404 08:34:14.362746 <6>[ 14.310203] input: meson-ir as /devices/platform/soc/ff800000.bus/ff808000.ir/rc/rc0/input0
1405 08:34:14.373822 <6>[ 14.322887] meson-dw-hdmi ff600000.hdmi-tx: Detected HDMI TX controller v2.01a with HDCP (meson_dw_hdmi_phy)
1406 08:34:14.379469 <6>[ 14.328246] meson-dw-hdmi ff600000.hdmi-tx: registered DesignWare HDMI I2C bus driver
1407 08:34:14.384925 <6>[ 14.328593] rc rc0: sw decoder init
1408 08:34:14.396038 <6>[ 14.339026] meson-drm ff900000.vpu: bound ff600000.hdmi-tx (ops meson_dw_hdmi_ops [meson_dw_hdmi])
1409 08:34:14.401565 <6>[ 14.349695] usbcore: registered new device driver onboard-usb-dev
1410 08:34:14.407102 <6>[ 14.350219] panfrost ffe40000.gpu: clock rate = 24000000
1411 08:34:14.412658 <6>[ 14.352598] meson-ir ff808000.ir: receiver initialized
1412 08:34:14.418259 <3>[ 14.360659] meson-drm ff900000.vpu: DSI transceiver device is disabled
1413 08:34:14.429305 <3>[ 14.365982] panfrost ffe40000.gpu: error -ENODEV: _opp_set_regulators: no regulator (mali) found
1414 08:34:14.434800 <6>[ 14.373921] [drm] Initialized meson 1.0.0 for ff900000.vpu on minor 0
1415 08:34:14.440794 <6>[ 14.385496] panfrost ffe40000.gpu: mali-g52 id 0x7212 major 0x0 minor 0x0 status 0x0
1416 08:34:14.451518 <6>[ 14.396082] panfrost ffe40000.gpu: features: 00000000,00000cf7, issues: 00000000,00000400
1417 08:34:14.457024 <6>[ 14.397860] meson8b-dwmac ff3f0000.ethernet end0: renamed from eth0
1418 08:34:14.468104 <6>[ 14.404450] panfrost ffe40000.gpu: Features: L2:0x07110206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
1419 08:34:14.474884 <6>[ 14.423028] panfrost ffe40000.gpu: shader_present=0x3 l2_present=0x1
1420 08:34:14.656749 <6>[ 14.440354] cpufreq: cpufreq_online: CPU2: Running at unlisted initial frequency: 999999 KHz, changing to: 1000000 KHz
1421 08:34:14.667807 <6>[ 14.443182] [drm] Initialized panfrost 1.2.0 for ffe40000.gpu on minor 1
1422 08:34:14.673323 <6>[ 14.589336] Console: switching to colour frame buffer device 128x48
1423 08:34:14.679458 <6>[ 14.626703] meson-drm ff900000.vpu: [drm] fb0: mesondrmfb frame buffer device
1424 08:34:14.924674 <6>[ 14.881518] hub 1-1:1.0: USB hub found
1425 08:34:14.929429 <6>[ 14.881820] hub 1-1:1.0: 4 ports detected
1426 08:34:15.073256 <4>[ 15.024562] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1427 08:34:15.078802 <3>[ 15.026953] onboard-usb-dev 1-1: Failed to suspend device, error -32
1428 08:34:15.084842 <3>[ 15.033373] onboard-usb-dev 1-1: can't set config #1, error -71
1429 08:34:15.101212 <4>[ 15.052561] xhci-hcd xhci-hcd.0.auto: USB core suspending port 1-1 not in U0/U1/U2
1430 08:34:15.106774 <6>[ 15.054880] onboard-usb-dev 1-1: USB disconnect, device number 2
1431 08:34:15.112886 <3>[ 15.061038] onboard-usb-dev 1-1: Failed to suspend device, error -32
1432 08:34:15.359085 <6>[ 15.312588] usb 1-1: new high-speed USB device number 3 using xhci-hcd
1433 08:34:15.532833 <6>[ 15.489662] hub 1-1:1.0: USB hub found
1434 08:34:15.537660 <6>[ 15.490006] hub 1-1:1.0: 4 ports detected
1435 08:34:15.545345 Begin: Loading essential drivers ... done.
1436 08:34:15.550879 Begin: Running /scripts/init-premount ... done.
1437 08:34:15.556508 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
1438 08:34:15.569285 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
1439 08:34:15.569832 Device /sys/class/net/end0 found
1440 08:34:15.570297 done.
1441 08:34:15.592180 Begin: Waiting up to 180 secs for any network device to become available ... done.
1442 08:34:15.641840 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
<6>[ 15.589929] meson8b-dwmac ff3f0000.ethernet end0: Register MEM_TYPE_PAGE_POOL RxQ-0
1443 08:34:15.642391
1444 08:34:15.696093 <6>[ 15.649510] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1445 08:34:15.731153 <6>[ 15.680650] meson8b-dwmac ff3f0000.ethernet end0: PHY [mdio_mux-0.0:00] driver [RTL8211F Gigabit Ethernet] (irq=23)
1446 08:34:15.746119 <6>[ 15.697388] meson8b-dwmac ff3f0000.ethernet end0: No Safety Features support found
1447 08:34:15.751826 <6>[ 15.699578] meson8b-dwmac ff3f0000.ethernet end0: PTP not supported by HW
1448 08:34:15.760068 <6>[ 15.707077] meson8b-dwmac ff3f0000.ethernet end0: configuring for phy/rgmii link mode
1449 08:34:15.948723 <4>[ 15.905476] rc rc0: two consecutive events of type space
1450 08:34:15.968127 <6>[ 15.921511] usb 2-1: reset SuperSpeed USB device number 2 using xhci-hcd
1451 08:34:17.755330 IP-Config: no response after 2 secs - giving up
1452 08:34:17.802846 IP-Config: end0 hardware address de:ca:d3:e3:c6:63 mtu 1500 DHCP
1453 08:34:18.716033 <6>[ 18.667555] meson8b-dwmac ff3f0000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
1454 08:34:20.016844 IP-Config: end0 guessed broadcast address 192.168.6.255
1455 08:34:20.022364 IP-Config: end0 complete (dhcp from 192.168.6.1):
1456 08:34:20.027842 address: 192.168.6.27 broadcast: 192.168.6.255 netmask: 255.255.255.0
1457 08:34:20.038867 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
1458 08:34:20.039364 rootserver: 192.168.6.1 rootpath:
1459 08:34:20.041488 filename :
1460 08:34:20.142637 done.
1461 08:34:20.153443 Begin: Running /scripts/nfs-bottom ... done.
1462 08:34:20.161698 Begin: Running /scripts/init-bottom ... done.
1463 08:34:20.467449 <30>[ 20.420657] systemd[1]: System time before build time, advancing clock.
1464 08:34:20.523422 <6>[ 20.480133] NET: Registered PF_INET6 protocol family
1465 08:34:20.528939 <6>[ 20.481056] Segment Routing with IPv6
1466 08:34:20.533233 <6>[ 20.483638] In-situ OAM (IOAM) with IPv6
1467 08:34:20.619565 <30>[ 20.545236] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
1468 08:34:20.625103 <30>[ 20.572644] systemd[1]: Detected architecture arm64.
1469 08:34:20.625593
1470 08:34:20.628257 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
1471 08:34:20.628726
1472 08:34:20.640450 <30>[ 20.594339] systemd[1]: Hostname set to <debian-bookworm-arm64>.
1473 08:34:21.291502 <30>[ 21.244241] systemd[1]: Queued start job for default target graphical.target.
1474 08:34:21.331906 <30>[ 21.283059] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
1475 08:34:21.338358 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
1476 08:34:21.350191 <30>[ 21.301529] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
1477 08:34:21.357717 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
1478 08:34:21.370371 <30>[ 21.321604] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
1479 08:34:21.378645 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
1480 08:34:21.389997 <30>[ 21.341306] systemd[1]: Created slice user.slice - User and Session Slice.
1481 08:34:21.396518 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
1482 08:34:21.407511 <30>[ 21.356815] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
1483 08:34:21.418988 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
1484 08:34:21.430058 <30>[ 21.376743] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
1485 08:34:21.436629 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
1486 08:34:21.458762 <30>[ 21.396712] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
1487 08:34:21.464441 <30>[ 21.410776] systemd[1]: Expecting device dev-ttyAML0.device - /dev/ttyAML0...
1488 08:34:21.470338 Expecting device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0...
1489 08:34:21.481383 <30>[ 21.432630] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
1490 08:34:21.488606 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
1491 08:34:21.505416 <30>[ 21.456666] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
1492 08:34:21.513866 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
1493 08:34:21.525445 <30>[ 21.476670] systemd[1]: Reached target paths.target - Path Units.
1494 08:34:21.529598 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
1495 08:34:21.541407 <30>[ 21.492637] systemd[1]: Reached target remote-fs.target - Remote File Systems.
1496 08:34:21.547593 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
1497 08:34:21.555921 <30>[ 21.508631] systemd[1]: Reached target slices.target - Slice Units.
1498 08:34:21.561848 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
1499 08:34:21.573416 <30>[ 21.524644] systemd[1]: Reached target swap.target - Swaps.
1500 08:34:21.576563 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
1501 08:34:21.589418 <30>[ 21.540666] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
1502 08:34:21.597316 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
1503 08:34:21.613570 <30>[ 21.564815] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
1504 08:34:21.621754 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
1505 08:34:21.634717 <30>[ 21.586026] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
1506 08:34:21.642557 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
1507 08:34:21.658266 <30>[ 21.609547] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
1508 08:34:21.666728 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
1509 08:34:21.681697 <30>[ 21.632971] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
1510 08:34:21.688533 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
1511 08:34:21.699625 <30>[ 21.649555] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
1512 08:34:21.706669 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
1513 08:34:21.719236 <30>[ 21.670530] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
1514 08:34:21.724857 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
1515 08:34:21.737570 <30>[ 21.688862] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
1516 08:34:21.745154 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
1517 08:34:21.785526 <30>[ 21.736755] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
1518 08:34:21.791280 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
1519 08:34:21.804108 <30>[ 21.755380] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
1520 08:34:21.810789 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
1521 08:34:21.824002 <30>[ 21.775258] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
1522 08:34:21.830436 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
1523 08:34:21.847250 <30>[ 21.792990] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
1524 08:34:21.856256 <30>[ 21.806094] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
1525 08:34:21.864463 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
1526 08:34:21.884254 <30>[ 21.835529] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
1527 08:34:21.891282 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
1528 08:34:21.904105 <30>[ 21.855395] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
1529 08:34:21.910786 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
1530 08:34:21.923480 <30>[ 21.874793] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
1531 08:34:21.934611 <6>[ 21.879812] device-mapper: ioctl: 4.48.0-ioctl (2023-03-01) initialised: dm-devel@lists.linux.dev
1532 08:34:21.938667 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
1533 08:34:21.952265 <30>[ 21.903495] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
1534 08:34:21.959687 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
1535 08:34:21.976093 <30>[ 21.927410] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
1536 08:34:21.982490 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
1537 08:34:21.995937 <30>[ 21.947226] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
1538 08:34:22.001535 Starting [0;1;39mmodprob<6>[ 21.955256] fuse: init (API version 7.41)
1539 08:34:22.005054 e@loop.ser…e[0m - Load Kernel Module loop...
1540 08:34:22.026144 <30>[ 21.977432] systemd[1]: Starting systemd-journald.service - Journal Service...
1541 08:34:22.031669 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
1542 08:34:22.051761 <30>[ 22.003065] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
1543 08:34:22.058496 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
1544 08:34:22.074533 <30>[ 22.025728] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
1545 08:34:22.083508 Starting [0;1;39msystemd-network-g… units from Kernel command line...
1546 08:34:22.102979 <30>[ 22.054221] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
1547 08:34:22.110826 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
1548 08:34:22.132747 <30>[ 22.083982] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
1549 08:34:22.139842 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
1550 08:34:22.152513 <30>[ 22.103697] systemd[1]: Started systemd-journald.service - Journal Service.
1551 08:34:22.158363 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
1552 08:34:22.174077 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
1553 08:34:22.189092 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
1554 08:34:22.209024 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
1555 08:34:22.229289 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
1556 08:34:22.249653 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
1557 08:34:22.265694 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
1558 08:34:22.281404 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
1559 08:34:22.297680 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
1560 08:34:22.313466 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
1561 08:34:22.329673 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
1562 08:34:22.341550 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
1563 08:34:22.357330 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
1564 08:34:22.373446 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
1565 08:34:22.389725 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
1566 08:34:22.424090 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
1567 08:34:22.434542 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
1568 08:34:22.446773 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
1569 08:34:22.458980 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
1570 08:34:22.473526 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
1571 08:34:22.487892 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
1572 08:34:22.511706 <46>[ 22.462875] systemd-journald[232]: Received client request to flush runtime journal.
1573 08:34:22.519018 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
1574 08:34:22.533476 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
1575 08:34:22.545114 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
1576 08:34:22.565558 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
1577 08:34:22.577492 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
1578 08:34:22.635296 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
1579 08:34:22.688421 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
1580 08:34:22.783921 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
1581 08:34:22.805423 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
1582 08:34:22.821004 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
1583 08:34:22.832236 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
1584 08:34:22.884702 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
1585 08:34:22.901694 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
1586 08:34:23.093928 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
1587 08:34:23.136738 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
1588 08:34:23.218725 [[0;32m OK [0m] Found device [0;1;39mdev-ttyAML0.device[0m - /dev/ttyAML0.
1589 08:34:23.231711 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
1590 08:34:23.293786 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
1591 08:34:23.300179 <5>[ 23.249248] cfg80211: Loading compiled-in X.509 certificates for regulatory database
1592 08:34:23.310924 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
1593 08:34:23.347042 <5>[ 23.298398] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
1594 08:34:23.352853 <5>[ 23.299086] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
1595 08:34:23.361813 <4>[ 23.307354] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
1596 08:34:23.365297 <6>[ 23.315197] cfg80211: failed to load regulatory.db
1597 08:34:23.388512 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
1598 08:34:23.426096 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
1599 08:34:23.435389 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
1600 08:34:23.468598 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
1601 08:34:23.490592 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
1602 08:34:23.497594 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
1603 08:34:23.509074 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
1604 08:34:23.519877 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
1605 08:34:23.537021 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
1606 08:34:23.552784 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
1607 08:34:23.571336 <46>[ 23.512245] systemd-journald[232]: Oldest entry in /var/log/journal/44a983756b26438995e691b947c527e4/system.journal is older than the configured file retention duration (1month), suggesting rotation.
1608 08:34:23.585077 <46>[ 23.524793] systemd-journald[232]: /var/log/journal/44a983756b26438995e691b947c527e4/system.journal: Journal header limits reached or header out-of-date, rotating.
1609 08:34:23.601688 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
1610 08:34:23.618818 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
1611 08:34:23.633311 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
1612 08:34:23.639282 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
1613 08:34:23.724460 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
1614 08:34:23.742785 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
1615 08:34:23.747643 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
1616 08:34:23.803541 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
1617 08:34:23.820906 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
1618 08:34:23.892274 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
1619 08:34:23.902723 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
1620 08:34:23.939001 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
1621 08:34:23.952405 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
1622 08:34:23.965545 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
1623 08:34:23.981989 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
1624 08:34:24.028225 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
1625 08:34:24.037637 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
1626 08:34:24.051440 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyAM…ice[0m - Serial Getty on ttyAML0.
1627 08:34:24.063654 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
1628 08:34:24.078291 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
1629 08:34:24.090402 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
1630 08:34:24.101196 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
1631 08:34:24.112671 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
1632 08:34:24.127508 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
1633 08:34:24.160531 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
1634 08:34:24.220941 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
1635 08:34:24.316980
1636 08:34:24.317534 Debian GNU/Linux 12 debian-bookworm-arm64 ttyAML0
1637 08:34:24.317970
1638 08:34:24.323080 debian-bookworm-arm64 login: root (automatic login)
1639 08:34:24.323593
1640 08:34:24.477080 Linux debian-bookworm-arm64 6.12.0-rc6 #1 SMP PREEMPT Mon Nov 4 08:13:19 UTC 2024 aarch64
1641 08:34:24.477659
1642 08:34:24.482691 The programs included with the Debian GNU/Linux system are free software;
1643 08:34:24.488220 the exact distribution terms for each program are described in the
1644 08:34:24.493653 individual files in /usr/share/doc/*/copyright.
1645 08:34:24.494173
1646 08:34:24.499284 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
1647 08:34:24.501518 permitted by applicable law.
1648 08:34:25.194161 Matched prompt #10: / #
1650 08:34:25.195686 Setting prompt string to ['/ #']
1651 08:34:25.196310 end: 2.4.4.1 login-action (duration 00:00:26) [common]
1653 08:34:25.197739 end: 2.4.4 auto-login-action (duration 00:00:26) [common]
1654 08:34:25.198304 start: 2.4.5 expect-shell-connection (timeout 00:03:16) [common]
1655 08:34:25.198758 Setting prompt string to ['/ #']
1656 08:34:25.199180 Forcing a shell prompt, looking for ['/ #']
1658 08:34:25.250272 / #
1659 08:34:25.251042 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
1660 08:34:25.251556 Waiting using forced prompt support (timeout 00:02:30)
1661 08:34:25.255131
1662 08:34:25.256043 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
1663 08:34:25.256637 start: 2.4.6 export-device-env (timeout 00:03:16) [common]
1664 08:34:25.257130 Sending with 10 millisecond of delay
1666 08:34:30.247666 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/933468/extract-nfsrootfs-ycl9qdu0'
1667 08:34:30.258834 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/933468/extract-nfsrootfs-ycl9qdu0'
1668 08:34:30.259765 Sending with 10 millisecond of delay
1670 08:34:32.359221 / # export NFS_SERVER_IP='192.168.6.2'
1671 08:34:32.369890 export NFS_SERVER_IP='192.168.6.2'
1672 08:34:32.370504 end: 2.4.6 export-device-env (duration 00:00:07) [common]
1673 08:34:32.370833 end: 2.4 uboot-commands (duration 00:01:51) [common]
1674 08:34:32.371140 end: 2 uboot-action (duration 00:01:51) [common]
1675 08:34:32.371428 start: 3 lava-test-retry (timeout 00:06:48) [common]
1676 08:34:32.371729 start: 3.1 lava-test-shell (timeout 00:06:48) [common]
1677 08:34:32.372010 Using namespace: common
1679 08:34:32.472750 / # #
1680 08:34:32.473275 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
1681 08:34:32.477134 #
1682 08:34:32.477668 Using /lava-933468
1684 08:34:32.578406 / # export SHELL=/bin/bash
1685 08:34:32.582903 export SHELL=/bin/bash
1687 08:34:32.683943 / # . /lava-933468/environment
1688 08:34:32.687522 . /lava-933468/environment
1690 08:34:32.793279 / # /lava-933468/bin/lava-test-runner /lava-933468/0
1691 08:34:32.794045 Test shell timeout: 10s (minimum of the action and connection timeout)
1692 08:34:32.797120 /lava-933468/bin/lava-test-runner /lava-933468/0
1693 08:34:33.015282 + export TESTRUN_ID=0_timesync-off
1694 08:34:33.022067 + TESTRUN_ID=0_timesync-off
1695 08:34:33.022612 + cd /lava-933468/0/tests/0_timesync-off
1696 08:34:33.023028 ++ cat uuid
1697 08:34:33.027456 + UUID=933468_1.6.2.4.1
1698 08:34:33.027951 + set +x
1699 08:34:33.029562 <LAVA_SIGNAL_STARTRUN 0_timesync-off 933468_1.6.2.4.1>
1700 08:34:33.030265 Received signal: <STARTRUN> 0_timesync-off 933468_1.6.2.4.1
1701 08:34:33.030697 Starting test lava.0_timesync-off (933468_1.6.2.4.1)
1702 08:34:33.031225 Skipping test definition patterns.
1703 08:34:33.034449 + systemctl stop systemd-timesyncd
1704 08:34:33.078847 + set +x
1705 08:34:33.079471 <LAVA_SIGNAL_ENDRUN 0_timesync-off 933468_1.6.2.4.1>
1706 08:34:33.080152 Received signal: <ENDRUN> 0_timesync-off 933468_1.6.2.4.1
1707 08:34:33.080652 Ending use of test pattern.
1708 08:34:33.081060 Ending test lava.0_timesync-off (933468_1.6.2.4.1), duration 0.05
1710 08:34:33.175172 + export TESTRUN_ID=1_kselftest-alsa
1711 08:34:33.182543 + TESTRUN_ID=1_kselftest-alsa
1712 08:34:33.183067 + cd /lava-933468/0/tests/1_kselftest-alsa
1713 08:34:33.183491 ++ cat uuid
1714 08:34:33.196672 + UUID=933468_1.6.2.4.5
1715 08:34:33.197212 + set +x
1716 08:34:33.202216 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 933468_1.6.2.4.5>
1717 08:34:33.202742 + cd ./automated/linux/kselftest/
1718 08:34:33.203439 Received signal: <STARTRUN> 1_kselftest-alsa 933468_1.6.2.4.5
1719 08:34:33.203890 Starting test lava.1_kselftest-alsa (933468_1.6.2.4.5)
1720 08:34:33.204578 Skipping test definition patterns.
1721 08:34:33.229106 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/tip/master/v6.12-rc6-328-gf46306bca74bb/arm64/defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b meson-g12b-a311d-libretech-cc -g tip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1722 08:34:33.268220 INFO: install_deps skipped
1723 08:34:33.387354 --2024-11-04 08:34:33-- http://storage.kernelci.org/tip/master/v6.12-rc6-328-gf46306bca74bb/arm64/defconfig/gcc-12/kselftest.tar.xz
1724 08:34:33.418969 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1725 08:34:33.556176 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1726 08:34:33.692431 HTTP request sent, awaiting response... 200 OK
1727 08:34:33.693011 Length: 6925992 (6.6M) [application/octet-stream]
1728 08:34:33.697966 Saving to: 'kselftest_armhf.tar.gz'
1729 08:34:33.698459
1730 08:34:34.822310
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 0%[ ] 47.54K 176KB/s
kselftest_armhf.tar 3%[ ] 216.29K 400KB/s
kselftest_armhf.tar 13%[=> ] 893.67K 1.08MB/s
kselftest_armhf.tar 53%[=========> ] 3.51M 3.25MB/s
kselftest_armhf.tar 100%[===================>] 6.60M 5.87MB/s in 1.1s
1731 08:34:34.822750
1732 08:34:34.914748 2024-11-04 08:34:34 (5.87 MB/s) - 'kselftest_armhf.tar.gz' saved [6925992/6925992]
1733 08:34:34.915250
1734 08:34:44.242308 skiplist:
1735 08:34:44.242999 ========================================
1736 08:34:44.246967 ========================================
1737 08:34:44.290704 alsa:mixer-test
1738 08:34:44.291494 alsa:pcm-test
1739 08:34:44.292631 alsa:test-pcmtest-driver
1740 08:34:44.293836 alsa:utimer-test
1741 08:34:44.306589 ============== Tests to run ===============
1742 08:34:44.307209 alsa:mixer-test
1743 08:34:44.312055 alsa:pcm-test
1744 08:34:44.312590 alsa:test-pcmtest-driver
1745 08:34:44.313034 alsa:utimer-test
1746 08:34:44.319112 ===========End Tests to run ===============
1747 08:34:44.319544 shardfile-alsa pass
1748 08:34:44.444069 <12>[ 44.399671] kselftest: Running tests in alsa
1749 08:34:44.453428 TAP version 13
1750 08:34:44.464770 1..4
1751 08:34:44.483498 # timeout set to 45
1752 08:34:44.484090 # selftests: alsa: mixer-test
1753 08:34:44.698780 # TAP version 13
1754 08:34:44.699408 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
1755 08:34:44.704108 # 1..427
1756 08:34:44.704638 # ok 1 get_value.LCALTA.60
1757 08:34:44.704979 # # LCALTA.60 TDMOUT_A SRC SEL
1758 08:34:44.709606 # ok 2 name.LCALTA.60
1759 08:34:44.710166 # ok 3 write_default.LCALTA.60
1760 08:34:44.713011 # ok 4 write_valid.LCALTA.60
1761 08:34:44.720127 # ok 5 write_invalid.LCALTA.60
1762 08:34:44.720495 # ok 6 event_missing.LCALTA.60
1763 08:34:44.724051 # ok 7 event_spurious.LCALTA.60
1764 08:34:44.724348 # ok 8 get_value.LCALTA.59
1765 08:34:44.729724 # # LCALTA.59 TDMOUT_B SRC SEL
1766 08:34:44.729969 # ok 9 name.LCALTA.59
1767 08:34:44.735130 # ok 10 write_default.LCALTA.59
1768 08:34:44.735370 # ok 11 write_valid.LCALTA.59
1769 08:34:44.740611 # ok 12 write_invalid.LCALTA.59
1770 08:34:44.740983 # ok 13 event_missing.LCALTA.59
1771 08:34:44.746244 # ok 14 event_spurious.LCALTA.59
1772 08:34:44.746584 # ok 15 get_value.LCALTA.58
1773 08:34:44.752638 # # LCALTA.58 TDMOUT_C SRC SEL
1774 08:34:44.752991 # ok 16 name.LCALTA.58
1775 08:34:44.753200 # ok 17 write_default.LCALTA.58
1776 08:34:44.757308 # ok 18 write_valid.LCALTA.58
1777 08:34:44.757673 # ok 19 write_invalid.LCALTA.58
1778 08:34:44.762870 # ok 20 event_missing.LCALTA.58
1779 08:34:44.763172 # ok 21 event_spurious.LCALTA.58
1780 08:34:44.768392 # ok 22 get_value.LCALTA.57
1781 08:34:44.768707 # # LCALTA.57 TDMIN_A SRC SEL
1782 08:34:44.774002 # ok 23 name.LCALTA.57
1783 08:34:44.774529 # ok 24 write_default.LCALTA.57
1784 08:34:44.779628 # ok 25 write_valid.LCALTA.57
1785 08:34:44.780183 # ok 26 write_invalid.LCALTA.57
1786 08:34:44.785224 # ok 27 event_missing.LCALTA.57
1787 08:34:44.785752 # ok 28 event_spurious.LCALTA.57
1788 08:34:44.790811 # ok 29 get_value.LCALTA.56
1789 08:34:44.791412 # # LCALTA.56 TDMIN_B SRC SEL
1790 08:34:44.796324 # ok 30 name.LCALTA.56
1791 08:34:44.796868 # ok 31 write_default.LCALTA.56
1792 08:34:44.801751 # ok 32 write_valid.LCALTA.56
1793 08:34:44.802260 # ok 33 write_invalid.LCALTA.56
1794 08:34:44.807340 # ok 34 event_missing.LCALTA.56
1795 08:34:44.807877 # ok 35 event_spurious.LCALTA.56
1796 08:34:44.812961 # ok 36 get_value.LCALTA.55
1797 08:34:44.823937 # # LCALTA.55 TDMIN_<3>[ 44.768195] fe.dai-link-5: ASoC: no backend DAIs enabled for fe.dai-link-5, possibly missing ALSA mixer-based routing or UCM profile
1798 08:34:44.824515 C SRC SEL
1799 08:34:44.829591 # ok 37 name.LCALTA.55
1800 08:34:44.830127 # ok 38 write_default.LCALTA.55
1801 08:34:44.835133 # ok 39 write_valid.LCALTA.55
1802 08:34:44.835677 # ok 40 write_invalid.LCALTA.55
1803 08:34:44.840752 # ok 41 event_missing.LCALTA.55
1804 08:34:44.841302 # ok 42 event_spurious.LCALTA.55
1805 08:34:44.846178 # ok 43 get_value.LCALTA.54
1806 08:34:44.846681 # # LCALTA.54 ACODEC Left DAC Sel
1807 08:34:44.851824 # ok 44 name.LCALTA.54
1808 08:34:44.852393 # ok 45 write_default.LCALTA.54
1809 08:34:44.857299 # ok 46 write_valid.LCALTA.54
1810 08:34:44.857823 # ok 47 write_invalid.LCALTA.54
1811 08:34:44.862749 # ok 48 event_missing.LCALTA.54
1812 08:34:44.863283 # ok 49 event_spurious.LCALTA.54
1813 08:34:44.868241 # ok 50 get_value.LCALTA.53
1814 08:34:44.868588 # # LCALTA.53 ACODEC Right DAC Sel
1815 08:34:44.873880 # ok 51 name.LCALTA.53
1816 08:34:44.874439 # ok 52 write_default.LCALTA.53
1817 08:34:44.879410 # ok 53 write_valid.LCALTA.53
1818 08:34:44.880008 # ok 54 write_invalid.LCALTA.53
1819 08:34:44.884981 # ok 55 event_missing.LCALTA.53
1820 08:34:44.885519 # ok 56 event_spurious.LCALTA.53
1821 08:34:44.890438 # ok 57 get_value.LCALTA.52
1822 08:34:44.890986 # # LCALTA.52 TOACODEC OUT EN Switch
1823 08:34:44.896173 # ok 58 name.LCALTA.52
1824 08:34:44.896799 # ok 59 write_default.LCALTA.52
1825 08:34:44.901704 # ok 60 write_valid.LCALTA.52
1826 08:34:44.902288 # ok 61 write_invalid.LCALTA.52
1827 08:34:44.907249 # ok 62 event_missing.LCALTA.52
1828 08:34:44.907858 # ok 63 event_spurious.LCALTA.52
1829 08:34:44.912859 # ok 64 get_value.LCALTA.51
1830 08:34:44.913288 # # LCALTA.51 TOACODEC SRC
1831 08:34:44.913502 # ok 65 name.LCALTA.51
1832 08:34:44.918594 # ok 66 write_default.LCALTA.51
1833 08:34:44.919776 # ok 67 write_valid.LCALTA.51
1834 08:34:44.924020 # ok 68 write_invalid.LCALTA.51
1835 08:34:44.924637 # ok 69 event_missing.LCALTA.51
1836 08:34:44.929380 # ok 70 event_spurious.LCALTA.51
1837 08:34:44.929785 # ok 71 get_value.LCALTA.50
1838 08:34:44.935099 # # LCALTA.50 TOHDMITX SPDIF SRC
1839 08:34:44.935468 # ok 72 name.LCALTA.50
1840 08:34:44.940449 # ok 73 write_default.LCALTA.50
1841 08:34:44.940811 # ok 74 write_valid.LCALTA.50
1842 08:34:44.946059 # ok 75 write_invalid.LCALTA.50
1843 08:34:44.946422 # ok 76 event_missing.LCALTA.50
1844 08:34:44.951607 # ok 77 event_spurious.LCALTA.50
1845 08:34:44.952005 # ok 78 get_value.LCALTA.49
1846 08:34:44.957210 # # LCALTA.49 TOHDMITX Switch
1847 08:34:44.957581 # ok 79 name.LCALTA.49
1848 08:34:44.962876 # ok 80 write_default.LCALTA.49
1849 08:34:44.963274 # ok 81 write_valid.LCALTA.49
1850 08:34:44.968273 # ok 82 write_invalid.LCALTA.49
1851 08:34:44.968649 # ok 83 event_missing.LCALTA.49
1852 08:34:44.973744 # ok 84 event_spurious.LCALTA.49
1853 08:34:44.974101 # ok 85 get_value.LCALTA.48
1854 08:34:44.979389 # # LCALTA.48 TOHDMITX I2S SRC
1855 08:34:44.979796 # ok 86 name.LCALTA.48
1856 08:34:44.984837 # ok 87 write_default.LCALTA.48
1857 08:34:44.985195 # ok 88 write_valid.LCALTA.48
1858 08:34:44.990298 # ok 89 write_invalid.LCALTA.48
1859 08:34:44.990696 # ok 90 event_missing.LCALTA.48
1860 08:34:44.995969 # ok 91 event_spurious.LCALTA.48
1861 08:34:44.996393 # ok 92 get_value.LCALTA.47
1862 08:34:45.001464 # # LCALTA.47 TODDR_C SRC SEL
1863 08:34:45.001869 # ok 93 name.LCALTA.47
1864 08:34:45.007050 # ok 94 write_default.LCALTA.47
1865 08:34:45.007447 # ok 95 write_valid.LCALTA.47
1866 08:34:45.012573 # ok 96 write_invalid.LCALTA.47
1867 08:34:45.012953 # ok 97 event_missing.LCALTA.47
1868 08:34:45.018292 # ok 98 event_spurious.LCALTA.47
1869 08:34:45.018895 # ok 99 get_value.LCALTA.46
1870 08:34:45.019305 # # LCALTA.46 TODDR_B SRC SEL
1871 08:34:45.023738 # ok 100 name.LCALTA.46
1872 08:34:45.024174 # ok 101 write_default.LCALTA.46
1873 08:34:45.029474 # ok 102 write_valid.LCALTA.46
1874 08:34:45.029956 # ok 103 write_invalid.LCALTA.46
1875 08:34:45.034913 # ok 104 event_missing.LCALTA.46
1876 08:34:45.040392 # ok 105 event_spurious.LCALTA.46
1877 08:34:45.040807 # ok 106 get_value.LCALTA.45
1878 08:34:45.041066 # # LCALTA.45 TODDR_A SRC SEL
1879 08:34:45.046060 # ok 107 name.LCALTA.45
1880 08:34:45.046482 # ok 108 write_default.LCALTA.45
1881 08:34:45.051450 # ok 109 write_valid.LCALTA.45
1882 08:34:45.051880 # ok 110 write_invalid.LCALTA.45
1883 08:34:45.057121 # ok 111 event_missing.LCALTA.45
1884 08:34:45.062544 # ok 112 event_spurious.LCALTA.45
1885 08:34:45.063006 # ok 113 get_value.LCALTA.44
1886 08:34:45.068252 # # LCALTA.44 FRDDR_C SINK 3 SEL
1887 08:34:45.068760 # ok 114 name.LCALTA.44
1888 08:34:45.069028 # ok 115 write_default.LCALTA.44
1889 08:34:45.073850 # ok 116 write_valid.LCALTA.44
1890 08:34:45.074674 # ok 117 write_invalid.LCALTA.44
1891 08:34:45.079315 # ok 118 event_missing.LCALTA.44
1892 08:34:45.084825 # ok 119 event_spurious.LCALTA.44
1893 08:34:45.085257 # ok 120 get_value.LCALTA.43
1894 08:34:45.090327 # # LCALTA.43 FRDDR_C SINK 2 SEL
1895 08:34:45.090782 # ok 121 name.LCALTA.43
1896 08:34:45.091432 # ok 122 write_default.LCALTA.43
1897 08:34:45.095805 # ok 123 write_valid.LCALTA.43
1898 08:34:45.096182 # ok 124 write_invalid.LCALTA.43
1899 08:34:45.101285 # ok 125 event_missing.LCALTA.43
1900 08:34:45.106743 # ok 126 event_spurious.LCALTA.43
1901 08:34:45.107136 # ok 127 get_value.LCALTA.42
1902 08:34:45.112424 # # LCALTA.42 FRDDR_C SINK 1 SEL
1903 08:34:45.112798 # ok 128 name.LCALTA.42
1904 08:34:45.113030 # ok 129 write_default.LCALTA.42
1905 08:34:45.118094 # ok 130 write_valid.LCALTA.42
1906 08:34:45.123589 # ok 131 write_invalid.LCALTA.42
1907 08:34:45.124076 # ok 132 event_missing.LCALTA.42
1908 08:34:45.129140 # ok 133 event_spurious.LCALTA.42
1909 08:34:45.129562 # ok 134 get_value.LCALTA.41
1910 08:34:45.134867 # # LCALTA.41 FRDDR_C SRC 3 EN Switch
1911 08:34:45.135289 # ok 135 name.LCALTA.41
1912 08:34:45.140279 # ok 136 write_default.LCALTA.41
1913 08:34:45.140690 # ok 137 write_valid.LCALTA.41
1914 08:34:45.145836 # ok 138 write_invalid.LCALTA.41
1915 08:34:45.146271 # ok 139 event_missing.LCALTA.41
1916 08:34:45.151629 # ok 140 event_spurious.LCALTA.41
1917 08:34:45.152192 # ok 141 get_value.LCALTA.40
1918 08:34:45.156940 # # LCALTA.40 FRDDR_C SRC 2 EN Switch
1919 08:34:45.157389 # ok 142 name.LCALTA.40
1920 08:34:45.162426 # ok 143 write_default.LCALTA.40
1921 08:34:45.162835 # ok 144 write_valid.LCALTA.40
1922 08:34:45.168793 # ok 145 write_invalid.LCALTA.40
1923 08:34:45.169227 # ok 146 event_missing.LCALTA.40
1924 08:34:45.173735 # ok 147 event_spurious.LCALTA.40
1925 08:34:45.174178 # ok 148 get_value.LCALTA.39
1926 08:34:45.179125 # # LCALTA.39 FRDDR_C SRC 1 EN Switch
1927 08:34:45.179593 # ok 149 name.LCALTA.39
1928 08:34:45.184591 # ok 150 write_default.LCALTA.39
1929 08:34:45.185042 # ok 151 write_valid.LCALTA.39
1930 08:34:45.190211 # ok 152 write_invalid.LCALTA.39
1931 08:34:45.190665 # ok 153 event_missing.LCALTA.39
1932 08:34:45.195811 # ok 154 event_spurious.LCALTA.39
1933 08:34:45.196281 # ok 155 get_value.LCALTA.38
1934 08:34:45.201288 # # LCALTA.38 FRDDR_B SINK 3 SEL
1935 08:34:45.201897 # ok 156 name.LCALTA.38
1936 08:34:45.206920 # ok 157 write_default.LCALTA.38
1937 08:34:45.207366 # ok 158 write_valid.LCALTA.38
1938 08:34:45.212362 # ok 159 write_invalid.LCALTA.38
1939 08:34:45.212784 # ok 160 event_missing.LCALTA.38
1940 08:34:45.217868 # ok 161 event_spurious.LCALTA.38
1941 08:34:45.218288 # ok 162 get_value.LCALTA.37
1942 08:34:45.223485 # # LCALTA.37 FRDDR_B SINK 2 SEL
1943 08:34:45.224143 # ok 163 name.LCALTA.37
1944 08:34:45.228954 # ok 164 write_default.LCALTA.37
1945 08:34:45.229383 # ok 165 write_valid.LCALTA.37
1946 08:34:45.234582 # ok 166 write_invalid.LCALTA.37
1947 08:34:45.235185 # ok 167 event_missing.LCALTA.37
1948 08:34:45.240081 # ok 168 event_spurious.LCALTA.37
1949 08:34:45.240487 # ok 169 get_value.LCALTA.36
1950 08:34:45.245578 # # LCALTA.36 FRDDR_B SINK 1 SEL
1951 08:34:45.246005 # ok 170 name.LCALTA.36
1952 08:34:45.251178 # ok 171 write_default.LCALTA.36
1953 08:34:45.251609 # ok 172 write_valid.LCALTA.36
1954 08:34:45.256759 # ok 173 write_invalid.LCALTA.36
1955 08:34:45.257177 # ok 174 event_missing.LCALTA.36
1956 08:34:45.262435 # ok 175 event_spurious.LCALTA.36
1957 08:34:45.262867 # ok 176 get_value.LCALTA.35
1958 08:34:45.267823 # # LCALTA.35 FRDDR_B SRC 3 EN Switch
1959 08:34:45.268416 # ok 177 name.LCALTA.35
1960 08:34:45.273367 # ok 178 write_default.LCALTA.35
1961 08:34:45.278961 # ok 179 write_valid.LCALTA.35
1962 08:34:45.279367 # ok 180 write_invalid.LCALTA.35
1963 08:34:45.284388 # ok 181 event_missing.LCALTA.35
1964 08:34:45.284784 # ok 182 event_spurious.LCALTA.35
1965 08:34:45.289857 # ok 183 get_value.LCALTA.34
1966 08:34:45.290398 # # LCALTA.34 FRDDR_B SRC 2 EN Switch
1967 08:34:45.297245 # ok 184 name.LCALTA.34
1968 08:34:45.297759 # ok 185 write_default.LCALTA.34
1969 08:34:45.301117 # ok 186 write_valid.LCALTA.34
1970 08:34:45.301516 # ok 187 write_invalid.LCALTA.34
1971 08:34:45.306646 # ok 188 event_missing.LCALTA.34
1972 08:34:45.307086 # ok 189 event_spurious.LCALTA.34
1973 08:34:45.312218 # ok 190 get_value.LCALTA.33
1974 08:34:45.312676 # # LCALTA.33 FRDDR_B SRC 1 EN Switch
1975 08:34:45.317796 # ok 191 name.LCALTA.33
1976 08:34:45.318226 # ok 192 write_default.LCALTA.33
1977 08:34:45.323321 # ok 193 write_valid.LCALTA.33
1978 08:34:45.323774 # ok 194 write_invalid.LCALTA.33
1979 08:34:45.328805 # ok 195 event_missing.LCALTA.33
1980 08:34:45.329197 # ok 196 event_spurious.LCALTA.33
1981 08:34:45.334393 # ok 197 get_value.LCALTA.32
1982 08:34:45.335152 # # LCALTA.32 FRDDR_A SINK 3 SEL
1983 08:34:45.339953 # ok 198 name.LCALTA.32
1984 08:34:45.340424 # ok 199 write_default.LCALTA.32
1985 08:34:45.345469 # ok 200 write_valid.LCALTA.32
1986 08:34:45.345897 # ok 201 write_invalid.LCALTA.32
1987 08:34:45.351006 # ok 202 event_missing.LCALTA.32
1988 08:34:45.351578 # ok 203 event_spurious.LCALTA.32
1989 08:34:45.356537 # ok 204 get_value.LCALTA.31
1990 08:34:45.356977 # # LCALTA.31 FRDDR_A SINK 2 SEL
1991 08:34:45.362039 # ok 205 name.LCALTA.31
1992 08:34:45.362477 # ok 206 write_default.LCALTA.31
1993 08:34:45.367524 # ok 207 write_valid.LCALTA.31
1994 08:34:45.367924 # ok 208 write_invalid.LCALTA.31
1995 08:34:45.373196 # ok 209 event_missing.LCALTA.31
1996 08:34:45.373605 # ok 210 event_spurious.LCALTA.31
1997 08:34:45.378883 # ok 211 get_value.LCALTA.30
1998 08:34:45.379324 # # LCALTA.30 FRDDR_A SINK 1 SEL
1999 08:34:45.384300 # ok 212 name.LCALTA.30
2000 08:34:45.384696 # ok 213 write_default.LCALTA.30
2001 08:34:45.389876 # ok 214 write_valid.LCALTA.30
2002 08:34:45.390272 # ok 215 write_invalid.LCALTA.30
2003 08:34:45.395350 # ok 216 event_missing.LCALTA.30
2004 08:34:45.395724 # ok 217 event_spurious.LCALTA.30
2005 08:34:45.400958 # ok 218 get_value.LCALTA.29
2006 08:34:45.406501 # # LCALTA.29 FRDDR_A SRC 3 EN Switch
2007 08:34:45.406902 # ok 219 name.LCALTA.29
2008 08:34:45.407132 # ok 220 write_default.LCALTA.29
2009 08:34:45.411957 # ok 221 write_valid.LCALTA.29
2010 08:34:45.412366 # ok 222 write_invalid.LCALTA.29
2011 08:34:45.417537 # ok 223 event_missing.LCALTA.29
2012 08:34:45.423022 # ok 224 event_spurious.LCALTA.29
2013 08:34:45.423436 # ok 225 get_value.LCALTA.28
2014 08:34:45.428425 # # LCALTA.28 FRDDR_A SRC 2 EN Switch
2015 08:34:45.428834 # ok 226 name.LCALTA.28
2016 08:34:45.434086 # ok 227 write_default.LCALTA.28
2017 08:34:45.434468 # ok 228 write_valid.LCALTA.28
2018 08:34:45.439750 # ok 229 write_invalid.LCALTA.28
2019 08:34:45.440192 # ok 230 event_missing.LCALTA.28
2020 08:34:45.445142 # ok 231 event_spurious.LCALTA.28
2021 08:34:45.445527 # ok 232 get_value.LCALTA.27
2022 08:34:45.450738 # # LCALTA.27 FRDDR_A SRC 1 EN Switch
2023 08:34:45.451102 # ok 233 name.LCALTA.27
2024 08:34:45.456271 # ok 234 write_default.LCALTA.27
2025 08:34:45.456620 # ok 235 write_valid.LCALTA.27
2026 08:34:45.461836 # ok 236 write_invalid.LCALTA.27
2027 08:34:45.462182 # ok 237 event_missing.LCALTA.27
2028 08:34:45.467289 # ok 238 event_spurious.LCALTA.27
2029 08:34:45.467637 # ok 239 get_value.LCALTA.26
2030 08:34:45.472876 # # LCALTA.26 ELD
2031 08:34:45.473270 # ok 240 name.LCALTA.26
2032 08:34:45.473512 # # ELD is not writeable
2033 08:34:45.478481 # ok 241 # SKIP write_default.LCALTA.26
2034 08:34:45.478830 # # ELD is not writeable
2035 08:34:45.484074 # ok 242 # SKIP write_valid.LCALTA.26
2036 08:34:45.484449 # # ELD is not writeable
2037 08:34:45.489492 # ok 243 # SKIP write_invalid.LCALTA.26
2038 08:34:45.495092 # ok 244 event_missing.LCALTA.26
2039 08:34:45.495453 # ok 245 event_spurious.LCALTA.26
2040 08:34:45.500773 # ok 246 get_value.LCALTA.25
2041 08:34:45.501171 # # LCALTA.25 IEC958 Playback Default
2042 08:34:45.506299 # ok 247 name.LCALTA.25
2043 08:34:45.506660 # ok 248 write_default.LCALTA.25
2044 08:34:45.511774 # ok 249 # SKIP write_valid.LCALTA.25
2045 08:34:45.512141 # ok 250 # SKIP write_invalid.LCALTA.25
2046 08:34:45.517275 # ok 251 event_missing.LCALTA.25
2047 08:34:45.517663 # ok 252 event_spurious.LCALTA.25
2048 08:34:45.522841 # ok 253 get_value.LCALTA.24
2049 08:34:45.523224 # # LCALTA.24 IEC958 Playback Mask
2050 08:34:45.528272 # ok 254 name.LCALTA.24
2051 08:34:45.533946 # # IEC958 Playback Mask is not writeable
2052 08:34:45.534329 # ok 255 # SKIP write_default.LCALTA.24
2053 08:34:45.539460 # # IEC958 Playback Mask is not writeable
2054 08:34:45.539825 # ok 256 # SKIP write_valid.LCALTA.24
2055 08:34:45.545114 # # IEC958 Playback Mask is not writeable
2056 08:34:45.550525 # ok 257 # SKIP write_invalid.LCALTA.24
2057 08:34:45.550884 # ok 258 event_missing.LCALTA.24
2058 08:34:45.556271 # ok 259 event_spurious.LCALTA.24
2059 08:34:45.556674 # ok 260 get_value.LCALTA.23
2060 08:34:45.561790 # # LCALTA.23 Playback Channel Map
2061 08:34:45.562166 # ok 261 name.LCALTA.23
2062 08:34:45.567277 # # Playback Channel Map is not writeable
2063 08:34:45.572990 # ok 262 # SKIP write_default.LCALTA.23
2064 08:34:45.573406 # # Playback Channel Map is not writeable
2065 08:34:45.578691 # ok 263 # SKIP write_valid.LCALTA.23
2066 08:34:45.584168 # # Playback Channel Map is not writeable
2067 08:34:45.584540 # ok 264 # SKIP write_invalid.LCALTA.23
2068 08:34:45.589537 # ok 265 event_missing.LCALTA.23
2069 08:34:45.589911 # ok 266 event_spurious.LCALTA.23
2070 08:34:45.594909 # ok 267 get_value.LCALTA.22
2071 08:34:45.595276 # # LCALTA.22 TDMOUT_A Gain Enable Switch
2072 08:34:45.600522 # ok 268 name.LCALTA.22
2073 08:34:45.600888 # ok 269 write_default.LCALTA.22
2074 08:34:45.606153 # ok 270 write_valid.LCALTA.22
2075 08:34:45.606564 # ok 271 write_invalid.LCALTA.22
2076 08:34:45.611571 # ok 272 event_missing.LCALTA.22
2077 08:34:45.611965 # ok 273 event_spurious.LCALTA.22
2078 08:34:45.617463 # ok 274 get_value.LCALTA.21
2079 08:34:45.617828 # # LCALTA.21 TDMOUT_A Lane 3 Volume
2080 08:34:45.622780 # ok 275 name.LCALTA.21
2081 08:34:45.623102 # ok 276 write_default.LCALTA.21
2082 08:34:45.628591 # ok 277 write_valid.LCALTA.21
2083 08:34:45.628971 # ok 278 write_invalid.LCALTA.21
2084 08:34:45.634391 # ok 279 event_missing.LCALTA.21
2085 08:34:45.639589 # ok 280 event_spurious.LCALTA.21
2086 08:34:45.640095 # ok 281 get_value.LCALTA.20
2087 08:34:45.645107 # # LCALTA.20 TDMOUT_A Lane 2 Volume
2088 08:34:45.645808 # ok 282 name.LCALTA.20
2089 08:34:45.650646 # ok 283 write_default.LCALTA.20
2090 08:34:45.651259 # ok 284 write_valid.LCALTA.20
2091 08:34:45.656184 # ok 285 write_invalid.LCALTA.20
2092 08:34:45.656805 # ok 286 event_missing.LCALTA.20
2093 08:34:45.661694 # ok 287 event_spurious.LCALTA.20
2094 08:34:45.662210 # ok 288 get_value.LCALTA.19
2095 08:34:45.667656 # # LCALTA.19 TDMOUT_A Lane 1 Volume
2096 08:34:45.668225 # ok 289 name.LCALTA.19
2097 08:34:45.672733 # ok 290 write_default.LCALTA.19
2098 08:34:45.673243 # ok 291 write_valid.LCALTA.19
2099 08:34:45.679925 # ok 292 write_invalid.LCALTA.19
2100 08:34:45.680569 # ok 293 event_missing.LCALTA.19
2101 08:34:45.683915 # ok 294 event_spurious.LCALTA.19
2102 08:34:45.684537 # ok 295 get_value.LCALTA.18
2103 08:34:45.689393 # # LCALTA.18 TDMOUT_A Lane 0 Volume
2104 08:34:45.689981 # ok 296 name.LCALTA.18
2105 08:34:45.694923 # ok 297 write_default.LCALTA.18
2106 08:34:45.695545 # ok 298 write_valid.LCALTA.18
2107 08:34:45.700549 # ok 299 write_invalid.LCALTA.18
2108 08:34:45.701173 # ok 300 event_missing.LCALTA.18
2109 08:34:45.706036 # ok 301 event_spurious.LCALTA.18
2110 08:34:45.706606 # ok 302 get_value.LCALTA.17
2111 08:34:45.711885 # # LCALTA.17 TDMOUT_B Gain Enable Switch
2112 08:34:45.712589 # ok 303 name.LCALTA.17
2113 08:34:45.717261 # ok 304 write_default.LCALTA.17
2114 08:34:45.717912 # ok 305 write_valid.LCALTA.17
2115 08:34:45.722740 # ok 306 write_invalid.LCALTA.17
2116 08:34:45.723107 # ok 307 event_missing.LCALTA.17
2117 08:34:45.728299 # ok 308 event_spurious.LCALTA.17
2118 08:34:45.728854 # ok 309 get_value.LCALTA.16
2119 08:34:45.733788 # # LCALTA.16 TDMOUT_B Lane 3 Volume
2120 08:34:45.734366 # ok 310 name.LCALTA.16
2121 08:34:45.739310 # ok 311 write_default.LCALTA.16
2122 08:34:45.739900 # ok 312 write_valid.LCALTA.16
2123 08:34:45.744918 # ok 313 write_invalid.LCALTA.16
2124 08:34:45.750467 # ok 314 event_missing.LCALTA.16
2125 08:34:45.751091 # ok 315 event_spurious.LCALTA.16
2126 08:34:45.756018 # ok 316 get_value.LCALTA.15
2127 08:34:45.756630 # # LCALTA.15 TDMOUT_B Lane 2 Volume
2128 08:34:45.761581 # ok 317 name.LCALTA.15
2129 08:34:45.762150 # ok 318 write_default.LCALTA.15
2130 08:34:45.767041 # ok 319 write_valid.LCALTA.15
2131 08:34:45.767585 # ok 320 write_invalid.LCALTA.15
2132 08:34:45.772559 # ok 321 event_missing.LCALTA.15
2133 08:34:45.773085 # ok 322 event_spurious.LCALTA.15
2134 08:34:45.778208 # ok 323 get_value.LCALTA.14
2135 08:34:45.778782 # # LCALTA.14 TDMOUT_B Lane 1 Volume
2136 08:34:45.783672 # ok 324 name.LCALTA.14
2137 08:34:45.784285 # ok 325 write_default.LCALTA.14
2138 08:34:45.789269 # ok 326 write_valid.LCALTA.14
2139 08:34:45.789892 # ok 327 write_invalid.LCALTA.14
2140 08:34:45.794717 # ok 328 event_missing.LCALTA.14
2141 08:34:45.795314 # ok 329 event_spurious.LCALTA.14
2142 08:34:45.800356 # ok 330 get_value.LCALTA.13
2143 08:34:45.800917 # # LCALTA.13 TDMOUT_B Lane 0 Volume
2144 08:34:45.805926 # ok 331 name.LCALTA.13
2145 08:34:45.806501 # ok 332 write_default.LCALTA.13
2146 08:34:45.811423 # ok 333 write_valid.LCALTA.13
2147 08:34:45.812048 # ok 334 write_invalid.LCALTA.13
2148 08:34:45.816908 # ok 335 event_missing.LCALTA.13
2149 08:34:45.817485 # ok 336 event_spurious.LCALTA.13
2150 08:34:45.822467 # ok 337 get_value.LCALTA.12
2151 08:34:45.823016 # # LCALTA.12 TDMOUT_C Gain Enable Switch
2152 08:34:45.828081 # ok 338 name.LCALTA.12
2153 08:34:45.828650 # ok 339 write_default.LCALTA.12
2154 08:34:45.833490 # ok 340 write_valid.LCALTA.12
2155 08:34:45.834046 # ok 341 write_invalid.LCALTA.12
2156 08:34:45.839077 # ok 342 event_missing.LCALTA.12
2157 08:34:45.844681 # ok 343 event_spurious.LCALTA.12
2158 08:34:45.845247 # ok 344 get_value.LCALTA.11
2159 08:34:45.850232 # # LCALTA.11 TDMOUT_C Lane 3 Volume
2160 08:34:45.850780 # ok 345 name.LCALTA.11
2161 08:34:45.855847 # ok 346 write_default.LCALTA.11
2162 08:34:45.856429 # ok 347 write_valid.LCALTA.11
2163 08:34:45.861350 # ok 348 write_invalid.LCALTA.11
2164 08:34:45.861935 # ok 349 event_missing.LCALTA.11
2165 08:34:45.867013 # ok 350 event_spurious.LCALTA.11
2166 08:34:45.867588 # ok 351 get_value.LCALTA.10
2167 08:34:45.872333 # # LCALTA.10 TDMOUT_C Lane 2 Volume
2168 08:34:45.872887 # ok 352 name.LCALTA.10
2169 08:34:45.877950 # ok 353 write_default.LCALTA.10
2170 08:34:45.878498 # ok 354 write_valid.LCALTA.10
2171 08:34:45.883477 # ok 355 write_invalid.LCALTA.10
2172 08:34:45.884077 # ok 356 event_missing.LCALTA.10
2173 08:34:45.889113 # ok 357 event_spurious.LCALTA.10
2174 08:34:45.889702 # ok 358 get_value.LCALTA.9
2175 08:34:45.894607 # # LCALTA.9 TDMOUT_C Lane 1 Volume
2176 08:34:45.895167 # ok 359 name.LCALTA.9
2177 08:34:45.900160 # ok 360 write_default.LCALTA.9
2178 08:34:45.900751 # ok 361 write_valid.LCALTA.9
2179 08:34:45.905679 # ok 362 write_invalid.LCALTA.9
2180 08:34:45.906263 # ok 363 event_missing.LCALTA.9
2181 08:34:45.912129 # ok 364 event_spurious.LCALTA.9
2182 08:34:45.912710 # ok 365 get_value.LCALTA.8
2183 08:34:45.916801 # # LCALTA.8 TDMOUT_C Lane 0 Volume
2184 08:34:45.917384 # ok 366 name.LCALTA.8
2185 08:34:45.922419 # ok 367 write_default.LCALTA.8
2186 08:34:45.922977 # ok 368 write_valid.LCALTA.8
2187 08:34:45.927952 # ok 369 write_invalid.LCALTA.8
2188 08:34:45.928531 # ok 370 event_missing.LCALTA.8
2189 08:34:45.933455 # ok 371 event_spurious.LCALTA.8
2190 08:34:45.933995 # ok 372 get_value.LCALTA.7
2191 08:34:45.939239 # # LCALTA.7 ACODEC Unmute Ramp Switch
2192 08:34:45.940166 # ok 373 name.LCALTA.7
2193 08:34:45.944577 # ok 374 write_default.LCALTA.7
2194 08:34:45.945148 # ok 375 write_valid.LCALTA.7
2195 08:34:45.950119 # ok 376 write_invalid.LCALTA.7
2196 08:34:45.950661 # ok 377 event_missing.LCALTA.7
2197 08:34:45.955566 # ok 378 event_spurious.LCALTA.7
2198 08:34:45.956124 # ok 379 get_value.LCALTA.6
2199 08:34:45.961247 # # LCALTA.6 ACODEC Mute Ramp Switch
2200 08:34:45.961797 # ok 380 name.LCALTA.6
2201 08:34:45.966690 # ok 381 write_default.LCALTA.6
2202 08:34:45.967221 # ok 382 write_valid.LCALTA.6
2203 08:34:45.972302 # ok 383 write_invalid.LCALTA.6
2204 08:34:45.972872 # ok 384 event_missing.LCALTA.6
2205 08:34:45.977765 # ok 385 event_spurious.LCALTA.6
2206 08:34:45.978293 # ok 386 get_value.LCALTA.5
2207 08:34:45.983393 # # LCALTA.5 ACODEC Volume Ramp Switch
2208 08:34:45.983924 # ok 387 name.LCALTA.5
2209 08:34:45.988925 # ok 388 write_default.LCALTA.5
2210 08:34:45.989443 # ok 389 write_valid.LCALTA.5
2211 08:34:45.994373 # ok 390 write_invalid.LCALTA.5
2212 08:34:45.994909 # ok 391 event_missing.LCALTA.5
2213 08:34:46.000007 # ok 392 event_spurious.LCALTA.5
2214 08:34:46.000543 # ok 393 get_value.LCALTA.4
2215 08:34:46.005507 # # LCALTA.4 ACODEC Ramp Rate
2216 08:34:46.006039 # ok 394 name.LCALTA.4
2217 08:34:46.006478 # ok 395 write_default.LCALTA.4
2218 08:34:46.011073 # ok 396 write_valid.LCALTA.4
2219 08:34:46.011621 # ok 397 write_invalid.LCALTA.4
2220 08:34:46.016563 # ok 398 event_missing.LCALTA.4
2221 08:34:46.022195 # ok 399 event_spurious.LCALTA.4
2222 08:34:46.022716 # ok 400 get_value.LCALTA.3
2223 08:34:46.027684 # # LCALTA.3 ACODEC Playback Volume
2224 08:34:46.028251 # ok 401 name.LCALTA.3
2225 08:34:46.028691 # ok 402 write_default.LCALTA.3
2226 08:34:46.033269 # ok 403 write_valid.LCALTA.3
2227 08:34:46.033795 # ok 404 write_invalid.LCALTA.3
2228 08:34:46.038715 # ok 405 event_missing.LCALTA.3
2229 08:34:46.044371 # ok 406 event_spurious.LCALTA.3
2230 08:34:46.044912 # ok 407 get_value.LCALTA.2
2231 08:34:46.049982 # # LCALTA.2 ACODEC Playback Switch
2232 08:34:46.050519 # ok 408 name.LCALTA.2
2233 08:34:46.050953 # ok 409 write_default.LCALTA.2
2234 08:34:46.055484 # ok 410 write_valid.LCALTA.2
2235 08:34:46.056057 # ok 411 write_invalid.LCALTA.2
2236 08:34:46.060949 # ok 412 event_missing.LCALTA.2
2237 08:34:46.061484 # ok 413 event_spurious.LCALTA.2
2238 08:34:46.066601 # ok 414 get_value.LCALTA.1
2239 08:34:46.072104 # # LCALTA.1 ACODEC Playback Channel Mode
2240 08:34:46.072644 # ok 415 name.LCALTA.1
2241 08:34:46.073083 # ok 416 write_default.LCALTA.1
2242 08:34:46.077638 # ok 417 write_valid.LCALTA.1
2243 08:34:46.078164 # ok 418 write_invalid.LCALTA.1
2244 08:34:46.083212 # ok 419 event_missing.LCALTA.1
2245 08:34:46.088643 # ok 420 event_spurious.LCALTA.1
2246 08:34:46.089187 # ok 421 get_value.LCALTA.0
2247 08:34:46.094346 # # LCALTA.0 TOACODEC Lane Select
2248 08:34:46.094888 # ok 422 name.LCALTA.0
2249 08:34:46.095325 # ok 423 write_default.LCALTA.0
2250 08:34:46.099790 # ok 424 write_valid.LCALTA.0
2251 08:34:46.100339 # ok 425 write_invalid.LCALTA.0
2252 08:34:46.105354 # ok 426 event_missing.LCALTA.0
2253 08:34:46.105872 # ok 427 event_spurious.LCALTA.0
2254 08:34:46.110917 # # Totals: pass:416 fail:0 xfail:0 xpass:0 skip:11 error:0
2255 08:34:46.116552 ok 1 selftests: alsa: mixer-test
2256 08:34:46.117148 # timeout set to 45
2257 08:34:46.121937 # selftests: alsa: pcm-test
2258 08:34:46.122460 # TAP version 13
2259 08:34:46.127458 # # Card 0/LCALTA - LC-ALTA (LC-ALTA)
2260 08:34:46.128012 # # LCALTA.0 - fe.dai-link-0 (*)
2261 08:34:46.133159 # # LCALTA.0 - fe.dai-link-1 (*)
2262 08:34:46.133703 # # LCALTA.0 - fe.dai-link-2 (*)
2263 08:34:46.138722 # # LCALTA.0 - fe.dai-link-3 (*)
2264 08:34:46.139277 # # LCALTA.0 - fe.dai-link-4 (*)
2265 08:34:46.144216 # # LCALTA.0 - fe.dai-link-5 (*)
2266 08:34:46.144751 # 1..42
2267 08:34:46.149711 # # default.time1.LCALTA.5.0.CAPTURE - 8kHz mono large periods
2268 08:34:46.155307 # ok 1 # SKIP default.time1.LCALTA.5.0.CAPTURE
2269 08:34:46.155830 # # snd_pcm_hw_params: Invalid argument
2270 08:34:46.160821 # # default.time2.LCALTA.5.0.CAPTURE - 8kHz stereo large periods
2271 08:34:46.166406 # ok 2 # SKIP default.time2.LCALTA.5.0.CAPTURE
2272 08:34:46.171929 # # snd_pcm_hw_params: Invalid argument
2273 08:34:46.177529 # # default.time3.LCALTA.5.0.CAPTURE - 44.1kHz stereo large periods
2274 08:34:46.183006 # ok 3 # SKIP default.time3.LCALTA.5.0.CAPTURE
2275 08:34:46.183540 # # snd_pcm_hw_params: Invalid argument
2276 08:34:46.188562 # # default.time4.LCALTA.5.0.CAPTURE - 48kHz stereo small periods
2277 08:34:46.194186 # ok 4 # SKIP default.time4.LCALTA.5.0.CAPTURE
2278 08:34:46.199584 # # snd_pcm_hw_params: Invalid argument
2279 08:34:46.205215 # # default.time5.LCALTA.5.0.CAPTURE - 48kHz stereo large periods
2280 08:34:46.205773 # ok 5 # SKIP default.time5.LCALTA.5.0.CAPTURE
2281 08:34:46.210712 # # snd_pcm_hw_params: Invalid argument
2282 08:34:46.216395 # # default.time6.LCALTA.5.0.CAPTURE - 48kHz 6 channel large periods
2283 08:34:46.222015 # ok 6 # SKIP default.time6.LCALTA.5.0.CAPTURE
2284 08:34:46.227404 # # snd_pcm_hw_params: Invalid argument
2285 08:34:46.233071 # # default.time7.LCALTA.5.0.CAPTURE - 96kHz stereo large periods
2286 08:34:46.233627 # ok 7 # SKIP default.time7.LCALTA.5.0.CAPTURE
2287 08:34:46.238529 # # snd_pcm_hw_params: Invalid argument
2288 08:34:46.244068 # # default.time1.LCALTA.4.0.CAPTURE - 8kHz mono large periods
2289 08:34:46.249514 # ok 8 # SKIP default.time1.LCALTA.4.0.CAPTURE
2290 08:34:46.250033 # # snd_pcm_hw_params: Invalid argument
2291 08:34:46.255117 # # default.time2.LCALTA.4.0.CAPTURE - 8kHz stereo large periods
2292 08:34:46.260718 # ok 9 # SKIP default.time2.LCALTA.4.0.CAPTURE
2293 08:34:46.266220 # # snd_pcm_hw_params: Invalid argument
2294 08:34:46.271727 # # default.time3.LCALTA.4.0.CAPTURE - 44.1kHz stereo large periods
2295 08:34:46.277268 # ok 10 # SKIP default.time3.LCALTA.4.0.CAPTURE
2296 08:34:46.277811 # # snd_pcm_hw_params: Invalid argument
2297 08:34:46.282822 # # default.time4.LCALTA.4.0.CAPTURE - 48kHz stereo small periods
2298 08:34:46.288341 # ok 11 # SKIP default.time4.LCALTA.4.0.CAPTURE
2299 08:34:46.293905 # # snd_pcm_hw_params: Invalid argument
2300 08:34:46.299371 # # default.time5.LCALTA.4.0.CAPTURE - 48kHz stereo large periods
2301 08:34:46.304912 # ok 12 # SKIP default.time5.LCALTA.4.0.CAPTURE
2302 08:34:46.305432 # # snd_pcm_hw_params: Invalid argument
2303 08:34:46.310463 # # default.time6.LCALTA.4.0.CAPTURE - 48kHz 6 channel large periods
2304 08:34:46.316099 # ok 13 # SKIP default.time6.LCALTA.4.0.CAPTURE
2305 08:34:46.321580 # # snd_pcm_hw_params: Invalid argument
2306 08:34:46.327133 # # default.time7.LCALTA.4.0.CAPTURE - 96kHz stereo large periods
2307 08:34:46.332696 # ok 14 # SKIP default.time7.LCALTA.4.0.CAPTURE
2308 08:34:46.333214 # # snd_pcm_hw_params: Invalid argument
2309 08:34:46.338266 # # default.time1.LCALTA.3.0.CAPTURE - 8kHz mono large periods
2310 08:34:46.343777 # ok 15 # SKIP default.time1.LCALTA.3.0.CAPTURE
2311 08:34:46.349311 # # snd_pcm_hw_params: Invalid argument
2312 08:34:46.354921 # # default.time2.LCALTA.3.0.CAPTURE - 8kHz stereo large periods
2313 08:34:46.355446 # ok 16 # SKIP default.time2.LCALTA.3.0.CAPTURE
2314 08:34:46.360427 # # snd_pcm_hw_params: Invalid argument
2315 08:34:46.365958 # # default.time3.LCALTA.3.0.CAPTURE - 44.1kHz stereo large periods
2316 08:34:46.371521 # ok 17 # SKIP default.time3.LCALTA.3.0.CAPTURE
2317 08:34:46.377074 # # snd_pcm_hw_params: Invalid argument
2318 08:34:46.382671 # # default.time4.LCALTA.3.0.CAPTURE - 48kHz stereo small periods
2319 08:34:46.383192 # ok 18 # SKIP default.time4.LCALTA.3.0.CAPTURE
2320 08:34:46.388158 # # snd_pcm_hw_params: Invalid argument
2321 08:34:46.393705 # # default.time5.LCALTA.3.0.CAPTURE - 48kHz stereo large periods
2322 08:34:46.399244 # ok 19 # SKIP default.time5.LCALTA.3.0.CAPTURE
2323 08:34:46.399758 # # snd_pcm_hw_params: Invalid argument
2324 08:34:46.410262 # # default.time6.LCALTA.3.0.CAPTURE - 48kHz 6 channel large periods
2325 08:34:46.410794 # ok 20 # SKIP default.time6.LCALTA.3.0.CAPTURE
2326 08:34:46.416026 # # snd_pcm_hw_params: Invalid argument
2327 08:34:46.421420 # # default.time7.LCALTA.3.0.CAPTURE - 96kHz stereo large periods
2328 08:34:46.426960 # ok 21 # SKIP default.time7.LCALTA.3.0.CAPTURE
2329 08:34:46.427474 # # snd_pcm_hw_params: Invalid argument
2330 08:34:46.432527 # # default.time1.LCALTA.2.0.PLAYBACK - 8kHz mono large periods
2331 08:34:46.438057 # ok 22 # SKIP default.time1.LCALTA.2.0.PLAYBACK
2332 08:34:46.443687 # # snd_pcm_hw_params: Invalid argument
2333 08:34:46.449190 # # default.time2.LCALTA.2.0.PLAYBACK - 8kHz stereo large periods
2334 08:34:46.454723 # ok 23 # SKIP default.time2.LCALTA.2.0.PLAYBACK
2335 08:34:46.455238 # # snd_pcm_hw_params: Invalid argument
2336 08:34:46.460274 # # default.time3.LCALTA.2.0.PLAYBACK - 44.1kHz stereo large periods
2337 08:34:46.465917 # ok 24 # SKIP default.time3.LCALTA.2.0.PLAYBACK
2338 08:34:46.471315 # # snd_pcm_hw_params: Invalid argument
2339 08:34:46.476914 # # default.time4.LCALTA.2.0.PLAYBACK - 48kHz stereo small periods
2340 08:34:46.482408 # ok 25 # SKIP default.time4.LCALTA.2.0.PLAYBACK
2341 08:34:46.482918 # # snd_pcm_hw_params: Invalid argument
2342 08:34:46.487952 # # default.time5.LCALTA.2.0.PLAYBACK - 48kHz stereo large periods
2343 08:34:46.493498 # ok 26 # SKIP default.time5.LCALTA.2.0.PLAYBACK
2344 08:34:46.499021 # # snd_pcm_hw_params: Invalid argument
2345 08:34:46.504660 # # default.time6.LCALTA.2.0.PLAYBACK - 48kHz 6 channel large periods
2346 08:34:46.510202 # ok 27 # SKIP default.time6.LCALTA.2.0.PLAYBACK
2347 08:34:46.510722 # # snd_pcm_hw_params: Invalid argument
2348 08:34:46.515762 # # default.time7.LCALTA.2.0.PLAYBACK - 96kHz stereo large periods
2349 08:34:46.521240 # ok 28 # SKIP default.time7.LCALTA.2.0.PLAYBACK
2350 08:34:46.526941 # # snd_pcm_hw_params: Invalid argument
2351 08:34:46.532346 # # default.time1.LCALTA.1.0.PLAYBACK - 8kHz mono large periods
2352 08:34:46.537929 # ok 29 # SKIP default.time1.LCALTA.1.0.PLAYBACK
2353 08:34:46.538448 # # snd_pcm_hw_params: Invalid argument
2354 08:34:46.543457 # # default.time2.LCALTA.1.0.PLAYBACK - 8kHz stereo large periods
2355 08:34:46.548994 # ok 30 # SKIP default.time2.LCALTA.1.0.PLAYBACK
2356 08:34:46.554563 # # snd_pcm_hw_params: Invalid argument
2357 08:34:46.560096 # # default.time3.LCALTA.1.0.PLAYBACK - 44.1kHz stereo large periods
2358 08:34:46.565681 # ok 31 # SKIP default.time3.LCALTA.1.0.PLAYBACK
2359 08:34:46.566195 # # snd_pcm_hw_params: Invalid argument
2360 08:34:46.571207 # # default.time4.LCALTA.1.0.PLAYBACK - 48kHz stereo small periods
2361 08:34:46.576735 # ok 32 # SKIP default.time4.LCALTA.1.0.PLAYBACK
2362 08:34:46.582308 # # snd_pcm_hw_params: Invalid argument
2363 08:34:46.588029 # # default.time5.LCALTA.1.0.PLAYBACK - 48kHz stereo large periods
2364 08:34:46.593405 # ok 33 # SKIP default.time5.LCALTA.1.0.PLAYBACK
2365 08:34:46.593911 # # snd_pcm_hw_params: Invalid argument
2366 08:34:46.598987 # # default.time6.LCALTA.1.0.PLAYBACK - 48kHz 6 channel large periods
2367 08:34:46.604453 # ok 34 # SKIP default.time6.LCALTA.1.0.PLAYBACK
2368 08:34:46.610038 # # snd_pcm_hw_params: Invalid argument
2369 08:34:46.615651 # # default.time7.LCALTA.1.0.PLAYBACK - 96kHz stereo large periods
2370 08:34:46.621182 # ok 35 # SKIP default.time7.LCALTA.1.0.PLAYBACK
2371 08:34:46.621698 # # snd_pcm_hw_params: Invalid argument
2372 08:34:46.626736 # # default.time1.LCALTA.0.0.PLAYBACK - 8kHz mono large periods
2373 08:34:46.632270 # ok 36 # SKIP default.time1.LCALTA.0.0.PLAYBACK
2374 08:34:46.637743 # # snd_pcm_hw_params: Invalid argument
2375 08:34:46.643303 # # default.time2.LCALTA.0.0.PLAYBACK - 8kHz stereo large periods
2376 08:34:46.643814 # ok 37 # SKIP default.time2.LCALTA.0.0.PLAYBACK
2377 08:34:46.648957 # # snd_pcm_hw_params: Invalid argument
2378 08:34:46.654322 # # default.time3.LCALTA.0.0.PLAYBACK - 44.1kHz stereo large periods
2379 08:34:46.659939 # ok 38 # SKIP default.time3.LCALTA.0.0.PLAYBACK
2380 08:34:46.665457 # # snd_pcm_hw_params: Invalid argument
2381 08:34:46.670975 # # default.time4.LCALTA.0.0.PLAYBACK - 48kHz stereo small periods
2382 08:34:46.671485 # ok 39 # SKIP default.time4.LCALTA.0.0.PLAYBACK
2383 08:34:46.676552 # # snd_pcm_hw_params: Invalid argument
2384 08:34:46.682092 # # default.time5.LCALTA.0.0.PLAYBACK - 48kHz stereo large periods
2385 08:34:46.687716 # ok 40 # SKIP default.time5.LCALTA.0.0.PLAYBACK
2386 08:34:46.693193 # # snd_pcm_hw_params: Invalid argument
2387 08:34:46.698768 # # default.time6.LCALTA.0.0.PLAYBACK - 48kHz 6 channel large periods
2388 08:34:46.699286 # ok 41 # SKIP default.time6.LCALTA.0.0.PLAYBACK
2389 08:34:46.704359 # # snd_pcm_hw_params: Invalid argument
2390 08:34:46.709917 # # default.time7.LCALTA.0.0.PLAYBACK - 96kHz stereo large periods
2391 08:34:46.715408 # ok 42 # SKIP default.time7.LCALTA.0.0.PLAYBACK
2392 08:34:46.720966 # # snd_pcm_hw_params: Invalid argument
2393 08:34:46.726471 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:42 error:0
2394 08:34:46.727004 ok 2 selftests: alsa: pcm-test
2395 08:34:46.727473 # timeout set to 45
2396 08:34:46.732093 # selftests: alsa: test-pcmtest-driver
2397 08:34:46.732661 # TAP version 13
2398 08:34:46.733122 # 1..5
2399 08:34:46.737663 # # Starting 5 tests from 1 test cases.
2400 08:34:46.743191 # # RUN pcmtest.playback ...
2401 08:34:46.748779 # # SKIP Can't read patterns. Probably, module isn't loaded
2402 08:34:46.749362 # # OK pcmtest.playback
2403 08:34:46.759766 # ok 1 pcmtest.playback # SKIP Can't read patterns. Probably, module isn't loaded
2404 08:34:46.760408 # # RUN pcmtest.capture ...
2405 08:34:46.765373 # # SKIP Can't read patterns. Probably, module isn't loaded
2406 08:34:46.770961 # # OK pcmtest.capture
2407 08:34:46.776409 # ok 2 pcmtest.capture # SKIP Can't read patterns. Probably, module isn't loaded
2408 08:34:46.781973 # # RUN pcmtest.ni_capture ...
2409 08:34:46.787495 # # SKIP Can't read patterns. Probably, module isn't loaded
2410 08:34:46.793111 # # OK pcmtest.ni_capture
2411 08:34:46.798588 # ok 3 pcmtest.ni_capture # SKIP Can't read patterns. Probably, module isn't loaded
2412 08:34:46.804131 # # RUN pcmtest.ni_playback ...
2413 08:34:46.809750 # # SKIP Can't read patterns. Probably, module isn't loaded
2414 08:34:46.810317 # # OK pcmtest.ni_playback
2415 08:34:46.820822 # ok 4 pcmtest.ni_playback # SKIP Can't read patterns. Probably, module isn't loaded
2416 08:34:46.821397 # # RUN pcmtest.reset_ioctl ...
2417 08:34:46.832005 # # SKIP Can't read patterns. Probably, module isn't loaded
2418 08:34:46.832588 # # OK pcmtest.reset_ioctl
2419 08:34:46.837445 # ok 5 pcmtest.reset_ioctl # SKIP Can't read patterns. Probably, module isn't loaded
2420 08:34:46.842963 # # PASSED: 5 / 5 tests passed.
2421 08:34:46.848527 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
2422 08:34:46.854073 ok 3 selftests: alsa: test-pcmtest-driver
2423 08:34:46.854640 # timeout set to 45
2424 08:34:46.855127 # selftests: alsa: utimer-test
2425 08:34:46.859605 # TAP version 13
2426 08:34:46.860202 # 1..2
2427 08:34:46.860686 # # Starting 2 tests from 2 test cases.
2428 08:34:46.865134 # # RUN global.wrong_timers_test ...
2429 08:34:46.870755 # # OK global.wrong_timers_test
2430 08:34:46.871298 # ok 1 global.wrong_timers_test
2431 08:34:46.876281 # # RUN timer_f.utimer ...
2432 08:34:46.887356 # # utimer-test.c:55:utimer:Expected ioctl(timer_dev_fd, SNDRV_TIMER_IOCTL_CREATE, self->utimer_info) (-1) == 0 (0)
2433 08:34:46.892933 # # utimer: Test terminated by assertion
2434 08:34:46.893451 # # FAIL timer_f.utimer
2435 08:34:46.893906 # not ok 2 timer_f.utimer
2436 08:34:46.898379 # # FAILED: 1 / 2 tests passed.
2437 08:34:46.903939 # # Totals: pass:1 fail:1 xfail:0 xpass:0 skip:0 error:0
2438 08:34:46.908028 not ok 4 selftests: alsa: utimer-test # exit=1
2439 08:34:47.411293 alsa_mixer-test_get_value_LCALTA_60 pass
2440 08:34:47.416676 alsa_mixer-test_name_LCALTA_60 pass
2441 08:34:47.417186 alsa_mixer-test_write_default_LCALTA_60 pass
2442 08:34:47.422212 alsa_mixer-test_write_valid_LCALTA_60 pass
2443 08:34:47.427716 alsa_mixer-test_write_invalid_LCALTA_60 pass
2444 08:34:47.433286 alsa_mixer-test_event_missing_LCALTA_60 pass
2445 08:34:47.433784 alsa_mixer-test_event_spurious_LCALTA_60 pass
2446 08:34:47.438934 alsa_mixer-test_get_value_LCALTA_59 pass
2447 08:34:47.444345 alsa_mixer-test_name_LCALTA_59 pass
2448 08:34:47.444837 alsa_mixer-test_write_default_LCALTA_59 pass
2449 08:34:47.449927 alsa_mixer-test_write_valid_LCALTA_59 pass
2450 08:34:47.455430 alsa_mixer-test_write_invalid_LCALTA_59 pass
2451 08:34:47.455921 alsa_mixer-test_event_missing_LCALTA_59 pass
2452 08:34:47.461009 alsa_mixer-test_event_spurious_LCALTA_59 pass
2453 08:34:47.466549 alsa_mixer-test_get_value_LCALTA_58 pass
2454 08:34:47.467043 alsa_mixer-test_name_LCALTA_58 pass
2455 08:34:47.472081 alsa_mixer-test_write_default_LCALTA_58 pass
2456 08:34:47.477662 alsa_mixer-test_write_valid_LCALTA_58 pass
2457 08:34:47.478155 alsa_mixer-test_write_invalid_LCALTA_58 pass
2458 08:34:47.483171 alsa_mixer-test_event_missing_LCALTA_58 pass
2459 08:34:47.488704 alsa_mixer-test_event_spurious_LCALTA_58 pass
2460 08:34:47.494294 alsa_mixer-test_get_value_LCALTA_57 pass
2461 08:34:47.494790 alsa_mixer-test_name_LCALTA_57 pass
2462 08:34:47.500095 alsa_mixer-test_write_default_LCALTA_57 pass
2463 08:34:47.505507 alsa_mixer-test_write_valid_LCALTA_57 pass
2464 08:34:47.506026 alsa_mixer-test_write_invalid_LCALTA_57 pass
2465 08:34:47.511040 alsa_mixer-test_event_missing_LCALTA_57 pass
2466 08:34:47.516581 alsa_mixer-test_event_spurious_LCALTA_57 pass
2467 08:34:47.517093 alsa_mixer-test_get_value_LCALTA_56 pass
2468 08:34:47.522156 alsa_mixer-test_name_LCALTA_56 pass
2469 08:34:47.527701 alsa_mixer-test_write_default_LCALTA_56 pass
2470 08:34:47.528259 alsa_mixer-test_write_valid_LCALTA_56 pass
2471 08:34:47.533228 alsa_mixer-test_write_invalid_LCALTA_56 pass
2472 08:34:47.538826 alsa_mixer-test_event_missing_LCALTA_56 pass
2473 08:34:47.544317 alsa_mixer-test_event_spurious_LCALTA_56 pass
2474 08:34:47.544824 alsa_mixer-test_get_value_LCALTA_55 pass
2475 08:34:47.549868 alsa_mixer-test_name_LCALTA_55 pass
2476 08:34:47.555425 alsa_mixer-test_write_default_LCALTA_55 pass
2477 08:34:47.555931 alsa_mixer-test_write_valid_LCALTA_55 pass
2478 08:34:47.561072 alsa_mixer-test_write_invalid_LCALTA_55 pass
2479 08:34:47.566503 alsa_mixer-test_event_missing_LCALTA_55 pass
2480 08:34:47.567003 alsa_mixer-test_event_spurious_LCALTA_55 pass
2481 08:34:47.572074 alsa_mixer-test_get_value_LCALTA_54 pass
2482 08:34:47.577593 alsa_mixer-test_name_LCALTA_54 pass
2483 08:34:47.578098 alsa_mixer-test_write_default_LCALTA_54 pass
2484 08:34:47.583133 alsa_mixer-test_write_valid_LCALTA_54 pass
2485 08:34:47.588678 alsa_mixer-test_write_invalid_LCALTA_54 pass
2486 08:34:47.589189 alsa_mixer-test_event_missing_LCALTA_54 pass
2487 08:34:47.594230 alsa_mixer-test_event_spurious_LCALTA_54 pass
2488 08:34:47.599806 alsa_mixer-test_get_value_LCALTA_53 pass
2489 08:34:47.600338 alsa_mixer-test_name_LCALTA_53 pass
2490 08:34:47.605322 alsa_mixer-test_write_default_LCALTA_53 pass
2491 08:34:47.610868 alsa_mixer-test_write_valid_LCALTA_53 pass
2492 08:34:47.616881 alsa_mixer-test_write_invalid_LCALTA_53 pass
2493 08:34:47.617426 alsa_mixer-test_event_missing_LCALTA_53 pass
2494 08:34:47.622138 alsa_mixer-test_event_spurious_LCALTA_53 pass
2495 08:34:47.627571 alsa_mixer-test_get_value_LCALTA_52 pass
2496 08:34:47.628159 alsa_mixer-test_name_LCALTA_52 pass
2497 08:34:47.633049 alsa_mixer-test_write_default_LCALTA_52 pass
2498 08:34:47.638569 alsa_mixer-test_write_valid_LCALTA_52 pass
2499 08:34:47.639078 alsa_mixer-test_write_invalid_LCALTA_52 pass
2500 08:34:47.644171 alsa_mixer-test_event_missing_LCALTA_52 pass
2501 08:34:47.649683 alsa_mixer-test_event_spurious_LCALTA_52 pass
2502 08:34:47.650195 alsa_mixer-test_get_value_LCALTA_51 pass
2503 08:34:47.655258 alsa_mixer-test_name_LCALTA_51 pass
2504 08:34:47.660835 alsa_mixer-test_write_default_LCALTA_51 pass
2505 08:34:47.661345 alsa_mixer-test_write_valid_LCALTA_51 pass
2506 08:34:47.666357 alsa_mixer-test_write_invalid_LCALTA_51 pass
2507 08:34:47.671873 alsa_mixer-test_event_missing_LCALTA_51 pass
2508 08:34:47.677443 alsa_mixer-test_event_spurious_LCALTA_51 pass
2509 08:34:47.677955 alsa_mixer-test_get_value_LCALTA_50 pass
2510 08:34:47.683048 alsa_mixer-test_name_LCALTA_50 pass
2511 08:34:47.688514 alsa_mixer-test_write_default_LCALTA_50 pass
2512 08:34:47.689033 alsa_mixer-test_write_valid_LCALTA_50 pass
2513 08:34:47.694060 alsa_mixer-test_write_invalid_LCALTA_50 pass
2514 08:34:47.699614 alsa_mixer-test_event_missing_LCALTA_50 pass
2515 08:34:47.700149 alsa_mixer-test_event_spurious_LCALTA_50 pass
2516 08:34:47.705151 alsa_mixer-test_get_value_LCALTA_49 pass
2517 08:34:47.710688 alsa_mixer-test_name_LCALTA_49 pass
2518 08:34:47.711200 alsa_mixer-test_write_default_LCALTA_49 pass
2519 08:34:47.716233 alsa_mixer-test_write_valid_LCALTA_49 pass
2520 08:34:47.721896 alsa_mixer-test_write_invalid_LCALTA_49 pass
2521 08:34:47.727359 alsa_mixer-test_event_missing_LCALTA_49 pass
2522 08:34:47.727870 alsa_mixer-test_event_spurious_LCALTA_49 pass
2523 08:34:47.732898 alsa_mixer-test_get_value_LCALTA_48 pass
2524 08:34:47.733403 alsa_mixer-test_name_LCALTA_48 pass
2525 08:34:47.738475 alsa_mixer-test_write_default_LCALTA_48 pass
2526 08:34:47.744157 alsa_mixer-test_write_valid_LCALTA_48 pass
2527 08:34:47.749554 alsa_mixer-test_write_invalid_LCALTA_48 pass
2528 08:34:47.750071 alsa_mixer-test_event_missing_LCALTA_48 pass
2529 08:34:47.755077 alsa_mixer-test_event_spurious_LCALTA_48 pass
2530 08:34:47.760675 alsa_mixer-test_get_value_LCALTA_47 pass
2531 08:34:47.761186 alsa_mixer-test_name_LCALTA_47 pass
2532 08:34:47.766189 alsa_mixer-test_write_default_LCALTA_47 pass
2533 08:34:47.771725 alsa_mixer-test_write_valid_LCALTA_47 pass
2534 08:34:47.772265 alsa_mixer-test_write_invalid_LCALTA_47 pass
2535 08:34:47.777271 alsa_mixer-test_event_missing_LCALTA_47 pass
2536 08:34:47.782826 alsa_mixer-test_event_spurious_LCALTA_47 pass
2537 08:34:47.788351 alsa_mixer-test_get_value_LCALTA_46 pass
2538 08:34:47.788861 alsa_mixer-test_name_LCALTA_46 pass
2539 08:34:47.793921 alsa_mixer-test_write_default_LCALTA_46 pass
2540 08:34:47.799457 alsa_mixer-test_write_valid_LCALTA_46 pass
2541 08:34:47.799960 alsa_mixer-test_write_invalid_LCALTA_46 pass
2542 08:34:47.805074 alsa_mixer-test_event_missing_LCALTA_46 pass
2543 08:34:47.810448 alsa_mixer-test_event_spurious_LCALTA_46 pass
2544 08:34:47.810947 alsa_mixer-test_get_value_LCALTA_45 pass
2545 08:34:47.816066 alsa_mixer-test_name_LCALTA_45 pass
2546 08:34:47.821623 alsa_mixer-test_write_default_LCALTA_45 pass
2547 08:34:47.822117 alsa_mixer-test_write_valid_LCALTA_45 pass
2548 08:34:47.827138 alsa_mixer-test_write_invalid_LCALTA_45 pass
2549 08:34:47.832669 alsa_mixer-test_event_missing_LCALTA_45 pass
2550 08:34:47.833173 alsa_mixer-test_event_spurious_LCALTA_45 pass
2551 08:34:47.838202 alsa_mixer-test_get_value_LCALTA_44 pass
2552 08:34:47.843742 alsa_mixer-test_name_LCALTA_44 pass
2553 08:34:47.844275 alsa_mixer-test_write_default_LCALTA_44 pass
2554 08:34:47.849294 alsa_mixer-test_write_valid_LCALTA_44 pass
2555 08:34:47.854853 alsa_mixer-test_write_invalid_LCALTA_44 pass
2556 08:34:47.860410 alsa_mixer-test_event_missing_LCALTA_44 pass
2557 08:34:47.860912 alsa_mixer-test_event_spurious_LCALTA_44 pass
2558 08:34:47.866028 alsa_mixer-test_get_value_LCALTA_43 pass
2559 08:34:47.871461 alsa_mixer-test_name_LCALTA_43 pass
2560 08:34:47.871956 alsa_mixer-test_write_default_LCALTA_43 pass
2561 08:34:47.877081 alsa_mixer-test_write_valid_LCALTA_43 pass
2562 08:34:47.882559 alsa_mixer-test_write_invalid_LCALTA_43 pass
2563 08:34:47.883080 alsa_mixer-test_event_missing_LCALTA_43 pass
2564 08:34:47.888201 alsa_mixer-test_event_spurious_LCALTA_43 pass
2565 08:34:47.893681 alsa_mixer-test_get_value_LCALTA_42 pass
2566 08:34:47.894196 alsa_mixer-test_name_LCALTA_42 pass
2567 08:34:47.899219 alsa_mixer-test_write_default_LCALTA_42 pass
2568 08:34:47.904764 alsa_mixer-test_write_valid_LCALTA_42 pass
2569 08:34:47.905283 alsa_mixer-test_write_invalid_LCALTA_42 pass
2570 08:34:47.910276 alsa_mixer-test_event_missing_LCALTA_42 pass
2571 08:34:47.915822 alsa_mixer-test_event_spurious_LCALTA_42 pass
2572 08:34:47.921502 alsa_mixer-test_get_value_LCALTA_41 pass
2573 08:34:47.922009 alsa_mixer-test_name_LCALTA_41 pass
2574 08:34:47.927129 alsa_mixer-test_write_default_LCALTA_41 pass
2575 08:34:47.932521 alsa_mixer-test_write_valid_LCALTA_41 pass
2576 08:34:47.933042 alsa_mixer-test_write_invalid_LCALTA_41 pass
2577 08:34:47.938088 alsa_mixer-test_event_missing_LCALTA_41 pass
2578 08:34:47.943580 alsa_mixer-test_event_spurious_LCALTA_41 pass
2579 08:34:47.944110 alsa_mixer-test_get_value_LCALTA_40 pass
2580 08:34:47.949150 alsa_mixer-test_name_LCALTA_40 pass
2581 08:34:47.954681 alsa_mixer-test_write_default_LCALTA_40 pass
2582 08:34:47.955201 alsa_mixer-test_write_valid_LCALTA_40 pass
2583 08:34:47.960237 alsa_mixer-test_write_invalid_LCALTA_40 pass
2584 08:34:47.965764 alsa_mixer-test_event_missing_LCALTA_40 pass
2585 08:34:47.971314 alsa_mixer-test_event_spurious_LCALTA_40 pass
2586 08:34:47.971822 alsa_mixer-test_get_value_LCALTA_39 pass
2587 08:34:47.976869 alsa_mixer-test_name_LCALTA_39 pass
2588 08:34:47.982399 alsa_mixer-test_write_default_LCALTA_39 pass
2589 08:34:47.982909 alsa_mixer-test_write_valid_LCALTA_39 pass
2590 08:34:47.988054 alsa_mixer-test_write_invalid_LCALTA_39 pass
2591 08:34:47.993521 alsa_mixer-test_event_missing_LCALTA_39 pass
2592 08:34:47.994028 alsa_mixer-test_event_spurious_LCALTA_39 pass
2593 08:34:47.999081 alsa_mixer-test_get_value_LCALTA_38 pass
2594 08:34:48.004602 alsa_mixer-test_name_LCALTA_38 pass
2595 08:34:48.005133 alsa_mixer-test_write_default_LCALTA_38 pass
2596 08:34:48.010144 alsa_mixer-test_write_valid_LCALTA_38 pass
2597 08:34:48.015680 alsa_mixer-test_write_invalid_LCALTA_38 pass
2598 08:34:48.016235 alsa_mixer-test_event_missing_LCALTA_38 pass
2599 08:34:48.021225 alsa_mixer-test_event_spurious_LCALTA_38 pass
2600 08:34:48.026837 alsa_mixer-test_get_value_LCALTA_37 pass
2601 08:34:48.027340 alsa_mixer-test_name_LCALTA_37 pass
2602 08:34:48.032327 alsa_mixer-test_write_default_LCALTA_37 pass
2603 08:34:48.037910 alsa_mixer-test_write_valid_LCALTA_37 pass
2604 08:34:48.043428 alsa_mixer-test_write_invalid_LCALTA_37 pass
2605 08:34:48.043934 alsa_mixer-test_event_missing_LCALTA_37 pass
2606 08:34:48.049048 alsa_mixer-test_event_spurious_LCALTA_37 pass
2607 08:34:48.054541 alsa_mixer-test_get_value_LCALTA_36 pass
2608 08:34:48.055048 alsa_mixer-test_name_LCALTA_36 pass
2609 08:34:48.060105 alsa_mixer-test_write_default_LCALTA_36 pass
2610 08:34:48.065587 alsa_mixer-test_write_valid_LCALTA_36 pass
2611 08:34:48.066084 alsa_mixer-test_write_invalid_LCALTA_36 pass
2612 08:34:48.071173 alsa_mixer-test_event_missing_LCALTA_36 pass
2613 08:34:48.076702 alsa_mixer-test_event_spurious_LCALTA_36 pass
2614 08:34:48.077210 alsa_mixer-test_get_value_LCALTA_35 pass
2615 08:34:48.082214 alsa_mixer-test_name_LCALTA_35 pass
2616 08:34:48.087785 alsa_mixer-test_write_default_LCALTA_35 pass
2617 08:34:48.088319 alsa_mixer-test_write_valid_LCALTA_35 pass
2618 08:34:48.093391 alsa_mixer-test_write_invalid_LCALTA_35 pass
2619 08:34:48.098872 alsa_mixer-test_event_missing_LCALTA_35 pass
2620 08:34:48.104442 alsa_mixer-test_event_spurious_LCALTA_35 pass
2621 08:34:48.104943 alsa_mixer-test_get_value_LCALTA_34 pass
2622 08:34:48.110043 alsa_mixer-test_name_LCALTA_34 pass
2623 08:34:48.115540 alsa_mixer-test_write_default_LCALTA_34 pass
2624 08:34:48.116075 alsa_mixer-test_write_valid_LCALTA_34 pass
2625 08:34:48.121079 alsa_mixer-test_write_invalid_LCALTA_34 pass
2626 08:34:48.126791 alsa_mixer-test_event_missing_LCALTA_34 pass
2627 08:34:48.127297 alsa_mixer-test_event_spurious_LCALTA_34 pass
2628 08:34:48.132237 alsa_mixer-test_get_value_LCALTA_33 pass
2629 08:34:48.137838 alsa_mixer-test_name_LCALTA_33 pass
2630 08:34:48.138341 alsa_mixer-test_write_default_LCALTA_33 pass
2631 08:34:48.143274 alsa_mixer-test_write_valid_LCALTA_33 pass
2632 08:34:48.148824 alsa_mixer-test_write_invalid_LCALTA_33 pass
2633 08:34:48.154353 alsa_mixer-test_event_missing_LCALTA_33 pass
2634 08:34:48.154854 alsa_mixer-test_event_spurious_LCALTA_33 pass
2635 08:34:48.160090 alsa_mixer-test_get_value_LCALTA_32 pass
2636 08:34:48.160593 alsa_mixer-test_name_LCALTA_32 pass
2637 08:34:48.165461 alsa_mixer-test_write_default_LCALTA_32 pass
2638 08:34:48.171052 alsa_mixer-test_write_valid_LCALTA_32 pass
2639 08:34:48.176547 alsa_mixer-test_write_invalid_LCALTA_32 pass
2640 08:34:48.177059 alsa_mixer-test_event_missing_LCALTA_32 pass
2641 08:34:48.182117 alsa_mixer-test_event_spurious_LCALTA_32 pass
2642 08:34:48.187661 alsa_mixer-test_get_value_LCALTA_31 pass
2643 08:34:48.188191 alsa_mixer-test_name_LCALTA_31 pass
2644 08:34:48.193226 alsa_mixer-test_write_default_LCALTA_31 pass
2645 08:34:48.198829 alsa_mixer-test_write_valid_LCALTA_31 pass
2646 08:34:48.199341 alsa_mixer-test_write_invalid_LCALTA_31 pass
2647 08:34:48.204315 alsa_mixer-test_event_missing_LCALTA_31 pass
2648 08:34:48.209825 alsa_mixer-test_event_spurious_LCALTA_31 pass
2649 08:34:48.215334 alsa_mixer-test_get_value_LCALTA_30 pass
2650 08:34:48.215833 alsa_mixer-test_name_LCALTA_30 pass
2651 08:34:48.221057 alsa_mixer-test_write_default_LCALTA_30 pass
2652 08:34:48.226499 alsa_mixer-test_write_valid_LCALTA_30 pass
2653 08:34:48.226999 alsa_mixer-test_write_invalid_LCALTA_30 pass
2654 08:34:48.232085 alsa_mixer-test_event_missing_LCALTA_30 pass
2655 08:34:48.237572 alsa_mixer-test_event_spurious_LCALTA_30 pass
2656 08:34:48.238072 alsa_mixer-test_get_value_LCALTA_29 pass
2657 08:34:48.243110 alsa_mixer-test_name_LCALTA_29 pass
2658 08:34:48.248699 alsa_mixer-test_write_default_LCALTA_29 pass
2659 08:34:48.249211 alsa_mixer-test_write_valid_LCALTA_29 pass
2660 08:34:48.254190 alsa_mixer-test_write_invalid_LCALTA_29 pass
2661 08:34:48.259824 alsa_mixer-test_event_missing_LCALTA_29 pass
2662 08:34:48.260355 alsa_mixer-test_event_spurious_LCALTA_29 pass
2663 08:34:48.265278 alsa_mixer-test_get_value_LCALTA_28 pass
2664 08:34:48.270871 alsa_mixer-test_name_LCALTA_28 pass
2665 08:34:48.271368 alsa_mixer-test_write_default_LCALTA_28 pass
2666 08:34:48.276372 alsa_mixer-test_write_valid_LCALTA_28 pass
2667 08:34:48.282087 alsa_mixer-test_write_invalid_LCALTA_28 pass
2668 08:34:48.287506 alsa_mixer-test_event_missing_LCALTA_28 pass
2669 08:34:48.288106 alsa_mixer-test_event_spurious_LCALTA_28 pass
2670 08:34:48.293169 alsa_mixer-test_get_value_LCALTA_27 pass
2671 08:34:48.298645 alsa_mixer-test_name_LCALTA_27 pass
2672 08:34:48.299227 alsa_mixer-test_write_default_LCALTA_27 pass
2673 08:34:48.304139 alsa_mixer-test_write_valid_LCALTA_27 pass
2674 08:34:48.309704 alsa_mixer-test_write_invalid_LCALTA_27 pass
2675 08:34:48.310270 alsa_mixer-test_event_missing_LCALTA_27 pass
2676 08:34:48.315224 alsa_mixer-test_event_spurious_LCALTA_27 pass
2677 08:34:48.320832 alsa_mixer-test_get_value_LCALTA_26 pass
2678 08:34:48.321362 alsa_mixer-test_name_LCALTA_26 pass
2679 08:34:48.326359 alsa_mixer-test_write_default_LCALTA_26 skip
2680 08:34:48.331878 alsa_mixer-test_write_valid_LCALTA_26 skip
2681 08:34:48.332509 alsa_mixer-test_write_invalid_LCALTA_26 skip
2682 08:34:48.337428 alsa_mixer-test_event_missing_LCALTA_26 pass
2683 08:34:48.343107 alsa_mixer-test_event_spurious_LCALTA_26 pass
2684 08:34:48.348514 alsa_mixer-test_get_value_LCALTA_25 pass
2685 08:34:48.349086 alsa_mixer-test_name_LCALTA_25 pass
2686 08:34:48.354085 alsa_mixer-test_write_default_LCALTA_25 pass
2687 08:34:48.359578 alsa_mixer-test_write_valid_LCALTA_25 skip
2688 08:34:48.360143 alsa_mixer-test_write_invalid_LCALTA_25 skip
2689 08:34:48.365132 alsa_mixer-test_event_missing_LCALTA_25 pass
2690 08:34:48.370696 alsa_mixer-test_event_spurious_LCALTA_25 pass
2691 08:34:48.371206 alsa_mixer-test_get_value_LCALTA_24 pass
2692 08:34:48.376238 alsa_mixer-test_name_LCALTA_24 pass
2693 08:34:48.381854 alsa_mixer-test_write_default_LCALTA_24 skip
2694 08:34:48.382378 alsa_mixer-test_write_valid_LCALTA_24 skip
2695 08:34:48.387341 alsa_mixer-test_write_invalid_LCALTA_24 skip
2696 08:34:48.392877 alsa_mixer-test_event_missing_LCALTA_24 pass
2697 08:34:48.398414 alsa_mixer-test_event_spurious_LCALTA_24 pass
2698 08:34:48.398924 alsa_mixer-test_get_value_LCALTA_23 pass
2699 08:34:48.404112 alsa_mixer-test_name_LCALTA_23 pass
2700 08:34:48.409508 alsa_mixer-test_write_default_LCALTA_23 skip
2701 08:34:48.410023 alsa_mixer-test_write_valid_LCALTA_23 skip
2702 08:34:48.415120 alsa_mixer-test_write_invalid_LCALTA_23 skip
2703 08:34:48.420605 alsa_mixer-test_event_missing_LCALTA_23 pass
2704 08:34:48.421124 alsa_mixer-test_event_spurious_LCALTA_23 pass
2705 08:34:48.426339 alsa_mixer-test_get_value_LCALTA_22 pass
2706 08:34:48.431788 alsa_mixer-test_name_LCALTA_22 pass
2707 08:34:48.432343 alsa_mixer-test_write_default_LCALTA_22 pass
2708 08:34:48.437271 alsa_mixer-test_write_valid_LCALTA_22 pass
2709 08:34:48.442852 alsa_mixer-test_write_invalid_LCALTA_22 pass
2710 08:34:48.443365 alsa_mixer-test_event_missing_LCALTA_22 pass
2711 08:34:48.448333 alsa_mixer-test_event_spurious_LCALTA_22 pass
2712 08:34:48.453875 alsa_mixer-test_get_value_LCALTA_21 pass
2713 08:34:48.454377 alsa_mixer-test_name_LCALTA_21 pass
2714 08:34:48.459453 alsa_mixer-test_write_default_LCALTA_21 pass
2715 08:34:48.465120 alsa_mixer-test_write_valid_LCALTA_21 pass
2716 08:34:48.470534 alsa_mixer-test_write_invalid_LCALTA_21 pass
2717 08:34:48.471038 alsa_mixer-test_event_missing_LCALTA_21 pass
2718 08:34:48.476118 alsa_mixer-test_event_spurious_LCALTA_21 pass
2719 08:34:48.481606 alsa_mixer-test_get_value_LCALTA_20 pass
2720 08:34:48.482114 alsa_mixer-test_name_LCALTA_20 pass
2721 08:34:48.487118 alsa_mixer-test_write_default_LCALTA_20 pass
2722 08:34:48.492737 alsa_mixer-test_write_valid_LCALTA_20 pass
2723 08:34:48.493258 alsa_mixer-test_write_invalid_LCALTA_20 pass
2724 08:34:48.498284 alsa_mixer-test_event_missing_LCALTA_20 pass
2725 08:34:48.503868 alsa_mixer-test_event_spurious_LCALTA_20 pass
2726 08:34:48.504403 alsa_mixer-test_get_value_LCALTA_19 pass
2727 08:34:48.509389 alsa_mixer-test_name_LCALTA_19 pass
2728 08:34:48.514898 alsa_mixer-test_write_default_LCALTA_19 pass
2729 08:34:48.515405 alsa_mixer-test_write_valid_LCALTA_19 pass
2730 08:34:48.520435 alsa_mixer-test_write_invalid_LCALTA_19 pass
2731 08:34:48.526157 alsa_mixer-test_event_missing_LCALTA_19 pass
2732 08:34:48.531576 alsa_mixer-test_event_spurious_LCALTA_19 pass
2733 08:34:48.532108 alsa_mixer-test_get_value_LCALTA_18 pass
2734 08:34:48.537127 alsa_mixer-test_name_LCALTA_18 pass
2735 08:34:48.542619 alsa_mixer-test_write_default_LCALTA_18 pass
2736 08:34:48.543125 alsa_mixer-test_write_valid_LCALTA_18 pass
2737 08:34:48.548197 alsa_mixer-test_write_invalid_LCALTA_18 pass
2738 08:34:48.553748 alsa_mixer-test_event_missing_LCALTA_18 pass
2739 08:34:48.554245 alsa_mixer-test_event_spurious_LCALTA_18 pass
2740 08:34:48.559280 alsa_mixer-test_get_value_LCALTA_17 pass
2741 08:34:48.564869 alsa_mixer-test_name_LCALTA_17 pass
2742 08:34:48.565369 alsa_mixer-test_write_default_LCALTA_17 pass
2743 08:34:48.570375 alsa_mixer-test_write_valid_LCALTA_17 pass
2744 08:34:48.575895 alsa_mixer-test_write_invalid_LCALTA_17 pass
2745 08:34:48.581509 alsa_mixer-test_event_missing_LCALTA_17 pass
2746 08:34:48.582009 alsa_mixer-test_event_spurious_LCALTA_17 pass
2747 08:34:48.587130 alsa_mixer-test_get_value_LCALTA_16 pass
2748 08:34:48.587636 alsa_mixer-test_name_LCALTA_16 pass
2749 08:34:48.592559 alsa_mixer-test_write_default_LCALTA_16 pass
2750 08:34:48.598115 alsa_mixer-test_write_valid_LCALTA_16 pass
2751 08:34:48.603737 alsa_mixer-test_write_invalid_LCALTA_16 pass
2752 08:34:48.604272 alsa_mixer-test_event_missing_LCALTA_16 pass
2753 08:34:48.609565 alsa_mixer-test_event_spurious_LCALTA_16 pass
2754 08:34:48.614821 alsa_mixer-test_get_value_LCALTA_15 pass
2755 08:34:48.615330 alsa_mixer-test_name_LCALTA_15 pass
2756 08:34:48.620334 alsa_mixer-test_write_default_LCALTA_15 pass
2757 08:34:48.625915 alsa_mixer-test_write_valid_LCALTA_15 pass
2758 08:34:48.626424 alsa_mixer-test_write_invalid_LCALTA_15 pass
2759 08:34:48.631384 alsa_mixer-test_event_missing_LCALTA_15 pass
2760 08:34:48.636965 alsa_mixer-test_event_spurious_LCALTA_15 pass
2761 08:34:48.642514 alsa_mixer-test_get_value_LCALTA_14 pass
2762 08:34:48.643046 alsa_mixer-test_name_LCALTA_14 pass
2763 08:34:48.648166 alsa_mixer-test_write_default_LCALTA_14 pass
2764 08:34:48.653555 alsa_mixer-test_write_valid_LCALTA_14 pass
2765 08:34:48.654058 alsa_mixer-test_write_invalid_LCALTA_14 pass
2766 08:34:48.659099 alsa_mixer-test_event_missing_LCALTA_14 pass
2767 08:34:48.664643 alsa_mixer-test_event_spurious_LCALTA_14 pass
2768 08:34:48.665143 alsa_mixer-test_get_value_LCALTA_13 pass
2769 08:34:48.670205 alsa_mixer-test_name_LCALTA_13 pass
2770 08:34:48.675746 alsa_mixer-test_write_default_LCALTA_13 pass
2771 08:34:48.676353 alsa_mixer-test_write_valid_LCALTA_13 pass
2772 08:34:48.681308 alsa_mixer-test_write_invalid_LCALTA_13 pass
2773 08:34:48.686909 alsa_mixer-test_event_missing_LCALTA_13 pass
2774 08:34:48.687430 alsa_mixer-test_event_spurious_LCALTA_13 pass
2775 08:34:48.692390 alsa_mixer-test_get_value_LCALTA_12 pass
2776 08:34:48.697948 alsa_mixer-test_name_LCALTA_12 pass
2777 08:34:48.698572 alsa_mixer-test_write_default_LCALTA_12 pass
2778 08:34:48.703537 alsa_mixer-test_write_valid_LCALTA_12 pass
2779 08:34:48.709203 alsa_mixer-test_write_invalid_LCALTA_12 pass
2780 08:34:48.714578 alsa_mixer-test_event_missing_LCALTA_12 pass
2781 08:34:48.715156 alsa_mixer-test_event_spurious_LCALTA_12 pass
2782 08:34:48.720142 alsa_mixer-test_get_value_LCALTA_11 pass
2783 08:34:48.725750 alsa_mixer-test_name_LCALTA_11 pass
2784 08:34:48.726307 alsa_mixer-test_write_default_LCALTA_11 pass
2785 08:34:48.731185 alsa_mixer-test_write_valid_LCALTA_11 pass
2786 08:34:48.736744 alsa_mixer-test_write_invalid_LCALTA_11 pass
2787 08:34:48.737308 alsa_mixer-test_event_missing_LCALTA_11 pass
2788 08:34:48.742316 alsa_mixer-test_event_spurious_LCALTA_11 pass
2789 08:34:48.747959 alsa_mixer-test_get_value_LCALTA_10 pass
2790 08:34:48.748595 alsa_mixer-test_name_LCALTA_10 pass
2791 08:34:48.753498 alsa_mixer-test_write_default_LCALTA_10 pass
2792 08:34:48.758938 alsa_mixer-test_write_valid_LCALTA_10 pass
2793 08:34:48.759498 alsa_mixer-test_write_invalid_LCALTA_10 pass
2794 08:34:48.764536 alsa_mixer-test_event_missing_LCALTA_10 pass
2795 08:34:48.770123 alsa_mixer-test_event_spurious_LCALTA_10 pass
2796 08:34:48.775622 alsa_mixer-test_get_value_LCALTA_9 pass
2797 08:34:48.776282 alsa_mixer-test_name_LCALTA_9 pass
2798 08:34:48.781239 alsa_mixer-test_write_default_LCALTA_9 pass
2799 08:34:48.786685 alsa_mixer-test_write_valid_LCALTA_9 pass
2800 08:34:48.787239 alsa_mixer-test_write_invalid_LCALTA_9 pass
2801 08:34:48.792318 alsa_mixer-test_event_missing_LCALTA_9 pass
2802 08:34:48.797782 alsa_mixer-test_event_spurious_LCALTA_9 pass
2803 08:34:48.798344 alsa_mixer-test_get_value_LCALTA_8 pass
2804 08:34:48.803311 alsa_mixer-test_name_LCALTA_8 pass
2805 08:34:48.808978 alsa_mixer-test_write_default_LCALTA_8 pass
2806 08:34:48.809574 alsa_mixer-test_write_valid_LCALTA_8 pass
2807 08:34:48.814471 alsa_mixer-test_write_invalid_LCALTA_8 pass
2808 08:34:48.819956 alsa_mixer-test_event_missing_LCALTA_8 pass
2809 08:34:48.820584 alsa_mixer-test_event_spurious_LCALTA_8 pass
2810 08:34:48.825580 alsa_mixer-test_get_value_LCALTA_7 pass
2811 08:34:48.831221 alsa_mixer-test_name_LCALTA_7 pass
2812 08:34:48.831765 alsa_mixer-test_write_default_LCALTA_7 pass
2813 08:34:48.836712 alsa_mixer-test_write_valid_LCALTA_7 pass
2814 08:34:48.842276 alsa_mixer-test_write_invalid_LCALTA_7 pass
2815 08:34:48.842796 alsa_mixer-test_event_missing_LCALTA_7 pass
2816 08:34:48.847806 alsa_mixer-test_event_spurious_LCALTA_7 pass
2817 08:34:48.853220 alsa_mixer-test_get_value_LCALTA_6 pass
2818 08:34:48.853798 alsa_mixer-test_name_LCALTA_6 pass
2819 08:34:48.858822 alsa_mixer-test_write_default_LCALTA_6 pass
2820 08:34:48.864463 alsa_mixer-test_write_valid_LCALTA_6 pass
2821 08:34:48.864999 alsa_mixer-test_write_invalid_LCALTA_6 pass
2822 08:34:48.869927 alsa_mixer-test_event_missing_LCALTA_6 pass
2823 08:34:48.875412 alsa_mixer-test_event_spurious_LCALTA_6 pass
2824 08:34:48.875939 alsa_mixer-test_get_value_LCALTA_5 pass
2825 08:34:48.881039 alsa_mixer-test_name_LCALTA_5 pass
2826 08:34:48.886509 alsa_mixer-test_write_default_LCALTA_5 pass
2827 08:34:48.887041 alsa_mixer-test_write_valid_LCALTA_5 pass
2828 08:34:48.892314 alsa_mixer-test_write_invalid_LCALTA_5 pass
2829 08:34:48.897838 alsa_mixer-test_event_missing_LCALTA_5 pass
2830 08:34:48.898420 alsa_mixer-test_event_spurious_LCALTA_5 pass
2831 08:34:48.903139 alsa_mixer-test_get_value_LCALTA_4 pass
2832 08:34:48.908744 alsa_mixer-test_name_LCALTA_4 pass
2833 08:34:48.909300 alsa_mixer-test_write_default_LCALTA_4 pass
2834 08:34:48.914272 alsa_mixer-test_write_valid_LCALTA_4 pass
2835 08:34:48.919837 alsa_mixer-test_write_invalid_LCALTA_4 pass
2836 08:34:48.920458 alsa_mixer-test_event_missing_LCALTA_4 pass
2837 08:34:48.925388 alsa_mixer-test_event_spurious_LCALTA_4 pass
2838 08:34:48.930939 alsa_mixer-test_get_value_LCALTA_3 pass
2839 08:34:48.931473 alsa_mixer-test_name_LCALTA_3 pass
2840 08:34:48.936427 alsa_mixer-test_write_default_LCALTA_3 pass
2841 08:34:48.941958 alsa_mixer-test_write_valid_LCALTA_3 pass
2842 08:34:48.942476 alsa_mixer-test_write_invalid_LCALTA_3 pass
2843 08:34:48.947521 alsa_mixer-test_event_missing_LCALTA_3 pass
2844 08:34:48.953283 alsa_mixer-test_event_spurious_LCALTA_3 pass
2845 08:34:48.953873 alsa_mixer-test_get_value_LCALTA_2 pass
2846 08:34:48.958577 alsa_mixer-test_name_LCALTA_2 pass
2847 08:34:48.964237 alsa_mixer-test_write_default_LCALTA_2 pass
2848 08:34:48.964740 alsa_mixer-test_write_valid_LCALTA_2 pass
2849 08:34:48.969702 alsa_mixer-test_write_invalid_LCALTA_2 pass
2850 08:34:48.975245 alsa_mixer-test_event_missing_LCALTA_2 pass
2851 08:34:48.980834 alsa_mixer-test_event_spurious_LCALTA_2 pass
2852 08:34:48.981319 alsa_mixer-test_get_value_LCALTA_1 pass
2853 08:34:48.986425 alsa_mixer-test_name_LCALTA_1 pass
2854 08:34:48.986902 alsa_mixer-test_write_default_LCALTA_1 pass
2855 08:34:48.991874 alsa_mixer-test_write_valid_LCALTA_1 pass
2856 08:34:48.997409 alsa_mixer-test_write_invalid_LCALTA_1 pass
2857 08:34:49.002985 alsa_mixer-test_event_missing_LCALTA_1 pass
2858 08:34:49.003460 alsa_mixer-test_event_spurious_LCALTA_1 pass
2859 08:34:49.008524 alsa_mixer-test_get_value_LCALTA_0 pass
2860 08:34:49.008997 alsa_mixer-test_name_LCALTA_0 pass
2861 08:34:49.014173 alsa_mixer-test_write_default_LCALTA_0 pass
2862 08:34:49.019648 alsa_mixer-test_write_valid_LCALTA_0 pass
2863 08:34:49.025224 alsa_mixer-test_write_invalid_LCALTA_0 pass
2864 08:34:49.025707 alsa_mixer-test_event_missing_LCALTA_0 pass
2865 08:34:49.030749 alsa_mixer-test_event_spurious_LCALTA_0 pass
2866 08:34:49.031223 alsa_mixer-test pass
2867 08:34:49.036278 alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE skip
2868 08:34:49.041965 alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE skip
2869 08:34:49.047345 alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE skip
2870 08:34:49.052911 alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE skip
2871 08:34:49.053453 alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE skip
2872 08:34:49.058451 alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE skip
2873 08:34:49.064098 alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE skip
2874 08:34:49.069649 alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE skip
2875 08:34:49.075209 alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE skip
2876 08:34:49.080630 alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE skip
2877 08:34:49.081150 alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE skip
2878 08:34:49.086290 alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE skip
2879 08:34:49.091717 alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE skip
2880 08:34:49.097344 alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE skip
2881 08:34:49.102807 alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE skip
2882 08:34:49.108353 alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE skip
2883 08:34:49.108898 alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE skip
2884 08:34:49.113889 alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE skip
2885 08:34:49.119429 alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE skip
2886 08:34:49.125047 alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE skip
2887 08:34:49.130533 alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE skip
2888 08:34:49.136290 alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK skip
2889 08:34:49.136820 alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK skip
2890 08:34:49.141756 alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK skip
2891 08:34:49.147280 alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK skip
2892 08:34:49.152883 alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK skip
2893 08:34:49.158497 alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK skip
2894 08:34:49.163899 alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK skip
2895 08:34:49.164468 alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK skip
2896 08:34:49.169579 alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK skip
2897 08:34:49.174934 alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK skip
2898 08:34:49.180501 alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK skip
2899 08:34:49.186286 alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK skip
2900 08:34:49.191586 alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK skip
2901 08:34:49.197219 alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK skip
2902 08:34:49.197791 alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK skip
2903 08:34:49.202736 alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK skip
2904 08:34:49.208319 alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK skip
2905 08:34:49.213798 alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK skip
2906 08:34:49.219408 alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK skip
2907 08:34:49.224968 alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK skip
2908 08:34:49.225528 alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK skip
2909 08:34:49.230442 alsa_pcm-test pass
2910 08:34:49.236208 alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2911 08:34:49.247076 alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2912 08:34:49.252616 alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2913 08:34:49.263726 alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2914 08:34:49.269306 alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded skip
2915 08:34:49.274813 alsa_test-pcmtest-driver pass
2916 08:34:49.280357 alsa_utimer-test_global_wrong_timers_test pass
2917 08:34:49.280910 alsa_utimer-test_timer_f_utimer fail
2918 08:34:49.285864 alsa_utimer-test fail
2919 08:34:49.286397 + ../../utils/send-to-lava.sh ./output/result.txt
2920 08:34:49.291498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
2921 08:34:49.293102 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
2923 08:34:49.302596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass>
2924 08:34:49.303564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_60 RESULT=pass
2926 08:34:49.307498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass>
2927 08:34:49.308394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_60 RESULT=pass
2929 08:34:49.322833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass>
2930 08:34:49.323800 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_60 RESULT=pass
2932 08:34:49.374581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass>
2933 08:34:49.375565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_60 RESULT=pass
2935 08:34:49.428090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass>
2936 08:34:49.429053 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_60 RESULT=pass
2938 08:34:49.480743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass>
2939 08:34:49.481667 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_60 RESULT=pass
2941 08:34:49.532521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass>
2942 08:34:49.533416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_60 RESULT=pass
2944 08:34:49.586198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass>
2945 08:34:49.587115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_59 RESULT=pass
2947 08:34:49.639244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass>
2948 08:34:49.640208 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_59 RESULT=pass
2950 08:34:49.695412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass>
2951 08:34:49.696386 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_59 RESULT=pass
2953 08:34:49.755182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass>
2954 08:34:49.756089 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_59 RESULT=pass
2956 08:34:49.808524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass>
2957 08:34:49.809421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_59 RESULT=pass
2959 08:34:49.866148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass>
2960 08:34:49.867061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_59 RESULT=pass
2962 08:34:49.911826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass>
2963 08:34:49.912732 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_59 RESULT=pass
2965 08:34:49.960229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass>
2966 08:34:49.961139 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_58 RESULT=pass
2968 08:34:50.006205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass>
2969 08:34:50.007192 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_58 RESULT=pass
2971 08:34:50.057288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass>
2972 08:34:50.058144 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_58 RESULT=pass
2974 08:34:50.104571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass>
2975 08:34:50.105467 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_58 RESULT=pass
2977 08:34:50.159328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass>
2978 08:34:50.160213 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_58 RESULT=pass
2980 08:34:50.210751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass>
2981 08:34:50.211652 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_58 RESULT=pass
2983 08:34:50.261535 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass>
2984 08:34:50.262120 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_58 RESULT=pass
2986 08:34:50.313573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass>
2987 08:34:50.314151 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_57 RESULT=pass
2989 08:34:50.361513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass>
2990 08:34:50.362080 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_57 RESULT=pass
2992 08:34:50.412474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass>
2993 08:34:50.413026 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_57 RESULT=pass
2995 08:34:50.457724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass>
2996 08:34:50.458278 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_57 RESULT=pass
2998 08:34:50.511182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass>
2999 08:34:50.511733 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_57 RESULT=pass
3001 08:34:50.563553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass>
3002 08:34:50.564102 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_57 RESULT=pass
3004 08:34:50.615053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass>
3005 08:34:50.615596 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_57 RESULT=pass
3007 08:34:50.660577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass>
3008 08:34:50.661105 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_56 RESULT=pass
3010 08:34:50.711621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass>
3011 08:34:50.712168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_56 RESULT=pass
3013 08:34:50.766575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass>
3014 08:34:50.767114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_56 RESULT=pass
3016 08:34:50.817844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass>
3017 08:34:50.818375 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_56 RESULT=pass
3019 08:34:50.862329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass>
3020 08:34:50.862877 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_56 RESULT=pass
3022 08:34:50.913564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass>
3023 08:34:50.914115 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_56 RESULT=pass
3025 08:34:50.962679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass>
3026 08:34:50.963226 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_56 RESULT=pass
3028 08:34:51.019692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass>
3029 08:34:51.020259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_55 RESULT=pass
3031 08:34:51.072409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass>
3032 08:34:51.072964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_55 RESULT=pass
3034 08:34:51.116671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass>
3035 08:34:51.117244 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_55 RESULT=pass
3037 08:34:51.171603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass>
3038 08:34:51.172168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_55 RESULT=pass
3040 08:34:51.215824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass>
3041 08:34:51.216409 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_55 RESULT=pass
3043 08:34:51.265807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass>
3044 08:34:51.266358 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_55 RESULT=pass
3046 08:34:51.315585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass>
3047 08:34:51.316130 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_55 RESULT=pass
3049 08:34:51.361246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass>
3050 08:34:51.361793 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_54 RESULT=pass
3052 08:34:51.408738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass>
3053 08:34:51.409268 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_54 RESULT=pass
3055 08:34:51.462071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass>
3056 08:34:51.462609 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_54 RESULT=pass
3058 08:34:51.511324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass>
3059 08:34:51.511854 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_54 RESULT=pass
3061 08:34:51.566022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass>
3062 08:34:51.566556 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_54 RESULT=pass
3064 08:34:51.618284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass>
3065 08:34:51.618811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_54 RESULT=pass
3067 08:34:51.672502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass>
3068 08:34:51.673072 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_54 RESULT=pass
3070 08:34:51.724503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass>
3071 08:34:51.725040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_53 RESULT=pass
3073 08:34:51.774800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass>
3074 08:34:51.775329 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_53 RESULT=pass
3076 08:34:51.823871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass>
3077 08:34:51.824432 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_53 RESULT=pass
3079 08:34:51.870207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass>
3080 08:34:51.870746 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_53 RESULT=pass
3082 08:34:51.914195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass>
3083 08:34:51.914743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_53 RESULT=pass
3085 08:34:51.961258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass>
3086 08:34:51.961865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_53 RESULT=pass
3088 08:34:52.011661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass>
3089 08:34:52.012235 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_53 RESULT=pass
3091 08:34:52.062814 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass>
3092 08:34:52.063337 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_52 RESULT=pass
3094 08:34:52.105956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass>
3095 08:34:52.106479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_52 RESULT=pass
3097 08:34:52.163089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass>
3098 08:34:52.163609 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_52 RESULT=pass
3100 08:34:52.213047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass>
3101 08:34:52.213575 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_52 RESULT=pass
3103 08:34:52.264666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass>
3104 08:34:52.265198 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_52 RESULT=pass
3106 08:34:52.309553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass>
3107 08:34:52.310069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_52 RESULT=pass
3109 08:34:52.366288 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass>
3110 08:34:52.366802 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_52 RESULT=pass
3112 08:34:52.417543 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass>
3113 08:34:52.418061 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_51 RESULT=pass
3115 08:34:52.467948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass>
3116 08:34:52.468506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_51 RESULT=pass
3118 08:34:52.519677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass>
3119 08:34:52.520217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_51 RESULT=pass
3121 08:34:52.573890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass>
3122 08:34:52.574437 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_51 RESULT=pass
3124 08:34:52.629895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass>
3125 08:34:52.630419 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_51 RESULT=pass
3127 08:34:52.679633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass>
3128 08:34:52.680154 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_51 RESULT=pass
3130 08:34:52.735482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass>
3131 08:34:52.736035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_51 RESULT=pass
3133 08:34:52.790996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass>
3134 08:34:52.791532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_50 RESULT=pass
3136 08:34:52.844564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass>
3137 08:34:52.845079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_50 RESULT=pass
3139 08:34:52.889376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass>
3140 08:34:52.890205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_50 RESULT=pass
3142 08:34:52.940985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass>
3143 08:34:52.941806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_50 RESULT=pass
3145 08:34:52.987621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass>
3146 08:34:52.988511 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_50 RESULT=pass
3148 08:34:53.034432 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass>
3149 08:34:53.035346 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_50 RESULT=pass
3151 08:34:53.090335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass>
3152 08:34:53.091211 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_50 RESULT=pass
3154 08:34:53.144534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass>
3155 08:34:53.145347 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_49 RESULT=pass
3157 08:34:53.198345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass>
3158 08:34:53.199150 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_49 RESULT=pass
3160 08:34:53.248367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass>
3161 08:34:53.249236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_49 RESULT=pass
3163 08:34:53.310101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass>
3164 08:34:53.310966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_49 RESULT=pass
3166 08:34:53.373803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass>
3167 08:34:53.374667 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_49 RESULT=pass
3169 08:34:53.423367 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass>
3170 08:34:53.424334 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_49 RESULT=pass
3172 08:34:53.481470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass>
3173 08:34:53.482358 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_49 RESULT=pass
3175 08:34:53.539496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass>
3176 08:34:53.540464 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_48 RESULT=pass
3178 08:34:53.583649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass>
3179 08:34:53.584337 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_48 RESULT=pass
3181 08:34:53.641798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass>
3182 08:34:53.642791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_48 RESULT=pass
3184 08:34:53.687118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass>
3185 08:34:53.688077 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_48 RESULT=pass
3187 08:34:53.734786 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass>
3188 08:34:53.735672 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_48 RESULT=pass
3190 08:34:53.782572 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass>
3191 08:34:53.783632 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_48 RESULT=pass
3193 08:34:53.829133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass>
3194 08:34:53.830119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_48 RESULT=pass
3196 08:34:53.875239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass>
3197 08:34:53.876180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_47 RESULT=pass
3199 08:34:53.939772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass>
3200 08:34:53.940672 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_47 RESULT=pass
3202 08:34:53.994171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass>
3203 08:34:53.994750 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_47 RESULT=pass
3205 08:34:54.045882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass>
3206 08:34:54.046442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_47 RESULT=pass
3208 08:34:54.101279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass>
3209 08:34:54.101832 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_47 RESULT=pass
3211 08:34:54.159450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass>
3212 08:34:54.160041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_47 RESULT=pass
3214 08:34:54.212451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass>
3215 08:34:54.213054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_47 RESULT=pass
3217 08:34:54.262125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass>
3218 08:34:54.262668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_46 RESULT=pass
3220 08:34:54.317164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass>
3221 08:34:54.317748 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_46 RESULT=pass
3223 08:34:54.367585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass>
3224 08:34:54.368145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_46 RESULT=pass
3226 08:34:54.426172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass>
3227 08:34:54.426770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_46 RESULT=pass
3229 08:34:54.476546 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass>
3230 08:34:54.477132 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_46 RESULT=pass
3232 08:34:54.527257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass>
3233 08:34:54.527797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_46 RESULT=pass
3235 08:34:54.573782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass>
3236 08:34:54.574322 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_46 RESULT=pass
3238 08:34:54.623302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass>
3239 08:34:54.623826 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_45 RESULT=pass
3241 08:34:54.673700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass>
3242 08:34:54.674271 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_45 RESULT=pass
3244 08:34:54.727034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass>
3245 08:34:54.727586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_45 RESULT=pass
3247 08:34:54.779141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass>
3248 08:34:54.779704 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_45 RESULT=pass
3250 08:34:54.834812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass>
3251 08:34:54.835388 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_45 RESULT=pass
3253 08:34:54.887063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass>
3254 08:34:54.887638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_45 RESULT=pass
3256 08:34:54.930281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass>
3257 08:34:54.930846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_45 RESULT=pass
3259 08:34:54.982225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass>
3260 08:34:54.982791 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_44 RESULT=pass
3262 08:34:55.036555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass>
3263 08:34:55.037107 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_44 RESULT=pass
3265 08:34:55.091844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass>
3266 08:34:55.092457 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_44 RESULT=pass
3268 08:34:55.138429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass>
3269 08:34:55.138994 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_44 RESULT=pass
3271 08:34:55.192200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass>
3272 08:34:55.192772 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_44 RESULT=pass
3274 08:34:55.243671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass>
3275 08:34:55.244318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_44 RESULT=pass
3277 08:34:55.290247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass>
3278 08:34:55.290853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_44 RESULT=pass
3280 08:34:55.336454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass>
3281 08:34:55.337047 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_43 RESULT=pass
3283 08:34:55.385992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass>
3284 08:34:55.386596 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_43 RESULT=pass
3286 08:34:55.439060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass>
3287 08:34:55.439663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_43 RESULT=pass
3289 08:34:55.484750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass>
3290 08:34:55.485323 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_43 RESULT=pass
3292 08:34:55.535087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass>
3293 08:34:55.535663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_43 RESULT=pass
3295 08:34:55.586792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass>
3296 08:34:55.587380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_43 RESULT=pass
3298 08:34:55.635211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass>
3299 08:34:55.635795 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_43 RESULT=pass
3301 08:34:55.690340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass>
3302 08:34:55.690937 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_42 RESULT=pass
3304 08:34:55.733996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass>
3305 08:34:55.734613 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_42 RESULT=pass
3307 08:34:55.794595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass>
3308 08:34:55.795180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_42 RESULT=pass
3310 08:34:55.855307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass>
3311 08:34:55.855882 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_42 RESULT=pass
3313 08:34:55.900258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass>
3314 08:34:55.900811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_42 RESULT=pass
3316 08:34:55.955996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass>
3317 08:34:55.956545 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_42 RESULT=pass
3319 08:34:56.009237 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass>
3320 08:34:56.009801 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_42 RESULT=pass
3322 08:34:56.065270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass>
3323 08:34:56.065851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_41 RESULT=pass
3325 08:34:56.108926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass>
3326 08:34:56.109489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_41 RESULT=pass
3328 08:34:56.155951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass>
3329 08:34:56.156561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_41 RESULT=pass
3331 08:34:56.215116 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass>
3332 08:34:56.215695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_41 RESULT=pass
3334 08:34:56.263970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass>
3335 08:34:56.264639 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_41 RESULT=pass
3337 08:34:56.317874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass>
3338 08:34:56.318534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_41 RESULT=pass
3340 08:34:56.368882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass>
3341 08:34:56.369503 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_41 RESULT=pass
3343 08:34:56.412122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass>
3344 08:34:56.412692 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_40 RESULT=pass
3346 08:34:56.460108 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass>
3347 08:34:56.460649 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_40 RESULT=pass
3349 08:34:56.517414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass>
3350 08:34:56.518035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_40 RESULT=pass
3352 08:34:56.565589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass>
3353 08:34:56.566353 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_40 RESULT=pass
3355 08:34:56.625434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass>
3356 08:34:56.626101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_40 RESULT=pass
3358 08:34:56.682044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass>
3359 08:34:56.682965 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_40 RESULT=pass
3361 08:34:56.732845 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass>
3362 08:34:56.733750 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_40 RESULT=pass
3364 08:34:56.786666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass>
3365 08:34:56.787568 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_39 RESULT=pass
3367 08:34:56.840259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass>
3368 08:34:56.841271 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_39 RESULT=pass
3370 08:34:56.915502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass>
3371 08:34:56.916743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_39 RESULT=pass
3373 08:34:56.986056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass>
3374 08:34:56.986665 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_39 RESULT=pass
3376 08:34:57.033167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass>
3377 08:34:57.034109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_39 RESULT=pass
3379 08:34:57.089021 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass>
3380 08:34:57.089926 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_39 RESULT=pass
3382 08:34:57.146202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass>
3383 08:34:57.147134 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_39 RESULT=pass
3385 08:34:57.212561 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass>
3386 08:34:57.213480 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_38 RESULT=pass
3388 08:34:57.271822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass>
3389 08:34:57.272784 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_38 RESULT=pass
3391 08:34:57.328604 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass>
3392 08:34:57.329471 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_38 RESULT=pass
3394 08:34:57.373503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass>
3395 08:34:57.374390 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_38 RESULT=pass
3397 08:34:57.428985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass>
3398 08:34:57.429858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_38 RESULT=pass
3400 08:34:57.476375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass>
3401 08:34:57.477245 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_38 RESULT=pass
3403 08:34:57.529625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass>
3404 08:34:57.530491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_38 RESULT=pass
3406 08:34:57.585538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass>
3407 08:34:57.586179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_37 RESULT=pass
3409 08:34:57.632601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass>
3410 08:34:57.633489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_37 RESULT=pass
3412 08:34:57.684872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass>
3413 08:34:57.685725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_37 RESULT=pass
3415 08:34:57.735229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass>
3416 08:34:57.736095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_37 RESULT=pass
3418 08:34:57.779732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass>
3419 08:34:57.780583 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_37 RESULT=pass
3421 08:34:57.830222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass>
3422 08:34:57.831074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_37 RESULT=pass
3424 08:34:57.875659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass>
3425 08:34:57.876576 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_37 RESULT=pass
3427 08:34:57.932016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass>
3428 08:34:57.932831 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_36 RESULT=pass
3430 08:34:57.987743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass>
3431 08:34:57.988598 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_36 RESULT=pass
3433 08:34:58.040690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass>
3434 08:34:58.041518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_36 RESULT=pass
3436 08:34:58.092682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass>
3437 08:34:58.093523 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_36 RESULT=pass
3439 08:34:58.150921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass>
3440 08:34:58.151821 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_36 RESULT=pass
3442 08:34:58.207170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass>
3443 08:34:58.208069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_36 RESULT=pass
3445 08:34:58.264113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass>
3446 08:34:58.264969 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_36 RESULT=pass
3448 08:34:58.310751 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass>
3449 08:34:58.311567 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_35 RESULT=pass
3451 08:34:58.362141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass>
3452 08:34:58.363008 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_35 RESULT=pass
3454 08:34:58.408394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass>
3455 08:34:58.409225 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_35 RESULT=pass
3457 08:34:58.462575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass>
3458 08:34:58.463436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_35 RESULT=pass
3460 08:34:58.514534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass>
3461 08:34:58.515415 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_35 RESULT=pass
3463 08:34:58.570112 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass>
3464 08:34:58.570942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_35 RESULT=pass
3466 08:34:58.622544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass>
3467 08:34:58.623375 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_35 RESULT=pass
3469 08:34:58.672560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass>
3470 08:34:58.673230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_34 RESULT=pass
3472 08:34:58.727433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass>
3473 08:34:58.728132 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_34 RESULT=pass
3475 08:34:58.776037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass>
3476 08:34:58.776697 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_34 RESULT=pass
3478 08:34:58.826173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass>
3479 08:34:58.826951 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_34 RESULT=pass
3481 08:34:59.135103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass>
3482 08:34:59.135527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass>
3483 08:34:59.135779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass>
3484 08:34:59.136052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass>
3485 08:34:59.136574 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_34 RESULT=pass
3487 08:34:59.137615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_34 RESULT=pass
3489 08:34:59.138365 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_34 RESULT=pass
3491 08:34:59.139069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_33 RESULT=pass
3493 08:34:59.139820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass>
3494 08:34:59.140331 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_33 RESULT=pass
3496 08:34:59.153223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass>
3497 08:34:59.153812 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_33 RESULT=pass
3499 08:34:59.213191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass>
3500 08:34:59.213830 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_33 RESULT=pass
3502 08:34:59.259125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass>
3503 08:34:59.259755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_33 RESULT=pass
3505 08:34:59.316429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass>
3506 08:34:59.317055 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_33 RESULT=pass
3508 08:34:59.367321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass>
3509 08:34:59.367952 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_33 RESULT=pass
3511 08:34:59.419536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass>
3512 08:34:59.420169 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_32 RESULT=pass
3514 08:34:59.467823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass>
3515 08:34:59.468484 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_32 RESULT=pass
3517 08:34:59.522888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass>
3518 08:34:59.523525 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_32 RESULT=pass
3520 08:34:59.575327 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass>
3521 08:34:59.575972 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_32 RESULT=pass
3523 08:34:59.619366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass>
3524 08:34:59.620060 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_32 RESULT=pass
3526 08:34:59.665399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass>
3527 08:34:59.666029 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_32 RESULT=pass
3529 08:34:59.714943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass>
3530 08:34:59.715836 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_32 RESULT=pass
3532 08:35:00.056098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass>
3533 08:35:00.056987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_31 RESULT=pass
3535 08:35:00.106686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass>
3536 08:35:00.107554 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_31 RESULT=pass
3538 08:35:00.161400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass>
3539 08:35:00.162247 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_31 RESULT=pass
3541 08:35:00.206711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass>
3542 08:35:00.207572 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_31 RESULT=pass
3544 08:35:00.255848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass>
3545 08:35:00.256709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_31 RESULT=pass
3547 08:35:00.307057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass>
3548 08:35:00.307927 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_31 RESULT=pass
3550 08:35:00.354739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass>
3551 08:35:00.355567 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_31 RESULT=pass
3553 08:35:00.400455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass>
3554 08:35:00.401314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_30 RESULT=pass
3556 08:35:00.452139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass>
3557 08:35:00.453169 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_30 RESULT=pass
3559 08:35:00.497319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass>
3560 08:35:00.498352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_30 RESULT=pass
3562 08:35:00.543341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass>
3563 08:35:00.544421 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_30 RESULT=pass
3565 08:35:00.600947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass>
3566 08:35:00.602018 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_30 RESULT=pass
3568 08:35:00.646607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass>
3569 08:35:00.647609 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_30 RESULT=pass
3571 08:35:00.695335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass>
3572 08:35:00.696655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_30 RESULT=pass
3574 08:35:00.738872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass>
3575 08:35:00.739927 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_29 RESULT=pass
3577 08:35:00.789889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass>
3578 08:35:00.790961 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_29 RESULT=pass
3580 08:35:00.840743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass>
3581 08:35:00.841801 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_29 RESULT=pass
3583 08:35:00.892941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass>
3584 08:35:00.893987 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_29 RESULT=pass
3586 08:35:00.942172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass>
3587 08:35:00.943268 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_29 RESULT=pass
3589 08:35:00.994144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass>
3590 08:35:00.995213 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_29 RESULT=pass
3592 08:35:01.045592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass>
3593 08:35:01.046660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_29 RESULT=pass
3595 08:35:01.096620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass>
3596 08:35:01.097830 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_28 RESULT=pass
3598 08:35:01.143665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass>
3599 08:35:01.144352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_28 RESULT=pass
3601 08:35:01.207107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass>
3602 08:35:01.207755 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_28 RESULT=pass
3604 08:35:01.263345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass>
3605 08:35:01.264030 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_28 RESULT=pass
3607 08:35:01.314421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass>
3608 08:35:01.315049 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_28 RESULT=pass
3610 08:35:01.384128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass>
3611 08:35:01.384833 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_28 RESULT=pass
3613 08:35:01.438706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass>
3614 08:35:01.439403 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_28 RESULT=pass
3616 08:35:01.489537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass>
3617 08:35:01.490219 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_27 RESULT=pass
3619 08:35:01.534810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass>
3620 08:35:01.535479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_27 RESULT=pass
3622 08:35:01.593781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass>
3623 08:35:01.594511 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_27 RESULT=pass
3625 08:35:01.651129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass>
3626 08:35:01.651937 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_27 RESULT=pass
3628 08:35:01.705429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass>
3629 08:35:01.706224 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_27 RESULT=pass
3631 08:35:01.761395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass>
3632 08:35:01.762283 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_27 RESULT=pass
3634 08:35:01.818178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass>
3635 08:35:01.818997 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_27 RESULT=pass
3637 08:35:01.874431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass>
3638 08:35:01.875326 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_26 RESULT=pass
3640 08:35:01.933727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass>
3641 08:35:01.934469 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_26 RESULT=pass
3643 08:35:01.988397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip>
3644 08:35:01.989292 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_26 RESULT=skip
3646 08:35:02.034191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip>
3647 08:35:02.035043 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_26 RESULT=skip
3649 08:35:02.078706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip>
3650 08:35:02.079581 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_26 RESULT=skip
3652 08:35:02.136107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass>
3653 08:35:02.137009 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_26 RESULT=pass
3655 08:35:02.193075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass>
3656 08:35:02.193963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_26 RESULT=pass
3658 08:35:02.252458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass>
3659 08:35:02.254083 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_25 RESULT=pass
3661 08:35:02.309487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass>
3662 08:35:02.310546 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_25 RESULT=pass
3664 08:35:02.368317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass>
3665 08:35:02.369048 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_25 RESULT=pass
3667 08:35:02.421189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip>
3668 08:35:02.421924 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_25 RESULT=skip
3670 08:35:02.473765 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip>
3671 08:35:02.474531 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_25 RESULT=skip
3673 08:35:02.522819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass>
3674 08:35:02.523462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_25 RESULT=pass
3676 08:35:02.575612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass>
3677 08:35:02.576279 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_25 RESULT=pass
3679 08:35:02.637963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass>
3680 08:35:02.638678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_24 RESULT=pass
3682 08:35:02.688955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass>
3683 08:35:02.689960 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_24 RESULT=pass
3685 08:35:02.739615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip>
3686 08:35:02.740588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_24 RESULT=skip
3688 08:35:02.795126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip>
3689 08:35:02.795831 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_24 RESULT=skip
3691 08:35:02.845233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip>
3692 08:35:02.845890 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_24 RESULT=skip
3694 08:35:02.905348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass>
3695 08:35:02.906028 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_24 RESULT=pass
3697 08:35:02.967144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass>
3698 08:35:02.967786 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_24 RESULT=pass
3700 08:35:03.013412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass>
3701 08:35:03.014337 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_23 RESULT=pass
3703 08:35:03.072534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass>
3704 08:35:03.073417 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_23 RESULT=pass
3706 08:35:03.127062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip>
3707 08:35:03.127960 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_23 RESULT=skip
3709 08:35:03.183311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip>
3710 08:35:03.184127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_23 RESULT=skip
3712 08:35:03.235967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip>
3713 08:35:03.236685 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_23 RESULT=skip
3715 08:35:03.287950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass>
3716 08:35:03.288893 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_23 RESULT=pass
3718 08:35:03.350275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass>
3719 08:35:03.351179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_23 RESULT=pass
3721 08:35:03.402908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass>
3722 08:35:03.403591 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_22 RESULT=pass
3724 08:35:03.455772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass>
3725 08:35:03.456485 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_22 RESULT=pass
3727 08:35:03.503581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass>
3728 08:35:03.504291 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_22 RESULT=pass
3730 08:35:03.558712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass>
3731 08:35:03.559760 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_22 RESULT=pass
3733 08:35:03.612234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass>
3734 08:35:03.612891 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_22 RESULT=pass
3736 08:35:03.657541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass>
3737 08:35:03.658189 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_22 RESULT=pass
3739 08:35:03.703470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass>
3740 08:35:03.704116 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_22 RESULT=pass
3742 08:35:03.751695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass>
3743 08:35:03.752326 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_21 RESULT=pass
3745 08:35:03.802728 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass>
3746 08:35:03.803410 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_21 RESULT=pass
3748 08:35:03.854746 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass>
3749 08:35:03.855597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_21 RESULT=pass
3751 08:35:03.908182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass>
3752 08:35:03.908845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_21 RESULT=pass
3754 08:35:03.955916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass>
3755 08:35:03.956795 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_21 RESULT=pass
3757 08:35:04.011207 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass>
3758 08:35:04.012049 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_21 RESULT=pass
3760 08:35:04.057721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass>
3761 08:35:04.058544 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_21 RESULT=pass
3763 08:35:04.114574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass>
3764 08:35:04.115215 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_20 RESULT=pass
3766 08:35:04.168526 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass>
3767 08:35:04.169173 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_20 RESULT=pass
3769 08:35:04.218393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass>
3770 08:35:04.219045 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_20 RESULT=pass
3772 08:35:04.265463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass>
3773 08:35:04.266069 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_20 RESULT=pass
3775 08:35:04.315977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass>
3776 08:35:04.316646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_20 RESULT=pass
3778 08:35:04.368630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass>
3779 08:35:04.369666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_20 RESULT=pass
3781 08:35:04.419358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass>
3782 08:35:04.420041 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_20 RESULT=pass
3784 08:35:04.467939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass>
3785 08:35:04.468627 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_19 RESULT=pass
3787 08:35:04.517104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass>
3788 08:35:04.517738 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_19 RESULT=pass
3790 08:35:04.561588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass>
3791 08:35:04.562233 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_19 RESULT=pass
3793 08:35:04.613379 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass>
3794 08:35:04.614114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_19 RESULT=pass
3796 08:35:04.671552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass>
3797 08:35:04.672322 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_19 RESULT=pass
3799 08:35:04.717958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass>
3800 08:35:04.718605 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_19 RESULT=pass
3802 08:35:04.772674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass>
3803 08:35:04.773544 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_19 RESULT=pass
3805 08:35:04.825457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass>
3806 08:35:04.826401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_18 RESULT=pass
3808 08:35:04.869366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass>
3809 08:35:04.870027 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_18 RESULT=pass
3811 08:35:04.927743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass>
3812 08:35:04.928428 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_18 RESULT=pass
3814 08:35:04.980427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass>
3815 08:35:04.981317 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_18 RESULT=pass
3817 08:35:05.037578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass>
3818 08:35:05.038478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_18 RESULT=pass
3820 08:35:05.085775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass>
3821 08:35:05.086625 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_18 RESULT=pass
3823 08:35:05.132583 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass>
3824 08:35:05.133225 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_18 RESULT=pass
3826 08:35:05.186084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass>
3827 08:35:05.186721 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_17 RESULT=pass
3829 08:35:05.233067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass>
3830 08:35:05.233710 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_17 RESULT=pass
3832 08:35:05.288969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass>
3833 08:35:05.289861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_17 RESULT=pass
3835 08:35:05.340761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass>
3836 08:35:05.341663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_17 RESULT=pass
3838 08:35:05.391429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass>
3839 08:35:05.392376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_17 RESULT=pass
3841 08:35:05.437836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass>
3842 08:35:05.438753 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_17 RESULT=pass
3844 08:35:05.484770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass>
3845 08:35:05.485622 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_17 RESULT=pass
3847 08:35:05.540994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass>
3848 08:35:05.541861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_16 RESULT=pass
3850 08:35:05.592357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass>
3851 08:35:05.593146 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_16 RESULT=pass
3853 08:35:05.642915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass>
3854 08:35:05.643678 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_16 RESULT=pass
3856 08:35:05.701394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass>
3857 08:35:05.702228 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_16 RESULT=pass
3859 08:35:05.749972 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass>
3860 08:35:05.750809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_16 RESULT=pass
3862 08:35:05.801571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass>
3863 08:35:05.802178 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_16 RESULT=pass
3865 08:35:05.859334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass>
3866 08:35:05.860034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_16 RESULT=pass
3868 08:35:05.915889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass>
3869 08:35:05.916581 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_15 RESULT=pass
3871 08:35:05.963596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass>
3872 08:35:05.964256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_15 RESULT=pass
3874 08:35:06.017145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass>
3875 08:35:06.017785 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_15 RESULT=pass
3877 08:35:06.066111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass>
3878 08:35:06.066769 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_15 RESULT=pass
3880 08:35:06.115396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass>
3881 08:35:06.116147 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_15 RESULT=pass
3883 08:35:06.162516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass>
3884 08:35:06.163714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_15 RESULT=pass
3886 08:35:06.220790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass>
3887 08:35:06.221448 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_15 RESULT=pass
3889 08:35:06.267587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass>
3890 08:35:06.268529 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_14 RESULT=pass
3892 08:35:06.323601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass>
3893 08:35:06.324257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_14 RESULT=pass
3895 08:35:06.372198 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass>
3896 08:35:06.372845 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_14 RESULT=pass
3898 08:35:06.422310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass>
3899 08:35:06.422960 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_14 RESULT=pass
3901 08:35:06.474342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass>
3902 08:35:06.475214 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_14 RESULT=pass
3904 08:35:06.523304 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass>
3905 08:35:06.524163 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_14 RESULT=pass
3907 08:35:06.564774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass>
3908 08:35:06.565611 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_14 RESULT=pass
3910 08:35:06.619069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass>
3911 08:35:06.619711 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_13 RESULT=pass
3913 08:35:06.669023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass>
3914 08:35:06.669642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_13 RESULT=pass
3916 08:35:06.720762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass>
3917 08:35:06.721384 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_13 RESULT=pass
3919 08:35:06.768088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass>
3920 08:35:06.768763 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_13 RESULT=pass
3922 08:35:06.813949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass>
3923 08:35:06.814605 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_13 RESULT=pass
3925 08:35:06.858996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass>
3926 08:35:06.859638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_13 RESULT=pass
3928 08:35:06.908064 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass>
3929 08:35:06.908692 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_13 RESULT=pass
3931 08:35:06.955558 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass>
3932 08:35:06.956160 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_12 RESULT=pass
3934 08:35:07.005730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass>
3935 08:35:07.006562 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_12 RESULT=pass
3937 08:35:07.052651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass>
3938 08:35:07.053288 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_12 RESULT=pass
3940 08:35:07.098245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass>
3941 08:35:07.098817 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_12 RESULT=pass
3943 08:35:07.153769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass>
3944 08:35:07.154371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_12 RESULT=pass
3946 08:35:07.206325 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass>
3947 08:35:07.207018 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_12 RESULT=pass
3949 08:35:07.253465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass>
3950 08:35:07.254048 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_12 RESULT=pass
3952 08:35:07.298914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass>
3953 08:35:07.299512 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_11 RESULT=pass
3955 08:35:07.351721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass>
3956 08:35:07.352347 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_11 RESULT=pass
3958 08:35:07.407698 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass>
3959 08:35:07.408319 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_11 RESULT=pass
3961 08:35:07.458052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass>
3962 08:35:07.458633 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_11 RESULT=pass
3964 08:35:07.510103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass>
3965 08:35:07.510715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_11 RESULT=pass
3967 08:35:07.554103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass>
3968 08:35:07.554705 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_11 RESULT=pass
3970 08:35:07.599729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass>
3971 08:35:07.600372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_11 RESULT=pass
3973 08:35:07.652468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass>
3974 08:35:07.653070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_10 RESULT=pass
3976 08:35:07.703900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass>
3977 08:35:07.704510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_10 RESULT=pass
3979 08:35:07.754191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass>
3980 08:35:07.754772 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_10 RESULT=pass
3982 08:35:07.808201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass>
3983 08:35:07.808922 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_10 RESULT=pass
3985 08:35:07.858614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass>
3986 08:35:07.859244 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_10 RESULT=pass
3988 08:35:07.910319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass>
3989 08:35:07.910931 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_10 RESULT=pass
3991 08:35:07.963495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass>
3992 08:35:07.964143 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_10 RESULT=pass
3994 08:35:08.007842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass>
3995 08:35:08.008685 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_9 RESULT=pass
3997 08:35:08.057878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass>
3998 08:35:08.058674 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_9 RESULT=pass
4000 08:35:08.105963 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass>
4001 08:35:08.106765 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_9 RESULT=pass
4003 08:35:08.156739 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass>
4004 08:35:08.157697 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_9 RESULT=pass
4006 08:35:08.208809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass>
4007 08:35:08.209426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_9 RESULT=pass
4009 08:35:08.262563 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass>
4010 08:35:08.263149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_9 RESULT=pass
4012 08:35:08.306650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass>
4013 08:35:08.307243 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_9 RESULT=pass
4015 08:35:08.358084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass>
4016 08:35:08.358675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_8 RESULT=pass
4018 08:35:08.410294 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass>
4019 08:35:08.410888 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_8 RESULT=pass
4021 08:35:08.455575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass>
4022 08:35:08.456160 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_8 RESULT=pass
4024 08:35:08.501141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass>
4025 08:35:08.501730 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_8 RESULT=pass
4027 08:35:08.552349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass>
4028 08:35:08.552945 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_8 RESULT=pass
4030 08:35:08.595858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass>
4031 08:35:08.596470 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_8 RESULT=pass
4033 08:35:08.650284 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass>
4034 08:35:08.650883 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_8 RESULT=pass
4036 08:35:08.693970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass>
4037 08:35:08.694554 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_7 RESULT=pass
4039 08:35:08.750823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass>
4040 08:35:08.751409 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_7 RESULT=pass
4042 08:35:08.795899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass>
4043 08:35:08.796673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_7 RESULT=pass
4045 08:35:08.851159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass>
4046 08:35:08.851927 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_7 RESULT=pass
4048 08:35:08.896897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass>
4049 08:35:08.897664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_7 RESULT=pass
4051 08:35:08.947175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass>
4052 08:35:08.947946 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_7 RESULT=pass
4054 08:35:08.998551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass>
4055 08:35:08.999352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_7 RESULT=pass
4057 08:35:09.039611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass>
4058 08:35:09.040418 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_6 RESULT=pass
4060 08:35:09.080671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass>
4061 08:35:09.081457 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_6 RESULT=pass
4063 08:35:09.140928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass>
4064 08:35:09.141736 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_6 RESULT=pass
4066 08:35:09.193801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass>
4067 08:35:09.194588 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_6 RESULT=pass
4069 08:35:09.250727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass>
4070 08:35:09.251539 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_6 RESULT=pass
4072 08:35:09.301736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass>
4073 08:35:09.302598 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_6 RESULT=pass
4075 08:35:09.345940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass>
4076 08:35:09.346712 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_6 RESULT=pass
4078 08:35:09.395452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass>
4079 08:35:09.396230 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_5 RESULT=pass
4081 08:35:09.454956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass>
4082 08:35:09.455719 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_5 RESULT=pass
4084 08:35:09.500091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass>
4085 08:35:09.500885 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_5 RESULT=pass
4087 08:35:09.556286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass>
4088 08:35:09.557058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_5 RESULT=pass
4090 08:35:09.609545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass>
4091 08:35:09.610333 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_5 RESULT=pass
4093 08:35:09.662581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass>
4094 08:35:09.663363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_5 RESULT=pass
4096 08:35:09.711250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass>
4097 08:35:09.712052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_5 RESULT=pass
4099 08:35:09.765590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass>
4100 08:35:09.766363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_4 RESULT=pass
4102 08:35:09.815061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass>
4103 08:35:09.815827 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_4 RESULT=pass
4105 08:35:09.877050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass>
4106 08:35:09.877823 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_4 RESULT=pass
4108 08:35:09.919041 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass>
4109 08:35:09.919815 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_4 RESULT=pass
4111 08:35:09.966409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass>
4112 08:35:09.967167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_4 RESULT=pass
4114 08:35:10.026582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass>
4115 08:35:10.027338 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_4 RESULT=pass
4117 08:35:10.070363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass>
4118 08:35:10.071127 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_4 RESULT=pass
4120 08:35:10.125554 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass>
4121 08:35:10.126334 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_3 RESULT=pass
4123 08:35:10.176679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass>
4124 08:35:10.177453 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_3 RESULT=pass
4126 08:35:10.227146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass>
4127 08:35:10.227910 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_3 RESULT=pass
4129 08:35:10.279088 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass>
4130 08:35:10.279855 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_3 RESULT=pass
4132 08:35:10.327726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass>
4133 08:35:10.328541 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_3 RESULT=pass
4135 08:35:10.386749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass>
4136 08:35:10.387512 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_3 RESULT=pass
4138 08:35:10.436253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass>
4139 08:35:10.437058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_3 RESULT=pass
4141 08:35:10.485906 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass>
4142 08:35:10.486725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_2 RESULT=pass
4144 08:35:10.539295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass>
4145 08:35:10.540098 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_2 RESULT=pass
4147 08:35:10.594811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass>
4148 08:35:10.595638 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_2 RESULT=pass
4150 08:35:10.645927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass>
4151 08:35:10.646729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_2 RESULT=pass
4153 08:35:10.701674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass>
4154 08:35:10.702514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_2 RESULT=pass
4156 08:35:10.763494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass>
4157 08:35:10.764339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_2 RESULT=pass
4159 08:35:10.819209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass>
4160 08:35:10.820040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_2 RESULT=pass
4162 08:35:10.873766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass>
4163 08:35:10.874579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_1 RESULT=pass
4165 08:35:10.922772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass>
4166 08:35:10.923565 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_1 RESULT=pass
4168 08:35:10.971642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass>
4169 08:35:10.972456 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_1 RESULT=pass
4171 08:35:11.022164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass>
4172 08:35:11.022943 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_1 RESULT=pass
4174 08:35:11.079922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass>
4175 08:35:11.080721 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_1 RESULT=pass
4177 08:35:11.135249 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass>
4178 08:35:11.136064 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_1 RESULT=pass
4180 08:35:11.191200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass>
4181 08:35:11.191965 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_1 RESULT=pass
4183 08:35:11.246078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass>
4184 08:35:11.246837 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_LCALTA_0 RESULT=pass
4186 08:35:11.294752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass>
4187 08:35:11.295522 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_LCALTA_0 RESULT=pass
4189 08:35:11.344283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass>
4190 08:35:11.345068 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_LCALTA_0 RESULT=pass
4192 08:35:11.387876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass>
4193 08:35:11.388503 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_LCALTA_0 RESULT=pass
4195 08:35:11.443037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass>
4196 08:35:11.443630 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_LCALTA_0 RESULT=pass
4198 08:35:11.497233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass>
4199 08:35:11.497859 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_LCALTA_0 RESULT=pass
4201 08:35:11.552375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass>
4202 08:35:11.552985 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_LCALTA_0 RESULT=pass
4204 08:35:11.596808 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
4206 08:35:11.599693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
4207 08:35:11.652213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip>
4208 08:35:11.652831 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE RESULT=skip
4210 08:35:11.702080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip>
4211 08:35:11.702695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE RESULT=skip
4213 08:35:11.765128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip>
4214 08:35:11.765962 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE RESULT=skip
4216 08:35:11.814600 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip>
4217 08:35:11.815385 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE RESULT=skip
4219 08:35:11.871901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip>
4220 08:35:11.872700 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE RESULT=skip
4222 08:35:11.930803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip>
4223 08:35:11.931558 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE RESULT=skip
4225 08:35:11.980824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip>
4226 08:35:11.981571 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE RESULT=skip
4228 08:35:12.031353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip>
4229 08:35:12.032103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE RESULT=skip
4231 08:35:12.079701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip>
4232 08:35:12.080489 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE RESULT=skip
4234 08:35:12.130552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip>
4235 08:35:12.131318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE RESULT=skip
4237 08:35:12.182357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip>
4238 08:35:12.183108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE RESULT=skip
4240 08:35:12.231666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip>
4241 08:35:12.232440 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE RESULT=skip
4243 08:35:12.284812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip>
4244 08:35:12.285548 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE RESULT=skip
4246 08:35:12.338715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip>
4247 08:35:12.339453 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE RESULT=skip
4249 08:35:12.391929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip>
4250 08:35:12.392706 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE RESULT=skip
4252 08:35:12.444494 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip>
4253 08:35:12.445232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE RESULT=skip
4255 08:35:12.495853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip>
4256 08:35:12.496687 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE RESULT=skip
4258 08:35:12.543383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip>
4259 08:35:12.544177 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE RESULT=skip
4261 08:35:12.602417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip>
4262 08:35:12.603206 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE RESULT=skip
4264 08:35:12.654283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip>
4265 08:35:12.655073 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE RESULT=skip
4267 08:35:12.714839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip>
4268 08:35:12.715627 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE RESULT=skip
4270 08:35:12.765533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip>
4271 08:35:12.766319 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK RESULT=skip
4273 08:35:12.814723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip>
4274 08:35:12.815514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK RESULT=skip
4276 08:35:12.871657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip>
4277 08:35:12.872477 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK RESULT=skip
4279 08:35:12.934793 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip>
4280 08:35:12.935589 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK RESULT=skip
4282 08:35:12.984521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip>
4283 08:35:12.985306 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK RESULT=skip
4285 08:35:13.032970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip>
4286 08:35:13.033838 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK RESULT=skip
4288 08:35:13.088510 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip>
4289 08:35:13.089321 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK RESULT=skip
4291 08:35:13.139639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip>
4292 08:35:13.140538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK RESULT=skip
4294 08:35:13.183166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip>
4295 08:35:13.184050 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK RESULT=skip
4297 08:35:13.239850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip>
4298 08:35:13.240707 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK RESULT=skip
4300 08:35:13.293628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip>
4301 08:35:13.294397 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK RESULT=skip
4303 08:35:13.347309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip>
4304 08:35:13.348081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK RESULT=skip
4306 08:35:13.398674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip>
4307 08:35:13.399452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK RESULT=skip
4309 08:35:13.450162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip>
4310 08:35:13.451048 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK RESULT=skip
4312 08:35:13.504117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip>
4313 08:35:13.504893 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK RESULT=skip
4315 08:35:13.545634 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip>
4316 08:35:13.546383 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK RESULT=skip
4318 08:35:13.601750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip>
4319 08:35:13.602684 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK RESULT=skip
4321 08:35:13.650354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip>
4322 08:35:13.651103 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK RESULT=skip
4324 08:35:13.702030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip>
4325 08:35:13.702805 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK RESULT=skip
4327 08:35:13.754446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip>
4328 08:35:13.755205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK RESULT=skip
4330 08:35:13.810313 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip>
4331 08:35:13.811058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK RESULT=skip
4333 08:35:13.859805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_pcm-test RESULT=pass>
4334 08:35:13.860604 Received signal: <TESTCASE> TEST_CASE_ID=alsa_pcm-test RESULT=pass
4336 08:35:13.923424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4337 08:35:13.924263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4339 08:35:13.974312 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4340 08:35:13.975107 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4342 08:35:14.023447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4343 08:35:14.024295 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4345 08:35:14.080716 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4346 08:35:14.081513 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4348 08:35:14.134598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip>
4349 08:35:14.135409 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded RESULT=skip
4351 08:35:14.183080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass>
4352 08:35:14.183880 Received signal: <TESTCASE> TEST_CASE_ID=alsa_test-pcmtest-driver RESULT=pass
4354 08:35:14.230452 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass>
4355 08:35:14.231280 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_global_wrong_timers_test RESULT=pass
4357 08:35:14.282894 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail>
4358 08:35:14.283734 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test_timer_f_utimer RESULT=fail
4360 08:35:14.329668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_utimer-test RESULT=fail
4362 08:35:14.334949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_utimer-test RESULT=fail>
4363 08:35:14.335425 + set +x
4364 08:35:14.340906 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 933468_1.6.2.4.5>
4365 08:35:14.341367 <LAVA_TEST_RUNNER EXIT>
4366 08:35:14.342001 Received signal: <ENDRUN> 1_kselftest-alsa 933468_1.6.2.4.5
4367 08:35:14.342435 Ending use of test pattern.
4368 08:35:14.342823 Ending test lava.1_kselftest-alsa (933468_1.6.2.4.5), duration 41.14
4370 08:35:14.344345 ok: lava_test_shell seems to have completed
4371 08:35:14.366490 alsa_mixer-test: pass
alsa_mixer-test_event_missing_LCALTA_0: pass
alsa_mixer-test_event_missing_LCALTA_1: pass
alsa_mixer-test_event_missing_LCALTA_10: pass
alsa_mixer-test_event_missing_LCALTA_11: pass
alsa_mixer-test_event_missing_LCALTA_12: pass
alsa_mixer-test_event_missing_LCALTA_13: pass
alsa_mixer-test_event_missing_LCALTA_14: pass
alsa_mixer-test_event_missing_LCALTA_15: pass
alsa_mixer-test_event_missing_LCALTA_16: pass
alsa_mixer-test_event_missing_LCALTA_17: pass
alsa_mixer-test_event_missing_LCALTA_18: pass
alsa_mixer-test_event_missing_LCALTA_19: pass
alsa_mixer-test_event_missing_LCALTA_2: pass
alsa_mixer-test_event_missing_LCALTA_20: pass
alsa_mixer-test_event_missing_LCALTA_21: pass
alsa_mixer-test_event_missing_LCALTA_22: pass
alsa_mixer-test_event_missing_LCALTA_23: pass
alsa_mixer-test_event_missing_LCALTA_24: pass
alsa_mixer-test_event_missing_LCALTA_25: pass
alsa_mixer-test_event_missing_LCALTA_26: pass
alsa_mixer-test_event_missing_LCALTA_27: pass
alsa_mixer-test_event_missing_LCALTA_28: pass
alsa_mixer-test_event_missing_LCALTA_29: pass
alsa_mixer-test_event_missing_LCALTA_3: pass
alsa_mixer-test_event_missing_LCALTA_30: pass
alsa_mixer-test_event_missing_LCALTA_31: pass
alsa_mixer-test_event_missing_LCALTA_32: pass
alsa_mixer-test_event_missing_LCALTA_33: pass
alsa_mixer-test_event_missing_LCALTA_34: pass
alsa_mixer-test_event_missing_LCALTA_35: pass
alsa_mixer-test_event_missing_LCALTA_36: pass
alsa_mixer-test_event_missing_LCALTA_37: pass
alsa_mixer-test_event_missing_LCALTA_38: pass
alsa_mixer-test_event_missing_LCALTA_39: pass
alsa_mixer-test_event_missing_LCALTA_4: pass
alsa_mixer-test_event_missing_LCALTA_40: pass
alsa_mixer-test_event_missing_LCALTA_41: pass
alsa_mixer-test_event_missing_LCALTA_42: pass
alsa_mixer-test_event_missing_LCALTA_43: pass
alsa_mixer-test_event_missing_LCALTA_44: pass
alsa_mixer-test_event_missing_LCALTA_45: pass
alsa_mixer-test_event_missing_LCALTA_46: pass
alsa_mixer-test_event_missing_LCALTA_47: pass
alsa_mixer-test_event_missing_LCALTA_48: pass
alsa_mixer-test_event_missing_LCALTA_49: pass
alsa_mixer-test_event_missing_LCALTA_5: pass
alsa_mixer-test_event_missing_LCALTA_50: pass
alsa_mixer-test_event_missing_LCALTA_51: pass
alsa_mixer-test_event_missing_LCALTA_52: pass
alsa_mixer-test_event_missing_LCALTA_53: pass
alsa_mixer-test_event_missing_LCALTA_54: pass
alsa_mixer-test_event_missing_LCALTA_55: pass
alsa_mixer-test_event_missing_LCALTA_56: pass
alsa_mixer-test_event_missing_LCALTA_57: pass
alsa_mixer-test_event_missing_LCALTA_58: pass
alsa_mixer-test_event_missing_LCALTA_59: pass
alsa_mixer-test_event_missing_LCALTA_6: pass
alsa_mixer-test_event_missing_LCALTA_60: pass
alsa_mixer-test_event_missing_LCALTA_7: pass
alsa_mixer-test_event_missing_LCALTA_8: pass
alsa_mixer-test_event_missing_LCALTA_9: pass
alsa_mixer-test_event_spurious_LCALTA_0: pass
alsa_mixer-test_event_spurious_LCALTA_1: pass
alsa_mixer-test_event_spurious_LCALTA_10: pass
alsa_mixer-test_event_spurious_LCALTA_11: pass
alsa_mixer-test_event_spurious_LCALTA_12: pass
alsa_mixer-test_event_spurious_LCALTA_13: pass
alsa_mixer-test_event_spurious_LCALTA_14: pass
alsa_mixer-test_event_spurious_LCALTA_15: pass
alsa_mixer-test_event_spurious_LCALTA_16: pass
alsa_mixer-test_event_spurious_LCALTA_17: pass
alsa_mixer-test_event_spurious_LCALTA_18: pass
alsa_mixer-test_event_spurious_LCALTA_19: pass
alsa_mixer-test_event_spurious_LCALTA_2: pass
alsa_mixer-test_event_spurious_LCALTA_20: pass
alsa_mixer-test_event_spurious_LCALTA_21: pass
alsa_mixer-test_event_spurious_LCALTA_22: pass
alsa_mixer-test_event_spurious_LCALTA_23: pass
alsa_mixer-test_event_spurious_LCALTA_24: pass
alsa_mixer-test_event_spurious_LCALTA_25: pass
alsa_mixer-test_event_spurious_LCALTA_26: pass
alsa_mixer-test_event_spurious_LCALTA_27: pass
alsa_mixer-test_event_spurious_LCALTA_28: pass
alsa_mixer-test_event_spurious_LCALTA_29: pass
alsa_mixer-test_event_spurious_LCALTA_3: pass
alsa_mixer-test_event_spurious_LCALTA_30: pass
alsa_mixer-test_event_spurious_LCALTA_31: pass
alsa_mixer-test_event_spurious_LCALTA_32: pass
alsa_mixer-test_event_spurious_LCALTA_33: pass
alsa_mixer-test_event_spurious_LCALTA_34: pass
alsa_mixer-test_event_spurious_LCALTA_35: pass
alsa_mixer-test_event_spurious_LCALTA_36: pass
alsa_mixer-test_event_spurious_LCALTA_37: pass
alsa_mixer-test_event_spurious_LCALTA_38: pass
alsa_mixer-test_event_spurious_LCALTA_39: pass
alsa_mixer-test_event_spurious_LCALTA_4: pass
alsa_mixer-test_event_spurious_LCALTA_40: pass
alsa_mixer-test_event_spurious_LCALTA_41: pass
alsa_mixer-test_event_spurious_LCALTA_42: pass
alsa_mixer-test_event_spurious_LCALTA_43: pass
alsa_mixer-test_event_spurious_LCALTA_44: pass
alsa_mixer-test_event_spurious_LCALTA_45: pass
alsa_mixer-test_event_spurious_LCALTA_46: pass
alsa_mixer-test_event_spurious_LCALTA_47: pass
alsa_mixer-test_event_spurious_LCALTA_48: pass
alsa_mixer-test_event_spurious_LCALTA_49: pass
alsa_mixer-test_event_spurious_LCALTA_5: pass
alsa_mixer-test_event_spurious_LCALTA_50: pass
alsa_mixer-test_event_spurious_LCALTA_51: pass
alsa_mixer-test_event_spurious_LCALTA_52: pass
alsa_mixer-test_event_spurious_LCALTA_53: pass
alsa_mixer-test_event_spurious_LCALTA_54: pass
alsa_mixer-test_event_spurious_LCALTA_55: pass
alsa_mixer-test_event_spurious_LCALTA_56: pass
alsa_mixer-test_event_spurious_LCALTA_57: pass
alsa_mixer-test_event_spurious_LCALTA_58: pass
alsa_mixer-test_event_spurious_LCALTA_59: pass
alsa_mixer-test_event_spurious_LCALTA_6: pass
alsa_mixer-test_event_spurious_LCALTA_60: pass
alsa_mixer-test_event_spurious_LCALTA_7: pass
alsa_mixer-test_event_spurious_LCALTA_8: pass
alsa_mixer-test_event_spurious_LCALTA_9: pass
alsa_mixer-test_get_value_LCALTA_0: pass
alsa_mixer-test_get_value_LCALTA_1: pass
alsa_mixer-test_get_value_LCALTA_10: pass
alsa_mixer-test_get_value_LCALTA_11: pass
alsa_mixer-test_get_value_LCALTA_12: pass
alsa_mixer-test_get_value_LCALTA_13: pass
alsa_mixer-test_get_value_LCALTA_14: pass
alsa_mixer-test_get_value_LCALTA_15: pass
alsa_mixer-test_get_value_LCALTA_16: pass
alsa_mixer-test_get_value_LCALTA_17: pass
alsa_mixer-test_get_value_LCALTA_18: pass
alsa_mixer-test_get_value_LCALTA_19: pass
alsa_mixer-test_get_value_LCALTA_2: pass
alsa_mixer-test_get_value_LCALTA_20: pass
alsa_mixer-test_get_value_LCALTA_21: pass
alsa_mixer-test_get_value_LCALTA_22: pass
alsa_mixer-test_get_value_LCALTA_23: pass
alsa_mixer-test_get_value_LCALTA_24: pass
alsa_mixer-test_get_value_LCALTA_25: pass
alsa_mixer-test_get_value_LCALTA_26: pass
alsa_mixer-test_get_value_LCALTA_27: pass
alsa_mixer-test_get_value_LCALTA_28: pass
alsa_mixer-test_get_value_LCALTA_29: pass
alsa_mixer-test_get_value_LCALTA_3: pass
alsa_mixer-test_get_value_LCALTA_30: pass
alsa_mixer-test_get_value_LCALTA_31: pass
alsa_mixer-test_get_value_LCALTA_32: pass
alsa_mixer-test_get_value_LCALTA_33: pass
alsa_mixer-test_get_value_LCALTA_34: pass
alsa_mixer-test_get_value_LCALTA_35: pass
alsa_mixer-test_get_value_LCALTA_36: pass
alsa_mixer-test_get_value_LCALTA_37: pass
alsa_mixer-test_get_value_LCALTA_38: pass
alsa_mixer-test_get_value_LCALTA_39: pass
alsa_mixer-test_get_value_LCALTA_4: pass
alsa_mixer-test_get_value_LCALTA_40: pass
alsa_mixer-test_get_value_LCALTA_41: pass
alsa_mixer-test_get_value_LCALTA_42: pass
alsa_mixer-test_get_value_LCALTA_43: pass
alsa_mixer-test_get_value_LCALTA_44: pass
alsa_mixer-test_get_value_LCALTA_45: pass
alsa_mixer-test_get_value_LCALTA_46: pass
alsa_mixer-test_get_value_LCALTA_47: pass
alsa_mixer-test_get_value_LCALTA_48: pass
alsa_mixer-test_get_value_LCALTA_49: pass
alsa_mixer-test_get_value_LCALTA_5: pass
alsa_mixer-test_get_value_LCALTA_50: pass
alsa_mixer-test_get_value_LCALTA_51: pass
alsa_mixer-test_get_value_LCALTA_52: pass
alsa_mixer-test_get_value_LCALTA_53: pass
alsa_mixer-test_get_value_LCALTA_54: pass
alsa_mixer-test_get_value_LCALTA_55: pass
alsa_mixer-test_get_value_LCALTA_56: pass
alsa_mixer-test_get_value_LCALTA_57: pass
alsa_mixer-test_get_value_LCALTA_58: pass
alsa_mixer-test_get_value_LCALTA_59: pass
alsa_mixer-test_get_value_LCALTA_6: pass
alsa_mixer-test_get_value_LCALTA_60: pass
alsa_mixer-test_get_value_LCALTA_7: pass
alsa_mixer-test_get_value_LCALTA_8: pass
alsa_mixer-test_get_value_LCALTA_9: pass
alsa_mixer-test_name_LCALTA_0: pass
alsa_mixer-test_name_LCALTA_1: pass
alsa_mixer-test_name_LCALTA_10: pass
alsa_mixer-test_name_LCALTA_11: pass
alsa_mixer-test_name_LCALTA_12: pass
alsa_mixer-test_name_LCALTA_13: pass
alsa_mixer-test_name_LCALTA_14: pass
alsa_mixer-test_name_LCALTA_15: pass
alsa_mixer-test_name_LCALTA_16: pass
alsa_mixer-test_name_LCALTA_17: pass
alsa_mixer-test_name_LCALTA_18: pass
alsa_mixer-test_name_LCALTA_19: pass
alsa_mixer-test_name_LCALTA_2: pass
alsa_mixer-test_name_LCALTA_20: pass
alsa_mixer-test_name_LCALTA_21: pass
alsa_mixer-test_name_LCALTA_22: pass
alsa_mixer-test_name_LCALTA_23: pass
alsa_mixer-test_name_LCALTA_24: pass
alsa_mixer-test_name_LCALTA_25: pass
alsa_mixer-test_name_LCALTA_26: pass
alsa_mixer-test_name_LCALTA_27: pass
alsa_mixer-test_name_LCALTA_28: pass
alsa_mixer-test_name_LCALTA_29: pass
alsa_mixer-test_name_LCALTA_3: pass
alsa_mixer-test_name_LCALTA_30: pass
alsa_mixer-test_name_LCALTA_31: pass
alsa_mixer-test_name_LCALTA_32: pass
alsa_mixer-test_name_LCALTA_33: pass
alsa_mixer-test_name_LCALTA_34: pass
alsa_mixer-test_name_LCALTA_35: pass
alsa_mixer-test_name_LCALTA_36: pass
alsa_mixer-test_name_LCALTA_37: pass
alsa_mixer-test_name_LCALTA_38: pass
alsa_mixer-test_name_LCALTA_39: pass
alsa_mixer-test_name_LCALTA_4: pass
alsa_mixer-test_name_LCALTA_40: pass
alsa_mixer-test_name_LCALTA_41: pass
alsa_mixer-test_name_LCALTA_42: pass
alsa_mixer-test_name_LCALTA_43: pass
alsa_mixer-test_name_LCALTA_44: pass
alsa_mixer-test_name_LCALTA_45: pass
alsa_mixer-test_name_LCALTA_46: pass
alsa_mixer-test_name_LCALTA_47: pass
alsa_mixer-test_name_LCALTA_48: pass
alsa_mixer-test_name_LCALTA_49: pass
alsa_mixer-test_name_LCALTA_5: pass
alsa_mixer-test_name_LCALTA_50: pass
alsa_mixer-test_name_LCALTA_51: pass
alsa_mixer-test_name_LCALTA_52: pass
alsa_mixer-test_name_LCALTA_53: pass
alsa_mixer-test_name_LCALTA_54: pass
alsa_mixer-test_name_LCALTA_55: pass
alsa_mixer-test_name_LCALTA_56: pass
alsa_mixer-test_name_LCALTA_57: pass
alsa_mixer-test_name_LCALTA_58: pass
alsa_mixer-test_name_LCALTA_59: pass
alsa_mixer-test_name_LCALTA_6: pass
alsa_mixer-test_name_LCALTA_60: pass
alsa_mixer-test_name_LCALTA_7: pass
alsa_mixer-test_name_LCALTA_8: pass
alsa_mixer-test_name_LCALTA_9: pass
alsa_mixer-test_write_default_LCALTA_0: pass
alsa_mixer-test_write_default_LCALTA_1: pass
alsa_mixer-test_write_default_LCALTA_10: pass
alsa_mixer-test_write_default_LCALTA_11: pass
alsa_mixer-test_write_default_LCALTA_12: pass
alsa_mixer-test_write_default_LCALTA_13: pass
alsa_mixer-test_write_default_LCALTA_14: pass
alsa_mixer-test_write_default_LCALTA_15: pass
alsa_mixer-test_write_default_LCALTA_16: pass
alsa_mixer-test_write_default_LCALTA_17: pass
alsa_mixer-test_write_default_LCALTA_18: pass
alsa_mixer-test_write_default_LCALTA_19: pass
alsa_mixer-test_write_default_LCALTA_2: pass
alsa_mixer-test_write_default_LCALTA_20: pass
alsa_mixer-test_write_default_LCALTA_21: pass
alsa_mixer-test_write_default_LCALTA_22: pass
alsa_mixer-test_write_default_LCALTA_23: skip
alsa_mixer-test_write_default_LCALTA_24: skip
alsa_mixer-test_write_default_LCALTA_25: pass
alsa_mixer-test_write_default_LCALTA_26: skip
alsa_mixer-test_write_default_LCALTA_27: pass
alsa_mixer-test_write_default_LCALTA_28: pass
alsa_mixer-test_write_default_LCALTA_29: pass
alsa_mixer-test_write_default_LCALTA_3: pass
alsa_mixer-test_write_default_LCALTA_30: pass
alsa_mixer-test_write_default_LCALTA_31: pass
alsa_mixer-test_write_default_LCALTA_32: pass
alsa_mixer-test_write_default_LCALTA_33: pass
alsa_mixer-test_write_default_LCALTA_34: pass
alsa_mixer-test_write_default_LCALTA_35: pass
alsa_mixer-test_write_default_LCALTA_36: pass
alsa_mixer-test_write_default_LCALTA_37: pass
alsa_mixer-test_write_default_LCALTA_38: pass
alsa_mixer-test_write_default_LCALTA_39: pass
alsa_mixer-test_write_default_LCALTA_4: pass
alsa_mixer-test_write_default_LCALTA_40: pass
alsa_mixer-test_write_default_LCALTA_41: pass
alsa_mixer-test_write_default_LCALTA_42: pass
alsa_mixer-test_write_default_LCALTA_43: pass
alsa_mixer-test_write_default_LCALTA_44: pass
alsa_mixer-test_write_default_LCALTA_45: pass
alsa_mixer-test_write_default_LCALTA_46: pass
alsa_mixer-test_write_default_LCALTA_47: pass
alsa_mixer-test_write_default_LCALTA_48: pass
alsa_mixer-test_write_default_LCALTA_49: pass
alsa_mixer-test_write_default_LCALTA_5: pass
alsa_mixer-test_write_default_LCALTA_50: pass
alsa_mixer-test_write_default_LCALTA_51: pass
alsa_mixer-test_write_default_LCALTA_52: pass
alsa_mixer-test_write_default_LCALTA_53: pass
alsa_mixer-test_write_default_LCALTA_54: pass
alsa_mixer-test_write_default_LCALTA_55: pass
alsa_mixer-test_write_default_LCALTA_56: pass
alsa_mixer-test_write_default_LCALTA_57: pass
alsa_mixer-test_write_default_LCALTA_58: pass
alsa_mixer-test_write_default_LCALTA_59: pass
alsa_mixer-test_write_default_LCALTA_6: pass
alsa_mixer-test_write_default_LCALTA_60: pass
alsa_mixer-test_write_default_LCALTA_7: pass
alsa_mixer-test_write_default_LCALTA_8: pass
alsa_mixer-test_write_default_LCALTA_9: pass
alsa_mixer-test_write_invalid_LCALTA_0: pass
alsa_mixer-test_write_invalid_LCALTA_1: pass
alsa_mixer-test_write_invalid_LCALTA_10: pass
alsa_mixer-test_write_invalid_LCALTA_11: pass
alsa_mixer-test_write_invalid_LCALTA_12: pass
alsa_mixer-test_write_invalid_LCALTA_13: pass
alsa_mixer-test_write_invalid_LCALTA_14: pass
alsa_mixer-test_write_invalid_LCALTA_15: pass
alsa_mixer-test_write_invalid_LCALTA_16: pass
alsa_mixer-test_write_invalid_LCALTA_17: pass
alsa_mixer-test_write_invalid_LCALTA_18: pass
alsa_mixer-test_write_invalid_LCALTA_19: pass
alsa_mixer-test_write_invalid_LCALTA_2: pass
alsa_mixer-test_write_invalid_LCALTA_20: pass
alsa_mixer-test_write_invalid_LCALTA_21: pass
alsa_mixer-test_write_invalid_LCALTA_22: pass
alsa_mixer-test_write_invalid_LCALTA_23: skip
alsa_mixer-test_write_invalid_LCALTA_24: skip
alsa_mixer-test_write_invalid_LCALTA_25: skip
alsa_mixer-test_write_invalid_LCALTA_26: skip
alsa_mixer-test_write_invalid_LCALTA_27: pass
alsa_mixer-test_write_invalid_LCALTA_28: pass
alsa_mixer-test_write_invalid_LCALTA_29: pass
alsa_mixer-test_write_invalid_LCALTA_3: pass
alsa_mixer-test_write_invalid_LCALTA_30: pass
alsa_mixer-test_write_invalid_LCALTA_31: pass
alsa_mixer-test_write_invalid_LCALTA_32: pass
alsa_mixer-test_write_invalid_LCALTA_33: pass
alsa_mixer-test_write_invalid_LCALTA_34: pass
alsa_mixer-test_write_invalid_LCALTA_35: pass
alsa_mixer-test_write_invalid_LCALTA_36: pass
alsa_mixer-test_write_invalid_LCALTA_37: pass
alsa_mixer-test_write_invalid_LCALTA_38: pass
alsa_mixer-test_write_invalid_LCALTA_39: pass
alsa_mixer-test_write_invalid_LCALTA_4: pass
alsa_mixer-test_write_invalid_LCALTA_40: pass
alsa_mixer-test_write_invalid_LCALTA_41: pass
alsa_mixer-test_write_invalid_LCALTA_42: pass
alsa_mixer-test_write_invalid_LCALTA_43: pass
alsa_mixer-test_write_invalid_LCALTA_44: pass
alsa_mixer-test_write_invalid_LCALTA_45: pass
alsa_mixer-test_write_invalid_LCALTA_46: pass
alsa_mixer-test_write_invalid_LCALTA_47: pass
alsa_mixer-test_write_invalid_LCALTA_48: pass
alsa_mixer-test_write_invalid_LCALTA_49: pass
alsa_mixer-test_write_invalid_LCALTA_5: pass
alsa_mixer-test_write_invalid_LCALTA_50: pass
alsa_mixer-test_write_invalid_LCALTA_51: pass
alsa_mixer-test_write_invalid_LCALTA_52: pass
alsa_mixer-test_write_invalid_LCALTA_53: pass
alsa_mixer-test_write_invalid_LCALTA_54: pass
alsa_mixer-test_write_invalid_LCALTA_55: pass
alsa_mixer-test_write_invalid_LCALTA_56: pass
alsa_mixer-test_write_invalid_LCALTA_57: pass
alsa_mixer-test_write_invalid_LCALTA_58: pass
alsa_mixer-test_write_invalid_LCALTA_59: pass
alsa_mixer-test_write_invalid_LCALTA_6: pass
alsa_mixer-test_write_invalid_LCALTA_60: pass
alsa_mixer-test_write_invalid_LCALTA_7: pass
alsa_mixer-test_write_invalid_LCALTA_8: pass
alsa_mixer-test_write_invalid_LCALTA_9: pass
alsa_mixer-test_write_valid_LCALTA_0: pass
alsa_mixer-test_write_valid_LCALTA_1: pass
alsa_mixer-test_write_valid_LCALTA_10: pass
alsa_mixer-test_write_valid_LCALTA_11: pass
alsa_mixer-test_write_valid_LCALTA_12: pass
alsa_mixer-test_write_valid_LCALTA_13: pass
alsa_mixer-test_write_valid_LCALTA_14: pass
alsa_mixer-test_write_valid_LCALTA_15: pass
alsa_mixer-test_write_valid_LCALTA_16: pass
alsa_mixer-test_write_valid_LCALTA_17: pass
alsa_mixer-test_write_valid_LCALTA_18: pass
alsa_mixer-test_write_valid_LCALTA_19: pass
alsa_mixer-test_write_valid_LCALTA_2: pass
alsa_mixer-test_write_valid_LCALTA_20: pass
alsa_mixer-test_write_valid_LCALTA_21: pass
alsa_mixer-test_write_valid_LCALTA_22: pass
alsa_mixer-test_write_valid_LCALTA_23: skip
alsa_mixer-test_write_valid_LCALTA_24: skip
alsa_mixer-test_write_valid_LCALTA_25: skip
alsa_mixer-test_write_valid_LCALTA_26: skip
alsa_mixer-test_write_valid_LCALTA_27: pass
alsa_mixer-test_write_valid_LCALTA_28: pass
alsa_mixer-test_write_valid_LCALTA_29: pass
alsa_mixer-test_write_valid_LCALTA_3: pass
alsa_mixer-test_write_valid_LCALTA_30: pass
alsa_mixer-test_write_valid_LCALTA_31: pass
alsa_mixer-test_write_valid_LCALTA_32: pass
alsa_mixer-test_write_valid_LCALTA_33: pass
alsa_mixer-test_write_valid_LCALTA_34: pass
alsa_mixer-test_write_valid_LCALTA_35: pass
alsa_mixer-test_write_valid_LCALTA_36: pass
alsa_mixer-test_write_valid_LCALTA_37: pass
alsa_mixer-test_write_valid_LCALTA_38: pass
alsa_mixer-test_write_valid_LCALTA_39: pass
alsa_mixer-test_write_valid_LCALTA_4: pass
alsa_mixer-test_write_valid_LCALTA_40: pass
alsa_mixer-test_write_valid_LCALTA_41: pass
alsa_mixer-test_write_valid_LCALTA_42: pass
alsa_mixer-test_write_valid_LCALTA_43: pass
alsa_mixer-test_write_valid_LCALTA_44: pass
alsa_mixer-test_write_valid_LCALTA_45: pass
alsa_mixer-test_write_valid_LCALTA_46: pass
alsa_mixer-test_write_valid_LCALTA_47: pass
alsa_mixer-test_write_valid_LCALTA_48: pass
alsa_mixer-test_write_valid_LCALTA_49: pass
alsa_mixer-test_write_valid_LCALTA_5: pass
alsa_mixer-test_write_valid_LCALTA_50: pass
alsa_mixer-test_write_valid_LCALTA_51: pass
alsa_mixer-test_write_valid_LCALTA_52: pass
alsa_mixer-test_write_valid_LCALTA_53: pass
alsa_mixer-test_write_valid_LCALTA_54: pass
alsa_mixer-test_write_valid_LCALTA_55: pass
alsa_mixer-test_write_valid_LCALTA_56: pass
alsa_mixer-test_write_valid_LCALTA_57: pass
alsa_mixer-test_write_valid_LCALTA_58: pass
alsa_mixer-test_write_valid_LCALTA_59: pass
alsa_mixer-test_write_valid_LCALTA_6: pass
alsa_mixer-test_write_valid_LCALTA_60: pass
alsa_mixer-test_write_valid_LCALTA_7: pass
alsa_mixer-test_write_valid_LCALTA_8: pass
alsa_mixer-test_write_valid_LCALTA_9: pass
alsa_pcm-test: pass
alsa_pcm-test_default_time1_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time1_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time1_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time2_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time2_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time3_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time3_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time4_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time4_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time5_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time5_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time6_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time6_LCALTA_5_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_0_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_1_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_2_0_PLAYBACK: skip
alsa_pcm-test_default_time7_LCALTA_3_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_4_0_CAPTURE: skip
alsa_pcm-test_default_time7_LCALTA_5_0_CAPTURE: skip
alsa_test-pcmtest-driver: pass
alsa_test-pcmtest-driver_pcmtest_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_capture_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_ni_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_playback_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_test-pcmtest-driver_pcmtest_reset_ioctl_Can_t_read_patterns_Probably_module_isn_t_loaded: skip
alsa_utimer-test: fail
alsa_utimer-test_global_wrong_timers_test: pass
alsa_utimer-test_timer_f_utimer: fail
shardfile-alsa: pass
4372 08:35:14.368221 end: 3.1 lava-test-shell (duration 00:00:42) [common]
4373 08:35:14.368765 end: 3 lava-test-retry (duration 00:00:42) [common]
4374 08:35:14.369302 start: 4 finalize (timeout 00:06:06) [common]
4375 08:35:14.369841 start: 4.1 power-off (timeout 00:00:30) [common]
4376 08:35:14.370746 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
4377 08:35:14.404794 >> OK - accepted request
4378 08:35:14.406635 Returned 0 in 0 seconds
4379 08:35:14.507743 end: 4.1 power-off (duration 00:00:00) [common]
4381 08:35:14.509392 start: 4.2 read-feedback (timeout 00:06:05) [common]
4382 08:35:14.510468 Listened to connection for namespace 'common' for up to 1s
4383 08:35:15.511278 Finalising connection for namespace 'common'
4384 08:35:15.512046 Disconnecting from shell: Finalise
4385 08:35:15.512591 / #
4386 08:35:15.613561 end: 4.2 read-feedback (duration 00:00:01) [common]
4387 08:35:15.614271 end: 4 finalize (duration 00:00:01) [common]
4388 08:35:15.614953 Cleaning after the job
4389 08:35:15.615559 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933468/tftp-deploy-8t0m58g2/ramdisk
4390 08:35:15.628572 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933468/tftp-deploy-8t0m58g2/kernel
4391 08:35:15.656550 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933468/tftp-deploy-8t0m58g2/dtb
4392 08:35:15.657943 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933468/tftp-deploy-8t0m58g2/nfsrootfs
4393 08:35:15.737183 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933468/tftp-deploy-8t0m58g2/modules
4394 08:35:15.743610 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/933468
4395 08:35:19.027358 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/933468
4396 08:35:19.027944 Job finished correctly