Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 08:41:28.428252 lava-dispatcher, installed at version: 2024.01
2 08:41:28.429115 start: 0 validate
3 08:41:28.429633 Start time: 2024-11-04 08:41:28.429601+00:00 (UTC)
4 08:41:28.430201 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 08:41:28.430789 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 08:41:28.473095 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 08:41:28.473658 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-328-gf46306bca74bb%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 08:41:28.507122 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 08:41:28.507780 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-328-gf46306bca74bb%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 08:41:28.538222 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 08:41:28.538755 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 08:41:28.583034 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 08:41:28.583557 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-328-gf46306bca74bb%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 08:41:28.619220 validate duration: 0.19
16 08:41:28.620061 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 08:41:28.620381 start: 1.1 download-retry (timeout 00:10:00) [common]
18 08:41:28.620684 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 08:41:28.621328 Not decompressing ramdisk as can be used compressed.
20 08:41:28.621775 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 08:41:28.622047 saving as /var/lib/lava/dispatcher/tmp/933547/tftp-deploy-afef1qp8/ramdisk/initrd.cpio.gz
22 08:41:28.622311 total size: 5628169 (5 MB)
23 08:41:28.662437 progress 0 % (0 MB)
24 08:41:28.670231 progress 5 % (0 MB)
25 08:41:28.678434 progress 10 % (0 MB)
26 08:41:28.683073 progress 15 % (0 MB)
27 08:41:28.687406 progress 20 % (1 MB)
28 08:41:28.691259 progress 25 % (1 MB)
29 08:41:28.695411 progress 30 % (1 MB)
30 08:41:28.699472 progress 35 % (1 MB)
31 08:41:28.703271 progress 40 % (2 MB)
32 08:41:28.707297 progress 45 % (2 MB)
33 08:41:28.711040 progress 50 % (2 MB)
34 08:41:28.715064 progress 55 % (2 MB)
35 08:41:28.719134 progress 60 % (3 MB)
36 08:41:28.722807 progress 65 % (3 MB)
37 08:41:28.726959 progress 70 % (3 MB)
38 08:41:28.730660 progress 75 % (4 MB)
39 08:41:28.734672 progress 80 % (4 MB)
40 08:41:28.738298 progress 85 % (4 MB)
41 08:41:28.742377 progress 90 % (4 MB)
42 08:41:28.746227 progress 95 % (5 MB)
43 08:41:28.749547 progress 100 % (5 MB)
44 08:41:28.750195 5 MB downloaded in 0.13 s (41.98 MB/s)
45 08:41:28.750718 end: 1.1.1 http-download (duration 00:00:00) [common]
47 08:41:28.751597 end: 1.1 download-retry (duration 00:00:00) [common]
48 08:41:28.751885 start: 1.2 download-retry (timeout 00:10:00) [common]
49 08:41:28.752185 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 08:41:28.752663 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-328-gf46306bca74bb/arm64/defconfig/gcc-12/kernel/Image
51 08:41:28.752903 saving as /var/lib/lava/dispatcher/tmp/933547/tftp-deploy-afef1qp8/kernel/Image
52 08:41:28.753114 total size: 45713920 (43 MB)
53 08:41:28.753326 No compression specified
54 08:41:28.787504 progress 0 % (0 MB)
55 08:41:28.816502 progress 5 % (2 MB)
56 08:41:28.844381 progress 10 % (4 MB)
57 08:41:28.872234 progress 15 % (6 MB)
58 08:41:28.900874 progress 20 % (8 MB)
59 08:41:28.929238 progress 25 % (10 MB)
60 08:41:28.958046 progress 30 % (13 MB)
61 08:41:28.985799 progress 35 % (15 MB)
62 08:41:29.014064 progress 40 % (17 MB)
63 08:41:29.042151 progress 45 % (19 MB)
64 08:41:29.070279 progress 50 % (21 MB)
65 08:41:29.099076 progress 55 % (24 MB)
66 08:41:29.127901 progress 60 % (26 MB)
67 08:41:29.156746 progress 65 % (28 MB)
68 08:41:29.185715 progress 70 % (30 MB)
69 08:41:29.214356 progress 75 % (32 MB)
70 08:41:29.244520 progress 80 % (34 MB)
71 08:41:29.275281 progress 85 % (37 MB)
72 08:41:29.303703 progress 90 % (39 MB)
73 08:41:29.332657 progress 95 % (41 MB)
74 08:41:29.361218 progress 100 % (43 MB)
75 08:41:29.361813 43 MB downloaded in 0.61 s (71.62 MB/s)
76 08:41:29.362297 end: 1.2.1 http-download (duration 00:00:01) [common]
78 08:41:29.363115 end: 1.2 download-retry (duration 00:00:01) [common]
79 08:41:29.363419 start: 1.3 download-retry (timeout 00:09:59) [common]
80 08:41:29.363729 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 08:41:29.364236 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-328-gf46306bca74bb/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 08:41:29.364550 saving as /var/lib/lava/dispatcher/tmp/933547/tftp-deploy-afef1qp8/dtb/meson-g12b-a311d-libretech-cc.dtb
83 08:41:29.364764 total size: 54703 (0 MB)
84 08:41:29.364974 No compression specified
85 08:41:29.403479 progress 59 % (0 MB)
86 08:41:29.404370 progress 100 % (0 MB)
87 08:41:29.404930 0 MB downloaded in 0.04 s (1.30 MB/s)
88 08:41:29.405399 end: 1.3.1 http-download (duration 00:00:00) [common]
90 08:41:29.406211 end: 1.3 download-retry (duration 00:00:00) [common]
91 08:41:29.406476 start: 1.4 download-retry (timeout 00:09:59) [common]
92 08:41:29.406741 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 08:41:29.407201 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 08:41:29.407445 saving as /var/lib/lava/dispatcher/tmp/933547/tftp-deploy-afef1qp8/nfsrootfs/full.rootfs.tar
95 08:41:29.407651 total size: 120894716 (115 MB)
96 08:41:29.407861 Using unxz to decompress xz
97 08:41:29.443724 progress 0 % (0 MB)
98 08:41:30.235149 progress 5 % (5 MB)
99 08:41:31.093792 progress 10 % (11 MB)
100 08:41:31.895575 progress 15 % (17 MB)
101 08:41:32.637951 progress 20 % (23 MB)
102 08:41:33.232041 progress 25 % (28 MB)
103 08:41:34.060145 progress 30 % (34 MB)
104 08:41:34.849469 progress 35 % (40 MB)
105 08:41:35.214656 progress 40 % (46 MB)
106 08:41:35.588036 progress 45 % (51 MB)
107 08:41:36.315569 progress 50 % (57 MB)
108 08:41:37.199247 progress 55 % (63 MB)
109 08:41:37.981068 progress 60 % (69 MB)
110 08:41:38.738676 progress 65 % (74 MB)
111 08:41:39.521027 progress 70 % (80 MB)
112 08:41:40.349138 progress 75 % (86 MB)
113 08:41:41.212392 progress 80 % (92 MB)
114 08:41:42.108411 progress 85 % (98 MB)
115 08:41:42.976024 progress 90 % (103 MB)
116 08:41:43.793336 progress 95 % (109 MB)
117 08:41:44.704714 progress 100 % (115 MB)
118 08:41:44.717343 115 MB downloaded in 15.31 s (7.53 MB/s)
119 08:41:44.718482 end: 1.4.1 http-download (duration 00:00:15) [common]
121 08:41:44.720355 end: 1.4 download-retry (duration 00:00:15) [common]
122 08:41:44.720935 start: 1.5 download-retry (timeout 00:09:44) [common]
123 08:41:44.721491 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 08:41:44.723629 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-328-gf46306bca74bb/arm64/defconfig/gcc-12/modules.tar.xz
125 08:41:44.724241 saving as /var/lib/lava/dispatcher/tmp/933547/tftp-deploy-afef1qp8/modules/modules.tar
126 08:41:44.724744 total size: 11614628 (11 MB)
127 08:41:44.725275 Using unxz to decompress xz
128 08:41:44.779052 progress 0 % (0 MB)
129 08:41:44.848972 progress 5 % (0 MB)
130 08:41:44.925600 progress 10 % (1 MB)
131 08:41:45.023236 progress 15 % (1 MB)
132 08:41:45.118544 progress 20 % (2 MB)
133 08:41:45.201336 progress 25 % (2 MB)
134 08:41:45.297809 progress 30 % (3 MB)
135 08:41:45.386387 progress 35 % (3 MB)
136 08:41:45.462060 progress 40 % (4 MB)
137 08:41:45.545023 progress 45 % (5 MB)
138 08:41:45.635748 progress 50 % (5 MB)
139 08:41:45.725452 progress 55 % (6 MB)
140 08:41:45.818692 progress 60 % (6 MB)
141 08:41:45.903824 progress 65 % (7 MB)
142 08:41:45.988888 progress 70 % (7 MB)
143 08:41:46.070064 progress 75 % (8 MB)
144 08:41:46.153910 progress 80 % (8 MB)
145 08:41:46.234341 progress 85 % (9 MB)
146 08:41:46.317650 progress 90 % (10 MB)
147 08:41:46.391486 progress 95 % (10 MB)
148 08:41:46.469083 progress 100 % (11 MB)
149 08:41:46.481258 11 MB downloaded in 1.76 s (6.31 MB/s)
150 08:41:46.482095 end: 1.5.1 http-download (duration 00:00:02) [common]
152 08:41:46.483949 end: 1.5 download-retry (duration 00:00:02) [common]
153 08:41:46.484625 start: 1.6 prepare-tftp-overlay (timeout 00:09:42) [common]
154 08:41:46.485225 start: 1.6.1 extract-nfsrootfs (timeout 00:09:42) [common]
155 08:42:04.315967 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/933547/extract-nfsrootfs-dknoix43
156 08:42:04.316599 end: 1.6.1 extract-nfsrootfs (duration 00:00:18) [common]
157 08:42:04.316921 start: 1.6.2 lava-overlay (timeout 00:09:24) [common]
158 08:42:04.317559 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86
159 08:42:04.318063 makedir: /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin
160 08:42:04.318475 makedir: /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/tests
161 08:42:04.318861 makedir: /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/results
162 08:42:04.319252 Creating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-add-keys
163 08:42:04.319802 Creating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-add-sources
164 08:42:04.320425 Creating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-background-process-start
165 08:42:04.320979 Creating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-background-process-stop
166 08:42:04.321499 Creating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-common-functions
167 08:42:04.321990 Creating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-echo-ipv4
168 08:42:04.322501 Creating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-install-packages
169 08:42:04.322985 Creating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-installed-packages
170 08:42:04.323458 Creating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-os-build
171 08:42:04.323935 Creating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-probe-channel
172 08:42:04.324450 Creating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-probe-ip
173 08:42:04.324936 Creating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-target-ip
174 08:42:04.325415 Creating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-target-mac
175 08:42:04.325908 Creating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-target-storage
176 08:42:04.326394 Creating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-test-case
177 08:42:04.326879 Creating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-test-event
178 08:42:04.327358 Creating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-test-feedback
179 08:42:04.327858 Creating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-test-raise
180 08:42:04.328376 Creating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-test-reference
181 08:42:04.328857 Creating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-test-runner
182 08:42:04.329341 Creating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-test-set
183 08:42:04.329825 Creating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-test-shell
184 08:42:04.330340 Updating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-add-keys (debian)
185 08:42:04.330936 Updating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-add-sources (debian)
186 08:42:04.331455 Updating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-install-packages (debian)
187 08:42:04.331971 Updating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-installed-packages (debian)
188 08:42:04.332522 Updating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/bin/lava-os-build (debian)
189 08:42:04.332974 Creating /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/environment
190 08:42:04.333354 LAVA metadata
191 08:42:04.333617 - LAVA_JOB_ID=933547
192 08:42:04.333833 - LAVA_DISPATCHER_IP=192.168.6.2
193 08:42:04.334212 start: 1.6.2.1 ssh-authorize (timeout 00:09:24) [common]
194 08:42:04.335209 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 08:42:04.335529 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:24) [common]
196 08:42:04.335736 skipped lava-vland-overlay
197 08:42:04.335974 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 08:42:04.336260 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:24) [common]
199 08:42:04.336480 skipped lava-multinode-overlay
200 08:42:04.336720 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 08:42:04.336969 start: 1.6.2.4 test-definition (timeout 00:09:24) [common]
202 08:42:04.337216 Loading test definitions
203 08:42:04.337492 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:24) [common]
204 08:42:04.337711 Using /lava-933547 at stage 0
205 08:42:04.339345 uuid=933547_1.6.2.4.1 testdef=None
206 08:42:04.339688 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 08:42:04.339963 start: 1.6.2.4.2 test-overlay (timeout 00:09:24) [common]
208 08:42:04.341693 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 08:42:04.342479 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:24) [common]
211 08:42:04.344510 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 08:42:04.345350 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:24) [common]
214 08:42:04.347186 runner path: /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/0/tests/0_timesync-off test_uuid 933547_1.6.2.4.1
215 08:42:04.347741 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 08:42:04.348584 start: 1.6.2.4.5 git-repo-action (timeout 00:09:24) [common]
218 08:42:04.348809 Using /lava-933547 at stage 0
219 08:42:04.349170 Fetching tests from https://github.com/kernelci/test-definitions.git
220 08:42:04.349464 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/0/tests/1_kselftest-dt'
221 08:42:07.740215 Running '/usr/bin/git checkout kernelci.org
222 08:42:08.199262 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
223 08:42:08.201818 uuid=933547_1.6.2.4.5 testdef=None
224 08:42:08.202501 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 08:42:08.204150 start: 1.6.2.4.6 test-overlay (timeout 00:09:20) [common]
227 08:42:08.210112 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 08:42:08.211868 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:20) [common]
230 08:42:08.219781 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 08:42:08.221652 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:20) [common]
233 08:42:08.229363 runner path: /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/0/tests/1_kselftest-dt test_uuid 933547_1.6.2.4.5
234 08:42:08.229952 BOARD='meson-g12b-a311d-libretech-cc'
235 08:42:08.230413 BRANCH='tip'
236 08:42:08.230848 SKIPFILE='/dev/null'
237 08:42:08.231286 SKIP_INSTALL='True'
238 08:42:08.231723 TESTPROG_URL='http://storage.kernelci.org/tip/master/v6.12-rc6-328-gf46306bca74bb/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 08:42:08.232215 TST_CASENAME=''
240 08:42:08.232668 TST_CMDFILES='dt'
241 08:42:08.233795 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 08:42:08.235491 Creating lava-test-runner.conf files
244 08:42:08.235946 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/933547/lava-overlay-3wvupa86/lava-933547/0 for stage 0
245 08:42:08.236757 - 0_timesync-off
246 08:42:08.237278 - 1_kselftest-dt
247 08:42:08.237988 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 08:42:08.238592 start: 1.6.2.5 compress-overlay (timeout 00:09:20) [common]
249 08:42:31.680944 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 08:42:31.681401 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:57) [common]
251 08:42:31.681670 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 08:42:31.681943 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 08:42:31.682207 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:57) [common]
254 08:42:32.308236 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 08:42:32.308758 start: 1.6.4 extract-modules (timeout 00:08:56) [common]
256 08:42:32.309029 extracting modules file /var/lib/lava/dispatcher/tmp/933547/tftp-deploy-afef1qp8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/933547/extract-nfsrootfs-dknoix43
257 08:42:33.699908 extracting modules file /var/lib/lava/dispatcher/tmp/933547/tftp-deploy-afef1qp8/modules/modules.tar to /var/lib/lava/dispatcher/tmp/933547/extract-overlay-ramdisk-o7luyk80/ramdisk
258 08:42:35.112879 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 08:42:35.113356 start: 1.6.5 apply-overlay-tftp (timeout 00:08:54) [common]
260 08:42:35.113635 [common] Applying overlay to NFS
261 08:42:35.113851 [common] Applying overlay /var/lib/lava/dispatcher/tmp/933547/compress-overlay-wl06rfra/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/933547/extract-nfsrootfs-dknoix43
262 08:42:37.876016 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 08:42:37.876504 start: 1.6.6 prepare-kernel (timeout 00:08:51) [common]
264 08:42:37.876783 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:51) [common]
265 08:42:37.877014 Converting downloaded kernel to a uImage
266 08:42:37.877322 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/933547/tftp-deploy-afef1qp8/kernel/Image /var/lib/lava/dispatcher/tmp/933547/tftp-deploy-afef1qp8/kernel/uImage
267 08:42:38.373057 output: Image Name:
268 08:42:38.373489 output: Created: Mon Nov 4 08:42:37 2024
269 08:42:38.373701 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 08:42:38.373909 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 08:42:38.374112 output: Load Address: 01080000
272 08:42:38.374312 output: Entry Point: 01080000
273 08:42:38.374510 output:
274 08:42:38.374841 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 08:42:38.375111 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 08:42:38.375383 start: 1.6.7 configure-preseed-file (timeout 00:08:50) [common]
277 08:42:38.375639 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 08:42:38.375896 start: 1.6.8 compress-ramdisk (timeout 00:08:50) [common]
279 08:42:38.376195 Building ramdisk /var/lib/lava/dispatcher/tmp/933547/extract-overlay-ramdisk-o7luyk80/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/933547/extract-overlay-ramdisk-o7luyk80/ramdisk
280 08:42:40.551346 >> 166824 blocks
281 08:42:48.246382 Adding RAMdisk u-boot header.
282 08:42:48.247090 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/933547/extract-overlay-ramdisk-o7luyk80/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/933547/extract-overlay-ramdisk-o7luyk80/ramdisk.cpio.gz.uboot
283 08:42:48.530412 output: Image Name:
284 08:42:48.531039 output: Created: Mon Nov 4 08:42:48 2024
285 08:42:48.531492 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 08:42:48.531931 output: Data Size: 23434567 Bytes = 22885.32 KiB = 22.35 MiB
287 08:42:48.532424 output: Load Address: 00000000
288 08:42:48.532859 output: Entry Point: 00000000
289 08:42:48.533292 output:
290 08:42:48.534320 rename /var/lib/lava/dispatcher/tmp/933547/extract-overlay-ramdisk-o7luyk80/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/933547/tftp-deploy-afef1qp8/ramdisk/ramdisk.cpio.gz.uboot
291 08:42:48.535128 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 08:42:48.535731 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 08:42:48.536356 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:40) [common]
294 08:42:48.536854 No LXC device requested
295 08:42:48.537396 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 08:42:48.537952 start: 1.8 deploy-device-env (timeout 00:08:40) [common]
297 08:42:48.538491 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 08:42:48.538937 Checking files for TFTP limit of 4294967296 bytes.
299 08:42:48.541827 end: 1 tftp-deploy (duration 00:01:20) [common]
300 08:42:48.542447 start: 2 uboot-action (timeout 00:05:00) [common]
301 08:42:48.543020 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 08:42:48.543560 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 08:42:48.544139 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 08:42:48.544721 Using kernel file from prepare-kernel: 933547/tftp-deploy-afef1qp8/kernel/uImage
305 08:42:48.545405 substitutions:
306 08:42:48.545851 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 08:42:48.546293 - {DTB_ADDR}: 0x01070000
308 08:42:48.546730 - {DTB}: 933547/tftp-deploy-afef1qp8/dtb/meson-g12b-a311d-libretech-cc.dtb
309 08:42:48.547172 - {INITRD}: 933547/tftp-deploy-afef1qp8/ramdisk/ramdisk.cpio.gz.uboot
310 08:42:48.547609 - {KERNEL_ADDR}: 0x01080000
311 08:42:48.548065 - {KERNEL}: 933547/tftp-deploy-afef1qp8/kernel/uImage
312 08:42:48.548503 - {LAVA_MAC}: None
313 08:42:48.548974 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/933547/extract-nfsrootfs-dknoix43
314 08:42:48.549408 - {NFS_SERVER_IP}: 192.168.6.2
315 08:42:48.549841 - {PRESEED_CONFIG}: None
316 08:42:48.550269 - {PRESEED_LOCAL}: None
317 08:42:48.550696 - {RAMDISK_ADDR}: 0x08000000
318 08:42:48.551120 - {RAMDISK}: 933547/tftp-deploy-afef1qp8/ramdisk/ramdisk.cpio.gz.uboot
319 08:42:48.551546 - {ROOT_PART}: None
320 08:42:48.551969 - {ROOT}: None
321 08:42:48.552450 - {SERVER_IP}: 192.168.6.2
322 08:42:48.552881 - {TEE_ADDR}: 0x83000000
323 08:42:48.553306 - {TEE}: None
324 08:42:48.553734 Parsed boot commands:
325 08:42:48.554147 - setenv autoload no
326 08:42:48.554571 - setenv initrd_high 0xffffffff
327 08:42:48.554991 - setenv fdt_high 0xffffffff
328 08:42:48.555414 - dhcp
329 08:42:48.555836 - setenv serverip 192.168.6.2
330 08:42:48.556290 - tftpboot 0x01080000 933547/tftp-deploy-afef1qp8/kernel/uImage
331 08:42:48.556720 - tftpboot 0x08000000 933547/tftp-deploy-afef1qp8/ramdisk/ramdisk.cpio.gz.uboot
332 08:42:48.557148 - tftpboot 0x01070000 933547/tftp-deploy-afef1qp8/dtb/meson-g12b-a311d-libretech-cc.dtb
333 08:42:48.557577 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/933547/extract-nfsrootfs-dknoix43,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 08:42:48.558017 - bootm 0x01080000 0x08000000 0x01070000
335 08:42:48.558555 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 08:42:48.560192 start: 2.3 connect-device (timeout 00:05:00) [common]
338 08:42:48.560654 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 08:42:48.577491 Setting prompt string to ['lava-test: # ']
340 08:42:48.579144 end: 2.3 connect-device (duration 00:00:00) [common]
341 08:42:48.579819 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 08:42:48.580478 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 08:42:48.581067 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 08:42:48.582314 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 08:42:48.620422 >> OK - accepted request
346 08:42:48.622678 Returned 0 in 0 seconds
347 08:42:48.723809 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 08:42:48.725559 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 08:42:48.726165 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 08:42:48.726708 Setting prompt string to ['Hit any key to stop autoboot']
352 08:42:48.727204 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 08:42:48.728908 Trying 192.168.56.21...
354 08:42:48.729422 Connected to conserv1.
355 08:42:48.729869 Escape character is '^]'.
356 08:42:48.730323
357 08:42:48.730774 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
358 08:42:48.731242
359 08:42:59.642703 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 08:42:59.643626 bl2_stage_init 0x01
361 08:42:59.644427 bl2_stage_init 0x81
362 08:42:59.648269 hw id: 0x0000 - pwm id 0x01
363 08:42:59.649029 bl2_stage_init 0xc1
364 08:42:59.649767 bl2_stage_init 0x02
365 08:42:59.650438
366 08:42:59.653859 L0:00000000
367 08:42:59.654643 L1:20000703
368 08:42:59.655318 L2:00008067
369 08:42:59.656066 L3:14000000
370 08:42:59.659305 B2:00402000
371 08:42:59.660089 B1:e0f83180
372 08:42:59.660755
373 08:42:59.661409 TE: 58167
374 08:42:59.662050
375 08:42:59.664970 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 08:42:59.665658
377 08:42:59.666312 Board ID = 1
378 08:42:59.670596 Set A53 clk to 24M
379 08:42:59.671319 Set A73 clk to 24M
380 08:42:59.671975 Set clk81 to 24M
381 08:42:59.676089 A53 clk: 1200 MHz
382 08:42:59.676779 A73 clk: 1200 MHz
383 08:42:59.677471 CLK81: 166.6M
384 08:42:59.678111 smccc: 00012abd
385 08:42:59.681708 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 08:42:59.687255 board id: 1
387 08:42:59.692704 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 08:42:59.703795 fw parse done
389 08:42:59.709290 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 08:42:59.751686 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 08:42:59.763342 PIEI prepare done
392 08:42:59.764232 fastboot data load
393 08:42:59.764969 fastboot data verify
394 08:42:59.768930 verify result: 266
395 08:42:59.774551 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 08:42:59.775308 LPDDR4 probe
397 08:42:59.776095 ddr clk to 1584MHz
398 08:42:59.782151 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 08:42:59.819544
400 08:42:59.820501 dmc_version 0001
401 08:42:59.826238 Check phy result
402 08:42:59.832342 INFO : End of CA training
403 08:42:59.833112 INFO : End of initialization
404 08:42:59.837850 INFO : Training has run successfully!
405 08:42:59.838616 Check phy result
406 08:42:59.843540 INFO : End of initialization
407 08:42:59.844393 INFO : End of read enable training
408 08:42:59.849089 INFO : End of fine write leveling
409 08:42:59.854738 INFO : End of Write leveling coarse delay
410 08:42:59.855438 INFO : Training has run successfully!
411 08:42:59.856184 Check phy result
412 08:42:59.860217 INFO : End of initialization
413 08:42:59.860953 INFO : End of read dq deskew training
414 08:42:59.865863 INFO : End of MPR read delay center optimization
415 08:42:59.871598 INFO : End of write delay center optimization
416 08:42:59.877018 INFO : End of read delay center optimization
417 08:42:59.877780 INFO : End of max read latency training
418 08:42:59.882764 INFO : Training has run successfully!
419 08:42:59.883529 1D training succeed
420 08:42:59.891335 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 08:42:59.939497 Check phy result
422 08:42:59.940243 INFO : End of initialization
423 08:42:59.960493 INFO : End of 2D read delay Voltage center optimization
424 08:42:59.981521 INFO : End of 2D read delay Voltage center optimization
425 08:43:00.033194 INFO : End of 2D write delay Voltage center optimization
426 08:43:00.082886 INFO : End of 2D write delay Voltage center optimization
427 08:43:00.088487 INFO : Training has run successfully!
428 08:43:00.089097
429 08:43:00.089597 channel==0
430 08:43:00.094048 RxClkDly_Margin_A0==88 ps 9
431 08:43:00.094452 TxDqDly_Margin_A0==98 ps 10
432 08:43:00.099610 RxClkDly_Margin_A1==88 ps 9
433 08:43:00.099924 TxDqDly_Margin_A1==98 ps 10
434 08:43:00.100189 TrainedVREFDQ_A0==74
435 08:43:00.105214 TrainedVREFDQ_A1==74
436 08:43:00.105528 VrefDac_Margin_A0==25
437 08:43:00.105754 DeviceVref_Margin_A0==40
438 08:43:00.110826 VrefDac_Margin_A1==25
439 08:43:00.111133 DeviceVref_Margin_A1==40
440 08:43:00.111356
441 08:43:00.111575
442 08:43:00.116441 channel==1
443 08:43:00.116749 RxClkDly_Margin_A0==98 ps 10
444 08:43:00.116969 TxDqDly_Margin_A0==88 ps 9
445 08:43:00.122032 RxClkDly_Margin_A1==88 ps 9
446 08:43:00.122339 TxDqDly_Margin_A1==88 ps 9
447 08:43:00.127639 TrainedVREFDQ_A0==77
448 08:43:00.127951 TrainedVREFDQ_A1==77
449 08:43:00.128205 VrefDac_Margin_A0==22
450 08:43:00.133240 DeviceVref_Margin_A0==37
451 08:43:00.133546 VrefDac_Margin_A1==24
452 08:43:00.138736 DeviceVref_Margin_A1==37
453 08:43:00.139040
454 08:43:00.139266 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 08:43:00.139486
456 08:43:00.172398 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
457 08:43:00.172824 2D training succeed
458 08:43:00.177924 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 08:43:00.183552 auto size-- 65535DDR cs0 size: 2048MB
460 08:43:00.183907 DDR cs1 size: 2048MB
461 08:43:00.189114 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 08:43:00.189427 cs0 DataBus test pass
463 08:43:00.194705 cs1 DataBus test pass
464 08:43:00.195009 cs0 AddrBus test pass
465 08:43:00.195231 cs1 AddrBus test pass
466 08:43:00.195446
467 08:43:00.200315 100bdlr_step_size ps== 420
468 08:43:00.200648 result report
469 08:43:00.205917 boot times 0Enable ddr reg access
470 08:43:00.210990 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 08:43:00.224237 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 08:43:00.797801 0.0;M3 CHK:0;cm4_sp_mode 0
473 08:43:00.798498 MVN_1=0x00000000
474 08:43:00.803245 MVN_2=0x00000000
475 08:43:00.809007 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 08:43:00.809555 OPS=0x10
477 08:43:00.810011 ring efuse init
478 08:43:00.810453 chipver efuse init
479 08:43:00.817191 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 08:43:00.817793 [0.018961 Inits done]
481 08:43:00.824518 secure task start!
482 08:43:00.825169 high task start!
483 08:43:00.825663 low task start!
484 08:43:00.826184 run into bl31
485 08:43:00.831436 NOTICE: BL31: v1.3(release):4fc40b1
486 08:43:00.838310 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 08:43:00.838905 NOTICE: BL31: G12A normal boot!
488 08:43:00.864766 NOTICE: BL31: BL33 decompress pass
489 08:43:00.869327 ERROR: Error initializing runtime service opteed_fast
490 08:43:02.102993
491 08:43:02.103377
492 08:43:02.110479 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 08:43:02.110765
494 08:43:02.110992 Model: Libre Computer AML-A311D-CC Alta
495 08:43:02.319884 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 08:43:02.343249 DRAM: 2 GiB (effective 3.8 GiB)
497 08:43:02.486397 Core: 408 devices, 31 uclasses, devicetree: separate
498 08:43:02.491240 WDT: Not starting watchdog@f0d0
499 08:43:02.524523 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 08:43:02.537067 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 08:43:02.541944 ** Bad device specification mmc 0 **
502 08:43:02.552256 Card did not respond to voltage select! : -110
503 08:43:02.559946 ** Bad device specification mmc 0 **
504 08:43:02.560480 Couldn't find partition mmc 0
505 08:43:02.568247 Card did not respond to voltage select! : -110
506 08:43:02.573739 ** Bad device specification mmc 0 **
507 08:43:02.574236 Couldn't find partition mmc 0
508 08:43:02.578809 Error: could not access storage.
509 08:43:03.842699 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 08:43:03.843313 bl2_stage_init 0x01
511 08:43:03.843761 bl2_stage_init 0x81
512 08:43:03.848307 hw id: 0x0000 - pwm id 0x01
513 08:43:03.848799 bl2_stage_init 0xc1
514 08:43:03.849242 bl2_stage_init 0x02
515 08:43:03.849682
516 08:43:03.853915 L0:00000000
517 08:43:03.854406 L1:20000703
518 08:43:03.854838 L2:00008067
519 08:43:03.855268 L3:14000000
520 08:43:03.859491 B2:00402000
521 08:43:03.860009 B1:e0f83180
522 08:43:03.860456
523 08:43:03.860890 TE: 58159
524 08:43:03.861319
525 08:43:03.865197 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 08:43:03.865698
527 08:43:03.866139 Board ID = 1
528 08:43:03.870685 Set A53 clk to 24M
529 08:43:03.871174 Set A73 clk to 24M
530 08:43:03.871616 Set clk81 to 24M
531 08:43:03.876306 A53 clk: 1200 MHz
532 08:43:03.876793 A73 clk: 1200 MHz
533 08:43:03.877230 CLK81: 166.6M
534 08:43:03.877660 smccc: 00012ab5
535 08:43:03.881888 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 08:43:03.887481 board id: 1
537 08:43:03.893371 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 08:43:03.904082 fw parse done
539 08:43:03.909985 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 08:43:03.952644 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 08:43:03.963541 PIEI prepare done
542 08:43:03.964093 fastboot data load
543 08:43:03.964544 fastboot data verify
544 08:43:03.969309 verify result: 266
545 08:43:03.974831 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 08:43:03.975344 LPDDR4 probe
547 08:43:03.975782 ddr clk to 1584MHz
548 08:43:03.982777 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 08:43:04.020057
550 08:43:04.020582 dmc_version 0001
551 08:43:04.025786 Check phy result
552 08:43:04.032598 INFO : End of CA training
553 08:43:04.033086 INFO : End of initialization
554 08:43:04.038301 INFO : Training has run successfully!
555 08:43:04.038790 Check phy result
556 08:43:04.043812 INFO : End of initialization
557 08:43:04.044333 INFO : End of read enable training
558 08:43:04.049367 INFO : End of fine write leveling
559 08:43:04.054995 INFO : End of Write leveling coarse delay
560 08:43:04.055483 INFO : Training has run successfully!
561 08:43:04.055919 Check phy result
562 08:43:04.060596 INFO : End of initialization
563 08:43:04.061088 INFO : End of read dq deskew training
564 08:43:04.066314 INFO : End of MPR read delay center optimization
565 08:43:04.071792 INFO : End of write delay center optimization
566 08:43:04.077379 INFO : End of read delay center optimization
567 08:43:04.077868 INFO : End of max read latency training
568 08:43:04.082994 INFO : Training has run successfully!
569 08:43:04.083483 1D training succeed
570 08:43:04.091247 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 08:43:04.139751 Check phy result
572 08:43:04.140286 INFO : End of initialization
573 08:43:04.161462 INFO : End of 2D read delay Voltage center optimization
574 08:43:04.180652 INFO : End of 2D read delay Voltage center optimization
575 08:43:04.233252 INFO : End of 2D write delay Voltage center optimization
576 08:43:04.282597 INFO : End of 2D write delay Voltage center optimization
577 08:43:04.288269 INFO : Training has run successfully!
578 08:43:04.288766
579 08:43:04.289209 channel==0
580 08:43:04.293771 RxClkDly_Margin_A0==88 ps 9
581 08:43:04.294269 TxDqDly_Margin_A0==98 ps 10
582 08:43:04.299373 RxClkDly_Margin_A1==88 ps 9
583 08:43:04.299871 TxDqDly_Margin_A1==98 ps 10
584 08:43:04.300364 TrainedVREFDQ_A0==74
585 08:43:04.304990 TrainedVREFDQ_A1==75
586 08:43:04.305489 VrefDac_Margin_A0==25
587 08:43:04.305925 DeviceVref_Margin_A0==40
588 08:43:04.310600 VrefDac_Margin_A1==25
589 08:43:04.311112 DeviceVref_Margin_A1==39
590 08:43:04.311550
591 08:43:04.312014
592 08:43:04.316285 channel==1
593 08:43:04.316780 RxClkDly_Margin_A0==98 ps 10
594 08:43:04.317220 TxDqDly_Margin_A0==98 ps 10
595 08:43:04.321787 RxClkDly_Margin_A1==98 ps 10
596 08:43:04.322276 TxDqDly_Margin_A1==88 ps 9
597 08:43:04.327391 TrainedVREFDQ_A0==77
598 08:43:04.327888 TrainedVREFDQ_A1==77
599 08:43:04.328370 VrefDac_Margin_A0==22
600 08:43:04.332982 DeviceVref_Margin_A0==37
601 08:43:04.333468 VrefDac_Margin_A1==22
602 08:43:04.338591 DeviceVref_Margin_A1==37
603 08:43:04.339077
604 08:43:04.339513 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 08:43:04.344244
606 08:43:04.372255 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
607 08:43:04.372816 2D training succeed
608 08:43:04.377789 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 08:43:04.383393 auto size-- 65535DDR cs0 size: 2048MB
610 08:43:04.383892 DDR cs1 size: 2048MB
611 08:43:04.388979 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 08:43:04.389473 cs0 DataBus test pass
613 08:43:04.394595 cs1 DataBus test pass
614 08:43:04.395100 cs0 AddrBus test pass
615 08:43:04.395538 cs1 AddrBus test pass
616 08:43:04.395970
617 08:43:04.400291 100bdlr_step_size ps== 420
618 08:43:04.400822 result report
619 08:43:04.405757 boot times 0Enable ddr reg access
620 08:43:04.411183 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 08:43:04.424932 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 08:43:04.996644 0.0;M3 CHK:0;cm4_sp_mode 0
623 08:43:04.997299 MVN_1=0x00000000
624 08:43:05.002145 MVN_2=0x00000000
625 08:43:05.007891 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 08:43:05.008435 OPS=0x10
627 08:43:05.008880 ring efuse init
628 08:43:05.009309 chipver efuse init
629 08:43:05.013504 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 08:43:05.019104 [0.018961 Inits done]
631 08:43:05.019603 secure task start!
632 08:43:05.020072 high task start!
633 08:43:05.022860 low task start!
634 08:43:05.023366 run into bl31
635 08:43:05.030391 NOTICE: BL31: v1.3(release):4fc40b1
636 08:43:05.038204 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 08:43:05.038715 NOTICE: BL31: G12A normal boot!
638 08:43:05.063521 NOTICE: BL31: BL33 decompress pass
639 08:43:05.069313 ERROR: Error initializing runtime service opteed_fast
640 08:43:06.302176
641 08:43:06.302801
642 08:43:06.310727 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 08:43:06.311234
644 08:43:06.311678 Model: Libre Computer AML-A311D-CC Alta
645 08:43:06.519080 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 08:43:06.542479 DRAM: 2 GiB (effective 3.8 GiB)
647 08:43:06.685314 Core: 408 devices, 31 uclasses, devicetree: separate
648 08:43:06.691223 WDT: Not starting watchdog@f0d0
649 08:43:06.723508 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 08:43:06.735908 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 08:43:06.740892 ** Bad device specification mmc 0 **
652 08:43:06.751206 Card did not respond to voltage select! : -110
653 08:43:06.758872 ** Bad device specification mmc 0 **
654 08:43:06.759150 Couldn't find partition mmc 0
655 08:43:06.767199 Card did not respond to voltage select! : -110
656 08:43:06.772729 ** Bad device specification mmc 0 **
657 08:43:06.773009 Couldn't find partition mmc 0
658 08:43:06.777742 Error: could not access storage.
659 08:43:07.120259 Net: eth0: ethernet@ff3f0000
660 08:43:07.120801 starting USB...
661 08:43:07.372103 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 08:43:07.372482 Starting the controller
663 08:43:07.379006 USB XHCI 1.10
664 08:43:09.092998 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 08:43:09.093577 bl2_stage_init 0x01
666 08:43:09.093824 bl2_stage_init 0x81
667 08:43:09.098569 hw id: 0x0000 - pwm id 0x01
668 08:43:09.098837 bl2_stage_init 0xc1
669 08:43:09.099044 bl2_stage_init 0x02
670 08:43:09.099246
671 08:43:09.104155 L0:00000000
672 08:43:09.104527 L1:20000703
673 08:43:09.104838 L2:00008067
674 08:43:09.105138 L3:14000000
675 08:43:09.107113 B2:00402000
676 08:43:09.107476 B1:e0f83180
677 08:43:09.107789
678 08:43:09.108132 TE: 58167
679 08:43:09.108366
680 08:43:09.118281 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 08:43:09.118580
682 08:43:09.118803 Board ID = 1
683 08:43:09.119006 Set A53 clk to 24M
684 08:43:09.119204 Set A73 clk to 24M
685 08:43:09.123907 Set clk81 to 24M
686 08:43:09.124195 A53 clk: 1200 MHz
687 08:43:09.124412 A73 clk: 1200 MHz
688 08:43:09.127383 CLK81: 166.6M
689 08:43:09.127750 smccc: 00012abd
690 08:43:09.133039 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 08:43:09.138584 board id: 1
692 08:43:09.143765 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 08:43:09.154364 fw parse done
694 08:43:09.160280 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 08:43:09.202847 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 08:43:09.213786 PIEI prepare done
697 08:43:09.214655 fastboot data load
698 08:43:09.215398 fastboot data verify
699 08:43:09.219346 verify result: 266
700 08:43:09.224944 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 08:43:09.225714 LPDDR4 probe
702 08:43:09.226480 ddr clk to 1584MHz
703 08:43:09.233074 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 08:43:09.270306
705 08:43:09.271162 dmc_version 0001
706 08:43:09.276814 Check phy result
707 08:43:09.282700 INFO : End of CA training
708 08:43:09.283167 INFO : End of initialization
709 08:43:09.288235 INFO : Training has run successfully!
710 08:43:09.288695 Check phy result
711 08:43:09.293837 INFO : End of initialization
712 08:43:09.294294 INFO : End of read enable training
713 08:43:09.299460 INFO : End of fine write leveling
714 08:43:09.305054 INFO : End of Write leveling coarse delay
715 08:43:09.305553 INFO : Training has run successfully!
716 08:43:09.305975 Check phy result
717 08:43:09.310793 INFO : End of initialization
718 08:43:09.311263 INFO : End of read dq deskew training
719 08:43:09.316272 INFO : End of MPR read delay center optimization
720 08:43:09.321926 INFO : End of write delay center optimization
721 08:43:09.327557 INFO : End of read delay center optimization
722 08:43:09.328433 INFO : End of max read latency training
723 08:43:09.333099 INFO : Training has run successfully!
724 08:43:09.333961 1D training succeed
725 08:43:09.342350 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 08:43:09.390076 Check phy result
727 08:43:09.391096 INFO : End of initialization
728 08:43:09.412615 INFO : End of 2D read delay Voltage center optimization
729 08:43:09.432882 INFO : End of 2D read delay Voltage center optimization
730 08:43:09.484871 INFO : End of 2D write delay Voltage center optimization
731 08:43:09.534187 INFO : End of 2D write delay Voltage center optimization
732 08:43:09.539707 INFO : Training has run successfully!
733 08:43:09.540667
734 08:43:09.541447 channel==0
735 08:43:09.545266 RxClkDly_Margin_A0==88 ps 9
736 08:43:09.545781 TxDqDly_Margin_A0==98 ps 10
737 08:43:09.550892 RxClkDly_Margin_A1==88 ps 9
738 08:43:09.551378 TxDqDly_Margin_A1==98 ps 10
739 08:43:09.551798 TrainedVREFDQ_A0==74
740 08:43:09.556473 TrainedVREFDQ_A1==75
741 08:43:09.556934 VrefDac_Margin_A0==24
742 08:43:09.557346 DeviceVref_Margin_A0==40
743 08:43:09.562089 VrefDac_Margin_A1==25
744 08:43:09.562424 DeviceVref_Margin_A1==39
745 08:43:09.562646
746 08:43:09.562854
747 08:43:09.567749 channel==1
748 08:43:09.568222 RxClkDly_Margin_A0==98 ps 10
749 08:43:09.568567 TxDqDly_Margin_A0==98 ps 10
750 08:43:09.573314 RxClkDly_Margin_A1==98 ps 10
751 08:43:09.573747 TxDqDly_Margin_A1==108 ps 11
752 08:43:09.578940 TrainedVREFDQ_A0==77
753 08:43:09.579375 TrainedVREFDQ_A1==78
754 08:43:09.579675 VrefDac_Margin_A0==22
755 08:43:09.584514 DeviceVref_Margin_A0==37
756 08:43:09.584858 VrefDac_Margin_A1==22
757 08:43:09.590123 DeviceVref_Margin_A1==36
758 08:43:09.590586
759 08:43:09.595711 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 08:43:09.596198
761 08:43:09.623690 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000018 00000018 00000017 00000017 00000016 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
762 08:43:09.624088 2D training succeed
763 08:43:09.629313 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 08:43:09.634945 auto size-- 65535DDR cs0 size: 2048MB
765 08:43:09.635406 DDR cs1 size: 2048MB
766 08:43:09.640513 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 08:43:09.640834 cs0 DataBus test pass
768 08:43:09.646095 cs1 DataBus test pass
769 08:43:09.646533 cs0 AddrBus test pass
770 08:43:09.646873 cs1 AddrBus test pass
771 08:43:09.647198
772 08:43:09.651708 100bdlr_step_size ps== 420
773 08:43:09.652059 result report
774 08:43:09.657352 boot times 0Enable ddr reg access
775 08:43:09.662063 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 08:43:09.676384 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 08:43:10.249524 0.0;M3 CHK:0;cm4_sp_mode 0
778 08:43:10.250204 MVN_1=0x00000000
779 08:43:10.255153 MVN_2=0x00000000
780 08:43:10.260800 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 08:43:10.261406 OPS=0x10
782 08:43:10.261867 ring efuse init
783 08:43:10.262302 chipver efuse init
784 08:43:10.266367 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 08:43:10.271955 [0.018961 Inits done]
786 08:43:10.272503 secure task start!
787 08:43:10.272944 high task start!
788 08:43:10.276499 low task start!
789 08:43:10.277014 run into bl31
790 08:43:10.283178 NOTICE: BL31: v1.3(release):4fc40b1
791 08:43:10.291010 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 08:43:10.291541 NOTICE: BL31: G12A normal boot!
793 08:43:10.316385 NOTICE: BL31: BL33 decompress pass
794 08:43:10.321760 ERROR: Error initializing runtime service opteed_fast
795 08:43:11.554905
796 08:43:11.555555
797 08:43:11.563380 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 08:43:11.563915
799 08:43:11.564418 Model: Libre Computer AML-A311D-CC Alta
800 08:43:11.770786 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 08:43:11.795148 DRAM: 2 GiB (effective 3.8 GiB)
802 08:43:11.938129 Core: 408 devices, 31 uclasses, devicetree: separate
803 08:43:11.944037 WDT: Not starting watchdog@f0d0
804 08:43:11.976336 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 08:43:11.988711 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 08:43:11.993704 ** Bad device specification mmc 0 **
807 08:43:12.004106 Card did not respond to voltage select! : -110
808 08:43:12.010752 ** Bad device specification mmc 0 **
809 08:43:12.011257 Couldn't find partition mmc 0
810 08:43:12.020066 Card did not respond to voltage select! : -110
811 08:43:12.025558 ** Bad device specification mmc 0 **
812 08:43:12.026062 Couldn't find partition mmc 0
813 08:43:12.030625 Error: could not access storage.
814 08:43:12.373182 Net: eth0: ethernet@ff3f0000
815 08:43:12.373763 starting USB...
816 08:43:12.625886 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 08:43:12.626431 Starting the controller
818 08:43:12.632906 USB XHCI 1.10
819 08:43:14.793276 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 08:43:14.793887 bl2_stage_init 0x01
821 08:43:14.794347 bl2_stage_init 0x81
822 08:43:14.798913 hw id: 0x0000 - pwm id 0x01
823 08:43:14.799418 bl2_stage_init 0xc1
824 08:43:14.799871 bl2_stage_init 0x02
825 08:43:14.800370
826 08:43:14.804495 L0:00000000
827 08:43:14.805000 L1:20000703
828 08:43:14.805451 L2:00008067
829 08:43:14.805893 L3:14000000
830 08:43:14.810045 B2:00402000
831 08:43:14.810547 B1:e0f83180
832 08:43:14.810996
833 08:43:14.811440 TE: 58124
834 08:43:14.811890
835 08:43:14.815726 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 08:43:14.816274
837 08:43:14.816731 Board ID = 1
838 08:43:14.821283 Set A53 clk to 24M
839 08:43:14.821780 Set A73 clk to 24M
840 08:43:14.822229 Set clk81 to 24M
841 08:43:14.826780 A53 clk: 1200 MHz
842 08:43:14.827278 A73 clk: 1200 MHz
843 08:43:14.827728 CLK81: 166.6M
844 08:43:14.828212 smccc: 00012a91
845 08:43:14.832365 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 08:43:14.838036 board id: 1
847 08:43:14.843059 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 08:43:14.854531 fw parse done
849 08:43:14.860573 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 08:43:14.902225 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 08:43:14.914057 PIEI prepare done
852 08:43:14.914584 fastboot data load
853 08:43:14.915039 fastboot data verify
854 08:43:14.919769 verify result: 266
855 08:43:14.925298 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 08:43:14.925807 LPDDR4 probe
857 08:43:14.926262 ddr clk to 1584MHz
858 08:43:14.933297 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 08:43:14.970508
860 08:43:14.971013 dmc_version 0001
861 08:43:14.977228 Check phy result
862 08:43:14.983080 INFO : End of CA training
863 08:43:14.983575 INFO : End of initialization
864 08:43:14.988666 INFO : Training has run successfully!
865 08:43:14.989170 Check phy result
866 08:43:14.994279 INFO : End of initialization
867 08:43:14.994779 INFO : End of read enable training
868 08:43:14.999870 INFO : End of fine write leveling
869 08:43:15.005525 INFO : End of Write leveling coarse delay
870 08:43:15.006036 INFO : Training has run successfully!
871 08:43:15.006493 Check phy result
872 08:43:15.011091 INFO : End of initialization
873 08:43:15.011593 INFO : End of read dq deskew training
874 08:43:15.016735 INFO : End of MPR read delay center optimization
875 08:43:15.022242 INFO : End of write delay center optimization
876 08:43:15.027901 INFO : End of read delay center optimization
877 08:43:15.028440 INFO : End of max read latency training
878 08:43:15.033486 INFO : Training has run successfully!
879 08:43:15.033986 1D training succeed
880 08:43:15.042671 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 08:43:15.090270 Check phy result
882 08:43:15.090804 INFO : End of initialization
883 08:43:15.112702 INFO : End of 2D read delay Voltage center optimization
884 08:43:15.132787 INFO : End of 2D read delay Voltage center optimization
885 08:43:15.184770 INFO : End of 2D write delay Voltage center optimization
886 08:43:15.234017 INFO : End of 2D write delay Voltage center optimization
887 08:43:15.239602 INFO : Training has run successfully!
888 08:43:15.240184
889 08:43:15.240652 channel==0
890 08:43:15.245118 RxClkDly_Margin_A0==88 ps 9
891 08:43:15.245630 TxDqDly_Margin_A0==98 ps 10
892 08:43:15.248520 RxClkDly_Margin_A1==88 ps 9
893 08:43:15.249022 TxDqDly_Margin_A1==98 ps 10
894 08:43:15.254113 TrainedVREFDQ_A0==74
895 08:43:15.254649 TrainedVREFDQ_A1==74
896 08:43:15.259682 VrefDac_Margin_A0==24
897 08:43:15.260258 DeviceVref_Margin_A0==40
898 08:43:15.260717 VrefDac_Margin_A1==24
899 08:43:15.265249 DeviceVref_Margin_A1==40
900 08:43:15.265776
901 08:43:15.266211
902 08:43:15.266636 channel==1
903 08:43:15.267059 RxClkDly_Margin_A0==98 ps 10
904 08:43:15.270899 TxDqDly_Margin_A0==98 ps 10
905 08:43:15.271391 RxClkDly_Margin_A1==98 ps 10
906 08:43:15.276341 TxDqDly_Margin_A1==88 ps 9
907 08:43:15.276837 TrainedVREFDQ_A0==77
908 08:43:15.277267 TrainedVREFDQ_A1==77
909 08:43:15.282043 VrefDac_Margin_A0==22
910 08:43:15.282527 DeviceVref_Margin_A0==37
911 08:43:15.287605 VrefDac_Margin_A1==22
912 08:43:15.288144 DeviceVref_Margin_A1==37
913 08:43:15.288598
914 08:43:15.293115 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 08:43:15.293611
916 08:43:15.321156 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000018 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
917 08:43:15.326878 2D training succeed
918 08:43:15.332286 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 08:43:15.332775 auto size-- 65535DDR cs0 size: 2048MB
920 08:43:15.337850 DDR cs1 size: 2048MB
921 08:43:15.338357 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 08:43:15.343481 cs0 DataBus test pass
923 08:43:15.343969 cs1 DataBus test pass
924 08:43:15.344450 cs0 AddrBus test pass
925 08:43:15.349109 cs1 AddrBus test pass
926 08:43:15.349593
927 08:43:15.350028 100bdlr_step_size ps== 420
928 08:43:15.350464 result report
929 08:43:15.354737 boot times 0Enable ddr reg access
930 08:43:15.362485 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 08:43:15.375908 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 08:43:15.947933 0.0;M3 CHK:0;cm4_sp_mode 0
933 08:43:15.948593 MVN_1=0x00000000
934 08:43:15.953406 MVN_2=0x00000000
935 08:43:15.959141 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 08:43:15.959647 OPS=0x10
937 08:43:15.960145 ring efuse init
938 08:43:15.960593 chipver efuse init
939 08:43:15.964753 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 08:43:15.970352 [0.018961 Inits done]
941 08:43:15.970847 secure task start!
942 08:43:15.971295 high task start!
943 08:43:15.974957 low task start!
944 08:43:15.975451 run into bl31
945 08:43:15.981599 NOTICE: BL31: v1.3(release):4fc40b1
946 08:43:15.989372 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 08:43:15.989875 NOTICE: BL31: G12A normal boot!
948 08:43:16.014742 NOTICE: BL31: BL33 decompress pass
949 08:43:16.019911 ERROR: Error initializing runtime service opteed_fast
950 08:43:17.253274
951 08:43:17.253901
952 08:43:17.261709 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 08:43:17.262218
954 08:43:17.262673 Model: Libre Computer AML-A311D-CC Alta
955 08:43:17.470187 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 08:43:17.493510 DRAM: 2 GiB (effective 3.8 GiB)
957 08:43:17.636557 Core: 408 devices, 31 uclasses, devicetree: separate
958 08:43:17.641561 WDT: Not starting watchdog@f0d0
959 08:43:17.674694 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 08:43:17.687143 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 08:43:17.691260 ** Bad device specification mmc 0 **
962 08:43:17.702551 Card did not respond to voltage select! : -110
963 08:43:17.709300 ** Bad device specification mmc 0 **
964 08:43:17.709801 Couldn't find partition mmc 0
965 08:43:17.718480 Card did not respond to voltage select! : -110
966 08:43:17.724007 ** Bad device specification mmc 0 **
967 08:43:17.724523 Couldn't find partition mmc 0
968 08:43:17.729045 Error: could not access storage.
969 08:43:18.071663 Net: eth0: ethernet@ff3f0000
970 08:43:18.072303 starting USB...
971 08:43:18.324387 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 08:43:18.324990 Starting the controller
973 08:43:18.331377 USB XHCI 1.10
974 08:43:20.072844 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 08:43:20.073483 bl2_stage_init 0x01
976 08:43:20.073949 bl2_stage_init 0x81
977 08:43:20.078481 hw id: 0x0000 - pwm id 0x01
978 08:43:20.078988 bl2_stage_init 0xc1
979 08:43:20.079444 bl2_stage_init 0x02
980 08:43:20.079889
981 08:43:20.084010 L0:00000000
982 08:43:20.084512 L1:20000703
983 08:43:20.084967 L2:00008067
984 08:43:20.085414 L3:14000000
985 08:43:20.086870 B2:00402000
986 08:43:20.087361 B1:e0f83180
987 08:43:20.087815
988 08:43:20.088314 TE: 58167
989 08:43:20.088762
990 08:43:20.098013 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 08:43:20.098529
992 08:43:20.098988 Board ID = 1
993 08:43:20.099426 Set A53 clk to 24M
994 08:43:20.099859 Set A73 clk to 24M
995 08:43:20.103588 Set clk81 to 24M
996 08:43:20.104108 A53 clk: 1200 MHz
997 08:43:20.104558 A73 clk: 1200 MHz
998 08:43:20.109204 CLK81: 166.6M
999 08:43:20.109708 smccc: 00012abe
1000 08:43:20.114793 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 08:43:20.115300 board id: 1
1002 08:43:20.120469 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 08:43:20.134146 fw parse done
1004 08:43:20.139096 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 08:43:20.181848 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 08:43:20.193659 PIEI prepare done
1007 08:43:20.194182 fastboot data load
1008 08:43:20.194638 fastboot data verify
1009 08:43:20.199327 verify result: 266
1010 08:43:20.204910 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 08:43:20.205417 LPDDR4 probe
1012 08:43:20.205869 ddr clk to 1584MHz
1013 08:43:20.212929 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 08:43:20.250166
1015 08:43:20.250727 dmc_version 0001
1016 08:43:20.256807 Check phy result
1017 08:43:20.262784 INFO : End of CA training
1018 08:43:20.263356 INFO : End of initialization
1019 08:43:20.268311 INFO : Training has run successfully!
1020 08:43:20.268829 Check phy result
1021 08:43:20.273895 INFO : End of initialization
1022 08:43:20.274385 INFO : End of read enable training
1023 08:43:20.279557 INFO : End of fine write leveling
1024 08:43:20.285075 INFO : End of Write leveling coarse delay
1025 08:43:20.285586 INFO : Training has run successfully!
1026 08:43:20.286024 Check phy result
1027 08:43:20.290747 INFO : End of initialization
1028 08:43:20.291288 INFO : End of read dq deskew training
1029 08:43:20.296360 INFO : End of MPR read delay center optimization
1030 08:43:20.301901 INFO : End of write delay center optimization
1031 08:43:20.307518 INFO : End of read delay center optimization
1032 08:43:20.308043 INFO : End of max read latency training
1033 08:43:20.313052 INFO : Training has run successfully!
1034 08:43:20.313543 1D training succeed
1035 08:43:20.322231 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 08:43:20.369947 Check phy result
1037 08:43:20.370485 INFO : End of initialization
1038 08:43:20.392701 INFO : End of 2D read delay Voltage center optimization
1039 08:43:20.412611 INFO : End of 2D read delay Voltage center optimization
1040 08:43:20.464826 INFO : End of 2D write delay Voltage center optimization
1041 08:43:20.514107 INFO : End of 2D write delay Voltage center optimization
1042 08:43:20.519685 INFO : Training has run successfully!
1043 08:43:20.520239
1044 08:43:20.520702 channel==0
1045 08:43:20.525278 RxClkDly_Margin_A0==88 ps 9
1046 08:43:20.525784 TxDqDly_Margin_A0==98 ps 10
1047 08:43:20.528712 RxClkDly_Margin_A1==88 ps 9
1048 08:43:20.529213 TxDqDly_Margin_A1==98 ps 10
1049 08:43:20.534342 TrainedVREFDQ_A0==74
1050 08:43:20.534841 TrainedVREFDQ_A1==74
1051 08:43:20.535292 VrefDac_Margin_A0==24
1052 08:43:20.539924 DeviceVref_Margin_A0==40
1053 08:43:20.540467 VrefDac_Margin_A1==24
1054 08:43:20.545601 DeviceVref_Margin_A1==40
1055 08:43:20.546122
1056 08:43:20.546575
1057 08:43:20.547018 channel==1
1058 08:43:20.547454 RxClkDly_Margin_A0==98 ps 10
1059 08:43:20.551103 TxDqDly_Margin_A0==98 ps 10
1060 08:43:20.551603 RxClkDly_Margin_A1==98 ps 10
1061 08:43:20.556821 TxDqDly_Margin_A1==88 ps 9
1062 08:43:20.557328 TrainedVREFDQ_A0==77
1063 08:43:20.557786 TrainedVREFDQ_A1==77
1064 08:43:20.562290 VrefDac_Margin_A0==22
1065 08:43:20.562796 DeviceVref_Margin_A0==37
1066 08:43:20.567964 VrefDac_Margin_A1==22
1067 08:43:20.568520 DeviceVref_Margin_A1==37
1068 08:43:20.568971
1069 08:43:20.573529 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 08:43:20.574038
1071 08:43:20.601547 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1072 08:43:20.607245 2D training succeed
1073 08:43:20.612728 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 08:43:20.613256 auto size-- 65535DDR cs0 size: 2048MB
1075 08:43:20.618306 DDR cs1 size: 2048MB
1076 08:43:20.618835 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 08:43:20.623977 cs0 DataBus test pass
1078 08:43:20.624576 cs1 DataBus test pass
1079 08:43:20.625036 cs0 AddrBus test pass
1080 08:43:20.629583 cs1 AddrBus test pass
1081 08:43:20.630137
1082 08:43:20.630594 100bdlr_step_size ps== 420
1083 08:43:20.631051 result report
1084 08:43:20.635110 boot times 0Enable ddr reg access
1085 08:43:20.641741 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 08:43:20.655256 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 08:43:21.229723 0.0;M3 CHK:0;cm4_sp_mode 0
1088 08:43:21.230287 MVN_1=0x00000000
1089 08:43:21.235289 MVN_2=0x00000000
1090 08:43:21.241047 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 08:43:21.241555 OPS=0x10
1092 08:43:21.242007 ring efuse init
1093 08:43:21.242452 chipver efuse init
1094 08:43:21.246642 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 08:43:21.252262 [0.018960 Inits done]
1096 08:43:21.252758 secure task start!
1097 08:43:21.253211 high task start!
1098 08:43:21.256849 low task start!
1099 08:43:21.257341 run into bl31
1100 08:43:21.263612 NOTICE: BL31: v1.3(release):4fc40b1
1101 08:43:21.271324 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 08:43:21.271823 NOTICE: BL31: G12A normal boot!
1103 08:43:21.296657 NOTICE: BL31: BL33 decompress pass
1104 08:43:21.302385 ERROR: Error initializing runtime service opteed_fast
1105 08:43:22.535191
1106 08:43:22.535783
1107 08:43:22.543759 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 08:43:22.544307
1109 08:43:22.544764 Model: Libre Computer AML-A311D-CC Alta
1110 08:43:22.751064 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 08:43:22.775490 DRAM: 2 GiB (effective 3.8 GiB)
1112 08:43:22.918432 Core: 408 devices, 31 uclasses, devicetree: separate
1113 08:43:22.923370 WDT: Not starting watchdog@f0d0
1114 08:43:22.956617 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 08:43:22.969009 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 08:43:22.973091 ** Bad device specification mmc 0 **
1117 08:43:22.984346 Card did not respond to voltage select! : -110
1118 08:43:22.991094 ** Bad device specification mmc 0 **
1119 08:43:22.991588 Couldn't find partition mmc 0
1120 08:43:23.000372 Card did not respond to voltage select! : -110
1121 08:43:23.005905 ** Bad device specification mmc 0 **
1122 08:43:23.006400 Couldn't find partition mmc 0
1123 08:43:23.010091 Error: could not access storage.
1124 08:43:23.352434 Net: eth0: ethernet@ff3f0000
1125 08:43:23.353011 starting USB...
1126 08:43:23.605166 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 08:43:23.605726 Starting the controller
1128 08:43:23.612357 USB XHCI 1.10
1129 08:43:25.166303 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 08:43:25.174656 scanning usb for storage devices... 0 Storage Device(s) found
1132 08:43:25.226333 Hit any key to stop autoboot: 1
1133 08:43:25.227194 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 08:43:25.227887 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1135 08:43:25.228473 Setting prompt string to ['=>']
1136 08:43:25.229027 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1137 08:43:25.242134 0
1138 08:43:25.243079 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 08:43:25.243626 Sending with 10 millisecond of delay
1141 08:43:26.378705 => setenv autoload no
1142 08:43:26.389556 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1143 08:43:26.395000 setenv autoload no
1144 08:43:26.395772 Sending with 10 millisecond of delay
1146 08:43:28.192873 => setenv initrd_high 0xffffffff
1147 08:43:28.203687 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1148 08:43:28.204672 setenv initrd_high 0xffffffff
1149 08:43:28.205442 Sending with 10 millisecond of delay
1151 08:43:29.821716 => setenv fdt_high 0xffffffff
1152 08:43:29.832538 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
1153 08:43:29.833469 setenv fdt_high 0xffffffff
1154 08:43:29.834227 Sending with 10 millisecond of delay
1156 08:43:30.126176 => dhcp
1157 08:43:30.136993 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 08:43:30.137881 dhcp
1159 08:43:30.138356 Speed: 1000, full duplex
1160 08:43:30.138808 BOOTP broadcast 1
1161 08:43:30.335238 DHCP client bound to address 192.168.6.27 (198 ms)
1162 08:43:30.336113 Sending with 10 millisecond of delay
1164 08:43:32.012775 => setenv serverip 192.168.6.2
1165 08:43:32.023649 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
1166 08:43:32.024718 setenv serverip 192.168.6.2
1167 08:43:32.025466 Sending with 10 millisecond of delay
1169 08:43:35.750566 => tftpboot 0x01080000 933547/tftp-deploy-afef1qp8/kernel/uImage
1170 08:43:35.761297 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1171 08:43:35.761877 tftpboot 0x01080000 933547/tftp-deploy-afef1qp8/kernel/uImage
1172 08:43:35.762144 Speed: 1000, full duplex
1173 08:43:35.762377 Using ethernet@ff3f0000 device
1174 08:43:35.764039 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 08:43:35.769595 Filename '933547/tftp-deploy-afef1qp8/kernel/uImage'.
1176 08:43:35.773621 Load address: 0x1080000
1177 08:43:38.856077 Loading: *################################################## 43.6 MiB
1178 08:43:38.856736 14.1 MiB/s
1179 08:43:38.857222 done
1180 08:43:38.859383 Bytes transferred = 45713984 (2b98a40 hex)
1181 08:43:38.860280 Sending with 10 millisecond of delay
1183 08:43:43.550299 => tftpboot 0x08000000 933547/tftp-deploy-afef1qp8/ramdisk/ramdisk.cpio.gz.uboot
1184 08:43:43.561198 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1185 08:43:43.562183 tftpboot 0x08000000 933547/tftp-deploy-afef1qp8/ramdisk/ramdisk.cpio.gz.uboot
1186 08:43:43.562720 Speed: 1000, full duplex
1187 08:43:43.563186 Using ethernet@ff3f0000 device
1188 08:43:43.564166 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 08:43:43.575927 Filename '933547/tftp-deploy-afef1qp8/ramdisk/ramdisk.cpio.gz.uboot'.
1190 08:43:43.576531 Load address: 0x8000000
1191 08:43:50.243171 Loading: *###########T ###################################### UDP wrong checksum 00000005 00003ad5
1192 08:43:50.825254 UDP wrong checksum 000000ff 000076fc
1193 08:43:50.845038 UDP wrong checksum 000000ff 00000def
1194 08:43:55.245077 T UDP wrong checksum 00000005 00003ad5
1195 08:44:01.262484 T UDP wrong checksum 000000ff 00000c67
1196 08:44:01.269063 UDP wrong checksum 000000ff 00009a59
1197 08:44:05.247287 T UDP wrong checksum 00000005 00003ad5
1198 08:44:25.247976 T T T UDP wrong checksum 00000005 00003ad5
1199 08:44:40.255321 T T T
1200 08:44:40.256046 Retry count exceeded; starting again
1202 08:44:40.257610 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1205 08:44:40.259693 end: 2.4 uboot-commands (duration 00:01:52) [common]
1207 08:44:40.261279 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1209 08:44:40.262387 end: 2 uboot-action (duration 00:01:52) [common]
1211 08:44:40.264074 Cleaning after the job
1212 08:44:40.264682 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933547/tftp-deploy-afef1qp8/ramdisk
1213 08:44:40.266140 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933547/tftp-deploy-afef1qp8/kernel
1214 08:44:40.313996 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933547/tftp-deploy-afef1qp8/dtb
1215 08:44:40.314782 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933547/tftp-deploy-afef1qp8/nfsrootfs
1216 08:44:40.426398 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933547/tftp-deploy-afef1qp8/modules
1217 08:44:40.446882 start: 4.1 power-off (timeout 00:00:30) [common]
1218 08:44:40.447547 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1219 08:44:40.486666 >> OK - accepted request
1220 08:44:40.488792 Returned 0 in 0 seconds
1221 08:44:40.589598 end: 4.1 power-off (duration 00:00:00) [common]
1223 08:44:40.590604 start: 4.2 read-feedback (timeout 00:10:00) [common]
1224 08:44:40.591266 Listened to connection for namespace 'common' for up to 1s
1225 08:44:41.592184 Finalising connection for namespace 'common'
1226 08:44:41.592653 Disconnecting from shell: Finalise
1227 08:44:41.592944 =>
1228 08:44:41.693679 end: 4.2 read-feedback (duration 00:00:01) [common]
1229 08:44:41.694311 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/933547
1230 08:44:44.917899 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/933547
1231 08:44:44.918665 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.