Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 08:55:08.741851 lava-dispatcher, installed at version: 2024.01
2 08:55:08.742623 start: 0 validate
3 08:55:08.743098 Start time: 2024-11-04 08:55:08.743068+00:00 (UTC)
4 08:55:08.743629 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 08:55:08.744210 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 08:55:08.785935 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 08:55:08.786575 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-328-gf46306bca74bb%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 08:55:08.816026 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 08:55:08.816649 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-328-gf46306bca74bb%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 08:55:08.845647 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 08:55:08.846138 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 08:55:08.878502 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 08:55:08.879446 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-328-gf46306bca74bb%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 08:55:08.915172 validate duration: 0.17
16 08:55:08.916261 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 08:55:08.916682 start: 1.1 download-retry (timeout 00:10:00) [common]
18 08:55:08.917071 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 08:55:08.917763 Not decompressing ramdisk as can be used compressed.
20 08:55:08.918286 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 08:55:08.918634 saving as /var/lib/lava/dispatcher/tmp/933562/tftp-deploy-yjquvwm7/ramdisk/initrd.cpio.gz
22 08:55:08.918969 total size: 5628140 (5 MB)
23 08:55:08.956905 progress 0 % (0 MB)
24 08:55:08.961850 progress 5 % (0 MB)
25 08:55:08.967015 progress 10 % (0 MB)
26 08:55:08.971529 progress 15 % (0 MB)
27 08:55:08.976595 progress 20 % (1 MB)
28 08:55:08.981053 progress 25 % (1 MB)
29 08:55:08.986119 progress 30 % (1 MB)
30 08:55:08.991155 progress 35 % (1 MB)
31 08:55:08.995567 progress 40 % (2 MB)
32 08:55:09.000395 progress 45 % (2 MB)
33 08:55:09.004895 progress 50 % (2 MB)
34 08:55:09.009794 progress 55 % (2 MB)
35 08:55:09.014815 progress 60 % (3 MB)
36 08:55:09.019096 progress 65 % (3 MB)
37 08:55:09.023940 progress 70 % (3 MB)
38 08:55:09.028413 progress 75 % (4 MB)
39 08:55:09.033364 progress 80 % (4 MB)
40 08:55:09.037637 progress 85 % (4 MB)
41 08:55:09.042513 progress 90 % (4 MB)
42 08:55:09.047352 progress 95 % (5 MB)
43 08:55:09.051358 progress 100 % (5 MB)
44 08:55:09.052150 5 MB downloaded in 0.13 s (40.31 MB/s)
45 08:55:09.052827 end: 1.1.1 http-download (duration 00:00:00) [common]
47 08:55:09.053913 end: 1.1 download-retry (duration 00:00:00) [common]
48 08:55:09.054285 start: 1.2 download-retry (timeout 00:10:00) [common]
49 08:55:09.054628 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 08:55:09.055207 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-328-gf46306bca74bb/arm64/defconfig/gcc-12/kernel/Image
51 08:55:09.055514 saving as /var/lib/lava/dispatcher/tmp/933562/tftp-deploy-yjquvwm7/kernel/Image
52 08:55:09.055776 total size: 45713920 (43 MB)
53 08:55:09.056066 No compression specified
54 08:55:09.089368 progress 0 % (0 MB)
55 08:55:09.122319 progress 5 % (2 MB)
56 08:55:09.154802 progress 10 % (4 MB)
57 08:55:09.187545 progress 15 % (6 MB)
58 08:55:09.219872 progress 20 % (8 MB)
59 08:55:09.251993 progress 25 % (10 MB)
60 08:55:09.284329 progress 30 % (13 MB)
61 08:55:09.317052 progress 35 % (15 MB)
62 08:55:09.349483 progress 40 % (17 MB)
63 08:55:09.381685 progress 45 % (19 MB)
64 08:55:09.414375 progress 50 % (21 MB)
65 08:55:09.446915 progress 55 % (24 MB)
66 08:55:09.479590 progress 60 % (26 MB)
67 08:55:09.511266 progress 65 % (28 MB)
68 08:55:09.543768 progress 70 % (30 MB)
69 08:55:09.576352 progress 75 % (32 MB)
70 08:55:09.608927 progress 80 % (34 MB)
71 08:55:09.640731 progress 85 % (37 MB)
72 08:55:09.673173 progress 90 % (39 MB)
73 08:55:09.705224 progress 95 % (41 MB)
74 08:55:09.736894 progress 100 % (43 MB)
75 08:55:09.737540 43 MB downloaded in 0.68 s (63.95 MB/s)
76 08:55:09.738140 end: 1.2.1 http-download (duration 00:00:01) [common]
78 08:55:09.739156 end: 1.2 download-retry (duration 00:00:01) [common]
79 08:55:09.739514 start: 1.3 download-retry (timeout 00:09:59) [common]
80 08:55:09.739849 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 08:55:09.740452 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-328-gf46306bca74bb/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 08:55:09.740790 saving as /var/lib/lava/dispatcher/tmp/933562/tftp-deploy-yjquvwm7/dtb/meson-g12b-a311d-libretech-cc.dtb
83 08:55:09.741060 total size: 54703 (0 MB)
84 08:55:09.741324 No compression specified
85 08:55:09.782666 progress 59 % (0 MB)
86 08:55:09.784110 progress 100 % (0 MB)
87 08:55:09.784668 0 MB downloaded in 0.04 s (1.20 MB/s)
88 08:55:09.785134 end: 1.3.1 http-download (duration 00:00:00) [common]
90 08:55:09.785942 end: 1.3 download-retry (duration 00:00:00) [common]
91 08:55:09.786205 start: 1.4 download-retry (timeout 00:09:59) [common]
92 08:55:09.786470 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 08:55:09.786923 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 08:55:09.787158 saving as /var/lib/lava/dispatcher/tmp/933562/tftp-deploy-yjquvwm7/nfsrootfs/full.rootfs.tar
95 08:55:09.787365 total size: 474398908 (452 MB)
96 08:55:09.787575 Using unxz to decompress xz
97 08:55:09.828402 progress 0 % (0 MB)
98 08:55:10.917694 progress 5 % (22 MB)
99 08:55:12.348432 progress 10 % (45 MB)
100 08:55:12.783464 progress 15 % (67 MB)
101 08:55:13.570253 progress 20 % (90 MB)
102 08:55:14.105594 progress 25 % (113 MB)
103 08:55:14.463878 progress 30 % (135 MB)
104 08:55:15.067600 progress 35 % (158 MB)
105 08:55:15.988236 progress 40 % (181 MB)
106 08:55:16.852671 progress 45 % (203 MB)
107 08:55:17.615297 progress 50 % (226 MB)
108 08:55:18.418364 progress 55 % (248 MB)
109 08:55:19.639196 progress 60 % (271 MB)
110 08:55:21.140791 progress 65 % (294 MB)
111 08:55:22.782182 progress 70 % (316 MB)
112 08:55:25.902073 progress 75 % (339 MB)
113 08:55:28.374815 progress 80 % (361 MB)
114 08:55:31.267171 progress 85 % (384 MB)
115 08:55:34.419094 progress 90 % (407 MB)
116 08:55:37.637509 progress 95 % (429 MB)
117 08:55:40.815312 progress 100 % (452 MB)
118 08:55:40.828125 452 MB downloaded in 31.04 s (14.58 MB/s)
119 08:55:40.829063 end: 1.4.1 http-download (duration 00:00:31) [common]
121 08:55:40.830810 end: 1.4 download-retry (duration 00:00:31) [common]
122 08:55:40.831380 start: 1.5 download-retry (timeout 00:09:28) [common]
123 08:55:40.831940 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 08:55:40.832970 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-328-gf46306bca74bb/arm64/defconfig/gcc-12/modules.tar.xz
125 08:55:40.833484 saving as /var/lib/lava/dispatcher/tmp/933562/tftp-deploy-yjquvwm7/modules/modules.tar
126 08:55:40.833932 total size: 11614628 (11 MB)
127 08:55:40.834391 Using unxz to decompress xz
128 08:55:40.879423 progress 0 % (0 MB)
129 08:55:40.945757 progress 5 % (0 MB)
130 08:55:41.019255 progress 10 % (1 MB)
131 08:55:41.114447 progress 15 % (1 MB)
132 08:55:41.207779 progress 20 % (2 MB)
133 08:55:41.286634 progress 25 % (2 MB)
134 08:55:41.361051 progress 30 % (3 MB)
135 08:55:41.438446 progress 35 % (3 MB)
136 08:55:41.510687 progress 40 % (4 MB)
137 08:55:41.585695 progress 45 % (5 MB)
138 08:55:41.668759 progress 50 % (5 MB)
139 08:55:41.744770 progress 55 % (6 MB)
140 08:55:41.828880 progress 60 % (6 MB)
141 08:55:41.908429 progress 65 % (7 MB)
142 08:55:41.987723 progress 70 % (7 MB)
143 08:55:42.065297 progress 75 % (8 MB)
144 08:55:42.147760 progress 80 % (8 MB)
145 08:55:42.226787 progress 85 % (9 MB)
146 08:55:42.309522 progress 90 % (10 MB)
147 08:55:42.382181 progress 95 % (10 MB)
148 08:55:42.458316 progress 100 % (11 MB)
149 08:55:42.470165 11 MB downloaded in 1.64 s (6.77 MB/s)
150 08:55:42.470844 end: 1.5.1 http-download (duration 00:00:02) [common]
152 08:55:42.471848 end: 1.5 download-retry (duration 00:00:02) [common]
153 08:55:42.472492 start: 1.6 prepare-tftp-overlay (timeout 00:09:26) [common]
154 08:55:42.473192 start: 1.6.1 extract-nfsrootfs (timeout 00:09:26) [common]
155 08:55:58.170870 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/933562/extract-nfsrootfs-ec9v6_e9
156 08:55:58.171486 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 08:55:58.171814 start: 1.6.2 lava-overlay (timeout 00:09:11) [common]
158 08:55:58.172594 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr
159 08:55:58.173090 makedir: /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin
160 08:55:58.173491 makedir: /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/tests
161 08:55:58.173868 makedir: /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/results
162 08:55:58.174257 Creating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin/lava-add-keys
163 08:55:58.174868 Creating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin/lava-add-sources
164 08:55:58.175431 Creating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin/lava-background-process-start
165 08:55:58.175951 Creating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin/lava-background-process-stop
166 08:55:58.176519 Creating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin/lava-common-functions
167 08:55:58.177030 Creating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin/lava-echo-ipv4
168 08:55:58.177524 Creating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin/lava-install-packages
169 08:55:58.178008 Creating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin/lava-installed-packages
170 08:55:58.178487 Creating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin/lava-os-build
171 08:55:58.178979 Creating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin/lava-probe-channel
172 08:55:58.179458 Creating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin/lava-probe-ip
173 08:55:58.179929 Creating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin/lava-target-ip
174 08:55:58.180446 Creating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin/lava-target-mac
175 08:55:58.180936 Creating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin/lava-target-storage
176 08:55:58.181438 Creating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin/lava-test-case
177 08:55:58.181928 Creating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin/lava-test-event
178 08:55:58.182481 Creating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin/lava-test-feedback
179 08:55:58.182968 Creating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin/lava-test-raise
180 08:55:58.183440 Creating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin/lava-test-reference
181 08:55:58.183909 Creating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin/lava-test-runner
182 08:55:58.184426 Creating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin/lava-test-set
183 08:55:58.184918 Creating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin/lava-test-shell
184 08:55:58.185419 Updating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin/lava-install-packages (oe)
185 08:55:58.185952 Updating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/bin/lava-installed-packages (oe)
186 08:55:58.186387 Creating /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/environment
187 08:55:58.186750 LAVA metadata
188 08:55:58.187011 - LAVA_JOB_ID=933562
189 08:55:58.187225 - LAVA_DISPATCHER_IP=192.168.6.2
190 08:55:58.187581 start: 1.6.2.1 ssh-authorize (timeout 00:09:11) [common]
191 08:55:58.188546 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 08:55:58.188861 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:11) [common]
193 08:55:58.189070 skipped lava-vland-overlay
194 08:55:58.189312 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 08:55:58.189565 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:11) [common]
196 08:55:58.189785 skipped lava-multinode-overlay
197 08:55:58.190029 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 08:55:58.190279 start: 1.6.2.4 test-definition (timeout 00:09:11) [common]
199 08:55:58.190524 Loading test definitions
200 08:55:58.190799 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:11) [common]
201 08:55:58.191017 Using /lava-933562 at stage 0
202 08:55:58.192156 uuid=933562_1.6.2.4.1 testdef=None
203 08:55:58.192466 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 08:55:58.192728 start: 1.6.2.4.2 test-overlay (timeout 00:09:11) [common]
205 08:55:58.194450 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 08:55:58.195232 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:11) [common]
208 08:55:58.197422 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 08:55:58.198260 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:11) [common]
211 08:55:58.200318 runner path: /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/0/tests/0_v4l2-decoder-conformance-h264 test_uuid 933562_1.6.2.4.1
212 08:55:58.200866 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 08:55:58.201624 Creating lava-test-runner.conf files
215 08:55:58.201826 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/933562/lava-overlay-fuva6wgr/lava-933562/0 for stage 0
216 08:55:58.202153 - 0_v4l2-decoder-conformance-h264
217 08:55:58.202488 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 08:55:58.202761 start: 1.6.2.5 compress-overlay (timeout 00:09:11) [common]
219 08:55:58.224009 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 08:55:58.224353 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:11) [common]
221 08:55:58.224611 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 08:55:58.224875 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 08:55:58.225138 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:11) [common]
224 08:55:58.845075 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 08:55:58.845551 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 08:55:58.845799 extracting modules file /var/lib/lava/dispatcher/tmp/933562/tftp-deploy-yjquvwm7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/933562/extract-nfsrootfs-ec9v6_e9
227 08:56:00.190716 extracting modules file /var/lib/lava/dispatcher/tmp/933562/tftp-deploy-yjquvwm7/modules/modules.tar to /var/lib/lava/dispatcher/tmp/933562/extract-overlay-ramdisk-1o75xfsj/ramdisk
228 08:56:01.581677 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 08:56:01.582164 start: 1.6.5 apply-overlay-tftp (timeout 00:09:07) [common]
230 08:56:01.582443 [common] Applying overlay to NFS
231 08:56:01.582656 [common] Applying overlay /var/lib/lava/dispatcher/tmp/933562/compress-overlay-43c2mi79/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/933562/extract-nfsrootfs-ec9v6_e9
232 08:56:01.611919 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 08:56:01.612322 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 08:56:01.612598 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 08:56:01.612827 Converting downloaded kernel to a uImage
236 08:56:01.613133 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/933562/tftp-deploy-yjquvwm7/kernel/Image /var/lib/lava/dispatcher/tmp/933562/tftp-deploy-yjquvwm7/kernel/uImage
237 08:56:02.108659 output: Image Name:
238 08:56:02.109187 output: Created: Mon Nov 4 08:56:01 2024
239 08:56:02.109453 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 08:56:02.109697 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 08:56:02.109928 output: Load Address: 01080000
242 08:56:02.110162 output: Entry Point: 01080000
243 08:56:02.110388 output:
244 08:56:02.110760 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 08:56:02.111077 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 08:56:02.111398 start: 1.6.7 configure-preseed-file (timeout 00:09:07) [common]
247 08:56:02.111681 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 08:56:02.112011 start: 1.6.8 compress-ramdisk (timeout 00:09:07) [common]
249 08:56:02.112320 Building ramdisk /var/lib/lava/dispatcher/tmp/933562/extract-overlay-ramdisk-1o75xfsj/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/933562/extract-overlay-ramdisk-1o75xfsj/ramdisk
250 08:56:04.381160 >> 166824 blocks
251 08:56:12.096987 Adding RAMdisk u-boot header.
252 08:56:12.097656 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/933562/extract-overlay-ramdisk-1o75xfsj/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/933562/extract-overlay-ramdisk-1o75xfsj/ramdisk.cpio.gz.uboot
253 08:56:12.350214 output: Image Name:
254 08:56:12.350635 output: Created: Mon Nov 4 08:56:12 2024
255 08:56:12.350850 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 08:56:12.351057 output: Data Size: 23434197 Bytes = 22884.96 KiB = 22.35 MiB
257 08:56:12.351259 output: Load Address: 00000000
258 08:56:12.351460 output: Entry Point: 00000000
259 08:56:12.351658 output:
260 08:56:12.352472 rename /var/lib/lava/dispatcher/tmp/933562/extract-overlay-ramdisk-1o75xfsj/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/933562/tftp-deploy-yjquvwm7/ramdisk/ramdisk.cpio.gz.uboot
261 08:56:12.353265 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 08:56:12.353863 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 08:56:12.354447 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:57) [common]
264 08:56:12.354963 No LXC device requested
265 08:56:12.355516 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 08:56:12.356116 start: 1.8 deploy-device-env (timeout 00:08:57) [common]
267 08:56:12.356675 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 08:56:12.357132 Checking files for TFTP limit of 4294967296 bytes.
269 08:56:12.360042 end: 1 tftp-deploy (duration 00:01:03) [common]
270 08:56:12.360673 start: 2 uboot-action (timeout 00:05:00) [common]
271 08:56:12.361252 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 08:56:12.361798 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 08:56:12.362352 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 08:56:12.362922 Using kernel file from prepare-kernel: 933562/tftp-deploy-yjquvwm7/kernel/uImage
275 08:56:12.363607 substitutions:
276 08:56:12.364083 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 08:56:12.364532 - {DTB_ADDR}: 0x01070000
278 08:56:12.364974 - {DTB}: 933562/tftp-deploy-yjquvwm7/dtb/meson-g12b-a311d-libretech-cc.dtb
279 08:56:12.365413 - {INITRD}: 933562/tftp-deploy-yjquvwm7/ramdisk/ramdisk.cpio.gz.uboot
280 08:56:12.365854 - {KERNEL_ADDR}: 0x01080000
281 08:56:12.366288 - {KERNEL}: 933562/tftp-deploy-yjquvwm7/kernel/uImage
282 08:56:12.366723 - {LAVA_MAC}: None
283 08:56:12.367197 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/933562/extract-nfsrootfs-ec9v6_e9
284 08:56:12.367640 - {NFS_SERVER_IP}: 192.168.6.2
285 08:56:12.368110 - {PRESEED_CONFIG}: None
286 08:56:12.368553 - {PRESEED_LOCAL}: None
287 08:56:12.368987 - {RAMDISK_ADDR}: 0x08000000
288 08:56:12.369417 - {RAMDISK}: 933562/tftp-deploy-yjquvwm7/ramdisk/ramdisk.cpio.gz.uboot
289 08:56:12.369848 - {ROOT_PART}: None
290 08:56:12.370280 - {ROOT}: None
291 08:56:12.370709 - {SERVER_IP}: 192.168.6.2
292 08:56:12.371138 - {TEE_ADDR}: 0x83000000
293 08:56:12.371568 - {TEE}: None
294 08:56:12.372021 Parsed boot commands:
295 08:56:12.372447 - setenv autoload no
296 08:56:12.372875 - setenv initrd_high 0xffffffff
297 08:56:12.373301 - setenv fdt_high 0xffffffff
298 08:56:12.373730 - dhcp
299 08:56:12.374158 - setenv serverip 192.168.6.2
300 08:56:12.374587 - tftpboot 0x01080000 933562/tftp-deploy-yjquvwm7/kernel/uImage
301 08:56:12.375016 - tftpboot 0x08000000 933562/tftp-deploy-yjquvwm7/ramdisk/ramdisk.cpio.gz.uboot
302 08:56:12.375444 - tftpboot 0x01070000 933562/tftp-deploy-yjquvwm7/dtb/meson-g12b-a311d-libretech-cc.dtb
303 08:56:12.375875 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/933562/extract-nfsrootfs-ec9v6_e9,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 08:56:12.376349 - bootm 0x01080000 0x08000000 0x01070000
305 08:56:12.376897 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 08:56:12.378525 start: 2.3 connect-device (timeout 00:05:00) [common]
308 08:56:12.378983 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 08:56:12.393381 Setting prompt string to ['lava-test: # ']
310 08:56:12.394964 end: 2.3 connect-device (duration 00:00:00) [common]
311 08:56:12.395617 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 08:56:12.396257 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 08:56:12.396847 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 08:56:12.398054 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 08:56:12.439136 >> OK - accepted request
316 08:56:12.441502 Returned 0 in 0 seconds
317 08:56:12.542660 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 08:56:12.544404 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 08:56:12.545044 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 08:56:12.545608 Setting prompt string to ['Hit any key to stop autoboot']
322 08:56:12.546113 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 08:56:12.547781 Trying 192.168.56.21...
324 08:56:12.548335 Connected to conserv1.
325 08:56:12.548801 Escape character is '^]'.
326 08:56:12.549261
327 08:56:12.549721 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 08:56:12.550181
329 08:56:24.077638 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
330 08:56:24.078289 bl2_stage_init 0x81
331 08:56:24.083325 hw id: 0x0000 - pwm id 0x01
332 08:56:24.083862 bl2_stage_init 0xc1
333 08:56:24.084361 bl2_stage_init 0x02
334 08:56:24.084815
335 08:56:24.088792 L0:00000000
336 08:56:24.089265 L1:20000703
337 08:56:24.089716 L2:00008067
338 08:56:24.090146 L3:14000000
339 08:56:24.090583 B2:00402000
340 08:56:24.091740 B1:e0f83180
341 08:56:24.092247
342 08:56:24.092682 TE: 58150
343 08:56:24.093120
344 08:56:24.102973 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
345 08:56:24.103456
346 08:56:24.103895 Board ID = 1
347 08:56:24.104432 Set A53 clk to 24M
348 08:56:24.104872 Set A73 clk to 24M
349 08:56:24.108667 Set clk81 to 24M
350 08:56:24.109128 A53 clk: 1200 MHz
351 08:56:24.109562 A73 clk: 1200 MHz
352 08:56:24.114034 CLK81: 166.6M
353 08:56:24.114498 smccc: 00012aac
354 08:56:24.119558 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
355 08:56:24.120043 board id: 1
356 08:56:24.128200 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
357 08:56:24.138709 fw parse done
358 08:56:24.144842 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
359 08:56:24.187341 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
360 08:56:24.198182 PIEI prepare done
361 08:56:24.198649 fastboot data load
362 08:56:24.199083 fastboot data verify
363 08:56:24.203877 verify result: 266
364 08:56:24.209594 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
365 08:56:24.210062 LPDDR4 probe
366 08:56:24.210515 ddr clk to 1584MHz
367 08:56:24.217440 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
368 08:56:24.254716
369 08:56:24.255191 dmc_version 0001
370 08:56:24.261409 Check phy result
371 08:56:24.267239 INFO : End of CA training
372 08:56:24.267708 INFO : End of initialization
373 08:56:24.272834 INFO : Training has run successfully!
374 08:56:24.273303 Check phy result
375 08:56:24.278570 INFO : End of initialization
376 08:56:24.279040 INFO : End of read enable training
377 08:56:24.281747 INFO : End of fine write leveling
378 08:56:24.287292 INFO : End of Write leveling coarse delay
379 08:56:24.292895 INFO : Training has run successfully!
380 08:56:24.293360 Check phy result
381 08:56:24.293803 INFO : End of initialization
382 08:56:24.298614 INFO : End of read dq deskew training
383 08:56:24.304086 INFO : End of MPR read delay center optimization
384 08:56:24.304550 INFO : End of write delay center optimization
385 08:56:24.309713 INFO : End of read delay center optimization
386 08:56:24.315287 INFO : End of max read latency training
387 08:56:24.315753 INFO : Training has run successfully!
388 08:56:24.320912 1D training succeed
389 08:56:24.326875 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 08:56:24.374439 Check phy result
391 08:56:24.374904 INFO : End of initialization
392 08:56:24.396991 INFO : End of 2D read delay Voltage center optimization
393 08:56:24.417219 INFO : End of 2D read delay Voltage center optimization
394 08:56:24.469237 INFO : End of 2D write delay Voltage center optimization
395 08:56:24.518672 INFO : End of 2D write delay Voltage center optimization
396 08:56:24.524320 INFO : Training has run successfully!
397 08:56:24.524784
398 08:56:24.525233 channel==0
399 08:56:24.529878 RxClkDly_Margin_A0==88 ps 9
400 08:56:24.530356 TxDqDly_Margin_A0==98 ps 10
401 08:56:24.533190 RxClkDly_Margin_A1==88 ps 9
402 08:56:24.533657 TxDqDly_Margin_A1==98 ps 10
403 08:56:24.538670 TrainedVREFDQ_A0==74
404 08:56:24.539138 TrainedVREFDQ_A1==75
405 08:56:24.544311 VrefDac_Margin_A0==24
406 08:56:24.544782 DeviceVref_Margin_A0==40
407 08:56:24.545235 VrefDac_Margin_A1==24
408 08:56:24.549812 DeviceVref_Margin_A1==39
409 08:56:24.550293
410 08:56:24.550741
411 08:56:24.551183 channel==1
412 08:56:24.551622 RxClkDly_Margin_A0==98 ps 10
413 08:56:24.555475 TxDqDly_Margin_A0==88 ps 9
414 08:56:24.555953 RxClkDly_Margin_A1==88 ps 9
415 08:56:24.561486 TxDqDly_Margin_A1==88 ps 9
416 08:56:24.561961 TrainedVREFDQ_A0==77
417 08:56:24.562412 TrainedVREFDQ_A1==77
418 08:56:24.566727 VrefDac_Margin_A0==22
419 08:56:24.567193 DeviceVref_Margin_A0==37
420 08:56:24.572339 VrefDac_Margin_A1==24
421 08:56:24.572804 DeviceVref_Margin_A1==37
422 08:56:24.573250
423 08:56:24.577865 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
424 08:56:24.578341
425 08:56:24.605753 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
426 08:56:24.611348 2D training succeed
427 08:56:24.616959 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
428 08:56:24.617436 auto size-- 65535DDR cs0 size: 2048MB
429 08:56:24.622567 DDR cs1 size: 2048MB
430 08:56:24.623048 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
431 08:56:24.628213 cs0 DataBus test pass
432 08:56:24.628684 cs1 DataBus test pass
433 08:56:24.629131 cs0 AddrBus test pass
434 08:56:24.633743 cs1 AddrBus test pass
435 08:56:24.634216
436 08:56:24.634667 100bdlr_step_size ps== 420
437 08:56:24.635122 result report
438 08:56:24.639344 boot times 0Enable ddr reg access
439 08:56:24.646997 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
440 08:56:24.660528 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
441 08:56:25.234160 0.0;M3 CHK:0;cm4_sp_mode 0
442 08:56:25.234784 MVN_1=0x00000000
443 08:56:25.239638 MVN_2=0x00000000
444 08:56:25.245384 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
445 08:56:25.245899 OPS=0x10
446 08:56:25.246362 ring efuse init
447 08:56:25.246808 chipver efuse init
448 08:56:25.250987 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
449 08:56:25.256561 [0.018960 Inits done]
450 08:56:25.257028 secure task start!
451 08:56:25.257475 high task start!
452 08:56:25.261155 low task start!
453 08:56:25.261659 run into bl31
454 08:56:25.267857 NOTICE: BL31: v1.3(release):4fc40b1
455 08:56:25.275849 NOTICE: BL31: Built : 15:58:17, May 22 2019
456 08:56:25.276472 NOTICE: BL31: G12A normal boot!
457 08:56:25.302001 NOTICE: BL31: BL33 decompress pass
458 08:56:25.306829 ERROR: Error initializing runtime service opteed_fast
459 08:56:26.539683
460 08:56:26.540538
461 08:56:26.548104 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
462 08:56:26.548608
463 08:56:26.549046 Model: Libre Computer AML-A311D-CC Alta
464 08:56:26.756461 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
465 08:56:26.780044 DRAM: 2 GiB (effective 3.8 GiB)
466 08:56:26.922983 Core: 408 devices, 31 uclasses, devicetree: separate
467 08:56:26.928757 WDT: Not starting watchdog@f0d0
468 08:56:26.960964 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
469 08:56:26.973499 Loading Environment from FAT... Card did not respond to voltage select! : -110
470 08:56:26.978427 ** Bad device specification mmc 0 **
471 08:56:26.988766 Card did not respond to voltage select! : -110
472 08:56:26.996399 ** Bad device specification mmc 0 **
473 08:56:26.996865 Couldn't find partition mmc 0
474 08:56:27.004768 Card did not respond to voltage select! : -110
475 08:56:27.010287 ** Bad device specification mmc 0 **
476 08:56:27.010763 Couldn't find partition mmc 0
477 08:56:27.014411 Error: could not access storage.
478 08:56:28.277933 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
479 08:56:28.278631 bl2_stage_init 0x01
480 08:56:28.279184 bl2_stage_init 0x81
481 08:56:28.283471 hw id: 0x0000 - pwm id 0x01
482 08:56:28.284145 bl2_stage_init 0xc1
483 08:56:28.284760 bl2_stage_init 0x02
484 08:56:28.285302
485 08:56:28.289174 L0:00000000
486 08:56:28.289786 L1:20000703
487 08:56:28.290386 L2:00008067
488 08:56:28.290908 L3:14000000
489 08:56:28.294550 B2:00402000
490 08:56:28.295173 B1:e0f83180
491 08:56:28.295768
492 08:56:28.296336 TE: 58124
493 08:56:28.296930
494 08:56:28.300087 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
495 08:56:28.300410
496 08:56:28.300709 Board ID = 1
497 08:56:28.305910 Set A53 clk to 24M
498 08:56:28.306460 Set A73 clk to 24M
499 08:56:28.307050 Set clk81 to 24M
500 08:56:28.311347 A53 clk: 1200 MHz
501 08:56:28.311964 A73 clk: 1200 MHz
502 08:56:28.312529 CLK81: 166.6M
503 08:56:28.313113 smccc: 00012a91
504 08:56:28.316997 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
505 08:56:28.322615 board id: 1
506 08:56:28.328368 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
507 08:56:28.339218 fw parse done
508 08:56:28.345469 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
509 08:56:28.387834 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
510 08:56:28.398767 PIEI prepare done
511 08:56:28.399378 fastboot data load
512 08:56:28.400016 fastboot data verify
513 08:56:28.404383 verify result: 266
514 08:56:28.409938 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
515 08:56:28.410544 LPDDR4 probe
516 08:56:28.411089 ddr clk to 1584MHz
517 08:56:28.417920 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
518 08:56:28.455246
519 08:56:28.455861 dmc_version 0001
520 08:56:28.461936 Check phy result
521 08:56:28.467695 INFO : End of CA training
522 08:56:28.468324 INFO : End of initialization
523 08:56:28.473293 INFO : Training has run successfully!
524 08:56:28.473832 Check phy result
525 08:56:28.478946 INFO : End of initialization
526 08:56:28.479543 INFO : End of read enable training
527 08:56:28.484506 INFO : End of fine write leveling
528 08:56:28.490164 INFO : End of Write leveling coarse delay
529 08:56:28.490780 INFO : Training has run successfully!
530 08:56:28.491331 Check phy result
531 08:56:28.495675 INFO : End of initialization
532 08:56:28.496315 INFO : End of read dq deskew training
533 08:56:28.501286 INFO : End of MPR read delay center optimization
534 08:56:28.506894 INFO : End of write delay center optimization
535 08:56:28.512492 INFO : End of read delay center optimization
536 08:56:28.513066 INFO : End of max read latency training
537 08:56:28.518211 INFO : Training has run successfully!
538 08:56:28.518737 1D training succeed
539 08:56:28.527235 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 08:56:28.574887 Check phy result
541 08:56:28.575477 INFO : End of initialization
542 08:56:28.596532 INFO : End of 2D read delay Voltage center optimization
543 08:56:28.616573 INFO : End of 2D read delay Voltage center optimization
544 08:56:28.668481 INFO : End of 2D write delay Voltage center optimization
545 08:56:28.717734 INFO : End of 2D write delay Voltage center optimization
546 08:56:28.723294 INFO : Training has run successfully!
547 08:56:28.723871
548 08:56:28.724441 channel==0
549 08:56:28.728895 RxClkDly_Margin_A0==88 ps 9
550 08:56:28.729467 TxDqDly_Margin_A0==98 ps 10
551 08:56:28.734470 RxClkDly_Margin_A1==88 ps 9
552 08:56:28.735062 TxDqDly_Margin_A1==98 ps 10
553 08:56:28.735598 TrainedVREFDQ_A0==74
554 08:56:28.740265 TrainedVREFDQ_A1==74
555 08:56:28.740854 VrefDac_Margin_A0==25
556 08:56:28.741372 DeviceVref_Margin_A0==40
557 08:56:28.745661 VrefDac_Margin_A1==26
558 08:56:28.746240 DeviceVref_Margin_A1==40
559 08:56:28.746756
560 08:56:28.747265
561 08:56:28.751251 channel==1
562 08:56:28.751840 RxClkDly_Margin_A0==98 ps 10
563 08:56:28.752411 TxDqDly_Margin_A0==98 ps 10
564 08:56:28.756854 RxClkDly_Margin_A1==88 ps 9
565 08:56:28.757433 TxDqDly_Margin_A1==88 ps 9
566 08:56:28.762465 TrainedVREFDQ_A0==77
567 08:56:28.763036 TrainedVREFDQ_A1==77
568 08:56:28.763507 VrefDac_Margin_A0==22
569 08:56:28.768220 DeviceVref_Margin_A0==37
570 08:56:28.768799 VrefDac_Margin_A1==24
571 08:56:28.773696 DeviceVref_Margin_A1==37
572 08:56:28.774219
573 08:56:28.774741 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
574 08:56:28.775246
575 08:56:28.807247 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000016 00000018 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
576 08:56:28.807864 2D training succeed
577 08:56:28.812869 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
578 08:56:28.818465 auto size-- 65535DDR cs0 size: 2048MB
579 08:56:28.819052 DDR cs1 size: 2048MB
580 08:56:28.824305 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
581 08:56:28.824876 cs0 DataBus test pass
582 08:56:28.829674 cs1 DataBus test pass
583 08:56:28.830304 cs0 AddrBus test pass
584 08:56:28.830846 cs1 AddrBus test pass
585 08:56:28.831366
586 08:56:28.835222 100bdlr_step_size ps== 420
587 08:56:28.835819 result report
588 08:56:28.840877 boot times 0Enable ddr reg access
589 08:56:28.846280 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
590 08:56:28.859654 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
591 08:56:29.431709 0.0;M3 CHK:0;cm4_sp_mode 0
592 08:56:29.432483 MVN_1=0x00000000
593 08:56:29.437277 MVN_2=0x00000000
594 08:56:29.442969 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
595 08:56:29.443575 OPS=0x10
596 08:56:29.444179 ring efuse init
597 08:56:29.444733 chipver efuse init
598 08:56:29.448587 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
599 08:56:29.454321 [0.018961 Inits done]
600 08:56:29.454906 secure task start!
601 08:56:29.455468 high task start!
602 08:56:29.458767 low task start!
603 08:56:29.459365 run into bl31
604 08:56:29.465434 NOTICE: BL31: v1.3(release):4fc40b1
605 08:56:29.473172 NOTICE: BL31: Built : 15:58:17, May 22 2019
606 08:56:29.473798 NOTICE: BL31: G12A normal boot!
607 08:56:29.498564 NOTICE: BL31: BL33 decompress pass
608 08:56:29.504267 ERROR: Error initializing runtime service opteed_fast
609 08:56:30.737079
610 08:56:30.737599
611 08:56:30.745563 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
612 08:56:30.746028
613 08:56:30.746454 Model: Libre Computer AML-A311D-CC Alta
614 08:56:30.953984 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
615 08:56:30.977388 DRAM: 2 GiB (effective 3.8 GiB)
616 08:56:31.120423 Core: 408 devices, 31 uclasses, devicetree: separate
617 08:56:31.126341 WDT: Not starting watchdog@f0d0
618 08:56:31.158545 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
619 08:56:31.170888 Loading Environment from FAT... Card did not respond to voltage select! : -110
620 08:56:31.175036 ** Bad device specification mmc 0 **
621 08:56:31.186345 Card did not respond to voltage select! : -110
622 08:56:31.193930 ** Bad device specification mmc 0 **
623 08:56:31.194382 Couldn't find partition mmc 0
624 08:56:31.202108 Card did not respond to voltage select! : -110
625 08:56:31.208054 ** Bad device specification mmc 0 **
626 08:56:31.208703 Couldn't find partition mmc 0
627 08:56:31.212898 Error: could not access storage.
628 08:56:31.556470 Net: eth0: ethernet@ff3f0000
629 08:56:31.557097 starting USB...
630 08:56:31.808240 Bus usb@ff500000: Register 3000140 NbrPorts 3
631 08:56:31.808870 Starting the controller
632 08:56:31.814169 USB XHCI 1.10
633 08:56:33.528271 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
634 08:56:33.528842 bl2_stage_init 0x81
635 08:56:33.533919 hw id: 0x0000 - pwm id 0x01
636 08:56:33.534362 bl2_stage_init 0xc1
637 08:56:33.534769 bl2_stage_init 0x02
638 08:56:33.535165
639 08:56:33.539443 L0:00000000
640 08:56:33.539881 L1:20000703
641 08:56:33.540336 L2:00008067
642 08:56:33.540730 L3:14000000
643 08:56:33.541120 B2:00402000
644 08:56:33.542257 B1:e0f83180
645 08:56:33.542688
646 08:56:33.543088 TE: 58150
647 08:56:33.543484
648 08:56:33.553327 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
649 08:56:33.553771
650 08:56:33.554172 Board ID = 1
651 08:56:33.554583 Set A53 clk to 24M
652 08:56:33.554983 Set A73 clk to 24M
653 08:56:33.558943 Set clk81 to 24M
654 08:56:33.559386 A53 clk: 1200 MHz
655 08:56:33.559783 A73 clk: 1200 MHz
656 08:56:33.564473 CLK81: 166.6M
657 08:56:33.564908 smccc: 00012aab
658 08:56:33.570005 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
659 08:56:33.570442 board id: 1
660 08:56:33.575606 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
661 08:56:33.589386 fw parse done
662 08:56:33.595296 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
663 08:56:33.637942 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
664 08:56:33.648833 PIEI prepare done
665 08:56:33.649260 fastboot data load
666 08:56:33.649660 fastboot data verify
667 08:56:33.654561 verify result: 266
668 08:56:33.660075 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
669 08:56:33.660501 LPDDR4 probe
670 08:56:33.660895 ddr clk to 1584MHz
671 08:56:33.668184 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
672 08:56:33.705355
673 08:56:33.705786 dmc_version 0001
674 08:56:33.712064 Check phy result
675 08:56:33.717843 INFO : End of CA training
676 08:56:33.718272 INFO : End of initialization
677 08:56:33.723513 INFO : Training has run successfully!
678 08:56:33.723936 Check phy result
679 08:56:33.729165 INFO : End of initialization
680 08:56:33.729596 INFO : End of read enable training
681 08:56:33.732373 INFO : End of fine write leveling
682 08:56:33.737862 INFO : End of Write leveling coarse delay
683 08:56:33.743492 INFO : Training has run successfully!
684 08:56:33.743916 Check phy result
685 08:56:33.744349 INFO : End of initialization
686 08:56:33.749202 INFO : End of read dq deskew training
687 08:56:33.754856 INFO : End of MPR read delay center optimization
688 08:56:33.755288 INFO : End of write delay center optimization
689 08:56:33.760313 INFO : End of read delay center optimization
690 08:56:33.765893 INFO : End of max read latency training
691 08:56:33.766322 INFO : Training has run successfully!
692 08:56:33.771571 1D training succeed
693 08:56:33.777548 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
694 08:56:33.825079 Check phy result
695 08:56:33.825511 INFO : End of initialization
696 08:56:33.847580 INFO : End of 2D read delay Voltage center optimization
697 08:56:33.867699 INFO : End of 2D read delay Voltage center optimization
698 08:56:33.919610 INFO : End of 2D write delay Voltage center optimization
699 08:56:33.969042 INFO : End of 2D write delay Voltage center optimization
700 08:56:33.974389 INFO : Training has run successfully!
701 08:56:33.974820
702 08:56:33.975216 channel==0
703 08:56:33.980061 RxClkDly_Margin_A0==88 ps 9
704 08:56:33.980502 TxDqDly_Margin_A0==98 ps 10
705 08:56:33.983580 RxClkDly_Margin_A1==88 ps 9
706 08:56:33.984037 TxDqDly_Margin_A1==98 ps 10
707 08:56:33.988816 TrainedVREFDQ_A0==74
708 08:56:33.989245 TrainedVREFDQ_A1==74
709 08:56:33.994487 VrefDac_Margin_A0==24
710 08:56:33.994925 DeviceVref_Margin_A0==40
711 08:56:33.995320 VrefDac_Margin_A1==24
712 08:56:33.999959 DeviceVref_Margin_A1==40
713 08:56:34.000416
714 08:56:34.000813
715 08:56:34.001206 channel==1
716 08:56:34.001592 RxClkDly_Margin_A0==98 ps 10
717 08:56:34.003957 TxDqDly_Margin_A0==98 ps 10
718 08:56:34.009625 RxClkDly_Margin_A1==88 ps 9
719 08:56:34.010048 TxDqDly_Margin_A1==88 ps 9
720 08:56:34.010443 TrainedVREFDQ_A0==77
721 08:56:34.015249 TrainedVREFDQ_A1==77
722 08:56:34.015678 VrefDac_Margin_A0==22
723 08:56:34.020657 DeviceVref_Margin_A0==37
724 08:56:34.021085 VrefDac_Margin_A1==24
725 08:56:34.021472 DeviceVref_Margin_A1==37
726 08:56:34.021857
727 08:56:34.029779 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
728 08:56:34.030207
729 08:56:34.055710 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000019 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
730 08:56:34.061246 2D training succeed
731 08:56:34.064752 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
732 08:56:34.070268 auto size-- 65535DDR cs0 size: 2048MB
733 08:56:34.070696 DDR cs1 size: 2048MB
734 08:56:34.075865 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
735 08:56:34.076326 cs0 DataBus test pass
736 08:56:34.076722 cs1 DataBus test pass
737 08:56:34.081452 cs0 AddrBus test pass
738 08:56:34.081876 cs1 AddrBus test pass
739 08:56:34.082268
740 08:56:34.087070 100bdlr_step_size ps== 420
741 08:56:34.087504 result report
742 08:56:34.087896 boot times 0Enable ddr reg access
743 08:56:34.097233 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
744 08:56:34.110691 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
745 08:56:34.682658 0.0;M3 CHK:0;cm4_sp_mode 0
746 08:56:34.683213 MVN_1=0x00000000
747 08:56:34.688199 MVN_2=0x00000000
748 08:56:34.693928 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
749 08:56:34.694381 OPS=0x10
750 08:56:34.694776 ring efuse init
751 08:56:34.695165 chipver efuse init
752 08:56:34.699544 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
753 08:56:34.705119 [0.018961 Inits done]
754 08:56:34.705548 secure task start!
755 08:56:34.705941 high task start!
756 08:56:34.709749 low task start!
757 08:56:34.710171 run into bl31
758 08:56:34.716383 NOTICE: BL31: v1.3(release):4fc40b1
759 08:56:34.724200 NOTICE: BL31: Built : 15:58:17, May 22 2019
760 08:56:34.724630 NOTICE: BL31: G12A normal boot!
761 08:56:34.749547 NOTICE: BL31: BL33 decompress pass
762 08:56:34.755214 ERROR: Error initializing runtime service opteed_fast
763 08:56:35.988237
764 08:56:35.988784
765 08:56:35.996575 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
766 08:56:35.997028
767 08:56:35.997439 Model: Libre Computer AML-A311D-CC Alta
768 08:56:36.205081 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
769 08:56:36.228416 DRAM: 2 GiB (effective 3.8 GiB)
770 08:56:36.371365 Core: 408 devices, 31 uclasses, devicetree: separate
771 08:56:36.377244 WDT: Not starting watchdog@f0d0
772 08:56:36.409489 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
773 08:56:36.421945 Loading Environment from FAT... Card did not respond to voltage select! : -110
774 08:56:36.426931 ** Bad device specification mmc 0 **
775 08:56:36.437250 Card did not respond to voltage select! : -110
776 08:56:36.444907 ** Bad device specification mmc 0 **
777 08:56:36.445347 Couldn't find partition mmc 0
778 08:56:36.453303 Card did not respond to voltage select! : -110
779 08:56:36.458776 ** Bad device specification mmc 0 **
780 08:56:36.459211 Couldn't find partition mmc 0
781 08:56:36.463867 Error: could not access storage.
782 08:56:36.807386 Net: eth0: ethernet@ff3f0000
783 08:56:36.807964 starting USB...
784 08:56:37.059161 Bus usb@ff500000: Register 3000140 NbrPorts 3
785 08:56:37.059693 Starting the controller
786 08:56:37.066127 USB XHCI 1.10
787 08:56:39.229535 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
788 08:56:39.230113 bl2_stage_init 0x01
789 08:56:39.230538 bl2_stage_init 0x81
790 08:56:39.235110 hw id: 0x0000 - pwm id 0x01
791 08:56:39.235554 bl2_stage_init 0xc1
792 08:56:39.235967 bl2_stage_init 0x02
793 08:56:39.236427
794 08:56:39.240638 L0:00000000
795 08:56:39.241072 L1:20000703
796 08:56:39.241482 L2:00008067
797 08:56:39.241885 L3:14000000
798 08:56:39.243736 B2:00402000
799 08:56:39.244228 B1:e0f83180
800 08:56:39.244643
801 08:56:39.245054 TE: 58167
802 08:56:39.245453
803 08:56:39.254911 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
804 08:56:39.255352
805 08:56:39.255765 Board ID = 1
806 08:56:39.256202 Set A53 clk to 24M
807 08:56:39.256604 Set A73 clk to 24M
808 08:56:39.260401 Set clk81 to 24M
809 08:56:39.260843 A53 clk: 1200 MHz
810 08:56:39.261251 A73 clk: 1200 MHz
811 08:56:39.264021 CLK81: 166.6M
812 08:56:39.264462 smccc: 00012abe
813 08:56:39.269676 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
814 08:56:39.275189 board id: 1
815 08:56:39.280224 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
816 08:56:39.290772 fw parse done
817 08:56:39.296761 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
818 08:56:39.339370 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
819 08:56:39.350270 PIEI prepare done
820 08:56:39.350713 fastboot data load
821 08:56:39.351125 fastboot data verify
822 08:56:39.355867 verify result: 266
823 08:56:39.361478 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
824 08:56:39.361916 LPDDR4 probe
825 08:56:39.362322 ddr clk to 1584MHz
826 08:56:39.369444 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
827 08:56:39.406761
828 08:56:39.407222 dmc_version 0001
829 08:56:39.413390 Check phy result
830 08:56:39.419212 INFO : End of CA training
831 08:56:39.419643 INFO : End of initialization
832 08:56:39.424872 INFO : Training has run successfully!
833 08:56:39.425349 Check phy result
834 08:56:39.430543 INFO : End of initialization
835 08:56:39.430980 INFO : End of read enable training
836 08:56:39.433744 INFO : End of fine write leveling
837 08:56:39.439291 INFO : End of Write leveling coarse delay
838 08:56:39.444897 INFO : Training has run successfully!
839 08:56:39.445331 Check phy result
840 08:56:39.445745 INFO : End of initialization
841 08:56:39.450626 INFO : End of read dq deskew training
842 08:56:39.456143 INFO : End of MPR read delay center optimization
843 08:56:39.456571 INFO : End of write delay center optimization
844 08:56:39.461703 INFO : End of read delay center optimization
845 08:56:39.467291 INFO : End of max read latency training
846 08:56:39.467721 INFO : Training has run successfully!
847 08:56:39.472880 1D training succeed
848 08:56:39.478872 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
849 08:56:39.526447 Check phy result
850 08:56:39.526926 INFO : End of initialization
851 08:56:39.548162 INFO : End of 2D read delay Voltage center optimization
852 08:56:39.567586 INFO : End of 2D read delay Voltage center optimization
853 08:56:39.619600 INFO : End of 2D write delay Voltage center optimization
854 08:56:39.669044 INFO : End of 2D write delay Voltage center optimization
855 08:56:39.674601 INFO : Training has run successfully!
856 08:56:39.675040
857 08:56:39.675452 channel==0
858 08:56:39.680191 RxClkDly_Margin_A0==88 ps 9
859 08:56:39.680620 TxDqDly_Margin_A0==98 ps 10
860 08:56:39.683475 RxClkDly_Margin_A1==88 ps 9
861 08:56:39.683904 TxDqDly_Margin_A1==88 ps 9
862 08:56:39.689273 TrainedVREFDQ_A0==74
863 08:56:39.689755 TrainedVREFDQ_A1==74
864 08:56:39.690172 VrefDac_Margin_A0==25
865 08:56:39.694736 DeviceVref_Margin_A0==40
866 08:56:39.695192 VrefDac_Margin_A1==25
867 08:56:39.700460 DeviceVref_Margin_A1==40
868 08:56:39.700877
869 08:56:39.701270
870 08:56:39.701656 channel==1
871 08:56:39.702035 RxClkDly_Margin_A0==98 ps 10
872 08:56:39.703765 TxDqDly_Margin_A0==88 ps 9
873 08:56:39.709363 RxClkDly_Margin_A1==98 ps 10
874 08:56:39.709786 TxDqDly_Margin_A1==88 ps 9
875 08:56:39.710182 TrainedVREFDQ_A0==75
876 08:56:39.714969 TrainedVREFDQ_A1==77
877 08:56:39.715404 VrefDac_Margin_A0==23
878 08:56:39.720558 DeviceVref_Margin_A0==39
879 08:56:39.720981 VrefDac_Margin_A1==23
880 08:56:39.721369 DeviceVref_Margin_A1==37
881 08:56:39.721752
882 08:56:39.729456 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
883 08:56:39.729882
884 08:56:39.755230 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
885 08:56:39.760826 2D training succeed
886 08:56:39.766419 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
887 08:56:39.766843 auto size-- 65535DDR cs0 size: 2048MB
888 08:56:39.772034 DDR cs1 size: 2048MB
889 08:56:39.772459 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
890 08:56:39.777655 cs0 DataBus test pass
891 08:56:39.778073 cs1 DataBus test pass
892 08:56:39.783236 cs0 AddrBus test pass
893 08:56:39.783651 cs1 AddrBus test pass
894 08:56:39.784077
895 08:56:39.784472 100bdlr_step_size ps== 420
896 08:56:39.788838 result report
897 08:56:39.789254 boot times 0Enable ddr reg access
898 08:56:39.797360 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
899 08:56:39.810844 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
900 08:56:40.384580 0.0;M3 CHK:0;cm4_sp_mode 0
901 08:56:40.385203 MVN_1=0x00000000
902 08:56:40.389997 MVN_2=0x00000000
903 08:56:40.395751 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
904 08:56:40.396242 OPS=0x10
905 08:56:40.396659 ring efuse init
906 08:56:40.397063 chipver efuse init
907 08:56:40.404074 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
908 08:56:40.404525 [0.018961 Inits done]
909 08:56:40.404932 secure task start!
910 08:56:40.411545 high task start!
911 08:56:40.412006 low task start!
912 08:56:40.412421 run into bl31
913 08:56:40.418158 NOTICE: BL31: v1.3(release):4fc40b1
914 08:56:40.425948 NOTICE: BL31: Built : 15:58:17, May 22 2019
915 08:56:40.426387 NOTICE: BL31: G12A normal boot!
916 08:56:40.451377 NOTICE: BL31: BL33 decompress pass
917 08:56:40.457043 ERROR: Error initializing runtime service opteed_fast
918 08:56:41.690074
919 08:56:41.690644
920 08:56:41.698376 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
921 08:56:41.698825
922 08:56:41.699240 Model: Libre Computer AML-A311D-CC Alta
923 08:56:41.906731 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
924 08:56:41.930130 DRAM: 2 GiB (effective 3.8 GiB)
925 08:56:42.073133 Core: 408 devices, 31 uclasses, devicetree: separate
926 08:56:42.078963 WDT: Not starting watchdog@f0d0
927 08:56:42.111187 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
928 08:56:42.123665 Loading Environment from FAT... Card did not respond to voltage select! : -110
929 08:56:42.128632 ** Bad device specification mmc 0 **
930 08:56:42.138972 Card did not respond to voltage select! : -110
931 08:56:42.146636 ** Bad device specification mmc 0 **
932 08:56:42.147074 Couldn't find partition mmc 0
933 08:56:42.154962 Card did not respond to voltage select! : -110
934 08:56:42.160530 ** Bad device specification mmc 0 **
935 08:56:42.160964 Couldn't find partition mmc 0
936 08:56:42.165596 Error: could not access storage.
937 08:56:42.509124 Net: eth0: ethernet@ff3f0000
938 08:56:42.509652 starting USB...
939 08:56:42.760837 Bus usb@ff500000: Register 3000140 NbrPorts 3
940 08:56:42.761309 Starting the controller
941 08:56:42.767819 USB XHCI 1.10
942 08:56:44.629448 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
943 08:56:44.630026 bl2_stage_init 0x81
944 08:56:44.635009 hw id: 0x0000 - pwm id 0x01
945 08:56:44.635450 bl2_stage_init 0xc1
946 08:56:44.635856 bl2_stage_init 0x02
947 08:56:44.636319
948 08:56:44.640601 L0:00000000
949 08:56:44.641036 L1:20000703
950 08:56:44.641441 L2:00008067
951 08:56:44.641841 L3:14000000
952 08:56:44.642239 B2:00402000
953 08:56:44.643396 B1:e0f83180
954 08:56:44.643824
955 08:56:44.644262 TE: 58150
956 08:56:44.644668
957 08:56:44.654551 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
958 08:56:44.654998
959 08:56:44.655414 Board ID = 1
960 08:56:44.655821 Set A53 clk to 24M
961 08:56:44.656259 Set A73 clk to 24M
962 08:56:44.660232 Set clk81 to 24M
963 08:56:44.660665 A53 clk: 1200 MHz
964 08:56:44.661071 A73 clk: 1200 MHz
965 08:56:44.665776 CLK81: 166.6M
966 08:56:44.666208 smccc: 00012aac
967 08:56:44.671378 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
968 08:56:44.671809 board id: 1
969 08:56:44.680008 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
970 08:56:44.690629 fw parse done
971 08:56:44.696620 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
972 08:56:44.739333 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
973 08:56:44.750387 PIEI prepare done
974 08:56:44.750819 fastboot data load
975 08:56:44.751212 fastboot data verify
976 08:56:44.756045 verify result: 266
977 08:56:44.761462 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
978 08:56:44.761883 LPDDR4 probe
979 08:56:44.762270 ddr clk to 1584MHz
980 08:56:44.769596 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
981 08:56:44.806759
982 08:56:44.807188 dmc_version 0001
983 08:56:44.813600 Check phy result
984 08:56:44.819239 INFO : End of CA training
985 08:56:44.819651 INFO : End of initialization
986 08:56:44.824869 INFO : Training has run successfully!
987 08:56:44.825287 Check phy result
988 08:56:44.830458 INFO : End of initialization
989 08:56:44.830872 INFO : End of read enable training
990 08:56:44.833942 INFO : End of fine write leveling
991 08:56:44.839458 INFO : End of Write leveling coarse delay
992 08:56:44.845173 INFO : Training has run successfully!
993 08:56:44.845586 Check phy result
994 08:56:44.845977 INFO : End of initialization
995 08:56:44.850581 INFO : End of read dq deskew training
996 08:56:44.854132 INFO : End of MPR read delay center optimization
997 08:56:44.859753 INFO : End of write delay center optimization
998 08:56:44.860213 INFO : End of read delay center optimization
999 08:56:44.865364 INFO : End of max read latency training
1000 08:56:44.870985 INFO : Training has run successfully!
1001 08:56:44.871406 1D training succeed
1002 08:56:44.878855 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1003 08:56:44.926518 Check phy result
1004 08:56:44.926945 INFO : End of initialization
1005 08:56:44.948225 INFO : End of 2D read delay Voltage center optimization
1006 08:56:44.968391 INFO : End of 2D read delay Voltage center optimization
1007 08:56:45.020577 INFO : End of 2D write delay Voltage center optimization
1008 08:56:45.069753 INFO : End of 2D write delay Voltage center optimization
1009 08:56:45.075450 INFO : Training has run successfully!
1010 08:56:45.075881
1011 08:56:45.076337 channel==0
1012 08:56:45.080916 RxClkDly_Margin_A0==88 ps 9
1013 08:56:45.081350 TxDqDly_Margin_A0==98 ps 10
1014 08:56:45.084292 RxClkDly_Margin_A1==88 ps 9
1015 08:56:45.084725 TxDqDly_Margin_A1==98 ps 10
1016 08:56:45.089833 TrainedVREFDQ_A0==74
1017 08:56:45.090267 TrainedVREFDQ_A1==74
1018 08:56:45.095452 VrefDac_Margin_A0==25
1019 08:56:45.095880 DeviceVref_Margin_A0==40
1020 08:56:45.096321 VrefDac_Margin_A1==25
1021 08:56:45.101045 DeviceVref_Margin_A1==40
1022 08:56:45.101477
1023 08:56:45.101889
1024 08:56:45.102292 channel==1
1025 08:56:45.102690 RxClkDly_Margin_A0==98 ps 10
1026 08:56:45.104546 TxDqDly_Margin_A0==98 ps 10
1027 08:56:45.110151 RxClkDly_Margin_A1==98 ps 10
1028 08:56:45.110583 TxDqDly_Margin_A1==88 ps 9
1029 08:56:45.110992 TrainedVREFDQ_A0==77
1030 08:56:45.115748 TrainedVREFDQ_A1==77
1031 08:56:45.116221 VrefDac_Margin_A0==22
1032 08:56:45.121423 DeviceVref_Margin_A0==37
1033 08:56:45.121849 VrefDac_Margin_A1==22
1034 08:56:45.122249 DeviceVref_Margin_A1==37
1035 08:56:45.122648
1036 08:56:45.130284 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1037 08:56:45.130721
1038 08:56:45.158243 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000019 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1039 08:56:45.158715 2D training succeed
1040 08:56:45.169433 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1041 08:56:45.169873 auto size-- 65535DDR cs0 size: 2048MB
1042 08:56:45.170284 DDR cs1 size: 2048MB
1043 08:56:45.175047 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1044 08:56:45.175476 cs0 DataBus test pass
1045 08:56:45.180650 cs1 DataBus test pass
1046 08:56:45.181083 cs0 AddrBus test pass
1047 08:56:45.186250 cs1 AddrBus test pass
1048 08:56:45.186678
1049 08:56:45.187087 100bdlr_step_size ps== 420
1050 08:56:45.187498 result report
1051 08:56:45.191834 boot times 0Enable ddr reg access
1052 08:56:45.198311 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1053 08:56:45.211763 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1054 08:56:45.784909 0.0;M3 CHK:0;cm4_sp_mode 0
1055 08:56:45.785507 MVN_1=0x00000000
1056 08:56:45.790537 MVN_2=0x00000000
1057 08:56:45.796105 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1058 08:56:45.796576 OPS=0x10
1059 08:56:45.797000 ring efuse init
1060 08:56:45.797410 chipver efuse init
1061 08:56:45.801693 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1062 08:56:45.807390 [0.018961 Inits done]
1063 08:56:45.807840 secure task start!
1064 08:56:45.808299 high task start!
1065 08:56:45.811908 low task start!
1066 08:56:45.812381 run into bl31
1067 08:56:45.818550 NOTICE: BL31: v1.3(release):4fc40b1
1068 08:56:45.826358 NOTICE: BL31: Built : 15:58:17, May 22 2019
1069 08:56:45.826800 NOTICE: BL31: G12A normal boot!
1070 08:56:45.851671 NOTICE: BL31: BL33 decompress pass
1071 08:56:45.857471 ERROR: Error initializing runtime service opteed_fast
1072 08:56:47.090314
1073 08:56:47.090900
1074 08:56:47.098648 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1075 08:56:47.099102
1076 08:56:47.099517 Model: Libre Computer AML-A311D-CC Alta
1077 08:56:47.307061 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1078 08:56:47.330461 DRAM: 2 GiB (effective 3.8 GiB)
1079 08:56:47.473450 Core: 408 devices, 31 uclasses, devicetree: separate
1080 08:56:47.479320 WDT: Not starting watchdog@f0d0
1081 08:56:47.511645 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1082 08:56:47.524050 Loading Environment from FAT... Card did not respond to voltage select! : -110
1083 08:56:47.528991 ** Bad device specification mmc 0 **
1084 08:56:47.539333 Card did not respond to voltage select! : -110
1085 08:56:47.546969 ** Bad device specification mmc 0 **
1086 08:56:47.547407 Couldn't find partition mmc 0
1087 08:56:47.555306 Card did not respond to voltage select! : -110
1088 08:56:47.560861 ** Bad device specification mmc 0 **
1089 08:56:47.561297 Couldn't find partition mmc 0
1090 08:56:47.565902 Error: could not access storage.
1091 08:56:47.908416 Net: eth0: ethernet@ff3f0000
1092 08:56:47.909023 starting USB...
1093 08:56:48.160263 Bus usb@ff500000: Register 3000140 NbrPorts 3
1094 08:56:48.160882 Starting the controller
1095 08:56:48.167135 USB XHCI 1.10
1096 08:56:49.723298 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1097 08:56:49.731678 scanning usb for storage devices... 0 Storage Device(s) found
1099 08:56:49.783260 Hit any key to stop autoboot: 1
1100 08:56:49.784024 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1101 08:56:49.784596 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1102 08:56:49.785049 Setting prompt string to ['=>']
1103 08:56:49.785514 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1104 08:56:49.799092 0
1105 08:56:49.799923 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1106 08:56:49.800432 Sending with 10 millisecond of delay
1108 08:56:50.934868 => setenv autoload no
1109 08:56:50.945602 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
1110 08:56:50.950409 setenv autoload no
1111 08:56:50.951142 Sending with 10 millisecond of delay
1113 08:56:52.747593 => setenv initrd_high 0xffffffff
1114 08:56:52.758349 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1115 08:56:52.759146 setenv initrd_high 0xffffffff
1116 08:56:52.759848 Sending with 10 millisecond of delay
1118 08:56:54.375714 => setenv fdt_high 0xffffffff
1119 08:56:54.386443 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1120 08:56:54.387204 setenv fdt_high 0xffffffff
1121 08:56:54.387903 Sending with 10 millisecond of delay
1123 08:56:54.679700 => dhcp
1124 08:56:54.690388 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1125 08:56:54.691128 dhcp
1126 08:56:54.691553 Speed: 1000, full duplex
1127 08:56:54.691965 BOOTP broadcast 1
1128 08:56:54.698664 DHCP client bound to address 192.168.6.27 (8 ms)
1129 08:56:54.699344 Sending with 10 millisecond of delay
1131 08:56:56.375545 => setenv serverip 192.168.6.2
1132 08:56:56.386367 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1133 08:56:56.387224 setenv serverip 192.168.6.2
1134 08:56:56.387905 Sending with 10 millisecond of delay
1136 08:57:00.110344 => tftpboot 0x01080000 933562/tftp-deploy-yjquvwm7/kernel/uImage
1137 08:57:00.121079 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1138 08:57:00.121847 tftpboot 0x01080000 933562/tftp-deploy-yjquvwm7/kernel/uImage
1139 08:57:00.122298 Speed: 1000, full duplex
1140 08:57:00.122704 Using ethernet@ff3f0000 device
1141 08:57:00.123829 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1142 08:57:00.129300 Filename '933562/tftp-deploy-yjquvwm7/kernel/uImage'.
1143 08:57:00.133320 Load address: 0x1080000
1144 08:57:02.967174 Loading: *################################################## 43.6 MiB
1145 08:57:02.967767 15.4 MiB/s
1146 08:57:02.968253 done
1147 08:57:02.971557 Bytes transferred = 45713984 (2b98a40 hex)
1148 08:57:02.972375 Sending with 10 millisecond of delay
1150 08:57:07.657734 => tftpboot 0x08000000 933562/tftp-deploy-yjquvwm7/ramdisk/ramdisk.cpio.gz.uboot
1151 08:57:07.668436 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1152 08:57:07.669227 tftpboot 0x08000000 933562/tftp-deploy-yjquvwm7/ramdisk/ramdisk.cpio.gz.uboot
1153 08:57:07.669667 Speed: 1000, full duplex
1154 08:57:07.670076 Using ethernet@ff3f0000 device
1155 08:57:07.671082 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1156 08:57:07.683030 Filename '933562/tftp-deploy-yjquvwm7/ramdisk/ramdisk.cpio.gz.uboot'.
1157 08:57:07.683498 Load address: 0x8000000
1158 08:57:14.267677 Loading: *###################T ############################## UDP wrong checksum 00000005 00003901
1159 08:57:19.268397 T UDP wrong checksum 00000005 00003901
1160 08:57:29.271421 T T UDP wrong checksum 00000005 00003901
1161 08:57:49.273238 T T T UDP wrong checksum 00000005 00003901
1162 08:57:55.719518 T T UDP wrong checksum 000000ff 0000a4c1
1163 08:57:55.793674 UDP wrong checksum 000000ff 000037b4
1164 08:58:04.279576 T
1165 08:58:04.280116 Retry count exceeded; starting again
1167 08:58:04.281201 end: 2.4.3 bootloader-commands (duration 00:01:14) [common]
1170 08:58:04.283605 end: 2.4 uboot-commands (duration 00:01:52) [common]
1172 08:58:04.285424 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1174 08:58:04.286750 end: 2 uboot-action (duration 00:01:52) [common]
1176 08:58:04.288785 Cleaning after the job
1177 08:58:04.289510 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933562/tftp-deploy-yjquvwm7/ramdisk
1178 08:58:04.291159 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933562/tftp-deploy-yjquvwm7/kernel
1179 08:58:04.338641 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933562/tftp-deploy-yjquvwm7/dtb
1180 08:58:04.339609 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933562/tftp-deploy-yjquvwm7/nfsrootfs
1181 08:58:04.671454 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/933562/tftp-deploy-yjquvwm7/modules
1182 08:58:04.694209 start: 4.1 power-off (timeout 00:00:30) [common]
1183 08:58:04.695013 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1184 08:58:04.728567 >> OK - accepted request
1185 08:58:04.730817 Returned 0 in 0 seconds
1186 08:58:04.831701 end: 4.1 power-off (duration 00:00:00) [common]
1188 08:58:04.832951 start: 4.2 read-feedback (timeout 00:10:00) [common]
1189 08:58:04.833744 Listened to connection for namespace 'common' for up to 1s
1190 08:58:05.834669 Finalising connection for namespace 'common'
1191 08:58:05.835219 Disconnecting from shell: Finalise
1192 08:58:05.835580 =>
1193 08:58:05.936334 end: 4.2 read-feedback (duration 00:00:01) [common]
1194 08:58:05.936867 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/933562
1195 08:58:08.478166 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/933562
1196 08:58:08.478791 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.