Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 09:55:13.760300 lava-dispatcher, installed at version: 2024.01
2 09:55:13.761285 start: 0 validate
3 09:55:13.761929 Start time: 2024-11-05 09:55:13.761891+00:00 (UTC)
4 09:55:13.762595 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 09:55:13.763262 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 09:55:13.801305 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 09:55:13.802015 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-401-g1596ed05f2f47%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 09:55:13.826612 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 09:55:13.827360 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-401-g1596ed05f2f47%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 09:55:13.850911 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 09:55:13.851516 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 09:55:13.878825 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 09:55:13.879303 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-401-g1596ed05f2f47%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 09:55:13.912215 validate duration: 0.15
16 09:55:13.913101 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:55:13.913406 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:55:13.913674 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:55:13.914273 Not decompressing ramdisk as can be used compressed.
20 09:55:13.914675 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 09:55:13.914932 saving as /var/lib/lava/dispatcher/tmp/939283/tftp-deploy-sgxvwu_s/ramdisk/initrd.cpio.gz
22 09:55:13.915183 total size: 4775763 (4 MB)
23 09:55:13.951957 progress 0 % (0 MB)
24 09:55:13.955639 progress 5 % (0 MB)
25 09:55:13.958971 progress 10 % (0 MB)
26 09:55:13.962181 progress 15 % (0 MB)
27 09:55:13.965680 progress 20 % (0 MB)
28 09:55:13.968850 progress 25 % (1 MB)
29 09:55:13.971940 progress 30 % (1 MB)
30 09:55:13.975510 progress 35 % (1 MB)
31 09:55:13.978617 progress 40 % (1 MB)
32 09:55:13.981730 progress 45 % (2 MB)
33 09:55:13.984858 progress 50 % (2 MB)
34 09:55:13.988346 progress 55 % (2 MB)
35 09:55:13.991488 progress 60 % (2 MB)
36 09:55:13.994569 progress 65 % (2 MB)
37 09:55:13.998039 progress 70 % (3 MB)
38 09:55:14.001103 progress 75 % (3 MB)
39 09:55:14.004266 progress 80 % (3 MB)
40 09:55:14.007364 progress 85 % (3 MB)
41 09:55:14.010845 progress 90 % (4 MB)
42 09:55:14.013746 progress 95 % (4 MB)
43 09:55:14.016602 progress 100 % (4 MB)
44 09:55:14.017212 4 MB downloaded in 0.10 s (44.65 MB/s)
45 09:55:14.017747 end: 1.1.1 http-download (duration 00:00:00) [common]
47 09:55:14.018626 end: 1.1 download-retry (duration 00:00:00) [common]
48 09:55:14.018913 start: 1.2 download-retry (timeout 00:10:00) [common]
49 09:55:14.019179 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 09:55:14.019645 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-401-g1596ed05f2f47/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 09:55:14.019886 saving as /var/lib/lava/dispatcher/tmp/939283/tftp-deploy-sgxvwu_s/kernel/zImage
52 09:55:14.020107 total size: 11457024 (10 MB)
53 09:55:14.020314 No compression specified
54 09:55:14.054380 progress 0 % (0 MB)
55 09:55:14.061858 progress 5 % (0 MB)
56 09:55:14.069148 progress 10 % (1 MB)
57 09:55:14.076514 progress 15 % (1 MB)
58 09:55:14.083628 progress 20 % (2 MB)
59 09:55:14.090991 progress 25 % (2 MB)
60 09:55:14.097992 progress 30 % (3 MB)
61 09:55:14.105412 progress 35 % (3 MB)
62 09:55:14.112456 progress 40 % (4 MB)
63 09:55:14.120356 progress 45 % (4 MB)
64 09:55:14.127379 progress 50 % (5 MB)
65 09:55:14.134765 progress 55 % (6 MB)
66 09:55:14.141785 progress 60 % (6 MB)
67 09:55:14.149199 progress 65 % (7 MB)
68 09:55:14.156247 progress 70 % (7 MB)
69 09:55:14.163628 progress 75 % (8 MB)
70 09:55:14.170618 progress 80 % (8 MB)
71 09:55:14.177964 progress 85 % (9 MB)
72 09:55:14.184927 progress 90 % (9 MB)
73 09:55:14.192328 progress 95 % (10 MB)
74 09:55:14.199027 progress 100 % (10 MB)
75 09:55:14.199631 10 MB downloaded in 0.18 s (60.87 MB/s)
76 09:55:14.200116 end: 1.2.1 http-download (duration 00:00:00) [common]
78 09:55:14.200944 end: 1.2 download-retry (duration 00:00:00) [common]
79 09:55:14.201214 start: 1.3 download-retry (timeout 00:10:00) [common]
80 09:55:14.201476 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 09:55:14.201951 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-401-g1596ed05f2f47/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 09:55:14.202227 saving as /var/lib/lava/dispatcher/tmp/939283/tftp-deploy-sgxvwu_s/dtb/am335x-boneblack.dtb
83 09:55:14.202431 total size: 70568 (0 MB)
84 09:55:14.202635 No compression specified
85 09:55:14.235583 progress 46 % (0 MB)
86 09:55:14.236384 progress 92 % (0 MB)
87 09:55:14.237046 progress 100 % (0 MB)
88 09:55:14.237420 0 MB downloaded in 0.03 s (1.92 MB/s)
89 09:55:14.237883 end: 1.3.1 http-download (duration 00:00:00) [common]
91 09:55:14.238694 end: 1.3 download-retry (duration 00:00:00) [common]
92 09:55:14.238955 start: 1.4 download-retry (timeout 00:10:00) [common]
93 09:55:14.239217 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 09:55:14.239665 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 09:55:14.239898 saving as /var/lib/lava/dispatcher/tmp/939283/tftp-deploy-sgxvwu_s/nfsrootfs/full.rootfs.tar
96 09:55:14.240098 total size: 117747780 (112 MB)
97 09:55:14.240303 Using unxz to decompress xz
98 09:55:14.267943 progress 0 % (0 MB)
99 09:55:14.980799 progress 5 % (5 MB)
100 09:55:15.712795 progress 10 % (11 MB)
101 09:55:16.482913 progress 15 % (16 MB)
102 09:55:17.194704 progress 20 % (22 MB)
103 09:55:17.769735 progress 25 % (28 MB)
104 09:55:18.567057 progress 30 % (33 MB)
105 09:55:19.364564 progress 35 % (39 MB)
106 09:55:19.717540 progress 40 % (44 MB)
107 09:55:20.067063 progress 45 % (50 MB)
108 09:55:20.722803 progress 50 % (56 MB)
109 09:55:21.532695 progress 55 % (61 MB)
110 09:55:22.262625 progress 60 % (67 MB)
111 09:55:22.974413 progress 65 % (73 MB)
112 09:55:23.890122 progress 70 % (78 MB)
113 09:55:24.823135 progress 75 % (84 MB)
114 09:55:25.731756 progress 80 % (89 MB)
115 09:55:26.481241 progress 85 % (95 MB)
116 09:55:27.421548 progress 90 % (101 MB)
117 09:55:28.212717 progress 95 % (106 MB)
118 09:55:29.027063 progress 100 % (112 MB)
119 09:55:29.039307 112 MB downloaded in 14.80 s (7.59 MB/s)
120 09:55:29.039885 end: 1.4.1 http-download (duration 00:00:15) [common]
122 09:55:29.040709 end: 1.4 download-retry (duration 00:00:15) [common]
123 09:55:29.040974 start: 1.5 download-retry (timeout 00:09:45) [common]
124 09:55:29.041235 start: 1.5.1 http-download (timeout 00:09:45) [common]
125 09:55:29.041772 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-401-g1596ed05f2f47/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 09:55:29.042280 saving as /var/lib/lava/dispatcher/tmp/939283/tftp-deploy-sgxvwu_s/modules/modules.tar
127 09:55:29.042684 total size: 6609980 (6 MB)
128 09:55:29.043118 Using unxz to decompress xz
129 09:55:29.079418 progress 0 % (0 MB)
130 09:55:29.114211 progress 5 % (0 MB)
131 09:55:29.158025 progress 10 % (0 MB)
132 09:55:29.200989 progress 15 % (0 MB)
133 09:55:29.245592 progress 20 % (1 MB)
134 09:55:29.293190 progress 25 % (1 MB)
135 09:55:29.337221 progress 30 % (1 MB)
136 09:55:29.380314 progress 35 % (2 MB)
137 09:55:29.424668 progress 40 % (2 MB)
138 09:55:29.467993 progress 45 % (2 MB)
139 09:55:29.511238 progress 50 % (3 MB)
140 09:55:29.553710 progress 55 % (3 MB)
141 09:55:29.603103 progress 60 % (3 MB)
142 09:55:29.645104 progress 65 % (4 MB)
143 09:55:29.687995 progress 70 % (4 MB)
144 09:55:29.733720 progress 75 % (4 MB)
145 09:55:29.776395 progress 80 % (5 MB)
146 09:55:29.818828 progress 85 % (5 MB)
147 09:55:29.861958 progress 90 % (5 MB)
148 09:55:29.904841 progress 95 % (6 MB)
149 09:55:29.948355 progress 100 % (6 MB)
150 09:55:29.961924 6 MB downloaded in 0.92 s (6.86 MB/s)
151 09:55:29.962930 end: 1.5.1 http-download (duration 00:00:01) [common]
153 09:55:29.964673 end: 1.5 download-retry (duration 00:00:01) [common]
154 09:55:29.965239 start: 1.6 prepare-tftp-overlay (timeout 00:09:44) [common]
155 09:55:29.965800 start: 1.6.1 extract-nfsrootfs (timeout 00:09:44) [common]
156 09:55:46.957421 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/939283/extract-nfsrootfs-qtsz7v_s
157 09:55:46.958054 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
158 09:55:46.958351 start: 1.6.2 lava-overlay (timeout 00:09:27) [common]
159 09:55:46.959051 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq
160 09:55:46.959502 makedir: /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin
161 09:55:46.959833 makedir: /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/tests
162 09:55:46.960141 makedir: /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/results
163 09:55:46.960483 Creating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-add-keys
164 09:55:46.961010 Creating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-add-sources
165 09:55:46.961548 Creating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-background-process-start
166 09:55:46.962121 Creating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-background-process-stop
167 09:55:46.962659 Creating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-common-functions
168 09:55:46.963146 Creating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-echo-ipv4
169 09:55:46.963624 Creating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-install-packages
170 09:55:46.964102 Creating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-installed-packages
171 09:55:46.964576 Creating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-os-build
172 09:55:46.965054 Creating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-probe-channel
173 09:55:46.965556 Creating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-probe-ip
174 09:55:46.966110 Creating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-target-ip
175 09:55:46.966675 Creating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-target-mac
176 09:55:46.967166 Creating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-target-storage
177 09:55:46.967654 Creating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-test-case
178 09:55:46.968134 Creating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-test-event
179 09:55:46.968605 Creating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-test-feedback
180 09:55:46.969078 Creating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-test-raise
181 09:55:46.969571 Creating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-test-reference
182 09:55:46.970102 Creating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-test-runner
183 09:55:46.970594 Creating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-test-set
184 09:55:46.971078 Creating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-test-shell
185 09:55:46.971569 Updating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-add-keys (debian)
186 09:55:46.972103 Updating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-add-sources (debian)
187 09:55:46.972609 Updating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-install-packages (debian)
188 09:55:46.973109 Updating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-installed-packages (debian)
189 09:55:46.973602 Updating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/bin/lava-os-build (debian)
190 09:55:46.974068 Creating /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/environment
191 09:55:46.974440 LAVA metadata
192 09:55:46.974696 - LAVA_JOB_ID=939283
193 09:55:46.974914 - LAVA_DISPATCHER_IP=192.168.6.3
194 09:55:46.975273 start: 1.6.2.1 ssh-authorize (timeout 00:09:27) [common]
195 09:55:46.976202 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 09:55:46.976513 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:27) [common]
197 09:55:46.976719 skipped lava-vland-overlay
198 09:55:46.976959 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 09:55:46.977210 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:27) [common]
200 09:55:46.977426 skipped lava-multinode-overlay
201 09:55:46.977665 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 09:55:46.977963 start: 1.6.2.4 test-definition (timeout 00:09:27) [common]
203 09:55:46.978274 Loading test definitions
204 09:55:46.978593 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:27) [common]
205 09:55:46.978865 Using /lava-939283 at stage 0
206 09:55:46.980089 uuid=939283_1.6.2.4.1 testdef=None
207 09:55:46.980424 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 09:55:46.980723 start: 1.6.2.4.2 test-overlay (timeout 00:09:27) [common]
209 09:55:46.982541 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 09:55:46.983406 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:27) [common]
212 09:55:46.985694 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 09:55:46.986755 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:27) [common]
215 09:55:46.989594 runner path: /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/0/tests/0_timesync-off test_uuid 939283_1.6.2.4.1
216 09:55:46.990535 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 09:55:46.991645 start: 1.6.2.4.5 git-repo-action (timeout 00:09:27) [common]
219 09:55:46.991988 Using /lava-939283 at stage 0
220 09:55:46.992501 Fetching tests from https://github.com/kernelci/test-definitions.git
221 09:55:46.992912 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/0/tests/1_kselftest-dt'
222 09:55:50.450052 Running '/usr/bin/git checkout kernelci.org
223 09:55:50.816869 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 09:55:50.818347 uuid=939283_1.6.2.4.5 testdef=None
225 09:55:50.818689 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 09:55:50.819433 start: 1.6.2.4.6 test-overlay (timeout 00:09:23) [common]
228 09:55:50.822647 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 09:55:50.823471 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:23) [common]
231 09:55:50.827264 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 09:55:50.828115 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:23) [common]
234 09:55:50.831713 runner path: /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/0/tests/1_kselftest-dt test_uuid 939283_1.6.2.4.5
235 09:55:50.831995 BOARD='beaglebone-black'
236 09:55:50.832198 BRANCH='tip'
237 09:55:50.832393 SKIPFILE='/dev/null'
238 09:55:50.832591 SKIP_INSTALL='True'
239 09:55:50.832785 TESTPROG_URL='http://storage.kernelci.org/tip/master/v6.12-rc6-401-g1596ed05f2f47/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 09:55:50.832982 TST_CASENAME=''
241 09:55:50.833176 TST_CMDFILES='dt'
242 09:55:50.833713 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 09:55:50.834520 Creating lava-test-runner.conf files
245 09:55:50.834722 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/939283/lava-overlay-jnyd3kjq/lava-939283/0 for stage 0
246 09:55:50.835062 - 0_timesync-off
247 09:55:50.835300 - 1_kselftest-dt
248 09:55:50.835624 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 09:55:50.835900 start: 1.6.2.5 compress-overlay (timeout 00:09:23) [common]
250 09:56:14.268860 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
251 09:56:14.269284 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:00) [common]
252 09:56:14.269549 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 09:56:14.269839 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
254 09:56:14.270111 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:00) [common]
255 09:56:14.634975 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 09:56:14.635456 start: 1.6.4 extract-modules (timeout 00:08:59) [common]
257 09:56:14.635709 extracting modules file /var/lib/lava/dispatcher/tmp/939283/tftp-deploy-sgxvwu_s/modules/modules.tar to /var/lib/lava/dispatcher/tmp/939283/extract-nfsrootfs-qtsz7v_s
258 09:56:15.549015 extracting modules file /var/lib/lava/dispatcher/tmp/939283/tftp-deploy-sgxvwu_s/modules/modules.tar to /var/lib/lava/dispatcher/tmp/939283/extract-overlay-ramdisk-kmvtd_ys/ramdisk
259 09:56:16.515057 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 09:56:16.515516 start: 1.6.5 apply-overlay-tftp (timeout 00:08:57) [common]
261 09:56:16.515795 [common] Applying overlay to NFS
262 09:56:16.516011 [common] Applying overlay /var/lib/lava/dispatcher/tmp/939283/compress-overlay-bwnxdyzt/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/939283/extract-nfsrootfs-qtsz7v_s
263 09:56:19.295842 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 09:56:19.296323 start: 1.6.6 prepare-kernel (timeout 00:08:55) [common]
265 09:56:19.296593 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:55) [common]
266 09:56:19.296870 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 09:56:19.297119 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 09:56:19.297375 start: 1.6.7 configure-preseed-file (timeout 00:08:55) [common]
269 09:56:19.297622 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 09:56:19.297900 start: 1.6.8 compress-ramdisk (timeout 00:08:55) [common]
271 09:56:19.298152 Building ramdisk /var/lib/lava/dispatcher/tmp/939283/extract-overlay-ramdisk-kmvtd_ys/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/939283/extract-overlay-ramdisk-kmvtd_ys/ramdisk
272 09:56:20.307115 >> 74900 blocks
273 09:56:25.479995 Adding RAMdisk u-boot header.
274 09:56:25.480449 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/939283/extract-overlay-ramdisk-kmvtd_ys/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/939283/extract-overlay-ramdisk-kmvtd_ys/ramdisk.cpio.gz.uboot
275 09:56:25.635070 output: Image Name:
276 09:56:25.635463 output: Created: Tue Nov 5 09:56:25 2024
277 09:56:25.635671 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 09:56:25.635876 output: Data Size: 14794147 Bytes = 14447.41 KiB = 14.11 MiB
279 09:56:25.636077 output: Load Address: 00000000
280 09:56:25.636277 output: Entry Point: 00000000
281 09:56:25.636474 output:
282 09:56:25.637090 rename /var/lib/lava/dispatcher/tmp/939283/extract-overlay-ramdisk-kmvtd_ys/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/939283/tftp-deploy-sgxvwu_s/ramdisk/ramdisk.cpio.gz.uboot
283 09:56:25.637509 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 09:56:25.637796 end: 1.6 prepare-tftp-overlay (duration 00:00:56) [common]
285 09:56:25.638409 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:48) [common]
286 09:56:25.638893 No LXC device requested
287 09:56:25.639394 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 09:56:25.639897 start: 1.8 deploy-device-env (timeout 00:08:48) [common]
289 09:56:25.640384 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 09:56:25.640788 Checking files for TFTP limit of 4294967296 bytes.
291 09:56:25.643571 end: 1 tftp-deploy (duration 00:01:12) [common]
292 09:56:25.644152 start: 2 uboot-action (timeout 00:05:00) [common]
293 09:56:25.644673 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 09:56:25.645167 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 09:56:25.645660 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 09:56:25.646436 substitutions:
297 09:56:25.646857 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 09:56:25.647257 - {DTB_ADDR}: 0x88000000
299 09:56:25.647651 - {DTB}: 939283/tftp-deploy-sgxvwu_s/dtb/am335x-boneblack.dtb
300 09:56:25.648041 - {INITRD}: 939283/tftp-deploy-sgxvwu_s/ramdisk/ramdisk.cpio.gz.uboot
301 09:56:25.648429 - {KERNEL_ADDR}: 0x82000000
302 09:56:25.648815 - {KERNEL}: 939283/tftp-deploy-sgxvwu_s/kernel/zImage
303 09:56:25.649202 - {LAVA_MAC}: None
304 09:56:25.649622 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/939283/extract-nfsrootfs-qtsz7v_s
305 09:56:25.650048 - {NFS_SERVER_IP}: 192.168.6.3
306 09:56:25.650438 - {PRESEED_CONFIG}: None
307 09:56:25.650823 - {PRESEED_LOCAL}: None
308 09:56:25.651203 - {RAMDISK_ADDR}: 0x83000000
309 09:56:25.651588 - {RAMDISK}: 939283/tftp-deploy-sgxvwu_s/ramdisk/ramdisk.cpio.gz.uboot
310 09:56:25.651980 - {ROOT_PART}: None
311 09:56:25.652359 - {ROOT}: None
312 09:56:25.652740 - {SERVER_IP}: 192.168.6.3
313 09:56:25.653122 - {TEE_ADDR}: 0x83000000
314 09:56:25.653501 - {TEE}: None
315 09:56:25.653906 Parsed boot commands:
316 09:56:25.654282 - setenv autoload no
317 09:56:25.654664 - setenv initrd_high 0xffffffff
318 09:56:25.655044 - setenv fdt_high 0xffffffff
319 09:56:25.655419 - dhcp
320 09:56:25.655797 - setenv serverip 192.168.6.3
321 09:56:25.656174 - tftp 0x82000000 939283/tftp-deploy-sgxvwu_s/kernel/zImage
322 09:56:25.656552 - tftp 0x83000000 939283/tftp-deploy-sgxvwu_s/ramdisk/ramdisk.cpio.gz.uboot
323 09:56:25.656931 - setenv initrd_size ${filesize}
324 09:56:25.657309 - tftp 0x88000000 939283/tftp-deploy-sgxvwu_s/dtb/am335x-boneblack.dtb
325 09:56:25.657686 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/939283/extract-nfsrootfs-qtsz7v_s,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 09:56:25.658102 - bootz 0x82000000 0x83000000 0x88000000
327 09:56:25.658590 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 09:56:25.660040 start: 2.3 connect-device (timeout 00:05:00) [common]
330 09:56:25.660453 [common] connect-device Connecting to device using 'telnet conserv3 3002'
331 09:56:25.675558 Setting prompt string to ['lava-test: # ']
332 09:56:25.677013 end: 2.3 connect-device (duration 00:00:00) [common]
333 09:56:25.677598 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 09:56:25.678209 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 09:56:25.678732 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 09:56:25.679899 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-05'
337 09:56:25.717331 >> OK - accepted request
338 09:56:25.719308 Returned 0 in 0 seconds
339 09:56:25.820346 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 09:56:25.821972 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 09:56:25.822600 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 09:56:25.823125 Setting prompt string to ['Hit any key to stop autoboot']
344 09:56:25.823586 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 09:56:25.825144 Trying 192.168.56.22...
346 09:56:25.825632 Connected to conserv3.
347 09:56:25.826077 Escape character is '^]'.
348 09:56:25.826491
349 09:56:25.826907 ser2net port telnet,3002 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 09:56:25.827313
351 09:56:33.675124
352 09:56:33.681550 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
353 09:56:33.682116 Trying to boot from MMC1
354 09:56:37.731663
355 09:56:37.738394 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
356 09:56:37.738973 Trying to boot from MMC1
357 09:56:40.435601
358 09:56:40.442391 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
359 09:56:40.442951 Trying to boot from MMC1
360 09:56:41.026468
361 09:56:41.027076
362 09:56:41.032071 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
363 09:56:41.032604
364 09:56:41.033073 CPU : AM335X-GP rev 2.0
365 09:56:41.037176 Model: TI AM335x BeagleBone Black
366 09:56:41.037680 DRAM: 512 MiB
367 09:56:41.117139 Core: 160 devices, 18 uclasses, devicetree: separate
368 09:56:41.130149 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
369 09:56:41.531643 NAND: 0 MiB
370 09:56:41.542079 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
371 09:56:41.639185 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
372 09:56:41.660437 <ethaddr> not set. Validating first E-fuse MAC
373 09:56:41.690845 Net: eth2: ethernet@4a100000, eth3: usb_ether
375 09:56:41.749480 Hit any key to stop autoboot: 2
376 09:56:41.750492 end: 2.4.2 bootloader-interrupt (duration 00:00:16) [common]
377 09:56:41.751170 start: 2.4.3 bootloader-commands (timeout 00:04:44) [common]
378 09:56:41.751697 Setting prompt string to ['=>']
379 09:56:41.752224 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:44)
380 09:56:41.758636 0
381 09:56:41.759610 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
382 09:56:41.760179 Sending with 10 millisecond of delay
384 09:56:42.895004 => setenv autoload no
385 09:56:42.905893 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:43)
386 09:56:42.911365 setenv autoload no
387 09:56:42.912131 Sending with 10 millisecond of delay
389 09:56:44.712267 => setenv initrd_high 0xffffffff
390 09:56:44.723066 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:41)
391 09:56:44.723943 setenv initrd_high 0xffffffff
392 09:56:44.724658 Sending with 10 millisecond of delay
394 09:56:46.341678 => setenv fdt_high 0xffffffff
395 09:56:46.352508 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
396 09:56:46.353379 setenv fdt_high 0xffffffff
397 09:56:46.354141 Sending with 10 millisecond of delay
399 09:56:46.646110 => dhcp
400 09:56:46.656886 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
401 09:56:46.657748 dhcp
402 09:56:46.659751 link up on port 0, speed 100, full duplex
403 09:56:46.660218 BOOTP broadcast 1
404 09:56:46.911931 BOOTP broadcast 2
405 09:56:47.413950 BOOTP broadcast 3
406 09:56:48.415852 BOOTP broadcast 4
407 09:56:48.491996 DHCP client bound to address 192.168.6.8 (1830 ms)
408 09:56:48.492875 Sending with 10 millisecond of delay
410 09:56:50.169660 => setenv serverip 192.168.6.3
411 09:56:50.180464 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:35)
412 09:56:50.181281 setenv serverip 192.168.6.3
413 09:56:50.182008 Sending with 10 millisecond of delay
415 09:56:53.664868 => tftp 0x82000000 939283/tftp-deploy-sgxvwu_s/kernel/zImage
416 09:56:53.675658 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:32)
417 09:56:53.676560 tftp 0x82000000 939283/tftp-deploy-sgxvwu_s/kernel/zImage
418 09:56:53.676986 link up on port 0, speed 100, full duplex
419 09:56:53.680175 Using ethernet@4a100000 device
420 09:56:53.685845 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
421 09:56:53.693057 Filename '939283/tftp-deploy-sgxvwu_s/kernel/zImage'.
422 09:56:53.693485 Load address: 0x82000000
423 09:56:55.803100 Loading: *################################################## 10.9 MiB
424 09:56:55.803516 5.2 MiB/s
425 09:56:55.803742 done
426 09:56:55.806630 Bytes transferred = 11457024 (aed200 hex)
427 09:56:55.807174 Sending with 10 millisecond of delay
429 09:57:00.253681 => tftp 0x83000000 939283/tftp-deploy-sgxvwu_s/ramdisk/ramdisk.cpio.gz.uboot
430 09:57:00.264880 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
431 09:57:00.266021 tftp 0x83000000 939283/tftp-deploy-sgxvwu_s/ramdisk/ramdisk.cpio.gz.uboot
432 09:57:00.266599 link up on port 0, speed 100, full duplex
433 09:57:00.269627 Using ethernet@4a100000 device
434 09:57:00.275212 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
435 09:57:00.283837 Filename '939283/tftp-deploy-sgxvwu_s/ramdisk/ramdisk.cpio.gz.uboot'.
436 09:57:00.284325 Load address: 0x83000000
437 09:57:03.249407 Loading: *################################################## 14.1 MiB
438 09:57:03.249908 4.8 MiB/s
439 09:57:03.250138 done
440 09:57:03.252994 Bytes transferred = 14794211 (e1bde3 hex)
441 09:57:03.253605 Sending with 10 millisecond of delay
443 09:57:05.111309 => setenv initrd_size ${filesize}
444 09:57:05.122100 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
445 09:57:05.122962 setenv initrd_size ${filesize}
446 09:57:05.123683 Sending with 10 millisecond of delay
448 09:57:09.271002 => tftp 0x88000000 939283/tftp-deploy-sgxvwu_s/dtb/am335x-boneblack.dtb
449 09:57:09.281784 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
450 09:57:09.282746 tftp 0x88000000 939283/tftp-deploy-sgxvwu_s/dtb/am335x-boneblack.dtb
451 09:57:09.283223 link up on port 0, speed 100, full duplex
452 09:57:09.286762 Using ethernet@4a100000 device
453 09:57:09.293563 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
454 09:57:09.299579 Filename '939283/tftp-deploy-sgxvwu_s/dtb/am335x-boneblack.dtb'.
455 09:57:09.300141 Load address: 0x88000000
456 09:57:09.314312 Loading: *################################################## 68.9 KiB
457 09:57:09.320756 4 MiB/s
458 09:57:09.321303 done
459 09:57:09.324075 Bytes transferred = 70568 (113a8 hex)
460 09:57:09.324780 Sending with 10 millisecond of delay
462 09:57:22.508246 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/939283/extract-nfsrootfs-qtsz7v_s,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
463 09:57:22.519302 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:03)
464 09:57:22.520512 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/939283/extract-nfsrootfs-qtsz7v_s,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
465 09:57:22.521516 Sending with 10 millisecond of delay
467 09:57:24.862890 => bootz 0x82000000 0x83000000 0x88000000
468 09:57:24.873749 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
469 09:57:24.874431 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:01)
470 09:57:24.875510 bootz 0x82000000 0x83000000 0x88000000
471 09:57:24.876133 Kernel image @ 0x82000000 [ 0x000000 - 0xaed200 ]
472 09:57:24.876692 ## Loading init Ramdisk from Legacy Image at 83000000 ...
473 09:57:24.881644 Image Name:
474 09:57:24.882225 Created: 2024-11-05 9:56:25 UTC
475 09:57:24.884892 Image Type: ARM Linux RAMDisk Image (uncompressed)
476 09:57:24.890472 Data Size: 14794147 Bytes = 14.1 MiB
477 09:57:24.898567 Load Address: 00000000
478 09:57:24.899134 Entry Point: 00000000
479 09:57:25.067018 Verifying Checksum ... OK
480 09:57:25.067658 ## Flattened Device Tree blob at 88000000
481 09:57:25.073613 Booting using the fdt blob at 0x88000000
482 09:57:25.074258 Working FDT set to 88000000
483 09:57:25.079553 Using Device Tree in place at 88000000, end 880143a7
484 09:57:25.082959 Working FDT set to 88000000
485 09:57:25.097170
486 09:57:25.097767 Starting kernel ...
487 09:57:25.098304
488 09:57:25.099301 end: 2.4.3 bootloader-commands (duration 00:00:43) [common]
489 09:57:25.100002 start: 2.4.4 auto-login-action (timeout 00:04:01) [common]
490 09:57:25.100555 Setting prompt string to ['Linux version [0-9]']
491 09:57:25.101071 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
492 09:57:25.101584 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
493 09:57:25.939394 [ 0.000000] Booting Linux on physical CPU 0x0
494 09:57:25.945392 start: 2.4.4.1 login-action (timeout 00:04:00) [common]
495 09:57:25.946059 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
496 09:57:25.946551 Setting prompt string to []
497 09:57:25.947063 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
498 09:57:25.947539 Using line separator: #'\n'#
499 09:57:25.947959 No login prompt set.
500 09:57:25.948426 Parsing kernel messages
501 09:57:25.948836 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
502 09:57:25.949765 [login-action] Waiting for messages, (timeout 00:04:00)
503 09:57:25.950268 Waiting using forced prompt support (timeout 00:02:00)
504 09:57:25.962410 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j363173-arm-gcc-12-multi-v7-defconfig-jkdnf) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Tue Nov 5 09:12:23 UTC 2024
505 09:57:25.968093 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
506 09:57:25.973884 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
507 09:57:25.985014 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
508 09:57:25.990882 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
509 09:57:25.996829 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
510 09:57:25.997401 [ 0.000000] Memory policy: Data cache writeback
511 09:57:26.003362 [ 0.000000] efi: UEFI not found.
512 09:57:26.007917 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
513 09:57:26.014257 [ 0.000000] Zone ranges:
514 09:57:26.020261 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
515 09:57:26.025848 [ 0.000000] Normal empty
516 09:57:26.026419 [ 0.000000] HighMem empty
517 09:57:26.028693 [ 0.000000] Movable zone start for each node
518 09:57:26.034393 [ 0.000000] Early memory node ranges
519 09:57:26.040222 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
520 09:57:26.048322 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
521 09:57:26.073764 [ 0.000000] CPU: All CPU(s) started in SVC mode.
522 09:57:26.078657 [ 0.000000] AM335X ES2.0 (sgx neon)
523 09:57:26.091112 [ 0.000000] percpu: Embedded 17 pages/cpu s40908 r8192 d20532 u69632
524 09:57:26.111457 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/939283/extract-nfsrootfs-qtsz7v_s,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
525 09:57:26.117244 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
526 09:57:26.128682 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
527 09:57:26.134429 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
528 09:57:26.140783 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
529 09:57:26.170658 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
530 09:57:26.176702 <6>[ 0.000000] trace event string verifier disabled
531 09:57:26.177399 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
532 09:57:26.184829 <6>[ 0.000000] rcu: RCU event tracing is enabled.
533 09:57:26.190435 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
534 09:57:26.196099 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
535 09:57:26.204940 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
536 09:57:26.210587 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
537 09:57:26.219266 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1.
538 09:57:26.235871 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
539 09:57:26.254470 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
540 09:57:26.260206 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
541 09:57:26.354608 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
542 09:57:26.366151 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
543 09:57:26.372755 <6>[ 0.008339] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
544 09:57:26.384972 <6>[ 0.019150] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
545 09:57:26.393198 <6>[ 0.034016] Console: colour dummy device 80x30
546 09:57:26.399374 Matched prompt #6: WARNING:
547 09:57:26.399955 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
548 09:57:26.404790 <3>[ 0.038911] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
549 09:57:26.407590 <3>[ 0.045980] This ensures that you still see kernel messages. Please
550 09:57:26.412843 <3>[ 0.052705] update your kernel commandline.
551 09:57:26.454365 <6>[ 0.057318] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
552 09:57:26.460185 <6>[ 0.096157] CPU: Testing write buffer coherency: ok
553 09:57:26.466192 <6>[ 0.101524] CPU0: Spectre v2: using BPIALL workaround
554 09:57:26.466918 <6>[ 0.106991] pid_max: default: 32768 minimum: 301
555 09:57:26.477498 <6>[ 0.112181] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
556 09:57:26.484440 <6>[ 0.120006] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
557 09:57:26.491697 <6>[ 0.129358] CPU0: thread -1, cpu 0, socket -1, mpidr 0
558 09:57:26.499168 <6>[ 0.136458] Setting up static identity map for 0x80300000 - 0x803000ac
559 09:57:26.505380 <6>[ 0.146158] rcu: Hierarchical SRCU implementation.
560 09:57:26.512569 <6>[ 0.151448] rcu: Max phase no-delay instances is 1000.
561 09:57:26.522209 <6>[ 0.162554] EFI services will not be available.
562 09:57:26.527969 <6>[ 0.167827] smp: Bringing up secondary CPUs ...
563 09:57:26.533644 <6>[ 0.172872] smp: Brought up 1 node, 1 CPU
564 09:57:26.539435 <6>[ 0.177275] SMP: Total of 1 processors activated (996.14 BogoMIPS).
565 09:57:26.545322 <6>[ 0.184044] CPU: All CPU(s) started in SVC mode.
566 09:57:26.564818 <6>[ 0.189231] Memory: 405996K/522240K available (16384K kernel code, 2543K rwdata, 6788K rodata, 2048K init, 430K bss, 49052K reserved, 65536K cma-reserved, 0K highmem)
567 09:57:26.565435 <6>[ 0.205502] devtmpfs: initialized
568 09:57:26.587848 <6>[ 0.222514] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
569 09:57:26.596220 <6>[ 0.231091] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
570 09:57:26.604330 <6>[ 0.241546] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
571 09:57:26.616080 <6>[ 0.253903] pinctrl core: initialized pinctrl subsystem
572 09:57:26.625399 <6>[ 0.264584] DMI not present or invalid.
573 09:57:26.632337 <6>[ 0.270430] NET: Registered PF_NETLINK/PF_ROUTE protocol family
574 09:57:26.642304 <6>[ 0.279369] DMA: preallocated 256 KiB pool for atomic coherent allocations
575 09:57:26.657391 <6>[ 0.290949] thermal_sys: Registered thermal governor 'step_wise'
576 09:57:26.658011 <6>[ 0.291112] cpuidle: using governor menu
577 09:57:26.686009 <6>[ 0.326744] No ATAGs?
578 09:57:26.691265 <6>[ 0.329387] hw-breakpoint: debug architecture 0x4 unsupported.
579 09:57:26.702453 <6>[ 0.341447] Serial: AMBA PL011 UART driver
580 09:57:26.734295 <6>[ 0.374881] iommu: Default domain type: Translated
581 09:57:26.743325 <6>[ 0.380226] iommu: DMA domain TLB invalidation policy: strict mode
582 09:57:26.770569 <5>[ 0.410602] SCSI subsystem initialized
583 09:57:26.776414 <6>[ 0.415491] usbcore: registered new interface driver usbfs
584 09:57:26.782242 <6>[ 0.421524] usbcore: registered new interface driver hub
585 09:57:26.788987 <6>[ 0.427304] usbcore: registered new device driver usb
586 09:57:26.794629 <6>[ 0.433807] pps_core: LinuxPPS API ver. 1 registered
587 09:57:26.806261 <6>[ 0.439193] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
588 09:57:26.812741 <6>[ 0.448911] PTP clock support registered
589 09:57:26.813275 <6>[ 0.453372] EDAC MC: Ver: 3.0.0
590 09:57:26.862175 <6>[ 0.500281] scmi_core: SCMI protocol bus registered
591 09:57:26.877689 <6>[ 0.517654] vgaarb: loaded
592 09:57:26.883765 <6>[ 0.521509] clocksource: Switched to clocksource dmtimer
593 09:57:26.926419 <6>[ 0.566864] NET: Registered PF_INET protocol family
594 09:57:26.939011 <6>[ 0.572529] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
595 09:57:26.946172 <6>[ 0.581340] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
596 09:57:26.957570 <6>[ 0.590269] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
597 09:57:26.963335 <6>[ 0.598531] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
598 09:57:26.969233 <6>[ 0.606818] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
599 09:57:26.975012 <6>[ 0.614540] TCP: Hash tables configured (established 4096 bind 4096)
600 09:57:26.986502 <6>[ 0.621445] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
601 09:57:26.992471 <6>[ 0.628479] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
602 09:57:26.997795 <6>[ 0.636086] NET: Registered PF_UNIX/PF_LOCAL protocol family
603 09:57:27.075516 <6>[ 0.710597] RPC: Registered named UNIX socket transport module.
604 09:57:27.076042 <6>[ 0.717032] RPC: Registered udp transport module.
605 09:57:27.081300 <6>[ 0.722164] RPC: Registered tcp transport module.
606 09:57:27.087030 <6>[ 0.727268] RPC: Registered tcp-with-tls transport module.
607 09:57:27.100029 <6>[ 0.733189] RPC: Registered tcp NFSv4.1 backchannel transport module.
608 09:57:27.100471 <6>[ 0.740095] PCI: CLS 0 bytes, default 64
609 09:57:27.106436 <5>[ 0.745900] Initialise system trusted keyrings
610 09:57:27.128334 <6>[ 0.765967] Trying to unpack rootfs image as initramfs...
611 09:57:27.207666 <6>[ 0.842238] workingset: timestamp_bits=30 max_order=17 bucket_order=0
612 09:57:27.212435 <6>[ 0.849742] squashfs: version 4.0 (2009/01/31) Phillip Lougher
613 09:57:27.251450 <5>[ 0.892239] NFS: Registering the id_resolver key type
614 09:57:27.257282 <5>[ 0.897829] Key type id_resolver registered
615 09:57:27.263094 <5>[ 0.902501] Key type id_legacy registered
616 09:57:27.268845 <6>[ 0.906941] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
617 09:57:27.278450 <6>[ 0.914139] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
618 09:57:27.331285 <5>[ 0.972096] Key type asymmetric registered
619 09:57:27.337478 <5>[ 0.976621] Asymmetric key parser 'x509' registered
620 09:57:27.345635 <6>[ 0.982112] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
621 09:57:27.351434 <6>[ 0.989999] io scheduler mq-deadline registered
622 09:57:27.359352 <6>[ 0.994955] io scheduler kyber registered
623 09:57:27.359841 <6>[ 0.999407] io scheduler bfq registered
624 09:57:27.480952 <6>[ 1.118008] ledtrig-cpu: registered to indicate activity on CPUs
625 09:57:27.734029 <6>[ 1.370906] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
626 09:57:27.766083 <6>[ 1.406598] msm_serial: driver initialized
627 09:57:27.772063 <6>[ 1.411389] SuperH (H)SCI(F) driver initialized
628 09:57:27.778053 <6>[ 1.416721] STMicroelectronics ASC driver initialized
629 09:57:27.783445 <6>[ 1.422395] STM32 USART driver initialized
630 09:57:27.914637 <6>[ 1.554713] brd: module loaded
631 09:57:27.935140 <6>[ 1.576163] loop: module loaded
632 09:57:27.969173 <6>[ 1.609123] CAN device driver interface
633 09:57:27.975702 <6>[ 1.614312] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
634 09:57:27.981525 <6>[ 1.621258] e1000e: Intel(R) PRO/1000 Network Driver
635 09:57:27.988343 <6>[ 1.626709] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
636 09:57:27.994044 <6>[ 1.633147] igb: Intel(R) Gigabit Ethernet Network Driver
637 09:57:28.000504 <6>[ 1.638971] igb: Copyright (c) 2007-2014 Intel Corporation.
638 09:57:28.013239 <6>[ 1.648183] pegasus: Pegasus/Pegasus II USB Ethernet driver
639 09:57:28.018997 <6>[ 1.654341] usbcore: registered new interface driver pegasus
640 09:57:28.024778 <6>[ 1.660468] usbcore: registered new interface driver asix
641 09:57:28.030577 <6>[ 1.666365] usbcore: registered new interface driver ax88179_178a
642 09:57:28.036487 <6>[ 1.672973] usbcore: registered new interface driver cdc_ether
643 09:57:28.042185 <6>[ 1.679278] usbcore: registered new interface driver smsc75xx
644 09:57:28.047978 <6>[ 1.685514] usbcore: registered new interface driver smsc95xx
645 09:57:28.053731 <6>[ 1.691748] usbcore: registered new interface driver net1080
646 09:57:28.059584 <6>[ 1.697869] usbcore: registered new interface driver cdc_subset
647 09:57:28.065269 <6>[ 1.704278] usbcore: registered new interface driver zaurus
648 09:57:28.072936 <6>[ 1.710319] usbcore: registered new interface driver cdc_ncm
649 09:57:28.082524 <6>[ 1.719786] usbcore: registered new interface driver usb-storage
650 09:57:28.091842 <6>[ 1.730870] i2c_dev: i2c /dev entries driver
651 09:57:28.116559 <5>[ 1.749116] cpuidle: enable-method property 'ti,am3352' found operations
652 09:57:28.122302 <6>[ 1.758648] sdhci: Secure Digital Host Controller Interface driver
653 09:57:28.129906 <6>[ 1.765418] sdhci: Copyright(c) Pierre Ossman
654 09:57:28.136969 <6>[ 1.772011] Synopsys Designware Multimedia Card Interface Driver
655 09:57:28.142537 <6>[ 1.779838] sdhci-pltfm: SDHCI platform and OF driver helper
656 09:57:28.156526 <6>[ 1.789698] usbcore: registered new interface driver usbhid
657 09:57:28.157051 <6>[ 1.795821] usbhid: USB HID core driver
658 09:57:28.169251 <6>[ 1.807291] NET: Registered PF_INET6 protocol family
659 09:57:28.612318 <6>[ 2.253014] Segment Routing with IPv6
660 09:57:28.618261 <6>[ 2.257163] In-situ OAM (IOAM) with IPv6
661 09:57:28.624824 <6>[ 2.261685] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
662 09:57:28.630620 <6>[ 2.268937] NET: Registered PF_PACKET protocol family
663 09:57:28.636484 <6>[ 2.274495] can: controller area network core
664 09:57:28.642215 <6>[ 2.279320] NET: Registered PF_CAN protocol family
665 09:57:28.642674 <6>[ 2.284547] can: raw protocol
666 09:57:28.647932 <6>[ 2.287872] can: broadcast manager protocol
667 09:57:28.654463 <6>[ 2.292471] can: netlink gateway - max_hops=1
668 09:57:28.660568 <5>[ 2.297948] Key type dns_resolver registered
669 09:57:28.666877 <6>[ 2.303039] ThumbEE CPU extension supported.
670 09:57:28.667342 <5>[ 2.307732] Registering SWP/SWPB emulation handler
671 09:57:28.676630 <3>[ 2.313430] omap_voltage_late_init: Voltage driver support not added
672 09:57:28.898440 <5>[ 2.536753] Loading compiled-in X.509 certificates
673 09:57:29.012508 <6>[ 2.640250] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
674 09:57:29.019599 <6>[ 2.656917] pinctrl-single 44e10800.pinmux: 142 pins, size 568
675 09:57:29.045859 <3>[ 2.680545] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
676 09:57:29.246193 <3>[ 2.880869] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
677 09:57:29.445002 <6>[ 3.082277] OMAP GPIO hardware version 0.1
678 09:57:29.464301 <6>[ 3.100863] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
679 09:57:29.566918 <4>[ 3.203752] at24 2-0054: supply vcc not found, using dummy regulator
680 09:57:29.615996 <4>[ 3.252830] at24 2-0055: supply vcc not found, using dummy regulator
681 09:57:29.649912 <4>[ 3.286620] at24 2-0056: supply vcc not found, using dummy regulator
682 09:57:29.696008 <4>[ 3.332782] at24 2-0057: supply vcc not found, using dummy regulator
683 09:57:29.739107 <6>[ 3.376668] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
684 09:57:29.820571 <3>[ 3.454020] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
685 09:57:29.844165 <6>[ 3.474889] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
686 09:57:29.867086 <4>[ 3.501433] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
687 09:57:29.874907 <4>[ 3.510280] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
688 09:57:30.024972 <6>[ 3.661813] omap_rng 48310000.rng: Random Number Generator ver. 20
689 09:57:30.048335 <5>[ 3.687949] random: crng init done
690 09:57:30.098957 <6>[ 3.732870] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
691 09:57:30.151070 <6>[ 3.790042] Freeing initrd memory: 14448K
692 09:57:30.206000 <6>[ 3.840332] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
693 09:57:30.211777 <6>[ 3.850668] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
694 09:57:30.223576 <6>[ 3.858032] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
695 09:57:30.229319 <6>[ 3.865541] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
696 09:57:30.240896 <6>[ 3.873679] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
697 09:57:30.248205 <6>[ 3.885312] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:00:92
698 09:57:30.260863 <5>[ 3.894353] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
699 09:57:30.289104 <3>[ 3.924029] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
700 09:57:30.294210 <6>[ 3.932574] edma 49000000.dma: TI EDMA DMA engine driver
701 09:57:30.365584 <3>[ 4.000134] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
702 09:57:30.380487 <6>[ 4.014855] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
703 09:57:30.392826 <3>[ 4.031868] l3-aon-clkctrl:0000:0: failed to disable
704 09:57:30.436218 <6>[ 4.071168] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
705 09:57:30.442075 <6>[ 4.080684] printk: legacy console [ttyS0] enabled
706 09:57:30.447949 <6>[ 4.080684] printk: legacy console [ttyS0] enabled
707 09:57:30.453333 <6>[ 4.091015] printk: legacy bootconsole [omap8250] disabled
708 09:57:30.458555 <6>[ 4.091015] printk: legacy bootconsole [omap8250] disabled
709 09:57:30.498351 <4>[ 4.132318] tps65217-pmic: Failed to locate of_node [id: -1]
710 09:57:30.501754 <4>[ 4.139699] tps65217-bl: Failed to locate of_node [id: -1]
711 09:57:30.518712 <6>[ 4.159406] tps65217 0-0024: TPS65217 ID 0xe version 1.2
712 09:57:30.538750 <6>[ 4.166344] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
713 09:57:30.550549 <6>[ 4.180040] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
714 09:57:30.553581 <6>[ 4.191909] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
715 09:57:30.576694 <6>[ 4.211931] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
716 09:57:30.582496 <6>[ 4.220986] sdhci-omap 48060000.mmc: Got CD GPIO
717 09:57:30.593803 <4>[ 4.226168] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
718 09:57:30.605299 <4>[ 4.239702] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
719 09:57:30.611619 <4>[ 4.248426] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
720 09:57:30.623333 <4>[ 4.257002] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
721 09:57:30.719627 <6>[ 4.356434] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
722 09:57:30.767123 <6>[ 4.402198] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
723 09:57:30.773688 <6>[ 4.410693] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
724 09:57:30.782326 <6>[ 4.419480] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
725 09:57:30.850415 <6>[ 4.489191] mmc1: new high speed MMC card at address 0001
726 09:57:30.858411 <6>[ 4.497241] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
727 09:57:30.876651 <6>[ 4.509823] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
728 09:57:30.883771 <6>[ 4.522821] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
729 09:57:30.894208 <6>[ 4.533353] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
730 09:57:30.914661 <6>[ 4.547744] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
731 09:57:30.921494 <6>[ 4.556517] mmc0: new high speed SDHC card at address aaaa
732 09:57:30.925010 <6>[ 4.563537] mmcblk0: mmc0:aaaa SU16G 14.8 GiB
733 09:57:30.934604 <6>[ 4.574212] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 >
734 09:57:33.047484 <6>[ 6.682571] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
735 09:57:33.181091 <5>[ 6.721516] Sending DHCP requests ., OK
736 09:57:33.192415 <6>[ 6.826169] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.8
737 09:57:33.193023 <6>[ 6.834275] IP-Config: Complete:
738 09:57:33.206539 <6>[ 6.837819] device=eth0, hwaddr=90:59:af:5b:00:92, ipaddr=192.168.6.8, mask=255.255.255.0, gw=192.168.6.1
739 09:57:33.212230 <6>[ 6.848304] host=192.168.6.8, domain=, nis-domain=(none)
740 09:57:33.218195 <6>[ 6.854437] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
741 09:57:33.224642 <6>[ 6.854473] nameserver0=10.255.253.1
742 09:57:33.225273 <6>[ 6.867024] clk: Disabling unused clocks
743 09:57:33.235725 <6>[ 6.871761] PM: genpd: Disabling unused power domains
744 09:57:33.252768 <6>[ 6.890419] Freeing unused kernel image (initmem) memory: 2048K
745 09:57:33.260586 <6>[ 6.900263] Run /init as init process
746 09:57:33.285668 Loading, please wait...
747 09:57:33.360431 Starting systemd-udevd version 252.22-1~deb12u1
748 09:57:36.450974 <4>[ 10.085028] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
749 09:57:36.579572 <4>[ 10.213583] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
750 09:57:36.741449 <6>[ 10.382650] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
751 09:57:36.752247 <6>[ 10.388323] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
752 09:57:36.986217 <6>[ 10.626711] hub 1-0:1.0: USB hub found
753 09:57:37.039389 <6>[ 10.679323] hub 1-0:1.0: 1 port detected
754 09:57:37.166182 <6>[ 10.805561] tda998x 0-0070: found TDA19988
755 09:57:40.205253 Begin: Loading essential drivers ... done.
756 09:57:40.210988 Begin: Running /scripts/init-premount ... done.
757 09:57:40.216331 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
758 09:57:40.225604 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
759 09:57:40.234860 Device /sys/class/net/eth0 found
760 09:57:40.235274 done.
761 09:57:40.314327 Begin: Waiting up to 180 secs for any network device to become available ... done.
762 09:57:40.382764 IP-Config: eth0 hardware address 90:59:af:5b:00:92 mtu 1500 DHCP
763 09:57:40.502953 IP-Config: eth0 guessed broadcast address 192.168.6.255
764 09:57:40.508480 IP-Config: eth0 complete (dhcp from 192.168.6.1):
765 09:57:40.514087 address: 192.168.6.8 broadcast: 192.168.6.255 netmask: 255.255.255.0
766 09:57:40.525250 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
767 09:57:40.525537 rootserver: 192.168.6.1 rootpath:
768 09:57:40.527912 filename :
769 09:57:40.587193 done.
770 09:57:40.604626 Begin: Running /scripts/nfs-bottom ... done.
771 09:57:40.673408 Begin: Running /scripts/init-bottom ... done.
772 09:57:42.091326 <30>[ 15.728313] systemd[1]: System time before build time, advancing clock.
773 09:57:42.262349 <30>[ 15.873172] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
774 09:57:42.271023 <30>[ 15.909885] systemd[1]: Detected architecture arm.
775 09:57:42.283540
776 09:57:42.283915 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
777 09:57:42.284163
778 09:57:42.314338 <30>[ 15.951981] systemd[1]: Hostname set to <debian-bookworm-armhf>.
779 09:57:44.466202 <30>[ 18.102768] systemd[1]: Queued start job for default target graphical.target.
780 09:57:44.482925 <30>[ 18.117313] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
781 09:57:44.490523 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
782 09:57:44.523621 <30>[ 18.157476] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
783 09:57:44.531023 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
784 09:57:44.562931 <30>[ 18.197792] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
785 09:57:44.575824 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
786 09:57:44.598216 <30>[ 18.233346] systemd[1]: Created slice user.slice - User and Session Slice.
787 09:57:44.604941 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
788 09:57:44.634902 <30>[ 18.263016] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
789 09:57:44.640899 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
790 09:57:44.669704 <30>[ 18.303577] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
791 09:57:44.680584 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
792 09:57:44.718747 <30>[ 18.342434] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
793 09:57:44.725061 <30>[ 18.363081] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
794 09:57:44.732524 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
795 09:57:44.756758 <30>[ 18.391941] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
796 09:57:44.765080 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
797 09:57:44.787629 <30>[ 18.422364] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
798 09:57:44.796107 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
799 09:57:44.819049 <30>[ 18.453570] systemd[1]: Reached target paths.target - Path Units.
800 09:57:44.824184 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
801 09:57:44.847098 <30>[ 18.482206] systemd[1]: Reached target remote-fs.target - Remote File Systems.
802 09:57:44.854425 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
803 09:57:44.876980 <30>[ 18.512033] systemd[1]: Reached target slices.target - Slice Units.
804 09:57:44.882320 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
805 09:57:44.907461 <30>[ 18.542309] systemd[1]: Reached target swap.target - Swaps.
806 09:57:44.911293 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
807 09:57:44.937670 <30>[ 18.572309] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
808 09:57:44.946336 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
809 09:57:44.968319 <30>[ 18.603118] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
810 09:57:44.976567 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
811 09:57:45.055991 <30>[ 18.685973] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
812 09:57:45.068663 <30>[ 18.703543] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
813 09:57:45.077089 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
814 09:57:45.100190 <30>[ 18.734256] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
815 09:57:45.107749 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
816 09:57:45.129893 <30>[ 18.764576] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
817 09:57:45.138117 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
818 09:57:45.162830 <30>[ 18.796461] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
819 09:57:45.168395 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
820 09:57:45.199712 <30>[ 18.833273] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
821 09:57:45.207282 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
822 09:57:45.234439 <30>[ 18.863299] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
823 09:57:45.253080 <30>[ 18.881860] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
824 09:57:45.301677 <30>[ 18.937365] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
825 09:57:45.327512 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
826 09:57:45.379078 <30>[ 19.014555] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
827 09:57:45.403320 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
828 09:57:45.478138 <30>[ 19.112702] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
829 09:57:45.506081 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
830 09:57:45.560980 <30>[ 19.196078] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
831 09:57:45.587153 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
832 09:57:45.637759 <30>[ 19.273285] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
833 09:57:45.657359 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
834 09:57:45.716965 <30>[ 19.353017] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
835 09:57:45.728408 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
836 09:57:45.788138 <30>[ 19.422778] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
837 09:57:45.815282 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
838 09:57:45.867411 <30>[ 19.502544] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
839 09:57:45.874695 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
840 09:57:45.909834 <30>[ 19.545667] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
841 09:57:45.946103 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
842 09:57:45.974555 <28>[ 19.603713] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
843 09:57:45.983072 <28>[ 19.618103] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
844 09:57:46.018596 <30>[ 19.654961] systemd[1]: Starting systemd-journald.service - Journal Service...
845 09:57:46.036633 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
846 09:57:46.098368 <30>[ 19.734152] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
847 09:57:46.117362 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
848 09:57:46.176948 <30>[ 19.812952] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
849 09:57:46.218991 Starting [0;1;39msystemd-network-g… units from Kernel command line...
850 09:57:46.282676 <30>[ 19.917131] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
851 09:57:46.329451 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
852 09:57:46.389483 <30>[ 20.024719] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
853 09:57:46.443146 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
854 09:57:46.498066 <30>[ 20.133961] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
855 09:57:46.548024 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
856 09:57:46.559064 <30>[ 20.195719] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
857 09:57:46.603221 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
858 09:57:46.631223 <30>[ 20.265997] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
859 09:57:46.666372 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
860 09:57:46.839890 <30>[ 20.476447] systemd[1]: modprobe@configfs.service: Deactivated successfully.
861 09:57:46.877128 <30>[ 20.513410] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
862 09:57:46.906797 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
863 09:57:46.928111 <30>[ 20.563307] systemd[1]: Started systemd-journald.service - Journal Service.
864 09:57:46.934936 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
865 09:57:46.977225 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
866 09:57:47.002464 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
867 09:57:47.037023 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
868 09:57:47.066994 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
869 09:57:47.101421 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
870 09:57:47.137186 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
871 09:57:47.159330 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
872 09:57:47.189394 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
873 09:57:47.217171 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
874 09:57:47.266468 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
875 09:57:47.336051 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
876 09:57:47.387736 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
877 09:57:47.462144 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
878 09:57:47.540390 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
879 09:57:47.689140 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
880 09:57:47.756777 <46>[ 21.393571] systemd-journald[165]: Received client request to flush runtime journal.
881 09:57:47.848092 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
882 09:57:47.952545 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
883 09:57:49.015628 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
884 09:57:49.069435 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
885 09:57:49.389759 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
886 09:57:49.619226 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
887 09:57:49.639036 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
888 09:57:49.659757 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
889 09:57:49.729360 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
890 09:57:49.765782 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
891 09:57:50.736003 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
892 09:57:50.787093 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
893 09:57:50.860222 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
894 09:57:50.977106 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
895 09:57:51.037995 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
896 09:57:52.983177 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
897 09:57:53.519905 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
898 09:57:53.761790 <5>[ 27.397893] cfg80211: Loading compiled-in X.509 certificates for regulatory database
899 09:57:54.389288 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
900 09:57:54.715894 <5>[ 28.354083] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
901 09:57:54.800734 <5>[ 28.437327] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
902 09:57:54.833746 <4>[ 28.469588] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
903 09:57:54.839712 <6>[ 28.478713] cfg80211: failed to load regulatory.db
904 09:57:55.233010 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - N<46>[ 28.858941] systemd-journald[165]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
905 09:57:55.236750 etwork Time Synchronization.
906 09:57:55.412412 <46>[ 29.041610] systemd-journald[165]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
907 09:57:55.643790 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
908 09:58:05.288599 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
909 09:58:05.316690 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
910 09:58:05.338620 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
911 09:58:05.361356 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
912 09:58:05.426756 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
913 09:58:05.469961 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
914 09:58:05.528983 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
915 09:58:05.568387 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
916 09:58:05.631455 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
917 09:58:05.662905 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
918 09:58:05.697527 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
919 09:58:05.722332 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
920 09:58:05.751509 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
921 09:58:05.796020 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
922 09:58:05.821177 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
923 09:58:05.860556 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
924 09:58:05.897309 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
925 09:58:05.922478 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
926 09:58:05.948481 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
927 09:58:05.969494 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
928 09:58:06.012026 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
929 09:58:06.035339 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
930 09:58:06.059515 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
931 09:58:06.137636 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
932 09:58:06.199038 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
933 09:58:06.281686 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
934 09:58:06.349654 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
935 09:58:06.437679 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
936 09:58:06.496194 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
937 09:58:06.530018 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
938 09:58:06.728003 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
939 09:58:06.780398 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
940 09:58:06.837872 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
941 09:58:06.857006 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
942 09:58:06.879682 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
943 09:58:07.078622 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
944 09:58:07.441864 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
945 09:58:07.497166 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
946 09:58:07.521348 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
947 09:58:07.599740 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
948 09:58:07.780989 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
949 09:58:07.920737
950 09:58:07.921178 Debian GNU/Linux 12worm-armhf login: root (automatic login)
951 09:58:07.924086
952 09:58:08.298437 Linux debian-bookworm-armhf 6.12.0-rc6 #1 SMP Tue Nov 5 09:12:23 UTC 2024 armv7l
953 09:58:08.299038
954 09:58:08.304018 The programs included with the Debian GNU/Linux system are free software;
955 09:58:08.307476 the exact distribution terms for each program are described in the
956 09:58:08.313016 individual files in /usr/share/doc/*/copyright.
957 09:58:08.313369
958 09:58:08.318538 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
959 09:58:08.323125 permitted by applicable law.
960 09:58:13.367433 Unable to match end of the kernel message
962 09:58:13.368307 Setting prompt string to ['/ #']
963 09:58:13.368603 end: 2.4.4.1 login-action (duration 00:00:47) [common]
965 09:58:13.369286 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
966 09:58:13.369561 start: 2.4.5 expect-shell-connection (timeout 00:03:12) [common]
967 09:58:13.369780 Setting prompt string to ['/ #']
968 09:58:13.370208 Forcing a shell prompt, looking for ['/ #']
970 09:58:13.421153 / #
971 09:58:13.421830 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
972 09:58:13.422343 Waiting using forced prompt support (timeout 00:02:30)
973 09:58:13.425835
974 09:58:13.432078 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
975 09:58:13.432654 start: 2.4.6 export-device-env (timeout 00:03:12) [common]
976 09:58:13.433128 Sending with 10 millisecond of delay
978 09:58:18.421871 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/939283/extract-nfsrootfs-qtsz7v_s'
979 09:58:18.434999 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/939283/extract-nfsrootfs-qtsz7v_s'
980 09:58:18.435529 Sending with 10 millisecond of delay
982 09:58:20.532639 / # export NFS_SERVER_IP='192.168.6.3'
983 09:58:20.543512 export NFS_SERVER_IP='192.168.6.3'
984 09:58:20.550124 end: 2.4.6 export-device-env (duration 00:00:07) [common]
985 09:58:20.550463 end: 2.4 uboot-commands (duration 00:01:55) [common]
986 09:58:20.550788 end: 2 uboot-action (duration 00:01:55) [common]
987 09:58:20.551148 start: 3 lava-test-retry (timeout 00:06:53) [common]
988 09:58:20.551729 start: 3.1 lava-test-shell (timeout 00:06:53) [common]
989 09:58:20.552193 Using namespace: common
991 09:58:20.653328 / # #
992 09:58:20.654165 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
993 09:58:20.658888 #
994 09:58:20.665185 Using /lava-939283
996 09:58:20.766346 / # export SHELL=/bin/bash
997 09:58:20.770946 export SHELL=/bin/bash
999 09:58:20.879242 / # . /lava-939283/environment
1000 09:58:21.140717 . /lava-939283/environment
1002 09:58:21.257206 / # /lava-939283/bin/lava-test-runner /lava-939283/0
1003 09:58:21.257921 Test shell timeout: 10s (minimum of the action and connection timeout)
1004 09:58:21.262444 /lava-939283/bin/lava-test-runner /lava-939283/0
1005 09:58:21.656591 + export TESTRUN_ID=0_timesync-off
1006 09:58:21.663485 + TESTRUN_ID=0_timesync-off
1007 09:58:21.663802 + cd /lava-939283/0/tests/0_timesync-off
1008 09:58:21.664033 ++ cat uuid
1009 09:58:21.680930 + UUID=939283_1.6.2.4.1
1010 09:58:21.681252 + set +x
1011 09:58:21.688338 <LAVA_SIGNAL_STARTRUN 0_timesync-off 939283_1.6.2.4.1>
1012 09:58:21.688629 + systemctl stop systemd-timesyncd
1013 09:58:21.689104 Received signal: <STARTRUN> 0_timesync-off 939283_1.6.2.4.1
1014 09:58:21.689361 Starting test lava.0_timesync-off (939283_1.6.2.4.1)
1015 09:58:21.689662 Skipping test definition patterns.
1016 09:58:21.967968 + set +x
1017 09:58:21.968359 <LAVA_SIGNAL_ENDRUN 0_timesync-off 939283_1.6.2.4.1>
1018 09:58:21.968819 Received signal: <ENDRUN> 0_timesync-off 939283_1.6.2.4.1
1019 09:58:21.969125 Ending use of test pattern.
1020 09:58:21.969365 Ending test lava.0_timesync-off (939283_1.6.2.4.1), duration 0.28
1022 09:58:22.144107 + export TESTRUN_ID=1_kselftest-dt
1023 09:58:22.151889 + TESTRUN_ID=1_kselftest-dt
1024 09:58:22.152342 + cd /lava-939283/0/tests/1_kselftest-dt
1025 09:58:22.152750 ++ cat uuid
1026 09:58:22.167291 + UUID=939283_1.6.2.4.5
1027 09:58:22.167728 + set +x
1028 09:58:22.173007 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 939283_1.6.2.4.5>
1029 09:58:22.173292 + cd ./automated/linux/kselftest/
1030 09:58:22.173746 Received signal: <STARTRUN> 1_kselftest-dt 939283_1.6.2.4.5
1031 09:58:22.174032 Starting test lava.1_kselftest-dt (939283_1.6.2.4.5)
1032 09:58:22.174331 Skipping test definition patterns.
1033 09:58:22.200127 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/tip/master/v6.12-rc6-401-g1596ed05f2f47/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g tip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1034 09:58:22.301874 INFO: install_deps skipped
1035 09:58:22.921068 --2024-11-05 09:58:22-- http://storage.kernelci.org/tip/master/v6.12-rc6-401-g1596ed05f2f47/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1036 09:58:22.946054 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1037 09:58:23.083978 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1038 09:58:23.220291 HTTP request sent, awaiting response... 200 OK
1039 09:58:23.220889 Length: 4105552 (3.9M) [application/octet-stream]
1040 09:58:23.225842 Saving to: 'kselftest_armhf.tar.gz'
1041 09:58:23.226291
1042 09:58:24.969218
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 185KB/s
kselftest_armhf.tar 4%[ ] 194.76K 356KB/s
kselftest_armhf.tar 19%[==> ] 771.76K 953KB/s
kselftest_armhf.tar 26%[====> ] 1.06M 1.02MB/s
kselftest_armhf.tar 59%[==========> ] 2.33M 1.82MB/s
kselftest_armhf.tar 84%[===============> ] 3.31M 2.23MB/s
kselftest_armhf.tar 93%[=================> ] 3.66M 2.12MB/s
kselftest_armhf.tar 100%[===================>] 3.92M 2.25MB/s in 1.7s
1043 09:58:24.969883
1044 09:58:25.717951 2024-11-05 09:58:24 (2.25 MB/s) - 'kselftest_armhf.tar.gz' saved [4105552/4105552]
1045 09:58:25.718564
1046 09:58:40.168483 skiplist:
1047 09:58:40.168913 ========================================
1048 09:58:40.174148 ========================================
1049 09:58:40.296193 dt:test_unprobed_devices.sh
1050 09:58:40.337205 ============== Tests to run ===============
1051 09:58:40.346906 dt:test_unprobed_devices.sh
1052 09:58:40.350823 ===========End Tests to run ===============
1053 09:58:40.362736 shardfile-dt pass
1054 09:58:40.609388 <12>[ 74.250535] kselftest: Running tests in dt
1055 09:58:40.637080 TAP version 13
1056 09:58:40.661952 1..1
1057 09:58:40.719857 # timeout set to 45
1058 09:58:40.720520 # selftests: dt: test_unprobed_devices.sh
1059 09:58:41.587990 # TAP version 13
1060 09:59:06.347547 # 1..257
1061 09:59:06.507432 # ok 1 / # SKIP
1062 09:59:06.528871 # ok 2 /clk_mcasp0
1063 09:59:06.599351 # ok 3 /clk_mcasp0_fixed # SKIP
1064 09:59:06.671082 # ok 4 /cpus/cpu@0 # SKIP
1065 09:59:06.739419 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1066 09:59:06.763279 # ok 6 /fixedregulator0
1067 09:59:06.783256 # ok 7 /leds
1068 09:59:06.805006 # ok 8 /ocp
1069 09:59:06.822498 # ok 9 /ocp/interconnect@44c00000
1070 09:59:06.849469 # ok 10 /ocp/interconnect@44c00000/segment@0
1071 09:59:06.873106 # ok 11 /ocp/interconnect@44c00000/segment@100000
1072 09:59:06.898895 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1073 09:59:06.969058 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1074 09:59:06.988686 # ok 14 /ocp/interconnect@44c00000/segment@200000
1075 09:59:07.011538 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1076 09:59:07.113177 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1077 09:59:07.184170 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1078 09:59:07.259458 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1079 09:59:07.331362 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1080 09:59:07.401944 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1081 09:59:07.471633 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1082 09:59:07.542929 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1083 09:59:07.614094 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1084 09:59:07.681102 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1085 09:59:07.751031 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1086 09:59:07.822648 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1087 09:59:07.898748 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1088 09:59:07.969789 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1089 09:59:08.039889 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1090 09:59:08.114002 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1091 09:59:08.193109 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1092 09:59:08.262261 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1093 09:59:08.335700 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1094 09:59:08.403441 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1095 09:59:08.479529 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1096 09:59:08.552227 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1097 09:59:08.624041 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1098 09:59:08.691355 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1099 09:59:08.762517 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1100 09:59:08.834021 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1101 09:59:08.908115 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1102 09:59:08.976450 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1103 09:59:09.052122 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1104 09:59:09.123348 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1105 09:59:09.194447 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1106 09:59:09.261347 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1107 09:59:09.332957 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1108 09:59:09.403768 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1109 09:59:09.477124 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1110 09:59:09.545376 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1111 09:59:09.618243 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1112 09:59:09.688953 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1113 09:59:09.759943 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1114 09:59:09.831314 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1115 09:59:09.900335 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1116 09:59:09.973025 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1117 09:59:10.043346 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1118 09:59:10.119574 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1119 09:59:10.190450 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1120 09:59:10.261946 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1121 09:59:10.333676 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1122 09:59:10.404669 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1123 09:59:10.477131 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1124 09:59:10.546097 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1125 09:59:10.616137 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1126 09:59:10.689010 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1127 09:59:10.761454 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1128 09:59:10.832129 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1129 09:59:10.909643 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1130 09:59:10.980638 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1131 09:59:11.054185 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1132 09:59:11.125070 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1133 09:59:11.197157 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1134 09:59:11.269197 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1135 09:59:11.340626 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1136 09:59:11.411942 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1137 09:59:11.483560 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1138 09:59:11.555667 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1139 09:59:11.625517 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1140 09:59:11.698087 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1141 09:59:11.768812 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1142 09:59:11.840145 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1143 09:59:11.910266 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1144 09:59:11.981741 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1145 09:59:12.058332 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1146 09:59:12.130262 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1147 09:59:12.434255 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1148 09:59:12.434904 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1149 09:59:12.435381 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1150 09:59:12.436656 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1151 09:59:12.490079 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1152 09:59:12.564050 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1153 09:59:12.634132 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1154 09:59:12.704229 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1155 09:59:12.725268 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1156 09:59:12.748588 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1157 09:59:12.774131 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1158 09:59:12.796713 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1159 09:59:12.820255 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1160 09:59:12.844701 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1161 09:59:12.868141 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1162 09:59:12.890679 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1163 09:59:12.996806 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1164 09:59:13.021209 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1165 09:59:13.045663 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1166 09:59:13.068814 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1167 09:59:13.179998 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1168 09:59:13.256036 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1169 09:59:13.325567 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1170 09:59:13.395705 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1171 09:59:13.465791 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1172 09:59:13.545676 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1173 09:59:13.613008 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1174 09:59:13.684875 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1175 09:59:13.762000 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1176 09:59:13.835810 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1177 09:59:13.906513 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1178 09:59:13.976252 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1179 09:59:14.046296 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1180 09:59:14.165438 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1181 09:59:14.279861 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1182 09:59:14.363899 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1183 09:59:14.385274 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1184 09:59:14.456458 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1185 09:59:14.526113 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1186 09:59:14.598152 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1187 09:59:14.618851 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1188 09:59:14.724761 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1189 09:59:14.750743 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1190 09:59:14.841614 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1191 09:59:14.863275 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1192 09:59:14.887799 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1193 09:59:14.910183 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1194 09:59:14.934757 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1195 09:59:14.957006 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1196 09:59:14.981552 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1197 09:59:15.007132 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1198 09:59:15.087921 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1199 09:59:15.112096 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1200 09:59:15.135622 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1201 09:59:15.206540 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1202 09:59:15.276573 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1203 09:59:15.297480 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1204 09:59:15.421589 # not ok 144 /ocp/interconnect@47c00000
1205 09:59:15.493420 # not ok 145 /ocp/interconnect@47c00000/segment@0
1206 09:59:15.514120 # ok 146 /ocp/interconnect@48000000
1207 09:59:15.539456 # ok 147 /ocp/interconnect@48000000/segment@0
1208 09:59:15.566982 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1209 09:59:15.590688 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1210 09:59:15.611223 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1211 09:59:15.637258 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1212 09:59:15.660573 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1213 09:59:15.682023 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1214 09:59:15.702913 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1215 09:59:15.811591 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1216 09:59:15.889607 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1217 09:59:15.910119 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1218 09:59:15.951954 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1219 09:59:15.981303 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1220 09:59:16.003651 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1221 09:59:16.026527 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1222 09:59:16.051890 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1223 09:59:16.072996 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1224 09:59:16.096944 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1225 09:59:16.119402 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1226 09:59:16.147962 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1227 09:59:16.170437 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1228 09:59:16.191855 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1229 09:59:16.213022 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1230 09:59:16.254422 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1231 09:59:16.301261 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1232 09:59:16.329158 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1233 09:59:16.358062 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1234 09:59:16.375861 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1235 09:59:16.396986 # ok 175 /ocp/interconnect@48000000/segment@100000
1236 09:59:16.425328 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1237 09:59:16.446678 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1238 09:59:16.519454 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1239 09:59:16.632697 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1240 09:59:16.720223 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1241 09:59:16.793222 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1242 09:59:16.862728 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1243 09:59:16.937680 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1244 09:59:17.004864 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1245 09:59:17.078978 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1246 09:59:17.098312 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1247 09:59:17.128204 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1248 09:59:17.144540 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1249 09:59:17.171477 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1250 09:59:17.210605 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1251 09:59:17.241766 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1252 09:59:17.261395 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1253 09:59:17.289840 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1254 09:59:17.305191 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1255 09:59:17.328158 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1256 09:59:17.352504 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1257 09:59:17.376820 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1258 09:59:17.399904 # ok 198 /ocp/interconnect@48000000/segment@200000
1259 09:59:17.429498 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1260 09:59:17.493542 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1261 09:59:17.513580 # ok 201 /ocp/interconnect@48000000/segment@300000
1262 09:59:17.540991 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1263 09:59:17.562389 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1264 09:59:17.586479 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1265 09:59:17.609010 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1266 09:59:17.631799 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1267 09:59:17.655498 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1268 09:59:17.727245 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1269 09:59:17.745998 # ok 209 /ocp/interconnect@4a000000
1270 09:59:17.779275 # ok 210 /ocp/interconnect@4a000000/segment@0
1271 09:59:17.807184 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1272 09:59:17.833585 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1273 09:59:17.857127 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1274 09:59:17.878344 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1275 09:59:17.950071 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1276 09:59:18.059644 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1277 09:59:18.131506 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1278 09:59:18.233069 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1279 09:59:18.300078 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1280 09:59:18.370695 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1281 09:59:18.469587 # not ok 221 /ocp/interconnect@4b140000
1282 09:59:18.541762 # not ok 222 /ocp/interconnect@4b140000/segment@0
1283 09:59:18.630552 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1284 09:59:18.654699 # ok 224 /ocp/target-module@40300000
1285 09:59:18.678725 # ok 225 /ocp/target-module@40300000/sram@0
1286 09:59:18.751185 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1287 09:59:18.818206 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1288 09:59:18.836647 # ok 228 /ocp/target-module@47400000
1289 09:59:18.862392 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1290 09:59:18.883943 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1291 09:59:18.906166 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1292 09:59:18.929412 # ok 232 /ocp/target-module@47400000/usb@1400
1293 09:59:18.951162 # ok 233 /ocp/target-module@47400000/usb@1800
1294 09:59:18.976235 # ok 234 /ocp/target-module@47810000
1295 09:59:18.998766 # ok 235 /ocp/target-module@49000000
1296 09:59:19.018114 # ok 236 /ocp/target-module@49000000/dma@0
1297 09:59:19.039068 # ok 237 /ocp/target-module@49800000
1298 09:59:19.066080 # ok 238 /ocp/target-module@49800000/dma@0
1299 09:59:19.087593 # ok 239 /ocp/target-module@49900000
1300 09:59:19.109128 # ok 240 /ocp/target-module@49900000/dma@0
1301 09:59:19.133671 # ok 241 /ocp/target-module@49a00000
1302 09:59:19.151893 # ok 242 /ocp/target-module@49a00000/dma@0
1303 09:59:19.173747 # ok 243 /ocp/target-module@4c000000
1304 09:59:19.249452 # not ok 244 /ocp/target-module@4c000000/emif@0
1305 09:59:19.266028 # ok 245 /ocp/target-module@50000000
1306 09:59:19.288640 # ok 246 /ocp/target-module@53100000
1307 09:59:19.363737 # not ok 247 /ocp/target-module@53100000/sham@0
1308 09:59:19.384913 # ok 248 /ocp/target-module@53500000
1309 09:59:19.455713 # not ok 249 /ocp/target-module@53500000/aes@0
1310 09:59:19.476667 # ok 250 /ocp/target-module@56000000
1311 09:59:19.576338 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1312 09:59:19.647835 # ok 252 /opp-table # SKIP
1313 09:59:19.723747 # ok 253 /soc # SKIP
1314 09:59:19.744727 # ok 254 /sound
1315 09:59:19.772341 # ok 255 /target-module@4b000000
1316 09:59:19.797330 # ok 256 /target-module@4b000000/target-module@140000
1317 09:59:19.814176 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1318 09:59:19.821959 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1319 09:59:19.828936 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1320 09:59:21.999735 dt_test_unprobed_devices_sh_ skip
1321 09:59:22.005389 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1322 09:59:22.010842 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1323 09:59:22.011374 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1324 09:59:22.019817 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1325 09:59:22.020343 dt_test_unprobed_devices_sh_fixedregulator0 pass
1326 09:59:22.025473 dt_test_unprobed_devices_sh_leds pass
1327 09:59:22.031016 dt_test_unprobed_devices_sh_ocp pass
1328 09:59:22.036535 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1329 09:59:22.042085 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1330 09:59:22.047639 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1331 09:59:22.053381 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1332 09:59:22.064519 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1333 09:59:22.070166 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1334 09:59:22.075583 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1335 09:59:22.086882 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1336 09:59:22.098282 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1337 09:59:22.104165 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1338 09:59:22.115024 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1339 09:59:22.126368 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1340 09:59:22.137455 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1341 09:59:22.148717 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1342 09:59:22.154322 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1343 09:59:22.165458 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1344 09:59:22.176686 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1345 09:59:22.187879 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1346 09:59:22.193660 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1347 09:59:22.204655 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1348 09:59:22.215952 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1349 09:59:22.227047 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1350 09:59:22.238354 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1351 09:59:22.243863 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1352 09:59:22.255063 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1353 09:59:22.266376 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1354 09:59:22.277444 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1355 09:59:22.283107 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1356 09:59:22.294201 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1357 09:59:22.305642 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1358 09:59:22.316611 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1359 09:59:22.327823 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1360 09:59:22.338992 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1361 09:59:22.350299 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1362 09:59:22.361376 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1363 09:59:22.372690 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1364 09:59:22.383794 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1365 09:59:22.395003 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1366 09:59:22.406125 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1367 09:59:22.417396 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1368 09:59:22.428438 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1369 09:59:22.439650 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1370 09:59:22.450827 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1371 09:59:22.462059 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1372 09:59:22.473359 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1373 09:59:22.484426 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1374 09:59:22.495659 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1375 09:59:22.506810 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1376 09:59:22.518034 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1377 09:59:22.529200 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1378 09:59:22.534777 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1379 09:59:22.545967 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1380 09:59:22.557209 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1381 09:59:22.568489 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1382 09:59:22.579564 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1383 09:59:22.590731 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1384 09:59:22.601943 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1385 09:59:22.613110 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1386 09:59:22.624325 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1387 09:59:22.635509 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1388 09:59:22.646678 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1389 09:59:22.652356 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1390 09:59:22.665981 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1391 09:59:22.674559 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1392 09:59:22.685746 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1393 09:59:22.696926 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1394 09:59:22.708235 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1395 09:59:22.719328 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1396 09:59:22.730667 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1397 09:59:22.741893 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1398 09:59:22.753062 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1399 09:59:22.764216 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1400 09:59:22.775433 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1401 09:59:22.786633 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1402 09:59:22.797854 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1403 09:59:22.809032 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1404 09:59:22.814648 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1405 09:59:22.825801 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1406 09:59:22.837024 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1407 09:59:22.848247 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1408 09:59:22.859454 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1409 09:59:22.870592 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1410 09:59:22.881778 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1411 09:59:22.892971 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1412 09:59:22.904152 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1413 09:59:22.915377 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1414 09:59:22.926411 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1415 09:59:22.937708 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1416 09:59:22.943391 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1417 09:59:22.954529 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1418 09:59:22.965692 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1419 09:59:22.971391 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1420 09:59:22.982494 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1421 09:59:22.988089 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1422 09:59:22.999307 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1423 09:59:23.010433 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1424 09:59:23.016048 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1425 09:59:23.027209 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1426 09:59:23.038394 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1427 09:59:23.049585 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1428 09:59:23.060751 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1429 09:59:23.072003 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1430 09:59:23.083086 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1431 09:59:23.099852 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1432 09:59:23.111031 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1433 09:59:23.122263 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1434 09:59:23.133489 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1435 09:59:23.144639 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1436 09:59:23.155823 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1437 09:59:23.167047 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1438 09:59:23.183799 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1439 09:59:23.195049 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1440 09:59:23.206305 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1441 09:59:23.222969 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1442 09:59:23.234149 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1443 09:59:23.239744 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1444 09:59:23.250934 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1445 09:59:23.256529 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1446 09:59:23.267726 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1447 09:59:23.278913 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1448 09:59:23.284527 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1449 09:59:23.295709 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1450 09:59:23.301309 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1451 09:59:23.312527 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1452 09:59:23.318120 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1453 09:59:23.329310 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1454 09:59:23.334865 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1455 09:59:23.346046 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1456 09:59:23.357305 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1457 09:59:23.368469 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1458 09:59:23.374066 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1459 09:59:23.385339 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1460 09:59:23.396431 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1461 09:59:23.407610 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1462 09:59:23.413331 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1463 09:59:23.418790 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1464 09:59:23.424421 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1465 09:59:23.429989 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1466 09:59:23.435644 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1467 09:59:23.446938 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1468 09:59:23.452479 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1469 09:59:23.463640 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1470 09:59:23.469295 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1471 09:59:23.474874 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1472 09:59:23.486099 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1473 09:59:23.491694 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1474 09:59:23.502873 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1475 09:59:23.508477 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1476 09:59:23.519633 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1477 09:59:23.525334 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1478 09:59:23.536474 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1479 09:59:23.542080 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1480 09:59:23.547615 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1481 09:59:23.558844 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1482 09:59:23.564452 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1483 09:59:23.575594 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1484 09:59:23.581254 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1485 09:59:23.592502 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1486 09:59:23.598044 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1487 09:59:23.609207 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1488 09:59:23.614784 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1489 09:59:23.626108 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1490 09:59:23.631676 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1491 09:59:23.642802 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1492 09:59:23.648443 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1493 09:59:23.659550 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1494 09:59:23.665213 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1495 09:59:23.670826 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1496 09:59:23.681952 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1497 09:59:23.693166 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1498 09:59:23.704405 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1499 09:59:23.715593 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1500 09:59:23.726750 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1501 09:59:23.732467 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1502 09:59:23.743531 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1503 09:59:23.754703 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1504 09:59:23.765939 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1505 09:59:23.777085 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1506 09:59:23.782746 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1507 09:59:23.793901 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1508 09:59:23.799621 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1509 09:59:23.810675 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1510 09:59:23.816320 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1511 09:59:23.827566 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1512 09:59:23.833115 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1513 09:59:23.844255 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1514 09:59:23.849921 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1515 09:59:23.861031 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1516 09:59:23.866652 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1517 09:59:23.877848 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1518 09:59:23.883498 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1519 09:59:23.894616 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1520 09:59:23.900263 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1521 09:59:23.905857 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1522 09:59:23.916983 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1523 09:59:23.922623 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1524 09:59:23.933729 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1525 09:59:23.939429 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1526 09:59:23.950568 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1527 09:59:23.956207 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1528 09:59:23.961831 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1529 09:59:23.967389 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1530 09:59:23.978562 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1531 09:59:23.984176 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1532 09:59:23.995299 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1533 09:59:24.000954 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1534 09:59:24.012116 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1535 09:59:24.023269 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1536 09:59:24.034581 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1537 09:59:24.040138 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1538 09:59:24.051280 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1539 09:59:24.062605 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1540 09:59:24.068174 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1541 09:59:24.073801 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1542 09:59:24.079461 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1543 09:59:24.084972 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1544 09:59:24.090510 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1545 09:59:24.096042 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1546 09:59:24.101653 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1547 09:59:24.107308 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1548 09:59:24.118472 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1549 09:59:24.124069 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1550 09:59:24.129625 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1551 09:59:24.135284 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1552 09:59:24.140868 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1553 09:59:24.146553 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1554 09:59:24.152146 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1555 09:59:24.157853 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1556 09:59:24.163415 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1557 09:59:24.169028 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1558 09:59:24.174657 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1559 09:59:24.180300 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1560 09:59:24.185888 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1561 09:59:24.191506 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1562 09:59:24.197089 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1563 09:59:24.202689 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1564 09:59:24.208275 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1565 09:59:24.213879 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1566 09:59:24.219518 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1567 09:59:24.225031 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1568 09:59:24.230614 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1569 09:59:24.236231 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1570 09:59:24.242028 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1571 09:59:24.247535 dt_test_unprobed_devices_sh_opp-table skip
1572 09:59:24.248101 dt_test_unprobed_devices_sh_soc skip
1573 09:59:24.253091 dt_test_unprobed_devices_sh_sound pass
1574 09:59:24.258721 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1575 09:59:24.264283 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1576 09:59:24.269900 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1577 09:59:24.275566 dt_test_unprobed_devices_sh fail
1578 09:59:24.281027 + ../../utils/send-to-lava.sh ./output/result.txt
1579 09:59:24.286780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1580 09:59:24.287655 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1582 09:59:24.291759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1583 09:59:24.292548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1585 09:59:24.381096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1586 09:59:24.381911 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1588 09:59:24.471253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1589 09:59:24.472083 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1591 09:59:24.561644 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1592 09:59:24.562633 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1594 09:59:24.654910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1595 09:59:24.655830 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1597 09:59:24.749212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1598 09:59:24.750186 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1600 09:59:24.840812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1601 09:59:24.841736 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1603 09:59:24.930444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1604 09:59:24.931364 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1606 09:59:25.026014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1607 09:59:25.026906 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1609 09:59:25.119266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1610 09:59:25.120160 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1612 09:59:25.211201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1613 09:59:25.212119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1615 09:59:25.311766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1616 09:59:25.312665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1618 09:59:25.403998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1619 09:59:25.404891 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1621 09:59:25.496170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1622 09:59:25.497053 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1624 09:59:25.588075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1625 09:59:25.589004 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1627 09:59:25.681642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1628 09:59:25.682705 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1630 09:59:25.772030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1631 09:59:25.772924 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1633 09:59:25.857603 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1634 09:59:25.858566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1636 09:59:25.950092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1637 09:59:25.951029 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1639 09:59:26.040748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1640 09:59:26.041675 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1642 09:59:26.130363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1643 09:59:26.131343 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1645 09:59:26.223114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1646 09:59:26.224014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1648 09:59:26.315508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1649 09:59:26.316350 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1651 09:59:26.406847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1652 09:59:26.407676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1654 09:59:26.499096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1655 09:59:26.499946 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1657 09:59:26.589718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1658 09:59:26.590582 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1660 09:59:26.682109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1661 09:59:26.682991 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1663 09:59:26.772946 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1664 09:59:26.773801 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1666 09:59:26.862670 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1667 09:59:26.863444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1669 09:59:26.951800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1670 09:59:26.952530 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1672 09:59:27.043523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1673 09:59:27.044266 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1675 09:59:27.135118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1676 09:59:27.135834 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1678 09:59:27.227149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1679 09:59:27.227842 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1681 09:59:27.316696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1682 09:59:27.317413 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1684 09:59:27.408299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1685 09:59:27.409066 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1687 09:59:27.500139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1688 09:59:27.500917 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1690 09:59:27.605677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1691 09:59:27.606512 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1693 09:59:27.692300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1694 09:59:27.693042 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1696 09:59:27.782416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1697 09:59:27.783141 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1699 09:59:27.893105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1700 09:59:27.893953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1702 09:59:27.983860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1703 09:59:27.984679 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1705 09:59:28.085297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1706 09:59:28.086169 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1708 09:59:28.177035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1709 09:59:28.177874 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1711 09:59:28.267287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1712 09:59:28.267950 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1714 09:59:28.356199 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1715 09:59:28.356867 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1717 09:59:28.448818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1718 09:59:28.449473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1720 09:59:28.538193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1721 09:59:28.538814 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1723 09:59:28.628967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1724 09:59:28.629774 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1726 09:59:28.724592 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1727 09:59:28.725418 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1729 09:59:28.812656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1730 09:59:28.813473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1732 09:59:28.897398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1733 09:59:28.898259 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1735 09:59:28.991166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1736 09:59:28.992002 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1738 09:59:29.082695 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1739 09:59:29.083510 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1741 09:59:29.174616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1742 09:59:29.175467 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1744 09:59:29.267386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1745 09:59:29.268241 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1747 09:59:29.360416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1748 09:59:29.361167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1750 09:59:29.452363 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1751 09:59:29.453199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1753 09:59:29.542863 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1754 09:59:29.543666 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1756 09:59:29.634266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1757 09:59:29.635094 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1759 09:59:29.725932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1760 09:59:29.726739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1762 09:59:29.816351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1763 09:59:29.817254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1765 09:59:29.919860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1766 09:59:29.920868 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1768 09:59:30.013718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1769 09:59:30.014721 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1771 09:59:30.111349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1772 09:59:30.112291 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1774 09:59:30.207405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1775 09:59:30.208532 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1777 09:59:30.314897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1778 09:59:30.315849 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1780 09:59:30.409438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1781 09:59:30.410425 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1783 09:59:30.502651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1784 09:59:30.503608 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1786 09:59:30.593631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1787 09:59:30.594621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1789 09:59:30.688804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1790 09:59:30.689976 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1792 09:59:30.787979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1793 09:59:30.788923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1795 09:59:30.887048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1796 09:59:30.888019 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1798 09:59:30.982271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1799 09:59:30.983221 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1801 09:59:31.071635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1802 09:59:31.072473 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1804 09:59:31.163004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1805 09:59:31.163858 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1807 09:59:31.254086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1808 09:59:31.254940 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1810 09:59:31.346059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1811 09:59:31.346931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1813 09:59:31.436337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1814 09:59:31.437254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1816 09:59:31.538678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1817 09:59:31.539579 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1819 09:59:31.633228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1820 09:59:31.634062 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1822 09:59:31.722802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1823 09:59:31.723622 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1825 09:59:31.813556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1826 09:59:31.814417 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1828 09:59:31.903700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1829 09:59:31.904516 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1831 09:59:31.994281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1832 09:59:31.995088 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1834 09:59:32.086071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1835 09:59:32.086938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1837 09:59:32.178787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1838 09:59:32.179631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1840 09:59:32.271290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1841 09:59:32.272123 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1843 09:59:32.362239 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1844 09:59:32.363065 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1846 09:59:32.455909 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1847 09:59:32.456750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1849 09:59:32.549142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1850 09:59:32.550008 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1852 09:59:32.640823 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1853 09:59:32.641676 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1855 09:59:32.735700 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1856 09:59:32.736596 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1858 09:59:32.836860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1859 09:59:32.837731 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1861 09:59:32.938149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1862 09:59:32.939047 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1864 09:59:33.027115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1865 09:59:33.028022 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1867 09:59:33.119259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1868 09:59:33.120102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1870 09:59:33.210531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1871 09:59:33.211350 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1873 09:59:33.302348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1874 09:59:33.303227 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1876 09:59:33.394153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1877 09:59:33.394979 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1879 09:59:33.486626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1880 09:59:33.487313 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1882 09:59:33.578641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1883 09:59:33.579468 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1885 09:59:33.667984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1886 09:59:33.668856 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1888 09:59:33.761153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1889 09:59:33.762004 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1891 09:59:33.848225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1892 09:59:33.849074 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1894 09:59:33.942037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1895 09:59:33.942890 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1897 09:59:34.032712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1898 09:59:34.033562 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1900 09:59:34.124126 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1901 09:59:34.124994 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1903 09:59:34.218514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1904 09:59:34.219475 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1906 09:59:34.312114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1907 09:59:34.313038 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1909 09:59:34.405208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1910 09:59:34.406119 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1912 09:59:34.506001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1913 09:59:34.506879 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1915 09:59:34.597050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1916 09:59:34.597931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1918 09:59:34.689760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1919 09:59:34.690674 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1921 09:59:34.783549 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1922 09:59:34.785733 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1924 09:59:34.874244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1925 09:59:34.875120 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1927 09:59:34.966244 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1928 09:59:34.967094 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1930 09:59:35.057934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1931 09:59:35.058833 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1933 09:59:35.150164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1934 09:59:35.151039 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1936 09:59:35.240574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1937 09:59:35.241446 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1939 09:59:35.331385 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1941 09:59:35.334574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1942 09:59:35.422479 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1944 09:59:35.425727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1945 09:59:35.508021 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1947 09:59:35.511030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1948 09:59:35.602061 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1949 09:59:35.602713 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1951 09:59:35.690760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1952 09:59:35.691974 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1954 09:59:35.781774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1955 09:59:35.782717 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1957 09:59:35.874760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1958 09:59:35.875686 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1960 09:59:35.966339 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1961 09:59:35.967228 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1963 09:59:36.059019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1964 09:59:36.059916 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1966 09:59:36.150710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1967 09:59:36.151580 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1969 09:59:36.242687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1970 09:59:36.243563 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1972 09:59:36.333940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1973 09:59:36.334812 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1975 09:59:36.427697 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1976 09:59:36.428567 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1978 09:59:36.518966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1979 09:59:36.519894 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1981 09:59:36.611574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1982 09:59:36.612453 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1984 09:59:36.703002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1985 09:59:36.703907 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1987 09:59:36.794829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1988 09:59:36.795727 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1990 09:59:36.885103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1991 09:59:36.886007 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1993 09:59:36.975956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
1994 09:59:36.976841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
1996 09:59:37.064460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
1997 09:59:37.065354 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
1999 09:59:37.155091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2000 09:59:37.155967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2002 09:59:37.252780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2003 09:59:37.253415 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2005 09:59:37.342012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2006 09:59:37.342621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2008 09:59:37.429900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2009 09:59:37.430560 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2011 09:59:37.517462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2012 09:59:37.518213 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2014 09:59:37.606831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2015 09:59:37.607441 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2017 09:59:37.696782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2018 09:59:37.697418 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2020 09:59:37.787179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2021 09:59:37.787998 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2023 09:59:37.879875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2024 09:59:37.880705 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2026 09:59:37.971641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2027 09:59:37.972270 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2029 09:59:38.060227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2030 09:59:38.061094 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2032 09:59:38.150886 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2033 09:59:38.151761 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2035 09:59:38.240668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2036 09:59:38.241501 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2038 09:59:38.335272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2039 09:59:38.336067 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2041 09:59:38.425358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2042 09:59:38.426176 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2044 09:59:38.515772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2045 09:59:38.516541 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2047 09:59:38.609450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2048 09:59:38.610305 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2050 09:59:38.698925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2051 09:59:38.699719 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2053 09:59:38.789211 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2054 09:59:38.790016 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2056 09:59:38.880396 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2057 09:59:38.881149 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2059 09:59:38.969444 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2060 09:59:38.970238 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2062 09:59:39.054498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2063 09:59:39.055481 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2065 09:59:39.146087 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2066 09:59:39.146961 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2068 09:59:39.238499 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2069 09:59:39.239163 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2071 09:59:39.329547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2072 09:59:39.330274 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2074 09:59:39.420238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2075 09:59:39.421076 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2077 09:59:39.510891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2078 09:59:39.511649 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2080 09:59:39.599469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2081 09:59:39.600249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2083 09:59:39.690666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2084 09:59:39.691488 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2086 09:59:39.779584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2087 09:59:39.780358 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2089 09:59:39.867390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2090 09:59:39.868125 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2092 09:59:39.959233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2093 09:59:39.959931 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2095 09:59:40.051447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2096 09:59:40.052164 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2098 09:59:40.140397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2099 09:59:40.141105 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2101 09:59:40.233891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2102 09:59:40.234597 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2104 09:59:40.325447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2105 09:59:40.326060 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2107 09:59:40.419537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2108 09:59:40.420460 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2110 09:59:40.510481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2111 09:59:40.511433 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2113 09:59:40.603483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2114 09:59:40.604284 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2116 09:59:40.697164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2117 09:59:40.697966 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2119 09:59:40.786851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2120 09:59:40.787444 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2122 09:59:40.881657 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2123 09:59:40.882327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2125 09:59:40.971556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2126 09:59:40.972161 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2128 09:59:41.063466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2129 09:59:41.064059 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2131 09:59:41.147672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2132 09:59:41.148277 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2134 09:59:41.239758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2135 09:59:41.240373 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2137 09:59:41.328025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2138 09:59:41.328665 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2140 09:59:41.417615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2141 09:59:41.418344 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2143 09:59:41.510169 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2144 09:59:41.510778 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2146 09:59:41.600232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2147 09:59:41.600840 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2149 09:59:41.683575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2150 09:59:41.684378 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2152 09:59:41.773176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2153 09:59:41.773790 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2155 09:59:41.864833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2156 09:59:41.865439 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2158 09:59:41.956710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2159 09:59:41.957316 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2161 09:59:42.047661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2162 09:59:42.048264 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2164 09:59:42.138771 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2165 09:59:42.139490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2167 09:59:42.228276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2168 09:59:42.229150 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2170 09:59:42.316883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2171 09:59:42.317480 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2173 09:59:42.405804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2174 09:59:42.406396 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2176 09:59:42.498349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2177 09:59:42.498953 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2179 09:59:42.590316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2180 09:59:42.590913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2182 09:59:42.676750 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2183 09:59:42.677325 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2185 09:59:42.770338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2186 09:59:42.770907 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2188 09:59:42.860250 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2189 09:59:42.860822 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2191 09:59:42.953337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2192 09:59:42.953927 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2194 09:59:43.043920 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2195 09:59:43.044490 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2197 09:59:43.134719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2198 09:59:43.135292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2200 09:59:43.224911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2201 09:59:43.225505 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2203 09:59:43.315272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2204 09:59:43.315854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2206 09:59:43.403707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2207 09:59:43.404272 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2209 09:59:43.496400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2210 09:59:43.496990 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2212 09:59:43.590684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2213 09:59:43.591294 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2215 09:59:43.680676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2216 09:59:43.681540 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2218 09:59:43.771520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2219 09:59:43.772367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2221 09:59:43.860981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2222 09:59:43.861862 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2224 09:59:43.951712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2225 09:59:43.952560 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2227 09:59:44.045085 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2228 09:59:44.045935 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2230 09:59:44.138999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2231 09:59:44.139841 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2233 09:59:44.229433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2234 09:59:44.230307 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2236 09:59:44.318805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2237 09:59:44.319628 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2239 09:59:44.410643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2240 09:59:44.411470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2242 09:59:44.495721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2243 09:59:44.496607 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2245 09:59:44.588238 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2246 09:59:44.589195 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2248 09:59:44.678665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2249 09:59:44.679538 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2251 09:59:44.767673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2252 09:59:44.768545 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2254 09:59:44.858815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2255 09:59:44.859685 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2257 09:59:44.953479 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2258 09:59:44.954375 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2260 09:59:45.041972 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2262 09:59:45.044083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2263 09:59:45.133967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2264 09:59:45.134812 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2266 09:59:45.227084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2267 09:59:45.227907 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2269 09:59:45.317418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2270 09:59:45.318274 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2272 09:59:45.405853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2273 09:59:45.406702 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2275 09:59:45.491331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2276 09:59:45.492180 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2278 09:59:45.582664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2279 09:59:45.583510 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2281 09:59:45.675012 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2282 09:59:45.675889 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2284 09:59:45.766426 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2285 09:59:45.767282 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2287 09:59:45.857399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2288 09:59:45.858285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2290 09:59:45.946976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2291 09:59:45.947969 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2293 09:59:46.033772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2294 09:59:46.034718 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2296 09:59:46.125399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2297 09:59:46.126293 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2299 09:59:46.217618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2300 09:59:46.218724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2302 09:59:46.309316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2303 09:59:46.310232 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2305 09:59:46.401714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2306 09:59:46.402696 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2308 09:59:46.493369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2309 09:59:46.494345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2311 09:59:46.585421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2312 09:59:46.586345 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2314 09:59:46.674931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2315 09:59:46.675821 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2317 09:59:46.766177 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2318 09:59:46.767058 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2320 09:59:46.857123 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2321 09:59:46.858012 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2323 09:59:46.945624 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2324 09:59:46.946499 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2326 09:59:47.036663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2327 09:59:47.037537 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2329 09:59:47.126488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2330 09:59:47.127412 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2332 09:59:47.217200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2333 09:59:47.218043 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2335 09:59:47.305668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2336 09:59:47.306564 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2338 09:59:47.395183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2339 09:59:47.396075 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2341 09:59:47.482028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2342 09:59:47.482621 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2344 09:59:47.575639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2345 09:59:47.576495 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2347 09:59:47.678425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2348 09:59:47.679340 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2350 09:59:47.770180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2351 09:59:47.771036 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2353 09:59:47.858497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2354 09:59:47.859124 + set +x
2355 09:59:47.859967 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2357 09:59:47.862757 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 939283_1.6.2.4.5>
2358 09:59:47.863559 Received signal: <ENDRUN> 1_kselftest-dt 939283_1.6.2.4.5
2359 09:59:47.864071 Ending use of test pattern.
2360 09:59:47.864517 Ending test lava.1_kselftest-dt (939283_1.6.2.4.5), duration 85.69
2362 09:59:47.870309 <LAVA_TEST_RUNNER EXIT>
2363 09:59:47.871080 ok: lava_test_shell seems to have completed
2364 09:59:47.885103 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2365 09:59:47.887315 end: 3.1 lava-test-shell (duration 00:01:27) [common]
2366 09:59:47.887963 end: 3 lava-test-retry (duration 00:01:27) [common]
2367 09:59:47.888587 start: 4 finalize (timeout 00:05:26) [common]
2368 09:59:47.889248 start: 4.1 power-off (timeout 00:00:30) [common]
2369 09:59:47.890368 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-05'
2370 09:59:47.925068 >> OK - accepted request
2371 09:59:47.926894 Returned 0 in 0 seconds
2372 09:59:48.028076 end: 4.1 power-off (duration 00:00:00) [common]
2374 09:59:48.029888 start: 4.2 read-feedback (timeout 00:05:26) [common]
2375 09:59:48.031130 Listened to connection for namespace 'common' for up to 1s
2376 09:59:48.032036 Listened to connection for namespace 'common' for up to 1s
2377 09:59:49.031565 Finalising connection for namespace 'common'
2378 09:59:49.032346 Disconnecting from shell: Finalise
2379 09:59:49.032916 / #
2380 09:59:49.133969 end: 4.2 read-feedback (duration 00:00:01) [common]
2381 09:59:49.134719 end: 4 finalize (duration 00:00:01) [common]
2382 09:59:49.135427 Cleaning after the job
2383 09:59:49.136139 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939283/tftp-deploy-sgxvwu_s/ramdisk
2384 09:59:49.139350 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939283/tftp-deploy-sgxvwu_s/kernel
2385 09:59:49.141479 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939283/tftp-deploy-sgxvwu_s/dtb
2386 09:59:49.142820 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939283/tftp-deploy-sgxvwu_s/nfsrootfs
2387 09:59:49.195924 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939283/tftp-deploy-sgxvwu_s/modules
2388 09:59:49.199976 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/939283
2389 09:59:52.061133 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/939283
2390 09:59:52.061674 Job finished correctly