Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 09:32:44.889144 lava-dispatcher, installed at version: 2024.01
2 09:32:44.889942 start: 0 validate
3 09:32:44.890426 Start time: 2024-11-05 09:32:44.890397+00:00 (UTC)
4 09:32:44.890959 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 09:32:44.891502 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 09:32:44.935085 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 09:32:44.935617 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-401-g1596ed05f2f47%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 09:32:44.970624 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 09:32:44.971240 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-401-g1596ed05f2f47%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 09:32:46.020468 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 09:32:46.020986 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-401-g1596ed05f2f47%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 09:32:46.065321 validate duration: 1.18
14 09:32:46.066775 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:32:46.067393 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:32:46.067961 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:32:46.068980 Not decompressing ramdisk as can be used compressed.
18 09:32:46.069723 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 09:32:46.070178 saving as /var/lib/lava/dispatcher/tmp/939397/tftp-deploy-kzpkb545/ramdisk/rootfs.cpio.gz
20 09:32:46.070658 total size: 8181887 (7 MB)
21 09:32:46.110509 progress 0 % (0 MB)
22 09:32:46.122353 progress 5 % (0 MB)
23 09:32:46.133485 progress 10 % (0 MB)
24 09:32:46.145537 progress 15 % (1 MB)
25 09:32:46.153986 progress 20 % (1 MB)
26 09:32:46.159607 progress 25 % (1 MB)
27 09:32:46.164813 progress 30 % (2 MB)
28 09:32:46.170409 progress 35 % (2 MB)
29 09:32:46.175543 progress 40 % (3 MB)
30 09:32:46.181059 progress 45 % (3 MB)
31 09:32:46.186235 progress 50 % (3 MB)
32 09:32:46.191807 progress 55 % (4 MB)
33 09:32:46.197049 progress 60 % (4 MB)
34 09:32:46.202554 progress 65 % (5 MB)
35 09:32:46.207713 progress 70 % (5 MB)
36 09:32:46.213222 progress 75 % (5 MB)
37 09:32:46.218353 progress 80 % (6 MB)
38 09:32:46.223802 progress 85 % (6 MB)
39 09:32:46.228894 progress 90 % (7 MB)
40 09:32:46.234314 progress 95 % (7 MB)
41 09:32:46.238962 progress 100 % (7 MB)
42 09:32:46.239594 7 MB downloaded in 0.17 s (46.19 MB/s)
43 09:32:46.240169 end: 1.1.1 http-download (duration 00:00:00) [common]
45 09:32:46.241047 end: 1.1 download-retry (duration 00:00:00) [common]
46 09:32:46.241333 start: 1.2 download-retry (timeout 00:10:00) [common]
47 09:32:46.241598 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 09:32:46.242066 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-401-g1596ed05f2f47/arm64/defconfig/gcc-12/kernel/Image
49 09:32:46.242305 saving as /var/lib/lava/dispatcher/tmp/939397/tftp-deploy-kzpkb545/kernel/Image
50 09:32:46.242510 total size: 45713920 (43 MB)
51 09:32:46.242719 No compression specified
52 09:32:46.282171 progress 0 % (0 MB)
53 09:32:46.310752 progress 5 % (2 MB)
54 09:32:46.339271 progress 10 % (4 MB)
55 09:32:46.368529 progress 15 % (6 MB)
56 09:32:46.397061 progress 20 % (8 MB)
57 09:32:46.426127 progress 25 % (10 MB)
58 09:32:46.454888 progress 30 % (13 MB)
59 09:32:46.483871 progress 35 % (15 MB)
60 09:32:46.513603 progress 40 % (17 MB)
61 09:32:46.542259 progress 45 % (19 MB)
62 09:32:46.571682 progress 50 % (21 MB)
63 09:32:46.600770 progress 55 % (24 MB)
64 09:32:46.630155 progress 60 % (26 MB)
65 09:32:46.659098 progress 65 % (28 MB)
66 09:32:46.688196 progress 70 % (30 MB)
67 09:32:46.717408 progress 75 % (32 MB)
68 09:32:46.746436 progress 80 % (34 MB)
69 09:32:46.774766 progress 85 % (37 MB)
70 09:32:46.803926 progress 90 % (39 MB)
71 09:32:46.834811 progress 95 % (41 MB)
72 09:32:46.863241 progress 100 % (43 MB)
73 09:32:46.863775 43 MB downloaded in 0.62 s (70.17 MB/s)
74 09:32:46.864287 end: 1.2.1 http-download (duration 00:00:01) [common]
76 09:32:46.865103 end: 1.2 download-retry (duration 00:00:01) [common]
77 09:32:46.865378 start: 1.3 download-retry (timeout 00:09:59) [common]
78 09:32:46.865639 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 09:32:46.866132 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-401-g1596ed05f2f47/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 09:32:46.866408 saving as /var/lib/lava/dispatcher/tmp/939397/tftp-deploy-kzpkb545/dtb/meson-g12b-a311d-libretech-cc.dtb
81 09:32:46.866617 total size: 54703 (0 MB)
82 09:32:46.866825 No compression specified
83 09:32:46.910170 progress 59 % (0 MB)
84 09:32:46.911011 progress 100 % (0 MB)
85 09:32:46.911582 0 MB downloaded in 0.04 s (1.16 MB/s)
86 09:32:46.912084 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:32:46.912911 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:32:46.913173 start: 1.4 download-retry (timeout 00:09:59) [common]
90 09:32:46.913435 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 09:32:46.913915 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-401-g1596ed05f2f47/arm64/defconfig/gcc-12/modules.tar.xz
92 09:32:46.914167 saving as /var/lib/lava/dispatcher/tmp/939397/tftp-deploy-kzpkb545/modules/modules.tar
93 09:32:46.914373 total size: 11611116 (11 MB)
94 09:32:46.914582 Using unxz to decompress xz
95 09:32:46.947312 progress 0 % (0 MB)
96 09:32:47.015176 progress 5 % (0 MB)
97 09:32:47.091265 progress 10 % (1 MB)
98 09:32:47.190518 progress 15 % (1 MB)
99 09:32:47.283619 progress 20 % (2 MB)
100 09:32:47.362855 progress 25 % (2 MB)
101 09:32:47.439787 progress 30 % (3 MB)
102 09:32:47.518745 progress 35 % (3 MB)
103 09:32:47.591829 progress 40 % (4 MB)
104 09:32:47.668553 progress 45 % (5 MB)
105 09:32:47.753038 progress 50 % (5 MB)
106 09:32:47.830592 progress 55 % (6 MB)
107 09:32:47.916577 progress 60 % (6 MB)
108 09:32:47.998162 progress 65 % (7 MB)
109 09:32:48.079706 progress 70 % (7 MB)
110 09:32:48.158533 progress 75 % (8 MB)
111 09:32:48.244682 progress 80 % (8 MB)
112 09:32:48.328112 progress 85 % (9 MB)
113 09:32:48.413195 progress 90 % (9 MB)
114 09:32:48.495028 progress 95 % (10 MB)
115 09:32:48.574919 progress 100 % (11 MB)
116 09:32:48.588215 11 MB downloaded in 1.67 s (6.62 MB/s)
117 09:32:48.589325 end: 1.4.1 http-download (duration 00:00:02) [common]
119 09:32:48.591126 end: 1.4 download-retry (duration 00:00:02) [common]
120 09:32:48.591707 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 09:32:48.592331 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 09:32:48.592884 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:32:48.593438 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 09:32:48.594528 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q
125 09:32:48.595489 makedir: /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin
126 09:32:48.596283 makedir: /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/tests
127 09:32:48.596999 makedir: /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/results
128 09:32:48.597682 Creating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin/lava-add-keys
129 09:32:48.598774 Creating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin/lava-add-sources
130 09:32:48.599904 Creating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin/lava-background-process-start
131 09:32:48.601111 Creating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin/lava-background-process-stop
132 09:32:48.602305 Creating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin/lava-common-functions
133 09:32:48.603419 Creating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin/lava-echo-ipv4
134 09:32:48.604525 Creating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin/lava-install-packages
135 09:32:48.605583 Creating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin/lava-installed-packages
136 09:32:48.606619 Creating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin/lava-os-build
137 09:32:48.607855 Creating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin/lava-probe-channel
138 09:32:48.608987 Creating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin/lava-probe-ip
139 09:32:48.610001 Creating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin/lava-target-ip
140 09:32:48.610982 Creating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin/lava-target-mac
141 09:32:48.612022 Creating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin/lava-target-storage
142 09:32:48.613076 Creating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin/lava-test-case
143 09:32:48.614109 Creating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin/lava-test-event
144 09:32:48.615125 Creating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin/lava-test-feedback
145 09:32:48.616254 Creating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin/lava-test-raise
146 09:32:48.617284 Creating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin/lava-test-reference
147 09:32:48.618302 Creating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin/lava-test-runner
148 09:32:48.619349 Creating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin/lava-test-set
149 09:32:48.620477 Creating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin/lava-test-shell
150 09:32:48.621653 Updating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin/lava-install-packages (oe)
151 09:32:48.622759 Updating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/bin/lava-installed-packages (oe)
152 09:32:48.623752 Creating /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/environment
153 09:32:48.624684 LAVA metadata
154 09:32:48.625226 - LAVA_JOB_ID=939397
155 09:32:48.625692 - LAVA_DISPATCHER_IP=192.168.6.2
156 09:32:48.626431 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 09:32:48.628466 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 09:32:48.629123 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 09:32:48.629577 skipped lava-vland-overlay
160 09:32:48.630114 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 09:32:48.630671 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 09:32:48.631140 skipped lava-multinode-overlay
163 09:32:48.631678 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 09:32:48.632267 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 09:32:48.632802 Loading test definitions
166 09:32:48.633415 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 09:32:48.633902 Using /lava-939397 at stage 0
168 09:32:48.636472 uuid=939397_1.5.2.4.1 testdef=None
169 09:32:48.637161 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 09:32:48.637735 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 09:32:48.641730 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 09:32:48.643366 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 09:32:48.647916 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 09:32:48.649620 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 09:32:48.653922 runner path: /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/0/tests/0_dmesg test_uuid 939397_1.5.2.4.1
178 09:32:48.654997 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 09:32:48.656313 Creating lava-test-runner.conf files
181 09:32:48.656527 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/939397/lava-overlay-tz_j669q/lava-939397/0 for stage 0
182 09:32:48.656910 - 0_dmesg
183 09:32:48.657299 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 09:32:48.657593 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 09:32:48.682100 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 09:32:48.682544 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 09:32:48.682809 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 09:32:48.683081 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 09:32:48.683347 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 09:32:49.611172 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 09:32:49.611628 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 09:32:49.611877 extracting modules file /var/lib/lava/dispatcher/tmp/939397/tftp-deploy-kzpkb545/modules/modules.tar to /var/lib/lava/dispatcher/tmp/939397/extract-overlay-ramdisk-_frxi37h/ramdisk
193 09:32:50.929110 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 09:32:50.929590 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 09:32:50.929863 [common] Applying overlay /var/lib/lava/dispatcher/tmp/939397/compress-overlay-940fwr0u/overlay-1.5.2.5.tar.gz to ramdisk
196 09:32:50.930074 [common] Applying overlay /var/lib/lava/dispatcher/tmp/939397/compress-overlay-940fwr0u/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/939397/extract-overlay-ramdisk-_frxi37h/ramdisk
197 09:32:50.959885 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 09:32:50.960318 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 09:32:50.960585 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 09:32:50.960809 Converting downloaded kernel to a uImage
201 09:32:50.961111 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/939397/tftp-deploy-kzpkb545/kernel/Image /var/lib/lava/dispatcher/tmp/939397/tftp-deploy-kzpkb545/kernel/uImage
202 09:32:51.420158 output: Image Name:
203 09:32:51.420549 output: Created: Tue Nov 5 09:32:50 2024
204 09:32:51.420757 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 09:32:51.420963 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 09:32:51.421165 output: Load Address: 01080000
207 09:32:51.421362 output: Entry Point: 01080000
208 09:32:51.421557 output:
209 09:32:51.421889 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 09:32:51.422200 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 09:32:51.422492 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 09:32:51.422749 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 09:32:51.423011 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 09:32:51.423266 Building ramdisk /var/lib/lava/dispatcher/tmp/939397/extract-overlay-ramdisk-_frxi37h/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/939397/extract-overlay-ramdisk-_frxi37h/ramdisk
215 09:32:53.906919 >> 181608 blocks
216 09:33:02.437953 Adding RAMdisk u-boot header.
217 09:33:02.438659 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/939397/extract-overlay-ramdisk-_frxi37h/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/939397/extract-overlay-ramdisk-_frxi37h/ramdisk.cpio.gz.uboot
218 09:33:02.721704 output: Image Name:
219 09:33:02.722089 output: Created: Tue Nov 5 09:33:02 2024
220 09:33:02.722296 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 09:33:02.722497 output: Data Size: 26062861 Bytes = 25452.01 KiB = 24.86 MiB
222 09:33:02.722698 output: Load Address: 00000000
223 09:33:02.722895 output: Entry Point: 00000000
224 09:33:02.723090 output:
225 09:33:02.723724 rename /var/lib/lava/dispatcher/tmp/939397/extract-overlay-ramdisk-_frxi37h/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/939397/tftp-deploy-kzpkb545/ramdisk/ramdisk.cpio.gz.uboot
226 09:33:02.724268 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 09:33:02.724868 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 09:33:02.725439 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 09:33:02.725931 No LXC device requested
230 09:33:02.726471 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 09:33:02.727017 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 09:33:02.727551 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 09:33:02.728021 Checking files for TFTP limit of 4294967296 bytes.
234 09:33:02.730911 end: 1 tftp-deploy (duration 00:00:17) [common]
235 09:33:02.731523 start: 2 uboot-action (timeout 00:05:00) [common]
236 09:33:02.732117 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 09:33:02.732666 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 09:33:02.733209 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 09:33:02.733777 Using kernel file from prepare-kernel: 939397/tftp-deploy-kzpkb545/kernel/uImage
240 09:33:02.734453 substitutions:
241 09:33:02.734904 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 09:33:02.735343 - {DTB_ADDR}: 0x01070000
243 09:33:02.735779 - {DTB}: 939397/tftp-deploy-kzpkb545/dtb/meson-g12b-a311d-libretech-cc.dtb
244 09:33:02.736253 - {INITRD}: 939397/tftp-deploy-kzpkb545/ramdisk/ramdisk.cpio.gz.uboot
245 09:33:02.736693 - {KERNEL_ADDR}: 0x01080000
246 09:33:02.737128 - {KERNEL}: 939397/tftp-deploy-kzpkb545/kernel/uImage
247 09:33:02.737562 - {LAVA_MAC}: None
248 09:33:02.738035 - {PRESEED_CONFIG}: None
249 09:33:02.738471 - {PRESEED_LOCAL}: None
250 09:33:02.738898 - {RAMDISK_ADDR}: 0x08000000
251 09:33:02.739321 - {RAMDISK}: 939397/tftp-deploy-kzpkb545/ramdisk/ramdisk.cpio.gz.uboot
252 09:33:02.739754 - {ROOT_PART}: None
253 09:33:02.740217 - {ROOT}: None
254 09:33:02.740649 - {SERVER_IP}: 192.168.6.2
255 09:33:02.741079 - {TEE_ADDR}: 0x83000000
256 09:33:02.741507 - {TEE}: None
257 09:33:02.741934 Parsed boot commands:
258 09:33:02.742351 - setenv autoload no
259 09:33:02.742773 - setenv initrd_high 0xffffffff
260 09:33:02.743197 - setenv fdt_high 0xffffffff
261 09:33:02.743621 - dhcp
262 09:33:02.744071 - setenv serverip 192.168.6.2
263 09:33:02.744498 - tftpboot 0x01080000 939397/tftp-deploy-kzpkb545/kernel/uImage
264 09:33:02.744922 - tftpboot 0x08000000 939397/tftp-deploy-kzpkb545/ramdisk/ramdisk.cpio.gz.uboot
265 09:33:02.745348 - tftpboot 0x01070000 939397/tftp-deploy-kzpkb545/dtb/meson-g12b-a311d-libretech-cc.dtb
266 09:33:02.745773 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 09:33:02.746203 - bootm 0x01080000 0x08000000 0x01070000
268 09:33:02.746733 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 09:33:02.748372 start: 2.3 connect-device (timeout 00:05:00) [common]
271 09:33:02.748851 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 09:33:02.763509 Setting prompt string to ['lava-test: # ']
273 09:33:02.765100 end: 2.3 connect-device (duration 00:00:00) [common]
274 09:33:02.765749 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 09:33:02.766402 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 09:33:02.767062 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 09:33:02.768348 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 09:33:02.805711 >> OK - accepted request
279 09:33:02.807806 Returned 0 in 0 seconds
280 09:33:02.908875 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 09:33:02.910553 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 09:33:02.911161 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 09:33:02.911707 Setting prompt string to ['Hit any key to stop autoboot']
285 09:33:02.912256 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 09:33:02.913964 Trying 192.168.56.21...
287 09:33:02.914474 Connected to conserv1.
288 09:33:02.914918 Escape character is '^]'.
289 09:33:02.915369
290 09:33:02.915824 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 09:33:02.916336
292 09:33:14.332051 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 09:33:14.332764 bl2_stage_init 0x01
294 09:33:14.333258 bl2_stage_init 0x81
295 09:33:14.337467 hw id: 0x0000 - pwm id 0x01
296 09:33:14.338077 bl2_stage_init 0xc1
297 09:33:14.338547 bl2_stage_init 0x02
298 09:33:14.339070
299 09:33:14.343114 L0:00000000
300 09:33:14.343666 L1:20000703
301 09:33:14.344165 L2:00008067
302 09:33:14.344578 L3:14000000
303 09:33:14.345911 B2:00402000
304 09:33:14.346342 B1:e0f83180
305 09:33:14.346737
306 09:33:14.347130 TE: 58124
307 09:33:14.347519
308 09:33:14.357087 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 09:33:14.357651
310 09:33:14.358062 Board ID = 1
311 09:33:14.358477 Set A53 clk to 24M
312 09:33:14.358875 Set A73 clk to 24M
313 09:33:14.362665 Set clk81 to 24M
314 09:33:14.363169 A53 clk: 1200 MHz
315 09:33:14.363570 A73 clk: 1200 MHz
316 09:33:14.368225 CLK81: 166.6M
317 09:33:14.368733 smccc: 00012a92
318 09:33:14.374036 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 09:33:14.374551 board id: 1
320 09:33:14.382479 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 09:33:14.393102 fw parse done
322 09:33:14.399108 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 09:33:14.441593 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 09:33:14.452429 PIEI prepare done
325 09:33:14.452885 fastboot data load
326 09:33:14.453285 fastboot data verify
327 09:33:14.458131 verify result: 266
328 09:33:14.463737 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 09:33:14.464319 LPDDR4 probe
330 09:33:14.464723 ddr clk to 1584MHz
331 09:33:14.471691 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 09:33:14.509575
333 09:33:14.510144 dmc_version 0001
334 09:33:14.515624 Check phy result
335 09:33:14.521496 INFO : End of CA training
336 09:33:14.521961 INFO : End of initialization
337 09:33:14.527105 INFO : Training has run successfully!
338 09:33:14.527556 Check phy result
339 09:33:14.532653 INFO : End of initialization
340 09:33:14.533107 INFO : End of read enable training
341 09:33:14.536057 INFO : End of fine write leveling
342 09:33:14.541669 INFO : End of Write leveling coarse delay
343 09:33:14.547234 INFO : Training has run successfully!
344 09:33:14.547711 Check phy result
345 09:33:14.548168 INFO : End of initialization
346 09:33:14.552816 INFO : End of read dq deskew training
347 09:33:14.556213 INFO : End of MPR read delay center optimization
348 09:33:14.561748 INFO : End of write delay center optimization
349 09:33:14.567564 INFO : End of read delay center optimization
350 09:33:14.568076 INFO : End of max read latency training
351 09:33:14.573083 INFO : Training has run successfully!
352 09:33:14.573541 1D training succeed
353 09:33:14.581213 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 09:33:14.628844 Check phy result
355 09:33:14.629448 INFO : End of initialization
356 09:33:14.651157 INFO : End of 2D read delay Voltage center optimization
357 09:33:14.671183 INFO : End of 2D read delay Voltage center optimization
358 09:33:14.723127 INFO : End of 2D write delay Voltage center optimization
359 09:33:14.772355 INFO : End of 2D write delay Voltage center optimization
360 09:33:14.777928 INFO : Training has run successfully!
361 09:33:14.778389
362 09:33:14.778812 channel==0
363 09:33:14.783487 RxClkDly_Margin_A0==88 ps 9
364 09:33:14.783936 TxDqDly_Margin_A0==98 ps 10
365 09:33:14.789097 RxClkDly_Margin_A1==88 ps 9
366 09:33:14.789543 TxDqDly_Margin_A1==98 ps 10
367 09:33:14.789959 TrainedVREFDQ_A0==74
368 09:33:14.794665 TrainedVREFDQ_A1==76
369 09:33:14.795109 VrefDac_Margin_A0==25
370 09:33:14.795518 DeviceVref_Margin_A0==40
371 09:33:14.800291 VrefDac_Margin_A1==24
372 09:33:14.800736 DeviceVref_Margin_A1==38
373 09:33:14.801150
374 09:33:14.801555
375 09:33:14.806009 channel==1
376 09:33:14.806560 RxClkDly_Margin_A0==98 ps 10
377 09:33:14.806998 TxDqDly_Margin_A0==88 ps 9
378 09:33:14.811781 RxClkDly_Margin_A1==88 ps 9
379 09:33:14.812357 TxDqDly_Margin_A1==88 ps 9
380 09:33:14.817272 TrainedVREFDQ_A0==77
381 09:33:14.817881 TrainedVREFDQ_A1==77
382 09:33:14.818334 VrefDac_Margin_A0==22
383 09:33:14.822795 DeviceVref_Margin_A0==37
384 09:33:14.823379 VrefDac_Margin_A1==24
385 09:33:14.828679 DeviceVref_Margin_A1==37
386 09:33:14.829296
387 09:33:14.829774 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 09:33:14.830228
389 09:33:14.862196 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000018 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
390 09:33:14.862857 2D training succeed
391 09:33:14.867632 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 09:33:14.873175 auto size-- 65535DDR cs0 size: 2048MB
393 09:33:14.873674 DDR cs1 size: 2048MB
394 09:33:14.878715 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 09:33:14.879187 cs0 DataBus test pass
396 09:33:14.884313 cs1 DataBus test pass
397 09:33:14.884785 cs0 AddrBus test pass
398 09:33:14.885199 cs1 AddrBus test pass
399 09:33:14.885604
400 09:33:14.889959 100bdlr_step_size ps== 420
401 09:33:14.890473 result report
402 09:33:14.895547 boot times 0Enable ddr reg access
403 09:33:14.900842 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 09:33:14.913357 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 09:33:15.486162 0.0;M3 CHK:0;cm4_sp_mode 0
406 09:33:15.486793 MVN_1=0x00000000
407 09:33:15.491646 MVN_2=0x00000000
408 09:33:15.497494 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 09:33:15.497953 OPS=0x10
410 09:33:15.498371 ring efuse init
411 09:33:15.498777 chipver efuse init
412 09:33:15.502990 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 09:33:15.508611 [0.018961 Inits done]
414 09:33:15.509108 secure task start!
415 09:33:15.509533 high task start!
416 09:33:15.512214 low task start!
417 09:33:15.512657 run into bl31
418 09:33:15.519898 NOTICE: BL31: v1.3(release):4fc40b1
419 09:33:15.527668 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 09:33:15.528148 NOTICE: BL31: G12A normal boot!
421 09:33:15.553575 NOTICE: BL31: BL33 decompress pass
422 09:33:15.559222 ERROR: Error initializing runtime service opteed_fast
423 09:33:16.792271
424 09:33:16.792886
425 09:33:16.800601 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 09:33:16.801051
427 09:33:16.801464 Model: Libre Computer AML-A311D-CC Alta
428 09:33:17.008814 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 09:33:17.032515 DRAM: 2 GiB (effective 3.8 GiB)
430 09:33:17.175384 Core: 408 devices, 31 uclasses, devicetree: separate
431 09:33:17.181148 WDT: Not starting watchdog@f0d0
432 09:33:17.213447 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 09:33:17.225901 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 09:33:17.230903 ** Bad device specification mmc 0 **
435 09:33:17.241328 Card did not respond to voltage select! : -110
436 09:33:17.248623 ** Bad device specification mmc 0 **
437 09:33:17.248907 Couldn't find partition mmc 0
438 09:33:17.257241 Card did not respond to voltage select! : -110
439 09:33:17.262710 ** Bad device specification mmc 0 **
440 09:33:17.262995 Couldn't find partition mmc 0
441 09:33:17.267807 Error: could not access storage.
442 09:33:18.532278 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 09:33:18.532726 bl2_stage_init 0x01
444 09:33:18.532955 bl2_stage_init 0x81
445 09:33:18.537820 hw id: 0x0000 - pwm id 0x01
446 09:33:18.538104 bl2_stage_init 0xc1
447 09:33:18.538319 bl2_stage_init 0x02
448 09:33:18.538526
449 09:33:18.543406 L0:00000000
450 09:33:18.543725 L1:20000703
451 09:33:18.543939 L2:00008067
452 09:33:18.544184 L3:14000000
453 09:33:18.548972 B2:00402000
454 09:33:18.549247 B1:e0f83180
455 09:33:18.549455
456 09:33:18.549657 TE: 58167
457 09:33:18.549858
458 09:33:18.554589 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 09:33:18.554863
460 09:33:18.555180 Board ID = 1
461 09:33:18.560186 Set A53 clk to 24M
462 09:33:18.560445 Set A73 clk to 24M
463 09:33:18.560658 Set clk81 to 24M
464 09:33:18.565935 A53 clk: 1200 MHz
465 09:33:18.566200 A73 clk: 1200 MHz
466 09:33:18.566412 CLK81: 166.6M
467 09:33:18.566616 smccc: 00012abd
468 09:33:18.571378 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 09:33:18.577001 board id: 1
470 09:33:18.582838 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 09:33:18.593585 fw parse done
472 09:33:18.599506 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 09:33:18.642140 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 09:33:18.653019 PIEI prepare done
475 09:33:18.653303 fastboot data load
476 09:33:18.653519 fastboot data verify
477 09:33:18.658700 verify result: 266
478 09:33:18.664285 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 09:33:18.664553 LPDDR4 probe
480 09:33:18.664766 ddr clk to 1584MHz
481 09:33:18.672187 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 09:33:18.709534
483 09:33:18.709856 dmc_version 0001
484 09:33:18.716270 Check phy result
485 09:33:18.722079 INFO : End of CA training
486 09:33:18.722338 INFO : End of initialization
487 09:33:18.727716 INFO : Training has run successfully!
488 09:33:18.728031 Check phy result
489 09:33:18.733314 INFO : End of initialization
490 09:33:18.733575 INFO : End of read enable training
491 09:33:18.738883 INFO : End of fine write leveling
492 09:33:18.744453 INFO : End of Write leveling coarse delay
493 09:33:18.744708 INFO : Training has run successfully!
494 09:33:18.744911 Check phy result
495 09:33:18.750068 INFO : End of initialization
496 09:33:18.750327 INFO : End of read dq deskew training
497 09:33:18.755636 INFO : End of MPR read delay center optimization
498 09:33:18.761272 INFO : End of write delay center optimization
499 09:33:18.766831 INFO : End of read delay center optimization
500 09:33:18.767086 INFO : End of max read latency training
501 09:33:18.772441 INFO : Training has run successfully!
502 09:33:18.772697 1D training succeed
503 09:33:18.781692 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 09:33:18.828598 Check phy result
505 09:33:18.828920 INFO : End of initialization
506 09:33:18.850460 INFO : End of 2D read delay Voltage center optimization
507 09:33:18.871204 INFO : End of 2D read delay Voltage center optimization
508 09:33:18.923306 INFO : End of 2D write delay Voltage center optimization
509 09:33:18.972613 INFO : End of 2D write delay Voltage center optimization
510 09:33:18.978160 INFO : Training has run successfully!
511 09:33:18.978428
512 09:33:18.978643 channel==0
513 09:33:18.983824 RxClkDly_Margin_A0==88 ps 9
514 09:33:18.984112 TxDqDly_Margin_A0==98 ps 10
515 09:33:18.989362 RxClkDly_Margin_A1==88 ps 9
516 09:33:18.989619 TxDqDly_Margin_A1==88 ps 9
517 09:33:18.989830 TrainedVREFDQ_A0==74
518 09:33:18.995044 TrainedVREFDQ_A1==74
519 09:33:18.995298 VrefDac_Margin_A0==25
520 09:33:18.995509 DeviceVref_Margin_A0==40
521 09:33:19.000569 VrefDac_Margin_A1==25
522 09:33:19.000843 DeviceVref_Margin_A1==40
523 09:33:19.001052
524 09:33:19.001257
525 09:33:19.001465 channel==1
526 09:33:19.006176 RxClkDly_Margin_A0==98 ps 10
527 09:33:19.006438 TxDqDly_Margin_A0==88 ps 9
528 09:33:19.011759 RxClkDly_Margin_A1==98 ps 10
529 09:33:19.012062 TxDqDly_Margin_A1==88 ps 9
530 09:33:19.017352 TrainedVREFDQ_A0==77
531 09:33:19.017607 TrainedVREFDQ_A1==77
532 09:33:19.017821 VrefDac_Margin_A0==22
533 09:33:19.023285 DeviceVref_Margin_A0==37
534 09:33:19.023853 VrefDac_Margin_A1==22
535 09:33:19.028663 DeviceVref_Margin_A1==37
536 09:33:19.029220
537 09:33:19.029701 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 09:33:19.030170
539 09:33:19.062264 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
540 09:33:19.062855 2D training succeed
541 09:33:19.067806 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 09:33:19.073426 auto size-- 65535DDR cs0 size: 2048MB
543 09:33:19.073968 DDR cs1 size: 2048MB
544 09:33:19.079116 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 09:33:19.079666 cs0 DataBus test pass
546 09:33:19.084652 cs1 DataBus test pass
547 09:33:19.085196 cs0 AddrBus test pass
548 09:33:19.085642 cs1 AddrBus test pass
549 09:33:19.086078
550 09:33:19.090238 100bdlr_step_size ps== 420
551 09:33:19.090795 result report
552 09:33:19.095808 boot times 0Enable ddr reg access
553 09:33:19.101183 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 09:33:19.114182 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 09:33:19.688557 0.0;M3 CHK:0;cm4_sp_mode 0
556 09:33:19.689230 MVN_1=0x00000000
557 09:33:19.694152 MVN_2=0x00000000
558 09:33:19.699671 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 09:33:19.700291 OPS=0x10
560 09:33:19.700751 ring efuse init
561 09:33:19.701184 chipver efuse init
562 09:33:19.705355 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 09:33:19.710821 [0.018961 Inits done]
564 09:33:19.711295 secure task start!
565 09:33:19.711729 high task start!
566 09:33:19.715390 low task start!
567 09:33:19.715848 run into bl31
568 09:33:19.722039 NOTICE: BL31: v1.3(release):4fc40b1
569 09:33:19.729995 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 09:33:19.730556 NOTICE: BL31: G12A normal boot!
571 09:33:19.755233 NOTICE: BL31: BL33 decompress pass
572 09:33:19.760904 ERROR: Error initializing runtime service opteed_fast
573 09:33:20.993908
574 09:33:20.994567
575 09:33:21.002411 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 09:33:21.002945
577 09:33:21.003411 Model: Libre Computer AML-A311D-CC Alta
578 09:33:21.210733 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 09:33:21.234108 DRAM: 2 GiB (effective 3.8 GiB)
580 09:33:21.377146 Core: 408 devices, 31 uclasses, devicetree: separate
581 09:33:21.383010 WDT: Not starting watchdog@f0d0
582 09:33:21.415271 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 09:33:21.427702 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 09:33:21.432682 ** Bad device specification mmc 0 **
585 09:33:21.442985 Card did not respond to voltage select! : -110
586 09:33:21.450678 ** Bad device specification mmc 0 **
587 09:33:21.451197 Couldn't find partition mmc 0
588 09:33:21.458906 Card did not respond to voltage select! : -110
589 09:33:21.464560 ** Bad device specification mmc 0 **
590 09:33:21.465084 Couldn't find partition mmc 0
591 09:33:21.469674 Error: could not access storage.
592 09:33:21.812058 Net: eth0: ethernet@ff3f0000
593 09:33:21.812688 starting USB...
594 09:33:22.063754 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 09:33:22.064398 Starting the controller
596 09:33:22.070876 USB XHCI 1.10
597 09:33:23.781077 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 09:33:23.781714 bl2_stage_init 0x01
599 09:33:23.782178 bl2_stage_init 0x81
600 09:33:23.786802 hw id: 0x0000 - pwm id 0x01
601 09:33:23.787310 bl2_stage_init 0xc1
602 09:33:23.787762 bl2_stage_init 0x02
603 09:33:23.788264
604 09:33:23.792323 L0:00000000
605 09:33:23.792826 L1:20000703
606 09:33:23.793276 L2:00008067
607 09:33:23.793716 L3:14000000
608 09:33:23.797846 B2:00402000
609 09:33:23.798344 B1:e0f83180
610 09:33:23.798794
611 09:33:23.799239 TE: 58167
612 09:33:23.799683
613 09:33:23.803477 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 09:33:23.804011
615 09:33:23.804474 Board ID = 1
616 09:33:23.808990 Set A53 clk to 24M
617 09:33:23.809496 Set A73 clk to 24M
618 09:33:23.809941 Set clk81 to 24M
619 09:33:23.814675 A53 clk: 1200 MHz
620 09:33:23.815178 A73 clk: 1200 MHz
621 09:33:23.815626 CLK81: 166.6M
622 09:33:23.816099 smccc: 00012abd
623 09:33:23.820258 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 09:33:23.825868 board id: 1
625 09:33:23.831756 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 09:33:23.842435 fw parse done
627 09:33:23.848340 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 09:33:23.891051 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 09:33:23.901810 PIEI prepare done
630 09:33:23.902313 fastboot data load
631 09:33:23.902767 fastboot data verify
632 09:33:23.907572 verify result: 266
633 09:33:23.913175 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 09:33:23.913679 LPDDR4 probe
635 09:33:23.914125 ddr clk to 1584MHz
636 09:33:23.921151 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 09:33:23.957440
638 09:33:23.957949 dmc_version 0001
639 09:33:23.965042 Check phy result
640 09:33:23.970939 INFO : End of CA training
641 09:33:23.971436 INFO : End of initialization
642 09:33:23.976548 INFO : Training has run successfully!
643 09:33:23.977049 Check phy result
644 09:33:23.982100 INFO : End of initialization
645 09:33:23.982597 INFO : End of read enable training
646 09:33:23.987712 INFO : End of fine write leveling
647 09:33:23.993339 INFO : End of Write leveling coarse delay
648 09:33:23.993840 INFO : Training has run successfully!
649 09:33:23.994289 Check phy result
650 09:33:23.998935 INFO : End of initialization
651 09:33:23.999435 INFO : End of read dq deskew training
652 09:33:24.004538 INFO : End of MPR read delay center optimization
653 09:33:24.010099 INFO : End of write delay center optimization
654 09:33:24.015673 INFO : End of read delay center optimization
655 09:33:24.016217 INFO : End of max read latency training
656 09:33:24.021334 INFO : Training has run successfully!
657 09:33:24.021833 1D training succeed
658 09:33:24.030476 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 09:33:24.078107 Check phy result
660 09:33:24.078630 INFO : End of initialization
661 09:33:24.099884 INFO : End of 2D read delay Voltage center optimization
662 09:33:24.120113 INFO : End of 2D read delay Voltage center optimization
663 09:33:24.171351 INFO : End of 2D write delay Voltage center optimization
664 09:33:24.221457 INFO : End of 2D write delay Voltage center optimization
665 09:33:24.227080 INFO : Training has run successfully!
666 09:33:24.227582
667 09:33:24.228085 channel==0
668 09:33:24.232671 RxClkDly_Margin_A0==88 ps 9
669 09:33:24.233175 TxDqDly_Margin_A0==98 ps 10
670 09:33:24.238314 RxClkDly_Margin_A1==88 ps 9
671 09:33:24.238815 TxDqDly_Margin_A1==98 ps 10
672 09:33:24.239273 TrainedVREFDQ_A0==74
673 09:33:24.243771 TrainedVREFDQ_A1==74
674 09:33:24.244314 VrefDac_Margin_A0==25
675 09:33:24.244772 DeviceVref_Margin_A0==40
676 09:33:24.249752 VrefDac_Margin_A1==25
677 09:33:24.250252 DeviceVref_Margin_A1==40
678 09:33:24.250700
679 09:33:24.251142
680 09:33:24.255801 channel==1
681 09:33:24.256333 RxClkDly_Margin_A0==98 ps 10
682 09:33:24.256780 TxDqDly_Margin_A0==88 ps 9
683 09:33:24.260702 RxClkDly_Margin_A1==88 ps 9
684 09:33:24.261202 TxDqDly_Margin_A1==98 ps 10
685 09:33:24.266228 TrainedVREFDQ_A0==77
686 09:33:24.266736 TrainedVREFDQ_A1==78
687 09:33:24.267183 VrefDac_Margin_A0==22
688 09:33:24.271813 DeviceVref_Margin_A0==37
689 09:33:24.272373 VrefDac_Margin_A1==24
690 09:33:24.277498 DeviceVref_Margin_A1==36
691 09:33:24.278007
692 09:33:24.278457 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 09:33:24.278896
694 09:33:24.310857 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000017 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
695 09:33:24.311418 2D training succeed
696 09:33:24.316542 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 09:33:24.322168 auto size-- 65535DDR cs0 size: 2048MB
698 09:33:24.322675 DDR cs1 size: 2048MB
699 09:33:24.327725 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 09:33:24.328274 cs0 DataBus test pass
701 09:33:24.333318 cs1 DataBus test pass
702 09:33:24.333817 cs0 AddrBus test pass
703 09:33:24.334266 cs1 AddrBus test pass
704 09:33:24.334703
705 09:33:24.338933 100bdlr_step_size ps== 420
706 09:33:24.339448 result report
707 09:33:24.344552 boot times 0Enable ddr reg access
708 09:33:24.349042 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 09:33:24.363315 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 09:33:24.937018 0.0;M3 CHK:0;cm4_sp_mode 0
711 09:33:24.937627 MVN_1=0x00000000
712 09:33:24.942558 MVN_2=0x00000000
713 09:33:24.948364 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 09:33:24.948884 OPS=0x10
715 09:33:24.949290 ring efuse init
716 09:33:24.949683 chipver efuse init
717 09:33:24.953879 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 09:33:24.959364 [0.018960 Inits done]
719 09:33:24.959790 secure task start!
720 09:33:24.960228 high task start!
721 09:33:24.963959 low task start!
722 09:33:24.964413 run into bl31
723 09:33:24.970653 NOTICE: BL31: v1.3(release):4fc40b1
724 09:33:24.978457 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 09:33:24.978890 NOTICE: BL31: G12A normal boot!
726 09:33:25.003896 NOTICE: BL31: BL33 decompress pass
727 09:33:25.009108 ERROR: Error initializing runtime service opteed_fast
728 09:33:26.242353
729 09:33:26.242987
730 09:33:26.250844 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 09:33:26.251380
732 09:33:26.251848 Model: Libre Computer AML-A311D-CC Alta
733 09:33:26.459343 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 09:33:26.482662 DRAM: 2 GiB (effective 3.8 GiB)
735 09:33:26.625634 Core: 408 devices, 31 uclasses, devicetree: separate
736 09:33:26.631513 WDT: Not starting watchdog@f0d0
737 09:33:26.663827 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 09:33:26.676229 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 09:33:26.681246 ** Bad device specification mmc 0 **
740 09:33:26.691512 Card did not respond to voltage select! : -110
741 09:33:26.698321 ** Bad device specification mmc 0 **
742 09:33:26.698877 Couldn't find partition mmc 0
743 09:33:26.707531 Card did not respond to voltage select! : -110
744 09:33:26.713023 ** Bad device specification mmc 0 **
745 09:33:26.713582 Couldn't find partition mmc 0
746 09:33:26.718084 Error: could not access storage.
747 09:33:27.060955 Net: eth0: ethernet@ff3f0000
748 09:33:27.061563 starting USB...
749 09:33:27.313640 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 09:33:27.314247 Starting the controller
751 09:33:27.320482 USB XHCI 1.10
752 09:33:29.481383 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 09:33:29.482081 bl2_stage_init 0x01
754 09:33:29.482558 bl2_stage_init 0x81
755 09:33:29.486874 hw id: 0x0000 - pwm id 0x01
756 09:33:29.487399 bl2_stage_init 0xc1
757 09:33:29.487855 bl2_stage_init 0x02
758 09:33:29.488359
759 09:33:29.492480 L0:00000000
760 09:33:29.493003 L1:20000703
761 09:33:29.493457 L2:00008067
762 09:33:29.493901 L3:14000000
763 09:33:29.495366 B2:00402000
764 09:33:29.495868 B1:e0f83180
765 09:33:29.496366
766 09:33:29.496820 TE: 58124
767 09:33:29.497296
768 09:33:29.506439 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 09:33:29.507027
770 09:33:29.507495 Board ID = 1
771 09:33:29.507943 Set A53 clk to 24M
772 09:33:29.508440 Set A73 clk to 24M
773 09:33:29.512140 Set clk81 to 24M
774 09:33:29.512708 A53 clk: 1200 MHz
775 09:33:29.513166 A73 clk: 1200 MHz
776 09:33:29.517717 CLK81: 166.6M
777 09:33:29.518286 smccc: 00012a92
778 09:33:29.523341 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 09:33:29.523903 board id: 1
780 09:33:29.531222 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 09:33:29.542648 fw parse done
782 09:33:29.548573 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 09:33:29.590563 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 09:33:29.602031 PIEI prepare done
785 09:33:29.602632 fastboot data load
786 09:33:29.603090 fastboot data verify
787 09:33:29.607758 verify result: 266
788 09:33:29.613363 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 09:33:29.613911 LPDDR4 probe
790 09:33:29.614360 ddr clk to 1584MHz
791 09:33:29.621226 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 09:33:29.658613
793 09:33:29.659200 dmc_version 0001
794 09:33:29.665301 Check phy result
795 09:33:29.671154 INFO : End of CA training
796 09:33:29.671693 INFO : End of initialization
797 09:33:29.676796 INFO : Training has run successfully!
798 09:33:29.677320 Check phy result
799 09:33:29.682382 INFO : End of initialization
800 09:33:29.682894 INFO : End of read enable training
801 09:33:29.687899 INFO : End of fine write leveling
802 09:33:29.693559 INFO : End of Write leveling coarse delay
803 09:33:29.694091 INFO : Training has run successfully!
804 09:33:29.694545 Check phy result
805 09:33:29.699175 INFO : End of initialization
806 09:33:29.699697 INFO : End of read dq deskew training
807 09:33:29.704800 INFO : End of MPR read delay center optimization
808 09:33:29.710400 INFO : End of write delay center optimization
809 09:33:29.716160 INFO : End of read delay center optimization
810 09:33:29.716811 INFO : End of max read latency training
811 09:33:29.721619 INFO : Training has run successfully!
812 09:33:29.722186 1D training succeed
813 09:33:29.730815 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 09:33:29.778297 Check phy result
815 09:33:29.778947 INFO : End of initialization
816 09:33:29.800071 INFO : End of 2D read delay Voltage center optimization
817 09:33:29.820312 INFO : End of 2D read delay Voltage center optimization
818 09:33:29.872469 INFO : End of 2D write delay Voltage center optimization
819 09:33:29.921729 INFO : End of 2D write delay Voltage center optimization
820 09:33:29.927361 INFO : Training has run successfully!
821 09:33:29.927915
822 09:33:29.928449 channel==0
823 09:33:29.932981 RxClkDly_Margin_A0==88 ps 9
824 09:33:29.934997 TxDqDly_Margin_A0==98 ps 10
825 09:33:29.938556 RxClkDly_Margin_A1==88 ps 9
826 09:33:29.938979 TxDqDly_Margin_A1==98 ps 10
827 09:33:29.939302 TrainedVREFDQ_A0==74
828 09:33:29.944310 TrainedVREFDQ_A1==74
829 09:33:29.944756 VrefDac_Margin_A0==25
830 09:33:29.945082 DeviceVref_Margin_A0==40
831 09:33:29.949564 VrefDac_Margin_A1==25
832 09:33:29.949966 DeviceVref_Margin_A1==40
833 09:33:29.950283
834 09:33:29.950598
835 09:33:29.955107 channel==1
836 09:33:29.955501 RxClkDly_Margin_A0==98 ps 10
837 09:33:29.955823 TxDqDly_Margin_A0==88 ps 9
838 09:33:29.960652 RxClkDly_Margin_A1==98 ps 10
839 09:33:29.961032 TxDqDly_Margin_A1==98 ps 10
840 09:33:29.966250 TrainedVREFDQ_A0==77
841 09:33:29.966631 TrainedVREFDQ_A1==77
842 09:33:29.966942 VrefDac_Margin_A0==22
843 09:33:29.971850 DeviceVref_Margin_A0==37
844 09:33:29.972242 VrefDac_Margin_A1==22
845 09:33:29.977417 DeviceVref_Margin_A1==37
846 09:33:29.977796
847 09:33:29.978123 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 09:33:29.983059
849 09:33:30.011062 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
850 09:33:30.011499 2D training succeed
851 09:33:30.016648 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 09:33:30.022300 auto size-- 65535DDR cs0 size: 2048MB
853 09:33:30.022695 DDR cs1 size: 2048MB
854 09:33:30.027862 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 09:33:30.028278 cs0 DataBus test pass
856 09:33:30.033494 cs1 DataBus test pass
857 09:33:30.033878 cs0 AddrBus test pass
858 09:33:30.034205 cs1 AddrBus test pass
859 09:33:30.034523
860 09:33:30.039052 100bdlr_step_size ps== 420
861 09:33:30.039445 result report
862 09:33:30.044712 boot times 0Enable ddr reg access
863 09:33:30.050230 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 09:33:30.063565 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 09:33:30.636737 0.0;M3 CHK:0;cm4_sp_mode 0
866 09:33:30.637305 MVN_1=0x00000000
867 09:33:30.642139 MVN_2=0x00000000
868 09:33:30.647905 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 09:33:30.648418 OPS=0x10
870 09:33:30.648737 ring efuse init
871 09:33:30.649034 chipver efuse init
872 09:33:30.656336 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 09:33:30.656826 [0.018961 Inits done]
874 09:33:30.657133 secure task start!
875 09:33:30.663825 high task start!
876 09:33:30.664507 low task start!
877 09:33:30.664856 run into bl31
878 09:33:30.670393 NOTICE: BL31: v1.3(release):4fc40b1
879 09:33:30.677343 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 09:33:30.677831 NOTICE: BL31: G12A normal boot!
881 09:33:30.703818 NOTICE: BL31: BL33 decompress pass
882 09:33:30.709287 ERROR: Error initializing runtime service opteed_fast
883 09:33:31.942076
884 09:33:31.942868
885 09:33:31.950654 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 09:33:31.951244
887 09:33:31.951785 Model: Libre Computer AML-A311D-CC Alta
888 09:33:32.158818 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 09:33:32.182190 DRAM: 2 GiB (effective 3.8 GiB)
890 09:33:32.325319 Core: 408 devices, 31 uclasses, devicetree: separate
891 09:33:32.331153 WDT: Not starting watchdog@f0d0
892 09:33:32.363506 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 09:33:32.375905 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 09:33:32.380957 ** Bad device specification mmc 0 **
895 09:33:32.391212 Card did not respond to voltage select! : -110
896 09:33:32.398971 ** Bad device specification mmc 0 **
897 09:33:32.399575 Couldn't find partition mmc 0
898 09:33:32.407184 Card did not respond to voltage select! : -110
899 09:33:32.412695 ** Bad device specification mmc 0 **
900 09:33:32.413276 Couldn't find partition mmc 0
901 09:33:32.417751 Error: could not access storage.
902 09:33:32.760320 Net: eth0: ethernet@ff3f0000
903 09:33:32.761108 starting USB...
904 09:33:33.012170 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 09:33:33.012956 Starting the controller
906 09:33:33.019036 USB XHCI 1.10
907 09:33:34.573196 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
908 09:33:34.581453 scanning usb for storage devices... 0 Storage Device(s) found
910 09:33:34.633411 Hit any key to stop autoboot: 1
911 09:33:34.634475 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
912 09:33:34.635245 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
913 09:33:34.635861 Setting prompt string to ['=>']
914 09:33:34.636538 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
915 09:33:34.648831 0
916 09:33:34.649930 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
917 09:33:34.650573 Sending with 10 millisecond of delay
919 09:33:35.786044 => setenv autoload no
920 09:33:35.796852 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
921 09:33:35.801797 setenv autoload no
922 09:33:35.802535 Sending with 10 millisecond of delay
924 09:33:37.599380 => setenv initrd_high 0xffffffff
925 09:33:37.610213 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
926 09:33:37.611047 setenv initrd_high 0xffffffff
927 09:33:37.611751 Sending with 10 millisecond of delay
929 09:33:39.228479 => setenv fdt_high 0xffffffff
930 09:33:39.239268 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
931 09:33:39.240101 setenv fdt_high 0xffffffff
932 09:33:39.240817 Sending with 10 millisecond of delay
934 09:33:39.532597 => dhcp
935 09:33:39.543364 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
936 09:33:39.544200 dhcp
937 09:33:39.544633 Speed: 1000, full duplex
938 09:33:39.545043 BOOTP broadcast 1
939 09:33:39.551457 DHCP client bound to address 192.168.6.27 (8 ms)
940 09:33:39.552141 Sending with 10 millisecond of delay
942 09:33:41.228452 => setenv serverip 192.168.6.2
943 09:33:41.239196 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
944 09:33:41.240079 setenv serverip 192.168.6.2
945 09:33:41.240768 Sending with 10 millisecond of delay
947 09:33:44.973441 => tftpboot 0x01080000 939397/tftp-deploy-kzpkb545/kernel/uImage
948 09:33:44.984252 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
949 09:33:44.985069 tftpboot 0x01080000 939397/tftp-deploy-kzpkb545/kernel/uImage
950 09:33:44.985513 Speed: 1000, full duplex
951 09:33:44.985924 Using ethernet@ff3f0000 device
952 09:33:44.987074 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
953 09:33:44.992441 Filename '939397/tftp-deploy-kzpkb545/kernel/uImage'.
954 09:33:44.996402 Load address: 0x1080000
955 09:33:47.876045 Loading: *################################################## 43.6 MiB
956 09:33:47.876699 15.1 MiB/s
957 09:33:47.877147 done
958 09:33:47.880512 Bytes transferred = 45713984 (2b98a40 hex)
959 09:33:47.881376 Sending with 10 millisecond of delay
961 09:33:52.568745 => tftpboot 0x08000000 939397/tftp-deploy-kzpkb545/ramdisk/ramdisk.cpio.gz.uboot
962 09:33:52.579546 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
963 09:33:52.580489 tftpboot 0x08000000 939397/tftp-deploy-kzpkb545/ramdisk/ramdisk.cpio.gz.uboot
964 09:33:52.580978 Speed: 1000, full duplex
965 09:33:52.581433 Using ethernet@ff3f0000 device
966 09:33:52.582227 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
967 09:33:52.590761 Filename '939397/tftp-deploy-kzpkb545/ramdisk/ramdisk.cpio.gz.uboot'.
968 09:33:52.591282 Load address: 0x8000000
969 09:33:54.243748 Loading: *################################################# UDP wrong checksum 00000005 0000c7e5
970 09:33:59.245101 T UDP wrong checksum 00000005 0000c7e5
971 09:34:09.248101 T T UDP wrong checksum 00000005 0000c7e5
972 09:34:18.585058 T UDP wrong checksum 000000ff 0000b2bd
973 09:34:18.606941 UDP wrong checksum 000000ff 000049b0
974 09:34:29.252542 T T T UDP wrong checksum 00000005 0000c7e5
975 09:34:49.257377 T T T
976 09:34:49.258017 Retry count exceeded; starting again
978 09:34:49.259964 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
981 09:34:49.261881 end: 2.4 uboot-commands (duration 00:01:46) [common]
983 09:34:49.263239 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
985 09:34:49.264335 end: 2 uboot-action (duration 00:01:47) [common]
987 09:34:49.265930 Cleaning after the job
988 09:34:49.266525 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939397/tftp-deploy-kzpkb545/ramdisk
989 09:34:49.267829 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939397/tftp-deploy-kzpkb545/kernel
990 09:34:49.314014 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939397/tftp-deploy-kzpkb545/dtb
991 09:34:49.314836 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939397/tftp-deploy-kzpkb545/modules
992 09:34:49.335544 start: 4.1 power-off (timeout 00:00:30) [common]
993 09:34:49.336254 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
994 09:34:49.369900 >> OK - accepted request
995 09:34:49.372173 Returned 0 in 0 seconds
996 09:34:49.472947 end: 4.1 power-off (duration 00:00:00) [common]
998 09:34:49.473902 start: 4.2 read-feedback (timeout 00:10:00) [common]
999 09:34:49.474539 Listened to connection for namespace 'common' for up to 1s
1000 09:34:50.475531 Finalising connection for namespace 'common'
1001 09:34:50.476383 Disconnecting from shell: Finalise
1002 09:34:50.476902 =>
1003 09:34:50.577858 end: 4.2 read-feedback (duration 00:00:01) [common]
1004 09:34:50.578542 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/939397
1005 09:34:50.869920 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/939397
1006 09:34:50.870534 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.