Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 09:38:24.840829 lava-dispatcher, installed at version: 2024.01
2 09:38:24.841605 start: 0 validate
3 09:38:24.842076 Start time: 2024-11-05 09:38:24.842045+00:00 (UTC)
4 09:38:24.842613 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 09:38:24.843144 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 09:38:24.884722 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 09:38:24.885363 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-401-g1596ed05f2f47%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 09:38:24.916445 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 09:38:24.917180 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-401-g1596ed05f2f47%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 09:38:24.945138 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 09:38:24.945613 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:38:24.975910 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 09:38:24.976430 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-401-g1596ed05f2f47%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 09:38:25.016492 validate duration: 0.17
16 09:38:25.017371 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:38:25.017721 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:38:25.018054 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:38:25.018658 Not decompressing ramdisk as can be used compressed.
20 09:38:25.019116 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 09:38:25.019410 saving as /var/lib/lava/dispatcher/tmp/939329/tftp-deploy-vy7p4unu/ramdisk/initrd.cpio.gz
22 09:38:25.019686 total size: 5628140 (5 MB)
23 09:38:25.062797 progress 0 % (0 MB)
24 09:38:25.066920 progress 5 % (0 MB)
25 09:38:25.071184 progress 10 % (0 MB)
26 09:38:25.074869 progress 15 % (0 MB)
27 09:38:25.079056 progress 20 % (1 MB)
28 09:38:25.082872 progress 25 % (1 MB)
29 09:38:25.086861 progress 30 % (1 MB)
30 09:38:25.090894 progress 35 % (1 MB)
31 09:38:25.094593 progress 40 % (2 MB)
32 09:38:25.098643 progress 45 % (2 MB)
33 09:38:25.102282 progress 50 % (2 MB)
34 09:38:25.106319 progress 55 % (2 MB)
35 09:38:25.110346 progress 60 % (3 MB)
36 09:38:25.113942 progress 65 % (3 MB)
37 09:38:25.117917 progress 70 % (3 MB)
38 09:38:25.121527 progress 75 % (4 MB)
39 09:38:25.125637 progress 80 % (4 MB)
40 09:38:25.129261 progress 85 % (4 MB)
41 09:38:25.133193 progress 90 % (4 MB)
42 09:38:25.137019 progress 95 % (5 MB)
43 09:38:25.140313 progress 100 % (5 MB)
44 09:38:25.140988 5 MB downloaded in 0.12 s (44.26 MB/s)
45 09:38:25.141567 end: 1.1.1 http-download (duration 00:00:00) [common]
47 09:38:25.142493 end: 1.1 download-retry (duration 00:00:00) [common]
48 09:38:25.142812 start: 1.2 download-retry (timeout 00:10:00) [common]
49 09:38:25.143101 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 09:38:25.143592 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-401-g1596ed05f2f47/arm64/defconfig/gcc-12/kernel/Image
51 09:38:25.143854 saving as /var/lib/lava/dispatcher/tmp/939329/tftp-deploy-vy7p4unu/kernel/Image
52 09:38:25.144103 total size: 45713920 (43 MB)
53 09:38:25.144334 No compression specified
54 09:38:25.187552 progress 0 % (0 MB)
55 09:38:25.221016 progress 5 % (2 MB)
56 09:38:25.254759 progress 10 % (4 MB)
57 09:38:25.288425 progress 15 % (6 MB)
58 09:38:25.322279 progress 20 % (8 MB)
59 09:38:25.355567 progress 25 % (10 MB)
60 09:38:25.388956 progress 30 % (13 MB)
61 09:38:25.422765 progress 35 % (15 MB)
62 09:38:25.457136 progress 40 % (17 MB)
63 09:38:25.490571 progress 45 % (19 MB)
64 09:38:25.524334 progress 50 % (21 MB)
65 09:38:25.558316 progress 55 % (24 MB)
66 09:38:25.592127 progress 60 % (26 MB)
67 09:38:25.625195 progress 65 % (28 MB)
68 09:38:25.659089 progress 70 % (30 MB)
69 09:38:25.692667 progress 75 % (32 MB)
70 09:38:25.726559 progress 80 % (34 MB)
71 09:38:25.759750 progress 85 % (37 MB)
72 09:38:25.793724 progress 90 % (39 MB)
73 09:38:25.827126 progress 95 % (41 MB)
74 09:38:25.860095 progress 100 % (43 MB)
75 09:38:25.860750 43 MB downloaded in 0.72 s (60.84 MB/s)
76 09:38:25.861345 end: 1.2.1 http-download (duration 00:00:01) [common]
78 09:38:25.862354 end: 1.2 download-retry (duration 00:00:01) [common]
79 09:38:25.862694 start: 1.3 download-retry (timeout 00:09:59) [common]
80 09:38:25.863024 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 09:38:25.863596 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-401-g1596ed05f2f47/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 09:38:25.863924 saving as /var/lib/lava/dispatcher/tmp/939329/tftp-deploy-vy7p4unu/dtb/meson-g12b-a311d-libretech-cc.dtb
83 09:38:25.864212 total size: 54703 (0 MB)
84 09:38:25.864470 No compression specified
85 09:38:25.906988 progress 59 % (0 MB)
86 09:38:25.907833 progress 100 % (0 MB)
87 09:38:25.908459 0 MB downloaded in 0.04 s (1.18 MB/s)
88 09:38:25.908954 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:38:25.909811 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:38:25.910095 start: 1.4 download-retry (timeout 00:09:59) [common]
92 09:38:25.910376 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 09:38:25.910854 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 09:38:25.911114 saving as /var/lib/lava/dispatcher/tmp/939329/tftp-deploy-vy7p4unu/nfsrootfs/full.rootfs.tar
95 09:38:25.911332 total size: 474398908 (452 MB)
96 09:38:25.911553 Using unxz to decompress xz
97 09:38:25.948475 progress 0 % (0 MB)
98 09:38:27.063095 progress 5 % (22 MB)
99 09:38:28.522930 progress 10 % (45 MB)
100 09:38:28.955778 progress 15 % (67 MB)
101 09:38:29.726449 progress 20 % (90 MB)
102 09:38:30.238391 progress 25 % (113 MB)
103 09:38:30.606309 progress 30 % (135 MB)
104 09:38:31.246060 progress 35 % (158 MB)
105 09:38:32.179067 progress 40 % (181 MB)
106 09:38:33.020529 progress 45 % (203 MB)
107 09:38:33.699070 progress 50 % (226 MB)
108 09:38:34.343452 progress 55 % (248 MB)
109 09:38:35.564647 progress 60 % (271 MB)
110 09:38:36.979770 progress 65 % (294 MB)
111 09:38:38.571966 progress 70 % (316 MB)
112 09:38:41.900156 progress 75 % (339 MB)
113 09:38:44.477192 progress 80 % (361 MB)
114 09:38:47.375359 progress 85 % (384 MB)
115 09:38:50.743616 progress 90 % (407 MB)
116 09:38:54.191534 progress 95 % (429 MB)
117 09:38:57.398120 progress 100 % (452 MB)
118 09:38:57.411160 452 MB downloaded in 31.50 s (14.36 MB/s)
119 09:38:57.412140 end: 1.4.1 http-download (duration 00:00:32) [common]
121 09:38:57.413907 end: 1.4 download-retry (duration 00:00:32) [common]
122 09:38:57.414472 start: 1.5 download-retry (timeout 00:09:28) [common]
123 09:38:57.415035 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 09:38:57.416098 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-401-g1596ed05f2f47/arm64/defconfig/gcc-12/modules.tar.xz
125 09:38:57.416625 saving as /var/lib/lava/dispatcher/tmp/939329/tftp-deploy-vy7p4unu/modules/modules.tar
126 09:38:57.417078 total size: 11611116 (11 MB)
127 09:38:57.417540 Using unxz to decompress xz
128 09:38:57.463257 progress 0 % (0 MB)
129 09:38:57.529295 progress 5 % (0 MB)
130 09:38:57.603130 progress 10 % (1 MB)
131 09:38:57.698134 progress 15 % (1 MB)
132 09:38:57.791857 progress 20 % (2 MB)
133 09:38:57.869988 progress 25 % (2 MB)
134 09:38:57.944704 progress 30 % (3 MB)
135 09:38:58.021493 progress 35 % (3 MB)
136 09:38:58.092862 progress 40 % (4 MB)
137 09:38:58.167711 progress 45 % (5 MB)
138 09:38:58.250633 progress 50 % (5 MB)
139 09:38:58.326303 progress 55 % (6 MB)
140 09:38:58.409793 progress 60 % (6 MB)
141 09:38:58.488858 progress 65 % (7 MB)
142 09:38:58.568403 progress 70 % (7 MB)
143 09:38:58.647539 progress 75 % (8 MB)
144 09:38:58.731877 progress 80 % (8 MB)
145 09:38:58.810600 progress 85 % (9 MB)
146 09:38:58.888328 progress 90 % (9 MB)
147 09:38:58.965276 progress 95 % (10 MB)
148 09:38:59.042228 progress 100 % (11 MB)
149 09:38:59.053529 11 MB downloaded in 1.64 s (6.77 MB/s)
150 09:38:59.054470 end: 1.5.1 http-download (duration 00:00:02) [common]
152 09:38:59.056133 end: 1.5 download-retry (duration 00:00:02) [common]
153 09:38:59.056672 start: 1.6 prepare-tftp-overlay (timeout 00:09:26) [common]
154 09:38:59.057193 start: 1.6.1 extract-nfsrootfs (timeout 00:09:26) [common]
155 09:39:14.766852 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/939329/extract-nfsrootfs-ptpw6spu
156 09:39:14.767456 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 09:39:14.767779 start: 1.6.2 lava-overlay (timeout 00:09:10) [common]
158 09:39:14.768421 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r
159 09:39:14.768884 makedir: /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin
160 09:39:14.769261 makedir: /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/tests
161 09:39:14.769631 makedir: /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/results
162 09:39:14.770005 Creating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin/lava-add-keys
163 09:39:14.770539 Creating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin/lava-add-sources
164 09:39:14.771026 Creating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin/lava-background-process-start
165 09:39:14.771499 Creating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin/lava-background-process-stop
166 09:39:14.771976 Creating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin/lava-common-functions
167 09:39:14.772526 Creating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin/lava-echo-ipv4
168 09:39:14.773011 Creating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin/lava-install-packages
169 09:39:14.773491 Creating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin/lava-installed-packages
170 09:39:14.773950 Creating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin/lava-os-build
171 09:39:14.774407 Creating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin/lava-probe-channel
172 09:39:14.774858 Creating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin/lava-probe-ip
173 09:39:14.775309 Creating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin/lava-target-ip
174 09:39:14.775757 Creating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin/lava-target-mac
175 09:39:14.776264 Creating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin/lava-target-storage
176 09:39:14.776753 Creating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin/lava-test-case
177 09:39:14.777212 Creating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin/lava-test-event
178 09:39:14.777681 Creating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin/lava-test-feedback
179 09:39:14.778141 Creating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin/lava-test-raise
180 09:39:14.778620 Creating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin/lava-test-reference
181 09:39:14.779081 Creating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin/lava-test-runner
182 09:39:14.779567 Creating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin/lava-test-set
183 09:39:14.780065 Creating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin/lava-test-shell
184 09:39:14.780559 Updating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin/lava-install-packages (oe)
185 09:39:14.781080 Updating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/bin/lava-installed-packages (oe)
186 09:39:14.781501 Creating /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/environment
187 09:39:14.781852 LAVA metadata
188 09:39:14.782095 - LAVA_JOB_ID=939329
189 09:39:14.782308 - LAVA_DISPATCHER_IP=192.168.6.2
190 09:39:14.782655 start: 1.6.2.1 ssh-authorize (timeout 00:09:10) [common]
191 09:39:14.783627 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 09:39:14.783933 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:10) [common]
193 09:39:14.784166 skipped lava-vland-overlay
194 09:39:14.784411 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 09:39:14.784664 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:10) [common]
196 09:39:14.784868 skipped lava-multinode-overlay
197 09:39:14.785106 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 09:39:14.785352 start: 1.6.2.4 test-definition (timeout 00:09:10) [common]
199 09:39:14.785593 Loading test definitions
200 09:39:14.785867 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:10) [common]
201 09:39:14.786085 Using /lava-939329 at stage 0
202 09:39:14.787176 uuid=939329_1.6.2.4.1 testdef=None
203 09:39:14.787469 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 09:39:14.787727 start: 1.6.2.4.2 test-overlay (timeout 00:09:10) [common]
205 09:39:14.789467 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 09:39:14.790249 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:10) [common]
208 09:39:14.792350 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 09:39:14.793175 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:10) [common]
211 09:39:14.795158 runner path: /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/0/tests/0_v4l2-decoder-conformance-h264 test_uuid 939329_1.6.2.4.1
212 09:39:14.795680 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 09:39:14.796449 Creating lava-test-runner.conf files
215 09:39:14.796652 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/939329/lava-overlay-2a15wn8r/lava-939329/0 for stage 0
216 09:39:14.796977 - 0_v4l2-decoder-conformance-h264
217 09:39:14.797309 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 09:39:14.797574 start: 1.6.2.5 compress-overlay (timeout 00:09:10) [common]
219 09:39:14.818592 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 09:39:14.818972 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:10) [common]
221 09:39:14.819230 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 09:39:14.819494 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 09:39:14.819754 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:10) [common]
224 09:39:15.515555 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 09:39:15.516052 start: 1.6.4 extract-modules (timeout 00:09:10) [common]
226 09:39:15.516327 extracting modules file /var/lib/lava/dispatcher/tmp/939329/tftp-deploy-vy7p4unu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/939329/extract-nfsrootfs-ptpw6spu
227 09:39:16.859127 extracting modules file /var/lib/lava/dispatcher/tmp/939329/tftp-deploy-vy7p4unu/modules/modules.tar to /var/lib/lava/dispatcher/tmp/939329/extract-overlay-ramdisk-gidh4gbu/ramdisk
228 09:39:18.219048 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 09:39:18.219521 start: 1.6.5 apply-overlay-tftp (timeout 00:09:07) [common]
230 09:39:18.219780 [common] Applying overlay to NFS
231 09:39:18.220015 [common] Applying overlay /var/lib/lava/dispatcher/tmp/939329/compress-overlay-qpyt2w3y/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/939329/extract-nfsrootfs-ptpw6spu
232 09:39:18.248844 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 09:39:18.249249 start: 1.6.6 prepare-kernel (timeout 00:09:07) [common]
234 09:39:18.249541 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:07) [common]
235 09:39:18.249776 Converting downloaded kernel to a uImage
236 09:39:18.250084 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/939329/tftp-deploy-vy7p4unu/kernel/Image /var/lib/lava/dispatcher/tmp/939329/tftp-deploy-vy7p4unu/kernel/uImage
237 09:39:18.711770 output: Image Name:
238 09:39:18.712225 output: Created: Tue Nov 5 09:39:18 2024
239 09:39:18.712454 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 09:39:18.712668 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 09:39:18.712874 output: Load Address: 01080000
242 09:39:18.713077 output: Entry Point: 01080000
243 09:39:18.713279 output:
244 09:39:18.713621 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 09:39:18.713894 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 09:39:18.714166 start: 1.6.7 configure-preseed-file (timeout 00:09:06) [common]
247 09:39:18.714428 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 09:39:18.714691 start: 1.6.8 compress-ramdisk (timeout 00:09:06) [common]
249 09:39:18.714928 Building ramdisk /var/lib/lava/dispatcher/tmp/939329/extract-overlay-ramdisk-gidh4gbu/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/939329/extract-overlay-ramdisk-gidh4gbu/ramdisk
250 09:39:20.893042 >> 166825 blocks
251 09:39:28.661798 Adding RAMdisk u-boot header.
252 09:39:28.662506 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/939329/extract-overlay-ramdisk-gidh4gbu/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/939329/extract-overlay-ramdisk-gidh4gbu/ramdisk.cpio.gz.uboot
253 09:39:28.900610 output: Image Name:
254 09:39:28.901159 output: Created: Tue Nov 5 09:39:28 2024
255 09:39:28.901725 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 09:39:28.902288 output: Data Size: 23436285 Bytes = 22887.00 KiB = 22.35 MiB
257 09:39:28.902810 output: Load Address: 00000000
258 09:39:28.903326 output: Entry Point: 00000000
259 09:39:28.903835 output:
260 09:39:28.905237 rename /var/lib/lava/dispatcher/tmp/939329/extract-overlay-ramdisk-gidh4gbu/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/939329/tftp-deploy-vy7p4unu/ramdisk/ramdisk.cpio.gz.uboot
261 09:39:28.906168 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 09:39:28.906890 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
263 09:39:28.907585 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:56) [common]
264 09:39:28.908234 No LXC device requested
265 09:39:28.908918 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 09:39:28.909599 start: 1.8 deploy-device-env (timeout 00:08:56) [common]
267 09:39:28.910283 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 09:39:28.910828 Checking files for TFTP limit of 4294967296 bytes.
269 09:39:28.914447 end: 1 tftp-deploy (duration 00:01:04) [common]
270 09:39:28.915206 start: 2 uboot-action (timeout 00:05:00) [common]
271 09:39:28.915904 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 09:39:28.916636 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 09:39:28.917309 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 09:39:28.917968 Using kernel file from prepare-kernel: 939329/tftp-deploy-vy7p4unu/kernel/uImage
275 09:39:28.918777 substitutions:
276 09:39:28.919300 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 09:39:28.919827 - {DTB_ADDR}: 0x01070000
278 09:39:28.920391 - {DTB}: 939329/tftp-deploy-vy7p4unu/dtb/meson-g12b-a311d-libretech-cc.dtb
279 09:39:28.920908 - {INITRD}: 939329/tftp-deploy-vy7p4unu/ramdisk/ramdisk.cpio.gz.uboot
280 09:39:28.921421 - {KERNEL_ADDR}: 0x01080000
281 09:39:28.921930 - {KERNEL}: 939329/tftp-deploy-vy7p4unu/kernel/uImage
282 09:39:28.922441 - {LAVA_MAC}: None
283 09:39:28.922977 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/939329/extract-nfsrootfs-ptpw6spu
284 09:39:28.923488 - {NFS_SERVER_IP}: 192.168.6.2
285 09:39:28.924029 - {PRESEED_CONFIG}: None
286 09:39:28.924546 - {PRESEED_LOCAL}: None
287 09:39:28.925056 - {RAMDISK_ADDR}: 0x08000000
288 09:39:28.925561 - {RAMDISK}: 939329/tftp-deploy-vy7p4unu/ramdisk/ramdisk.cpio.gz.uboot
289 09:39:28.926064 - {ROOT_PART}: None
290 09:39:28.926566 - {ROOT}: None
291 09:39:28.927068 - {SERVER_IP}: 192.168.6.2
292 09:39:28.927573 - {TEE_ADDR}: 0x83000000
293 09:39:28.928100 - {TEE}: None
294 09:39:28.928616 Parsed boot commands:
295 09:39:28.929113 - setenv autoload no
296 09:39:28.929616 - setenv initrd_high 0xffffffff
297 09:39:28.930104 - setenv fdt_high 0xffffffff
298 09:39:28.930603 - dhcp
299 09:39:28.931103 - setenv serverip 192.168.6.2
300 09:39:28.931602 - tftpboot 0x01080000 939329/tftp-deploy-vy7p4unu/kernel/uImage
301 09:39:28.932131 - tftpboot 0x08000000 939329/tftp-deploy-vy7p4unu/ramdisk/ramdisk.cpio.gz.uboot
302 09:39:28.932639 - tftpboot 0x01070000 939329/tftp-deploy-vy7p4unu/dtb/meson-g12b-a311d-libretech-cc.dtb
303 09:39:28.933142 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/939329/extract-nfsrootfs-ptpw6spu,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 09:39:28.933655 - bootm 0x01080000 0x08000000 0x01070000
305 09:39:28.934310 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 09:39:28.936284 start: 2.3 connect-device (timeout 00:05:00) [common]
308 09:39:28.936850 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 09:39:28.951251 Setting prompt string to ['lava-test: # ']
310 09:39:28.954164 end: 2.3 connect-device (duration 00:00:00) [common]
311 09:39:28.955071 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 09:39:28.955827 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 09:39:28.956640 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 09:39:28.958264 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 09:39:29.000342 >> OK - accepted request
316 09:39:29.002543 Returned 0 in 0 seconds
317 09:39:29.104096 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 09:39:29.106460 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 09:39:29.107309 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 09:39:29.108162 Setting prompt string to ['Hit any key to stop autoboot']
322 09:39:29.108848 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 09:39:29.111347 Trying 192.168.56.21...
324 09:39:29.112064 Connected to conserv1.
325 09:39:29.112690 Escape character is '^]'.
326 09:39:29.113278
327 09:39:29.113848 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
328 09:39:29.114394
329 09:39:40.342505 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 09:39:40.343325 bl2_stage_init 0x01
331 09:39:40.343908 bl2_stage_init 0x81
332 09:39:40.348232 hw id: 0x0000 - pwm id 0x01
333 09:39:40.348914 bl2_stage_init 0xc1
334 09:39:40.349490 bl2_stage_init 0x02
335 09:39:40.350006
336 09:39:40.353619 L0:00000000
337 09:39:40.354198 L1:20000703
338 09:39:40.354718 L2:00008067
339 09:39:40.355232 L3:14000000
340 09:39:40.356463 B2:00402000
341 09:39:40.357025 B1:e0f83180
342 09:39:40.357531
343 09:39:40.358038 TE: 58167
344 09:39:40.358545
345 09:39:40.367783 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 09:39:40.368454
347 09:39:40.368911 Board ID = 1
348 09:39:40.369355 Set A53 clk to 24M
349 09:39:40.369735 Set A73 clk to 24M
350 09:39:40.373740 Set clk81 to 24M
351 09:39:40.374272 A53 clk: 1200 MHz
352 09:39:40.374733 A73 clk: 1200 MHz
353 09:39:40.376835 CLK81: 166.6M
354 09:39:40.377384 smccc: 00012abd
355 09:39:40.382538 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 09:39:40.388004 board id: 1
357 09:39:40.393308 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 09:39:40.403758 fw parse done
359 09:39:40.409706 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 09:39:40.452622 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 09:39:40.463268 PIEI prepare done
362 09:39:40.463827 fastboot data load
363 09:39:40.464331 fastboot data verify
364 09:39:40.468954 verify result: 266
365 09:39:40.474658 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 09:39:40.475259 LPDDR4 probe
367 09:39:40.475774 ddr clk to 1584MHz
368 09:39:40.482673 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 09:39:40.519874
370 09:39:40.520562 dmc_version 0001
371 09:39:40.526327 Check phy result
372 09:39:40.532517 INFO : End of CA training
373 09:39:40.533121 INFO : End of initialization
374 09:39:40.538049 INFO : Training has run successfully!
375 09:39:40.538643 Check phy result
376 09:39:40.543685 INFO : End of initialization
377 09:39:40.544246 INFO : End of read enable training
378 09:39:40.549208 INFO : End of fine write leveling
379 09:39:40.554894 INFO : End of Write leveling coarse delay
380 09:39:40.555424 INFO : Training has run successfully!
381 09:39:40.555844 Check phy result
382 09:39:40.560925 INFO : End of initialization
383 09:39:40.561474 INFO : End of read dq deskew training
384 09:39:40.565973 INFO : End of MPR read delay center optimization
385 09:39:40.571693 INFO : End of write delay center optimization
386 09:39:40.577100 INFO : End of read delay center optimization
387 09:39:40.577678 INFO : End of max read latency training
388 09:39:40.582955 INFO : Training has run successfully!
389 09:39:40.583887 1D training succeed
390 09:39:40.591337 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 09:39:40.639663 Check phy result
392 09:39:40.640790 INFO : End of initialization
393 09:39:40.661448 INFO : End of 2D read delay Voltage center optimization
394 09:39:40.681834 INFO : End of 2D read delay Voltage center optimization
395 09:39:40.733704 INFO : End of 2D write delay Voltage center optimization
396 09:39:40.782960 INFO : End of 2D write delay Voltage center optimization
397 09:39:40.788492 INFO : Training has run successfully!
398 09:39:40.789125
399 09:39:40.789668 channel==0
400 09:39:40.794105 RxClkDly_Margin_A0==88 ps 9
401 09:39:40.794654 TxDqDly_Margin_A0==98 ps 10
402 09:39:40.799632 RxClkDly_Margin_A1==88 ps 9
403 09:39:40.800124 TxDqDly_Margin_A1==98 ps 10
404 09:39:40.800446 TrainedVREFDQ_A0==74
405 09:39:40.805593 TrainedVREFDQ_A1==74
406 09:39:40.806551 VrefDac_Margin_A0==25
407 09:39:40.807395 DeviceVref_Margin_A0==40
408 09:39:40.810878 VrefDac_Margin_A1==25
409 09:39:40.811552 DeviceVref_Margin_A1==40
410 09:39:40.812106
411 09:39:40.812622
412 09:39:40.816532 channel==1
413 09:39:40.817001 RxClkDly_Margin_A0==98 ps 10
414 09:39:40.817457 TxDqDly_Margin_A0==98 ps 10
415 09:39:40.821844 RxClkDly_Margin_A1==88 ps 9
416 09:39:40.822243 TxDqDly_Margin_A1==98 ps 10
417 09:39:40.827579 TrainedVREFDQ_A0==77
418 09:39:40.828506 TrainedVREFDQ_A1==78
419 09:39:40.829290 VrefDac_Margin_A0==22
420 09:39:40.834074 DeviceVref_Margin_A0==37
421 09:39:40.834714 VrefDac_Margin_A1==24
422 09:39:40.838856 DeviceVref_Margin_A1==36
423 09:39:40.839206
424 09:39:40.839442 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 09:39:40.844506
426 09:39:40.872743 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 00000019 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
427 09:39:40.873600 2D training succeed
428 09:39:40.878029 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 09:39:40.883617 auto size-- 65535DDR cs0 size: 2048MB
430 09:39:40.884227 DDR cs1 size: 2048MB
431 09:39:40.889496 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 09:39:40.890095 cs0 DataBus test pass
433 09:39:40.895350 cs1 DataBus test pass
434 09:39:40.896046 cs0 AddrBus test pass
435 09:39:40.896542 cs1 AddrBus test pass
436 09:39:40.897010
437 09:39:40.900621 100bdlr_step_size ps== 420
438 09:39:40.901252 result report
439 09:39:40.907414 boot times 0Enable ddr reg access
440 09:39:40.910939 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 09:39:40.925363 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 09:39:41.497859 0.0;M3 CHK:0;cm4_sp_mode 0
443 09:39:41.498263 MVN_1=0x00000000
444 09:39:41.503496 MVN_2=0x00000000
445 09:39:41.509474 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 09:39:41.509811 OPS=0x10
447 09:39:41.510200 ring efuse init
448 09:39:41.510426 chipver efuse init
449 09:39:41.514718 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 09:39:41.520452 [0.018961 Inits done]
451 09:39:41.520774 secure task start!
452 09:39:41.520996 high task start!
453 09:39:41.524477 low task start!
454 09:39:41.525015 run into bl31
455 09:39:41.531569 NOTICE: BL31: v1.3(release):4fc40b1
456 09:39:41.540267 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 09:39:41.540613 NOTICE: BL31: G12A normal boot!
458 09:39:41.564759 NOTICE: BL31: BL33 decompress pass
459 09:39:41.570554 ERROR: Error initializing runtime service opteed_fast
460 09:39:42.803252
461 09:39:42.803753
462 09:39:42.810955 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 09:39:42.811467
464 09:39:42.811900 Model: Libre Computer AML-A311D-CC Alta
465 09:39:43.020338 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 09:39:43.043538 DRAM: 2 GiB (effective 3.8 GiB)
467 09:39:43.186612 Core: 408 devices, 31 uclasses, devicetree: separate
468 09:39:43.192387 WDT: Not starting watchdog@f0d0
469 09:39:43.224699 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 09:39:43.237129 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 09:39:43.242054 ** Bad device specification mmc 0 **
472 09:39:43.252435 Card did not respond to voltage select! : -110
473 09:39:43.260126 ** Bad device specification mmc 0 **
474 09:39:43.260660 Couldn't find partition mmc 0
475 09:39:43.268450 Card did not respond to voltage select! : -110
476 09:39:43.273899 ** Bad device specification mmc 0 **
477 09:39:43.274345 Couldn't find partition mmc 0
478 09:39:43.278944 Error: could not access storage.
479 09:39:44.542728 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 09:39:44.543157 bl2_stage_init 0x01
481 09:39:44.543385 bl2_stage_init 0x81
482 09:39:44.548281 hw id: 0x0000 - pwm id 0x01
483 09:39:44.548707 bl2_stage_init 0xc1
484 09:39:44.548937 bl2_stage_init 0x02
485 09:39:44.549146
486 09:39:44.553907 L0:00000000
487 09:39:44.554318 L1:20000703
488 09:39:44.554547 L2:00008067
489 09:39:44.554762 L3:14000000
490 09:39:44.556839 B2:00402000
491 09:39:44.557243 B1:e0f83180
492 09:39:44.557468
493 09:39:44.557676 TE: 58124
494 09:39:44.557904
495 09:39:44.568026 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 09:39:44.568415
497 09:39:44.568655 Board ID = 1
498 09:39:44.568867 Set A53 clk to 24M
499 09:39:44.569072 Set A73 clk to 24M
500 09:39:44.573628 Set clk81 to 24M
501 09:39:44.573954 A53 clk: 1200 MHz
502 09:39:44.574174 A73 clk: 1200 MHz
503 09:39:44.579194 CLK81: 166.6M
504 09:39:44.579508 smccc: 00012a92
505 09:39:44.585018 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 09:39:44.585331 board id: 1
507 09:39:44.593367 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 09:39:44.604067 fw parse done
509 09:39:44.609997 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 09:39:44.652778 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 09:39:44.663511 PIEI prepare done
512 09:39:44.663858 fastboot data load
513 09:39:44.664106 fastboot data verify
514 09:39:44.669188 verify result: 266
515 09:39:44.674702 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 09:39:44.675019 LPDDR4 probe
517 09:39:44.675236 ddr clk to 1584MHz
518 09:39:44.682719 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 09:39:44.720070
520 09:39:44.720467 dmc_version 0001
521 09:39:44.726629 Check phy result
522 09:39:44.732493 INFO : End of CA training
523 09:39:44.732817 INFO : End of initialization
524 09:39:44.738131 INFO : Training has run successfully!
525 09:39:44.738448 Check phy result
526 09:39:44.743668 INFO : End of initialization
527 09:39:44.743973 INFO : End of read enable training
528 09:39:44.749339 INFO : End of fine write leveling
529 09:39:44.754903 INFO : End of Write leveling coarse delay
530 09:39:44.755215 INFO : Training has run successfully!
531 09:39:44.755429 Check phy result
532 09:39:44.760550 INFO : End of initialization
533 09:39:44.760868 INFO : End of read dq deskew training
534 09:39:44.766077 INFO : End of MPR read delay center optimization
535 09:39:44.771732 INFO : End of write delay center optimization
536 09:39:44.777325 INFO : End of read delay center optimization
537 09:39:44.777887 INFO : End of max read latency training
538 09:39:44.782960 INFO : Training has run successfully!
539 09:39:44.783470 1D training succeed
540 09:39:44.792140 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 09:39:44.839730 Check phy result
542 09:39:44.840288 INFO : End of initialization
543 09:39:44.861354 INFO : End of 2D read delay Voltage center optimization
544 09:39:44.881460 INFO : End of 2D read delay Voltage center optimization
545 09:39:44.933389 INFO : End of 2D write delay Voltage center optimization
546 09:39:44.982578 INFO : End of 2D write delay Voltage center optimization
547 09:39:44.988164 INFO : Training has run successfully!
548 09:39:44.988660
549 09:39:44.989103 channel==0
550 09:39:44.993730 RxClkDly_Margin_A0==88 ps 9
551 09:39:44.994224 TxDqDly_Margin_A0==98 ps 10
552 09:39:44.999322 RxClkDly_Margin_A1==88 ps 9
553 09:39:44.999808 TxDqDly_Margin_A1==98 ps 10
554 09:39:45.000303 TrainedVREFDQ_A0==74
555 09:39:45.005055 TrainedVREFDQ_A1==74
556 09:39:45.005668 VrefDac_Margin_A0==25
557 09:39:45.006127 DeviceVref_Margin_A0==40
558 09:39:45.010590 VrefDac_Margin_A1==25
559 09:39:45.011092 DeviceVref_Margin_A1==40
560 09:39:45.011592
561 09:39:45.012086
562 09:39:45.016231 channel==1
563 09:39:45.016737 RxClkDly_Margin_A0==98 ps 10
564 09:39:45.017177 TxDqDly_Margin_A0==88 ps 9
565 09:39:45.021875 RxClkDly_Margin_A1==98 ps 10
566 09:39:45.022376 TxDqDly_Margin_A1==88 ps 9
567 09:39:45.027310 TrainedVREFDQ_A0==77
568 09:39:45.027819 TrainedVREFDQ_A1==77
569 09:39:45.028298 VrefDac_Margin_A0==22
570 09:39:45.033031 DeviceVref_Margin_A0==37
571 09:39:45.033511 VrefDac_Margin_A1==24
572 09:39:45.038616 DeviceVref_Margin_A1==37
573 09:39:45.039112
574 09:39:45.039558 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 09:39:45.040021
576 09:39:45.072130 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
577 09:39:45.072506 2D training succeed
578 09:39:45.077853 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 09:39:45.083375 auto size-- 65535DDR cs0 size: 2048MB
580 09:39:45.083707 DDR cs1 size: 2048MB
581 09:39:45.089022 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 09:39:45.089595 cs0 DataBus test pass
583 09:39:45.094629 cs1 DataBus test pass
584 09:39:45.095151 cs0 AddrBus test pass
585 09:39:45.095560 cs1 AddrBus test pass
586 09:39:45.095961
587 09:39:45.100245 100bdlr_step_size ps== 420
588 09:39:45.100619 result report
589 09:39:45.105771 boot times 0Enable ddr reg access
590 09:39:45.111240 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 09:39:45.124661 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 09:39:45.696631 0.0;M3 CHK:0;cm4_sp_mode 0
593 09:39:45.697263 MVN_1=0x00000000
594 09:39:45.702103 MVN_2=0x00000000
595 09:39:45.707888 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 09:39:45.708393 OPS=0x10
597 09:39:45.708814 ring efuse init
598 09:39:45.709206 chipver efuse init
599 09:39:45.716217 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 09:39:45.716825 [0.018961 Inits done]
601 09:39:45.723952 secure task start!
602 09:39:45.724564 high task start!
603 09:39:45.725019 low task start!
604 09:39:45.725456 run into bl31
605 09:39:45.730361 NOTICE: BL31: v1.3(release):4fc40b1
606 09:39:45.738280 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 09:39:45.738798 NOTICE: BL31: G12A normal boot!
608 09:39:45.763464 NOTICE: BL31: BL33 decompress pass
609 09:39:45.769259 ERROR: Error initializing runtime service opteed_fast
610 09:39:47.002067
611 09:39:47.002771
612 09:39:47.010462 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 09:39:47.010999
614 09:39:47.011469 Model: Libre Computer AML-A311D-CC Alta
615 09:39:47.218846 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 09:39:47.242242 DRAM: 2 GiB (effective 3.8 GiB)
617 09:39:47.385234 Core: 408 devices, 31 uclasses, devicetree: separate
618 09:39:47.391174 WDT: Not starting watchdog@f0d0
619 09:39:47.423495 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 09:39:47.435723 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 09:39:47.440785 ** Bad device specification mmc 0 **
622 09:39:47.451056 Card did not respond to voltage select! : -110
623 09:39:47.458780 ** Bad device specification mmc 0 **
624 09:39:47.459278 Couldn't find partition mmc 0
625 09:39:47.467084 Card did not respond to voltage select! : -110
626 09:39:47.472574 ** Bad device specification mmc 0 **
627 09:39:47.473075 Couldn't find partition mmc 0
628 09:39:47.477664 Error: could not access storage.
629 09:39:47.821339 Net: eth0: ethernet@ff3f0000
630 09:39:47.822018 starting USB...
631 09:39:48.072996 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 09:39:48.073503 Starting the controller
633 09:39:48.080146 USB XHCI 1.10
634 09:39:49.793110 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 09:39:49.793552 bl2_stage_init 0x01
636 09:39:49.793763 bl2_stage_init 0x81
637 09:39:49.798670 hw id: 0x0000 - pwm id 0x01
638 09:39:49.799030 bl2_stage_init 0xc1
639 09:39:49.799250 bl2_stage_init 0x02
640 09:39:49.799460
641 09:39:49.804240 L0:00000000
642 09:39:49.804549 L1:20000703
643 09:39:49.804765 L2:00008067
644 09:39:49.804972 L3:14000000
645 09:39:49.809842 B2:00402000
646 09:39:49.810170 B1:e0f83180
647 09:39:49.810405
648 09:39:49.810616 TE: 58167
649 09:39:49.810821
650 09:39:49.815426 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 09:39:49.815761
652 09:39:49.816011 Board ID = 1
653 09:39:49.821077 Set A53 clk to 24M
654 09:39:49.821470 Set A73 clk to 24M
655 09:39:49.821687 Set clk81 to 24M
656 09:39:49.826644 A53 clk: 1200 MHz
657 09:39:49.827031 A73 clk: 1200 MHz
658 09:39:49.827261 CLK81: 166.6M
659 09:39:49.827494 smccc: 00012abe
660 09:39:49.832267 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 09:39:49.837855 board id: 1
662 09:39:49.843846 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 09:39:49.854511 fw parse done
664 09:39:49.861452 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 09:39:49.903213 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 09:39:49.914156 PIEI prepare done
667 09:39:49.914570 fastboot data load
668 09:39:49.914794 fastboot data verify
669 09:39:49.919721 verify result: 266
670 09:39:49.925231 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 09:39:49.925806 LPDDR4 probe
672 09:39:49.926090 ddr clk to 1584MHz
673 09:39:49.933452 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 09:39:49.970820
675 09:39:49.971284 dmc_version 0001
676 09:39:49.977240 Check phy result
677 09:39:49.983015 INFO : End of CA training
678 09:39:49.983430 INFO : End of initialization
679 09:39:49.988665 INFO : Training has run successfully!
680 09:39:49.989255 Check phy result
681 09:39:49.994254 INFO : End of initialization
682 09:39:49.994669 INFO : End of read enable training
683 09:39:49.999851 INFO : End of fine write leveling
684 09:39:50.005425 INFO : End of Write leveling coarse delay
685 09:39:50.005959 INFO : Training has run successfully!
686 09:39:50.006306 Check phy result
687 09:39:50.011170 INFO : End of initialization
688 09:39:50.011548 INFO : End of read dq deskew training
689 09:39:50.016582 INFO : End of MPR read delay center optimization
690 09:39:50.022283 INFO : End of write delay center optimization
691 09:39:50.027750 INFO : End of read delay center optimization
692 09:39:50.028148 INFO : End of max read latency training
693 09:39:50.033509 INFO : Training has run successfully!
694 09:39:50.033879 1D training succeed
695 09:39:50.042592 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 09:39:50.090187 Check phy result
697 09:39:50.090616 INFO : End of initialization
698 09:39:50.111865 INFO : End of 2D read delay Voltage center optimization
699 09:39:50.131288 INFO : End of 2D read delay Voltage center optimization
700 09:39:50.183471 INFO : End of 2D write delay Voltage center optimization
701 09:39:50.232754 INFO : End of 2D write delay Voltage center optimization
702 09:39:50.238542 INFO : Training has run successfully!
703 09:39:50.239535
704 09:39:50.240740 channel==0
705 09:39:50.243955 RxClkDly_Margin_A0==88 ps 9
706 09:39:50.244681 TxDqDly_Margin_A0==98 ps 10
707 09:39:50.247146 RxClkDly_Margin_A1==88 ps 9
708 09:39:50.247532 TxDqDly_Margin_A1==98 ps 10
709 09:39:50.253067 TrainedVREFDQ_A0==74
710 09:39:50.253635 TrainedVREFDQ_A1==74
711 09:39:50.253952 VrefDac_Margin_A0==25
712 09:39:50.258661 DeviceVref_Margin_A0==40
713 09:39:50.259089 VrefDac_Margin_A1==25
714 09:39:50.263937 DeviceVref_Margin_A1==40
715 09:39:50.264387
716 09:39:50.264676
717 09:39:50.264896 channel==1
718 09:39:50.265101 RxClkDly_Margin_A0==78 ps 8
719 09:39:50.269889 TxDqDly_Margin_A0==98 ps 10
720 09:39:50.270528 RxClkDly_Margin_A1==88 ps 9
721 09:39:50.275352 TxDqDly_Margin_A1==88 ps 9
722 09:39:50.275963 TrainedVREFDQ_A0==77
723 09:39:50.276466 TrainedVREFDQ_A1==77
724 09:39:50.280954 VrefDac_Margin_A0==23
725 09:39:50.281561 DeviceVref_Margin_A0==37
726 09:39:50.286499 VrefDac_Margin_A1==24
727 09:39:50.287080 DeviceVref_Margin_A1==37
728 09:39:50.287531
729 09:39:50.292090 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 09:39:50.292609
731 09:39:50.320089 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000019 00000017 00000019 00000018 00000018 00000019 00000019 00000019 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
732 09:39:50.325640 2D training succeed
733 09:39:50.331182 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 09:39:50.331786 auto size-- 65535DDR cs0 size: 2048MB
735 09:39:50.336825 DDR cs1 size: 2048MB
736 09:39:50.337444 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 09:39:50.342363 cs0 DataBus test pass
738 09:39:50.342930 cs1 DataBus test pass
739 09:39:50.343377 cs0 AddrBus test pass
740 09:39:50.348061 cs1 AddrBus test pass
741 09:39:50.348679
742 09:39:50.349154 100bdlr_step_size ps== 420
743 09:39:50.349612 result report
744 09:39:50.353562 boot times 0Enable ddr reg access
745 09:39:50.361218 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 09:39:50.374730 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 09:39:50.948384 0.0;M3 CHK:0;cm4_sp_mode 0
748 09:39:50.949113 MVN_1=0x00000000
749 09:39:50.953868 MVN_2=0x00000000
750 09:39:50.959718 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 09:39:50.960504 OPS=0x10
752 09:39:50.960978 ring efuse init
753 09:39:50.961435 chipver efuse init
754 09:39:50.967946 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 09:39:50.968596 [0.018960 Inits done]
756 09:39:50.969048 secure task start!
757 09:39:50.975445 high task start!
758 09:39:50.975872 low task start!
759 09:39:50.976324 run into bl31
760 09:39:50.981953 NOTICE: BL31: v1.3(release):4fc40b1
761 09:39:50.989890 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 09:39:50.990570 NOTICE: BL31: G12A normal boot!
763 09:39:51.015372 NOTICE: BL31: BL33 decompress pass
764 09:39:51.021044 ERROR: Error initializing runtime service opteed_fast
765 09:39:52.253728
766 09:39:52.254413
767 09:39:52.262225 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 09:39:52.262735
769 09:39:52.263187 Model: Libre Computer AML-A311D-CC Alta
770 09:39:52.470791 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 09:39:52.494025 DRAM: 2 GiB (effective 3.8 GiB)
772 09:39:52.636991 Core: 408 devices, 31 uclasses, devicetree: separate
773 09:39:52.642968 WDT: Not starting watchdog@f0d0
774 09:39:52.675257 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 09:39:52.687459 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 09:39:52.692603 ** Bad device specification mmc 0 **
777 09:39:52.702933 Card did not respond to voltage select! : -110
778 09:39:52.710560 ** Bad device specification mmc 0 **
779 09:39:52.711050 Couldn't find partition mmc 0
780 09:39:52.718919 Card did not respond to voltage select! : -110
781 09:39:52.724400 ** Bad device specification mmc 0 **
782 09:39:52.724886 Couldn't find partition mmc 0
783 09:39:52.729395 Error: could not access storage.
784 09:39:53.073118 Net: eth0: ethernet@ff3f0000
785 09:39:53.073795 starting USB...
786 09:39:53.324817 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 09:39:53.325505 Starting the controller
788 09:39:53.331778 USB XHCI 1.10
789 09:39:55.494632 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 09:39:55.495051 bl2_stage_init 0x01
791 09:39:55.495262 bl2_stage_init 0x81
792 09:39:55.500219 hw id: 0x0000 - pwm id 0x01
793 09:39:55.500493 bl2_stage_init 0xc1
794 09:39:55.500710 bl2_stage_init 0x02
795 09:39:55.500910
796 09:39:55.505693 L0:00000000
797 09:39:55.506060 L1:20000703
798 09:39:55.506366 L2:00008067
799 09:39:55.506661 L3:14000000
800 09:39:55.511526 B2:00402000
801 09:39:55.511892 B1:e0f83180
802 09:39:55.512153
803 09:39:55.512358 TE: 58124
804 09:39:55.512555
805 09:39:55.516926 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 09:39:55.517311
807 09:39:55.517624 Board ID = 1
808 09:39:55.522504 Set A53 clk to 24M
809 09:39:55.522871 Set A73 clk to 24M
810 09:39:55.523175 Set clk81 to 24M
811 09:39:55.528220 A53 clk: 1200 MHz
812 09:39:55.528591 A73 clk: 1200 MHz
813 09:39:55.528821 CLK81: 166.6M
814 09:39:55.529024 smccc: 00012a91
815 09:39:55.533808 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 09:39:55.539429 board id: 1
817 09:39:55.545319 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 09:39:55.556018 fw parse done
819 09:39:55.561984 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 09:39:55.603463 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 09:39:55.615407 PIEI prepare done
822 09:39:55.615719 fastboot data load
823 09:39:55.615930 fastboot data verify
824 09:39:55.620903 verify result: 266
825 09:39:55.626498 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 09:39:55.626785 LPDDR4 probe
827 09:39:55.626991 ddr clk to 1584MHz
828 09:39:55.634455 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 09:39:55.671810
830 09:39:55.672215 dmc_version 0001
831 09:39:55.678506 Check phy result
832 09:39:55.684296 INFO : End of CA training
833 09:39:55.684602 INFO : End of initialization
834 09:39:55.689858 INFO : Training has run successfully!
835 09:39:55.690165 Check phy result
836 09:39:55.695476 INFO : End of initialization
837 09:39:55.695901 INFO : End of read enable training
838 09:39:55.701072 INFO : End of fine write leveling
839 09:39:55.706663 INFO : End of Write leveling coarse delay
840 09:39:55.706958 INFO : Training has run successfully!
841 09:39:55.707164 Check phy result
842 09:39:55.712262 INFO : End of initialization
843 09:39:55.712648 INFO : End of read dq deskew training
844 09:39:55.717843 INFO : End of MPR read delay center optimization
845 09:39:55.723452 INFO : End of write delay center optimization
846 09:39:55.729047 INFO : End of read delay center optimization
847 09:39:55.729323 INFO : End of max read latency training
848 09:39:55.734627 INFO : Training has run successfully!
849 09:39:55.735016 1D training succeed
850 09:39:55.743889 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 09:39:55.791609 Check phy result
852 09:39:55.791998 INFO : End of initialization
853 09:39:55.813203 INFO : End of 2D read delay Voltage center optimization
854 09:39:55.834797 INFO : End of 2D read delay Voltage center optimization
855 09:39:55.885678 INFO : End of 2D write delay Voltage center optimization
856 09:39:55.934915 INFO : End of 2D write delay Voltage center optimization
857 09:39:55.940428 INFO : Training has run successfully!
858 09:39:55.940890
859 09:39:55.941149 channel==0
860 09:39:55.945979 RxClkDly_Margin_A0==88 ps 9
861 09:39:55.946303 TxDqDly_Margin_A0==98 ps 10
862 09:39:55.951644 RxClkDly_Margin_A1==88 ps 9
863 09:39:55.951963 TxDqDly_Margin_A1==98 ps 10
864 09:39:55.952220 TrainedVREFDQ_A0==74
865 09:39:55.957306 TrainedVREFDQ_A1==74
866 09:39:55.957616 VrefDac_Margin_A0==25
867 09:39:55.957828 DeviceVref_Margin_A0==40
868 09:39:55.962844 VrefDac_Margin_A1==25
869 09:39:55.963161 DeviceVref_Margin_A1==40
870 09:39:55.963371
871 09:39:55.963578
872 09:39:55.968469 channel==1
873 09:39:55.968773 RxClkDly_Margin_A0==98 ps 10
874 09:39:55.968982 TxDqDly_Margin_A0==98 ps 10
875 09:39:55.974035 RxClkDly_Margin_A1==88 ps 9
876 09:39:55.974342 TxDqDly_Margin_A1==88 ps 9
877 09:39:55.979619 TrainedVREFDQ_A0==76
878 09:39:55.979916 TrainedVREFDQ_A1==77
879 09:39:55.980157 VrefDac_Margin_A0==22
880 09:39:55.985264 DeviceVref_Margin_A0==38
881 09:39:55.985560 VrefDac_Margin_A1==24
882 09:39:55.990803 DeviceVref_Margin_A1==37
883 09:39:55.991105
884 09:39:55.991317 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 09:39:55.991521
886 09:39:56.024482 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
887 09:39:56.024863 2D training succeed
888 09:39:56.030035 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 09:39:56.035614 auto size-- 65535DDR cs0 size: 2048MB
890 09:39:56.035916 DDR cs1 size: 2048MB
891 09:39:56.041201 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 09:39:56.041503 cs0 DataBus test pass
893 09:39:56.046823 cs1 DataBus test pass
894 09:39:56.047122 cs0 AddrBus test pass
895 09:39:56.047331 cs1 AddrBus test pass
896 09:39:56.047532
897 09:39:56.052575 100bdlr_step_size ps== 420
898 09:39:56.052892 result report
899 09:39:56.058046 boot times 0Enable ddr reg access
900 09:39:56.063373 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 09:39:56.076862 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 09:39:56.650719 0.0;M3 CHK:0;cm4_sp_mode 0
903 09:39:56.651146 MVN_1=0x00000000
904 09:39:56.656069 MVN_2=0x00000000
905 09:39:56.661820 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 09:39:56.662151 OPS=0x10
907 09:39:56.662369 ring efuse init
908 09:39:56.662584 chipver efuse init
909 09:39:56.670105 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 09:39:56.670441 [0.018961 Inits done]
911 09:39:56.670651 secure task start!
912 09:39:56.677656 high task start!
913 09:39:56.677969 low task start!
914 09:39:56.678176 run into bl31
915 09:39:56.684314 NOTICE: BL31: v1.3(release):4fc40b1
916 09:39:56.692062 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 09:39:56.692518 NOTICE: BL31: G12A normal boot!
918 09:39:56.717467 NOTICE: BL31: BL33 decompress pass
919 09:39:56.723087 ERROR: Error initializing runtime service opteed_fast
920 09:39:57.955970
921 09:39:57.956389
922 09:39:57.963555 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 09:39:57.963849
924 09:39:57.964087 Model: Libre Computer AML-A311D-CC Alta
925 09:39:58.172989 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 09:39:58.196295 DRAM: 2 GiB (effective 3.8 GiB)
927 09:39:58.339263 Core: 408 devices, 31 uclasses, devicetree: separate
928 09:39:58.345108 WDT: Not starting watchdog@f0d0
929 09:39:58.377411 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 09:39:58.389799 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 09:39:58.394320 ** Bad device specification mmc 0 **
932 09:39:58.405158 Card did not respond to voltage select! : -110
933 09:39:58.412905 ** Bad device specification mmc 0 **
934 09:39:58.413456 Couldn't find partition mmc 0
935 09:39:58.421120 Card did not respond to voltage select! : -110
936 09:39:58.426673 ** Bad device specification mmc 0 **
937 09:39:58.427302 Couldn't find partition mmc 0
938 09:39:58.431683 Error: could not access storage.
939 09:39:58.775224 Net: eth0: ethernet@ff3f0000
940 09:39:58.775953 starting USB...
941 09:39:59.026989 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 09:39:59.027723 Starting the controller
943 09:39:59.034119 USB XHCI 1.10
944 09:40:00.894142 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 09:40:00.896651 bl2_stage_init 0x01
946 09:40:00.897264 bl2_stage_init 0x81
947 09:40:00.897760 hw id: 0x0000 - pwm id 0x01
948 09:40:00.902019 bl2_stage_init 0xc1
949 09:40:00.902556 bl2_stage_init 0x02
950 09:40:00.903011
951 09:40:00.903452 L0:00000000
952 09:40:00.907719 L1:20000703
953 09:40:00.908395 L2:00008067
954 09:40:00.908916 L3:14000000
955 09:40:00.909368 B2:00402000
956 09:40:00.909816 B1:e0f83180
957 09:40:00.910258
958 09:40:00.913240 TE: 58167
959 09:40:00.913774
960 09:40:00.918941 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 09:40:00.919485
962 09:40:00.919933 Board ID = 1
963 09:40:00.920413 Set A53 clk to 24M
964 09:40:00.924541 Set A73 clk to 24M
965 09:40:00.925132 Set clk81 to 24M
966 09:40:00.925583 A53 clk: 1200 MHz
967 09:40:00.926062 A73 clk: 1200 MHz
968 09:40:00.930032 CLK81: 166.6M
969 09:40:00.930587 smccc: 00012abe
970 09:40:00.935609 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 09:40:00.936190 board id: 1
972 09:40:00.945371 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 09:40:00.955947 fw parse done
974 09:40:00.961860 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 09:40:01.004434 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 09:40:01.015338 PIEI prepare done
977 09:40:01.015949 fastboot data load
978 09:40:01.016498 fastboot data verify
979 09:40:01.020900 verify result: 266
980 09:40:01.026494 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 09:40:01.027105 LPDDR4 probe
982 09:40:01.027598 ddr clk to 1584MHz
983 09:40:01.034488 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 09:40:01.071826
985 09:40:01.072490 dmc_version 0001
986 09:40:01.078441 Check phy result
987 09:40:01.084362 INFO : End of CA training
988 09:40:01.084942 INFO : End of initialization
989 09:40:01.089954 INFO : Training has run successfully!
990 09:40:01.090602 Check phy result
991 09:40:01.095529 INFO : End of initialization
992 09:40:01.095899 INFO : End of read enable training
993 09:40:01.101305 INFO : End of fine write leveling
994 09:40:01.106804 INFO : End of Write leveling coarse delay
995 09:40:01.107184 INFO : Training has run successfully!
996 09:40:01.107418 Check phy result
997 09:40:01.112407 INFO : End of initialization
998 09:40:01.112767 INFO : End of read dq deskew training
999 09:40:01.125051 INFO : End of MPR read delay center optimization
1000 09:40:01.125432 INFO : End of write delay center optimization
1001 09:40:01.126916 INFO : End of read delay center optimization
1002 09:40:01.132518 INFO : End of max read latency training
1003 09:40:01.132868 INFO : Training has run successfully!
1004 09:40:01.138098 1D training succeed
1005 09:40:01.144185 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 09:40:01.191676 Check phy result
1007 09:40:01.192084 INFO : End of initialization
1008 09:40:01.213151 INFO : End of 2D read delay Voltage center optimization
1009 09:40:01.233241 INFO : End of 2D read delay Voltage center optimization
1010 09:40:01.285207 INFO : End of 2D write delay Voltage center optimization
1011 09:40:01.334447 INFO : End of 2D write delay Voltage center optimization
1012 09:40:01.340015 INFO : Training has run successfully!
1013 09:40:01.340425
1014 09:40:01.340672 channel==0
1015 09:40:01.345531 RxClkDly_Margin_A0==88 ps 9
1016 09:40:01.345929 TxDqDly_Margin_A0==98 ps 10
1017 09:40:01.351109 RxClkDly_Margin_A1==88 ps 9
1018 09:40:01.351441 TxDqDly_Margin_A1==98 ps 10
1019 09:40:01.351664 TrainedVREFDQ_A0==74
1020 09:40:01.356724 TrainedVREFDQ_A1==74
1021 09:40:01.357122 VrefDac_Margin_A0==25
1022 09:40:01.357343 DeviceVref_Margin_A0==40
1023 09:40:01.362352 VrefDac_Margin_A1==25
1024 09:40:01.362699 DeviceVref_Margin_A1==40
1025 09:40:01.362918
1026 09:40:01.363138
1027 09:40:01.367932 channel==1
1028 09:40:01.368326 RxClkDly_Margin_A0==98 ps 10
1029 09:40:01.368554 TxDqDly_Margin_A0==98 ps 10
1030 09:40:01.373511 RxClkDly_Margin_A1==98 ps 10
1031 09:40:01.373889 TxDqDly_Margin_A1==88 ps 9
1032 09:40:01.379152 TrainedVREFDQ_A0==77
1033 09:40:01.379562 TrainedVREFDQ_A1==77
1034 09:40:01.379792 VrefDac_Margin_A0==22
1035 09:40:01.384910 DeviceVref_Margin_A0==37
1036 09:40:01.385329 VrefDac_Margin_A1==22
1037 09:40:01.390396 DeviceVref_Margin_A1==37
1038 09:40:01.390841
1039 09:40:01.391081 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 09:40:01.395961
1041 09:40:01.423941 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000018 00000015 00000017 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1042 09:40:01.424378 2D training succeed
1043 09:40:01.429538 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 09:40:01.435166 auto size-- 65535DDR cs0 size: 2048MB
1045 09:40:01.435581 DDR cs1 size: 2048MB
1046 09:40:01.440727 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 09:40:01.441139 cs0 DataBus test pass
1048 09:40:01.446391 cs1 DataBus test pass
1049 09:40:01.446774 cs0 AddrBus test pass
1050 09:40:01.446999 cs1 AddrBus test pass
1051 09:40:01.447213
1052 09:40:01.451942 100bdlr_step_size ps== 420
1053 09:40:01.452345 result report
1054 09:40:01.457484 boot times 0Enable ddr reg access
1055 09:40:01.462965 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 09:40:01.476348 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 09:40:02.048489 0.0;M3 CHK:0;cm4_sp_mode 0
1058 09:40:02.049148 MVN_1=0x00000000
1059 09:40:02.053881 MVN_2=0x00000000
1060 09:40:02.059655 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 09:40:02.060211 OPS=0x10
1062 09:40:02.060665 ring efuse init
1063 09:40:02.061105 chipver efuse init
1064 09:40:02.066286 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 09:40:02.070904 [0.018961 Inits done]
1066 09:40:02.071415 secure task start!
1067 09:40:02.071864 high task start!
1068 09:40:02.075446 low task start!
1069 09:40:02.075941 run into bl31
1070 09:40:02.082092 NOTICE: BL31: v1.3(release):4fc40b1
1071 09:40:02.089971 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 09:40:02.090487 NOTICE: BL31: G12A normal boot!
1073 09:40:02.115367 NOTICE: BL31: BL33 decompress pass
1074 09:40:02.120941 ERROR: Error initializing runtime service opteed_fast
1075 09:40:03.353916
1076 09:40:03.354604
1077 09:40:03.362437 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 09:40:03.362971
1079 09:40:03.363423 Model: Libre Computer AML-A311D-CC Alta
1080 09:40:03.570784 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 09:40:03.594067 DRAM: 2 GiB (effective 3.8 GiB)
1082 09:40:03.737118 Core: 408 devices, 31 uclasses, devicetree: separate
1083 09:40:03.742970 WDT: Not starting watchdog@f0d0
1084 09:40:03.775227 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 09:40:03.787626 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 09:40:03.792643 ** Bad device specification mmc 0 **
1087 09:40:03.802962 Card did not respond to voltage select! : -110
1088 09:40:03.810590 ** Bad device specification mmc 0 **
1089 09:40:03.811095 Couldn't find partition mmc 0
1090 09:40:03.818902 Card did not respond to voltage select! : -110
1091 09:40:03.824497 ** Bad device specification mmc 0 **
1092 09:40:03.824980 Couldn't find partition mmc 0
1093 09:40:03.829573 Error: could not access storage.
1094 09:40:04.173056 Net: eth0: ethernet@ff3f0000
1095 09:40:04.173694 starting USB...
1096 09:40:04.424907 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 09:40:04.425575 Starting the controller
1098 09:40:04.431816 USB XHCI 1.10
1099 09:40:05.989152 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 09:40:05.997435 scanning usb for storage devices... 0 Storage Device(s) found
1102 09:40:06.049104 Hit any key to stop autoboot: 1
1103 09:40:06.050028 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 09:40:06.050650 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 09:40:06.051181 Setting prompt string to ['=>']
1106 09:40:06.051704 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 09:40:06.064911 0
1108 09:40:06.065869 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 09:40:06.066400 Sending with 10 millisecond of delay
1111 09:40:07.202706 => setenv autoload no
1112 09:40:07.213309 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1113 09:40:07.216103 setenv autoload no
1114 09:40:07.216678 Sending with 10 millisecond of delay
1116 09:40:09.012936 => setenv initrd_high 0xffffffff
1117 09:40:09.023469 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 09:40:09.024032 setenv initrd_high 0xffffffff
1119 09:40:09.024506 Sending with 10 millisecond of delay
1121 09:40:10.640261 => setenv fdt_high 0xffffffff
1122 09:40:10.650829 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 09:40:10.651364 setenv fdt_high 0xffffffff
1124 09:40:10.651909 Sending with 10 millisecond of delay
1126 09:40:10.943389 => dhcp
1127 09:40:10.953951 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 09:40:10.954480 dhcp
1129 09:40:10.954743 Speed: 1000, full duplex
1130 09:40:10.954983 BOOTP broadcast 1
1131 09:40:10.962048 DHCP client bound to address 192.168.6.27 (8 ms)
1132 09:40:10.962565 Sending with 10 millisecond of delay
1134 09:40:12.638851 => setenv serverip 192.168.6.2
1135 09:40:12.649456 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1136 09:40:12.650036 setenv serverip 192.168.6.2
1137 09:40:12.650529 Sending with 10 millisecond of delay
1139 09:40:16.377626 => tftpboot 0x01080000 939329/tftp-deploy-vy7p4unu/kernel/uImage
1140 09:40:16.388479 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:13)
1141 09:40:16.389171 tftpboot 0x01080000 939329/tftp-deploy-vy7p4unu/kernel/uImage
1142 09:40:16.389476 Speed: 1000, full duplex
1143 09:40:16.389716 Using ethernet@ff3f0000 device
1144 09:40:16.390997 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1145 09:40:16.396570 Filename '939329/tftp-deploy-vy7p4unu/kernel/uImage'.
1146 09:40:16.400629 Load address: 0x1080000
1147 09:40:19.593093 Loading: *################################################## 43.6 MiB
1148 09:40:19.593845 13.6 MiB/s
1149 09:40:19.594377 done
1150 09:40:19.597637 Bytes transferred = 45713984 (2b98a40 hex)
1151 09:40:19.598882 Sending with 10 millisecond of delay
1153 09:40:24.289355 => tftpboot 0x08000000 939329/tftp-deploy-vy7p4unu/ramdisk/ramdisk.cpio.gz.uboot
1154 09:40:24.300176 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1155 09:40:24.301060 tftpboot 0x08000000 939329/tftp-deploy-vy7p4unu/ramdisk/ramdisk.cpio.gz.uboot
1156 09:40:24.301544 Speed: 1000, full duplex
1157 09:40:24.301983 Using ethernet@ff3f0000 device
1158 09:40:24.302945 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1159 09:40:24.311503 Filename '939329/tftp-deploy-vy7p4unu/ramdisk/ramdisk.cpio.gz.uboot'.
1160 09:40:24.312066 Load address: 0x8000000
1161 09:40:30.836095 Loading: *#########T ######################################## UDP wrong checksum 00000005 00008e52
1162 09:40:35.836990 T UDP wrong checksum 00000005 00008e52
1163 09:40:45.840113 T T UDP wrong checksum 00000005 00008e52
1164 09:40:55.089362 T UDP wrong checksum 000000ff 00006c9c
1165 09:40:55.101930 UDP wrong checksum 000000ff 0000028f
1166 09:41:05.843114 T T T UDP wrong checksum 00000005 00008e52
1167 09:41:16.664625 T T UDP wrong checksum 000000ff 0000ec47
1168 09:41:16.703896 UDP wrong checksum 000000ff 0000853a
1169 09:41:20.848193
1170 09:41:20.848804 Retry count exceeded; starting again
1172 09:41:20.850335 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1175 09:41:20.852242 end: 2.4 uboot-commands (duration 00:01:52) [common]
1177 09:41:20.853638 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1179 09:41:20.854722 end: 2 uboot-action (duration 00:01:52) [common]
1181 09:41:20.856366 Cleaning after the job
1182 09:41:20.856986 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939329/tftp-deploy-vy7p4unu/ramdisk
1183 09:41:20.858326 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939329/tftp-deploy-vy7p4unu/kernel
1184 09:41:20.881083 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939329/tftp-deploy-vy7p4unu/dtb
1185 09:41:20.882505 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939329/tftp-deploy-vy7p4unu/nfsrootfs
1186 09:41:20.935281 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/939329/tftp-deploy-vy7p4unu/modules
1187 09:41:20.941937 start: 4.1 power-off (timeout 00:00:30) [common]
1188 09:41:20.942541 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1189 09:41:20.981994 >> OK - accepted request
1190 09:41:20.984088 Returned 0 in 0 seconds
1191 09:41:21.084996 end: 4.1 power-off (duration 00:00:00) [common]
1193 09:41:21.086718 start: 4.2 read-feedback (timeout 00:10:00) [common]
1194 09:41:21.087867 Listened to connection for namespace 'common' for up to 1s
1195 09:41:22.088279 Finalising connection for namespace 'common'
1196 09:41:22.089037 Disconnecting from shell: Finalise
1197 09:41:22.089518 =>
1198 09:41:22.190483 end: 4.2 read-feedback (duration 00:00:01) [common]
1199 09:41:22.191178 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/939329
1200 09:41:24.807700 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/939329
1201 09:41:24.808323 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.