Boot log: beaglebone-black
- Warnings: 2
- Kernel Warnings: 15
- Errors: 0
- Boot result: PASS
- Kernel Errors: 10
1 20:25:12.688348 lava-dispatcher, installed at version: 2024.01
2 20:25:12.689185 start: 0 validate
3 20:25:12.689704 Start time: 2024-11-07 20:25:12.689672+00:00 (UTC)
4 20:25:12.690355 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
5 20:25:12.690944 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Finitrd.cpio.gz exists
6 20:25:12.722259 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
7 20:25:12.722811 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-510-gd85128e259496%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fkernel%2FzImage exists
8 20:25:12.747549 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
9 20:25:12.748219 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-510-gd85128e259496%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fdtbs%2Fti%2Fomap%2Fam335x-boneblack.dtb exists
10 20:25:12.774045 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
11 20:25:12.774609 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farmhf%2Ffull.rootfs.tar.xz exists
12 20:25:12.800417 Using caching service: 'http://192.168.6.3:8001/api/v1/fetch?url=%s'
13 20:25:12.800927 Validating that http://192.168.6.3:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-510-gd85128e259496%2Farm%2Fmulti_v7_defconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 20:25:12.832219 validate duration: 0.14
16 20:25:12.833348 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 20:25:12.833716 start: 1.1 download-retry (timeout 00:10:00) [common]
18 20:25:12.834045 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 20:25:12.838003 Not decompressing ramdisk as can be used compressed.
20 20:25:12.838481 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/initrd.cpio.gz
21 20:25:12.838760 saving as /var/lib/lava/dispatcher/tmp/955215/tftp-deploy-b7zdcl50/ramdisk/initrd.cpio.gz
22 20:25:12.839036 total size: 4775763 (4 MB)
23 20:25:12.865175 progress 0 % (0 MB)
24 20:25:12.869469 progress 5 % (0 MB)
25 20:25:12.872757 progress 10 % (0 MB)
26 20:25:12.875846 progress 15 % (0 MB)
27 20:25:12.879380 progress 20 % (0 MB)
28 20:25:12.882473 progress 25 % (1 MB)
29 20:25:12.885593 progress 30 % (1 MB)
30 20:25:12.889104 progress 35 % (1 MB)
31 20:25:12.892248 progress 40 % (1 MB)
32 20:25:12.895282 progress 45 % (2 MB)
33 20:25:12.898193 progress 50 % (2 MB)
34 20:25:12.901496 progress 55 % (2 MB)
35 20:25:12.904428 progress 60 % (2 MB)
36 20:25:12.907318 progress 65 % (2 MB)
37 20:25:12.910651 progress 70 % (3 MB)
38 20:25:12.913525 progress 75 % (3 MB)
39 20:25:12.916529 progress 80 % (3 MB)
40 20:25:12.919456 progress 85 % (3 MB)
41 20:25:12.922730 progress 90 % (4 MB)
42 20:25:12.925598 progress 95 % (4 MB)
43 20:25:12.928547 progress 100 % (4 MB)
44 20:25:12.929204 4 MB downloaded in 0.09 s (50.53 MB/s)
45 20:25:12.929772 end: 1.1.1 http-download (duration 00:00:00) [common]
47 20:25:12.930717 end: 1.1 download-retry (duration 00:00:00) [common]
48 20:25:12.931036 start: 1.2 download-retry (timeout 00:10:00) [common]
49 20:25:12.931321 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 20:25:12.932038 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-510-gd85128e259496/arm/multi_v7_defconfig/gcc-12/kernel/zImage
51 20:25:12.932304 saving as /var/lib/lava/dispatcher/tmp/955215/tftp-deploy-b7zdcl50/kernel/zImage
52 20:25:12.932548 total size: 11457024 (10 MB)
53 20:25:12.932772 No compression specified
54 20:25:12.965801 progress 0 % (0 MB)
55 20:25:12.972890 progress 5 % (0 MB)
56 20:25:12.979705 progress 10 % (1 MB)
57 20:25:12.986963 progress 15 % (1 MB)
58 20:25:12.993709 progress 20 % (2 MB)
59 20:25:13.000855 progress 25 % (2 MB)
60 20:25:13.007790 progress 30 % (3 MB)
61 20:25:13.014816 progress 35 % (3 MB)
62 20:25:13.021440 progress 40 % (4 MB)
63 20:25:13.028620 progress 45 % (4 MB)
64 20:25:13.035327 progress 50 % (5 MB)
65 20:25:13.042522 progress 55 % (6 MB)
66 20:25:13.049423 progress 60 % (6 MB)
67 20:25:13.056902 progress 65 % (7 MB)
68 20:25:13.063983 progress 70 % (7 MB)
69 20:25:13.071515 progress 75 % (8 MB)
70 20:25:13.078328 progress 80 % (8 MB)
71 20:25:13.085112 progress 85 % (9 MB)
72 20:25:13.091564 progress 90 % (9 MB)
73 20:25:13.098283 progress 95 % (10 MB)
74 20:25:13.104865 progress 100 % (10 MB)
75 20:25:13.105506 10 MB downloaded in 0.17 s (63.18 MB/s)
76 20:25:13.106028 end: 1.2.1 http-download (duration 00:00:00) [common]
78 20:25:13.106888 end: 1.2 download-retry (duration 00:00:00) [common]
79 20:25:13.107162 start: 1.3 download-retry (timeout 00:10:00) [common]
80 20:25:13.107536 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 20:25:13.108180 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-510-gd85128e259496/arm/multi_v7_defconfig/gcc-12/dtbs/ti/omap/am335x-boneblack.dtb
82 20:25:13.108481 saving as /var/lib/lava/dispatcher/tmp/955215/tftp-deploy-b7zdcl50/dtb/am335x-boneblack.dtb
83 20:25:13.108703 total size: 70568 (0 MB)
84 20:25:13.108927 No compression specified
85 20:25:13.143254 progress 46 % (0 MB)
86 20:25:13.144091 progress 92 % (0 MB)
87 20:25:13.144828 progress 100 % (0 MB)
88 20:25:13.145224 0 MB downloaded in 0.04 s (1.84 MB/s)
89 20:25:13.145683 end: 1.3.1 http-download (duration 00:00:00) [common]
91 20:25:13.147426 end: 1.3 download-retry (duration 00:00:00) [common]
92 20:25:13.148002 start: 1.4 download-retry (timeout 00:10:00) [common]
93 20:25:13.148569 start: 1.4.1 http-download (timeout 00:10:00) [common]
94 20:25:13.150462 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/armhf/full.rootfs.tar.xz
95 20:25:13.150782 saving as /var/lib/lava/dispatcher/tmp/955215/tftp-deploy-b7zdcl50/nfsrootfs/full.rootfs.tar
96 20:25:13.150991 total size: 117747780 (112 MB)
97 20:25:13.151203 Using unxz to decompress xz
98 20:25:13.185637 progress 0 % (0 MB)
99 20:25:13.908090 progress 5 % (5 MB)
100 20:25:14.638535 progress 10 % (11 MB)
101 20:25:15.396861 progress 15 % (16 MB)
102 20:25:16.103480 progress 20 % (22 MB)
103 20:25:16.676925 progress 25 % (28 MB)
104 20:25:17.473406 progress 30 % (33 MB)
105 20:25:18.267259 progress 35 % (39 MB)
106 20:25:18.612729 progress 40 % (44 MB)
107 20:25:18.974714 progress 45 % (50 MB)
108 20:25:19.620775 progress 50 % (56 MB)
109 20:25:20.420725 progress 55 % (61 MB)
110 20:25:21.139793 progress 60 % (67 MB)
111 20:25:21.845132 progress 65 % (73 MB)
112 20:25:22.597394 progress 70 % (78 MB)
113 20:25:23.346454 progress 75 % (84 MB)
114 20:25:24.070716 progress 80 % (89 MB)
115 20:25:24.770843 progress 85 % (95 MB)
116 20:25:25.547163 progress 90 % (101 MB)
117 20:25:26.290538 progress 95 % (106 MB)
118 20:25:27.102861 progress 100 % (112 MB)
119 20:25:27.116951 112 MB downloaded in 13.97 s (8.04 MB/s)
120 20:25:27.118071 end: 1.4.1 http-download (duration 00:00:14) [common]
122 20:25:27.119914 end: 1.4 download-retry (duration 00:00:14) [common]
123 20:25:27.120511 start: 1.5 download-retry (timeout 00:09:46) [common]
124 20:25:27.121092 start: 1.5.1 http-download (timeout 00:09:46) [common]
125 20:25:27.122053 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-510-gd85128e259496/arm/multi_v7_defconfig/gcc-12/modules.tar.xz
126 20:25:27.122601 saving as /var/lib/lava/dispatcher/tmp/955215/tftp-deploy-b7zdcl50/modules/modules.tar
127 20:25:27.123067 total size: 6610144 (6 MB)
128 20:25:27.123540 Using unxz to decompress xz
129 20:25:27.158162 progress 0 % (0 MB)
130 20:25:27.194239 progress 5 % (0 MB)
131 20:25:27.239212 progress 10 % (0 MB)
132 20:25:27.284970 progress 15 % (0 MB)
133 20:25:27.331772 progress 20 % (1 MB)
134 20:25:27.380809 progress 25 % (1 MB)
135 20:25:27.426161 progress 30 % (1 MB)
136 20:25:27.469795 progress 35 % (2 MB)
137 20:25:27.515395 progress 40 % (2 MB)
138 20:25:27.560806 progress 45 % (2 MB)
139 20:25:27.605705 progress 50 % (3 MB)
140 20:25:27.649011 progress 55 % (3 MB)
141 20:25:27.699649 progress 60 % (3 MB)
142 20:25:27.744234 progress 65 % (4 MB)
143 20:25:27.787566 progress 70 % (4 MB)
144 20:25:27.836857 progress 75 % (4 MB)
145 20:25:27.880227 progress 80 % (5 MB)
146 20:25:27.923469 progress 85 % (5 MB)
147 20:25:27.967246 progress 90 % (5 MB)
148 20:25:28.010734 progress 95 % (6 MB)
149 20:25:28.054869 progress 100 % (6 MB)
150 20:25:28.069023 6 MB downloaded in 0.95 s (6.66 MB/s)
151 20:25:28.069646 end: 1.5.1 http-download (duration 00:00:01) [common]
153 20:25:28.070608 end: 1.5 download-retry (duration 00:00:01) [common]
154 20:25:28.070913 start: 1.6 prepare-tftp-overlay (timeout 00:09:45) [common]
155 20:25:28.071205 start: 1.6.1 extract-nfsrootfs (timeout 00:09:45) [common]
156 20:25:44.249252 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/955215/extract-nfsrootfs-p_uem4hq
157 20:25:44.249890 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
158 20:25:44.250182 start: 1.6.2 lava-overlay (timeout 00:09:29) [common]
159 20:25:44.250821 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i
160 20:25:44.251256 makedir: /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin
161 20:25:44.251618 makedir: /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/tests
162 20:25:44.251937 makedir: /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/results
163 20:25:44.252272 Creating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-add-keys
164 20:25:44.252797 Creating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-add-sources
165 20:25:44.253312 Creating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-background-process-start
166 20:25:44.253805 Creating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-background-process-stop
167 20:25:44.254378 Creating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-common-functions
168 20:25:44.254868 Creating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-echo-ipv4
169 20:25:44.255385 Creating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-install-packages
170 20:25:44.255880 Creating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-installed-packages
171 20:25:44.256348 Creating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-os-build
172 20:25:44.256816 Creating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-probe-channel
173 20:25:44.257279 Creating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-probe-ip
174 20:25:44.257798 Creating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-target-ip
175 20:25:44.258360 Creating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-target-mac
176 20:25:44.258843 Creating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-target-storage
177 20:25:44.259421 Creating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-test-case
178 20:25:44.259929 Creating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-test-event
179 20:25:44.260403 Creating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-test-feedback
180 20:25:44.260868 Creating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-test-raise
181 20:25:44.261336 Creating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-test-reference
182 20:25:44.261859 Creating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-test-runner
183 20:25:44.262415 Creating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-test-set
184 20:25:44.262953 Creating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-test-shell
185 20:25:44.263468 Updating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-add-keys (debian)
186 20:25:44.264009 Updating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-add-sources (debian)
187 20:25:44.264506 Updating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-install-packages (debian)
188 20:25:44.264999 Updating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-installed-packages (debian)
189 20:25:44.265481 Updating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/bin/lava-os-build (debian)
190 20:25:44.265925 Creating /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/environment
191 20:25:44.266302 LAVA metadata
192 20:25:44.266558 - LAVA_JOB_ID=955215
193 20:25:44.266768 - LAVA_DISPATCHER_IP=192.168.6.3
194 20:25:44.267120 start: 1.6.2.1 ssh-authorize (timeout 00:09:29) [common]
195 20:25:44.268039 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
196 20:25:44.268342 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:29) [common]
197 20:25:44.268547 skipped lava-vland-overlay
198 20:25:44.268786 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
199 20:25:44.269035 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:29) [common]
200 20:25:44.269233 skipped lava-multinode-overlay
201 20:25:44.269464 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
202 20:25:44.269709 start: 1.6.2.4 test-definition (timeout 00:09:29) [common]
203 20:25:44.269975 Loading test definitions
204 20:25:44.270247 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:29) [common]
205 20:25:44.270488 Using /lava-955215 at stage 0
206 20:25:44.271536 uuid=955215_1.6.2.4.1 testdef=None
207 20:25:44.271827 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
208 20:25:44.272086 start: 1.6.2.4.2 test-overlay (timeout 00:09:29) [common]
209 20:25:44.273681 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
211 20:25:44.274515 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:29) [common]
212 20:25:44.276449 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
214 20:25:44.277249 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:29) [common]
215 20:25:44.279045 runner path: /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/0/tests/0_timesync-off test_uuid 955215_1.6.2.4.1
216 20:25:44.279577 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
218 20:25:44.280373 start: 1.6.2.4.5 git-repo-action (timeout 00:09:29) [common]
219 20:25:44.280600 Using /lava-955215 at stage 0
220 20:25:44.280948 Fetching tests from https://github.com/kernelci/test-definitions.git
221 20:25:44.281234 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/0/tests/1_kselftest-dt'
222 20:25:48.272505 Running '/usr/bin/git checkout kernelci.org
223 20:25:48.529174 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
224 20:25:48.530662 uuid=955215_1.6.2.4.5 testdef=None
225 20:25:48.531008 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
227 20:25:48.531745 start: 1.6.2.4.6 test-overlay (timeout 00:09:24) [common]
228 20:25:48.534538 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
230 20:25:48.535346 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:24) [common]
231 20:25:48.539026 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
233 20:25:48.539861 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:24) [common]
234 20:25:48.543424 runner path: /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/0/tests/1_kselftest-dt test_uuid 955215_1.6.2.4.5
235 20:25:48.543728 BOARD='beaglebone-black'
236 20:25:48.543935 BRANCH='tip'
237 20:25:48.544130 SKIPFILE='/dev/null'
238 20:25:48.544324 SKIP_INSTALL='True'
239 20:25:48.544516 TESTPROG_URL='http://storage.kernelci.org/tip/master/v6.12-rc6-510-gd85128e259496/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz'
240 20:25:48.544711 TST_CASENAME=''
241 20:25:48.544904 TST_CMDFILES='dt'
242 20:25:48.545426 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
244 20:25:48.546232 Creating lava-test-runner.conf files
245 20:25:48.546435 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/955215/lava-overlay-kfswq14i/lava-955215/0 for stage 0
246 20:25:48.546792 - 0_timesync-off
247 20:25:48.547036 - 1_kselftest-dt
248 20:25:48.547363 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
249 20:25:48.547643 start: 1.6.2.5 compress-overlay (timeout 00:09:24) [common]
250 20:26:12.169783 end: 1.6.2.5 compress-overlay (duration 00:00:24) [common]
251 20:26:12.170388 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:01) [common]
252 20:26:12.170659 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
253 20:26:12.170930 end: 1.6.2 lava-overlay (duration 00:00:28) [common]
254 20:26:12.171193 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:01) [common]
255 20:26:12.526645 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
256 20:26:12.527113 start: 1.6.4 extract-modules (timeout 00:09:00) [common]
257 20:26:12.527362 extracting modules file /var/lib/lava/dispatcher/tmp/955215/tftp-deploy-b7zdcl50/modules/modules.tar to /var/lib/lava/dispatcher/tmp/955215/extract-nfsrootfs-p_uem4hq
258 20:26:13.412813 extracting modules file /var/lib/lava/dispatcher/tmp/955215/tftp-deploy-b7zdcl50/modules/modules.tar to /var/lib/lava/dispatcher/tmp/955215/extract-overlay-ramdisk-drrpuoch/ramdisk
259 20:26:14.326151 end: 1.6.4 extract-modules (duration 00:00:02) [common]
260 20:26:14.326611 start: 1.6.5 apply-overlay-tftp (timeout 00:08:59) [common]
261 20:26:14.326886 [common] Applying overlay to NFS
262 20:26:14.327100 [common] Applying overlay /var/lib/lava/dispatcher/tmp/955215/compress-overlay-7rr_3hrb/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/955215/extract-nfsrootfs-p_uem4hq
263 20:26:17.113603 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
264 20:26:17.114106 start: 1.6.6 prepare-kernel (timeout 00:08:56) [common]
265 20:26:17.114381 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:56) [common]
266 20:26:17.114688 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
267 20:26:17.114947 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
268 20:26:17.115206 start: 1.6.7 configure-preseed-file (timeout 00:08:56) [common]
269 20:26:17.115456 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
270 20:26:17.115711 start: 1.6.8 compress-ramdisk (timeout 00:08:56) [common]
271 20:26:17.115935 Building ramdisk /var/lib/lava/dispatcher/tmp/955215/extract-overlay-ramdisk-drrpuoch/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/955215/extract-overlay-ramdisk-drrpuoch/ramdisk
272 20:26:18.104729 >> 74900 blocks
273 20:26:23.106940 Adding RAMdisk u-boot header.
274 20:26:23.107429 mkimage -A arm -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/955215/extract-overlay-ramdisk-drrpuoch/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/955215/extract-overlay-ramdisk-drrpuoch/ramdisk.cpio.gz.uboot
275 20:26:23.263041 output: Image Name:
276 20:26:23.263436 output: Created: Thu Nov 7 20:26:23 2024
277 20:26:23.263863 output: Image Type: ARM Linux RAMDisk Image (uncompressed)
278 20:26:23.264281 output: Data Size: 14792923 Bytes = 14446.21 KiB = 14.11 MiB
279 20:26:23.264691 output: Load Address: 00000000
280 20:26:23.265091 output: Entry Point: 00000000
281 20:26:23.265490 output:
282 20:26:23.266623 rename /var/lib/lava/dispatcher/tmp/955215/extract-overlay-ramdisk-drrpuoch/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/955215/tftp-deploy-b7zdcl50/ramdisk/ramdisk.cpio.gz.uboot
283 20:26:23.267354 end: 1.6.8 compress-ramdisk (duration 00:00:06) [common]
284 20:26:23.267913 end: 1.6 prepare-tftp-overlay (duration 00:00:55) [common]
285 20:26:23.268458 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:50) [common]
286 20:26:23.268929 No LXC device requested
287 20:26:23.269455 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
288 20:26:23.270088 start: 1.8 deploy-device-env (timeout 00:08:50) [common]
289 20:26:23.270650 end: 1.8 deploy-device-env (duration 00:00:00) [common]
290 20:26:23.271097 Checking files for TFTP limit of 4294967296 bytes.
291 20:26:23.273831 end: 1 tftp-deploy (duration 00:01:10) [common]
292 20:26:23.274430 start: 2 uboot-action (timeout 00:05:00) [common]
293 20:26:23.274970 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
294 20:26:23.275477 end: 2.1 uboot-from-media (duration 00:00:00) [common]
295 20:26:23.275987 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
296 20:26:23.276743 substitutions:
297 20:26:23.277176 - {BOOTX}: bootz 0x82000000 0x83000000 0x88000000
298 20:26:23.277587 - {DTB_ADDR}: 0x88000000
299 20:26:23.278022 - {DTB}: 955215/tftp-deploy-b7zdcl50/dtb/am335x-boneblack.dtb
300 20:26:23.278425 - {INITRD}: 955215/tftp-deploy-b7zdcl50/ramdisk/ramdisk.cpio.gz.uboot
301 20:26:23.278822 - {KERNEL_ADDR}: 0x82000000
302 20:26:23.279235 - {KERNEL}: 955215/tftp-deploy-b7zdcl50/kernel/zImage
303 20:26:23.279639 - {LAVA_MAC}: None
304 20:26:23.280075 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/955215/extract-nfsrootfs-p_uem4hq
305 20:26:23.280490 - {NFS_SERVER_IP}: 192.168.6.3
306 20:26:23.280893 - {PRESEED_CONFIG}: None
307 20:26:23.281286 - {PRESEED_LOCAL}: None
308 20:26:23.281674 - {RAMDISK_ADDR}: 0x83000000
309 20:26:23.282095 - {RAMDISK}: 955215/tftp-deploy-b7zdcl50/ramdisk/ramdisk.cpio.gz.uboot
310 20:26:23.282494 - {ROOT_PART}: None
311 20:26:23.282885 - {ROOT}: None
312 20:26:23.283275 - {SERVER_IP}: 192.168.6.3
313 20:26:23.283661 - {TEE_ADDR}: 0x83000000
314 20:26:23.284044 - {TEE}: None
315 20:26:23.284431 Parsed boot commands:
316 20:26:23.284808 - setenv autoload no
317 20:26:23.285195 - setenv initrd_high 0xffffffff
318 20:26:23.285580 - setenv fdt_high 0xffffffff
319 20:26:23.285994 - dhcp
320 20:26:23.286414 - setenv serverip 192.168.6.3
321 20:26:23.286805 - tftp 0x82000000 955215/tftp-deploy-b7zdcl50/kernel/zImage
322 20:26:23.287196 - tftp 0x83000000 955215/tftp-deploy-b7zdcl50/ramdisk/ramdisk.cpio.gz.uboot
323 20:26:23.287588 - setenv initrd_size ${filesize}
324 20:26:23.287969 - tftp 0x88000000 955215/tftp-deploy-b7zdcl50/dtb/am335x-boneblack.dtb
325 20:26:23.288355 - setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/955215/extract-nfsrootfs-p_uem4hq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
326 20:26:23.288753 - bootz 0x82000000 0x83000000 0x88000000
327 20:26:23.289251 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
329 20:26:23.290787 start: 2.3 connect-device (timeout 00:05:00) [common]
330 20:26:23.291215 [common] connect-device Connecting to device using 'telnet conserv3 3002'
331 20:26:23.305888 Setting prompt string to ['lava-test: # ']
332 20:26:23.307350 end: 2.3 connect-device (duration 00:00:00) [common]
333 20:26:23.307972 start: 2.4 uboot-commands (timeout 00:05:00) [common]
334 20:26:23.308519 start: 2.4.1 reset-device (timeout 00:05:00) [common]
335 20:26:23.309052 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
336 20:26:23.310290 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=beaglebone-black-05'
337 20:26:23.344638 >> OK - accepted request
338 20:26:23.346457 Returned 0 in 0 seconds
339 20:26:23.447572 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
341 20:26:23.448724 end: 2.4.1 reset-device (duration 00:00:00) [common]
342 20:26:23.449091 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
343 20:26:23.449402 Setting prompt string to ['Hit any key to stop autoboot']
344 20:26:23.449692 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
345 20:26:23.451351 Trying 192.168.56.22...
346 20:26:23.451678 Connected to conserv3.
347 20:26:23.451920 Escape character is '^]'.
348 20:26:23.452154
349 20:26:23.452388 ser2net port telnet,3002 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.3:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
350 20:26:23.452643
351 20:26:31.912251
352 20:26:31.918998 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
353 20:26:31.919328 Trying to boot from MMC1
354 20:26:35.966411
355 20:26:35.973419 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
356 20:26:35.974225 Trying to boot from MMC1
357 20:26:38.673212
358 20:26:38.679959 U-Boot SPL 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
359 20:26:38.680255 Trying to boot from MMC1
360 20:26:39.263739
361 20:26:39.264414
362 20:26:39.269204 U-Boot 2023.04-rc1-00202-gce52d133f3 (Feb 06 2023 - 14:59:32 +0000)
363 20:26:39.269768
364 20:26:39.270300 CPU : AM335X-GP rev 2.0
365 20:26:39.274425 Model: TI AM335x BeagleBone Black
366 20:26:39.274999 DRAM: 512 MiB
367 20:26:39.354300 Core: 160 devices, 18 uclasses, devicetree: separate
368 20:26:39.368054 WDT: Started wdt@44e35000 with servicing every 1000ms (60s timeout)
369 20:26:39.768763 NAND: 0 MiB
370 20:26:39.779101 MMC: OMAP SD/MMC: 0, OMAP SD/MMC: 1
371 20:26:39.906737 Loading Environment from FAT... Unable to read "uboot.env" from mmc0:1...
372 20:26:39.927271 <ethaddr> not set. Validating first E-fuse MAC
373 20:26:39.958451 Net: eth2: ethernet@4a100000, eth3: usb_ether
375 20:26:40.016386 Hit any key to stop autoboot: 2
376 20:26:40.017536 end: 2.4.2 bootloader-interrupt (duration 00:00:17) [common]
377 20:26:40.018293 start: 2.4.3 bootloader-commands (timeout 00:04:43) [common]
378 20:26:40.018843 Setting prompt string to ['=>']
379 20:26:40.019382 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:43)
380 20:26:40.027044 0
381 20:26:40.028066 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
382 20:26:40.028624 Sending with 10 millisecond of delay
384 20:26:41.164306 => setenv autoload no
385 20:26:41.175275 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:42)
386 20:26:41.178447 setenv autoload no
387 20:26:41.178913 Sending with 10 millisecond of delay
389 20:26:42.976001 => setenv initrd_high 0xffffffff
390 20:26:42.986801 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
391 20:26:42.987650 setenv initrd_high 0xffffffff
392 20:26:42.988352 Sending with 10 millisecond of delay
394 20:26:44.606025 => setenv fdt_high 0xffffffff
395 20:26:44.616989 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
396 20:26:44.618149 setenv fdt_high 0xffffffff
397 20:26:44.619096 Sending with 10 millisecond of delay
399 20:26:44.911402 => dhcp
400 20:26:44.922261 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:38)
401 20:26:44.923403 dhcp
402 20:26:44.924594 link up on port 0, speed 100, full duplex
403 20:26:44.925270 BOOTP broadcast 1
404 20:26:45.177119 BOOTP broadcast 2
405 20:26:45.679030 BOOTP broadcast 3
406 20:26:46.680938 BOOTP broadcast 4
407 20:26:48.682990 BOOTP broadcast 5
408 20:26:48.766509 DHCP client bound to address 192.168.6.8 (3839 ms)
409 20:26:48.767669 Sending with 10 millisecond of delay
411 20:26:50.445748 => setenv serverip 192.168.6.3
412 20:26:50.456540 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:33)
413 20:26:50.457394 setenv serverip 192.168.6.3
414 20:26:50.458158 Sending with 10 millisecond of delay
416 20:26:53.945656 => tftp 0x82000000 955215/tftp-deploy-b7zdcl50/kernel/zImage
417 20:26:53.956589 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:29)
418 20:26:53.957600 tftp 0x82000000 955215/tftp-deploy-b7zdcl50/kernel/zImage
419 20:26:53.958133 link up on port 0, speed 100, full duplex
420 20:26:53.964253 Using ethernet@4a100000 device
421 20:26:53.966224 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
422 20:26:53.974288 Filename '955215/tftp-deploy-b7zdcl50/kernel/zImage'.
423 20:26:53.974832 Load address: 0x82000000
424 20:26:56.046881 Loading: *################################################## 10.9 MiB
425 20:26:56.047542 5.3 MiB/s
426 20:26:56.048032 done
427 20:26:56.050361 Bytes transferred = 11457024 (aed200 hex)
428 20:26:56.051195 Sending with 10 millisecond of delay
430 20:27:00.499419 => tftp 0x83000000 955215/tftp-deploy-b7zdcl50/ramdisk/ramdisk.cpio.gz.uboot
431 20:27:00.510621 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
432 20:27:00.511594 tftp 0x83000000 955215/tftp-deploy-b7zdcl50/ramdisk/ramdisk.cpio.gz.uboot
433 20:27:00.512082 link up on port 0, speed 100, full duplex
434 20:27:00.515222 Using ethernet@4a100000 device
435 20:27:00.520962 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
436 20:27:00.529398 Filename '955215/tftp-deploy-b7zdcl50/ramdisk/ramdisk.cpio.gz.uboot'.
437 20:27:00.530004 Load address: 0x83000000
438 20:27:03.215703 Loading: *################################################## 14.1 MiB
439 20:27:03.216334 5.3 MiB/s
440 20:27:03.216771 done
441 20:27:03.220017 Bytes transferred = 14792987 (e1b91b hex)
442 20:27:03.220747 Sending with 10 millisecond of delay
444 20:27:05.077399 => setenv initrd_size ${filesize}
445 20:27:05.087943 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
446 20:27:05.088383 setenv initrd_size ${filesize}
447 20:27:05.089119 Sending with 10 millisecond of delay
449 20:27:09.236202 => tftp 0x88000000 955215/tftp-deploy-b7zdcl50/dtb/am335x-boneblack.dtb
450 20:27:09.246972 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:14)
451 20:27:09.247808 tftp 0x88000000 955215/tftp-deploy-b7zdcl50/dtb/am335x-boneblack.dtb
452 20:27:09.248228 link up on port 0, speed 100, full duplex
453 20:27:09.251636 Using ethernet@4a100000 device
454 20:27:09.257135 TFTP from server 192.168.6.3; our IP address is 192.168.6.8
455 20:27:09.268392 Filename '955215/tftp-deploy-b7zdcl50/dtb/am335x-boneblack.dtb'.
456 20:27:09.268822 Load address: 0x88000000
457 20:27:09.279456 Loading: *################################################## 68.9 KiB
458 20:27:09.279878 4.2 MiB/s
459 20:27:09.288025 done
460 20:27:09.288482 Bytes transferred = 70568 (113a8 hex)
461 20:27:09.289136 Sending with 10 millisecond of delay
463 20:27:22.475800 => setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/955215/extract-nfsrootfs-p_uem4hq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
464 20:27:22.486893 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:01)
465 20:27:22.488120 setenv bootargs 'console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/955215/extract-nfsrootfs-p_uem4hq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
466 20:27:22.489041 Sending with 10 millisecond of delay
468 20:27:24.832421 => bootz 0x82000000 0x83000000 0x88000000
469 20:27:24.843066 Setting prompt string to ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
470 20:27:24.844179 bootloader-commands: Wait for prompt ['Starting kernel', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:03:58)
471 20:27:24.845335 bootz 0x82000000 0x83000000 0x88000000
472 20:27:24.845570 Kernel image @ 0x82000000 [ 0x000000 - 0xaed200 ]
473 20:27:24.846376 ## Loading init Ramdisk from Legacy Image at 83000000 ...
474 20:27:24.850579 Image Name:
475 20:27:24.850807 Created: 2024-11-07 20:26:23 UTC
476 20:27:24.856143 Image Type: ARM Linux RAMDisk Image (uncompressed)
477 20:27:24.861780 Data Size: 14792923 Bytes = 14.1 MiB
478 20:27:24.862017 Load Address: 00000000
479 20:27:24.868033 Entry Point: 00000000
480 20:27:25.036298 Verifying Checksum ... OK
481 20:27:25.036811 ## Flattened Device Tree blob at 88000000
482 20:27:25.043010 Booting using the fdt blob at 0x88000000
483 20:27:25.043441 Working FDT set to 88000000
484 20:27:25.048511 Using Device Tree in place at 88000000, end 880143a7
485 20:27:25.053009 Working FDT set to 88000000
486 20:27:25.066513
487 20:27:25.066937 Starting kernel ...
488 20:27:25.067330
489 20:27:25.068177 end: 2.4.3 bootloader-commands (duration 00:00:45) [common]
490 20:27:25.068739 start: 2.4.4 auto-login-action (timeout 00:03:58) [common]
491 20:27:25.069178 Setting prompt string to ['Linux version [0-9]']
492 20:27:25.069610 Setting prompt string to ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
493 20:27:25.070117 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:05:00)
494 20:27:25.907856 [ 0.000000] Booting Linux on physical CPU 0x0
495 20:27:25.913918 start: 2.4.4.1 login-action (timeout 00:03:57) [common]
496 20:27:25.914449 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
497 20:27:25.914911 Setting prompt string to []
498 20:27:25.915400 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
499 20:27:25.915862 Using line separator: #'\n'#
500 20:27:25.916275 No login prompt set.
501 20:27:25.916704 Parsing kernel messages
502 20:27:25.917102 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
503 20:27:25.917916 [login-action] Waiting for messages, (timeout 00:03:57)
504 20:27:25.918370 Waiting using forced prompt support (timeout 00:01:59)
505 20:27:25.930672 [ 0.000000] Linux version 6.12.0-rc6 (KernelCI@build-j367280-arm-gcc-12-multi-v7-defconfig-kmtxg) (arm-linux-gnueabihf-gcc (Debian 12.2.0-14) 12.2.0, GNU ld (GNU Binutils for Debian) 2.40) #1 SMP Thu Nov 7 19:36:57 UTC 2024
506 20:27:25.936390 [ 0.000000] CPU: ARMv7 Processor [413fc082] revision 2 (ARMv7), cr=10c5387d
507 20:27:25.942131 [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
508 20:27:25.953504 [ 0.000000] OF: fdt: Machine model: TI AM335x BeagleBone Black
509 20:27:25.959209 [ 0.000000] earlycon: omap8250 at MMIO 0x44e09000 (options '')
510 20:27:25.965118 [ 0.000000] printk: legacy bootconsole [omap8250] enabled
511 20:27:25.965577 [ 0.000000] Memory policy: Data cache writeback
512 20:27:25.971588 [ 0.000000] efi: UEFI not found.
513 20:27:25.976219 [ 0.000000] cma: Reserved 64 MiB at 0x9b800000 on node -1
514 20:27:25.982828 [ 0.000000] Zone ranges:
515 20:27:25.988623 [ 0.000000] DMA [mem 0x0000000080000000-0x000000009fdfffff]
516 20:27:25.994275 [ 0.000000] Normal empty
517 20:27:25.994719 [ 0.000000] HighMem empty
518 20:27:25.997264 [ 0.000000] Movable zone start for each node
519 20:27:26.002906 [ 0.000000] Early memory node ranges
520 20:27:26.008683 [ 0.000000] node 0: [mem 0x0000000080000000-0x000000009fdfffff]
521 20:27:26.015890 [ 0.000000] Initmem setup node 0 [mem 0x0000000080000000-0x000000009fdfffff]
522 20:27:26.042307 [ 0.000000] CPU: All CPU(s) started in SVC mode.
523 20:27:26.046955 [ 0.000000] AM335X ES2.0 (sgx neon)
524 20:27:26.059649 [ 0.000000] percpu: Embedded 17 pages/cpu s40908 r8192 d20532 u69632
525 20:27:26.077345 [ 0.000000] Kernel command line: console=ttyO0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.3:/var/lib/lava/dispatcher/tmp/955215/extract-nfsrootfs-p_uem4hq,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp
526 20:27:26.088835 <6>[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes, linear)
527 20:27:26.094646 <6>[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes, linear)
528 20:27:26.100437 <6>[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 130560
529 20:27:26.109438 <6>[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
530 20:27:26.139538 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
531 20:27:26.145472 <6>[ 0.000000] trace event string verifier disabled
532 20:27:26.145969 <6>[ 0.000000] rcu: Hierarchical RCU implementation.
533 20:27:26.151191 <6>[ 0.000000] rcu: RCU event tracing is enabled.
534 20:27:26.162622 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=16 to nr_cpu_ids=1.
535 20:27:26.163115 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
536 20:27:26.174242 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 10 jiffies.
537 20:27:26.179985 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=1
538 20:27:26.189754 <6>[ 0.000000] RCU Tasks Trace: Setting shift to 0 and lim to 1 rcu_task_cb_adjust=1 rcu_task_cpu_ids=1.
539 20:27:26.204592 <6>[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
540 20:27:26.222997 <6>[ 0.000000] IRQ: Found an INTC at 0x(ptrval) (revision 5.0) with 128 interrupts
541 20:27:26.228746 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
542 20:27:26.323262 <6>[ 0.000000] TI gptimer clocksource: always-on /ocp/interconnect@44c00000/segment@200000/target-module@31000
543 20:27:26.331899 <6>[ 0.000002] sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 89478484971ns
544 20:27:26.344235 <6>[ 0.008337] clocksource: dmtimer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635851949 ns
545 20:27:26.352203 <6>[ 0.019141] TI gptimer clockevent: 24000000 Hz at /ocp/interconnect@48000000/segment@0/target-module@40000
546 20:27:26.361995 <6>[ 0.033959] Console: colour dummy device 80x30
547 20:27:26.368109 Matched prompt #6: WARNING:
548 20:27:26.368735 Setting prompt string to ['end trace[^\\r]*\\r', '/ #', 'Login timed out', 'Login incorrect']
549 20:27:26.373423 <3>[ 0.038857] WARNING: Your 'console=ttyO0' has been replaced by 'ttyS0'
550 20:27:26.376367 <3>[ 0.045929] This ensures that you still see kernel messages. Please
551 20:27:26.381430 <3>[ 0.052653] update your kernel commandline.
552 20:27:26.423074 <6>[ 0.057267] Calibrating delay loop... 996.14 BogoMIPS (lpj=4980736)
553 20:27:26.428751 <6>[ 0.096141] CPU: Testing write buffer coherency: ok
554 20:27:26.434667 <6>[ 0.101509] CPU0: Spectre v2: using BPIALL workaround
555 20:27:26.435200 <6>[ 0.106975] pid_max: default: 32768 minimum: 301
556 20:27:26.446203 <6>[ 0.112171] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
557 20:27:26.453001 <6>[ 0.119990] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
558 20:27:26.459231 <6>[ 0.129344] CPU0: thread -1, cpu 0, socket -1, mpidr 0
559 20:27:26.520830 <6>[ 0.189660] Setting up static identity map for 0x80300000 - 0x803000ac
560 20:27:26.527322 <6>[ 0.199282] rcu: Hierarchical SRCU implementation.
561 20:27:26.535449 <6>[ 0.204570] rcu: Max phase no-delay instances is 1000.
562 20:27:26.543730 <6>[ 0.215537] EFI services will not be available.
563 20:27:26.549521 <6>[ 0.220885] smp: Bringing up secondary CPUs ...
564 20:27:26.555346 <6>[ 0.225853] smp: Brought up 1 node, 1 CPU
565 20:27:26.561055 <6>[ 0.230340] SMP: Total of 1 processors activated (996.14 BogoMIPS).
566 20:27:26.566982 <6>[ 0.237060] CPU: All CPU(s) started in SVC mode.
567 20:27:26.587346 <6>[ 0.242263] Memory: 405996K/522240K available (16384K kernel code, 2543K rwdata, 6792K rodata, 2048K init, 430K bss, 49052K reserved, 65536K cma-reserved, 0K highmem)
568 20:27:26.588000 <6>[ 0.258540] devtmpfs: initialized
569 20:27:26.609472 <6>[ 0.275501] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3
570 20:27:26.620952 <6>[ 0.284101] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
571 20:27:26.626869 <6>[ 0.294544] futex hash table entries: 256 (order: 2, 16384 bytes, linear)
572 20:27:26.637558 <6>[ 0.306802] pinctrl core: initialized pinctrl subsystem
573 20:27:26.646952 <6>[ 0.317429] DMI not present or invalid.
574 20:27:26.655391 <6>[ 0.323278] NET: Registered PF_NETLINK/PF_ROUTE protocol family
575 20:27:26.664747 <6>[ 0.332279] DMA: preallocated 256 KiB pool for atomic coherent allocations
576 20:27:26.680005 <6>[ 0.343744] thermal_sys: Registered thermal governor 'step_wise'
577 20:27:26.680691 <6>[ 0.343914] cpuidle: using governor menu
578 20:27:26.708245 <6>[ 0.380353] No ATAGs?
579 20:27:26.714449 <6>[ 0.382994] hw-breakpoint: debug architecture 0x4 unsupported.
580 20:27:26.724280 <6>[ 0.394898] Serial: AMBA PL011 UART driver
581 20:27:26.752973 <6>[ 0.424982] iommu: Default domain type: Translated
582 20:27:26.761075 <6>[ 0.430326] iommu: DMA domain TLB invalidation policy: strict mode
583 20:27:26.788892 <5>[ 0.460457] SCSI subsystem initialized
584 20:27:26.804164 <6>[ 0.470572] usbcore: registered new interface driver usbfs
585 20:27:26.810990 <6>[ 0.476532] usbcore: registered new interface driver hub
586 20:27:26.811637 <6>[ 0.482351] usbcore: registered new device driver usb
587 20:27:26.816742 <6>[ 0.488825] pps_core: LinuxPPS API ver. 1 registered
588 20:27:26.828327 <6>[ 0.494259] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
589 20:27:26.837073 <6>[ 0.503974] PTP clock support registered
590 20:27:26.837777 <6>[ 0.508417] EDAC MC: Ver: 3.0.0
591 20:27:26.883462 <6>[ 0.553852] scmi_core: SCMI protocol bus registered
592 20:27:26.908978 <6>[ 0.580398] vgaarb: loaded
593 20:27:26.914073 <6>[ 0.584179] clocksource: Switched to clocksource dmtimer
594 20:27:26.939519 <6>[ 0.611205] NET: Registered PF_INET protocol family
595 20:27:26.952053 <6>[ 0.616905] IP idents hash table entries: 8192 (order: 4, 65536 bytes, linear)
596 20:27:26.959147 <6>[ 0.625747] tcp_listen_portaddr_hash hash table entries: 512 (order: 0, 4096 bytes, linear)
597 20:27:26.970581 <6>[ 0.634670] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
598 20:27:26.976428 <6>[ 0.642910] TCP established hash table entries: 4096 (order: 2, 16384 bytes, linear)
599 20:27:26.982304 <6>[ 0.651198] TCP bind hash table entries: 4096 (order: 4, 65536 bytes, linear)
600 20:27:26.988145 <6>[ 0.658912] TCP: Hash tables configured (established 4096 bind 4096)
601 20:27:26.999643 <6>[ 0.665847] UDP hash table entries: 256 (order: 1, 8192 bytes, linear)
602 20:27:27.005459 <6>[ 0.672859] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes, linear)
603 20:27:27.010751 <6>[ 0.680465] NET: Registered PF_UNIX/PF_LOCAL protocol family
604 20:27:27.097646 <6>[ 0.764113] RPC: Registered named UNIX socket transport module.
605 20:27:27.098344 <6>[ 0.770537] RPC: Registered udp transport module.
606 20:27:27.103382 <6>[ 0.775668] RPC: Registered tcp transport module.
607 20:27:27.109133 <6>[ 0.780774] RPC: Registered tcp-with-tls transport module.
608 20:27:27.122158 <6>[ 0.786694] RPC: Registered tcp NFSv4.1 backchannel transport module.
609 20:27:27.122774 <6>[ 0.793601] PCI: CLS 0 bytes, default 64
610 20:27:27.128537 <5>[ 0.799416] Initialise system trusted keyrings
611 20:27:27.149480 <6>[ 0.819519] Trying to unpack rootfs image as initramfs...
612 20:27:27.228992 <6>[ 0.894749] workingset: timestamp_bits=30 max_order=17 bucket_order=0
613 20:27:27.233687 <6>[ 0.902256] squashfs: version 4.0 (2009/01/31) Phillip Lougher
614 20:27:27.273112 <5>[ 0.945100] NFS: Registering the id_resolver key type
615 20:27:27.278897 <5>[ 0.950702] Key type id_resolver registered
616 20:27:27.284690 <5>[ 0.955386] Key type id_legacy registered
617 20:27:27.293187 <6>[ 0.959829] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
618 20:27:27.300098 <6>[ 0.967031] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
619 20:27:27.372888 <5>[ 1.044957] Key type asymmetric registered
620 20:27:27.378762 <5>[ 1.049482] Asymmetric key parser 'x509' registered
621 20:27:27.387213 <6>[ 1.054957] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 246)
622 20:27:27.392928 <6>[ 1.062840] io scheduler mq-deadline registered
623 20:27:27.401771 <6>[ 1.067819] io scheduler kyber registered
624 20:27:27.402438 <6>[ 1.072271] io scheduler bfq registered
625 20:27:27.506678 <6>[ 1.175072] ledtrig-cpu: registered to indicate activity on CPUs
626 20:27:27.798489 <6>[ 1.466754] Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled
627 20:27:27.838107 <6>[ 1.509762] msm_serial: driver initialized
628 20:27:27.843935 <6>[ 1.514810] SuperH (H)SCI(F) driver initialized
629 20:27:27.849942 <6>[ 1.519930] STMicroelectronics ASC driver initialized
630 20:27:27.855101 <6>[ 1.525613] STM32 USART driver initialized
631 20:27:27.974498 <6>[ 1.645945] brd: module loaded
632 20:27:28.005601 <6>[ 1.677024] loop: module loaded
633 20:27:28.040889 <6>[ 1.712047] CAN device driver interface
634 20:27:28.047602 <6>[ 1.717360] bgmac_bcma: Broadcom 47xx GBit MAC driver loaded
635 20:27:28.053409 <6>[ 1.724464] e1000e: Intel(R) PRO/1000 Network Driver
636 20:27:28.059948 <6>[ 1.729850] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
637 20:27:28.065676 <6>[ 1.736295] igb: Intel(R) Gigabit Ethernet Network Driver
638 20:27:28.073126 <6>[ 1.742115] igb: Copyright (c) 2007-2014 Intel Corporation.
639 20:27:28.084944 <6>[ 1.751304] pegasus: Pegasus/Pegasus II USB Ethernet driver
640 20:27:28.090734 <6>[ 1.757453] usbcore: registered new interface driver pegasus
641 20:27:28.096606 <6>[ 1.763575] usbcore: registered new interface driver asix
642 20:27:28.102328 <6>[ 1.769475] usbcore: registered new interface driver ax88179_178a
643 20:27:28.108061 <6>[ 1.776072] usbcore: registered new interface driver cdc_ether
644 20:27:28.113920 <6>[ 1.782378] usbcore: registered new interface driver smsc75xx
645 20:27:28.119700 <6>[ 1.788613] usbcore: registered new interface driver smsc95xx
646 20:27:28.125526 <6>[ 1.794848] usbcore: registered new interface driver net1080
647 20:27:28.131234 <6>[ 1.800967] usbcore: registered new interface driver cdc_subset
648 20:27:28.136973 <6>[ 1.807375] usbcore: registered new interface driver zaurus
649 20:27:28.144589 <6>[ 1.813419] usbcore: registered new interface driver cdc_ncm
650 20:27:28.154394 <6>[ 1.822848] usbcore: registered new interface driver usb-storage
651 20:27:28.163834 <6>[ 1.834000] i2c_dev: i2c /dev entries driver
652 20:27:28.188488 <5>[ 1.852647] cpuidle: enable-method property 'ti,am3352' found operations
653 20:27:28.194396 <6>[ 1.862192] sdhci: Secure Digital Host Controller Interface driver
654 20:27:28.202285 <6>[ 1.868942] sdhci: Copyright(c) Pierre Ossman
655 20:27:28.209540 <6>[ 1.875543] Synopsys Designware Multimedia Card Interface Driver
656 20:27:28.214594 <6>[ 1.883410] sdhci-pltfm: SDHCI platform and OF driver helper
657 20:27:28.228884 <6>[ 1.893488] usbcore: registered new interface driver usbhid
658 20:27:28.229442 <6>[ 1.899600] usbhid: USB HID core driver
659 20:27:28.240999 <6>[ 1.911411] NET: Registered PF_INET6 protocol family
660 20:27:28.684031 <6>[ 2.356198] Segment Routing with IPv6
661 20:27:28.689932 <6>[ 2.360348] In-situ OAM (IOAM) with IPv6
662 20:27:28.696538 <6>[ 2.364871] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
663 20:27:28.703972 <6>[ 2.372143] NET: Registered PF_PACKET protocol family
664 20:27:28.709887 <6>[ 2.377700] can: controller area network core
665 20:27:28.710392 <6>[ 2.382527] NET: Registered PF_CAN protocol family
666 20:27:28.715560 <6>[ 2.387760] can: raw protocol
667 20:27:28.721364 <6>[ 2.391085] can: broadcast manager protocol
668 20:27:28.728252 <6>[ 2.395693] can: netlink gateway - max_hops=1
669 20:27:28.728757 <5>[ 2.401175] Key type dns_resolver registered
670 20:27:28.733991 <6>[ 2.406252] ThumbEE CPU extension supported.
671 20:27:28.740236 <5>[ 2.410943] Registering SWP/SWPB emulation handler
672 20:27:28.747487 <3>[ 2.416640] omap_voltage_late_init: Voltage driver support not added
673 20:27:28.955397 <5>[ 2.625142] Loading compiled-in X.509 certificates
674 20:27:29.088586 <6>[ 2.747673] platform 44e10800.pinmux: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800/clkout2-pins
675 20:27:29.095753 <6>[ 2.764415] pinctrl-single 44e10800.pinmux: 142 pins, size 568
676 20:27:29.121904 <3>[ 2.788017] ti-sysc 44e31000.target-module: probe with driver ti-sysc failed with error -16
677 20:27:29.332337 <3>[ 2.998416] ti-sysc 48040000.target-module: probe with driver ti-sysc failed with error -16
678 20:27:29.514426 <6>[ 3.184806] OMAP GPIO hardware version 0.1
679 20:27:29.534890 <6>[ 3.203375] omap-mailbox 480c8000.mailbox: omap mailbox rev 0x400
680 20:27:29.626757 <4>[ 3.295871] at24 2-0054: supply vcc not found, using dummy regulator
681 20:27:29.661911 <4>[ 3.330082] at24 2-0055: supply vcc not found, using dummy regulator
682 20:27:29.727197 <4>[ 3.395421] at24 2-0056: supply vcc not found, using dummy regulator
683 20:27:29.760413 <4>[ 3.428618] at24 2-0057: supply vcc not found, using dummy regulator
684 20:27:29.800128 <6>[ 3.469202] omap_i2c 4819c000.i2c: bus 2 rev0.11 at 100 kHz
685 20:27:29.872124 <3>[ 3.536971] 48000000.interconnect:segment@200000:target-module@0:mpu@0:fck: device ID is greater than 24
686 20:27:29.896469 <6>[ 3.557817] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
687 20:27:29.916937 <4>[ 3.583882] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
688 20:27:29.937829 <4>[ 3.604797] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
689 20:27:30.070173 <6>[ 3.738443] omap_rng 48310000.rng: Random Number Generator ver. 20
690 20:27:30.093664 <5>[ 3.764727] random: crng init done
691 20:27:30.148292 <6>[ 3.815194] davinci_mdio 4a101000.mdio: davinci mdio revision 1.6, bus freq 1000000
692 20:27:30.185805 <6>[ 3.856326] Freeing initrd memory: 14448K
693 20:27:30.230668 <6>[ 3.896631] davinci_mdio 4a101000.mdio: phy[0]: device 4a101000.mdio:00, driver SMSC LAN8710/LAN8720
694 20:27:30.236432 <6>[ 3.906968] cpsw-switch 4a100000.switch: initialized cpsw ale version 1.4
695 20:27:30.248191 <6>[ 3.914331] cpsw-switch 4a100000.switch: ALE Table size 1024, Policers 0
696 20:27:30.254060 <6>[ 3.921825] cpsw-switch 4a100000.switch: cpts: overflow check period 500 (jiffies)
697 20:27:30.265664 <6>[ 3.929961] cpsw-switch 4a100000.switch: CPTS: ref_clk_freq:250000000 calc_mult:2147483648 calc_shift:29 error:0 nsec/sec
698 20:27:30.272969 <6>[ 3.941587] cpsw-switch 4a100000.switch: Detected MACID = 90:59:af:5b:00:92
699 20:27:30.286072 <5>[ 3.950609] cpsw-switch 4a100000.switch: initialized (regs 0x4a100000, pool size 256) hw_ver:0019010C 1.12 (0)
700 20:27:30.313856 <3>[ 3.980336] debugfs: Directory '49000000.dma' with parent 'dmaengine' already present!
701 20:27:30.319572 <6>[ 3.988925] edma 49000000.dma: TI EDMA DMA engine driver
702 20:27:30.390340 <3>[ 4.056163] target-module@4b000000:target-module@140000:pmu@0:fck: device ID is greater than 24
703 20:27:30.404990 <6>[ 4.070469] hw perfevents: enabled with armv7_cortex_a8 PMU driver, 5 (8000000f) counters available
704 20:27:30.417933 <3>[ 4.087548] l3-aon-clkctrl:0000:0: failed to disable
705 20:27:30.466311 <6>[ 4.132780] 44e09000.serial: ttyS0 at MMIO 0x44e09000 (irq = 36, base_baud = 3000000) is a 8250
706 20:27:30.472034 <6>[ 4.142290] printk: legacy console [ttyS0] enabled
707 20:27:30.477741 <6>[ 4.142290] printk: legacy console [ttyS0] enabled
708 20:27:30.483380 <6>[ 4.152631] printk: legacy bootconsole [omap8250] disabled
709 20:27:30.489240 <6>[ 4.152631] printk: legacy bootconsole [omap8250] disabled
710 20:27:30.529459 <4>[ 4.194946] tps65217-pmic: Failed to locate of_node [id: -1]
711 20:27:30.533045 <4>[ 4.202337] tps65217-bl: Failed to locate of_node [id: -1]
712 20:27:30.549540 <6>[ 4.221957] tps65217 0-0024: TPS65217 ID 0xe version 1.2
713 20:27:30.570036 <6>[ 4.228884] platform 4830e000.lcdc: Fixed dependency cycle(s) with /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
714 20:27:30.581675 <6>[ 4.242581] i2c 0-0070: Fixed dependency cycle(s) with /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
715 20:27:30.584374 <6>[ 4.254493] omap_i2c 44e0b000.i2c: bus 0 rev0.11 at 400 kHz
716 20:27:30.607507 <6>[ 4.274296] omap_gpio 44e07000.gpio: Could not set line 6 debounce to 200000 microseconds (-22)
717 20:27:30.613354 <6>[ 4.283352] sdhci-omap 48060000.mmc: Got CD GPIO
718 20:27:30.621394 <4>[ 4.288508] sdhci-omap 48060000.mmc: supply pbias not found, using dummy regulator
719 20:27:30.636066 <4>[ 4.302151] sdhci-omap 48060000.mmc: supply vqmmc not found, using dummy regulator
720 20:27:30.642458 <4>[ 4.310800] sdhci-omap 481d8000.mmc: supply pbias not found, using dummy regulator
721 20:27:30.652351 <4>[ 4.319451] sdhci-omap 481d8000.mmc: supply vqmmc not found, using dummy regulator
722 20:27:30.775897 <6>[ 4.443748] at24 0-0050: 32768 byte 24c256 EEPROM, writable, 1 bytes/write
723 20:27:30.825874 <6>[ 4.490539] mmc1: SDHCI controller on 481d8000.mmc [481d8000.mmc] using External DMA
724 20:27:30.832356 <6>[ 4.500720] mmc0: SDHCI controller on 48060000.mmc [48060000.mmc] using External DMA
725 20:27:30.841624 <6>[ 4.509790] cpsw-switch 4a100000.switch: starting ndev. mode: dual_mac
726 20:27:30.910957 <6>[ 4.572309] mmc1: new high speed MMC card at address 0001
727 20:27:30.911555 <6>[ 4.581034] mmcblk1: mmc1:0001 MMC02G 1.79 GiB
728 20:27:30.928117 <6>[ 4.593272] SMSC LAN8710/LAN8720 4a101000.mdio:00: attached PHY driver (mii_bus:phy_addr=4a101000.mdio:00, irq=POLL)
729 20:27:30.936158 <6>[ 4.605860] mmcblk1boot0: mmc1:0001 MMC02G 1.00 MiB
730 20:27:30.952050 <6>[ 4.621656] mmcblk1boot1: mmc1:0001 MMC02G 1.00 MiB
731 20:27:30.968210 <6>[ 4.630457] mmc0: new high speed SDHC card at address aaaa
732 20:27:30.968769 <6>[ 4.638532] mmcblk0: mmc0:aaaa SU16G 14.8 GiB
733 20:27:30.976930 <6>[ 4.645329] mmcblk1rpmb: mmc1:0001 MMC02G 128 KiB, chardev (236:0)
734 20:27:30.998370 <6>[ 4.668611] mmcblk0: p1 p2 p3 p4 < p5 p6 p7 >
735 20:27:33.088882 <6>[ 6.755227] cpsw-switch 4a100000.switch eth0: Link is Up - 100Mbps/Full - flow control off
736 20:27:33.202322 <5>[ 6.794273] Sending DHCP requests ., OK
737 20:27:33.213613 <6>[ 6.878735] IP-Config: Got DHCP answer from 192.168.6.1, my address is 192.168.6.8
738 20:27:33.214160 <6>[ 6.886805] IP-Config: Complete:
739 20:27:33.228062 <6>[ 6.890343] device=eth0, hwaddr=90:59:af:5b:00:92, ipaddr=192.168.6.8, mask=255.255.255.0, gw=192.168.6.1
740 20:27:33.233666 <6>[ 6.900779] host=192.168.6.8, domain=, nis-domain=(none)
741 20:27:33.239398 <6>[ 6.906906] bootserver=192.168.6.1, rootserver=192.168.6.3, rootpath=
742 20:27:33.246582 <6>[ 6.906940] nameserver0=10.255.253.1
743 20:27:33.247058 <6>[ 6.919563] clk: Disabling unused clocks
744 20:27:33.254556 <6>[ 6.924291] PM: genpd: Disabling unused power domains
745 20:27:33.274495 <6>[ 6.943282] Freeing unused kernel image (initmem) memory: 2048K
746 20:27:33.281884 <6>[ 6.952978] Run /init as init process
747 20:27:33.306728 Loading, please wait...
748 20:27:33.382419 Starting systemd-udevd version 252.22-1~deb12u1
749 20:27:36.350794 <4>[ 10.015949] am335x-phy-driver 47401300.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
750 20:27:36.566338 <4>[ 10.231468] am335x-phy-driver 47401b00.usb-phy: dummy supplies not allowed for exclusive requests (id=vbus)
751 20:27:36.722070 <6>[ 10.394650] musb-hdrc musb-hdrc.1: MUSB HDRC host driver
752 20:27:36.732727 <6>[ 10.400325] musb-hdrc musb-hdrc.1: new USB bus registered, assigned bus number 1
753 20:27:36.959438 <6>[ 10.630505] hub 1-0:1.0: USB hub found
754 20:27:37.053223 <6>[ 10.724399] hub 1-0:1.0: 1 port detected
755 20:27:37.078299 <6>[ 10.749147] tda998x 0-0070: found TDA19988
756 20:27:40.263462 Begin: Loading essential drivers ... done.
757 20:27:40.268769 Begin: Running /scripts/init-premount ... done.
758 20:27:40.274245 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
759 20:27:40.282154 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
760 20:27:40.288111 Device /sys/class/net/eth0 found
761 20:27:40.288611 done.
762 20:27:40.364260 Begin: Waiting up to 180 secs for any network device to become available ... done.
763 20:27:40.434892 IP-Config: eth0 hardware address 90:59:af:5b:00:92 mtu 1500 DHCP
764 20:27:40.574450 IP-Config: eth0 guessed broadcast address 192.168.6.255
765 20:27:40.580035 IP-Config: eth0 complete (dhcp from 192.168.6.1):
766 20:27:40.585506 address: 192.168.6.8 broadcast: 192.168.6.255 netmask: 255.255.255.0
767 20:27:40.596826 gateway: 192.168.6.1 dns0 : 10.255.253.1 dns1 : 0.0.0.0
768 20:27:40.597348 rootserver: 192.168.6.1 rootpath:
769 20:27:40.599805 filename :
770 20:27:40.685996 done.
771 20:27:40.697755 Begin: Running /scripts/nfs-bottom ... done.
772 20:27:40.765886 Begin: Running /scripts/init-bottom ... done.
773 20:27:42.360584 <30>[ 16.029013] systemd[1]: System time before build time, advancing clock.
774 20:27:42.578577 <30>[ 16.220634] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
775 20:27:42.587352 <30>[ 16.257524] systemd[1]: Detected architecture arm.
776 20:27:42.599355
777 20:27:42.599884 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
778 20:27:42.600353
779 20:27:42.625792 <30>[ 16.294749] systemd[1]: Hostname set to <debian-bookworm-armhf>.
780 20:27:44.762344 <30>[ 18.430313] systemd[1]: Queued start job for default target graphical.target.
781 20:27:44.779742 <30>[ 18.445516] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
782 20:27:44.787244 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
783 20:27:44.811054 <30>[ 18.477145] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
784 20:27:44.819634 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
785 20:27:44.841717 <30>[ 18.507530] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
786 20:27:44.849708 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
787 20:27:44.869790 <30>[ 18.536157] systemd[1]: Created slice user.slice - User and Session Slice.
788 20:27:44.876517 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
789 20:27:44.904890 <30>[ 18.565583] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
790 20:27:44.910976 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
791 20:27:44.928856 <30>[ 18.595307] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
792 20:27:44.939920 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
793 20:27:44.967602 <30>[ 18.625393] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
794 20:27:44.980477 <30>[ 18.646315] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
795 20:27:44.986073 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
796 20:27:45.007979 <30>[ 18.674696] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
797 20:27:45.016303 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
798 20:27:45.038689 <30>[ 18.705060] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
799 20:27:45.047205 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
800 20:27:45.068655 <30>[ 18.735255] systemd[1]: Reached target paths.target - Path Units.
801 20:27:45.073747 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
802 20:27:45.098160 <30>[ 18.764852] systemd[1]: Reached target remote-fs.target - Remote File Systems.
803 20:27:45.105585 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
804 20:27:45.128041 <30>[ 18.794752] systemd[1]: Reached target slices.target - Slice Units.
805 20:27:45.133549 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
806 20:27:45.158242 <30>[ 18.824920] systemd[1]: Reached target swap.target - Swaps.
807 20:27:45.162304 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
808 20:27:45.188487 <30>[ 18.854986] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
809 20:27:45.196433 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
810 20:27:45.219625 <30>[ 18.885912] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
811 20:27:45.227782 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
812 20:27:45.307041 <30>[ 18.968678] systemd[1]: systemd-journald-audit.socket - Journal Audit Socket was skipped because of an unmet condition check (ConditionSecurity=audit).
813 20:27:45.319752 <30>[ 18.986194] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
814 20:27:45.328161 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
815 20:27:45.351859 <30>[ 19.016985] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
816 20:27:45.358880 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
817 20:27:45.380849 <30>[ 19.047264] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
818 20:27:45.389055 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
819 20:27:45.414262 <30>[ 19.079404] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
820 20:27:45.419871 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
821 20:27:45.447795 <30>[ 19.115901] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
822 20:27:45.459310 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
823 20:27:45.485613 <30>[ 19.145951] systemd[1]: dev-hugepages.mount - Huge Pages File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/mm/hugepages).
824 20:27:45.503542 <30>[ 19.164616] systemd[1]: dev-mqueue.mount - POSIX Message Queue File System was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/mqueue).
825 20:27:45.548386 <30>[ 19.214883] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
826 20:27:45.555891 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
827 20:27:45.589451 <30>[ 19.256589] systemd[1]: Mounting sys-kernel-tracing.mount - Kernel Trace File System...
828 20:27:45.615637 Mounting [0;1;39msys-kernel-tracin…[0m - Kernel Trace File System...
829 20:27:45.682619 <30>[ 19.348786] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
830 20:27:45.696589 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
831 20:27:45.738919 <30>[ 19.405799] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
832 20:27:45.760225 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
833 20:27:45.818815 <30>[ 19.486049] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
834 20:27:45.838655 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
835 20:27:45.898150 <30>[ 19.565758] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
836 20:27:45.915538 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
837 20:27:45.981131 <30>[ 19.647499] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
838 20:27:46.008701 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
839 20:27:46.060100 <30>[ 19.727576] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
840 20:27:46.088382 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
841 20:27:46.139942 <30>[ 19.807341] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
842 20:27:46.165452 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
843 20:27:46.195948 <28>[ 19.856535] systemd[1]: systemd-journald.service: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling.
844 20:27:46.204474 <28>[ 19.871182] systemd[1]: (This warning is only shown for the first unit using IP firewalling.)
845 20:27:46.257626 <30>[ 19.925642] systemd[1]: Starting systemd-journald.service - Journal Service...
846 20:27:46.276912 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
847 20:27:46.348393 <30>[ 20.015687] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
848 20:27:46.361081 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
849 20:27:46.390018 <30>[ 20.057458] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
850 20:27:46.440797 Starting [0;1;39msystemd-network-g… units from Kernel command line...
851 20:27:46.503606 <30>[ 20.169544] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
852 20:27:46.558020 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
853 20:27:46.643392 <30>[ 20.310129] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
854 20:27:46.697755 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
855 20:27:46.765434 <30>[ 20.433091] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
856 20:27:46.807993 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
857 20:27:46.820829 <30>[ 20.488327] systemd[1]: Mounted sys-kernel-tracing.mount - Kernel Trace File System.
858 20:27:46.863805 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-tracing…nt[0m - Kernel Trace File System.
859 20:27:46.883040 <30>[ 20.549366] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
860 20:27:46.904425 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
861 20:27:47.038998 <30>[ 20.707115] systemd[1]: modprobe@configfs.service: Deactivated successfully.
862 20:27:47.069081 <30>[ 20.736117] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
863 20:27:47.097845 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
864 20:27:47.108584 <30>[ 20.776987] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
865 20:27:47.138599 <30>[ 20.806063] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
866 20:27:47.167916 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
867 20:27:47.178462 <30>[ 20.847018] systemd[1]: modprobe@drm.service: Deactivated successfully.
868 20:27:47.208155 <30>[ 20.876019] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
869 20:27:47.237101 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
870 20:27:47.259229 <30>[ 20.925989] systemd[1]: Started systemd-journald.service - Journal Service.
871 20:27:47.266141 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
872 20:27:47.300301 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
873 20:27:47.328366 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
874 20:27:47.359422 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
875 20:27:47.380839 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
876 20:27:47.408326 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
877 20:27:47.430539 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
878 20:27:47.458157 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
879 20:27:47.517650 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
880 20:27:47.562126 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
881 20:27:47.641039 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
882 20:27:47.741856 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
883 20:27:47.807216 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
884 20:27:47.920027 <46>[ 21.587408] systemd-journald[165]: Received client request to flush runtime journal.
885 20:27:47.943029 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
886 20:27:48.056230 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
887 20:27:48.912119 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
888 20:27:49.247678 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
889 20:27:49.308120 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
890 20:27:49.633511 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
891 20:27:49.859639 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
892 20:27:49.879739 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
893 20:27:49.913795 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
894 20:27:50.001776 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
895 20:27:50.043987 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
896 20:27:50.990002 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
897 20:27:51.059100 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
898 20:27:51.154206 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
899 20:27:51.237908 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
900 20:27:51.278165 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
901 20:27:52.398054 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
902 20:27:53.875191 <5>[ 27.542882] cfg80211: Loading compiled-in X.509 certificates for regulatory database
903 20:27:53.928686 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
904 20:27:54.557666 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
905 20:27:54.954148 <5>[ 28.623860] Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
906 20:27:55.025158 <5>[ 28.690690] Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
907 20:27:55.030518 <4>[ 28.700028] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
908 20:27:55.038340 <6>[ 28.709123] cfg80211: failed to load regulatory.db
909 20:27:55.651876 <46>[ 29.310460] systemd-journald[165]: Oldest entry in /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal is older than the configured file retention duration (1month), suggesting rotation.
910 20:27:55.693052 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
911 20:27:55.897001 <46>[ 29.557539] systemd-journald[165]: /var/log/journal/658c871cd7314ccea6115dc5728f8992/system.journal: Journal header limits reached or header out-of-date, rotating.
912 20:27:56.683614 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
913 20:28:05.517743 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
914 20:28:05.537540 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
915 20:28:05.561862 [[0;32m OK [0m] Reached target [0;1;39musb-gadget.…m - Hardware activated USB gadget.
916 20:28:05.594890 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
917 20:28:05.658289 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
918 20:28:05.699520 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
919 20:28:05.762433 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
920 20:28:05.812931 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
921 20:28:05.864134 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
922 20:28:05.888708 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
923 20:28:05.913010 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
924 20:28:05.954594 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
925 20:28:05.981066 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
926 20:28:06.028402 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
927 20:28:06.054976 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
928 20:28:06.079384 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
929 20:28:06.103634 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
930 20:28:06.147460 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
931 20:28:06.168898 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
932 20:28:06.187023 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
933 20:28:06.218510 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
934 20:28:06.237150 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
935 20:28:06.260789 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
936 20:28:06.337518 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
937 20:28:06.372874 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
938 20:28:06.449437 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
939 20:28:06.538568 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
940 20:28:06.618515 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
941 20:28:06.660394 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
942 20:28:06.679555 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
943 20:28:06.863041 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
944 20:28:06.927927 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
945 20:28:06.999381 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
946 20:28:07.026976 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
947 20:28:07.049021 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
948 20:28:07.274459 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
949 20:28:07.657684 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
950 20:28:07.698638 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
951 20:28:07.722319 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
952 20:28:07.815632 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
953 20:28:07.983892 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
954 20:28:08.118189
955 20:28:08.118804 Debian GNU/Linux 12worm-armhf login: root (automatic login)
956 20:28:08.121585
957 20:28:08.414195 Linux debian-bookworm-armhf 6.12.0-rc6 #1 SMP Thu Nov 7 19:36:57 UTC 2024 armv7l
958 20:28:08.414833
959 20:28:08.420036 The programs included with the Debian GNU/Linux system are free software;
960 20:28:08.423253 the exact distribution terms for each program are described in the
961 20:28:08.429002 individual files in /usr/share/doc/*/copyright.
962 20:28:08.429642
963 20:28:08.434424 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
964 20:28:08.439093 permitted by applicable law.
965 20:28:13.475534 Unable to match end of the kernel message
967 20:28:13.477171 Setting prompt string to ['/ #']
968 20:28:13.477784 end: 2.4.4.1 login-action (duration 00:00:48) [common]
970 20:28:13.479352 end: 2.4.4 auto-login-action (duration 00:00:48) [common]
971 20:28:13.479931 start: 2.4.5 expect-shell-connection (timeout 00:03:10) [common]
972 20:28:13.480410 Setting prompt string to ['/ #']
973 20:28:13.480852 Forcing a shell prompt, looking for ['/ #']
975 20:28:13.531898 / #
976 20:28:13.532729 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
977 20:28:13.533289 Waiting using forced prompt support (timeout 00:02:30)
978 20:28:13.537292
979 20:28:13.548716 end: 2.4.5 expect-shell-connection (duration 00:00:00) [common]
980 20:28:13.549420 start: 2.4.6 export-device-env (timeout 00:03:10) [common]
981 20:28:13.550009 Sending with 10 millisecond of delay
983 20:28:18.542280 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/955215/extract-nfsrootfs-p_uem4hq'
984 20:28:18.553009 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/955215/extract-nfsrootfs-p_uem4hq'
985 20:28:18.553873 Sending with 10 millisecond of delay
987 20:28:20.654265 / # export NFS_SERVER_IP='192.168.6.3'
988 20:28:20.665261 export NFS_SERVER_IP='192.168.6.3'
989 20:28:20.666279 end: 2.4.6 export-device-env (duration 00:00:07) [common]
990 20:28:20.666945 end: 2.4 uboot-commands (duration 00:01:57) [common]
991 20:28:20.667591 end: 2 uboot-action (duration 00:01:57) [common]
992 20:28:20.668318 start: 3 lava-test-retry (timeout 00:06:52) [common]
993 20:28:20.669048 start: 3.1 lava-test-shell (timeout 00:06:52) [common]
994 20:28:20.669801 Using namespace: common
996 20:28:20.771344 / # #
997 20:28:20.772159 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
998 20:28:20.777034 #
999 20:28:20.784858 Using /lava-955215
1001 20:28:20.886268 / # export SHELL=/bin/bash
1002 20:28:20.891996 export SHELL=/bin/bash
1004 20:28:21.002394 / # . /lava-955215/environment
1005 20:28:21.007890 . /lava-955215/environment
1007 20:28:21.122173 / # /lava-955215/bin/lava-test-runner /lava-955215/0
1008 20:28:21.123270 Test shell timeout: 10s (minimum of the action and connection timeout)
1009 20:28:21.128213 /lava-955215/bin/lava-test-runner /lava-955215/0
1010 20:28:21.502600 + export TESTRUN_ID=0_timesync-off
1011 20:28:21.509592 + TESTRUN_ID=0_timesync-off
1012 20:28:21.510147 + cd /lava-955215/0/tests/0_timesync-off
1013 20:28:21.510573 ++ cat uuid
1014 20:28:21.526339 + UUID=955215_1.6.2.4.1
1015 20:28:21.526877 + set +x
1016 20:28:21.534718 <LAVA_SIGNAL_STARTRUN 0_timesync-off 955215_1.6.2.4.1>
1017 20:28:21.535225 + systemctl stop systemd-timesyncd
1018 20:28:21.535933 Received signal: <STARTRUN> 0_timesync-off 955215_1.6.2.4.1
1019 20:28:21.536370 Starting test lava.0_timesync-off (955215_1.6.2.4.1)
1020 20:28:21.536880 Skipping test definition patterns.
1021 20:28:21.822615 + set +x
1022 20:28:21.823206 <LAVA_SIGNAL_ENDRUN 0_timesync-off 955215_1.6.2.4.1>
1023 20:28:21.823911 Received signal: <ENDRUN> 0_timesync-off 955215_1.6.2.4.1
1024 20:28:21.824411 Ending use of test pattern.
1025 20:28:21.824809 Ending test lava.0_timesync-off (955215_1.6.2.4.1), duration 0.29
1027 20:28:22.012603 + export TESTRUN_ID=1_kselftest-dt
1028 20:28:22.020684 + TESTRUN_ID=1_kselftest-dt
1029 20:28:22.021194 + cd /lava-955215/0/tests/1_kselftest-dt
1030 20:28:22.021626 ++ cat uuid
1031 20:28:22.036190 + UUID=955215_1.6.2.4.5
1032 20:28:22.036560 + set +x
1033 20:28:22.041681 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 955215_1.6.2.4.5>
1034 20:28:22.042029 + cd ./automated/linux/kselftest/
1035 20:28:22.042510 Received signal: <STARTRUN> 1_kselftest-dt 955215_1.6.2.4.5
1036 20:28:22.042792 Starting test lava.1_kselftest-dt (955215_1.6.2.4.5)
1037 20:28:22.043082 Skipping test definition patterns.
1038 20:28:22.069152 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/tip/master/v6.12-rc6-510-gd85128e259496/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz -L '' -S /dev/null -b beaglebone-black -g tip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1 -E ''
1039 20:28:22.168779 INFO: install_deps skipped
1040 20:28:22.714294 --2024-11-07 20:28:22-- http://storage.kernelci.org/tip/master/v6.12-rc6-510-gd85128e259496/arm/multi_v7_defconfig/gcc-12/kselftest.tar.xz
1041 20:28:22.741471 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
1042 20:28:22.883640 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
1043 20:28:23.023961 HTTP request sent, awaiting response... 200 OK
1044 20:28:23.024543 Length: 4109392 (3.9M) [application/octet-stream]
1045 20:28:23.029425 Saving to: 'kselftest_armhf.tar.gz'
1046 20:28:23.029905
1047 20:28:24.767256
kselftest_armhf.tar 0%[ ] 0 --.-KB/s
kselftest_armhf.tar 1%[ ] 49.92K 180KB/s
kselftest_armhf.tar 4%[ ] 194.76K 347KB/s
kselftest_armhf.tar 18%[==> ] 728.17K 877KB/s
kselftest_armhf.tar 26%[====> ] 1.02M 889KB/s
kselftest_armhf.tar 62%[===========> ] 2.43M 1.76MB/s
kselftest_armhf.tar 74%[=============> ] 2.92M 1.82MB/s
kselftest_armhf.tar 100%[===================>] 3.92M 2.26MB/s in 1.7s
1048 20:28:24.767941
1049 20:28:25.276322 2024-11-07 20:28:24 (2.26 MB/s) - 'kselftest_armhf.tar.gz' saved [4109392/4109392]
1050 20:28:25.276982
1051 20:28:39.880568 skiplist:
1052 20:28:39.881282 ========================================
1053 20:28:39.885455 ========================================
1054 20:28:39.989589 dt:test_unprobed_devices.sh
1055 20:28:40.023435 ============== Tests to run ===============
1056 20:28:40.031540 dt:test_unprobed_devices.sh
1057 20:28:40.035463 ===========End Tests to run ===============
1058 20:28:40.043792 shardfile-dt pass
1059 20:28:40.280764 <12>[ 73.954547] kselftest: Running tests in dt
1060 20:28:40.309126 TAP version 13
1061 20:28:40.336232 1..1
1062 20:28:40.394812 # timeout set to 45
1063 20:28:40.395390 # selftests: dt: test_unprobed_devices.sh
1064 20:28:41.202474 # TAP version 13
1065 20:29:05.944390 # 1..257
1066 20:29:06.109990 # ok 1 / # SKIP
1067 20:29:06.130711 # ok 2 /clk_mcasp0
1068 20:29:06.199865 # ok 3 /clk_mcasp0_fixed # SKIP
1069 20:29:06.276194 # ok 4 /cpus/cpu@0 # SKIP
1070 20:29:06.343345 # ok 5 /cpus/idle-states/mpu_gate # SKIP
1071 20:29:06.368235 # ok 6 /fixedregulator0
1072 20:29:06.382930 # ok 7 /leds
1073 20:29:06.407665 # ok 8 /ocp
1074 20:29:06.436545 # ok 9 /ocp/interconnect@44c00000
1075 20:29:06.452356 # ok 10 /ocp/interconnect@44c00000/segment@0
1076 20:29:06.480017 # ok 11 /ocp/interconnect@44c00000/segment@100000
1077 20:29:06.502040 # ok 12 /ocp/interconnect@44c00000/segment@100000/target-module@0
1078 20:29:06.570123 # not ok 13 /ocp/interconnect@44c00000/segment@100000/target-module@0/cpu@0
1079 20:29:06.592049 # ok 14 /ocp/interconnect@44c00000/segment@200000
1080 20:29:06.618357 # ok 15 /ocp/interconnect@44c00000/segment@200000/target-module@0
1081 20:29:06.722824 # not ok 16 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0
1082 20:29:06.794693 # ok 17 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0 # SKIP
1083 20:29:06.864467 # ok 18 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@0 # SKIP
1084 20:29:06.932361 # ok 19 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@120 # SKIP
1085 20:29:07.003680 # ok 20 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@14c # SKIP
1086 20:29:07.073975 # ok 21 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@18 # SKIP
1087 20:29:07.152049 # ok 22 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@1c # SKIP
1088 20:29:07.221202 # ok 23 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@24 # SKIP
1089 20:29:07.292306 # ok 24 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@38 # SKIP
1090 20:29:07.364203 # ok 25 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@0/clock@e8 # SKIP
1091 20:29:07.434144 # ok 26 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400 # SKIP
1092 20:29:07.501875 # ok 27 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@0 # SKIP
1093 20:29:07.572006 # ok 28 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@14 # SKIP
1094 20:29:07.642824 # ok 29 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@400/clock@b0 # SKIP
1095 20:29:07.711839 # ok 30 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600 # SKIP
1096 20:29:07.783288 # ok 31 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@600/clock@0 # SKIP
1097 20:29:07.852921 # ok 32 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800 # SKIP
1098 20:29:07.930684 # ok 33 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@800/clock@0 # SKIP
1099 20:29:07.994920 # ok 34 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900 # SKIP
1100 20:29:08.066968 # ok 35 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@900/clock@0 # SKIP
1101 20:29:08.136493 # ok 36 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00 # SKIP
1102 20:29:08.209735 # ok 37 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clock@a00/clock@0 # SKIP
1103 20:29:08.280929 # ok 38 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-24mhz # SKIP
1104 20:29:08.351602 # ok 39 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-32768 # SKIP
1105 20:29:08.422368 # ok 40 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clk-rc32k # SKIP
1106 20:29:08.493143 # ok 41 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-clkdiv32k # SKIP
1107 20:29:08.567058 # ok 42 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-125mhz-gclk # SKIP
1108 20:29:08.638310 # ok 43 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-cpsw-cpts-rft@520 # SKIP
1109 20:29:08.712161 # ok 44 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4-div2 # SKIP
1110 20:29:08.782583 # ok 45 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m4@480 # SKIP
1111 20:29:08.853066 # ok 46 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m5@484 # SKIP
1112 20:29:08.923679 # ok 47 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-m6@4d8 # SKIP
1113 20:29:08.994180 # ok 48 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-core-x2 # SKIP
1114 20:29:09.064774 # ok 49 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2-div2 # SKIP
1115 20:29:09.138015 # ok 50 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-ddr-m2@4a0 # SKIP
1116 20:29:09.205559 # ok 51 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-disp-m2@4a4 # SKIP
1117 20:29:09.280264 # ok 52 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-mpu-m2@4a8 # SKIP
1118 20:29:09.346953 # ok 53 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4 # SKIP
1119 20:29:09.417701 # ok 54 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2-div4-wkupdm # SKIP
1120 20:29:09.488238 # ok 55 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-dpll-per-m2@4ac # SKIP
1121 20:29:09.559732 # ok 56 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-gpio0-dbclk-mux@53c # SKIP
1122 20:29:09.629723 # ok 57 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-ieee5000-fck-1@e4 # SKIP
1123 20:29:09.700173 # ok 58 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3-gclk # SKIP
1124 20:29:09.771302 # ok 59 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l3s-gclk # SKIP
1125 20:29:09.842423 # ok 60 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4-rtc-gclk # SKIP
1126 20:29:09.913345 # ok 61 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4fw-gclk # SKIP
1127 20:29:09.984771 # ok 62 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4hs-gclk # SKIP
1128 20:29:10.056298 # ok 63 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-l4ls-gclk # SKIP
1129 20:29:10.131335 # ok 64 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-lcd-gclk@534 # SKIP
1130 20:29:10.202202 # ok 65 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmc # SKIP
1131 20:29:10.273840 # ok 66 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-mmu-fck-1@914 # SKIP
1132 20:29:10.344786 # ok 67 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-pruss-ocp-gclk@530 # SKIP
1133 20:29:10.414726 # ok 68 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-sysclk-div # SKIP
1134 20:29:10.480317 # ok 69 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-tclkin # SKIP
1135 20:29:10.555734 # ok 70 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer1-fck@528 # SKIP
1136 20:29:10.625688 # ok 71 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer2-fck@508 # SKIP
1137 20:29:10.699597 # ok 72 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer3-fck@50c # SKIP
1138 20:29:10.766831 # ok 73 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer4-fck@510 # SKIP
1139 20:29:10.838799 # ok 74 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer5-fck@518 # SKIP
1140 20:29:10.909117 # ok 75 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer6-fck@51c # SKIP
1141 20:29:10.983690 # ok 76 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-timer7-fck@504 # SKIP
1142 20:29:11.054939 # ok 77 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-usbotg-fck-8@47c # SKIP
1143 20:29:11.128528 # ok 78 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-19200000 # SKIP
1144 20:29:11.198396 # ok 79 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-24000000 # SKIP
1145 20:29:11.267537 # ok 80 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-25000000 # SKIP
1146 20:29:11.339274 # ok 81 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-virt-26000000 # SKIP
1147 20:29:11.409932 # ok 82 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock-wdt1-fck@538 # SKIP
1148 20:29:11.480023 # ok 83 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@488 # SKIP
1149 20:29:11.550913 # ok 84 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@48c # SKIP
1150 20:29:11.622256 # ok 85 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@490 # SKIP
1151 20:29:11.693488 # ok 86 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@494 # SKIP
1152 20:29:11.770772 # ok 87 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@498 # SKIP
1153 20:29:11.835821 # ok 88 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c # SKIP
1154 20:29:11.909570 # ok 89 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fck-div@0 # SKIP
1155 20:29:11.986963 # ok 90 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@52c/clock-gfx-fclk-clksel@1 # SKIP
1156 20:29:12.053530 # ok 91 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700 # SKIP
1157 20:29:12.124399 # ok 92 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2-div@3 # SKIP
1158 20:29:12.195049 # ok 93 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-clkout2@7 # SKIP
1159 20:29:12.270699 # ok 94 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/clocks/clock@700/clock-sysclkout-pre@0 # SKIP
1160 20:29:12.287723 # ok 95 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1000
1161 20:29:12.310991 # ok 96 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1100
1162 20:29:12.334469 # ok 97 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@1200
1163 20:29:12.357861 # ok 98 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@c00
1164 20:29:12.383039 # ok 99 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@d00
1165 20:29:12.405222 # ok 100 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@e00
1166 20:29:12.428353 # ok 101 /ocp/interconnect@44c00000/segment@200000/target-module@0/prcm@0/prm@f00
1167 20:29:12.450471 # ok 102 /ocp/interconnect@44c00000/segment@200000/target-module@10000
1168 20:29:12.554998 # not ok 103 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0
1169 20:29:12.583781 # ok 104 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/control@620
1170 20:29:12.605598 # ok 105 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/dma-router@f90
1171 20:29:12.626803 # ok 106 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/pinmux@800
1172 20:29:12.732281 # not ok 107 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0
1173 20:29:12.805639 # ok 108 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-adc-tsc-fck # SKIP
1174 20:29:12.880089 # ok 109 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-aes0-fck # SKIP
1175 20:29:12.952952 # ok 110 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan0-fck # SKIP
1176 20:29:13.024097 # ok 111 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-dcan1-fck # SKIP
1177 20:29:13.095023 # ok 112 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp0-fck # SKIP
1178 20:29:13.166273 # ok 113 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-mcasp1-fck # SKIP
1179 20:29:13.235199 # ok 114 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-rng-fck # SKIP
1180 20:29:13.306646 # ok 115 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sha0-fck # SKIP
1181 20:29:13.378346 # ok 116 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex0-fck # SKIP
1182 20:29:13.451436 # ok 117 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-smartreflex1-fck # SKIP
1183 20:29:13.523209 # ok 118 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock-sys-clkin-22@40 # SKIP
1184 20:29:13.594113 # ok 119 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664 # SKIP
1185 20:29:13.668917 # ok 120 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm0-tbclk@0 # SKIP
1186 20:29:13.741019 # ok 121 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm1-tbclk@1 # SKIP
1187 20:29:13.817684 # ok 122 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/clocks/clock@664/clock-ehrpwm2-tbclk@2 # SKIP
1188 20:29:13.841656 # ok 123 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/scm_conf@0/phy-gmii-sel
1189 20:29:13.911064 # not ok 124 /ocp/interconnect@44c00000/segment@200000/target-module@10000/scm@0/wkup_m3_ipc@1324
1190 20:29:13.979876 # not ok 125 /ocp/interconnect@44c00000/segment@200000/target-module@31000
1191 20:29:14.049688 # ok 126 /ocp/interconnect@44c00000/segment@200000/target-module@31000/timer@0 # SKIP
1192 20:29:14.078182 # ok 127 /ocp/interconnect@44c00000/segment@200000/target-module@35000
1193 20:29:14.162043 # not ok 128 /ocp/interconnect@44c00000/segment@200000/target-module@35000/wdt@0
1194 20:29:14.183787 # ok 129 /ocp/interconnect@44c00000/segment@200000/target-module@3e000
1195 20:29:14.266526 # not ok 130 /ocp/interconnect@44c00000/segment@200000/target-module@3e000/rtc@0
1196 20:29:14.288667 # ok 131 /ocp/interconnect@44c00000/segment@200000/target-module@7000
1197 20:29:14.317797 # ok 132 /ocp/interconnect@44c00000/segment@200000/target-module@7000/gpio@0
1198 20:29:14.335679 # ok 133 /ocp/interconnect@44c00000/segment@200000/target-module@9000
1199 20:29:14.359875 # ok 134 /ocp/interconnect@44c00000/segment@200000/target-module@9000/serial@0
1200 20:29:14.383491 # ok 135 /ocp/interconnect@44c00000/segment@200000/target-module@b000
1201 20:29:14.410991 # ok 136 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0
1202 20:29:14.434358 # ok 137 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50
1203 20:29:14.508589 # ok 138 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/baseboard_eeprom@50/nvmem-layout # SKIP
1204 20:29:14.532714 # ok 139 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tda19988@70
1205 20:29:14.553236 # ok 140 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24
1206 20:29:14.624286 # not ok 141 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/charger
1207 20:29:14.694461 # not ok 142 /ocp/interconnect@44c00000/segment@200000/target-module@b000/i2c@0/tps@24/pwrbutton
1208 20:29:14.714890 # ok 143 /ocp/interconnect@44c00000/segment@200000/target-module@d000
1209 20:29:14.816974 # not ok 144 /ocp/interconnect@47c00000
1210 20:29:14.889261 # not ok 145 /ocp/interconnect@47c00000/segment@0
1211 20:29:14.909262 # ok 146 /ocp/interconnect@48000000
1212 20:29:14.928832 # ok 147 /ocp/interconnect@48000000/segment@0
1213 20:29:14.954064 # ok 148 /ocp/interconnect@48000000/segment@0/target-module@22000
1214 20:29:14.976223 # ok 149 /ocp/interconnect@48000000/segment@0/target-module@24000
1215 20:29:14.998969 # ok 150 /ocp/interconnect@48000000/segment@0/target-module@2a000
1216 20:29:15.025958 # ok 151 /ocp/interconnect@48000000/segment@0/target-module@30000
1217 20:29:15.049364 # ok 152 /ocp/interconnect@48000000/segment@0/target-module@38000
1218 20:29:15.072414 # ok 153 /ocp/interconnect@48000000/segment@0/target-module@38000/mcasp@0
1219 20:29:15.091500 # ok 154 /ocp/interconnect@48000000/segment@0/target-module@3c000
1220 20:29:15.161897 # not ok 155 /ocp/interconnect@48000000/segment@0/target-module@40000
1221 20:29:15.238322 # ok 156 /ocp/interconnect@48000000/segment@0/target-module@40000/timer@0 # SKIP
1222 20:29:15.259337 # ok 157 /ocp/interconnect@48000000/segment@0/target-module@42000
1223 20:29:15.283287 # ok 158 /ocp/interconnect@48000000/segment@0/target-module@42000/timer@0
1224 20:29:15.300109 # ok 159 /ocp/interconnect@48000000/segment@0/target-module@44000
1225 20:29:15.328824 # ok 160 /ocp/interconnect@48000000/segment@0/target-module@44000/timer@0
1226 20:29:15.350850 # ok 161 /ocp/interconnect@48000000/segment@0/target-module@46000
1227 20:29:15.372382 # ok 162 /ocp/interconnect@48000000/segment@0/target-module@46000/timer@0
1228 20:29:15.397518 # ok 163 /ocp/interconnect@48000000/segment@0/target-module@48000
1229 20:29:15.421623 # ok 164 /ocp/interconnect@48000000/segment@0/target-module@48000/timer@0
1230 20:29:15.442202 # ok 165 /ocp/interconnect@48000000/segment@0/target-module@4a000
1231 20:29:15.468823 # ok 166 /ocp/interconnect@48000000/segment@0/target-module@4a000/timer@0
1232 20:29:15.491084 # ok 167 /ocp/interconnect@48000000/segment@0/target-module@4c000
1233 20:29:15.512261 # ok 168 /ocp/interconnect@48000000/segment@0/target-module@4c000/gpio@0
1234 20:29:15.537603 # ok 169 /ocp/interconnect@48000000/segment@0/target-module@60000
1235 20:29:15.561195 # ok 170 /ocp/interconnect@48000000/segment@0/target-module@60000/mmc@0
1236 20:29:15.581856 # ok 171 /ocp/interconnect@48000000/segment@0/target-module@c8000
1237 20:29:15.608497 # ok 172 /ocp/interconnect@48000000/segment@0/target-module@c8000/mailbox@0
1238 20:29:15.630636 # ok 173 /ocp/interconnect@48000000/segment@0/target-module@ca000
1239 20:29:15.652761 # ok 174 /ocp/interconnect@48000000/segment@0/target-module@ca000/spinlock@0
1240 20:29:15.671194 # ok 175 /ocp/interconnect@48000000/segment@100000
1241 20:29:15.699953 # ok 176 /ocp/interconnect@48000000/segment@100000/target-module@9c000
1242 20:29:15.722739 # ok 177 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0
1243 20:29:15.792651 # not ok 178 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54
1244 20:29:15.865068 # ok 179 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom0@54/nvmem-layout # SKIP
1245 20:29:15.934037 # not ok 180 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55
1246 20:29:16.006230 # ok 181 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom1@55/nvmem-layout # SKIP
1247 20:29:16.075318 # not ok 182 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56
1248 20:29:16.152215 # ok 183 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom2@56/nvmem-layout # SKIP
1249 20:29:16.222947 # not ok 184 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57
1250 20:29:16.293916 # ok 185 /ocp/interconnect@48000000/segment@100000/target-module@9c000/i2c@0/cape_eeprom3@57/nvmem-layout # SKIP
1251 20:29:16.312048 # ok 186 /ocp/interconnect@48000000/segment@100000/target-module@a0000
1252 20:29:16.337113 # ok 187 /ocp/interconnect@48000000/segment@100000/target-module@a6000
1253 20:29:16.361590 # ok 188 /ocp/interconnect@48000000/segment@100000/target-module@a8000
1254 20:29:16.382247 # ok 189 /ocp/interconnect@48000000/segment@100000/target-module@aa000
1255 20:29:16.407857 # ok 190 /ocp/interconnect@48000000/segment@100000/target-module@ac000
1256 20:29:16.432674 # ok 191 /ocp/interconnect@48000000/segment@100000/target-module@ac000/gpio@0
1257 20:29:16.451466 # ok 192 /ocp/interconnect@48000000/segment@100000/target-module@ae000
1258 20:29:16.749000 # ok 193 /ocp/interconnect@48000000/segment@100000/target-module@ae000/gpio@0
1259 20:29:16.749442 # ok 194 /ocp/interconnect@48000000/segment@100000/target-module@cc000
1260 20:29:16.749698 # ok 195 /ocp/interconnect@48000000/segment@100000/target-module@d0000
1261 20:29:16.749994 # ok 196 /ocp/interconnect@48000000/segment@100000/target-module@d8000
1262 20:29:16.750239 # ok 197 /ocp/interconnect@48000000/segment@100000/target-module@d8000/mmc@0
1263 20:29:16.750485 # ok 198 /ocp/interconnect@48000000/segment@200000
1264 20:29:16.750728 # ok 199 /ocp/interconnect@48000000/segment@200000/target-module@0
1265 20:29:16.751378 # ok 200 /ocp/interconnect@48000000/segment@200000/target-module@0/mpu@0 # SKIP
1266 20:29:16.751677 # ok 201 /ocp/interconnect@48000000/segment@300000
1267 20:29:16.751917 # ok 202 /ocp/interconnect@48000000/segment@300000/target-module@0
1268 20:29:16.752536 # ok 203 /ocp/interconnect@48000000/segment@300000/target-module@10000
1269 20:29:16.781306 # ok 204 /ocp/interconnect@48000000/segment@300000/target-module@10000/rng@0
1270 20:29:16.802046 # ok 205 /ocp/interconnect@48000000/segment@300000/target-module@2000
1271 20:29:16.822882 # ok 206 /ocp/interconnect@48000000/segment@300000/target-module@4000
1272 20:29:16.846131 # ok 207 /ocp/interconnect@48000000/segment@300000/target-module@e000
1273 20:29:16.917061 # not ok 208 /ocp/interconnect@48000000/segment@300000/target-module@e000/lcdc@0
1274 20:29:16.935365 # ok 209 /ocp/interconnect@4a000000
1275 20:29:16.960060 # ok 210 /ocp/interconnect@4a000000/segment@0
1276 20:29:16.983658 # ok 211 /ocp/interconnect@4a000000/segment@0/target-module@100000
1277 20:29:17.011671 # ok 212 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0
1278 20:29:17.033639 # ok 213 /ocp/interconnect@4a000000/segment@0/target-module@100000/switch@0/mdio@1000
1279 20:29:17.057726 # ok 214 /ocp/interconnect@4a000000/segment@0/target-module@300000
1280 20:29:17.126722 # not ok 215 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0
1281 20:29:17.229918 # ok 216 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/cfg@26000 # SKIP
1282 20:29:17.300996 # not ok 217 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/interrupt-controller@20000
1283 20:29:17.403480 # ok 218 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/mii-rt@32000 # SKIP
1284 20:29:17.473216 # not ok 219 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@34000
1285 20:29:17.543975 # not ok 220 /ocp/interconnect@4a000000/segment@0/target-module@300000/pruss@0/pru@38000
1286 20:29:17.645453 # not ok 221 /ocp/interconnect@4b140000
1287 20:29:17.711069 # not ok 222 /ocp/interconnect@4b140000/segment@0
1288 20:29:17.783781 # ok 223 /ocp/interrupt-controller@48200000 # SKIP
1289 20:29:17.806702 # ok 224 /ocp/target-module@40300000
1290 20:29:17.825364 # ok 225 /ocp/target-module@40300000/sram@0
1291 20:29:17.901686 # ok 226 /ocp/target-module@40300000/sram@0/pm-code-sram@0 # SKIP
1292 20:29:17.968035 # ok 227 /ocp/target-module@40300000/sram@0/pm-data-sram@1000 # SKIP
1293 20:29:17.989152 # ok 228 /ocp/target-module@47400000
1294 20:29:18.016300 # ok 229 /ocp/target-module@47400000/dma-controller@2000
1295 20:29:18.035067 # ok 230 /ocp/target-module@47400000/usb-phy@1300
1296 20:29:18.060503 # ok 231 /ocp/target-module@47400000/usb-phy@1b00
1297 20:29:18.081554 # ok 232 /ocp/target-module@47400000/usb@1400
1298 20:29:18.102541 # ok 233 /ocp/target-module@47400000/usb@1800
1299 20:29:18.123283 # ok 234 /ocp/target-module@47810000
1300 20:29:18.149144 # ok 235 /ocp/target-module@49000000
1301 20:29:18.167873 # ok 236 /ocp/target-module@49000000/dma@0
1302 20:29:18.193886 # ok 237 /ocp/target-module@49800000
1303 20:29:18.216949 # ok 238 /ocp/target-module@49800000/dma@0
1304 20:29:18.238481 # ok 239 /ocp/target-module@49900000
1305 20:29:18.259703 # ok 240 /ocp/target-module@49900000/dma@0
1306 20:29:18.279123 # ok 241 /ocp/target-module@49a00000
1307 20:29:18.305739 # ok 242 /ocp/target-module@49a00000/dma@0
1308 20:29:18.327020 # ok 243 /ocp/target-module@4c000000
1309 20:29:18.394026 # not ok 244 /ocp/target-module@4c000000/emif@0
1310 20:29:18.418760 # ok 245 /ocp/target-module@50000000
1311 20:29:18.439322 # ok 246 /ocp/target-module@53100000
1312 20:29:18.509138 # not ok 247 /ocp/target-module@53100000/sham@0
1313 20:29:18.534719 # ok 248 /ocp/target-module@53500000
1314 20:29:18.601532 # not ok 249 /ocp/target-module@53500000/aes@0
1315 20:29:18.626161 # ok 250 /ocp/target-module@56000000
1316 20:29:18.749494 # ok 251 /ocp/target-module@56000000/gpu@0 # SKIP
1317 20:29:18.816794 # ok 252 /opp-table # SKIP
1318 20:29:18.887832 # ok 253 /soc # SKIP
1319 20:29:18.912756 # ok 254 /sound
1320 20:29:18.931474 # ok 255 /target-module@4b000000
1321 20:29:18.956353 # ok 256 /target-module@4b000000/target-module@140000
1322 20:29:18.976559 # ok 257 /target-module@4b000000/target-module@140000/pmu@0
1323 20:29:18.984916 # # Totals: pass:117 fail:27 xfail:0 xpass:0 skip:113 error:0
1324 20:29:18.994805 not ok 1 selftests: dt: test_unprobed_devices.sh # exit=1
1325 20:29:21.057793 dt_test_unprobed_devices_sh_ skip
1326 20:29:21.063213 dt_test_unprobed_devices_sh_clk_mcasp0 pass
1327 20:29:21.068847 dt_test_unprobed_devices_sh_clk_mcasp0_fixed skip
1328 20:29:21.069342 dt_test_unprobed_devices_sh_cpus_cpu_0 skip
1329 20:29:21.077950 dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate skip
1330 20:29:21.078456 dt_test_unprobed_devices_sh_fixedregulator0 pass
1331 20:29:21.083404 dt_test_unprobed_devices_sh_leds pass
1332 20:29:21.088959 dt_test_unprobed_devices_sh_ocp pass
1333 20:29:21.092507 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 pass
1334 20:29:21.098004 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 pass
1335 20:29:21.103557 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 pass
1336 20:29:21.114644 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 pass
1337 20:29:21.120268 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 fail
1338 20:29:21.125878 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 pass
1339 20:29:21.137145 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 pass
1340 20:29:21.142767 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 fail
1341 20:29:21.154015 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 skip
1342 20:29:21.165191 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 skip
1343 20:29:21.170808 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 skip
1344 20:29:21.182053 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c skip
1345 20:29:21.193268 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 skip
1346 20:29:21.204493 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c skip
1347 20:29:21.215596 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 skip
1348 20:29:21.221211 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 skip
1349 20:29:21.232432 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 skip
1350 20:29:21.243572 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 skip
1351 20:29:21.254832 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 skip
1352 20:29:21.265965 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 skip
1353 20:29:21.271562 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 skip
1354 20:29:21.282965 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 skip
1355 20:29:21.293924 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 skip
1356 20:29:21.305095 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 skip
1357 20:29:21.310650 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 skip
1358 20:29:21.321917 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 skip
1359 20:29:21.333103 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 skip
1360 20:29:21.344307 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 skip
1361 20:29:21.349903 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 skip
1362 20:29:21.361109 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz skip
1363 20:29:21.372302 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 skip
1364 20:29:21.383437 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k skip
1365 20:29:21.394626 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k skip
1366 20:29:21.405863 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk skip
1367 20:29:21.417043 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 skip
1368 20:29:21.428292 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 skip
1369 20:29:21.439558 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 skip
1370 20:29:21.450661 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 skip
1371 20:29:21.461884 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 skip
1372 20:29:21.473324 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 skip
1373 20:29:21.484285 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 skip
1374 20:29:21.495414 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 skip
1375 20:29:21.506529 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 skip
1376 20:29:21.517908 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 skip
1377 20:29:21.528996 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 skip
1378 20:29:21.540163 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm skip
1379 20:29:21.551407 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac skip
1380 20:29:21.562615 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c skip
1381 20:29:21.573782 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 skip
1382 20:29:21.584964 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk skip
1383 20:29:21.596150 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk skip
1384 20:29:21.607362 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk skip
1385 20:29:21.618568 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk skip
1386 20:29:21.629703 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk skip
1387 20:29:21.635323 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk skip
1388 20:29:21.646538 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 skip
1389 20:29:21.657660 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc skip
1390 20:29:21.668840 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 skip
1391 20:29:21.680068 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 skip
1392 20:29:21.691244 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div skip
1393 20:29:21.702572 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin skip
1394 20:29:21.713677 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 skip
1395 20:29:21.724828 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 skip
1396 20:29:21.736024 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c skip
1397 20:29:21.747255 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 skip
1398 20:29:21.758457 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 skip
1399 20:29:21.769569 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c skip
1400 20:29:21.780723 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 skip
1401 20:29:21.791899 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c skip
1402 20:29:21.803073 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 skip
1403 20:29:21.814366 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 skip
1404 20:29:21.825562 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 skip
1405 20:29:21.831111 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 skip
1406 20:29:21.842335 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 skip
1407 20:29:21.853531 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 skip
1408 20:29:21.864656 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c skip
1409 20:29:21.875914 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 skip
1410 20:29:21.887116 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 skip
1411 20:29:21.892744 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 skip
1412 20:29:21.903946 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c skip
1413 20:29:21.915107 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 skip
1414 20:29:21.926442 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 skip
1415 20:29:21.937604 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 skip
1416 20:29:21.948815 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 skip
1417 20:29:21.959984 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 skip
1418 20:29:21.976810 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 skip
1419 20:29:21.982484 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 pass
1420 20:29:21.993623 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 pass
1421 20:29:22.004829 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 pass
1422 20:29:22.010604 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 pass
1423 20:29:22.021721 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 pass
1424 20:29:22.032865 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 pass
1425 20:29:22.038644 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 pass
1426 20:29:22.049706 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 pass
1427 20:29:22.055399 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 fail
1428 20:29:22.066551 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 pass
1429 20:29:22.077740 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 pass
1430 20:29:22.088945 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 pass
1431 20:29:22.094652 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 fail
1432 20:29:22.111342 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck skip
1433 20:29:22.122560 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck skip
1434 20:29:22.133669 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck skip
1435 20:29:22.144944 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck skip
1436 20:29:22.156101 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck skip
1437 20:29:22.167288 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck skip
1438 20:29:22.178572 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck skip
1439 20:29:22.189675 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck skip
1440 20:29:22.200877 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck skip
1441 20:29:22.217680 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck skip
1442 20:29:22.228879 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 skip
1443 20:29:22.240071 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 skip
1444 20:29:22.251241 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 skip
1445 20:29:22.267984 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 skip
1446 20:29:22.279217 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 skip
1447 20:29:22.290478 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel pass
1448 20:29:22.301638 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 fail
1449 20:29:22.307272 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 fail
1450 20:29:22.318473 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 skip
1451 20:29:22.324029 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 pass
1452 20:29:22.335178 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 fail
1453 20:29:22.340815 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 pass
1454 20:29:22.351953 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 fail
1455 20:29:22.357692 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 pass
1456 20:29:22.368741 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 pass
1457 20:29:22.379959 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 pass
1458 20:29:22.385915 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 pass
1459 20:29:22.396737 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 pass
1460 20:29:22.402392 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 pass
1461 20:29:22.413674 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 pass
1462 20:29:22.424778 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout skip
1463 20:29:22.435959 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 pass
1464 20:29:22.447191 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 pass
1465 20:29:22.452768 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger fail
1466 20:29:22.463962 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton fail
1467 20:29:22.475110 dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 pass
1468 20:29:22.480757 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 fail
1469 20:29:22.486367 dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 fail
1470 20:29:22.491971 dt_test_unprobed_devices_sh_ocp_interconnect_48000000 pass
1471 20:29:22.497570 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 pass
1472 20:29:22.503181 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 pass
1473 20:29:22.508772 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 pass
1474 20:29:22.519927 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 pass
1475 20:29:22.525616 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 pass
1476 20:29:22.536733 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 pass
1477 20:29:22.542393 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 pass
1478 20:29:22.553474 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 pass
1479 20:29:22.559097 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 fail
1480 20:29:22.570289 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 skip
1481 20:29:22.575886 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 pass
1482 20:29:22.587093 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 pass
1483 20:29:22.592699 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 pass
1484 20:29:22.598297 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 pass
1485 20:29:22.609454 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 pass
1486 20:29:22.615018 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 pass
1487 20:29:22.626305 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 pass
1488 20:29:22.632083 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 pass
1489 20:29:22.643019 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 pass
1490 20:29:22.648746 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 pass
1491 20:29:22.659743 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 pass
1492 20:29:22.665429 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 pass
1493 20:29:22.676587 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 pass
1494 20:29:22.682195 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 pass
1495 20:29:22.693377 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 pass
1496 20:29:22.698966 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 pass
1497 20:29:22.704613 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 pass
1498 20:29:22.715762 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 pass
1499 20:29:22.721360 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 pass
1500 20:29:22.732623 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 pass
1501 20:29:22.738182 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 pass
1502 20:29:22.749317 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 fail
1503 20:29:22.760595 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout skip
1504 20:29:22.771713 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 fail
1505 20:29:22.782849 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout skip
1506 20:29:22.794098 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 fail
1507 20:29:22.805233 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout skip
1508 20:29:22.816421 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 fail
1509 20:29:22.827697 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout skip
1510 20:29:22.833253 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 pass
1511 20:29:22.844494 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 pass
1512 20:29:22.849970 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 pass
1513 20:29:22.861164 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 pass
1514 20:29:22.866796 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 pass
1515 20:29:22.877933 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 pass
1516 20:29:22.883736 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 pass
1517 20:29:22.894723 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 pass
1518 20:29:22.900321 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 pass
1519 20:29:22.911511 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 pass
1520 20:29:22.917073 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 pass
1521 20:29:22.928272 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 pass
1522 20:29:22.934034 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 pass
1523 20:29:22.939578 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 pass
1524 20:29:22.950630 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 skip
1525 20:29:22.956264 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 pass
1526 20:29:22.967389 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 pass
1527 20:29:22.973128 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 pass
1528 20:29:22.984277 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 pass
1529 20:29:22.989909 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 pass
1530 20:29:23.000999 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 pass
1531 20:29:23.006703 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 pass
1532 20:29:23.017990 dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 fail
1533 20:29:23.024110 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 pass
1534 20:29:23.029151 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 pass
1535 20:29:23.034843 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 pass
1536 20:29:23.045915 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 pass
1537 20:29:23.051500 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 pass
1538 20:29:23.062740 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 pass
1539 20:29:23.068224 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 fail
1540 20:29:23.079479 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 skip
1541 20:29:23.090631 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 fail
1542 20:29:23.101901 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 skip
1543 20:29:23.107458 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 fail
1544 20:29:23.118799 dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 fail
1545 20:29:23.124330 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 fail
1546 20:29:23.129975 dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 fail
1547 20:29:23.135588 dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 skip
1548 20:29:23.141128 dt_test_unprobed_devices_sh_ocp_target-module_40300000 pass
1549 20:29:23.146772 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 pass
1550 20:29:23.157980 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 skip
1551 20:29:23.163553 dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 skip
1552 20:29:23.169145 dt_test_unprobed_devices_sh_ocp_target-module_47400000 pass
1553 20:29:23.174782 dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 pass
1554 20:29:23.180303 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 pass
1555 20:29:23.185921 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 pass
1556 20:29:23.197146 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 pass
1557 20:29:23.202797 dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 pass
1558 20:29:23.208304 dt_test_unprobed_devices_sh_ocp_target-module_47810000 pass
1559 20:29:23.213958 dt_test_unprobed_devices_sh_ocp_target-module_49000000 pass
1560 20:29:23.219577 dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 pass
1561 20:29:23.225163 dt_test_unprobed_devices_sh_ocp_target-module_49800000 pass
1562 20:29:23.230796 dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 pass
1563 20:29:23.236632 dt_test_unprobed_devices_sh_ocp_target-module_49900000 pass
1564 20:29:23.242066 dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 pass
1565 20:29:23.247488 dt_test_unprobed_devices_sh_ocp_target-module_49a00000 pass
1566 20:29:23.253077 dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 pass
1567 20:29:23.258731 dt_test_unprobed_devices_sh_ocp_target-module_4c000000 pass
1568 20:29:23.264247 dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 fail
1569 20:29:23.269900 dt_test_unprobed_devices_sh_ocp_target-module_50000000 pass
1570 20:29:23.270462 dt_test_unprobed_devices_sh_ocp_target-module_53100000 pass
1571 20:29:23.281039 dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 fail
1572 20:29:23.281591 dt_test_unprobed_devices_sh_ocp_target-module_53500000 pass
1573 20:29:23.292255 dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 fail
1574 20:29:23.292812 dt_test_unprobed_devices_sh_ocp_target-module_56000000 pass
1575 20:29:23.303481 dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 skip
1576 20:29:23.304041 dt_test_unprobed_devices_sh_opp-table skip
1577 20:29:23.309113 dt_test_unprobed_devices_sh_soc skip
1578 20:29:23.309646 dt_test_unprobed_devices_sh_sound pass
1579 20:29:23.314770 dt_test_unprobed_devices_sh_target-module_4b000000 pass
1580 20:29:23.325905 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 pass
1581 20:29:23.331714 dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 pass
1582 20:29:23.332343 dt_test_unprobed_devices_sh fail
1583 20:29:23.337255 + ../../utils/send-to-lava.sh ./output/result.txt
1584 20:29:23.342825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=pass>
1585 20:29:23.343814 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=pass
1587 20:29:23.350915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip>
1588 20:29:23.351750 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ RESULT=skip
1590 20:29:23.434926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass>
1591 20:29:23.435845 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0 RESULT=pass
1593 20:29:23.527282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip>
1594 20:29:23.528206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_clk_mcasp0_fixed RESULT=skip
1596 20:29:23.616436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip>
1597 20:29:23.617359 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_cpu_0 RESULT=skip
1599 20:29:23.710533 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip>
1600 20:29:23.711458 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate RESULT=skip
1602 20:29:23.801707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass>
1603 20:29:23.802669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_fixedregulator0 RESULT=pass
1605 20:29:23.894443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass>
1606 20:29:23.895346 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_leds RESULT=pass
1608 20:29:23.985588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass>
1609 20:29:23.986711 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp RESULT=pass
1611 20:29:24.081165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass>
1612 20:29:24.082167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000 RESULT=pass
1614 20:29:24.189967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass>
1615 20:29:24.190677 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0 RESULT=pass
1617 20:29:24.318435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass>
1618 20:29:24.319167 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000 RESULT=pass
1620 20:29:24.430234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass>
1621 20:29:24.430957 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0 RESULT=pass
1623 20:29:24.539653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail>
1624 20:29:24.540440 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0 RESULT=fail
1626 20:29:24.647597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass>
1627 20:29:24.648534 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000 RESULT=pass
1629 20:29:24.758552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass>
1630 20:29:24.759525 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0 RESULT=pass
1632 20:29:24.865956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail>
1633 20:29:24.866885 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0 RESULT=fail
1635 20:29:24.960742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip>
1636 20:29:24.961702 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0 RESULT=skip
1638 20:29:25.053791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip>
1639 20:29:25.055088 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0 RESULT=skip
1641 20:29:25.147699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip>
1642 20:29:25.148655 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120 RESULT=skip
1644 20:29:25.239987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip>
1645 20:29:25.240928 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c RESULT=skip
1647 20:29:25.331173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip>
1648 20:29:25.332072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18 RESULT=skip
1650 20:29:25.424093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip>
1651 20:29:25.425001 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c RESULT=skip
1653 20:29:25.516352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip>
1654 20:29:25.517012 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24 RESULT=skip
1656 20:29:25.617650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip>
1657 20:29:25.618646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38 RESULT=skip
1659 20:29:25.711151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip>
1660 20:29:25.712093 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8 RESULT=skip
1662 20:29:25.802621 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip>
1663 20:29:25.805070 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400 RESULT=skip
1665 20:29:25.894359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip>
1666 20:29:25.894923 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0 RESULT=skip
1668 20:29:25.984620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip>
1669 20:29:25.987239 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14 RESULT=skip
1671 20:29:26.076015 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip>
1672 20:29:26.076857 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0 RESULT=skip
1674 20:29:26.166252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip>
1675 20:29:26.167100 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600 RESULT=skip
1677 20:29:26.259016 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip>
1678 20:29:26.259873 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0 RESULT=skip
1680 20:29:26.351639 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip>
1681 20:29:26.352553 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800 RESULT=skip
1683 20:29:26.442986 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip>
1684 20:29:26.443866 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0 RESULT=skip
1686 20:29:26.534468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip>
1687 20:29:26.535285 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900 RESULT=skip
1689 20:29:26.627635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip>
1690 20:29:26.628438 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0 RESULT=skip
1692 20:29:26.718206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip>
1693 20:29:26.719056 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00 RESULT=skip
1695 20:29:26.817022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip>
1696 20:29:26.817648 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0 RESULT=skip
1698 20:29:26.911254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip>
1699 20:29:26.911893 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz RESULT=skip
1701 20:29:27.003755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip>
1702 20:29:27.004739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768 RESULT=skip
1704 20:29:27.095400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip>
1705 20:29:27.096206 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k RESULT=skip
1707 20:29:27.187287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip>
1708 20:29:27.188014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k RESULT=skip
1710 20:29:27.281068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip>
1711 20:29:27.282061 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk RESULT=skip
1713 20:29:27.373531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip>
1714 20:29:27.374680 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520 RESULT=skip
1716 20:29:27.464165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip>
1717 20:29:27.465128 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2 RESULT=skip
1719 20:29:27.555785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip>
1720 20:29:27.556416 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480 RESULT=skip
1722 20:29:27.648951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip>
1723 20:29:27.649739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484 RESULT=skip
1725 20:29:27.759829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip>
1726 20:29:27.760770 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8 RESULT=skip
1728 20:29:27.853548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip>
1729 20:29:27.854507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2 RESULT=skip
1731 20:29:27.956975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip>
1732 20:29:27.957930 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2 RESULT=skip
1734 20:29:28.053100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip>
1735 20:29:28.053757 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0 RESULT=skip
1737 20:29:28.142326 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip>
1738 20:29:28.142994 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4 RESULT=skip
1740 20:29:28.232742 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip>
1741 20:29:28.233496 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8 RESULT=skip
1743 20:29:28.322791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip>
1744 20:29:28.323551 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4 RESULT=skip
1746 20:29:28.414951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip>
1747 20:29:28.415724 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm RESULT=skip
1749 20:29:28.499235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip>
1750 20:29:28.500014 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac RESULT=skip
1752 20:29:28.591884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip>
1753 20:29:28.592631 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c RESULT=skip
1755 20:29:28.679635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip>
1756 20:29:28.680388 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4 RESULT=skip
1758 20:29:28.770658 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip>
1759 20:29:28.771424 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk RESULT=skip
1761 20:29:28.860666 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip>
1762 20:29:28.861399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk RESULT=skip
1764 20:29:28.954165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip>
1765 20:29:28.955027 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk RESULT=skip
1767 20:29:29.044248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip>
1768 20:29:29.044898 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk RESULT=skip
1770 20:29:29.135013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip>
1771 20:29:29.135848 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk RESULT=skip
1773 20:29:29.225568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip>
1774 20:29:29.226470 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk RESULT=skip
1776 20:29:29.319257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip>
1777 20:29:29.320142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534 RESULT=skip
1779 20:29:29.411078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip>
1780 20:29:29.411838 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc RESULT=skip
1782 20:29:29.503342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip>
1783 20:29:29.504182 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914 RESULT=skip
1785 20:29:29.593266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip>
1786 20:29:29.594166 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530 RESULT=skip
1788 20:29:29.677571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip>
1789 20:29:29.678400 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div RESULT=skip
1791 20:29:29.768321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip>
1792 20:29:29.769118 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin RESULT=skip
1794 20:29:29.859285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip>
1795 20:29:29.860142 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528 RESULT=skip
1797 20:29:29.949758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip>
1798 20:29:29.950606 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508 RESULT=skip
1800 20:29:30.042138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip>
1801 20:29:30.043015 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c RESULT=skip
1803 20:29:30.132090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip>
1804 20:29:30.132872 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510 RESULT=skip
1806 20:29:30.224703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip>
1807 20:29:30.225517 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518 RESULT=skip
1809 20:29:30.316316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip>
1810 20:29:30.317107 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c RESULT=skip
1812 20:29:30.408486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip>
1813 20:29:30.409349 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504 RESULT=skip
1815 20:29:30.501692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip>
1816 20:29:30.502589 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c RESULT=skip
1818 20:29:30.592225 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip>
1819 20:29:30.593011 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000 RESULT=skip
1821 20:29:30.683097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip>
1822 20:29:30.683878 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000 RESULT=skip
1824 20:29:30.774649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip>
1825 20:29:30.775421 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000 RESULT=skip
1827 20:29:30.866764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip>
1828 20:29:30.867548 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000 RESULT=skip
1830 20:29:30.957413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip>
1831 20:29:30.958208 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538 RESULT=skip
1833 20:29:31.047892 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip>
1834 20:29:31.048685 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488 RESULT=skip
1836 20:29:31.140816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip>
1837 20:29:31.141694 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c RESULT=skip
1839 20:29:31.231883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip>
1840 20:29:31.232734 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490 RESULT=skip
1842 20:29:31.323280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip>
1843 20:29:31.324072 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494 RESULT=skip
1845 20:29:31.412580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip>
1846 20:29:31.413439 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498 RESULT=skip
1848 20:29:31.505682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip>
1849 20:29:31.506511 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c RESULT=skip
1851 20:29:31.597275 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip>
1852 20:29:31.598044 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0 RESULT=skip
1854 20:29:31.687645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip>
1855 20:29:31.688380 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1 RESULT=skip
1857 20:29:31.776055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip>
1858 20:29:31.776789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700 RESULT=skip
1860 20:29:31.869018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip>
1861 20:29:31.869899 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3 RESULT=skip
1863 20:29:31.960121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip>
1864 20:29:31.960759 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7 RESULT=skip
1866 20:29:32.054039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip>
1867 20:29:32.054712 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0 RESULT=skip
1869 20:29:32.138681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass>
1870 20:29:32.139328 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000 RESULT=pass
1872 20:29:32.229354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass>
1873 20:29:32.230235 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100 RESULT=pass
1875 20:29:32.321309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass>
1876 20:29:32.322193 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200 RESULT=pass
1878 20:29:32.409531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass>
1879 20:29:32.410479 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00 RESULT=pass
1881 20:29:32.502076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass>
1882 20:29:32.502956 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00 RESULT=pass
1884 20:29:32.591004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass>
1885 20:29:32.591965 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00 RESULT=pass
1887 20:29:32.680453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass>
1888 20:29:32.681280 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00 RESULT=pass
1890 20:29:32.770063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass>
1891 20:29:32.770860 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000 RESULT=pass
1893 20:29:32.861260 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail>
1894 20:29:32.862374 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0 RESULT=fail
1896 20:29:32.951223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass>
1897 20:29:32.952047 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620 RESULT=pass
1899 20:29:33.041369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass>
1900 20:29:33.042239 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90 RESULT=pass
1902 20:29:33.131792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass>
1903 20:29:33.132556 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800 RESULT=pass
1905 20:29:33.219552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail>
1906 20:29:33.220411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0 RESULT=fail
1908 20:29:33.312722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip>
1909 20:29:33.313512 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck RESULT=skip
1911 20:29:33.410138 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip>
1912 20:29:33.410975 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck RESULT=skip
1914 20:29:33.501949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip>
1915 20:29:33.502768 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck RESULT=skip
1917 20:29:33.592947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip>
1918 20:29:33.593700 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck RESULT=skip
1920 20:29:33.683515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip>
1921 20:29:33.684398 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck RESULT=skip
1923 20:29:33.775226 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip>
1924 20:29:33.777219 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck RESULT=skip
1926 20:29:33.864439 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip>
1927 20:29:33.865194 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck RESULT=skip
1929 20:29:33.954186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip>
1930 20:29:33.955112 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck RESULT=skip
1932 20:29:34.044792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip>
1933 20:29:34.046041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck RESULT=skip
1935 20:29:34.135345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip>
1936 20:29:34.136220 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck RESULT=skip
1938 20:29:34.228168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip>
1939 20:29:34.229081 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40 RESULT=skip
1941 20:29:34.319014 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip>
1942 20:29:34.319955 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664 RESULT=skip
1944 20:29:34.409852 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip
1946 20:29:34.412966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0 RESULT=skip>
1947 20:29:34.501127 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip
1949 20:29:34.504209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1 RESULT=skip>
1950 20:29:34.592803 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip
1952 20:29:34.595890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2 RESULT=skip>
1953 20:29:34.686371 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass>
1954 20:29:34.687399 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel RESULT=pass
1956 20:29:34.778515 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail>
1957 20:29:34.779506 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324 RESULT=fail
1959 20:29:34.869869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail>
1960 20:29:34.870839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000 RESULT=fail
1962 20:29:34.961089 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip>
1963 20:29:34.962051 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0 RESULT=skip
1965 20:29:35.050754 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass>
1966 20:29:35.051715 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000 RESULT=pass
1968 20:29:35.142790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail>
1969 20:29:35.143718 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0 RESULT=fail
1971 20:29:35.234971 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass>
1972 20:29:35.235913 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000 RESULT=pass
1974 20:29:35.326502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail>
1975 20:29:35.327494 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0 RESULT=fail
1977 20:29:35.419587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass>
1978 20:29:35.420553 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000 RESULT=pass
1980 20:29:35.509491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass>
1981 20:29:35.510492 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0 RESULT=pass
1983 20:29:35.600372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass>
1984 20:29:35.601316 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000 RESULT=pass
1986 20:29:35.692113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass>
1987 20:29:35.693055 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0 RESULT=pass
1989 20:29:35.781438 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass>
1990 20:29:35.782387 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000 RESULT=pass
1992 20:29:35.872483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass>
1993 20:29:35.873435 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0 RESULT=pass
1995 20:29:35.965504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass>
1996 20:29:35.966683 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50 RESULT=pass
1998 20:29:36.059821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip>
1999 20:29:36.060789 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout RESULT=skip
2001 20:29:36.149144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass>
2002 20:29:36.150080 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70 RESULT=pass
2004 20:29:36.241094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass>
2005 20:29:36.242042 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24 RESULT=pass
2007 20:29:36.330780 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail>
2008 20:29:36.331690 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger RESULT=fail
2010 20:29:36.422696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail>
2011 20:29:36.423590 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton RESULT=fail
2013 20:29:36.509872 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass>
2014 20:29:36.510855 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000 RESULT=pass
2016 20:29:36.598850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail>
2017 20:29:36.599987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000 RESULT=fail
2019 20:29:36.690484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail>
2020 20:29:36.691439 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0 RESULT=fail
2022 20:29:36.780140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass>
2023 20:29:36.781199 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000 RESULT=pass
2025 20:29:36.872427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass>
2026 20:29:36.873385 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0 RESULT=pass
2028 20:29:36.968519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass>
2029 20:29:36.969485 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000 RESULT=pass
2031 20:29:37.060978 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass>
2032 20:29:37.061929 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000 RESULT=pass
2034 20:29:37.152812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass>
2035 20:29:37.153938 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000 RESULT=pass
2037 20:29:37.243682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass>
2038 20:29:37.244602 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000 RESULT=pass
2040 20:29:37.336403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass>
2041 20:29:37.337336 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000 RESULT=pass
2043 20:29:37.429798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass>
2044 20:29:37.430771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0 RESULT=pass
2046 20:29:37.521350 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass>
2047 20:29:37.522319 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000 RESULT=pass
2049 20:29:37.612729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail>
2050 20:29:37.613646 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000 RESULT=fail
2052 20:29:37.705336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip>
2053 20:29:37.706327 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0 RESULT=skip
2055 20:29:37.798338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass>
2056 20:29:37.799249 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000 RESULT=pass
2058 20:29:37.890173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass>
2059 20:29:37.891217 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0 RESULT=pass
2061 20:29:37.981301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass>
2062 20:29:37.982230 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000 RESULT=pass
2064 20:29:38.074941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass>
2065 20:29:38.075875 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0 RESULT=pass
2067 20:29:38.166405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass>
2068 20:29:38.167321 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000 RESULT=pass
2070 20:29:38.259145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass>
2071 20:29:38.260187 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0 RESULT=pass
2073 20:29:38.351098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass>
2074 20:29:38.351771 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000 RESULT=pass
2076 20:29:38.443587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass>
2077 20:29:38.444533 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0 RESULT=pass
2079 20:29:38.535272 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass>
2080 20:29:38.536215 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000 RESULT=pass
2082 20:29:38.627195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass>
2083 20:29:38.628083 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0 RESULT=pass
2085 20:29:38.718481 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass>
2086 20:29:38.719367 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000 RESULT=pass
2088 20:29:38.812625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass>
2089 20:29:38.813543 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0 RESULT=pass
2091 20:29:38.911627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass>
2092 20:29:38.912532 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000 RESULT=pass
2094 20:29:39.008427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass>
2095 20:29:39.009373 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0 RESULT=pass
2097 20:29:39.109755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass>
2098 20:29:39.110720 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000 RESULT=pass
2100 20:29:39.219220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass>
2101 20:29:39.220375 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0 RESULT=pass
2103 20:29:39.314328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass>
2104 20:29:39.315023 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000 RESULT=pass
2106 20:29:39.415711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass>
2107 20:29:39.416376 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0 RESULT=pass
2109 20:29:39.507916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass>
2110 20:29:39.508607 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000 RESULT=pass
2112 20:29:39.627025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass>
2113 20:29:39.628007 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000 RESULT=pass
2115 20:29:39.734841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass>
2116 20:29:39.735787 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0 RESULT=pass
2118 20:29:39.828496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail>
2119 20:29:39.829468 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54 RESULT=fail
2121 20:29:39.920690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip>
2122 20:29:39.921558 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout RESULT=skip
2124 20:29:40.010340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail>
2125 20:29:40.011254 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55 RESULT=fail
2127 20:29:40.112827 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip>
2128 20:29:40.113698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout RESULT=skip
2130 20:29:40.205318 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail>
2131 20:29:40.206250 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56 RESULT=fail
2133 20:29:40.299127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip>
2134 20:29:40.300013 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout RESULT=skip
2136 20:29:40.393781 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail>
2137 20:29:40.394693 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57 RESULT=fail
2139 20:29:40.486828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip>
2140 20:29:40.487723 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout RESULT=skip
2142 20:29:40.590650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass>
2143 20:29:40.591390 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000 RESULT=pass
2145 20:29:40.699222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass>
2146 20:29:40.699893 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000 RESULT=pass
2148 20:29:40.795208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass>
2149 20:29:40.796161 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000 RESULT=pass
2151 20:29:40.894345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass>
2152 20:29:40.895448 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000 RESULT=pass
2154 20:29:40.989568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass>
2155 20:29:40.991701 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000 RESULT=pass
2157 20:29:41.087400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass>
2158 20:29:41.088355 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0 RESULT=pass
2160 20:29:41.183930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass>
2161 20:29:41.184874 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000 RESULT=pass
2163 20:29:41.279094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass>
2164 20:29:41.280010 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0 RESULT=pass
2166 20:29:41.374335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass>
2167 20:29:41.375257 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000 RESULT=pass
2169 20:29:41.469582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass>
2170 20:29:41.470362 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000 RESULT=pass
2172 20:29:41.565504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass>
2173 20:29:41.566434 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000 RESULT=pass
2175 20:29:41.665835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass>
2176 20:29:41.666503 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0 RESULT=pass
2178 20:29:41.757004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass>
2179 20:29:41.757645 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000 RESULT=pass
2181 20:29:41.850430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass>
2182 20:29:41.851292 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0 RESULT=pass
2184 20:29:41.943938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip>
2185 20:29:41.944823 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0 RESULT=skip
2187 20:29:42.037283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass>
2188 20:29:42.038255 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000 RESULT=pass
2190 20:29:42.129859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass>
2191 20:29:42.130884 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0 RESULT=pass
2193 20:29:42.221358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass>
2194 20:29:42.222295 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000 RESULT=pass
2196 20:29:42.314255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass>
2197 20:29:42.315182 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0 RESULT=pass
2199 20:29:42.405776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass>
2200 20:29:42.406710 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000 RESULT=pass
2202 20:29:42.495652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass>
2203 20:29:42.496326 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000 RESULT=pass
2205 20:29:42.586585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass>
2206 20:29:42.587522 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000 RESULT=pass
2208 20:29:42.678258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail>
2209 20:29:42.679104 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0 RESULT=fail
2211 20:29:42.764261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass>
2212 20:29:42.765144 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000 RESULT=pass
2214 20:29:42.857047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass>
2215 20:29:42.857939 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0 RESULT=pass
2217 20:29:42.947735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass>
2218 20:29:42.948629 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000 RESULT=pass
2220 20:29:43.041066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass>
2221 20:29:43.041987 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0 RESULT=pass
2223 20:29:43.131809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass>
2224 20:29:43.132725 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000 RESULT=pass
2226 20:29:43.221759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass>
2227 20:29:43.222772 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000 RESULT=pass
2229 20:29:43.314010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail>
2230 20:29:43.314943 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0 RESULT=fail
2232 20:29:43.406243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip>
2233 20:29:43.407148 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000 RESULT=skip
2235 20:29:43.500428 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail>
2236 20:29:43.501102 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000 RESULT=fail
2238 20:29:43.590714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip>
2239 20:29:43.591634 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000 RESULT=skip
2241 20:29:43.681602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail>
2242 20:29:43.682552 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000 RESULT=fail
2244 20:29:43.773167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail>
2245 20:29:43.774145 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000 RESULT=fail
2247 20:29:43.859517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail>
2248 20:29:43.860411 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000 RESULT=fail
2250 20:29:43.952152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail>
2251 20:29:43.953032 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0 RESULT=fail
2253 20:29:44.044366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip>
2254 20:29:44.045310 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000 RESULT=skip
2256 20:29:44.136816 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass>
2257 20:29:44.137739 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000 RESULT=pass
2259 20:29:44.237170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass>
2260 20:29:44.238151 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0 RESULT=pass
2262 20:29:44.339770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip>
2263 20:29:44.340850 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0 RESULT=skip
2265 20:29:44.429627 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip
2267 20:29:44.432900 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000 RESULT=skip>
2268 20:29:44.524630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass>
2269 20:29:44.525566 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000 RESULT=pass
2271 20:29:44.620491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass>
2272 20:29:44.621507 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000 RESULT=pass
2274 20:29:44.710024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass>
2275 20:29:44.711041 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300 RESULT=pass
2277 20:29:44.800922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass>
2278 20:29:44.801888 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00 RESULT=pass
2280 20:29:44.891927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass>
2281 20:29:44.892839 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400 RESULT=pass
2283 20:29:44.982951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass>
2284 20:29:44.983882 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800 RESULT=pass
2286 20:29:45.075759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass>
2287 20:29:45.076692 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_47810000 RESULT=pass
2289 20:29:45.167054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass>
2290 20:29:45.167994 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000 RESULT=pass
2292 20:29:45.257950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass>
2293 20:29:45.258854 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0 RESULT=pass
2295 20:29:45.348519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass>
2296 20:29:45.349405 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000 RESULT=pass
2298 20:29:45.450416 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass>
2299 20:29:45.451363 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0 RESULT=pass
2301 20:29:45.551235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass>
2302 20:29:45.552173 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000 RESULT=pass
2304 20:29:45.653465 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass>
2305 20:29:45.654135 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0 RESULT=pass
2307 20:29:45.745004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass>
2308 20:29:45.745669 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000 RESULT=pass
2310 20:29:45.835937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass>
2311 20:29:45.836593 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0 RESULT=pass
2313 20:29:45.926834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass>
2314 20:29:45.927488 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000 RESULT=pass
2316 20:29:46.018611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail>
2317 20:29:46.019547 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0 RESULT=fail
2319 20:29:46.110104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass>
2320 20:29:46.111035 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_50000000 RESULT=pass
2322 20:29:46.210574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass>
2323 20:29:46.211509 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000 RESULT=pass
2325 20:29:46.302833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail>
2326 20:29:46.304287 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0 RESULT=fail
2328 20:29:46.396106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass>
2329 20:29:46.397698 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000 RESULT=pass
2331 20:29:46.486182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail>
2332 20:29:46.486842 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0 RESULT=fail
2334 20:29:46.576693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass>
2335 20:29:46.577638 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000 RESULT=pass
2337 20:29:46.894168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip>
2338 20:29:46.894814 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0 RESULT=skip
2340 20:29:46.993509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip>
2341 20:29:46.994370 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_opp-table RESULT=skip
2343 20:29:47.085099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip>
2344 20:29:47.086408 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_soc RESULT=skip
2346 20:29:47.173869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass>
2347 20:29:47.174941 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_sound RESULT=pass
2349 20:29:47.266373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass>
2350 20:29:47.267393 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000 RESULT=pass
2352 20:29:47.359435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass>
2353 20:29:47.360524 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000 RESULT=pass
2355 20:29:47.450134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass>
2356 20:29:47.451208 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0 RESULT=pass
2358 20:29:47.538578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail>
2359 20:29:47.539403 + set +x
2360 20:29:47.540204 Received signal: <TESTCASE> TEST_CASE_ID=dt_test_unprobed_devices_sh RESULT=fail
2362 20:29:47.542808 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 955215_1.6.2.4.5>
2363 20:29:47.543694 Received signal: <ENDRUN> 1_kselftest-dt 955215_1.6.2.4.5
2364 20:29:47.544315 Ending use of test pattern.
2365 20:29:47.544857 Ending test lava.1_kselftest-dt (955215_1.6.2.4.5), duration 85.50
2367 20:29:47.550217 <LAVA_TEST_RUNNER EXIT>
2368 20:29:47.550733 ok: lava_test_shell seems to have completed
2369 20:29:47.557369 dt_test_unprobed_devices_sh: fail
dt_test_unprobed_devices_sh_: skip
dt_test_unprobed_devices_sh_clk_mcasp0: pass
dt_test_unprobed_devices_sh_clk_mcasp0_fixed: skip
dt_test_unprobed_devices_sh_cpus_cpu_0: skip
dt_test_unprobed_devices_sh_cpus_idle-states_mpu_gate: skip
dt_test_unprobed_devices_sh_fixedregulator0: pass
dt_test_unprobed_devices_sh_leds: pass
dt_test_unprobed_devices_sh_ocp: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_100000_target-module_0_cpu_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_120: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_14c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_18: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_1c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_24: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_38: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_0_clock_e8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_14: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_400_clock_b0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_600_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_800_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_900_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clock_a00_clock_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-24mhz: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-32768: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clk-rc32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-clkdiv32k: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-125mhz-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-cpsw-cpts-rft_520: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m4_480: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m5_484: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-m6_4d8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-core-x2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2-div2: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-ddr-m2_4a0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-disp-m2_4a4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-mpu-m2_4a8: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2-div4-wkupdm: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-dpll-per-m2_4ac: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-gpio0-dbclk-mux_53c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-ieee5000-fck-1_e4: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l3s-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4-rtc-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4fw-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4hs-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-l4ls-gclk: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-lcd-gclk_534: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmc: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-mmu-fck-1_914: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-pruss-ocp-gclk_530: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-sysclk-div: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-tclkin: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer1-fck_528: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer2-fck_508: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer3-fck_50c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer4-fck_510: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer5-fck_518: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer6-fck_51c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-timer7-fck_504: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-usbotg-fck-8_47c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-19200000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-24000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-25000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-virt-26000000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock-wdt1-fck_538: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_488: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_48c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_490: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_494: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_498: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fck-div_0: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_52c_clock-gfx-fclk-clksel_1
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2-div_3: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-clkout2_7: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_clocks_clock_700_clock-sysclkout-pre_0
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1100: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_1200: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_c00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_d00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_e00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_0_prcm_0_prm_f00: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_control_620: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_dma-router_f90: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_pinmux_800: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0: fail
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-adc-tsc-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-aes0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan0-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-dcan1-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-mcasp1-fck
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-rng-fck: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sha0-fck: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex0-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-smartreflex1-fck
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock-sys-clkin-22_40
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm0-tbclk_0
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm1-tbclk_1
: skip
? dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_clocks_clock_664_clock-ehrpwm2-tbclk_2
: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_scm_conf_0_phy-gmii-sel: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_10000_scm_0_wkup_m3_ipc_1324: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_31000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_35000_wdt_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_3e000_rtc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_7000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_9000_serial_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_baseboard_eeprom_50_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tda19988_70: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24: pass
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_charger: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_b000_i2c_0_tps_24_pwrbutton: fail
dt_test_unprobed_devices_sh_ocp_interconnect_44c00000_segment_200000_target-module_d000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_47c00000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_22000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_24000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_2a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_30000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_38000_mcasp_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_3c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_40000_timer_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_42000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_44000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_46000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_48000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4a000_timer_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_4c000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_60000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_c8000_mailbox_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_0_target-module_ca000_spinlock_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom0_54_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom1_55_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom2_56_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57: fail
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_9c000_i2c_0_cape_eeprom3_57_nvmem-layout: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a6000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_a8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_aa000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ac000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_ae000_gpio_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_cc000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d0000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_100000_target-module_d8000_mmc_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_200000_target-module_0_mpu_0: skip
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_10000_rng_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_2000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_4000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_48000000_segment_300000_target-module_e000_lcdc_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_100000_switch_0_mdio_1000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000: pass
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_cfg_26000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_interrupt-controller_20000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_mii-rt_32000: skip
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_34000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4a000000_segment_0_target-module_300000_pruss_0_pru_38000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000: fail
dt_test_unprobed_devices_sh_ocp_interconnect_4b140000_segment_0: fail
dt_test_unprobed_devices_sh_ocp_interrupt-controller_48200000: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-code-sram_0: skip
dt_test_unprobed_devices_sh_ocp_target-module_40300000_sram_0_pm-data-sram_1000: skip
dt_test_unprobed_devices_sh_ocp_target-module_47400000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_dma-controller_2000: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1300: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb-phy_1b00: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1400: pass
dt_test_unprobed_devices_sh_ocp_target-module_47400000_usb_1800: pass
dt_test_unprobed_devices_sh_ocp_target-module_47810000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49000000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49800000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49900000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000: pass
dt_test_unprobed_devices_sh_ocp_target-module_49a00000_dma_0: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_4c000000_emif_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_50000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53100000_sham_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_53500000: pass
dt_test_unprobed_devices_sh_ocp_target-module_53500000_aes_0: fail
dt_test_unprobed_devices_sh_ocp_target-module_56000000: pass
dt_test_unprobed_devices_sh_ocp_target-module_56000000_gpu_0: skip
dt_test_unprobed_devices_sh_opp-table: skip
dt_test_unprobed_devices_sh_soc: skip
dt_test_unprobed_devices_sh_sound: pass
dt_test_unprobed_devices_sh_target-module_4b000000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000: pass
dt_test_unprobed_devices_sh_target-module_4b000000_target-module_140000_pmu_0: pass
shardfile-dt: pass
2370 20:29:47.558862 end: 3.1 lava-test-shell (duration 00:01:27) [common]
2371 20:29:47.559314 end: 3 lava-test-retry (duration 00:01:27) [common]
2372 20:29:47.559635 start: 4 finalize (timeout 00:05:25) [common]
2373 20:29:47.559947 start: 4.1 power-off (timeout 00:00:30) [common]
2374 20:29:47.560669 Calling: 'curl' 'http://conserv3.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=beaglebone-black-05'
2375 20:29:47.596239 >> OK - accepted request
2376 20:29:47.598127 Returned 0 in 0 seconds
2377 20:29:47.699048 end: 4.1 power-off (duration 00:00:00) [common]
2379 20:29:47.700780 start: 4.2 read-feedback (timeout 00:05:25) [common]
2380 20:29:47.701979 Listened to connection for namespace 'common' for up to 1s
2381 20:29:47.702867 Listened to connection for namespace 'common' for up to 1s
2382 20:29:48.702052 Finalising connection for namespace 'common'
2383 20:29:48.703047 Disconnecting from shell: Finalise
2384 20:29:48.703757 / #
2385 20:29:48.805158 end: 4.2 read-feedback (duration 00:00:01) [common]
2386 20:29:48.806232 end: 4 finalize (duration 00:00:01) [common]
2387 20:29:48.807117 Cleaning after the job
2388 20:29:48.807951 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955215/tftp-deploy-b7zdcl50/ramdisk
2389 20:29:48.818825 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955215/tftp-deploy-b7zdcl50/kernel
2390 20:29:48.827111 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955215/tftp-deploy-b7zdcl50/dtb
2391 20:29:48.828799 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955215/tftp-deploy-b7zdcl50/nfsrootfs
2392 20:29:48.988773 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/955215/tftp-deploy-b7zdcl50/modules
2393 20:29:49.001518 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/955215
2394 20:29:52.176431 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/955215
2395 20:29:52.177010 Job finished correctly