Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 04:03:04.765082 lava-dispatcher, installed at version: 2024.01
2 04:03:04.765878 start: 0 validate
3 04:03:04.766352 Start time: 2024-11-08 04:03:04.766321+00:00 (UTC)
4 04:03:04.766905 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 04:03:04.767443 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 04:03:04.802142 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 04:03:04.802685 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-574-g603e41d0858f1%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 04:03:04.835395 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 04:03:04.836020 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-574-g603e41d0858f1%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 04:03:04.862857 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 04:03:04.863349 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-574-g603e41d0858f1%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 04:03:04.895872 validate duration: 0.13
14 04:03:04.896718 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 04:03:04.897047 start: 1.1 download-retry (timeout 00:10:00) [common]
16 04:03:04.897337 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 04:03:04.897896 Not decompressing ramdisk as can be used compressed.
18 04:03:04.898323 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 04:03:04.898561 saving as /var/lib/lava/dispatcher/tmp/957576/tftp-deploy-7h6ljksr/ramdisk/rootfs.cpio.gz
20 04:03:04.898810 total size: 47897469 (45 MB)
21 04:03:04.936460 progress 0 % (0 MB)
22 04:03:04.966759 progress 5 % (2 MB)
23 04:03:04.996072 progress 10 % (4 MB)
24 04:03:05.025414 progress 15 % (6 MB)
25 04:03:05.054568 progress 20 % (9 MB)
26 04:03:05.083687 progress 25 % (11 MB)
27 04:03:05.113143 progress 30 % (13 MB)
28 04:03:05.142191 progress 35 % (16 MB)
29 04:03:05.171045 progress 40 % (18 MB)
30 04:03:05.200120 progress 45 % (20 MB)
31 04:03:05.229065 progress 50 % (22 MB)
32 04:03:05.257798 progress 55 % (25 MB)
33 04:03:05.286893 progress 60 % (27 MB)
34 04:03:05.315771 progress 65 % (29 MB)
35 04:03:05.344566 progress 70 % (32 MB)
36 04:03:05.373319 progress 75 % (34 MB)
37 04:03:05.402278 progress 80 % (36 MB)
38 04:03:05.431206 progress 85 % (38 MB)
39 04:03:05.459952 progress 90 % (41 MB)
40 04:03:05.488726 progress 95 % (43 MB)
41 04:03:05.517073 progress 100 % (45 MB)
42 04:03:05.517824 45 MB downloaded in 0.62 s (73.80 MB/s)
43 04:03:05.518373 end: 1.1.1 http-download (duration 00:00:01) [common]
45 04:03:05.519258 end: 1.1 download-retry (duration 00:00:01) [common]
46 04:03:05.519550 start: 1.2 download-retry (timeout 00:09:59) [common]
47 04:03:05.519821 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 04:03:05.520315 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-574-g603e41d0858f1/arm64/defconfig/gcc-12/kernel/Image
49 04:03:05.520562 saving as /var/lib/lava/dispatcher/tmp/957576/tftp-deploy-7h6ljksr/kernel/Image
50 04:03:05.520771 total size: 45713920 (43 MB)
51 04:03:05.520983 No compression specified
52 04:03:05.554711 progress 0 % (0 MB)
53 04:03:05.582312 progress 5 % (2 MB)
54 04:03:05.609722 progress 10 % (4 MB)
55 04:03:05.637114 progress 15 % (6 MB)
56 04:03:05.664366 progress 20 % (8 MB)
57 04:03:05.691246 progress 25 % (10 MB)
58 04:03:05.718369 progress 30 % (13 MB)
59 04:03:05.745743 progress 35 % (15 MB)
60 04:03:05.773078 progress 40 % (17 MB)
61 04:03:05.800234 progress 45 % (19 MB)
62 04:03:05.827952 progress 50 % (21 MB)
63 04:03:05.855546 progress 55 % (24 MB)
64 04:03:05.883190 progress 60 % (26 MB)
65 04:03:05.910380 progress 65 % (28 MB)
66 04:03:05.937694 progress 70 % (30 MB)
67 04:03:05.965114 progress 75 % (32 MB)
68 04:03:05.992459 progress 80 % (34 MB)
69 04:03:06.020233 progress 85 % (37 MB)
70 04:03:06.047587 progress 90 % (39 MB)
71 04:03:06.074723 progress 95 % (41 MB)
72 04:03:06.101587 progress 100 % (43 MB)
73 04:03:06.102126 43 MB downloaded in 0.58 s (74.99 MB/s)
74 04:03:06.102608 end: 1.2.1 http-download (duration 00:00:01) [common]
76 04:03:06.103414 end: 1.2 download-retry (duration 00:00:01) [common]
77 04:03:06.103686 start: 1.3 download-retry (timeout 00:09:59) [common]
78 04:03:06.103948 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 04:03:06.104444 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-574-g603e41d0858f1/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 04:03:06.104715 saving as /var/lib/lava/dispatcher/tmp/957576/tftp-deploy-7h6ljksr/dtb/meson-g12b-a311d-libretech-cc.dtb
81 04:03:06.104923 total size: 54703 (0 MB)
82 04:03:06.105133 No compression specified
83 04:03:06.146227 progress 59 % (0 MB)
84 04:03:06.147118 progress 100 % (0 MB)
85 04:03:06.147676 0 MB downloaded in 0.04 s (1.22 MB/s)
86 04:03:06.148184 end: 1.3.1 http-download (duration 00:00:00) [common]
88 04:03:06.149006 end: 1.3 download-retry (duration 00:00:00) [common]
89 04:03:06.149266 start: 1.4 download-retry (timeout 00:09:59) [common]
90 04:03:06.149529 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 04:03:06.149986 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-574-g603e41d0858f1/arm64/defconfig/gcc-12/modules.tar.xz
92 04:03:06.150227 saving as /var/lib/lava/dispatcher/tmp/957576/tftp-deploy-7h6ljksr/modules/modules.tar
93 04:03:06.150431 total size: 11610020 (11 MB)
94 04:03:06.150642 Using unxz to decompress xz
95 04:03:06.191254 progress 0 % (0 MB)
96 04:03:06.256802 progress 5 % (0 MB)
97 04:03:06.330767 progress 10 % (1 MB)
98 04:03:06.426265 progress 15 % (1 MB)
99 04:03:06.522136 progress 20 % (2 MB)
100 04:03:06.602441 progress 25 % (2 MB)
101 04:03:06.678037 progress 30 % (3 MB)
102 04:03:06.756107 progress 35 % (3 MB)
103 04:03:06.828718 progress 40 % (4 MB)
104 04:03:06.904297 progress 45 % (5 MB)
105 04:03:06.988212 progress 50 % (5 MB)
106 04:03:07.066252 progress 55 % (6 MB)
107 04:03:07.151125 progress 60 % (6 MB)
108 04:03:07.231458 progress 65 % (7 MB)
109 04:03:07.312789 progress 70 % (7 MB)
110 04:03:07.391673 progress 75 % (8 MB)
111 04:03:07.476288 progress 80 % (8 MB)
112 04:03:07.556584 progress 85 % (9 MB)
113 04:03:07.637109 progress 90 % (9 MB)
114 04:03:07.716290 progress 95 % (10 MB)
115 04:03:07.794215 progress 100 % (11 MB)
116 04:03:07.805680 11 MB downloaded in 1.66 s (6.69 MB/s)
117 04:03:07.806447 end: 1.4.1 http-download (duration 00:00:02) [common]
119 04:03:07.808351 end: 1.4 download-retry (duration 00:00:02) [common]
120 04:03:07.808967 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 04:03:07.809565 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 04:03:07.810136 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 04:03:07.810710 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 04:03:07.811798 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr
125 04:03:07.812820 makedir: /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin
126 04:03:07.813599 makedir: /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/tests
127 04:03:07.814316 makedir: /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/results
128 04:03:07.815023 Creating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin/lava-add-keys
129 04:03:07.816146 Creating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin/lava-add-sources
130 04:03:07.817224 Creating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin/lava-background-process-start
131 04:03:07.818315 Creating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin/lava-background-process-stop
132 04:03:07.819443 Creating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin/lava-common-functions
133 04:03:07.820532 Creating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin/lava-echo-ipv4
134 04:03:07.821590 Creating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin/lava-install-packages
135 04:03:07.822643 Creating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin/lava-installed-packages
136 04:03:07.823732 Creating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin/lava-os-build
137 04:03:07.824877 Creating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin/lava-probe-channel
138 04:03:07.825936 Creating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin/lava-probe-ip
139 04:03:07.826985 Creating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin/lava-target-ip
140 04:03:07.828118 Creating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin/lava-target-mac
141 04:03:07.829212 Creating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin/lava-target-storage
142 04:03:07.830302 Creating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin/lava-test-case
143 04:03:07.831348 Creating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin/lava-test-event
144 04:03:07.832521 Creating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin/lava-test-feedback
145 04:03:07.833588 Creating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin/lava-test-raise
146 04:03:07.834643 Creating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin/lava-test-reference
147 04:03:07.835708 Creating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin/lava-test-runner
148 04:03:07.836810 Creating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin/lava-test-set
149 04:03:07.837853 Creating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin/lava-test-shell
150 04:03:07.838900 Updating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin/lava-install-packages (oe)
151 04:03:07.840085 Updating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/bin/lava-installed-packages (oe)
152 04:03:07.841066 Creating /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/environment
153 04:03:07.841896 LAVA metadata
154 04:03:07.842476 - LAVA_JOB_ID=957576
155 04:03:07.842970 - LAVA_DISPATCHER_IP=192.168.6.2
156 04:03:07.843734 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 04:03:07.845667 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 04:03:07.846306 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 04:03:07.846750 skipped lava-vland-overlay
160 04:03:07.847255 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 04:03:07.847782 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 04:03:07.848262 skipped lava-multinode-overlay
163 04:03:07.848781 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 04:03:07.849306 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 04:03:07.849796 Loading test definitions
166 04:03:07.850361 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 04:03:07.850816 Using /lava-957576 at stage 0
168 04:03:07.852600 uuid=957576_1.5.2.4.1 testdef=None
169 04:03:07.852956 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 04:03:07.853262 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 04:03:07.855044 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 04:03:07.855910 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 04:03:07.858163 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 04:03:07.859104 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 04:03:07.861306 runner path: /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/0/tests/0_igt-gpu-panfrost test_uuid 957576_1.5.2.4.1
178 04:03:07.861925 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 04:03:07.862807 Creating lava-test-runner.conf files
181 04:03:07.863040 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/957576/lava-overlay-6xb_ljtr/lava-957576/0 for stage 0
182 04:03:07.863415 - 0_igt-gpu-panfrost
183 04:03:07.863824 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 04:03:07.864174 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 04:03:07.887442 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 04:03:07.887874 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 04:03:07.888228 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 04:03:07.888532 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 04:03:07.888823 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 04:03:15.155673 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 04:03:15.156275 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 04:03:15.156748 extracting modules file /var/lib/lava/dispatcher/tmp/957576/tftp-deploy-7h6ljksr/modules/modules.tar to /var/lib/lava/dispatcher/tmp/957576/extract-overlay-ramdisk-onec7z4r/ramdisk
193 04:03:16.543611 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 04:03:16.544128 start: 1.5.5 apply-overlay-tftp (timeout 00:09:48) [common]
195 04:03:16.544412 [common] Applying overlay /var/lib/lava/dispatcher/tmp/957576/compress-overlay-wrpofkn0/overlay-1.5.2.5.tar.gz to ramdisk
196 04:03:16.544628 [common] Applying overlay /var/lib/lava/dispatcher/tmp/957576/compress-overlay-wrpofkn0/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/957576/extract-overlay-ramdisk-onec7z4r/ramdisk
197 04:03:16.574338 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 04:03:16.574754 start: 1.5.6 prepare-kernel (timeout 00:09:48) [common]
199 04:03:16.575025 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:48) [common]
200 04:03:16.575252 Converting downloaded kernel to a uImage
201 04:03:16.575555 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/957576/tftp-deploy-7h6ljksr/kernel/Image /var/lib/lava/dispatcher/tmp/957576/tftp-deploy-7h6ljksr/kernel/uImage
202 04:03:17.047021 output: Image Name:
203 04:03:17.047403 output: Created: Fri Nov 8 04:03:16 2024
204 04:03:17.047614 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 04:03:17.047818 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 04:03:17.048059 output: Load Address: 01080000
207 04:03:17.048264 output: Entry Point: 01080000
208 04:03:17.048464 output:
209 04:03:17.048796 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 04:03:17.049061 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 04:03:17.049327 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 04:03:17.049578 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 04:03:17.049833 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 04:03:17.050084 Building ramdisk /var/lib/lava/dispatcher/tmp/957576/extract-overlay-ramdisk-onec7z4r/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/957576/extract-overlay-ramdisk-onec7z4r/ramdisk
215 04:03:23.532336 >> 502412 blocks
216 04:03:44.133771 Adding RAMdisk u-boot header.
217 04:03:44.134440 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/957576/extract-overlay-ramdisk-onec7z4r/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/957576/extract-overlay-ramdisk-onec7z4r/ramdisk.cpio.gz.uboot
218 04:03:44.781434 output: Image Name:
219 04:03:44.781891 output: Created: Fri Nov 8 04:03:44 2024
220 04:03:44.782375 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 04:03:44.782831 output: Data Size: 65714345 Bytes = 64174.17 KiB = 62.67 MiB
222 04:03:44.783298 output: Load Address: 00000000
223 04:03:44.783742 output: Entry Point: 00000000
224 04:03:44.784238 output:
225 04:03:44.785268 rename /var/lib/lava/dispatcher/tmp/957576/extract-overlay-ramdisk-onec7z4r/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/957576/tftp-deploy-7h6ljksr/ramdisk/ramdisk.cpio.gz.uboot
226 04:03:44.786036 end: 1.5.8 compress-ramdisk (duration 00:00:28) [common]
227 04:03:44.786636 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 04:03:44.787219 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 04:03:44.787720 No LXC device requested
230 04:03:44.788320 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 04:03:44.788885 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 04:03:44.789433 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 04:03:44.789884 Checking files for TFTP limit of 4294967296 bytes.
234 04:03:44.792803 end: 1 tftp-deploy (duration 00:00:40) [common]
235 04:03:44.793434 start: 2 uboot-action (timeout 00:05:00) [common]
236 04:03:44.794021 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 04:03:44.794574 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 04:03:44.795134 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 04:03:44.795719 Using kernel file from prepare-kernel: 957576/tftp-deploy-7h6ljksr/kernel/uImage
240 04:03:44.796460 substitutions:
241 04:03:44.796924 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 04:03:44.797373 - {DTB_ADDR}: 0x01070000
243 04:03:44.797816 - {DTB}: 957576/tftp-deploy-7h6ljksr/dtb/meson-g12b-a311d-libretech-cc.dtb
244 04:03:44.798262 - {INITRD}: 957576/tftp-deploy-7h6ljksr/ramdisk/ramdisk.cpio.gz.uboot
245 04:03:44.798703 - {KERNEL_ADDR}: 0x01080000
246 04:03:44.799146 - {KERNEL}: 957576/tftp-deploy-7h6ljksr/kernel/uImage
247 04:03:44.799588 - {LAVA_MAC}: None
248 04:03:44.800098 - {PRESEED_CONFIG}: None
249 04:03:44.800544 - {PRESEED_LOCAL}: None
250 04:03:44.800979 - {RAMDISK_ADDR}: 0x08000000
251 04:03:44.801412 - {RAMDISK}: 957576/tftp-deploy-7h6ljksr/ramdisk/ramdisk.cpio.gz.uboot
252 04:03:44.801851 - {ROOT_PART}: None
253 04:03:44.802284 - {ROOT}: None
254 04:03:44.802715 - {SERVER_IP}: 192.168.6.2
255 04:03:44.803153 - {TEE_ADDR}: 0x83000000
256 04:03:44.803583 - {TEE}: None
257 04:03:44.804040 Parsed boot commands:
258 04:03:44.804469 - setenv autoload no
259 04:03:44.804900 - setenv initrd_high 0xffffffff
260 04:03:44.805327 - setenv fdt_high 0xffffffff
261 04:03:44.805752 - dhcp
262 04:03:44.806184 - setenv serverip 192.168.6.2
263 04:03:44.806613 - tftpboot 0x01080000 957576/tftp-deploy-7h6ljksr/kernel/uImage
264 04:03:44.807049 - tftpboot 0x08000000 957576/tftp-deploy-7h6ljksr/ramdisk/ramdisk.cpio.gz.uboot
265 04:03:44.807482 - tftpboot 0x01070000 957576/tftp-deploy-7h6ljksr/dtb/meson-g12b-a311d-libretech-cc.dtb
266 04:03:44.807915 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 04:03:44.808388 - bootm 0x01080000 0x08000000 0x01070000
268 04:03:44.808937 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 04:03:44.810615 start: 2.3 connect-device (timeout 00:05:00) [common]
271 04:03:44.811104 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 04:03:44.825530 Setting prompt string to ['lava-test: # ']
273 04:03:44.827093 end: 2.3 connect-device (duration 00:00:00) [common]
274 04:03:44.827758 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 04:03:44.828493 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 04:03:44.829228 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 04:03:44.830551 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 04:03:44.865934 >> OK - accepted request
279 04:03:44.868084 Returned 0 in 0 seconds
280 04:03:44.969282 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 04:03:44.970992 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 04:03:44.971621 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 04:03:44.972230 Setting prompt string to ['Hit any key to stop autoboot']
285 04:03:44.972744 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 04:03:44.974475 Trying 192.168.56.21...
287 04:03:44.974994 Connected to conserv1.
288 04:03:44.975472 Escape character is '^]'.
289 04:03:44.976069
290 04:03:44.976570 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 04:03:44.977053
292 04:03:55.542795 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 04:03:55.543485 bl2_stage_init 0x01
294 04:03:55.543965 bl2_stage_init 0x81
295 04:03:55.548353 hw id: 0x0000 - pwm id 0x01
296 04:03:55.548933 bl2_stage_init 0xc1
297 04:03:55.549392 bl2_stage_init 0x02
298 04:03:55.549842
299 04:03:55.554008 L0:00000000
300 04:03:55.554496 L1:20000703
301 04:03:55.554940 L2:00008067
302 04:03:55.555371 L3:14000000
303 04:03:55.556765 B2:00402000
304 04:03:55.557247 B1:e0f83180
305 04:03:55.557689
306 04:03:55.558124 TE: 58124
307 04:03:55.558553
308 04:03:55.567941 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 04:03:55.568447
310 04:03:55.568882 Board ID = 1
311 04:03:55.569309 Set A53 clk to 24M
312 04:03:55.569739 Set A73 clk to 24M
313 04:03:55.573565 Set clk81 to 24M
314 04:03:55.574039 A53 clk: 1200 MHz
315 04:03:55.574469 A73 clk: 1200 MHz
316 04:03:55.579131 CLK81: 166.6M
317 04:03:55.579589 smccc: 00012a92
318 04:03:55.584750 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 04:03:55.585215 board id: 1
320 04:03:55.593371 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 04:03:55.604051 fw parse done
322 04:03:55.610034 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 04:03:55.652658 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 04:03:55.663495 PIEI prepare done
325 04:03:55.663948 fastboot data load
326 04:03:55.664432 fastboot data verify
327 04:03:55.669089 verify result: 266
328 04:03:55.674735 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 04:03:55.675200 LPDDR4 probe
330 04:03:55.675632 ddr clk to 1584MHz
331 04:03:55.682689 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 04:03:55.719940
333 04:03:55.720438 dmc_version 0001
334 04:03:55.726681 Check phy result
335 04:03:55.732458 INFO : End of CA training
336 04:03:55.732919 INFO : End of initialization
337 04:03:55.738117 INFO : Training has run successfully!
338 04:03:55.738576 Check phy result
339 04:03:55.743698 INFO : End of initialization
340 04:03:55.744234 INFO : End of read enable training
341 04:03:55.749275 INFO : End of fine write leveling
342 04:03:55.754983 INFO : End of Write leveling coarse delay
343 04:03:55.755437 INFO : Training has run successfully!
344 04:03:55.755869 Check phy result
345 04:03:55.760479 INFO : End of initialization
346 04:03:55.760935 INFO : End of read dq deskew training
347 04:03:55.766078 INFO : End of MPR read delay center optimization
348 04:03:55.771667 INFO : End of write delay center optimization
349 04:03:55.777292 INFO : End of read delay center optimization
350 04:03:55.777766 INFO : End of max read latency training
351 04:03:55.782980 INFO : Training has run successfully!
352 04:03:55.783434 1D training succeed
353 04:03:55.792094 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 04:03:55.839739 Check phy result
355 04:03:55.840247 INFO : End of initialization
356 04:03:55.861160 INFO : End of 2D read delay Voltage center optimization
357 04:03:55.881426 INFO : End of 2D read delay Voltage center optimization
358 04:03:55.933261 INFO : End of 2D write delay Voltage center optimization
359 04:03:55.983430 INFO : End of 2D write delay Voltage center optimization
360 04:03:55.989030 INFO : Training has run successfully!
361 04:03:55.989495
362 04:03:55.989930 channel==0
363 04:03:55.994537 RxClkDly_Margin_A0==88 ps 9
364 04:03:55.994992 TxDqDly_Margin_A0==98 ps 10
365 04:03:56.000194 RxClkDly_Margin_A1==78 ps 8
366 04:03:56.000652 TxDqDly_Margin_A1==98 ps 10
367 04:03:56.001087 TrainedVREFDQ_A0==74
368 04:03:56.005716 TrainedVREFDQ_A1==74
369 04:03:56.006175 VrefDac_Margin_A0==25
370 04:03:56.006603 DeviceVref_Margin_A0==40
371 04:03:56.011317 VrefDac_Margin_A1==26
372 04:03:56.011769 DeviceVref_Margin_A1==40
373 04:03:56.012250
374 04:03:56.012688
375 04:03:56.017014 channel==1
376 04:03:56.017468 RxClkDly_Margin_A0==98 ps 10
377 04:03:56.017898 TxDqDly_Margin_A0==98 ps 10
378 04:03:56.022611 RxClkDly_Margin_A1==98 ps 10
379 04:03:56.023073 TxDqDly_Margin_A1==88 ps 9
380 04:03:56.028253 TrainedVREFDQ_A0==77
381 04:03:56.028715 TrainedVREFDQ_A1==77
382 04:03:56.029150 VrefDac_Margin_A0==22
383 04:03:56.033802 DeviceVref_Margin_A0==37
384 04:03:56.034256 VrefDac_Margin_A1==22
385 04:03:56.039321 DeviceVref_Margin_A1==37
386 04:03:56.039777
387 04:03:56.040254 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 04:03:56.045003
389 04:03:56.073024 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 04:03:56.073581 2D training succeed
391 04:03:56.078500 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 04:03:56.084200 auto size-- 65535DDR cs0 size: 2048MB
393 04:03:56.084661 DDR cs1 size: 2048MB
394 04:03:56.089762 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 04:03:56.090216 cs0 DataBus test pass
396 04:03:56.095337 cs1 DataBus test pass
397 04:03:56.095792 cs0 AddrBus test pass
398 04:03:56.096260 cs1 AddrBus test pass
399 04:03:56.096689
400 04:03:56.101040 100bdlr_step_size ps== 420
401 04:03:56.101508 result report
402 04:03:56.106573 boot times 0Enable ddr reg access
403 04:03:56.112102 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 04:03:56.125440 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 04:03:56.697571 0.0;M3 CHK:0;cm4_sp_mode 0
406 04:03:56.698205 MVN_1=0x00000000
407 04:03:56.702976 MVN_2=0x00000000
408 04:03:56.708739 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 04:03:56.709212 OPS=0x10
410 04:03:56.709666 ring efuse init
411 04:03:56.710109 chipver efuse init
412 04:03:56.714303 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 04:03:56.719924 [0.018961 Inits done]
414 04:03:56.720431 secure task start!
415 04:03:56.720876 high task start!
416 04:03:56.724498 low task start!
417 04:03:56.724982 run into bl31
418 04:03:56.731144 NOTICE: BL31: v1.3(release):4fc40b1
419 04:03:56.738956 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 04:03:56.739431 NOTICE: BL31: G12A normal boot!
421 04:03:56.764298 NOTICE: BL31: BL33 decompress pass
422 04:03:56.769991 ERROR: Error initializing runtime service opteed_fast
423 04:03:58.002992
424 04:03:58.003608
425 04:03:58.011448 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 04:03:58.012060
427 04:03:58.012530 Model: Libre Computer AML-A311D-CC Alta
428 04:03:58.219945 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 04:03:58.243114 DRAM: 2 GiB (effective 3.8 GiB)
430 04:03:58.386129 Core: 408 devices, 31 uclasses, devicetree: separate
431 04:03:58.391933 WDT: Not starting watchdog@f0d0
432 04:03:58.424349 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 04:03:58.436644 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 04:03:58.440709 ** Bad device specification mmc 0 **
435 04:03:58.452100 Card did not respond to voltage select! : -110
436 04:03:58.458861 ** Bad device specification mmc 0 **
437 04:03:58.459321 Couldn't find partition mmc 0
438 04:03:58.468108 Card did not respond to voltage select! : -110
439 04:03:58.473524 ** Bad device specification mmc 0 **
440 04:03:58.473952 Couldn't find partition mmc 0
441 04:03:58.477668 Error: could not access storage.
442 04:03:59.742965 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
443 04:03:59.743535 bl2_stage_init 0x01
444 04:03:59.743960 bl2_stage_init 0x81
445 04:03:59.748517 hw id: 0x0000 - pwm id 0x01
446 04:03:59.748953 bl2_stage_init 0xc1
447 04:03:59.749361 bl2_stage_init 0x02
448 04:03:59.749760
449 04:03:59.754124 L0:00000000
450 04:03:59.754549 L1:20000703
451 04:03:59.754951 L2:00008067
452 04:03:59.755348 L3:14000000
453 04:03:59.759718 B2:00402000
454 04:03:59.760182 B1:e0f83180
455 04:03:59.760585
456 04:03:59.760986 TE: 58167
457 04:03:59.761384
458 04:03:59.765315 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
459 04:03:59.765802
460 04:03:59.766210 Board ID = 1
461 04:03:59.770929 Set A53 clk to 24M
462 04:03:59.771356 Set A73 clk to 24M
463 04:03:59.771759 Set clk81 to 24M
464 04:03:59.776522 A53 clk: 1200 MHz
465 04:03:59.776976 A73 clk: 1200 MHz
466 04:03:59.777377 CLK81: 166.6M
467 04:03:59.777772 smccc: 00012abe
468 04:03:59.782125 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
469 04:03:59.787709 board id: 1
470 04:03:59.793601 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
471 04:03:59.804251 fw parse done
472 04:03:59.810212 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
473 04:03:59.852862 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
474 04:03:59.863768 PIEI prepare done
475 04:03:59.864237 fastboot data load
476 04:03:59.864647 fastboot data verify
477 04:03:59.869354 verify result: 266
478 04:03:59.874945 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
479 04:03:59.875380 LPDDR4 probe
480 04:03:59.875781 ddr clk to 1584MHz
481 04:03:59.883095 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
482 04:03:59.920032
483 04:03:59.920459 dmc_version 0001
484 04:03:59.927056 Check phy result
485 04:03:59.932816 INFO : End of CA training
486 04:03:59.933239 INFO : End of initialization
487 04:03:59.938449 INFO : Training has run successfully!
488 04:03:59.938871 Check phy result
489 04:03:59.944071 INFO : End of initialization
490 04:03:59.944489 INFO : End of read enable training
491 04:03:59.947340 INFO : End of fine write leveling
492 04:03:59.952926 INFO : End of Write leveling coarse delay
493 04:03:59.958962 INFO : Training has run successfully!
494 04:03:59.959382 Check phy result
495 04:03:59.959782 INFO : End of initialization
496 04:03:59.964337 INFO : End of read dq deskew training
497 04:03:59.969810 INFO : End of MPR read delay center optimization
498 04:03:59.970231 INFO : End of write delay center optimization
499 04:03:59.975399 INFO : End of read delay center optimization
500 04:03:59.981036 INFO : End of max read latency training
501 04:03:59.981457 INFO : Training has run successfully!
502 04:03:59.986589 1D training succeed
503 04:03:59.992376 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
504 04:04:00.040082 Check phy result
505 04:04:00.040537 INFO : End of initialization
506 04:04:00.061596 INFO : End of 2D read delay Voltage center optimization
507 04:04:00.080811 INFO : End of 2D read delay Voltage center optimization
508 04:04:00.132874 INFO : End of 2D write delay Voltage center optimization
509 04:04:00.182014 INFO : End of 2D write delay Voltage center optimization
510 04:04:00.187699 INFO : Training has run successfully!
511 04:04:00.188171
512 04:04:00.188582 channel==0
513 04:04:00.193156 RxClkDly_Margin_A0==88 ps 9
514 04:04:00.193581 TxDqDly_Margin_A0==98 ps 10
515 04:04:00.198823 RxClkDly_Margin_A1==88 ps 9
516 04:04:00.199248 TxDqDly_Margin_A1==98 ps 10
517 04:04:00.199651 TrainedVREFDQ_A0==74
518 04:04:00.204517 TrainedVREFDQ_A1==74
519 04:04:00.204957 VrefDac_Margin_A0==25
520 04:04:00.205361 DeviceVref_Margin_A0==40
521 04:04:00.210099 VrefDac_Margin_A1==25
522 04:04:00.210523 DeviceVref_Margin_A1==40
523 04:04:00.210923
524 04:04:00.211321
525 04:04:00.215725 channel==1
526 04:04:00.216188 RxClkDly_Margin_A0==88 ps 9
527 04:04:00.216590 TxDqDly_Margin_A0==98 ps 10
528 04:04:00.221179 RxClkDly_Margin_A1==88 ps 9
529 04:04:00.221599 TxDqDly_Margin_A1==88 ps 9
530 04:04:00.226807 TrainedVREFDQ_A0==77
531 04:04:00.227234 TrainedVREFDQ_A1==77
532 04:04:00.227638 VrefDac_Margin_A0==22
533 04:04:00.232338 DeviceVref_Margin_A0==37
534 04:04:00.232763 VrefDac_Margin_A1==24
535 04:04:00.237924 DeviceVref_Margin_A1==37
536 04:04:00.238338
537 04:04:00.238741 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
538 04:04:00.239136
539 04:04:00.271620 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000016 00000018 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
540 04:04:00.272101 2D training succeed
541 04:04:00.277107 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
542 04:04:00.282686 auto size-- 65535DDR cs0 size: 2048MB
543 04:04:00.283112 DDR cs1 size: 2048MB
544 04:04:00.288258 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
545 04:04:00.288681 cs0 DataBus test pass
546 04:04:00.293855 cs1 DataBus test pass
547 04:04:00.294284 cs0 AddrBus test pass
548 04:04:00.294685 cs1 AddrBus test pass
549 04:04:00.295090
550 04:04:00.299477 100bdlr_step_size ps== 420
551 04:04:00.299915 result report
552 04:04:00.305050 boot times 0Enable ddr reg access
553 04:04:00.310349 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
554 04:04:00.323785 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
555 04:04:00.895963 0.0;M3 CHK:0;cm4_sp_mode 0
556 04:04:00.896632 MVN_1=0x00000000
557 04:04:00.901322 MVN_2=0x00000000
558 04:04:00.907083 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
559 04:04:00.907570 OPS=0x10
560 04:04:00.908047 ring efuse init
561 04:04:00.908464 chipver efuse init
562 04:04:00.912691 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
563 04:04:00.918323 [0.018960 Inits done]
564 04:04:00.918780 secure task start!
565 04:04:00.919167 high task start!
566 04:04:00.922871 low task start!
567 04:04:00.923291 run into bl31
568 04:04:00.929506 NOTICE: BL31: v1.3(release):4fc40b1
569 04:04:00.937375 NOTICE: BL31: Built : 15:58:17, May 22 2019
570 04:04:00.937798 NOTICE: BL31: G12A normal boot!
571 04:04:00.962689 NOTICE: BL31: BL33 decompress pass
572 04:04:00.968393 ERROR: Error initializing runtime service opteed_fast
573 04:04:02.201277
574 04:04:02.201868
575 04:04:02.209620 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
576 04:04:02.210070
577 04:04:02.210489 Model: Libre Computer AML-A311D-CC Alta
578 04:04:02.418224 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
579 04:04:02.441401 DRAM: 2 GiB (effective 3.8 GiB)
580 04:04:02.584534 Core: 408 devices, 31 uclasses, devicetree: separate
581 04:04:02.590262 WDT: Not starting watchdog@f0d0
582 04:04:02.622565 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
583 04:04:02.635023 Loading Environment from FAT... Card did not respond to voltage select! : -110
584 04:04:02.640037 ** Bad device specification mmc 0 **
585 04:04:02.650329 Card did not respond to voltage select! : -110
586 04:04:02.657986 ** Bad device specification mmc 0 **
587 04:04:02.658417 Couldn't find partition mmc 0
588 04:04:02.666315 Card did not respond to voltage select! : -110
589 04:04:02.671842 ** Bad device specification mmc 0 **
590 04:04:02.672311 Couldn't find partition mmc 0
591 04:04:02.676925 Error: could not access storage.
592 04:04:03.019417 Net: eth0: ethernet@ff3f0000
593 04:04:03.019926 starting USB...
594 04:04:03.271223 Bus usb@ff500000: Register 3000140 NbrPorts 3
595 04:04:03.271838 Starting the controller
596 04:04:03.278271 USB XHCI 1.10
597 04:04:04.993184 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
598 04:04:04.993799 bl2_stage_init 0x01
599 04:04:04.994225 bl2_stage_init 0x81
600 04:04:04.998760 hw id: 0x0000 - pwm id 0x01
601 04:04:04.999201 bl2_stage_init 0xc1
602 04:04:04.999610 bl2_stage_init 0x02
603 04:04:05.000073
604 04:04:05.004316 L0:00000000
605 04:04:05.004758 L1:20000703
606 04:04:05.005164 L2:00008067
607 04:04:05.005560 L3:14000000
608 04:04:05.007218 B2:00402000
609 04:04:05.007646 B1:e0f83180
610 04:04:05.008077
611 04:04:05.008483 TE: 58159
612 04:04:05.008887
613 04:04:05.018455 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
614 04:04:05.018987
615 04:04:05.019403 Board ID = 1
616 04:04:05.019815 Set A53 clk to 24M
617 04:04:05.020263 Set A73 clk to 24M
618 04:04:05.024073 Set clk81 to 24M
619 04:04:05.024516 A53 clk: 1200 MHz
620 04:04:05.024922 A73 clk: 1200 MHz
621 04:04:05.029652 CLK81: 166.6M
622 04:04:05.030085 smccc: 00012ab5
623 04:04:05.035203 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
624 04:04:05.035636 board id: 1
625 04:04:05.043815 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
626 04:04:05.054455 fw parse done
627 04:04:05.060412 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
628 04:04:05.103119 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
629 04:04:05.114050 PIEI prepare done
630 04:04:05.114482 fastboot data load
631 04:04:05.114887 fastboot data verify
632 04:04:05.119573 verify result: 266
633 04:04:05.125199 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
634 04:04:05.125635 LPDDR4 probe
635 04:04:05.126037 ddr clk to 1584MHz
636 04:04:05.133188 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
637 04:04:05.170462
638 04:04:05.170910 dmc_version 0001
639 04:04:05.177159 Check phy result
640 04:04:05.183079 INFO : End of CA training
641 04:04:05.183507 INFO : End of initialization
642 04:04:05.188587 INFO : Training has run successfully!
643 04:04:05.189024 Check phy result
644 04:04:05.194163 INFO : End of initialization
645 04:04:05.194588 INFO : End of read enable training
646 04:04:05.199819 INFO : End of fine write leveling
647 04:04:05.205409 INFO : End of Write leveling coarse delay
648 04:04:05.205842 INFO : Training has run successfully!
649 04:04:05.206246 Check phy result
650 04:04:05.211100 INFO : End of initialization
651 04:04:05.211528 INFO : End of read dq deskew training
652 04:04:05.216577 INFO : End of MPR read delay center optimization
653 04:04:05.222172 INFO : End of write delay center optimization
654 04:04:05.227841 INFO : End of read delay center optimization
655 04:04:05.228306 INFO : End of max read latency training
656 04:04:05.233356 INFO : Training has run successfully!
657 04:04:05.233784 1D training succeed
658 04:04:05.242565 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
659 04:04:05.290397 Check phy result
660 04:04:05.290836 INFO : End of initialization
661 04:04:05.312178 INFO : End of 2D read delay Voltage center optimization
662 04:04:05.332373 INFO : End of 2D read delay Voltage center optimization
663 04:04:05.384579 INFO : End of 2D write delay Voltage center optimization
664 04:04:05.433748 INFO : End of 2D write delay Voltage center optimization
665 04:04:05.439203 INFO : Training has run successfully!
666 04:04:05.439643
667 04:04:05.440103 channel==0
668 04:04:05.444798 RxClkDly_Margin_A0==88 ps 9
669 04:04:05.445233 TxDqDly_Margin_A0==98 ps 10
670 04:04:05.448292 RxClkDly_Margin_A1==88 ps 9
671 04:04:05.448717 TxDqDly_Margin_A1==88 ps 9
672 04:04:05.453823 TrainedVREFDQ_A0==74
673 04:04:05.454274 TrainedVREFDQ_A1==75
674 04:04:05.454680 VrefDac_Margin_A0==25
675 04:04:05.459432 DeviceVref_Margin_A0==40
676 04:04:05.459862 VrefDac_Margin_A1==25
677 04:04:05.465042 DeviceVref_Margin_A1==39
678 04:04:05.465474
679 04:04:05.465876
680 04:04:05.466273 channel==1
681 04:04:05.466664 RxClkDly_Margin_A0==88 ps 9
682 04:04:05.470651 TxDqDly_Margin_A0==98 ps 10
683 04:04:05.471081 RxClkDly_Margin_A1==98 ps 10
684 04:04:05.476184 TxDqDly_Margin_A1==108 ps 11
685 04:04:05.476612 TrainedVREFDQ_A0==77
686 04:04:05.477014 TrainedVREFDQ_A1==77
687 04:04:05.481854 VrefDac_Margin_A0==22
688 04:04:05.482276 DeviceVref_Margin_A0==37
689 04:04:05.487344 VrefDac_Margin_A1==24
690 04:04:05.487767 DeviceVref_Margin_A1==37
691 04:04:05.488209
692 04:04:05.492992 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
693 04:04:05.493422
694 04:04:05.521026 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
695 04:04:05.526677 2D training succeed
696 04:04:05.532362 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
697 04:04:05.532817 auto size-- 65535DDR cs0 size: 2048MB
698 04:04:05.537819 DDR cs1 size: 2048MB
699 04:04:05.538263 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
700 04:04:05.543434 cs0 DataBus test pass
701 04:04:05.543886 cs1 DataBus test pass
702 04:04:05.544338 cs0 AddrBus test pass
703 04:04:05.549031 cs1 AddrBus test pass
704 04:04:05.549465
705 04:04:05.549874 100bdlr_step_size ps== 420
706 04:04:05.550276 result report
707 04:04:05.554668 boot times 0Enable ddr reg access
708 04:04:05.562392 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
709 04:04:05.575738 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
710 04:04:06.149284 0.0;M3 CHK:0;cm4_sp_mode 0
711 04:04:06.149821 MVN_1=0x00000000
712 04:04:06.155911 MVN_2=0x00000000
713 04:04:06.160613 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
714 04:04:06.161091 OPS=0x10
715 04:04:06.161481 ring efuse init
716 04:04:06.161870 chipver efuse init
717 04:04:06.166209 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
718 04:04:06.171808 [0.018961 Inits done]
719 04:04:06.172263 secure task start!
720 04:04:06.172653 high task start!
721 04:04:06.176422 low task start!
722 04:04:06.176836 run into bl31
723 04:04:06.183070 NOTICE: BL31: v1.3(release):4fc40b1
724 04:04:06.190524 NOTICE: BL31: Built : 15:58:17, May 22 2019
725 04:04:06.190946 NOTICE: BL31: G12A normal boot!
726 04:04:06.216758 NOTICE: BL31: BL33 decompress pass
727 04:04:06.222414 ERROR: Error initializing runtime service opteed_fast
728 04:04:07.455412
729 04:04:07.456081
730 04:04:07.463725 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
731 04:04:07.464194
732 04:04:07.464605 Model: Libre Computer AML-A311D-CC Alta
733 04:04:07.672265 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
734 04:04:07.694699 DRAM: 2 GiB (effective 3.8 GiB)
735 04:04:07.838581 Core: 408 devices, 31 uclasses, devicetree: separate
736 04:04:07.844546 WDT: Not starting watchdog@f0d0
737 04:04:07.876715 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
738 04:04:07.889201 Loading Environment from FAT... Card did not respond to voltage select! : -110
739 04:04:07.894170 ** Bad device specification mmc 0 **
740 04:04:07.904532 Card did not respond to voltage select! : -110
741 04:04:07.912152 ** Bad device specification mmc 0 **
742 04:04:07.912584 Couldn't find partition mmc 0
743 04:04:07.920502 Card did not respond to voltage select! : -110
744 04:04:07.925982 ** Bad device specification mmc 0 **
745 04:04:07.926406 Couldn't find partition mmc 0
746 04:04:07.931057 Error: could not access storage.
747 04:04:08.274630 Net: eth0: ethernet@ff3f0000
748 04:04:08.275146 starting USB...
749 04:04:08.526553 Bus usb@ff500000: Register 3000140 NbrPorts 3
750 04:04:08.527171 Starting the controller
751 04:04:08.533459 USB XHCI 1.10
752 04:04:10.693429 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
753 04:04:10.694033 bl2_stage_init 0x01
754 04:04:10.694451 bl2_stage_init 0x81
755 04:04:10.699004 hw id: 0x0000 - pwm id 0x01
756 04:04:10.699441 bl2_stage_init 0xc1
757 04:04:10.699846 bl2_stage_init 0x02
758 04:04:10.700301
759 04:04:10.704692 L0:00000000
760 04:04:10.705118 L1:20000703
761 04:04:10.705519 L2:00008067
762 04:04:10.705910 L3:14000000
763 04:04:10.710175 B2:00402000
764 04:04:10.710599 B1:e0f83180
765 04:04:10.710996
766 04:04:10.711392 TE: 58124
767 04:04:10.711784
768 04:04:10.715800 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
769 04:04:10.716258
770 04:04:10.716663 Board ID = 1
771 04:04:10.721379 Set A53 clk to 24M
772 04:04:10.721803 Set A73 clk to 24M
773 04:04:10.722204 Set clk81 to 24M
774 04:04:10.726988 A53 clk: 1200 MHz
775 04:04:10.727411 A73 clk: 1200 MHz
776 04:04:10.727808 CLK81: 166.6M
777 04:04:10.728245 smccc: 00012a92
778 04:04:10.732572 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
779 04:04:10.738155 board id: 1
780 04:04:10.744222 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
781 04:04:10.754642 fw parse done
782 04:04:10.760558 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
783 04:04:10.803217 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
784 04:04:10.814068 PIEI prepare done
785 04:04:10.814488 fastboot data load
786 04:04:10.814893 fastboot data verify
787 04:04:10.819764 verify result: 266
788 04:04:10.825336 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
789 04:04:10.825758 LPDDR4 probe
790 04:04:10.826152 ddr clk to 1584MHz
791 04:04:10.833325 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
792 04:04:10.870687
793 04:04:10.871122 dmc_version 0001
794 04:04:10.877354 Check phy result
795 04:04:10.883171 INFO : End of CA training
796 04:04:10.883613 INFO : End of initialization
797 04:04:10.888795 INFO : Training has run successfully!
798 04:04:10.889222 Check phy result
799 04:04:10.894398 INFO : End of initialization
800 04:04:10.894814 INFO : End of read enable training
801 04:04:10.900023 INFO : End of fine write leveling
802 04:04:10.905610 INFO : End of Write leveling coarse delay
803 04:04:10.906029 INFO : Training has run successfully!
804 04:04:10.906428 Check phy result
805 04:04:10.911104 INFO : End of initialization
806 04:04:10.911524 INFO : End of read dq deskew training
807 04:04:10.916807 INFO : End of MPR read delay center optimization
808 04:04:10.922351 INFO : End of write delay center optimization
809 04:04:10.928026 INFO : End of read delay center optimization
810 04:04:10.928457 INFO : End of max read latency training
811 04:04:10.933621 INFO : Training has run successfully!
812 04:04:10.934046 1D training succeed
813 04:04:10.942865 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
814 04:04:10.990307 Check phy result
815 04:04:10.990733 INFO : End of initialization
816 04:04:11.012730 INFO : End of 2D read delay Voltage center optimization
817 04:04:11.032859 INFO : End of 2D read delay Voltage center optimization
818 04:04:11.084820 INFO : End of 2D write delay Voltage center optimization
819 04:04:11.134066 INFO : End of 2D write delay Voltage center optimization
820 04:04:11.139596 INFO : Training has run successfully!
821 04:04:11.140059
822 04:04:11.140472 channel==0
823 04:04:11.145209 RxClkDly_Margin_A0==88 ps 9
824 04:04:11.145629 TxDqDly_Margin_A0==98 ps 10
825 04:04:11.148518 RxClkDly_Margin_A1==88 ps 9
826 04:04:11.148938 TxDqDly_Margin_A1==98 ps 10
827 04:04:11.154069 TrainedVREFDQ_A0==74
828 04:04:11.154491 TrainedVREFDQ_A1==75
829 04:04:11.159697 VrefDac_Margin_A0==25
830 04:04:11.160211 DeviceVref_Margin_A0==40
831 04:04:11.160627 VrefDac_Margin_A1==24
832 04:04:11.165270 DeviceVref_Margin_A1==39
833 04:04:11.165719
834 04:04:11.166109
835 04:04:11.166494 channel==1
836 04:04:11.166875 RxClkDly_Margin_A0==98 ps 10
837 04:04:11.168673 TxDqDly_Margin_A0==98 ps 10
838 04:04:11.174234 RxClkDly_Margin_A1==88 ps 9
839 04:04:11.174651 TxDqDly_Margin_A1==88 ps 9
840 04:04:11.175045 TrainedVREFDQ_A0==77
841 04:04:11.179816 TrainedVREFDQ_A1==77
842 04:04:11.180259 VrefDac_Margin_A0==22
843 04:04:11.185480 DeviceVref_Margin_A0==37
844 04:04:11.185889 VrefDac_Margin_A1==24
845 04:04:11.186272 DeviceVref_Margin_A1==37
846 04:04:11.186652
847 04:04:11.191022 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
848 04:04:11.191431
849 04:04:11.224586 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 00000019 00000016 00000019 00000017 dram_vref_reg_value 0x 0000005f
850 04:04:11.225030 2D training succeed
851 04:04:11.230188 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
852 04:04:11.235817 auto size-- 65535DDR cs0 size: 2048MB
853 04:04:11.236257 DDR cs1 size: 2048MB
854 04:04:11.241396 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
855 04:04:11.241806 cs0 DataBus test pass
856 04:04:11.242189 cs1 DataBus test pass
857 04:04:11.247026 cs0 AddrBus test pass
858 04:04:11.247432 cs1 AddrBus test pass
859 04:04:11.247817
860 04:04:11.252598 100bdlr_step_size ps== 420
861 04:04:11.253017 result report
862 04:04:11.253399 boot times 0Enable ddr reg access
863 04:04:11.262476 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
864 04:04:11.276160 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
865 04:04:11.848081 0.0;M3 CHK:0;cm4_sp_mode 0
866 04:04:11.848713 MVN_1=0x00000000
867 04:04:11.853403 MVN_2=0x00000000
868 04:04:11.859220 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
869 04:04:11.859656 OPS=0x10
870 04:04:11.860102 ring efuse init
871 04:04:11.860505 chipver efuse init
872 04:04:11.864798 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
873 04:04:11.870373 [0.018961 Inits done]
874 04:04:11.870799 secure task start!
875 04:04:11.871200 high task start!
876 04:04:11.875087 low task start!
877 04:04:11.875509 run into bl31
878 04:04:11.881612 NOTICE: BL31: v1.3(release):4fc40b1
879 04:04:11.889385 NOTICE: BL31: Built : 15:58:17, May 22 2019
880 04:04:11.889814 NOTICE: BL31: G12A normal boot!
881 04:04:11.914758 NOTICE: BL31: BL33 decompress pass
882 04:04:11.920435 ERROR: Error initializing runtime service opteed_fast
883 04:04:13.153359
884 04:04:13.153954
885 04:04:13.161704 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
886 04:04:13.162144
887 04:04:13.162554 Model: Libre Computer AML-A311D-CC Alta
888 04:04:13.370174 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
889 04:04:13.393527 DRAM: 2 GiB (effective 3.8 GiB)
890 04:04:13.536610 Core: 408 devices, 31 uclasses, devicetree: separate
891 04:04:13.542410 WDT: Not starting watchdog@f0d0
892 04:04:13.574690 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
893 04:04:13.587049 Loading Environment from FAT... Card did not respond to voltage select! : -110
894 04:04:13.592087 ** Bad device specification mmc 0 **
895 04:04:13.602417 Card did not respond to voltage select! : -110
896 04:04:13.610084 ** Bad device specification mmc 0 **
897 04:04:13.610514 Couldn't find partition mmc 0
898 04:04:13.618397 Card did not respond to voltage select! : -110
899 04:04:13.623916 ** Bad device specification mmc 0 **
900 04:04:13.624375 Couldn't find partition mmc 0
901 04:04:13.628976 Error: could not access storage.
902 04:04:13.971449 Net: eth0: ethernet@ff3f0000
903 04:04:13.971915 starting USB...
904 04:04:14.223224 Bus usb@ff500000: Register 3000140 NbrPorts 3
905 04:04:14.223698 Starting the controller
906 04:04:14.230221 USB XHCI 1.10
907 04:04:15.784597 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
908 04:04:15.792743 scanning usb for storage devices... 0 Storage Device(s) found
910 04:04:15.844252 Hit any key to stop autoboot: 1
911 04:04:15.845093 end: 2.4.2 bootloader-interrupt (duration 00:00:31) [common]
912 04:04:15.845678 start: 2.4.3 bootloader-commands (timeout 00:04:29) [common]
913 04:04:15.846149 Setting prompt string to ['=>']
914 04:04:15.846627 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:29)
915 04:04:15.860216 0
916 04:04:15.861048 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
917 04:04:15.861526 Sending with 10 millisecond of delay
919 04:04:16.996067 => setenv autoload no
920 04:04:17.006853 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:28)
921 04:04:17.011728 setenv autoload no
922 04:04:17.012474 Sending with 10 millisecond of delay
924 04:04:18.809149 => setenv initrd_high 0xffffffff
925 04:04:18.819931 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
926 04:04:18.820785 setenv initrd_high 0xffffffff
927 04:04:18.821489 Sending with 10 millisecond of delay
929 04:04:20.438461 => setenv fdt_high 0xffffffff
930 04:04:20.449311 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
931 04:04:20.450148 setenv fdt_high 0xffffffff
932 04:04:20.450895 Sending with 10 millisecond of delay
934 04:04:20.742730 => dhcp
935 04:04:20.753422 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
936 04:04:20.754236 dhcp
937 04:04:20.754698 Speed: 1000, full duplex
938 04:04:20.755141 BOOTP broadcast 1
939 04:04:20.761982 DHCP client bound to address 192.168.6.27 (8 ms)
940 04:04:20.762726 Sending with 10 millisecond of delay
942 04:04:22.439188 => setenv serverip 192.168.6.2
943 04:04:22.450054 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
944 04:04:22.450996 setenv serverip 192.168.6.2
945 04:04:22.451743 Sending with 10 millisecond of delay
947 04:04:26.175076 => tftpboot 0x01080000 957576/tftp-deploy-7h6ljksr/kernel/uImage
948 04:04:26.185923 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:19)
949 04:04:26.186786 tftpboot 0x01080000 957576/tftp-deploy-7h6ljksr/kernel/uImage
950 04:04:26.187274 Speed: 1000, full duplex
951 04:04:26.187733 Using ethernet@ff3f0000 device
952 04:04:26.188632 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
953 04:04:26.194251 Filename '957576/tftp-deploy-7h6ljksr/kernel/uImage'.
954 04:04:26.198082 Load address: 0x1080000
955 04:04:28.958291 Loading: *################################################## 43.6 MiB
956 04:04:28.958950 15.8 MiB/s
957 04:04:28.959430 done
958 04:04:28.962254 Bytes transferred = 45713984 (2b98a40 hex)
959 04:04:28.963068 Sending with 10 millisecond of delay
961 04:04:33.649960 => tftpboot 0x08000000 957576/tftp-deploy-7h6ljksr/ramdisk/ramdisk.cpio.gz.uboot
962 04:04:33.660806 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:11)
963 04:04:33.661662 tftpboot 0x08000000 957576/tftp-deploy-7h6ljksr/ramdisk/ramdisk.cpio.gz.uboot
964 04:04:33.662152 Speed: 1000, full duplex
965 04:04:33.662609 Using ethernet@ff3f0000 device
966 04:04:33.663587 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
967 04:04:33.675435 Filename '957576/tftp-deploy-7h6ljksr/ramdisk/ramdisk.cpio.gz.uboot'.
968 04:04:33.675965 Load address: 0x8000000
969 04:04:43.011854 Loading: *########T ######################################### UDP wrong checksum 0000000f 00008412
970 04:04:43.335037 UDP wrong checksum 000000ff 000009ed
971 04:04:43.377826 UDP wrong checksum 000000ff 0000a5df
972 04:04:48.013464 T UDP wrong checksum 0000000f 00008412
973 04:04:58.013969 T UDP wrong checksum 0000000f 00008412
974 04:05:18.019327 T T T T T UDP wrong checksum 0000000f 00008412
975 04:05:33.023715 T T
976 04:05:33.024457 Retry count exceeded; starting again
978 04:05:33.026011 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
981 04:05:33.028135 end: 2.4 uboot-commands (duration 00:01:48) [common]
983 04:05:33.029730 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
985 04:05:33.030937 end: 2 uboot-action (duration 00:01:48) [common]
987 04:05:33.032634 Cleaning after the job
988 04:05:33.033230 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957576/tftp-deploy-7h6ljksr/ramdisk
989 04:05:33.034557 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957576/tftp-deploy-7h6ljksr/kernel
990 04:05:33.082167 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957576/tftp-deploy-7h6ljksr/dtb
991 04:05:33.082964 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957576/tftp-deploy-7h6ljksr/modules
992 04:05:33.101119 start: 4.1 power-off (timeout 00:00:30) [common]
993 04:05:33.101732 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
994 04:05:33.139613 >> OK - accepted request
995 04:05:33.140879 Returned 0 in 0 seconds
996 04:05:33.241604 end: 4.1 power-off (duration 00:00:00) [common]
998 04:05:33.242520 start: 4.2 read-feedback (timeout 00:10:00) [common]
999 04:05:33.243169 Listened to connection for namespace 'common' for up to 1s
1000 04:05:34.244122 Finalising connection for namespace 'common'
1001 04:05:34.244638 Disconnecting from shell: Finalise
1002 04:05:34.244918 =>
1003 04:05:34.345615 end: 4.2 read-feedback (duration 00:00:01) [common]
1004 04:05:34.346106 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/957576
1005 04:05:34.949751 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/957576
1006 04:05:34.950362 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.