Boot log: meson-sm1-s905d3-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 04:46:46.544121 lava-dispatcher, installed at version: 2024.01
2 04:46:46.545450 start: 0 validate
3 04:46:46.546033 Start time: 2024-11-08 04:46:46.545996+00:00 (UTC)
4 04:46:46.546701 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 04:46:46.547362 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 04:46:46.586846 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 04:46:46.587388 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-574-g603e41d0858f1%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 04:46:46.618068 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 04:46:46.618732 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-574-g603e41d0858f1%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-sm1-s905d3-libretech-cc.dtb exists
10 04:46:46.652023 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 04:46:46.652513 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-574-g603e41d0858f1%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 04:46:46.689722 validate duration: 0.14
14 04:46:46.690583 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 04:46:46.690915 start: 1.1 download-retry (timeout 00:10:00) [common]
16 04:46:46.691223 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 04:46:46.691818 Not decompressing ramdisk as can be used compressed.
18 04:46:46.692288 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 04:46:46.692564 saving as /var/lib/lava/dispatcher/tmp/957588/tftp-deploy-313qaq89/ramdisk/rootfs.cpio.gz
20 04:46:46.692842 total size: 47897469 (45 MB)
21 04:46:46.727781 progress 0 % (0 MB)
22 04:46:46.758613 progress 5 % (2 MB)
23 04:46:46.788367 progress 10 % (4 MB)
24 04:46:46.818158 progress 15 % (6 MB)
25 04:46:46.847522 progress 20 % (9 MB)
26 04:46:46.877367 progress 25 % (11 MB)
27 04:46:46.906723 progress 30 % (13 MB)
28 04:46:46.936057 progress 35 % (16 MB)
29 04:46:46.965858 progress 40 % (18 MB)
30 04:46:46.995177 progress 45 % (20 MB)
31 04:46:47.024839 progress 50 % (22 MB)
32 04:46:47.054224 progress 55 % (25 MB)
33 04:46:47.084981 progress 60 % (27 MB)
34 04:46:47.114537 progress 65 % (29 MB)
35 04:46:47.144527 progress 70 % (32 MB)
36 04:46:47.174368 progress 75 % (34 MB)
37 04:46:47.203808 progress 80 % (36 MB)
38 04:46:47.233752 progress 85 % (38 MB)
39 04:46:47.263322 progress 90 % (41 MB)
40 04:46:47.293447 progress 95 % (43 MB)
41 04:46:47.321944 progress 100 % (45 MB)
42 04:46:47.322681 45 MB downloaded in 0.63 s (72.53 MB/s)
43 04:46:47.323248 end: 1.1.1 http-download (duration 00:00:01) [common]
45 04:46:47.324190 end: 1.1 download-retry (duration 00:00:01) [common]
46 04:46:47.324507 start: 1.2 download-retry (timeout 00:09:59) [common]
47 04:46:47.324788 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 04:46:47.325262 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-574-g603e41d0858f1/arm64/defconfig/gcc-12/kernel/Image
49 04:46:47.325509 saving as /var/lib/lava/dispatcher/tmp/957588/tftp-deploy-313qaq89/kernel/Image
50 04:46:47.325723 total size: 45713920 (43 MB)
51 04:46:47.325941 No compression specified
52 04:46:47.361280 progress 0 % (0 MB)
53 04:46:47.389333 progress 5 % (2 MB)
54 04:46:47.417948 progress 10 % (4 MB)
55 04:46:47.445762 progress 15 % (6 MB)
56 04:46:47.473260 progress 20 % (8 MB)
57 04:46:47.500638 progress 25 % (10 MB)
58 04:46:47.528500 progress 30 % (13 MB)
59 04:46:47.556467 progress 35 % (15 MB)
60 04:46:47.584115 progress 40 % (17 MB)
61 04:46:47.611666 progress 45 % (19 MB)
62 04:46:47.639416 progress 50 % (21 MB)
63 04:46:47.666969 progress 55 % (24 MB)
64 04:46:47.694466 progress 60 % (26 MB)
65 04:46:47.721743 progress 65 % (28 MB)
66 04:46:47.749333 progress 70 % (30 MB)
67 04:46:47.776715 progress 75 % (32 MB)
68 04:46:47.804293 progress 80 % (34 MB)
69 04:46:47.831579 progress 85 % (37 MB)
70 04:46:47.858883 progress 90 % (39 MB)
71 04:46:47.886660 progress 95 % (41 MB)
72 04:46:47.913569 progress 100 % (43 MB)
73 04:46:47.914086 43 MB downloaded in 0.59 s (74.10 MB/s)
74 04:46:47.914556 end: 1.2.1 http-download (duration 00:00:01) [common]
76 04:46:47.915359 end: 1.2 download-retry (duration 00:00:01) [common]
77 04:46:47.915631 start: 1.3 download-retry (timeout 00:09:59) [common]
78 04:46:47.915892 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 04:46:47.916377 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-574-g603e41d0858f1/arm64/defconfig/gcc-12/dtbs/amlogic/meson-sm1-s905d3-libretech-cc.dtb
80 04:46:47.916643 saving as /var/lib/lava/dispatcher/tmp/957588/tftp-deploy-313qaq89/dtb/meson-sm1-s905d3-libretech-cc.dtb
81 04:46:47.916850 total size: 53209 (0 MB)
82 04:46:47.917059 No compression specified
83 04:46:47.955192 progress 61 % (0 MB)
84 04:46:47.956049 progress 100 % (0 MB)
85 04:46:47.956585 0 MB downloaded in 0.04 s (1.28 MB/s)
86 04:46:47.957058 end: 1.3.1 http-download (duration 00:00:00) [common]
88 04:46:47.957862 end: 1.3 download-retry (duration 00:00:00) [common]
89 04:46:47.958120 start: 1.4 download-retry (timeout 00:09:59) [common]
90 04:46:47.958381 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 04:46:47.958827 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-574-g603e41d0858f1/arm64/defconfig/gcc-12/modules.tar.xz
92 04:46:47.959065 saving as /var/lib/lava/dispatcher/tmp/957588/tftp-deploy-313qaq89/modules/modules.tar
93 04:46:47.959267 total size: 11610020 (11 MB)
94 04:46:47.959475 Using unxz to decompress xz
95 04:46:47.995272 progress 0 % (0 MB)
96 04:46:48.060723 progress 5 % (0 MB)
97 04:46:48.134203 progress 10 % (1 MB)
98 04:46:48.229050 progress 15 % (1 MB)
99 04:46:48.323092 progress 20 % (2 MB)
100 04:46:48.406503 progress 25 % (2 MB)
101 04:46:48.482113 progress 30 % (3 MB)
102 04:46:48.560652 progress 35 % (3 MB)
103 04:46:48.633101 progress 40 % (4 MB)
104 04:46:48.708202 progress 45 % (5 MB)
105 04:46:48.791931 progress 50 % (5 MB)
106 04:46:48.868964 progress 55 % (6 MB)
107 04:46:48.953807 progress 60 % (6 MB)
108 04:46:49.035821 progress 65 % (7 MB)
109 04:46:49.117121 progress 70 % (7 MB)
110 04:46:49.194575 progress 75 % (8 MB)
111 04:46:49.277446 progress 80 % (8 MB)
112 04:46:49.358970 progress 85 % (9 MB)
113 04:46:49.437602 progress 90 % (9 MB)
114 04:46:49.516677 progress 95 % (10 MB)
115 04:46:49.596045 progress 100 % (11 MB)
116 04:46:49.607332 11 MB downloaded in 1.65 s (6.72 MB/s)
117 04:46:49.607935 end: 1.4.1 http-download (duration 00:00:02) [common]
119 04:46:49.609544 end: 1.4 download-retry (duration 00:00:02) [common]
120 04:46:49.610069 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 04:46:49.610587 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 04:46:49.611070 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 04:46:49.611567 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 04:46:49.612566 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2
125 04:46:49.613418 makedir: /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin
126 04:46:49.614056 makedir: /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/tests
127 04:46:49.614672 makedir: /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/results
128 04:46:49.615287 Creating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin/lava-add-keys
129 04:46:49.616261 Creating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin/lava-add-sources
130 04:46:49.617218 Creating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin/lava-background-process-start
131 04:46:49.618154 Creating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin/lava-background-process-stop
132 04:46:49.619126 Creating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin/lava-common-functions
133 04:46:49.620058 Creating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin/lava-echo-ipv4
134 04:46:49.620974 Creating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin/lava-install-packages
135 04:46:49.621870 Creating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin/lava-installed-packages
136 04:46:49.622749 Creating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin/lava-os-build
137 04:46:49.623627 Creating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin/lava-probe-channel
138 04:46:49.624545 Creating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin/lava-probe-ip
139 04:46:49.625437 Creating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin/lava-target-ip
140 04:46:49.626323 Creating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin/lava-target-mac
141 04:46:49.627199 Creating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin/lava-target-storage
142 04:46:49.628184 Creating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin/lava-test-case
143 04:46:49.629107 Creating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin/lava-test-event
144 04:46:49.629994 Creating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin/lava-test-feedback
145 04:46:49.630870 Creating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin/lava-test-raise
146 04:46:49.631744 Creating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin/lava-test-reference
147 04:46:49.632670 Creating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin/lava-test-runner
148 04:46:49.633562 Creating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin/lava-test-set
149 04:46:49.634440 Creating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin/lava-test-shell
150 04:46:49.635334 Updating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin/lava-install-packages (oe)
151 04:46:49.636339 Updating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/bin/lava-installed-packages (oe)
152 04:46:49.637176 Creating /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/environment
153 04:46:49.637885 LAVA metadata
154 04:46:49.638374 - LAVA_JOB_ID=957588
155 04:46:49.638797 - LAVA_DISPATCHER_IP=192.168.6.2
156 04:46:49.639443 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 04:46:49.641220 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 04:46:49.641840 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 04:46:49.642253 skipped lava-vland-overlay
160 04:46:49.642736 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 04:46:49.643238 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 04:46:49.643660 skipped lava-multinode-overlay
163 04:46:49.644239 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 04:46:49.644757 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 04:46:49.645234 Loading test definitions
166 04:46:49.645774 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 04:46:49.646212 Using /lava-957588 at stage 0
168 04:46:49.648260 uuid=957588_1.5.2.4.1 testdef=None
169 04:46:49.648615 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 04:46:49.648890 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 04:46:49.650627 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 04:46:49.651461 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 04:46:49.653640 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 04:46:49.654534 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 04:46:49.656650 runner path: /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/0/tests/0_igt-gpu-panfrost test_uuid 957588_1.5.2.4.1
178 04:46:49.657226 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 04:46:49.658062 Creating lava-test-runner.conf files
181 04:46:49.658269 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/957588/lava-overlay-lnsrdyb2/lava-957588/0 for stage 0
182 04:46:49.658599 - 0_igt-gpu-panfrost
183 04:46:49.658959 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 04:46:49.659253 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 04:46:49.682390 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 04:46:49.682803 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 04:46:49.683073 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 04:46:49.683340 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 04:46:49.683607 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 04:46:56.467018 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 04:46:56.467486 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 04:46:56.467734 extracting modules file /var/lib/lava/dispatcher/tmp/957588/tftp-deploy-313qaq89/modules/modules.tar to /var/lib/lava/dispatcher/tmp/957588/extract-overlay-ramdisk-u2_w0hcu/ramdisk
193 04:46:57.905344 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 04:46:57.905836 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
195 04:46:57.906118 [common] Applying overlay /var/lib/lava/dispatcher/tmp/957588/compress-overlay-eldsraaz/overlay-1.5.2.5.tar.gz to ramdisk
196 04:46:57.906332 [common] Applying overlay /var/lib/lava/dispatcher/tmp/957588/compress-overlay-eldsraaz/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/957588/extract-overlay-ramdisk-u2_w0hcu/ramdisk
197 04:46:57.936247 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 04:46:57.936641 start: 1.5.6 prepare-kernel (timeout 00:09:49) [common]
199 04:46:57.936914 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:49) [common]
200 04:46:57.937142 Converting downloaded kernel to a uImage
201 04:46:57.937442 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/957588/tftp-deploy-313qaq89/kernel/Image /var/lib/lava/dispatcher/tmp/957588/tftp-deploy-313qaq89/kernel/uImage
202 04:46:58.418160 output: Image Name:
203 04:46:58.418572 output: Created: Fri Nov 8 04:46:57 2024
204 04:46:58.418782 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 04:46:58.418990 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 04:46:58.419193 output: Load Address: 01080000
207 04:46:58.419395 output: Entry Point: 01080000
208 04:46:58.419595 output:
209 04:46:58.419926 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 04:46:58.420244 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 04:46:58.420515 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 04:46:58.420768 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 04:46:58.421024 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 04:46:58.421277 Building ramdisk /var/lib/lava/dispatcher/tmp/957588/extract-overlay-ramdisk-u2_w0hcu/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/957588/extract-overlay-ramdisk-u2_w0hcu/ramdisk
215 04:47:05.570922 >> 502412 blocks
216 04:47:26.322687 Adding RAMdisk u-boot header.
217 04:47:26.323359 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/957588/extract-overlay-ramdisk-u2_w0hcu/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/957588/extract-overlay-ramdisk-u2_w0hcu/ramdisk.cpio.gz.uboot
218 04:47:27.012498 output: Image Name:
219 04:47:27.012925 output: Created: Fri Nov 8 04:47:26 2024
220 04:47:27.013133 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 04:47:27.013335 output: Data Size: 65713577 Bytes = 64173.42 KiB = 62.67 MiB
222 04:47:27.013534 output: Load Address: 00000000
223 04:47:27.013731 output: Entry Point: 00000000
224 04:47:27.013928 output:
225 04:47:27.014509 rename /var/lib/lava/dispatcher/tmp/957588/extract-overlay-ramdisk-u2_w0hcu/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/957588/tftp-deploy-313qaq89/ramdisk/ramdisk.cpio.gz.uboot
226 04:47:27.014925 end: 1.5.8 compress-ramdisk (duration 00:00:29) [common]
227 04:47:27.015210 end: 1.5 prepare-tftp-overlay (duration 00:00:37) [common]
228 04:47:27.015480 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:20) [common]
229 04:47:27.015720 No LXC device requested
230 04:47:27.015972 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 04:47:27.016575 start: 1.7 deploy-device-env (timeout 00:09:20) [common]
232 04:47:27.017080 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 04:47:27.017491 Checking files for TFTP limit of 4294967296 bytes.
234 04:47:27.020141 end: 1 tftp-deploy (duration 00:00:40) [common]
235 04:47:27.020713 start: 2 uboot-action (timeout 00:05:00) [common]
236 04:47:27.021226 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 04:47:27.021712 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 04:47:27.022202 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 04:47:27.022721 Using kernel file from prepare-kernel: 957588/tftp-deploy-313qaq89/kernel/uImage
240 04:47:27.023340 substitutions:
241 04:47:27.023744 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 04:47:27.024179 - {DTB_ADDR}: 0x01070000
243 04:47:27.024576 - {DTB}: 957588/tftp-deploy-313qaq89/dtb/meson-sm1-s905d3-libretech-cc.dtb
244 04:47:27.024971 - {INITRD}: 957588/tftp-deploy-313qaq89/ramdisk/ramdisk.cpio.gz.uboot
245 04:47:27.025362 - {KERNEL_ADDR}: 0x01080000
246 04:47:27.025748 - {KERNEL}: 957588/tftp-deploy-313qaq89/kernel/uImage
247 04:47:27.026137 - {LAVA_MAC}: None
248 04:47:27.026563 - {PRESEED_CONFIG}: None
249 04:47:27.026952 - {PRESEED_LOCAL}: None
250 04:47:27.027336 - {RAMDISK_ADDR}: 0x08000000
251 04:47:27.027719 - {RAMDISK}: 957588/tftp-deploy-313qaq89/ramdisk/ramdisk.cpio.gz.uboot
252 04:47:27.028137 - {ROOT_PART}: None
253 04:47:27.028522 - {ROOT}: None
254 04:47:27.028910 - {SERVER_IP}: 192.168.6.2
255 04:47:27.029300 - {TEE_ADDR}: 0x83000000
256 04:47:27.029685 - {TEE}: None
257 04:47:27.030068 Parsed boot commands:
258 04:47:27.030442 - setenv autoload no
259 04:47:27.030825 - setenv initrd_high 0xffffffff
260 04:47:27.031205 - setenv fdt_high 0xffffffff
261 04:47:27.031585 - dhcp
262 04:47:27.031964 - setenv serverip 192.168.6.2
263 04:47:27.032371 - tftpboot 0x01080000 957588/tftp-deploy-313qaq89/kernel/uImage
264 04:47:27.032752 - tftpboot 0x08000000 957588/tftp-deploy-313qaq89/ramdisk/ramdisk.cpio.gz.uboot
265 04:47:27.033133 - tftpboot 0x01070000 957588/tftp-deploy-313qaq89/dtb/meson-sm1-s905d3-libretech-cc.dtb
266 04:47:27.033515 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 04:47:27.033901 - bootm 0x01080000 0x08000000 0x01070000
268 04:47:27.034383 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 04:47:27.035837 start: 2.3 connect-device (timeout 00:05:00) [common]
271 04:47:27.036305 [common] connect-device Connecting to device using 'telnet conserv1 3008'
272 04:47:27.051071 Setting prompt string to ['lava-test: # ']
273 04:47:27.052599 end: 2.3 connect-device (duration 00:00:00) [common]
274 04:47:27.053202 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 04:47:27.053736 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 04:47:27.054244 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 04:47:27.055378 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=solitude-01'
278 04:47:27.092171 >> OK - accepted request
279 04:47:27.094323 Returned 0 in 0 seconds
280 04:47:27.195344 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 04:47:27.196914 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 04:47:27.197465 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 04:47:27.197964 Setting prompt string to ['Hit any key to stop autoboot']
285 04:47:27.198401 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 04:47:27.199953 Trying 192.168.56.21...
287 04:47:27.200465 Connected to conserv1.
288 04:47:27.200880 Escape character is '^]'.
289 04:47:27.201293
290 04:47:27.201708 ser2net port telnet,3008 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.3.3:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 04:47:27.202128
292 04:47:35.100658 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
293 04:47:35.101279 bl2_stage_init 0x01
294 04:47:35.101728 bl2_stage_init 0x81
295 04:47:35.106147 hw id: 0x0000 - pwm id 0x01
296 04:47:35.106609 bl2_stage_init 0xc1
297 04:47:35.111800 bl2_stage_init 0x02
298 04:47:35.112288
299 04:47:35.112713 L0:00000000
300 04:47:35.113123 L1:00000703
301 04:47:35.113520 L2:00008067
302 04:47:35.113916 L3:15000000
303 04:47:35.117417 S1:00000000
304 04:47:35.117853 B2:20282000
305 04:47:35.118267 B1:a0f83180
306 04:47:35.118662
307 04:47:35.119056 TE: 74912
308 04:47:35.119449
309 04:47:35.123055 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
310 04:47:35.123487
311 04:47:35.128668 Board ID = 1
312 04:47:35.129094 Set cpu clk to 24M
313 04:47:35.129493 Set clk81 to 24M
314 04:47:35.134274 Use GP1_pll as DSU clk.
315 04:47:35.134700 DSU clk: 1200 Mhz
316 04:47:35.135099 CPU clk: 1200 MHz
317 04:47:35.139777 Set clk81 to 166.6M
318 04:47:35.145448 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
319 04:47:35.145876 board id: 1
320 04:47:35.152457 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 04:47:35.163043 fw parse done
322 04:47:35.169018 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 04:47:35.211650 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 04:47:35.222664 PIEI prepare done
325 04:47:35.223082 fastboot data load
326 04:47:35.223484 fastboot data verify
327 04:47:35.228202 verify result: 266
328 04:47:35.233814 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
329 04:47:35.234257 LPDDR4 probe
330 04:47:35.234656 ddr clk to 1584MHz
331 04:47:35.241786 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 04:47:35.279071
333 04:47:35.279498 dmc_version 0001
334 04:47:35.285716 Check phy result
335 04:47:35.291634 INFO : End of CA training
336 04:47:35.292095 INFO : End of initialization
337 04:47:35.297232 INFO : Training has run successfully!
338 04:47:35.297656 Check phy result
339 04:47:35.302834 INFO : End of initialization
340 04:47:35.303253 INFO : End of read enable training
341 04:47:35.308454 INFO : End of fine write leveling
342 04:47:35.314034 INFO : End of Write leveling coarse delay
343 04:47:35.314453 INFO : Training has run successfully!
344 04:47:35.314851 Check phy result
345 04:47:35.319629 INFO : End of initialization
346 04:47:35.320101 INFO : End of read dq deskew training
347 04:47:35.325238 INFO : End of MPR read delay center optimization
348 04:47:35.330843 INFO : End of write delay center optimization
349 04:47:35.336473 INFO : End of read delay center optimization
350 04:47:35.336911 INFO : End of max read latency training
351 04:47:35.342050 INFO : Training has run successfully!
352 04:47:35.342473 1D training succeed
353 04:47:35.351247 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 04:47:35.398819 Check phy result
355 04:47:35.399296 INFO : End of initialization
356 04:47:35.421268 INFO : End of 2D read delay Voltage center optimization
357 04:47:35.440324 INFO : End of 2D read delay Voltage center optimization
358 04:47:35.492237 INFO : End of 2D write delay Voltage center optimization
359 04:47:35.541473 INFO : End of 2D write delay Voltage center optimization
360 04:47:35.546977 INFO : Training has run successfully!
361 04:47:35.547414
362 04:47:35.547825 channel==0
363 04:47:35.552563 RxClkDly_Margin_A0==78 ps 8
364 04:47:35.552990 TxDqDly_Margin_A0==88 ps 9
365 04:47:35.558156 RxClkDly_Margin_A1==88 ps 9
366 04:47:35.558579 TxDqDly_Margin_A1==98 ps 10
367 04:47:35.558983 TrainedVREFDQ_A0==74
368 04:47:35.563770 TrainedVREFDQ_A1==74
369 04:47:35.564245 VrefDac_Margin_A0==23
370 04:47:35.564647 DeviceVref_Margin_A0==40
371 04:47:35.569375 VrefDac_Margin_A1==22
372 04:47:35.569802 DeviceVref_Margin_A1==40
373 04:47:35.570201
374 04:47:35.570599
375 04:47:35.570998 channel==1
376 04:47:35.574967 RxClkDly_Margin_A0==78 ps 8
377 04:47:35.575392 TxDqDly_Margin_A0==88 ps 9
378 04:47:35.580552 RxClkDly_Margin_A1==78 ps 8
379 04:47:35.580982 TxDqDly_Margin_A1==88 ps 9
380 04:47:35.586199 TrainedVREFDQ_A0==75
381 04:47:35.586620 TrainedVREFDQ_A1==75
382 04:47:35.587021 VrefDac_Margin_A0==22
383 04:47:35.591768 DeviceVref_Margin_A0==39
384 04:47:35.592213 VrefDac_Margin_A1==22
385 04:47:35.592612 DeviceVref_Margin_A1==39
386 04:47:35.597383
387 04:47:35.597810 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 04:47:35.598209
389 04:47:35.630959 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000018 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000017 00000016 00000017 dram_vref_reg_value 0x 00000061
390 04:47:35.631450 2D training succeed
391 04:47:35.636584 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 04:47:35.642202 auto size-- 65535DDR cs0 size: 2048MB
393 04:47:35.642622 DDR cs1 size: 2048MB
394 04:47:35.647767 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 04:47:35.648228 cs0 DataBus test pass
396 04:47:35.653387 cs1 DataBus test pass
397 04:47:35.653804 cs0 AddrBus test pass
398 04:47:35.654203 cs1 AddrBus test pass
399 04:47:35.654593
400 04:47:35.658959 100bdlr_step_size ps== 478
401 04:47:35.659387 result report
402 04:47:35.664570 boot times 0Enable ddr reg access
403 04:47:35.669642 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 04:47:35.683588 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
405 04:47:36.338742 bl2z: ptr: 05129330, size: 00001e40
406 04:47:36.344411 0.0;M3 CHK:0;cm4_sp_mode 0
407 04:47:36.344874 MVN_1=0x00000000
408 04:47:36.345283 MVN_2=0x00000000
409 04:47:36.355886 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
410 04:47:36.356381 OPS=0x04
411 04:47:36.356792 ring efuse init
412 04:47:36.361535 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
413 04:47:36.361976 [0.017319 Inits done]
414 04:47:36.362378 secure task start!
415 04:47:36.369620 high task start!
416 04:47:36.370067 low task start!
417 04:47:36.370491 run into bl31
418 04:47:36.378260 NOTICE: BL31: v1.3(release):4fc40b1
419 04:47:36.386045 NOTICE: BL31: Built : 15:57:33, May 22 2019
420 04:47:36.386487 NOTICE: BL31: G12A normal boot!
421 04:47:36.401587 NOTICE: BL31: BL33 decompress pass
422 04:47:36.407201 ERROR: Error initializing runtime service opteed_fast
423 04:47:39.146627 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0; SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
424 04:47:39.147226 bl2_stage_init 0x01
425 04:47:39.147658 bl2_stage_init 0x81
426 04:47:39.152222 hw id: 0x0000 - pwm id 0x01
427 04:47:39.152716 bl2_stage_init 0xc1
428 04:47:39.153127 bl2_stage_init 0x02
429 04:47:39.153533
430 04:47:39.157861 L0:00000000
431 04:47:39.158341 L1:00000703
432 04:47:39.158733 L2:00008067
433 04:47:39.159117 L3:15000000
434 04:47:39.159504 S1:00000000
435 04:47:39.163410 B2:20282000
436 04:47:39.163835 B1:a0f83180
437 04:47:39.164262
438 04:47:39.164652 TE: 70367
439 04:47:39.165037
440 04:47:39.169003 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
441 04:47:39.169437
442 04:47:39.174585 Board ID = 1
443 04:47:39.174993 Set cpu clk to 24M
444 04:47:39.175379 Set clk81 to 24M
445 04:47:39.180187 Use GP1_pll as DSU clk.
446 04:47:39.180595 DSU clk: 1200 Mhz
447 04:47:39.180976 CPU clk: 1200 MHz
448 04:47:39.181354 Set clk81 to 166.6M
449 04:47:39.191412 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
450 04:47:39.191831 board id: 1
451 04:47:39.197878 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
452 04:47:39.208751 fw parse done
453 04:47:39.214664 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
454 04:47:39.257894 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
455 04:47:39.269030 PIEI prepare done
456 04:47:39.269450 fastboot data load
457 04:47:39.269835 fastboot data verify
458 04:47:39.274528 verify result: 266
459 04:47:39.280184 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
460 04:47:39.280597 LPDDR4 probe
461 04:47:39.280979 ddr clk to 1584MHz
462 04:47:39.288165 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
463 04:47:39.325857
464 04:47:39.326301 dmc_version 0001
465 04:47:39.332961 Check phy result
466 04:47:39.339073 INFO : End of CA training
467 04:47:39.339510 INFO : End of initialization
468 04:47:39.344537 INFO : Training has run successfully!
469 04:47:39.344961 Check phy result
470 04:47:39.350104 INFO : End of initialization
471 04:47:39.350545 INFO : End of read enable training
472 04:47:39.355677 INFO : End of fine write leveling
473 04:47:39.361288 INFO : End of Write leveling coarse delay
474 04:47:39.361707 INFO : Training has run successfully!
475 04:47:39.362105 Check phy result
476 04:47:39.367014 INFO : End of initialization
477 04:47:39.367439 INFO : End of read dq deskew training
478 04:47:39.372519 INFO : End of MPR read delay center optimization
479 04:47:39.378115 INFO : End of write delay center optimization
480 04:47:39.383715 INFO : End of read delay center optimization
481 04:47:39.384180 INFO : End of max read latency training
482 04:47:39.389304 INFO : Training has run successfully!
483 04:47:39.389728 1D training succeed
484 04:47:39.398484 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
485 04:47:39.446859 Check phy result
486 04:47:39.447408 INFO : End of initialization
487 04:47:39.474116 INFO : End of 2D read delay Voltage center optimization
488 04:47:39.498329 INFO : End of 2D read delay Voltage center optimization
489 04:47:39.555048 INFO : End of 2D write delay Voltage center optimization
490 04:47:39.608969 INFO : End of 2D write delay Voltage center optimization
491 04:47:39.614503 INFO : Training has run successfully!
492 04:47:39.614930
493 04:47:39.615335 channel==0
494 04:47:39.620108 RxClkDly_Margin_A0==78 ps 8
495 04:47:39.620539 TxDqDly_Margin_A0==98 ps 10
496 04:47:39.625686 RxClkDly_Margin_A1==78 ps 8
497 04:47:39.626110 TxDqDly_Margin_A1==88 ps 9
498 04:47:39.626513 TrainedVREFDQ_A0==74
499 04:47:39.631294 TrainedVREFDQ_A1==74
500 04:47:39.631718 VrefDac_Margin_A0==23
501 04:47:39.632154 DeviceVref_Margin_A0==40
502 04:47:39.636897 VrefDac_Margin_A1==23
503 04:47:39.637338 DeviceVref_Margin_A1==40
504 04:47:39.637739
505 04:47:39.638135
506 04:47:39.638527 channel==1
507 04:47:39.642528 RxClkDly_Margin_A0==78 ps 8
508 04:47:39.642945 TxDqDly_Margin_A0==98 ps 10
509 04:47:39.648129 RxClkDly_Margin_A1==88 ps 9
510 04:47:39.648558 TxDqDly_Margin_A1==88 ps 9
511 04:47:39.653699 TrainedVREFDQ_A0==78
512 04:47:39.654123 TrainedVREFDQ_A1==75
513 04:47:39.654525 VrefDac_Margin_A0==22
514 04:47:39.659296 DeviceVref_Margin_A0==36
515 04:47:39.659714 VrefDac_Margin_A1==22
516 04:47:39.664940 DeviceVref_Margin_A1==39
517 04:47:39.665363
518 04:47:39.665764 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
519 04:47:39.666158
520 04:47:39.698493 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000016 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000015 00000018 00000014 00000016 00000017 00000018 00000019 00000018 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
521 04:47:39.698958 2D training succeed
522 04:47:39.704112 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
523 04:47:39.709696 auto size-- 65535DDR cs0 size: 2048MB
524 04:47:39.710125 DDR cs1 size: 2048MB
525 04:47:39.715300 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
526 04:47:39.715721 cs0 DataBus test pass
527 04:47:39.720942 cs1 DataBus test pass
528 04:47:39.721364 cs0 AddrBus test pass
529 04:47:39.721759 cs1 AddrBus test pass
530 04:47:39.722147
531 04:47:39.726496 100bdlr_step_size ps== 478
532 04:47:39.726925 result report
533 04:47:39.732150 boot times 0Enable ddr reg access
534 04:47:39.737265 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
535 04:47:39.751152 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
536 04:47:40.409689 bl2z: ptr: 05129330, size: 00001e40
537 04:47:40.416789 0.0;M3 CHK:0;cm4_sp_mode 0
538 04:47:40.417341 MVN_1=0x00000000
539 04:47:40.417749 MVN_2=0x00000000
540 04:47:40.428274 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
541 04:47:40.428715 OPS=0x04
542 04:47:40.429126 ring efuse init
543 04:47:40.431171 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
544 04:47:40.437514 [0.017355 Inits done]
545 04:47:40.437945 secure task start!
546 04:47:40.438344 high task start!
547 04:47:40.438736 low task start!
548 04:47:40.441735 run into bl31
549 04:47:40.450429 NOTICE: BL31: v1.3(release):4fc40b1
550 04:47:40.458169 NOTICE: BL31: Built : 15:57:33, May 22 2019
551 04:47:40.458612 NOTICE: BL31: G12A normal boot!
552 04:47:40.473704 NOTICE: BL31: BL33 decompress pass
553 04:47:40.479476 ERROR: Error initializing runtime service opteed_fast
554 04:47:41.846208 SM1:BL:511f6b:81ca2f;FEAT:A0F83180:20282000;POC:B;RCY:0;SPINOR:0;0.0;CHK:0;
555 04:47:41.846809 bl2_stage_init 0x01
556 04:47:41.847226 bl2_stage_init 0x81
557 04:47:41.851756 hw id: 0x0000 - pwm id 0x01
558 04:47:41.852238 bl2_stage_init 0xc1
559 04:47:41.857481 bl2_stage_init 0x02
560 04:47:41.857914
561 04:47:41.858320 L0:00000000
562 04:47:41.858716 L1:00000703
563 04:47:41.859109 L2:00008067
564 04:47:41.859495 L3:15000000
565 04:47:41.863017 S1:00000000
566 04:47:41.863442 B2:20282000
567 04:47:41.863841 B1:a0f83180
568 04:47:41.864271
569 04:47:41.864669 TE: 70285
570 04:47:41.865066
571 04:47:41.868581 BL2 Built : 15:21:48, Aug 28 2019. g12a g1bf2b53 - luan.yuan@droid15-sz
572 04:47:41.869009
573 04:47:41.874158 Board ID = 1
574 04:47:41.874585 Set cpu clk to 24M
575 04:47:41.874981 Set clk81 to 24M
576 04:47:41.879785 Use GP1_pll as DSU clk.
577 04:47:41.880236 DSU clk: 1200 Mhz
578 04:47:41.880641 CPU clk: 1200 MHz
579 04:47:41.885338 Set clk81 to 166.6M
580 04:47:41.890938 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:21:45
581 04:47:41.891362 board id: 1
582 04:47:41.898181 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
583 04:47:41.909058 fw parse done
584 04:47:41.915033 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
585 04:47:41.958181 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
586 04:47:41.969237 PIEI prepare done
587 04:47:41.969668 fastboot data load
588 04:47:41.970075 fastboot data verify
589 04:47:41.974902 verify result: 266
590 04:47:41.980447 Cfg max: 2, cur: 1. Board id: 255. Force loop cfg
591 04:47:41.980872 LPDDR4 probe
592 04:47:41.981271 ddr clk to 1584MHz
593 04:47:41.988525 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
594 04:47:42.026197
595 04:47:42.026661 dmc_version 0001
596 04:47:42.033251 Check phy result
597 04:47:42.039221 INFO : End of CA training
598 04:47:42.039651 INFO : End of initialization
599 04:47:42.044826 INFO : Training has run successfully!
600 04:47:42.045254 Check phy result
601 04:47:42.050437 INFO : End of initialization
602 04:47:42.050862 INFO : End of read enable training
603 04:47:42.056057 INFO : End of fine write leveling
604 04:47:42.061679 INFO : End of Write leveling coarse delay
605 04:47:42.062106 INFO : Training has run successfully!
606 04:47:42.062505 Check phy result
607 04:47:42.067305 INFO : End of initialization
608 04:47:42.067729 INFO : End of read dq deskew training
609 04:47:42.072824 INFO : End of MPR read delay center optimization
610 04:47:42.078433 INFO : End of write delay center optimization
611 04:47:42.084038 INFO : End of read delay center optimization
612 04:47:42.084470 INFO : End of max read latency training
613 04:47:42.089660 INFO : Training has run successfully!
614 04:47:42.090082 1D training succeed
615 04:47:42.098843 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
616 04:47:42.147110 Check phy result
617 04:47:42.147536 INFO : End of initialization
618 04:47:42.174567 INFO : End of 2D read delay Voltage center optimization
619 04:47:42.198581 INFO : End of 2D read delay Voltage center optimization
620 04:47:42.255248 INFO : End of 2D write delay Voltage center optimization
621 04:47:42.309244 INFO : End of 2D write delay Voltage center optimization
622 04:47:42.314784 INFO : Training has run successfully!
623 04:47:42.315207
624 04:47:42.315614 channel==0
625 04:47:42.320409 RxClkDly_Margin_A0==78 ps 8
626 04:47:42.320835 TxDqDly_Margin_A0==98 ps 10
627 04:47:42.323764 RxClkDly_Margin_A1==88 ps 9
628 04:47:42.324217 TxDqDly_Margin_A1==98 ps 10
629 04:47:42.329268 TrainedVREFDQ_A0==75
630 04:47:42.329691 TrainedVREFDQ_A1==74
631 04:47:42.330089 VrefDac_Margin_A0==24
632 04:47:42.334854 DeviceVref_Margin_A0==39
633 04:47:42.335275 VrefDac_Margin_A1==23
634 04:47:42.340532 DeviceVref_Margin_A1==40
635 04:47:42.340954
636 04:47:42.341350
637 04:47:42.341742 channel==1
638 04:47:42.342129 RxClkDly_Margin_A0==78 ps 8
639 04:47:42.344018 TxDqDly_Margin_A0==98 ps 10
640 04:47:42.349560 RxClkDly_Margin_A1==78 ps 8
641 04:47:42.349987 TxDqDly_Margin_A1==88 ps 9
642 04:47:42.350385 TrainedVREFDQ_A0==78
643 04:47:42.355062 TrainedVREFDQ_A1==77
644 04:47:42.355489 VrefDac_Margin_A0==22
645 04:47:42.360737 DeviceVref_Margin_A0==36
646 04:47:42.361154 VrefDac_Margin_A1==22
647 04:47:42.361547 DeviceVref_Margin_A1==37
648 04:47:42.361937
649 04:47:42.369837 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
650 04:47:42.370279
651 04:47:42.395568 soc_vref_reg_value 0x 00000019 00000018 00000018 00000017 00000018 00000015 00000018 00000015 00000017 00000017 00000017 00000017 00000017 00000018 00000018 00000019 00000018 00000017 00000018 00000015 00000017 00000014 00000015 00000017 00000018 00000019 00000017 00000018 0000001c 00000018 00000016 00000017 dram_vref_reg_value 0x 00000061
652 04:47:42.401167 2D training succeed
653 04:47:42.404703 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
654 04:47:42.410180 auto size-- 65535DDR cs0 size: 2048MB
655 04:47:42.410688 DDR cs1 size: 2048MB
656 04:47:42.415829 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
657 04:47:42.416402 cs0 DataBus test pass
658 04:47:42.421443 cs1 DataBus test pass
659 04:47:42.421874 cs0 AddrBus test pass
660 04:47:42.422278 cs1 AddrBus test pass
661 04:47:42.422676
662 04:47:42.424827 100bdlr_step_size ps== 471
663 04:47:42.425263 result report
664 04:47:42.430434 boot times 0Enable ddr reg access
665 04:47:42.437573 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
666 04:47:42.451498 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c4000, part: 0
667 04:47:43.109788 bl2z: ptr: 05129330, size: 00001e40
668 04:47:43.117361 0.0;M3 CHK:0;cm4_sp_mode 0
669 04:47:43.117836 MVN_1=0x00000000
670 04:47:43.118251 MVN_2=0x00000000
671 04:47:43.128776 [Image: g12a_v1.1.3390-6ac5299 2019-09-26 14:09:46 luan.yuan@droid15-sz]
672 04:47:43.129215 OPS=0x04
673 04:47:43.129618 ring efuse init
674 04:47:43.134470 2b 0c 04 00 01 21 18 00 00 04 34 34 36 46 50 50
675 04:47:43.134910 [0.017354 Inits done]
676 04:47:43.135308 secure task start!
677 04:47:43.141912 high task start!
678 04:47:43.142342 low task start!
679 04:47:43.142739 run into bl31
680 04:47:43.150514 NOTICE: BL31: v1.3(release):4fc40b1
681 04:47:43.158331 NOTICE: BL31: Built : 15:57:33, May 22 2019
682 04:47:43.158766 NOTICE: BL31: G12A normal boot!
683 04:47:43.173869 NOTICE: BL31: BL33 decompress pass
684 04:47:43.179597 ERROR: Error initializing runtime service opteed_fast
685 04:47:43.973800
686 04:47:43.974385
687 04:47:43.979102 U-Boot 2024.01-rc4+ (Dec 14 2023 - 02:26:00 -0500) Libre Computer AML-S905D3-CC
688 04:47:43.979539
689 04:47:43.982665 Model: Libre Computer AML-S905D3-CC Solitude
690 04:47:44.129621 SoC: Amlogic Meson SM1 (S905D3) Revision 2b:c (4:2)
691 04:47:44.145544 DRAM: 2 GiB (effective 3.8 GiB)
692 04:47:44.245985 Core: 406 devices, 33 uclasses, devicetree: separate
693 04:47:44.251848 WDT: Not starting watchdog@f0d0
694 04:47:44.276884 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
695 04:47:44.289060 Loading Environment from FAT... Card did not respond to voltage select! : -110
696 04:47:44.294085 ** Bad device specification mmc 0 **
697 04:47:44.304123 Card did not respond to voltage select! : -110
698 04:47:44.311813 ** Bad device specification mmc 0 **
699 04:47:44.312353 Couldn't find partition mmc 0
700 04:47:44.320123 Card did not respond to voltage select! : -110
701 04:47:44.325688 ** Bad device specification mmc 0 **
702 04:47:44.326338 Couldn't find partition mmc 0
703 04:47:44.330687 Error: could not access storage.
704 04:47:44.628127 Net: eth0: ethernet@ff3f0000
705 04:47:44.628792 starting USB...
706 04:47:44.872738 Bus usb@ff500000: Register 3000140 NbrPorts 3
707 04:47:44.873248 Starting the controller
708 04:47:44.879800 USB XHCI 1.10
709 04:47:46.433428 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
710 04:47:46.441687 scanning usb for storage devices... 0 Storage Device(s) found
712 04:47:46.493452 Hit any key to stop autoboot: 1
713 04:47:46.494478 end: 2.4.2 bootloader-interrupt (duration 00:00:19) [common]
714 04:47:46.495126 start: 2.4.3 bootloader-commands (timeout 00:04:41) [common]
715 04:47:46.495645 Setting prompt string to ['=>']
716 04:47:46.496249 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:41)
717 04:47:46.508017 0
718 04:47:46.509053 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
720 04:47:46.610439 => setenv autoload no
721 04:47:46.611560 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
722 04:47:46.617075 setenv autoload no
724 04:47:46.718721 => setenv initrd_high 0xffffffff
725 04:47:46.719577 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
726 04:47:46.723902 setenv initrd_high 0xffffffff
728 04:47:46.825474 => setenv fdt_high 0xffffffff
729 04:47:46.826197 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
730 04:47:46.830970 setenv fdt_high 0xffffffff
732 04:47:46.932584 => dhcp
733 04:47:46.933308 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:40)
734 04:47:46.937718 dhcp
735 04:47:47.493337 ethernet@ff3f0000 Waiting for PHY auto negotiation to complete. done
736 04:47:47.493982 Speed: 1000, full duplex
737 04:47:47.494449 BOOTP broadcast 1
738 04:47:47.742197 BOOTP broadcast 2
739 04:47:47.761548 DHCP client bound to address 192.168.6.21 (268 ms)
741 04:47:47.863093 => setenv serverip 192.168.6.2
742 04:47:47.863771 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
743 04:47:47.868562 setenv serverip 192.168.6.2
745 04:47:47.970130 => tftpboot 0x01080000 957588/tftp-deploy-313qaq89/kernel/uImage
746 04:47:47.970954 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:39)
747 04:47:47.977753 tftpboot 0x01080000 957588/tftp-deploy-313qaq89/kernel/uImage
748 04:47:47.978264 Speed: 1000, full duplex
749 04:47:47.978715 Using ethernet@ff3f0000 device
750 04:47:47.983300 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
751 04:47:47.988754 Filename '957588/tftp-deploy-313qaq89/kernel/uImage'.
752 04:47:47.992638 Load address: 0x1080000
753 04:47:48.459440 Loading: *######## UDP wrong checksum 00000005 00007fd6
754 04:47:50.845149 ########################################## 43.6 MiB
755 04:47:50.845809 15.3 MiB/s
756 04:47:50.846291 done
757 04:47:50.849468 Bytes transferred = 45713984 (2b98a40 hex)
759 04:47:50.951118 => tftpboot 0x08000000 957588/tftp-deploy-313qaq89/ramdisk/ramdisk.cpio.gz.uboot
760 04:47:50.951926 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:36)
761 04:47:50.958682 tftpboot 0x08000000 957588/tftp-deploy-313qaq89/ramdisk/ramdisk.cpio.gz.uboot
762 04:47:50.959174 Speed: 1000, full duplex
763 04:47:50.959615 Using ethernet@ff3f0000 device
764 04:47:50.964318 TFTP from server 192.168.6.2; our IP address is 192.168.6.21
765 04:47:50.974175 Filename '957588/tftp-deploy-313qaq89/ramdisk/ramdisk.cpio.gz.uboot'.
766 04:47:50.974662 Load address: 0x8000000
767 04:48:00.658028 Loading: *#########################T ######################## UDP wrong checksum 0000000f 0000e98f
768 04:48:05.658162 T UDP wrong checksum 0000000f 0000e98f
769 04:48:15.660264 T T UDP wrong checksum 0000000f 0000e98f
770 04:48:34.650997 T T T UDP wrong checksum 000000ff 000000c1
771 04:48:34.694771 UDP wrong checksum 000000ff 00005939
772 04:48:35.665008 T UDP wrong checksum 0000000f 0000e98f
773 04:48:50.667953 T T
774 04:48:50.668677 Retry count exceeded; starting again
776 04:48:50.670208 end: 2.4.3 bootloader-commands (duration 00:01:04) [common]
779 04:48:50.672311 end: 2.4 uboot-commands (duration 00:01:24) [common]
781 04:48:50.673836 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
783 04:48:50.674931 end: 2 uboot-action (duration 00:01:24) [common]
785 04:48:50.676630 Cleaning after the job
786 04:48:50.677226 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957588/tftp-deploy-313qaq89/ramdisk
787 04:48:50.679455 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957588/tftp-deploy-313qaq89/kernel
788 04:48:50.735226 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957588/tftp-deploy-313qaq89/dtb
789 04:48:50.737629 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/957588/tftp-deploy-313qaq89/modules
790 04:48:50.770769 start: 4.1 power-off (timeout 00:00:30) [common]
791 04:48:50.771456 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=solitude-01'
792 04:48:50.809169 >> OK - accepted request
793 04:48:50.811235 Returned 0 in 0 seconds
794 04:48:50.911959 end: 4.1 power-off (duration 00:00:00) [common]
796 04:48:50.912901 start: 4.2 read-feedback (timeout 00:10:00) [common]
797 04:48:50.913548 Listened to connection for namespace 'common' for up to 1s
798 04:48:51.914501 Finalising connection for namespace 'common'
799 04:48:51.915260 Disconnecting from shell: Finalise
800 04:48:51.915800 =>
801 04:48:52.016877 end: 4.2 read-feedback (duration 00:00:01) [common]
802 04:48:52.017533 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/957588
803 04:48:52.771614 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/957588
804 04:48:52.772246 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.