Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 19:18:16.407214 lava-dispatcher, installed at version: 2024.01
2 19:18:16.408112 start: 0 validate
3 19:18:16.408619 Start time: 2024-11-09 19:18:16.408588+00:00 (UTC)
4 19:18:16.409207 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 19:18:16.409790 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 19:18:16.449664 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 19:18:16.450329 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-679-gc8994e7b0f32%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 19:18:16.486166 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 19:18:16.486899 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-679-gc8994e7b0f32%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 19:18:16.521244 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 19:18:16.521818 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-679-gc8994e7b0f32%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 19:18:16.562514 validate duration: 0.15
14 19:18:16.563669 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 19:18:16.564230 start: 1.1 download-retry (timeout 00:10:00) [common]
16 19:18:16.564669 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 19:18:16.565500 Not decompressing ramdisk as can be used compressed.
18 19:18:16.566133 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 19:18:16.566483 saving as /var/lib/lava/dispatcher/tmp/967959/tftp-deploy-mszqrz52/ramdisk/rootfs.cpio.gz
20 19:18:16.566874 total size: 8181887 (7 MB)
21 19:18:16.601905 progress 0 % (0 MB)
22 19:18:16.608038 progress 5 % (0 MB)
23 19:18:16.613657 progress 10 % (0 MB)
24 19:18:16.619694 progress 15 % (1 MB)
25 19:18:16.625175 progress 20 % (1 MB)
26 19:18:16.630978 progress 25 % (1 MB)
27 19:18:16.636501 progress 30 % (2 MB)
28 19:18:16.642349 progress 35 % (2 MB)
29 19:18:16.647694 progress 40 % (3 MB)
30 19:18:16.653510 progress 45 % (3 MB)
31 19:18:16.658932 progress 50 % (3 MB)
32 19:18:16.664893 progress 55 % (4 MB)
33 19:18:16.670216 progress 60 % (4 MB)
34 19:18:16.676071 progress 65 % (5 MB)
35 19:18:16.681406 progress 70 % (5 MB)
36 19:18:16.687079 progress 75 % (5 MB)
37 19:18:16.692572 progress 80 % (6 MB)
38 19:18:16.698510 progress 85 % (6 MB)
39 19:18:16.703977 progress 90 % (7 MB)
40 19:18:16.709816 progress 95 % (7 MB)
41 19:18:16.714853 progress 100 % (7 MB)
42 19:18:16.715531 7 MB downloaded in 0.15 s (52.50 MB/s)
43 19:18:16.716180 end: 1.1.1 http-download (duration 00:00:00) [common]
45 19:18:16.717176 end: 1.1 download-retry (duration 00:00:00) [common]
46 19:18:16.717516 start: 1.2 download-retry (timeout 00:10:00) [common]
47 19:18:16.717831 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 19:18:16.718412 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-679-gc8994e7b0f32/arm64/defconfig/gcc-12/kernel/Image
49 19:18:16.718697 saving as /var/lib/lava/dispatcher/tmp/967959/tftp-deploy-mszqrz52/kernel/Image
50 19:18:16.718938 total size: 45713920 (43 MB)
51 19:18:16.719176 No compression specified
52 19:18:16.758520 progress 0 % (0 MB)
53 19:18:16.789842 progress 5 % (2 MB)
54 19:18:16.820794 progress 10 % (4 MB)
55 19:18:16.854274 progress 15 % (6 MB)
56 19:18:16.885128 progress 20 % (8 MB)
57 19:18:16.914289 progress 25 % (10 MB)
58 19:18:16.945898 progress 30 % (13 MB)
59 19:18:16.976239 progress 35 % (15 MB)
60 19:18:17.005540 progress 40 % (17 MB)
61 19:18:17.035145 progress 45 % (19 MB)
62 19:18:17.066886 progress 50 % (21 MB)
63 19:18:17.098891 progress 55 % (24 MB)
64 19:18:17.128541 progress 60 % (26 MB)
65 19:18:17.157765 progress 65 % (28 MB)
66 19:18:17.191421 progress 70 % (30 MB)
67 19:18:17.221148 progress 75 % (32 MB)
68 19:18:17.251048 progress 80 % (34 MB)
69 19:18:17.283696 progress 85 % (37 MB)
70 19:18:17.312471 progress 90 % (39 MB)
71 19:18:17.343286 progress 95 % (41 MB)
72 19:18:17.372778 progress 100 % (43 MB)
73 19:18:17.373358 43 MB downloaded in 0.65 s (66.62 MB/s)
74 19:18:17.373898 end: 1.2.1 http-download (duration 00:00:01) [common]
76 19:18:17.374819 end: 1.2 download-retry (duration 00:00:01) [common]
77 19:18:17.375135 start: 1.3 download-retry (timeout 00:09:59) [common]
78 19:18:17.375444 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 19:18:17.375945 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-679-gc8994e7b0f32/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 19:18:17.376252 saving as /var/lib/lava/dispatcher/tmp/967959/tftp-deploy-mszqrz52/dtb/meson-g12b-a311d-libretech-cc.dtb
81 19:18:17.376464 total size: 54703 (0 MB)
82 19:18:17.376674 No compression specified
83 19:18:17.414624 progress 59 % (0 MB)
84 19:18:17.415545 progress 100 % (0 MB)
85 19:18:17.416215 0 MB downloaded in 0.04 s (1.31 MB/s)
86 19:18:17.416738 end: 1.3.1 http-download (duration 00:00:00) [common]
88 19:18:17.417627 end: 1.3 download-retry (duration 00:00:00) [common]
89 19:18:17.417935 start: 1.4 download-retry (timeout 00:09:59) [common]
90 19:18:17.418241 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 19:18:17.418741 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-679-gc8994e7b0f32/arm64/defconfig/gcc-12/modules.tar.xz
92 19:18:17.418994 saving as /var/lib/lava/dispatcher/tmp/967959/tftp-deploy-mszqrz52/modules/modules.tar
93 19:18:17.419239 total size: 11612124 (11 MB)
94 19:18:17.419458 Using unxz to decompress xz
95 19:18:17.457648 progress 0 % (0 MB)
96 19:18:17.524079 progress 5 % (0 MB)
97 19:18:17.600764 progress 10 % (1 MB)
98 19:18:17.696587 progress 15 % (1 MB)
99 19:18:17.788582 progress 20 % (2 MB)
100 19:18:17.867918 progress 25 % (2 MB)
101 19:18:17.943525 progress 30 % (3 MB)
102 19:18:18.022266 progress 35 % (3 MB)
103 19:18:18.095290 progress 40 % (4 MB)
104 19:18:18.172387 progress 45 % (5 MB)
105 19:18:18.256718 progress 50 % (5 MB)
106 19:18:18.333371 progress 55 % (6 MB)
107 19:18:18.418232 progress 60 % (6 MB)
108 19:18:18.498693 progress 65 % (7 MB)
109 19:18:18.579675 progress 70 % (7 MB)
110 19:18:18.658216 progress 75 % (8 MB)
111 19:18:18.741357 progress 80 % (8 MB)
112 19:18:18.821086 progress 85 % (9 MB)
113 19:18:18.901178 progress 90 % (9 MB)
114 19:18:18.978064 progress 95 % (10 MB)
115 19:18:19.054339 progress 100 % (11 MB)
116 19:18:19.065952 11 MB downloaded in 1.65 s (6.73 MB/s)
117 19:18:19.066890 end: 1.4.1 http-download (duration 00:00:02) [common]
119 19:18:19.068684 end: 1.4 download-retry (duration 00:00:02) [common]
120 19:18:19.069261 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 19:18:19.069831 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 19:18:19.070368 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 19:18:19.070927 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 19:18:19.072018 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p
125 19:18:19.072935 makedir: /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin
126 19:18:19.073645 makedir: /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/tests
127 19:18:19.074348 makedir: /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/results
128 19:18:19.075020 Creating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin/lava-add-keys
129 19:18:19.076110 Creating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin/lava-add-sources
130 19:18:19.077120 Creating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin/lava-background-process-start
131 19:18:19.078131 Creating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin/lava-background-process-stop
132 19:18:19.079188 Creating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin/lava-common-functions
133 19:18:19.080333 Creating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin/lava-echo-ipv4
134 19:18:19.081333 Creating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin/lava-install-packages
135 19:18:19.082320 Creating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin/lava-installed-packages
136 19:18:19.083304 Creating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin/lava-os-build
137 19:18:19.084315 Creating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin/lava-probe-channel
138 19:18:19.085282 Creating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin/lava-probe-ip
139 19:18:19.086242 Creating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin/lava-target-ip
140 19:18:19.087200 Creating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin/lava-target-mac
141 19:18:19.088186 Creating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin/lava-target-storage
142 19:18:19.089179 Creating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin/lava-test-case
143 19:18:19.090171 Creating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin/lava-test-event
144 19:18:19.091150 Creating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin/lava-test-feedback
145 19:18:19.092143 Creating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin/lava-test-raise
146 19:18:19.093118 Creating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin/lava-test-reference
147 19:18:19.094081 Creating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin/lava-test-runner
148 19:18:19.095043 Creating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin/lava-test-set
149 19:18:19.096027 Creating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin/lava-test-shell
150 19:18:19.097012 Updating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin/lava-install-packages (oe)
151 19:18:19.098056 Updating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/bin/lava-installed-packages (oe)
152 19:18:19.098941 Creating /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/environment
153 19:18:19.099696 LAVA metadata
154 19:18:19.100341 - LAVA_JOB_ID=967959
155 19:18:19.100820 - LAVA_DISPATCHER_IP=192.168.6.2
156 19:18:19.101540 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 19:18:19.103540 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 19:18:19.104235 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 19:18:19.104694 skipped lava-vland-overlay
160 19:18:19.105231 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 19:18:19.105790 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 19:18:19.106258 skipped lava-multinode-overlay
163 19:18:19.106788 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 19:18:19.107337 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 19:18:19.107857 Loading test definitions
166 19:18:19.108512 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 19:18:19.108956 Using /lava-967959 at stage 0
168 19:18:19.111179 uuid=967959_1.5.2.4.1 testdef=None
169 19:18:19.111752 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 19:18:19.112213 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 19:18:19.114040 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 19:18:19.114838 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 19:18:19.117123 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 19:18:19.117952 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 19:18:19.120145 runner path: /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/0/tests/0_dmesg test_uuid 967959_1.5.2.4.1
178 19:18:19.120701 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 19:18:19.121467 Creating lava-test-runner.conf files
181 19:18:19.121668 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/967959/lava-overlay-aopevw3p/lava-967959/0 for stage 0
182 19:18:19.122000 - 0_dmesg
183 19:18:19.122343 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 19:18:19.122622 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 19:18:19.146162 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 19:18:19.146547 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 19:18:19.146809 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 19:18:19.147072 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 19:18:19.147333 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 19:18:20.066016 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
191 19:18:20.066467 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
192 19:18:20.066716 extracting modules file /var/lib/lava/dispatcher/tmp/967959/tftp-deploy-mszqrz52/modules/modules.tar to /var/lib/lava/dispatcher/tmp/967959/extract-overlay-ramdisk-hss1ciby/ramdisk
193 19:18:21.403813 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 19:18:21.404299 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
195 19:18:21.404590 [common] Applying overlay /var/lib/lava/dispatcher/tmp/967959/compress-overlay-lvvyf1wu/overlay-1.5.2.5.tar.gz to ramdisk
196 19:18:21.404818 [common] Applying overlay /var/lib/lava/dispatcher/tmp/967959/compress-overlay-lvvyf1wu/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/967959/extract-overlay-ramdisk-hss1ciby/ramdisk
197 19:18:21.434825 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 19:18:21.435220 start: 1.5.6 prepare-kernel (timeout 00:09:55) [common]
199 19:18:21.435482 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:55) [common]
200 19:18:21.435705 Converting downloaded kernel to a uImage
201 19:18:21.436040 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/967959/tftp-deploy-mszqrz52/kernel/Image /var/lib/lava/dispatcher/tmp/967959/tftp-deploy-mszqrz52/kernel/uImage
202 19:18:21.897422 output: Image Name:
203 19:18:21.897846 output: Created: Sat Nov 9 19:18:21 2024
204 19:18:21.898056 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 19:18:21.898260 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 19:18:21.898461 output: Load Address: 01080000
207 19:18:21.898659 output: Entry Point: 01080000
208 19:18:21.898856 output:
209 19:18:21.899189 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 19:18:21.899452 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 19:18:21.899718 start: 1.5.7 configure-preseed-file (timeout 00:09:55) [common]
212 19:18:21.899967 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 19:18:21.900275 start: 1.5.8 compress-ramdisk (timeout 00:09:55) [common]
214 19:18:21.900531 Building ramdisk /var/lib/lava/dispatcher/tmp/967959/extract-overlay-ramdisk-hss1ciby/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/967959/extract-overlay-ramdisk-hss1ciby/ramdisk
215 19:18:24.251387 >> 181610 blocks
216 19:18:32.824856 Adding RAMdisk u-boot header.
217 19:18:32.825434 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/967959/extract-overlay-ramdisk-hss1ciby/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/967959/extract-overlay-ramdisk-hss1ciby/ramdisk.cpio.gz.uboot
218 19:18:33.104986 output: Image Name:
219 19:18:33.105403 output: Created: Sat Nov 9 19:18:32 2024
220 19:18:33.105608 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 19:18:33.105809 output: Data Size: 26060277 Bytes = 25449.49 KiB = 24.85 MiB
222 19:18:33.106006 output: Load Address: 00000000
223 19:18:33.106203 output: Entry Point: 00000000
224 19:18:33.106396 output:
225 19:18:33.106976 rename /var/lib/lava/dispatcher/tmp/967959/extract-overlay-ramdisk-hss1ciby/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/967959/tftp-deploy-mszqrz52/ramdisk/ramdisk.cpio.gz.uboot
226 19:18:33.107381 end: 1.5.8 compress-ramdisk (duration 00:00:11) [common]
227 19:18:33.107663 end: 1.5 prepare-tftp-overlay (duration 00:00:14) [common]
228 19:18:33.107964 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
229 19:18:33.108542 No LXC device requested
230 19:18:33.109109 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 19:18:33.109664 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
232 19:18:33.110198 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 19:18:33.110646 Checking files for TFTP limit of 4294967296 bytes.
234 19:18:33.113572 end: 1 tftp-deploy (duration 00:00:17) [common]
235 19:18:33.114193 start: 2 uboot-action (timeout 00:05:00) [common]
236 19:18:33.114764 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 19:18:33.115304 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 19:18:33.115851 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 19:18:33.116461 Using kernel file from prepare-kernel: 967959/tftp-deploy-mszqrz52/kernel/uImage
240 19:18:33.117122 substitutions:
241 19:18:33.117568 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 19:18:33.118014 - {DTB_ADDR}: 0x01070000
243 19:18:33.118450 - {DTB}: 967959/tftp-deploy-mszqrz52/dtb/meson-g12b-a311d-libretech-cc.dtb
244 19:18:33.118888 - {INITRD}: 967959/tftp-deploy-mszqrz52/ramdisk/ramdisk.cpio.gz.uboot
245 19:18:33.119320 - {KERNEL_ADDR}: 0x01080000
246 19:18:33.119751 - {KERNEL}: 967959/tftp-deploy-mszqrz52/kernel/uImage
247 19:18:33.120220 - {LAVA_MAC}: None
248 19:18:33.120694 - {PRESEED_CONFIG}: None
249 19:18:33.121127 - {PRESEED_LOCAL}: None
250 19:18:33.121558 - {RAMDISK_ADDR}: 0x08000000
251 19:18:33.121983 - {RAMDISK}: 967959/tftp-deploy-mszqrz52/ramdisk/ramdisk.cpio.gz.uboot
252 19:18:33.122416 - {ROOT_PART}: None
253 19:18:33.122845 - {ROOT}: None
254 19:18:33.123272 - {SERVER_IP}: 192.168.6.2
255 19:18:33.123702 - {TEE_ADDR}: 0x83000000
256 19:18:33.124157 - {TEE}: None
257 19:18:33.124587 Parsed boot commands:
258 19:18:33.125003 - setenv autoload no
259 19:18:33.125427 - setenv initrd_high 0xffffffff
260 19:18:33.125851 - setenv fdt_high 0xffffffff
261 19:18:33.126272 - dhcp
262 19:18:33.126696 - setenv serverip 192.168.6.2
263 19:18:33.127116 - tftpboot 0x01080000 967959/tftp-deploy-mszqrz52/kernel/uImage
264 19:18:33.127539 - tftpboot 0x08000000 967959/tftp-deploy-mszqrz52/ramdisk/ramdisk.cpio.gz.uboot
265 19:18:33.127963 - tftpboot 0x01070000 967959/tftp-deploy-mszqrz52/dtb/meson-g12b-a311d-libretech-cc.dtb
266 19:18:33.128416 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 19:18:33.128850 - bootm 0x01080000 0x08000000 0x01070000
268 19:18:33.129381 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 19:18:33.131002 start: 2.3 connect-device (timeout 00:05:00) [common]
271 19:18:33.131479 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 19:18:33.146820 Setting prompt string to ['lava-test: # ']
273 19:18:33.148459 end: 2.3 connect-device (duration 00:00:00) [common]
274 19:18:33.149104 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 19:18:33.149731 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 19:18:33.150310 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 19:18:33.151558 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 19:18:33.189244 >> OK - accepted request
279 19:18:33.191408 Returned 0 in 0 seconds
280 19:18:33.292610 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 19:18:33.294302 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 19:18:33.294894 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 19:18:33.295449 Setting prompt string to ['Hit any key to stop autoboot']
285 19:18:33.295946 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 19:18:33.297677 Trying 192.168.56.21...
287 19:18:33.298187 Connected to conserv1.
288 19:18:33.298630 Escape character is '^]'.
289 19:18:33.299093
290 19:18:33.299560 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
291 19:18:33.300065
292 19:18:45.522515 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 19:18:45.523219 bl2_stage_init 0x01
294 19:18:45.523725 bl2_stage_init 0x81
295 19:18:45.528088 hw id: 0x0000 - pwm id 0x01
296 19:18:45.528686 bl2_stage_init 0xc1
297 19:18:45.529173 bl2_stage_init 0x02
298 19:18:45.529643
299 19:18:45.533712 L0:00000000
300 19:18:45.534195 L1:20000703
301 19:18:45.534628 L2:00008067
302 19:18:45.535059 L3:14000000
303 19:18:45.536468 B2:00402000
304 19:18:45.536929 B1:e0f83180
305 19:18:45.537359
306 19:18:45.537788 TE: 58124
307 19:18:45.538219
308 19:18:45.547650 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 19:18:45.548163
310 19:18:45.548596 Board ID = 1
311 19:18:45.549022 Set A53 clk to 24M
312 19:18:45.549452 Set A73 clk to 24M
313 19:18:45.553196 Set clk81 to 24M
314 19:18:45.553689 A53 clk: 1200 MHz
315 19:18:45.554117 A73 clk: 1200 MHz
316 19:18:45.556760 CLK81: 166.6M
317 19:18:45.557227 smccc: 00012a91
318 19:18:45.562428 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 19:18:45.567953 board id: 1
320 19:18:45.573226 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 19:18:45.583645 fw parse done
322 19:18:45.589575 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 19:18:45.632209 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 19:18:45.643256 PIEI prepare done
325 19:18:45.643726 fastboot data load
326 19:18:45.644215 fastboot data verify
327 19:18:45.648789 verify result: 266
328 19:18:45.654364 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 19:18:45.654910 LPDDR4 probe
330 19:18:45.655379 ddr clk to 1584MHz
331 19:18:45.662370 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 19:18:45.699605
333 19:18:45.700131 dmc_version 0001
334 19:18:45.706369 Check phy result
335 19:18:45.712301 INFO : End of CA training
336 19:18:45.712792 INFO : End of initialization
337 19:18:45.717794 INFO : Training has run successfully!
338 19:18:45.718275 Check phy result
339 19:18:45.723335 INFO : End of initialization
340 19:18:45.723802 INFO : End of read enable training
341 19:18:45.726661 INFO : End of fine write leveling
342 19:18:45.732313 INFO : End of Write leveling coarse delay
343 19:18:45.737935 INFO : Training has run successfully!
344 19:18:45.738399 Check phy result
345 19:18:45.738845 INFO : End of initialization
346 19:18:45.743491 INFO : End of read dq deskew training
347 19:18:45.746886 INFO : End of MPR read delay center optimization
348 19:18:45.752415 INFO : End of write delay center optimization
349 19:18:45.757963 INFO : End of read delay center optimization
350 19:18:45.758431 INFO : End of max read latency training
351 19:18:45.763557 INFO : Training has run successfully!
352 19:18:45.764064 1D training succeed
353 19:18:45.771870 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 19:18:45.819346 Check phy result
355 19:18:45.819880 INFO : End of initialization
356 19:18:45.841938 INFO : End of 2D read delay Voltage center optimization
357 19:18:45.862137 INFO : End of 2D read delay Voltage center optimization
358 19:18:45.914318 INFO : End of 2D write delay Voltage center optimization
359 19:18:45.963687 INFO : End of 2D write delay Voltage center optimization
360 19:18:45.969283 INFO : Training has run successfully!
361 19:18:45.969769
362 19:18:45.970225 channel==0
363 19:18:45.974753 RxClkDly_Margin_A0==88 ps 9
364 19:18:45.975236 TxDqDly_Margin_A0==98 ps 10
365 19:18:45.980317 RxClkDly_Margin_A1==88 ps 9
366 19:18:45.980786 TxDqDly_Margin_A1==98 ps 10
367 19:18:45.981231 TrainedVREFDQ_A0==74
368 19:18:45.986021 TrainedVREFDQ_A1==74
369 19:18:45.986495 VrefDac_Margin_A0==25
370 19:18:45.986939 DeviceVref_Margin_A0==40
371 19:18:45.991574 VrefDac_Margin_A1==25
372 19:18:45.992078 DeviceVref_Margin_A1==40
373 19:18:45.992528
374 19:18:45.992970
375 19:18:45.997093 channel==1
376 19:18:45.997562 RxClkDly_Margin_A0==98 ps 10
377 19:18:45.998007 TxDqDly_Margin_A0==98 ps 10
378 19:18:46.002734 RxClkDly_Margin_A1==98 ps 10
379 19:18:46.003199 TxDqDly_Margin_A1==98 ps 10
380 19:18:46.008427 TrainedVREFDQ_A0==77
381 19:18:46.008899 TrainedVREFDQ_A1==77
382 19:18:46.009346 VrefDac_Margin_A0==22
383 19:18:46.013894 DeviceVref_Margin_A0==37
384 19:18:46.014353 VrefDac_Margin_A1==22
385 19:18:46.019523 DeviceVref_Margin_A1==37
386 19:18:46.020016
387 19:18:46.020480 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 19:18:46.025007
389 19:18:46.053068 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
390 19:18:46.053645 2D training succeed
391 19:18:46.058743 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 19:18:46.064257 auto size-- 65535DDR cs0 size: 2048MB
393 19:18:46.064731 DDR cs1 size: 2048MB
394 19:18:46.069875 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 19:18:46.070341 cs0 DataBus test pass
396 19:18:46.075522 cs1 DataBus test pass
397 19:18:46.076029 cs0 AddrBus test pass
398 19:18:46.076481 cs1 AddrBus test pass
399 19:18:46.076918
400 19:18:46.081097 100bdlr_step_size ps== 420
401 19:18:46.081579 result report
402 19:18:46.086726 boot times 0Enable ddr reg access
403 19:18:46.092396 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 19:18:46.105766 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 19:18:46.679367 0.0;M3 CHK:0;cm4_sp_mode 0
406 19:18:46.679808 MVN_1=0x00000000
407 19:18:46.684817 MVN_2=0x00000000
408 19:18:46.690572 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 19:18:46.691136 OPS=0x10
410 19:18:46.691629 ring efuse init
411 19:18:46.692123 chipver efuse init
412 19:18:46.698830 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 19:18:46.699328 [0.018961 Inits done]
414 19:18:46.706369 secure task start!
415 19:18:46.706864 high task start!
416 19:18:46.707309 low task start!
417 19:18:46.707743 run into bl31
418 19:18:46.713007 NOTICE: BL31: v1.3(release):4fc40b1
419 19:18:46.720819 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 19:18:46.721305 NOTICE: BL31: G12A normal boot!
421 19:18:46.746300 NOTICE: BL31: BL33 decompress pass
422 19:18:46.751963 ERROR: Error initializing runtime service opteed_fast
423 19:18:47.984959
424 19:18:47.985631
425 19:18:47.993288 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 19:18:47.993855
427 19:18:47.994335 Model: Libre Computer AML-A311D-CC Alta
428 19:18:48.201747 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 19:18:48.225067 DRAM: 2 GiB (effective 3.8 GiB)
430 19:18:48.368150 Core: 408 devices, 31 uclasses, devicetree: separate
431 19:18:48.373908 WDT: Not starting watchdog@f0d0
432 19:18:48.406227 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 19:18:48.418658 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 19:18:48.423616 ** Bad device specification mmc 0 **
435 19:18:48.433941 Card did not respond to voltage select! : -110
436 19:18:48.441592 ** Bad device specification mmc 0 **
437 19:18:48.442136 Couldn't find partition mmc 0
438 19:18:48.449979 Card did not respond to voltage select! : -110
439 19:18:48.455522 ** Bad device specification mmc 0 **
440 19:18:48.456103 Couldn't find partition mmc 0
441 19:18:48.460577 Error: could not access storage.
442 19:18:49.722962 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
443 19:18:49.723667 bl2_stage_init 0x81
444 19:18:49.728457 hw id: 0x0000 - pwm id 0x01
445 19:18:49.729046 bl2_stage_init 0xc1
446 19:18:49.729516 bl2_stage_init 0x02
447 19:18:49.730001
448 19:18:49.734038 L0:00000000
449 19:18:49.734786 L1:20000703
450 19:18:49.735280 L2:00008067
451 19:18:49.735738 L3:14000000
452 19:18:49.736233 B2:00402000
453 19:18:49.739638 B1:e0f83180
454 19:18:49.740173
455 19:18:49.740642 TE: 58150
456 19:18:49.741095
457 19:18:49.745271 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 19:18:49.745817
459 19:18:49.746302 Board ID = 1
460 19:18:49.750835 Set A53 clk to 24M
461 19:18:49.751349 Set A73 clk to 24M
462 19:18:49.751807 Set clk81 to 24M
463 19:18:49.756516 A53 clk: 1200 MHz
464 19:18:49.757356 A73 clk: 1200 MHz
465 19:18:49.757916 CLK81: 166.6M
466 19:18:49.758396 smccc: 00012aab
467 19:18:49.762039 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 19:18:49.767633 board id: 1
469 19:18:49.774636 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 19:18:49.784127 fw parse done
471 19:18:49.790062 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 19:18:49.832760 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 19:18:49.843667 PIEI prepare done
474 19:18:49.844274 fastboot data load
475 19:18:49.844763 fastboot data verify
476 19:18:49.849308 verify result: 266
477 19:18:49.854947 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 19:18:49.855706 LPDDR4 probe
479 19:18:49.856297 ddr clk to 1584MHz
480 19:18:49.862852 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 19:18:49.900107
482 19:18:49.900646 dmc_version 0001
483 19:18:49.906791 Check phy result
484 19:18:49.912736 INFO : End of CA training
485 19:18:49.913243 INFO : End of initialization
486 19:18:49.918253 INFO : Training has run successfully!
487 19:18:49.918748 Check phy result
488 19:18:49.923813 INFO : End of initialization
489 19:18:49.924332 INFO : End of read enable training
490 19:18:49.929427 INFO : End of fine write leveling
491 19:18:49.935044 INFO : End of Write leveling coarse delay
492 19:18:49.935524 INFO : Training has run successfully!
493 19:18:49.936006 Check phy result
494 19:18:49.940726 INFO : End of initialization
495 19:18:49.941216 INFO : End of read dq deskew training
496 19:18:49.946220 INFO : End of MPR read delay center optimization
497 19:18:49.951834 INFO : End of write delay center optimization
498 19:18:49.957419 INFO : End of read delay center optimization
499 19:18:49.957919 INFO : End of max read latency training
500 19:18:49.963040 INFO : Training has run successfully!
501 19:18:49.963553 1D training succeed
502 19:18:49.972223 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 19:18:50.019908 Check phy result
504 19:18:50.020538 INFO : End of initialization
505 19:18:50.041568 INFO : End of 2D read delay Voltage center optimization
506 19:18:50.061902 INFO : End of 2D read delay Voltage center optimization
507 19:18:50.113923 INFO : End of 2D write delay Voltage center optimization
508 19:18:50.163269 INFO : End of 2D write delay Voltage center optimization
509 19:18:50.168794 INFO : Training has run successfully!
510 19:18:50.169375
511 19:18:50.169858 channel==0
512 19:18:50.174381 RxClkDly_Margin_A0==88 ps 9
513 19:18:50.174910 TxDqDly_Margin_A0==98 ps 10
514 19:18:50.179967 RxClkDly_Margin_A1==88 ps 9
515 19:18:50.180529 TxDqDly_Margin_A1==88 ps 9
516 19:18:50.181001 TrainedVREFDQ_A0==74
517 19:18:50.185611 TrainedVREFDQ_A1==74
518 19:18:50.186128 VrefDac_Margin_A0==25
519 19:18:50.186582 DeviceVref_Margin_A0==40
520 19:18:50.191168 VrefDac_Margin_A1==25
521 19:18:50.191698 DeviceVref_Margin_A1==40
522 19:18:50.192208
523 19:18:50.192688
524 19:18:50.193157 channel==1
525 19:18:50.196766 RxClkDly_Margin_A0==98 ps 10
526 19:18:50.197341 TxDqDly_Margin_A0==98 ps 10
527 19:18:50.202464 RxClkDly_Margin_A1==98 ps 10
528 19:18:50.203006 TxDqDly_Margin_A1==98 ps 10
529 19:18:50.208019 TrainedVREFDQ_A0==77
530 19:18:50.208588 TrainedVREFDQ_A1==77
531 19:18:50.209071 VrefDac_Margin_A0==22
532 19:18:50.213579 DeviceVref_Margin_A0==37
533 19:18:50.214099 VrefDac_Margin_A1==22
534 19:18:50.219143 DeviceVref_Margin_A1==37
535 19:18:50.219661
536 19:18:50.220175 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 19:18:50.224763
538 19:18:50.252744 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
539 19:18:50.253327 2D training succeed
540 19:18:50.258373 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 19:18:50.264049 auto size-- 65535DDR cs0 size: 2048MB
542 19:18:50.264638 DDR cs1 size: 2048MB
543 19:18:50.269605 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 19:18:50.270174 cs0 DataBus test pass
545 19:18:50.275163 cs1 DataBus test pass
546 19:18:50.275704 cs0 AddrBus test pass
547 19:18:50.276228 cs1 AddrBus test pass
548 19:18:50.276708
549 19:18:50.280771 100bdlr_step_size ps== 420
550 19:18:50.281303 result report
551 19:18:50.286386 boot times 0Enable ddr reg access
552 19:18:50.291861 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 19:18:50.305289 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 19:18:50.879014 0.0;M3 CHK:0;cm4_sp_mode 0
555 19:18:50.879685 MVN_1=0x00000000
556 19:18:50.884295 MVN_2=0x00000000
557 19:18:50.890146 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 19:18:50.890676 OPS=0x10
559 19:18:50.891142 ring efuse init
560 19:18:50.891618 chipver efuse init
561 19:18:50.898403 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 19:18:50.898940 [0.018961 Inits done]
563 19:18:50.899375 secure task start!
564 19:18:50.905892 high task start!
565 19:18:50.906371 low task start!
566 19:18:50.906800 run into bl31
567 19:18:50.912502 NOTICE: BL31: v1.3(release):4fc40b1
568 19:18:50.920327 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 19:18:50.920816 NOTICE: BL31: G12A normal boot!
570 19:18:50.945738 NOTICE: BL31: BL33 decompress pass
571 19:18:50.951443 ERROR: Error initializing runtime service opteed_fast
572 19:18:52.184589
573 19:18:52.185237
574 19:18:52.192993 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 19:18:52.193578
576 19:18:52.194083 Model: Libre Computer AML-A311D-CC Alta
577 19:18:52.400671 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 19:18:52.424853 DRAM: 2 GiB (effective 3.8 GiB)
579 19:18:52.567928 Core: 408 devices, 31 uclasses, devicetree: separate
580 19:18:52.573638 WDT: Not starting watchdog@f0d0
581 19:18:52.605923 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 19:18:52.618305 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 19:18:52.623401 ** Bad device specification mmc 0 **
584 19:18:52.633680 Card did not respond to voltage select! : -110
585 19:18:52.641552 ** Bad device specification mmc 0 **
586 19:18:52.642039 Couldn't find partition mmc 0
587 19:18:52.649634 Card did not respond to voltage select! : -110
588 19:18:52.655114 ** Bad device specification mmc 0 **
589 19:18:52.655603 Couldn't find partition mmc 0
590 19:18:52.660195 Error: could not access storage.
591 19:18:53.002721 Net: eth0: ethernet@ff3f0000
592 19:18:53.003334 starting USB...
593 19:18:53.254408 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 19:18:53.254937 Starting the controller
595 19:18:53.261526 USB XHCI 1.10
596 19:18:54.971851 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
597 19:18:54.972537 bl2_stage_init 0x81
598 19:18:54.977404 hw id: 0x0000 - pwm id 0x01
599 19:18:54.977858 bl2_stage_init 0xc1
600 19:18:54.978276 bl2_stage_init 0x02
601 19:18:54.978677
602 19:18:54.982951 L0:00000000
603 19:18:54.983392 L1:20000703
604 19:18:54.983803 L2:00008067
605 19:18:54.984246 L3:14000000
606 19:18:54.984649 B2:00402000
607 19:18:54.985817 B1:e0f83180
608 19:18:54.986256
609 19:18:54.986663 TE: 58150
610 19:18:54.987068
611 19:18:54.996911 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
612 19:18:54.997371
613 19:18:54.997783 Board ID = 1
614 19:18:54.998185 Set A53 clk to 24M
615 19:18:54.998585 Set A73 clk to 24M
616 19:18:55.002598 Set clk81 to 24M
617 19:18:55.003038 A53 clk: 1200 MHz
618 19:18:55.003446 A73 clk: 1200 MHz
619 19:18:55.008197 CLK81: 166.6M
620 19:18:55.008633 smccc: 00012aab
621 19:18:55.013699 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
622 19:18:55.014135 board id: 1
623 19:18:55.022856 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
624 19:18:55.032948 fw parse done
625 19:18:55.038931 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
626 19:18:55.081582 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
627 19:18:55.092484 PIEI prepare done
628 19:18:55.092928 fastboot data load
629 19:18:55.093339 fastboot data verify
630 19:18:55.098095 verify result: 266
631 19:18:55.103634 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
632 19:18:55.104115 LPDDR4 probe
633 19:18:55.104527 ddr clk to 1584MHz
634 19:18:55.111639 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
635 19:18:55.148909
636 19:18:55.149360 dmc_version 0001
637 19:18:55.155619 Check phy result
638 19:18:55.161474 INFO : End of CA training
639 19:18:55.161912 INFO : End of initialization
640 19:18:55.167024 INFO : Training has run successfully!
641 19:18:55.167452 Check phy result
642 19:18:55.172576 INFO : End of initialization
643 19:18:55.173006 INFO : End of read enable training
644 19:18:55.175957 INFO : End of fine write leveling
645 19:18:55.181514 INFO : End of Write leveling coarse delay
646 19:18:55.187110 INFO : Training has run successfully!
647 19:18:55.187545 Check phy result
648 19:18:55.187953 INFO : End of initialization
649 19:18:55.192695 INFO : End of read dq deskew training
650 19:18:55.196112 INFO : End of MPR read delay center optimization
651 19:18:55.201624 INFO : End of write delay center optimization
652 19:18:55.207228 INFO : End of read delay center optimization
653 19:18:55.207663 INFO : End of max read latency training
654 19:18:55.212771 INFO : Training has run successfully!
655 19:18:55.213220 1D training succeed
656 19:18:55.221106 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
657 19:18:55.268622 Check phy result
658 19:18:55.269058 INFO : End of initialization
659 19:18:55.290481 INFO : End of 2D read delay Voltage center optimization
660 19:18:55.310606 INFO : End of 2D read delay Voltage center optimization
661 19:18:55.362760 INFO : End of 2D write delay Voltage center optimization
662 19:18:55.412075 INFO : End of 2D write delay Voltage center optimization
663 19:18:55.417718 INFO : Training has run successfully!
664 19:18:55.418266
665 19:18:55.418688 channel==0
666 19:18:55.423254 RxClkDly_Margin_A0==88 ps 9
667 19:18:55.423697 TxDqDly_Margin_A0==108 ps 11
668 19:18:55.426627 RxClkDly_Margin_A1==88 ps 9
669 19:18:55.427064 TxDqDly_Margin_A1==98 ps 10
670 19:18:55.432224 TrainedVREFDQ_A0==74
671 19:18:55.432657 TrainedVREFDQ_A1==75
672 19:18:55.437657 VrefDac_Margin_A0==25
673 19:18:55.438091 DeviceVref_Margin_A0==40
674 19:18:55.438494 VrefDac_Margin_A1==25
675 19:18:55.443473 DeviceVref_Margin_A1==39
676 19:18:55.443909
677 19:18:55.444359
678 19:18:55.444764 channel==1
679 19:18:55.445157 RxClkDly_Margin_A0==98 ps 10
680 19:18:55.448941 TxDqDly_Margin_A0==88 ps 9
681 19:18:55.449417 RxClkDly_Margin_A1==98 ps 10
682 19:18:55.454553 TxDqDly_Margin_A1==88 ps 9
683 19:18:55.454995 TrainedVREFDQ_A0==76
684 19:18:55.455403 TrainedVREFDQ_A1==77
685 19:18:55.460237 VrefDac_Margin_A0==22
686 19:18:55.460676 DeviceVref_Margin_A0==38
687 19:18:55.465722 VrefDac_Margin_A1==24
688 19:18:55.466154 DeviceVref_Margin_A1==37
689 19:18:55.466557
690 19:18:55.471438 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
691 19:18:55.471887
692 19:18:55.499429 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000018 00000018 00000019 00000018 0000001a 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
693 19:18:55.504910 2D training succeed
694 19:18:55.510513 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
695 19:18:55.510969 auto size-- 65535DDR cs0 size: 2048MB
696 19:18:55.516173 DDR cs1 size: 2048MB
697 19:18:55.516630 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
698 19:18:55.521685 cs0 DataBus test pass
699 19:18:55.522130 cs1 DataBus test pass
700 19:18:55.522533 cs0 AddrBus test pass
701 19:18:55.527414 cs1 AddrBus test pass
702 19:18:55.527854
703 19:18:55.528310 100bdlr_step_size ps== 420
704 19:18:55.528725 result report
705 19:18:55.532871 boot times 0Enable ddr reg access
706 19:18:55.540648 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
707 19:18:55.554118 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
708 19:18:56.127900 0.0;M3 CHK:0;cm4_sp_mode 0
709 19:18:56.128560 MVN_1=0x00000000
710 19:18:56.133311 MVN_2=0x00000000
711 19:18:56.139080 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
712 19:18:56.139628 OPS=0x10
713 19:18:56.140071 ring efuse init
714 19:18:56.140466 chipver efuse init
715 19:18:56.144619 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
716 19:18:56.150228 [0.018960 Inits done]
717 19:18:56.150664 secure task start!
718 19:18:56.151053 high task start!
719 19:18:56.154809 low task start!
720 19:18:56.155234 run into bl31
721 19:18:56.161477 NOTICE: BL31: v1.3(release):4fc40b1
722 19:18:56.169252 NOTICE: BL31: Built : 15:58:17, May 22 2019
723 19:18:56.169689 NOTICE: BL31: G12A normal boot!
724 19:18:56.194715 NOTICE: BL31: BL33 decompress pass
725 19:18:56.200376 ERROR: Error initializing runtime service opteed_fast
726 19:18:57.433281
727 19:18:57.433904
728 19:18:57.441745 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
729 19:18:57.442292
730 19:18:57.442712 Model: Libre Computer AML-A311D-CC Alta
731 19:18:57.650100 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
732 19:18:57.673436 DRAM: 2 GiB (effective 3.8 GiB)
733 19:18:57.816436 Core: 408 devices, 31 uclasses, devicetree: separate
734 19:18:57.822265 WDT: Not starting watchdog@f0d0
735 19:18:57.854639 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
736 19:18:57.867000 Loading Environment from FAT... Card did not respond to voltage select! : -110
737 19:18:57.871947 ** Bad device specification mmc 0 **
738 19:18:57.882285 Card did not respond to voltage select! : -110
739 19:18:57.889949 ** Bad device specification mmc 0 **
740 19:18:57.890428 Couldn't find partition mmc 0
741 19:18:57.898265 Card did not respond to voltage select! : -110
742 19:18:57.903805 ** Bad device specification mmc 0 **
743 19:18:57.904296 Couldn't find partition mmc 0
744 19:18:57.908838 Error: could not access storage.
745 19:18:58.252422 Net: eth0: ethernet@ff3f0000
746 19:18:58.253028 starting USB...
747 19:18:58.504304 Bus usb@ff500000: Register 3000140 NbrPorts 3
748 19:18:58.504920 Starting the controller
749 19:18:58.511143 USB XHCI 1.10
750 19:19:00.671974 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
751 19:19:00.672680 bl2_stage_init 0x01
752 19:19:00.673141 bl2_stage_init 0x81
753 19:19:00.677548 hw id: 0x0000 - pwm id 0x01
754 19:19:00.678114 bl2_stage_init 0xc1
755 19:19:00.678541 bl2_stage_init 0x02
756 19:19:00.678958
757 19:19:00.683075 L0:00000000
758 19:19:00.683587 L1:20000703
759 19:19:00.684030 L2:00008067
760 19:19:00.684445 L3:14000000
761 19:19:00.688706 B2:00402000
762 19:19:00.689208 B1:e0f83180
763 19:19:00.689615
764 19:19:00.690035 TE: 58167
765 19:19:00.690445
766 19:19:00.694288 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
767 19:19:00.694819
768 19:19:00.695258 Board ID = 1
769 19:19:00.700013 Set A53 clk to 24M
770 19:19:00.700524 Set A73 clk to 24M
771 19:19:00.700934 Set clk81 to 24M
772 19:19:00.705600 A53 clk: 1200 MHz
773 19:19:00.706120 A73 clk: 1200 MHz
774 19:19:00.706559 CLK81: 166.6M
775 19:19:00.706964 smccc: 00012abd
776 19:19:00.711027 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
777 19:19:00.716661 board id: 1
778 19:19:00.722541 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
779 19:19:00.733180 fw parse done
780 19:19:00.739266 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
781 19:19:00.781848 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
782 19:19:00.792695 PIEI prepare done
783 19:19:00.793216 fastboot data load
784 19:19:00.793675 fastboot data verify
785 19:19:00.798336 verify result: 266
786 19:19:00.804026 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
787 19:19:00.804518 LPDDR4 probe
788 19:19:00.804976 ddr clk to 1584MHz
789 19:19:00.811893 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
790 19:19:00.849168
791 19:19:00.849824 dmc_version 0001
792 19:19:00.855933 Check phy result
793 19:19:00.861742 INFO : End of CA training
794 19:19:00.862266 INFO : End of initialization
795 19:19:00.867279 INFO : Training has run successfully!
796 19:19:00.867779 Check phy result
797 19:19:00.872940 INFO : End of initialization
798 19:19:00.873418 INFO : End of read enable training
799 19:19:00.876286 INFO : End of fine write leveling
800 19:19:00.881847 INFO : End of Write leveling coarse delay
801 19:19:00.887437 INFO : Training has run successfully!
802 19:19:00.887929 Check phy result
803 19:19:00.888375 INFO : End of initialization
804 19:19:00.892994 INFO : End of read dq deskew training
805 19:19:00.896475 INFO : End of MPR read delay center optimization
806 19:19:00.902031 INFO : End of write delay center optimization
807 19:19:00.907724 INFO : End of read delay center optimization
808 19:19:00.908280 INFO : End of max read latency training
809 19:19:00.913355 INFO : Training has run successfully!
810 19:19:00.913872 1D training succeed
811 19:19:00.921431 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
812 19:19:00.968945 Check phy result
813 19:19:00.969559 INFO : End of initialization
814 19:19:00.991517 INFO : End of 2D read delay Voltage center optimization
815 19:19:01.011761 INFO : End of 2D read delay Voltage center optimization
816 19:19:01.063866 INFO : End of 2D write delay Voltage center optimization
817 19:19:01.113222 INFO : End of 2D write delay Voltage center optimization
818 19:19:01.118775 INFO : Training has run successfully!
819 19:19:01.119305
820 19:19:01.119729 channel==0
821 19:19:01.124488 RxClkDly_Margin_A0==88 ps 9
822 19:19:01.125008 TxDqDly_Margin_A0==98 ps 10
823 19:19:01.129946 RxClkDly_Margin_A1==88 ps 9
824 19:19:01.130446 TxDqDly_Margin_A1==98 ps 10
825 19:19:01.130879 TrainedVREFDQ_A0==74
826 19:19:01.135625 TrainedVREFDQ_A1==74
827 19:19:01.136165 VrefDac_Margin_A0==24
828 19:19:01.136581 DeviceVref_Margin_A0==40
829 19:19:01.141086 VrefDac_Margin_A1==25
830 19:19:01.141602 DeviceVref_Margin_A1==40
831 19:19:01.141990
832 19:19:01.142379
833 19:19:01.147208 channel==1
834 19:19:01.147571 RxClkDly_Margin_A0==98 ps 10
835 19:19:01.147781 TxDqDly_Margin_A0==88 ps 9
836 19:19:01.152399 RxClkDly_Margin_A1==98 ps 10
837 19:19:01.152934 TxDqDly_Margin_A1==88 ps 9
838 19:19:01.157862 TrainedVREFDQ_A0==77
839 19:19:01.158398 TrainedVREFDQ_A1==77
840 19:19:01.158801 VrefDac_Margin_A0==22
841 19:19:01.163573 DeviceVref_Margin_A0==37
842 19:19:01.164138 VrefDac_Margin_A1==22
843 19:19:01.169162 DeviceVref_Margin_A1==37
844 19:19:01.169676
845 19:19:01.170072 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
846 19:19:01.170460
847 19:19:01.202724 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000017 00000017 00000018 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
848 19:19:01.203333 2D training succeed
849 19:19:01.208381 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
850 19:19:01.213833 auto size-- 65535DDR cs0 size: 2048MB
851 19:19:01.214339 DDR cs1 size: 2048MB
852 19:19:01.219369 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
853 19:19:01.219835 cs0 DataBus test pass
854 19:19:01.224997 cs1 DataBus test pass
855 19:19:01.225452 cs0 AddrBus test pass
856 19:19:01.225843 cs1 AddrBus test pass
857 19:19:01.226227
858 19:19:01.230556 100bdlr_step_size ps== 420
859 19:19:01.231014 result report
860 19:19:01.236258 boot times 0Enable ddr reg access
861 19:19:01.241608 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
862 19:19:01.255057 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
863 19:19:01.828698 0.0;M3 CHK:0;cm4_sp_mode 0
864 19:19:01.829346 MVN_1=0x00000000
865 19:19:01.834274 MVN_2=0x00000000
866 19:19:01.840094 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
867 19:19:01.840640 OPS=0x10
868 19:19:01.841073 ring efuse init
869 19:19:01.841491 chipver efuse init
870 19:19:01.848360 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
871 19:19:01.848944 [0.018961 Inits done]
872 19:19:01.849369 secure task start!
873 19:19:01.855779 high task start!
874 19:19:01.856326 low task start!
875 19:19:01.856737 run into bl31
876 19:19:01.862438 NOTICE: BL31: v1.3(release):4fc40b1
877 19:19:01.870205 NOTICE: BL31: Built : 15:58:17, May 22 2019
878 19:19:01.870733 NOTICE: BL31: G12A normal boot!
879 19:19:01.895597 NOTICE: BL31: BL33 decompress pass
880 19:19:01.901349 ERROR: Error initializing runtime service opteed_fast
881 19:19:03.134056
882 19:19:03.134703
883 19:19:03.142474 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
884 19:19:03.142976
885 19:19:03.143396 Model: Libre Computer AML-A311D-CC Alta
886 19:19:03.350950 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
887 19:19:03.374359 DRAM: 2 GiB (effective 3.8 GiB)
888 19:19:03.517343 Core: 408 devices, 31 uclasses, devicetree: separate
889 19:19:03.523219 WDT: Not starting watchdog@f0d0
890 19:19:03.555551 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
891 19:19:03.567963 Loading Environment from FAT... Card did not respond to voltage select! : -110
892 19:19:03.572887 ** Bad device specification mmc 0 **
893 19:19:03.583261 Card did not respond to voltage select! : -110
894 19:19:03.590860 ** Bad device specification mmc 0 **
895 19:19:03.591394 Couldn't find partition mmc 0
896 19:19:03.599247 Card did not respond to voltage select! : -110
897 19:19:03.604745 ** Bad device specification mmc 0 **
898 19:19:03.605263 Couldn't find partition mmc 0
899 19:19:03.609777 Error: could not access storage.
900 19:19:03.952266 Net: eth0: ethernet@ff3f0000
901 19:19:03.953126 starting USB...
902 19:19:04.204119 Bus usb@ff500000: Register 3000140 NbrPorts 3
903 19:19:04.204729 Starting the controller
904 19:19:04.210983 USB XHCI 1.10
905 19:19:05.764951 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
906 19:19:05.773248 scanning usb for storage devices... 0 Storage Device(s) found
908 19:19:05.824862 Hit any key to stop autoboot: 1
909 19:19:05.825974 end: 2.4.2 bootloader-interrupt (duration 00:00:33) [common]
910 19:19:05.826602 start: 2.4.3 bootloader-commands (timeout 00:04:27) [common]
911 19:19:05.827085 Setting prompt string to ['=>']
912 19:19:05.827576 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:27)
913 19:19:05.840732 0
914 19:19:05.841660 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
915 19:19:05.842160 Sending with 10 millisecond of delay
917 19:19:06.977168 => setenv autoload no
918 19:19:06.988034 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:26)
919 19:19:06.992966 setenv autoload no
920 19:19:06.993700 Sending with 10 millisecond of delay
922 19:19:08.790814 => setenv initrd_high 0xffffffff
923 19:19:08.801755 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:24)
924 19:19:08.802326 setenv initrd_high 0xffffffff
925 19:19:08.802810 Sending with 10 millisecond of delay
927 19:19:10.418809 => setenv fdt_high 0xffffffff
928 19:19:10.429616 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
929 19:19:10.430457 setenv fdt_high 0xffffffff
930 19:19:10.431169 Sending with 10 millisecond of delay
932 19:19:10.723056 => dhcp
933 19:19:10.733841 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
934 19:19:10.734706 dhcp
935 19:19:10.735150 Speed: 1000, full duplex
936 19:19:10.735565 BOOTP broadcast 1
937 19:19:10.746856 DHCP client bound to address 192.168.6.27 (12 ms)
938 19:19:10.747606 Sending with 10 millisecond of delay
940 19:19:12.424358 => setenv serverip 192.168.6.2
941 19:19:12.435012 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
942 19:19:12.435702 setenv serverip 192.168.6.2
943 19:19:12.436189 Sending with 10 millisecond of delay
945 19:19:16.160351 => tftpboot 0x01080000 967959/tftp-deploy-mszqrz52/kernel/uImage
946 19:19:16.171184 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:17)
947 19:19:16.172095 tftpboot 0x01080000 967959/tftp-deploy-mszqrz52/kernel/uImage
948 19:19:16.172597 Speed: 1000, full duplex
949 19:19:16.173056 Using ethernet@ff3f0000 device
950 19:19:16.173969 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
951 19:19:16.179468 Filename '967959/tftp-deploy-mszqrz52/kernel/uImage'.
952 19:19:16.183298 Load address: 0x1080000
953 19:19:19.056891 Loading: *################################################## 43.6 MiB
954 19:19:19.057524 15.2 MiB/s
955 19:19:19.057962 done
956 19:19:19.061356 Bytes transferred = 45713984 (2b98a40 hex)
957 19:19:19.062170 Sending with 10 millisecond of delay
959 19:19:23.749868 => tftpboot 0x08000000 967959/tftp-deploy-mszqrz52/ramdisk/ramdisk.cpio.gz.uboot
960 19:19:23.760799 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:09)
961 19:19:23.761777 tftpboot 0x08000000 967959/tftp-deploy-mszqrz52/ramdisk/ramdisk.cpio.gz.uboot
962 19:19:23.762287 Speed: 1000, full duplex
963 19:19:23.762749 Using ethernet@ff3f0000 device
964 19:19:23.763633 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
965 19:19:23.772274 Filename '967959/tftp-deploy-mszqrz52/ramdisk/ramdisk.cpio.gz.uboot'.
966 19:19:23.772827 Load address: 0x8000000
967 19:19:30.783784 Loading: *#################T ################################ UDP wrong checksum 00000005 0000d080
968 19:19:35.784833 T UDP wrong checksum 00000005 0000d080
969 19:19:42.611130 T UDP wrong checksum 000000ff 000069b5
970 19:19:42.660478 UDP wrong checksum 000000ff 000002a8
971 19:19:45.788281 T UDP wrong checksum 00000005 0000d080
972 19:20:03.166135 T T T UDP wrong checksum 000000ff 00005ef9
973 19:20:03.188143 UDP wrong checksum 000000ff 0000e7eb
974 19:20:05.790992 T UDP wrong checksum 00000005 0000d080
975 19:20:18.919185 T T UDP wrong checksum 000000ff 00005b81
976 19:20:18.957725 UDP wrong checksum 000000ff 0000ee73
977 19:20:20.796187
978 19:20:20.796902 Retry count exceeded; starting again
980 19:20:20.798480 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
983 19:20:20.800512 end: 2.4 uboot-commands (duration 00:01:48) [common]
985 19:20:20.802004 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
987 19:20:20.803147 end: 2 uboot-action (duration 00:01:48) [common]
989 19:20:20.804879 Cleaning after the job
990 19:20:20.805504 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/967959/tftp-deploy-mszqrz52/ramdisk
991 19:20:20.806971 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/967959/tftp-deploy-mszqrz52/kernel
992 19:20:20.855952 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/967959/tftp-deploy-mszqrz52/dtb
993 19:20:20.856904 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/967959/tftp-deploy-mszqrz52/modules
994 19:20:20.876759 start: 4.1 power-off (timeout 00:00:30) [common]
995 19:20:20.877430 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
996 19:20:20.909865 >> OK - accepted request
997 19:20:20.911994 Returned 0 in 0 seconds
998 19:20:21.012821 end: 4.1 power-off (duration 00:00:00) [common]
1000 19:20:21.013890 start: 4.2 read-feedback (timeout 00:10:00) [common]
1001 19:20:21.014633 Listened to connection for namespace 'common' for up to 1s
1002 19:20:22.014968 Finalising connection for namespace 'common'
1003 19:20:22.015728 Disconnecting from shell: Finalise
1004 19:20:22.016307 =>
1005 19:20:22.117407 end: 4.2 read-feedback (duration 00:00:01) [common]
1006 19:20:22.118097 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/967959
1007 19:20:22.399910 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/967959
1008 19:20:22.400549 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.