Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 19:38:17.091369 lava-dispatcher, installed at version: 2024.01
2 19:38:17.092201 start: 0 validate
3 19:38:17.092716 Start time: 2024-11-09 19:38:17.092685+00:00 (UTC)
4 19:38:17.093263 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 19:38:17.093789 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 19:38:17.134513 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 19:38:17.135044 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-679-gc8994e7b0f32%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 19:38:17.172018 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 19:38:17.172674 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-679-gc8994e7b0f32%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 19:38:17.206646 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 19:38:17.207187 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 19:38:17.242827 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 19:38:17.243503 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-679-gc8994e7b0f32%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 19:38:17.290245 validate duration: 0.20
16 19:38:17.291700 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:38:17.292292 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:38:17.292641 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:38:17.293242 Not decompressing ramdisk as can be used compressed.
20 19:38:17.293690 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 19:38:17.293981 saving as /var/lib/lava/dispatcher/tmp/967934/tftp-deploy-azjqtwi5/ramdisk/initrd.cpio.gz
22 19:38:17.294535 total size: 5628169 (5 MB)
23 19:38:17.333297 progress 0 % (0 MB)
24 19:38:17.340772 progress 5 % (0 MB)
25 19:38:17.348697 progress 10 % (0 MB)
26 19:38:17.355592 progress 15 % (0 MB)
27 19:38:17.363246 progress 20 % (1 MB)
28 19:38:17.367213 progress 25 % (1 MB)
29 19:38:17.371186 progress 30 % (1 MB)
30 19:38:17.375151 progress 35 % (1 MB)
31 19:38:17.378803 progress 40 % (2 MB)
32 19:38:17.382765 progress 45 % (2 MB)
33 19:38:17.386389 progress 50 % (2 MB)
34 19:38:17.390360 progress 55 % (2 MB)
35 19:38:17.394398 progress 60 % (3 MB)
36 19:38:17.398008 progress 65 % (3 MB)
37 19:38:17.402077 progress 70 % (3 MB)
38 19:38:17.405755 progress 75 % (4 MB)
39 19:38:17.410006 progress 80 % (4 MB)
40 19:38:17.414064 progress 85 % (4 MB)
41 19:38:17.418123 progress 90 % (4 MB)
42 19:38:17.422007 progress 95 % (5 MB)
43 19:38:17.425296 progress 100 % (5 MB)
44 19:38:17.425963 5 MB downloaded in 0.13 s (40.84 MB/s)
45 19:38:17.426503 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:38:17.427389 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:38:17.427681 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:38:17.427952 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:38:17.428477 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-679-gc8994e7b0f32/arm64/defconfig/gcc-12/kernel/Image
51 19:38:17.428780 saving as /var/lib/lava/dispatcher/tmp/967934/tftp-deploy-azjqtwi5/kernel/Image
52 19:38:17.429011 total size: 45713920 (43 MB)
53 19:38:17.429224 No compression specified
54 19:38:17.477801 progress 0 % (0 MB)
55 19:38:17.506175 progress 5 % (2 MB)
56 19:38:17.534671 progress 10 % (4 MB)
57 19:38:17.562889 progress 15 % (6 MB)
58 19:38:17.590874 progress 20 % (8 MB)
59 19:38:17.618212 progress 25 % (10 MB)
60 19:38:17.645823 progress 30 % (13 MB)
61 19:38:17.674272 progress 35 % (15 MB)
62 19:38:17.701865 progress 40 % (17 MB)
63 19:38:17.729013 progress 45 % (19 MB)
64 19:38:17.756817 progress 50 % (21 MB)
65 19:38:17.785473 progress 55 % (24 MB)
66 19:38:17.814011 progress 60 % (26 MB)
67 19:38:17.842000 progress 65 % (28 MB)
68 19:38:17.871060 progress 70 % (30 MB)
69 19:38:17.899925 progress 75 % (32 MB)
70 19:38:17.928104 progress 80 % (34 MB)
71 19:38:17.956698 progress 85 % (37 MB)
72 19:38:17.984572 progress 90 % (39 MB)
73 19:38:18.012300 progress 95 % (41 MB)
74 19:38:18.039542 progress 100 % (43 MB)
75 19:38:18.040109 43 MB downloaded in 0.61 s (71.34 MB/s)
76 19:38:18.040613 end: 1.2.1 http-download (duration 00:00:01) [common]
78 19:38:18.041448 end: 1.2 download-retry (duration 00:00:01) [common]
79 19:38:18.041727 start: 1.3 download-retry (timeout 00:09:59) [common]
80 19:38:18.041992 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 19:38:18.042471 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-679-gc8994e7b0f32/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 19:38:18.042744 saving as /var/lib/lava/dispatcher/tmp/967934/tftp-deploy-azjqtwi5/dtb/meson-g12b-a311d-libretech-cc.dtb
83 19:38:18.042952 total size: 54703 (0 MB)
84 19:38:18.043161 No compression specified
85 19:38:18.084283 progress 59 % (0 MB)
86 19:38:18.085170 progress 100 % (0 MB)
87 19:38:18.085754 0 MB downloaded in 0.04 s (1.22 MB/s)
88 19:38:18.086239 end: 1.3.1 http-download (duration 00:00:00) [common]
90 19:38:18.087091 end: 1.3 download-retry (duration 00:00:00) [common]
91 19:38:18.087369 start: 1.4 download-retry (timeout 00:09:59) [common]
92 19:38:18.087646 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 19:38:18.088156 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 19:38:18.088432 saving as /var/lib/lava/dispatcher/tmp/967934/tftp-deploy-azjqtwi5/nfsrootfs/full.rootfs.tar
95 19:38:18.088654 total size: 120894716 (115 MB)
96 19:38:18.088872 Using unxz to decompress xz
97 19:38:18.130015 progress 0 % (0 MB)
98 19:38:18.924411 progress 5 % (5 MB)
99 19:38:19.763658 progress 10 % (11 MB)
100 19:38:20.555819 progress 15 % (17 MB)
101 19:38:21.294020 progress 20 % (23 MB)
102 19:38:21.886827 progress 25 % (28 MB)
103 19:38:22.708853 progress 30 % (34 MB)
104 19:38:23.497860 progress 35 % (40 MB)
105 19:38:23.861266 progress 40 % (46 MB)
106 19:38:24.239326 progress 45 % (51 MB)
107 19:38:24.965677 progress 50 % (57 MB)
108 19:38:25.850906 progress 55 % (63 MB)
109 19:38:26.639697 progress 60 % (69 MB)
110 19:38:27.403604 progress 65 % (74 MB)
111 19:38:28.184714 progress 70 % (80 MB)
112 19:38:29.012760 progress 75 % (86 MB)
113 19:38:29.829133 progress 80 % (92 MB)
114 19:38:30.597778 progress 85 % (98 MB)
115 19:38:31.455716 progress 90 % (103 MB)
116 19:38:32.240813 progress 95 % (109 MB)
117 19:38:33.079551 progress 100 % (115 MB)
118 19:38:33.092218 115 MB downloaded in 15.00 s (7.68 MB/s)
119 19:38:33.093240 end: 1.4.1 http-download (duration 00:00:15) [common]
121 19:38:33.095027 end: 1.4 download-retry (duration 00:00:15) [common]
122 19:38:33.095592 start: 1.5 download-retry (timeout 00:09:44) [common]
123 19:38:33.096191 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 19:38:33.097119 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-679-gc8994e7b0f32/arm64/defconfig/gcc-12/modules.tar.xz
125 19:38:33.097634 saving as /var/lib/lava/dispatcher/tmp/967934/tftp-deploy-azjqtwi5/modules/modules.tar
126 19:38:33.098081 total size: 11612124 (11 MB)
127 19:38:33.098537 Using unxz to decompress xz
128 19:38:33.149820 progress 0 % (0 MB)
129 19:38:33.216544 progress 5 % (0 MB)
130 19:38:33.290840 progress 10 % (1 MB)
131 19:38:33.386668 progress 15 % (1 MB)
132 19:38:33.479224 progress 20 % (2 MB)
133 19:38:33.559430 progress 25 % (2 MB)
134 19:38:33.635310 progress 30 % (3 MB)
135 19:38:33.714006 progress 35 % (3 MB)
136 19:38:33.786639 progress 40 % (4 MB)
137 19:38:33.863088 progress 45 % (5 MB)
138 19:38:33.948204 progress 50 % (5 MB)
139 19:38:34.026652 progress 55 % (6 MB)
140 19:38:34.112386 progress 60 % (6 MB)
141 19:38:34.194294 progress 65 % (7 MB)
142 19:38:34.275066 progress 70 % (7 MB)
143 19:38:34.354313 progress 75 % (8 MB)
144 19:38:34.438471 progress 80 % (8 MB)
145 19:38:34.519860 progress 85 % (9 MB)
146 19:38:34.599109 progress 90 % (9 MB)
147 19:38:34.677098 progress 95 % (10 MB)
148 19:38:34.755736 progress 100 % (11 MB)
149 19:38:34.767347 11 MB downloaded in 1.67 s (6.63 MB/s)
150 19:38:34.767975 end: 1.5.1 http-download (duration 00:00:02) [common]
152 19:38:34.770019 end: 1.5 download-retry (duration 00:00:02) [common]
153 19:38:34.770675 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 19:38:34.771369 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 19:38:52.141157 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/967934/extract-nfsrootfs-k6u7nhla
156 19:38:52.141765 end: 1.6.1 extract-nfsrootfs (duration 00:00:17) [common]
157 19:38:52.142053 start: 1.6.2 lava-overlay (timeout 00:09:25) [common]
158 19:38:52.142674 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja
159 19:38:52.143111 makedir: /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin
160 19:38:52.143440 makedir: /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/tests
161 19:38:52.143758 makedir: /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/results
162 19:38:52.144120 Creating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-add-keys
163 19:38:52.144668 Creating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-add-sources
164 19:38:52.145278 Creating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-background-process-start
165 19:38:52.145908 Creating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-background-process-stop
166 19:38:52.146530 Creating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-common-functions
167 19:38:52.147271 Creating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-echo-ipv4
168 19:38:52.147893 Creating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-install-packages
169 19:38:52.148438 Creating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-installed-packages
170 19:38:52.148923 Creating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-os-build
171 19:38:52.149408 Creating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-probe-channel
172 19:38:52.149893 Creating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-probe-ip
173 19:38:52.150416 Creating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-target-ip
174 19:38:52.150903 Creating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-target-mac
175 19:38:52.151377 Creating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-target-storage
176 19:38:52.151873 Creating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-test-case
177 19:38:52.152500 Creating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-test-event
178 19:38:52.152994 Creating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-test-feedback
179 19:38:52.153471 Creating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-test-raise
180 19:38:52.153938 Creating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-test-reference
181 19:38:52.154412 Creating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-test-runner
182 19:38:52.154912 Creating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-test-set
183 19:38:52.155428 Creating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-test-shell
184 19:38:52.155917 Updating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-add-keys (debian)
185 19:38:52.156475 Updating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-add-sources (debian)
186 19:38:52.156983 Updating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-install-packages (debian)
187 19:38:52.157478 Updating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-installed-packages (debian)
188 19:38:52.157971 Updating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/bin/lava-os-build (debian)
189 19:38:52.158585 Creating /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/environment
190 19:38:52.158998 LAVA metadata
191 19:38:52.159280 - LAVA_JOB_ID=967934
192 19:38:52.159499 - LAVA_DISPATCHER_IP=192.168.6.2
193 19:38:52.159866 start: 1.6.2.1 ssh-authorize (timeout 00:09:25) [common]
194 19:38:52.160907 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
195 19:38:52.161227 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:25) [common]
196 19:38:52.161433 skipped lava-vland-overlay
197 19:38:52.161671 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
198 19:38:52.161922 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:25) [common]
199 19:38:52.162136 skipped lava-multinode-overlay
200 19:38:52.162374 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
201 19:38:52.162623 start: 1.6.2.4 test-definition (timeout 00:09:25) [common]
202 19:38:52.162870 Loading test definitions
203 19:38:52.163143 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:25) [common]
204 19:38:52.163361 Using /lava-967934 at stage 0
205 19:38:52.164480 uuid=967934_1.6.2.4.1 testdef=None
206 19:38:52.164791 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
207 19:38:52.165053 start: 1.6.2.4.2 test-overlay (timeout 00:09:25) [common]
208 19:38:52.166605 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
210 19:38:52.167389 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:25) [common]
211 19:38:52.169341 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
213 19:38:52.170165 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:25) [common]
214 19:38:52.172005 runner path: /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/0/tests/0_timesync-off test_uuid 967934_1.6.2.4.1
215 19:38:52.172566 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
217 19:38:52.173379 start: 1.6.2.4.5 git-repo-action (timeout 00:09:25) [common]
218 19:38:52.173601 Using /lava-967934 at stage 0
219 19:38:52.173952 Fetching tests from https://github.com/kernelci/test-definitions.git
220 19:38:52.174238 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/0/tests/1_kselftest-alsa'
221 19:38:55.479491 Running '/usr/bin/git checkout kernelci.org
222 19:38:55.863088 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
223 19:38:55.865662 uuid=967934_1.6.2.4.5 testdef=None
224 19:38:55.866337 end: 1.6.2.4.5 git-repo-action (duration 00:00:04) [common]
226 19:38:55.867973 start: 1.6.2.4.6 test-overlay (timeout 00:09:21) [common]
227 19:38:55.874040 end: 1.6.2.4.6 test-overlay (duration 00:00:00) [common]
229 19:38:55.875824 start: 1.6.2.4.7 test-install-overlay (timeout 00:09:21) [common]
230 19:38:55.883763 end: 1.6.2.4.7 test-install-overlay (duration 00:00:00) [common]
232 19:38:55.885678 start: 1.6.2.4.8 test-runscript-overlay (timeout 00:09:21) [common]
233 19:38:55.893387 runner path: /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/0/tests/1_kselftest-alsa test_uuid 967934_1.6.2.4.5
234 19:38:55.893972 BOARD='meson-g12b-a311d-libretech-cc'
235 19:38:55.894432 BRANCH='tip'
236 19:38:55.894872 SKIPFILE='/dev/null'
237 19:38:55.895310 SKIP_INSTALL='True'
238 19:38:55.895745 TESTPROG_URL='http://storage.kernelci.org/tip/master/v6.12-rc6-679-gc8994e7b0f32/arm64/defconfig/gcc-12/kselftest.tar.xz'
239 19:38:55.896224 TST_CASENAME=''
240 19:38:55.896665 TST_CMDFILES='alsa'
241 19:38:55.897771 end: 1.6.2.4.8 test-runscript-overlay (duration 00:00:00) [common]
243 19:38:55.899475 Creating lava-test-runner.conf files
244 19:38:55.899933 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/967934/lava-overlay-dgnez5ja/lava-967934/0 for stage 0
245 19:38:55.900750 - 0_timesync-off
246 19:38:55.901278 - 1_kselftest-alsa
247 19:38:55.901997 end: 1.6.2.4 test-definition (duration 00:00:04) [common]
248 19:38:55.902603 start: 1.6.2.5 compress-overlay (timeout 00:09:21) [common]
249 19:39:19.320873 end: 1.6.2.5 compress-overlay (duration 00:00:23) [common]
250 19:39:19.321329 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:08:58) [common]
251 19:39:19.321627 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
252 19:39:19.321937 end: 1.6.2 lava-overlay (duration 00:00:27) [common]
253 19:39:19.322229 start: 1.6.3 extract-overlay-ramdisk (timeout 00:08:58) [common]
254 19:39:19.937487 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
255 19:39:19.937959 start: 1.6.4 extract-modules (timeout 00:08:57) [common]
256 19:39:19.938230 extracting modules file /var/lib/lava/dispatcher/tmp/967934/tftp-deploy-azjqtwi5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/967934/extract-nfsrootfs-k6u7nhla
257 19:39:21.306260 extracting modules file /var/lib/lava/dispatcher/tmp/967934/tftp-deploy-azjqtwi5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/967934/extract-overlay-ramdisk-o0ef3i24/ramdisk
258 19:39:22.749916 end: 1.6.4 extract-modules (duration 00:00:03) [common]
259 19:39:22.750396 start: 1.6.5 apply-overlay-tftp (timeout 00:08:55) [common]
260 19:39:22.750691 [common] Applying overlay to NFS
261 19:39:22.750922 [common] Applying overlay /var/lib/lava/dispatcher/tmp/967934/compress-overlay-h_pll7te/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/967934/extract-nfsrootfs-k6u7nhla
262 19:39:25.490996 end: 1.6.5 apply-overlay-tftp (duration 00:00:03) [common]
263 19:39:25.491476 start: 1.6.6 prepare-kernel (timeout 00:08:52) [common]
264 19:39:25.491781 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:08:52) [common]
265 19:39:25.492072 Converting downloaded kernel to a uImage
266 19:39:25.492406 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/967934/tftp-deploy-azjqtwi5/kernel/Image /var/lib/lava/dispatcher/tmp/967934/tftp-deploy-azjqtwi5/kernel/uImage
267 19:39:25.969207 output: Image Name:
268 19:39:25.969627 output: Created: Sat Nov 9 19:39:25 2024
269 19:39:25.969839 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
270 19:39:25.970044 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
271 19:39:25.970246 output: Load Address: 01080000
272 19:39:25.970445 output: Entry Point: 01080000
273 19:39:25.970641 output:
274 19:39:25.970972 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
275 19:39:25.971240 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
276 19:39:25.971507 start: 1.6.7 configure-preseed-file (timeout 00:08:51) [common]
277 19:39:25.971758 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
278 19:39:25.972051 start: 1.6.8 compress-ramdisk (timeout 00:08:51) [common]
279 19:39:25.972328 Building ramdisk /var/lib/lava/dispatcher/tmp/967934/extract-overlay-ramdisk-o0ef3i24/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/967934/extract-overlay-ramdisk-o0ef3i24/ramdisk
280 19:39:28.224327 >> 166827 blocks
281 19:39:36.139087 Adding RAMdisk u-boot header.
282 19:39:36.139525 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/967934/extract-overlay-ramdisk-o0ef3i24/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/967934/extract-overlay-ramdisk-o0ef3i24/ramdisk.cpio.gz.uboot
283 19:39:36.382882 output: Image Name:
284 19:39:36.383315 output: Created: Sat Nov 9 19:39:36 2024
285 19:39:36.383746 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
286 19:39:36.384223 output: Data Size: 23436503 Bytes = 22887.21 KiB = 22.35 MiB
287 19:39:36.384640 output: Load Address: 00000000
288 19:39:36.385043 output: Entry Point: 00000000
289 19:39:36.385445 output:
290 19:39:36.386586 rename /var/lib/lava/dispatcher/tmp/967934/extract-overlay-ramdisk-o0ef3i24/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/967934/tftp-deploy-azjqtwi5/ramdisk/ramdisk.cpio.gz.uboot
291 19:39:36.387308 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
292 19:39:36.387862 end: 1.6 prepare-tftp-overlay (duration 00:01:02) [common]
293 19:39:36.388492 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:41) [common]
294 19:39:36.388949 No LXC device requested
295 19:39:36.389454 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
296 19:39:36.389968 start: 1.8 deploy-device-env (timeout 00:08:41) [common]
297 19:39:36.390466 end: 1.8 deploy-device-env (duration 00:00:00) [common]
298 19:39:36.390879 Checking files for TFTP limit of 4294967296 bytes.
299 19:39:36.393568 end: 1 tftp-deploy (duration 00:01:19) [common]
300 19:39:36.394140 start: 2 uboot-action (timeout 00:05:00) [common]
301 19:39:36.394671 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
302 19:39:36.395170 end: 2.1 uboot-from-media (duration 00:00:00) [common]
303 19:39:36.395677 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
304 19:39:36.396211 Using kernel file from prepare-kernel: 967934/tftp-deploy-azjqtwi5/kernel/uImage
305 19:39:36.396849 substitutions:
306 19:39:36.397262 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
307 19:39:36.397666 - {DTB_ADDR}: 0x01070000
308 19:39:36.398067 - {DTB}: 967934/tftp-deploy-azjqtwi5/dtb/meson-g12b-a311d-libretech-cc.dtb
309 19:39:36.398470 - {INITRD}: 967934/tftp-deploy-azjqtwi5/ramdisk/ramdisk.cpio.gz.uboot
310 19:39:36.398867 - {KERNEL_ADDR}: 0x01080000
311 19:39:36.399301 - {KERNEL}: 967934/tftp-deploy-azjqtwi5/kernel/uImage
312 19:39:36.399724 - {LAVA_MAC}: None
313 19:39:36.400193 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/967934/extract-nfsrootfs-k6u7nhla
314 19:39:36.400613 - {NFS_SERVER_IP}: 192.168.6.2
315 19:39:36.401024 - {PRESEED_CONFIG}: None
316 19:39:36.401434 - {PRESEED_LOCAL}: None
317 19:39:36.401839 - {RAMDISK_ADDR}: 0x08000000
318 19:39:36.402236 - {RAMDISK}: 967934/tftp-deploy-azjqtwi5/ramdisk/ramdisk.cpio.gz.uboot
319 19:39:36.402624 - {ROOT_PART}: None
320 19:39:36.403010 - {ROOT}: None
321 19:39:36.403393 - {SERVER_IP}: 192.168.6.2
322 19:39:36.403774 - {TEE_ADDR}: 0x83000000
323 19:39:36.404198 - {TEE}: None
324 19:39:36.404583 Parsed boot commands:
325 19:39:36.404955 - setenv autoload no
326 19:39:36.405335 - setenv initrd_high 0xffffffff
327 19:39:36.405713 - setenv fdt_high 0xffffffff
328 19:39:36.406091 - dhcp
329 19:39:36.406473 - setenv serverip 192.168.6.2
330 19:39:36.406855 - tftpboot 0x01080000 967934/tftp-deploy-azjqtwi5/kernel/uImage
331 19:39:36.407238 - tftpboot 0x08000000 967934/tftp-deploy-azjqtwi5/ramdisk/ramdisk.cpio.gz.uboot
332 19:39:36.407622 - tftpboot 0x01070000 967934/tftp-deploy-azjqtwi5/dtb/meson-g12b-a311d-libretech-cc.dtb
333 19:39:36.408055 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/967934/extract-nfsrootfs-k6u7nhla,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
334 19:39:36.408460 - bootm 0x01080000 0x08000000 0x01070000
335 19:39:36.408964 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
337 19:39:36.410447 start: 2.3 connect-device (timeout 00:05:00) [common]
338 19:39:36.410860 [common] connect-device Connecting to device using 'telnet conserv1 3007'
339 19:39:36.426747 Setting prompt string to ['lava-test: # ']
340 19:39:36.428640 end: 2.3 connect-device (duration 00:00:00) [common]
341 19:39:36.429302 start: 2.4 uboot-commands (timeout 00:05:00) [common]
342 19:39:36.429926 start: 2.4.1 reset-device (timeout 00:05:00) [common]
343 19:39:36.430470 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
344 19:39:36.431648 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
345 19:39:36.468288 >> OK - accepted request
346 19:39:36.470782 Returned 0 in 0 seconds
347 19:39:36.571927 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
349 19:39:36.573683 end: 2.4.1 reset-device (duration 00:00:00) [common]
350 19:39:36.574244 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
351 19:39:36.574762 Setting prompt string to ['Hit any key to stop autoboot']
352 19:39:36.575232 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
353 19:39:36.576862 Trying 192.168.56.21...
354 19:39:36.577337 Connected to conserv1.
355 19:39:36.577739 Escape character is '^]'.
356 19:39:36.578146
357 19:39:36.578554 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
358 19:39:36.578999
359 19:39:47.859322 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
360 19:39:47.859963 bl2_stage_init 0x01
361 19:39:47.860457 bl2_stage_init 0x81
362 19:39:47.864774 hw id: 0x0000 - pwm id 0x01
363 19:39:47.865229 bl2_stage_init 0xc1
364 19:39:47.865683 bl2_stage_init 0x02
365 19:39:47.866129
366 19:39:47.870350 L0:00000000
367 19:39:47.870810 L1:20000703
368 19:39:47.871218 L2:00008067
369 19:39:47.871623 L3:14000000
370 19:39:47.873239 B2:00402000
371 19:39:47.873677 B1:e0f83180
372 19:39:47.874066
373 19:39:47.874453 TE: 58159
374 19:39:47.874839
375 19:39:47.884357 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
376 19:39:47.884802
377 19:39:47.885190 Board ID = 1
378 19:39:47.885572 Set A53 clk to 24M
379 19:39:47.885952 Set A73 clk to 24M
380 19:39:47.889973 Set clk81 to 24M
381 19:39:47.890392 A53 clk: 1200 MHz
382 19:39:47.890782 A73 clk: 1200 MHz
383 19:39:47.895551 CLK81: 166.6M
384 19:39:47.895965 smccc: 00012ab5
385 19:39:47.901217 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
386 19:39:47.901643 board id: 1
387 19:39:47.906772 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
388 19:39:47.920436 fw parse done
389 19:39:47.926382 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
390 19:39:47.969144 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
391 19:39:47.980093 PIEI prepare done
392 19:39:47.980553 fastboot data load
393 19:39:47.980954 fastboot data verify
394 19:39:47.985642 verify result: 266
395 19:39:47.991215 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
396 19:39:47.991658 LPDDR4 probe
397 19:39:47.992122 ddr clk to 1584MHz
398 19:39:47.999241 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
399 19:39:48.036579
400 19:39:48.037206 dmc_version 0001
401 19:39:48.043130 Check phy result
402 19:39:48.049041 INFO : End of CA training
403 19:39:48.049521 INFO : End of initialization
404 19:39:48.054607 INFO : Training has run successfully!
405 19:39:48.055052 Check phy result
406 19:39:48.060253 INFO : End of initialization
407 19:39:48.060704 INFO : End of read enable training
408 19:39:48.065749 INFO : End of fine write leveling
409 19:39:48.071409 INFO : End of Write leveling coarse delay
410 19:39:48.071844 INFO : Training has run successfully!
411 19:39:48.072287 Check phy result
412 19:39:48.076974 INFO : End of initialization
413 19:39:48.077415 INFO : End of read dq deskew training
414 19:39:48.082587 INFO : End of MPR read delay center optimization
415 19:39:48.088275 INFO : End of write delay center optimization
416 19:39:48.093796 INFO : End of read delay center optimization
417 19:39:48.094241 INFO : End of max read latency training
418 19:39:48.099386 INFO : Training has run successfully!
419 19:39:48.099820 1D training succeed
420 19:39:48.108575 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
421 19:39:48.156280 Check phy result
422 19:39:48.156794 INFO : End of initialization
423 19:39:48.178754 INFO : End of 2D read delay Voltage center optimization
424 19:39:48.198966 INFO : End of 2D read delay Voltage center optimization
425 19:39:48.251115 INFO : End of 2D write delay Voltage center optimization
426 19:39:48.300438 INFO : End of 2D write delay Voltage center optimization
427 19:39:48.305957 INFO : Training has run successfully!
428 19:39:48.306396
429 19:39:48.306811 channel==0
430 19:39:48.311541 RxClkDly_Margin_A0==88 ps 9
431 19:39:48.311967 TxDqDly_Margin_A0==98 ps 10
432 19:39:48.317155 RxClkDly_Margin_A1==88 ps 9
433 19:39:48.317605 TxDqDly_Margin_A1==98 ps 10
434 19:39:48.318009 TrainedVREFDQ_A0==74
435 19:39:48.322826 TrainedVREFDQ_A1==74
436 19:39:48.323263 VrefDac_Margin_A0==25
437 19:39:48.323666 DeviceVref_Margin_A0==40
438 19:39:48.328317 VrefDac_Margin_A1==25
439 19:39:48.328748 DeviceVref_Margin_A1==40
440 19:39:48.329146
441 19:39:48.329543
442 19:39:48.333914 channel==1
443 19:39:48.334345 RxClkDly_Margin_A0==98 ps 10
444 19:39:48.334740 TxDqDly_Margin_A0==88 ps 9
445 19:39:48.339533 RxClkDly_Margin_A1==88 ps 9
446 19:39:48.339961 TxDqDly_Margin_A1==88 ps 9
447 19:39:48.345157 TrainedVREFDQ_A0==76
448 19:39:48.345646 TrainedVREFDQ_A1==77
449 19:39:48.346056 VrefDac_Margin_A0==22
450 19:39:48.350704 DeviceVref_Margin_A0==38
451 19:39:48.351137 VrefDac_Margin_A1==24
452 19:39:48.356300 DeviceVref_Margin_A1==37
453 19:39:48.356727
454 19:39:48.357135 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
455 19:39:48.357535
456 19:39:48.389957 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000017 00000017 00000015 00000017 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
457 19:39:48.390495 2D training succeed
458 19:39:48.395559 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
459 19:39:48.401219 auto size-- 65535DDR cs0 size: 2048MB
460 19:39:48.401734 DDR cs1 size: 2048MB
461 19:39:48.406836 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
462 19:39:48.407292 cs0 DataBus test pass
463 19:39:48.412364 cs1 DataBus test pass
464 19:39:48.412797 cs0 AddrBus test pass
465 19:39:48.413201 cs1 AddrBus test pass
466 19:39:48.413595
467 19:39:48.417953 100bdlr_step_size ps== 420
468 19:39:48.418403 result report
469 19:39:48.423557 boot times 0Enable ddr reg access
470 19:39:48.428810 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
471 19:39:48.442329 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
472 19:39:49.016130 0.0;M3 CHK:0;cm4_sp_mode 0
473 19:39:49.016830 MVN_1=0x00000000
474 19:39:49.021599 MVN_2=0x00000000
475 19:39:49.027438 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
476 19:39:49.027943 OPS=0x10
477 19:39:49.028426 ring efuse init
478 19:39:49.028868 chipver efuse init
479 19:39:49.035508 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
480 19:39:49.036014 [0.018960 Inits done]
481 19:39:49.043042 secure task start!
482 19:39:49.043503 high task start!
483 19:39:49.043914 low task start!
484 19:39:49.044349 run into bl31
485 19:39:49.049713 NOTICE: BL31: v1.3(release):4fc40b1
486 19:39:49.057516 NOTICE: BL31: Built : 15:58:17, May 22 2019
487 19:39:49.057989 NOTICE: BL31: G12A normal boot!
488 19:39:49.082943 NOTICE: BL31: BL33 decompress pass
489 19:39:49.087636 ERROR: Error initializing runtime service opteed_fast
490 19:39:50.321492
491 19:39:50.322120
492 19:39:50.329883 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
493 19:39:50.330346
494 19:39:50.330763 Model: Libre Computer AML-A311D-CC Alta
495 19:39:50.538498 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
496 19:39:50.561959 DRAM: 2 GiB (effective 3.8 GiB)
497 19:39:50.705001 Core: 408 devices, 31 uclasses, devicetree: separate
498 19:39:50.710888 WDT: Not starting watchdog@f0d0
499 19:39:50.743015 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
500 19:39:50.755411 Loading Environment from FAT... Card did not respond to voltage select! : -110
501 19:39:50.760522 ** Bad device specification mmc 0 **
502 19:39:50.770885 Card did not respond to voltage select! : -110
503 19:39:50.778489 ** Bad device specification mmc 0 **
504 19:39:50.778963 Couldn't find partition mmc 0
505 19:39:50.786905 Card did not respond to voltage select! : -110
506 19:39:50.792310 ** Bad device specification mmc 0 **
507 19:39:50.792777 Couldn't find partition mmc 0
508 19:39:50.797472 Error: could not access storage.
509 19:39:52.060146 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
510 19:39:52.060802 bl2_stage_init 0x01
511 19:39:52.061252 bl2_stage_init 0x81
512 19:39:52.065502 hw id: 0x0000 - pwm id 0x01
513 19:39:52.066000 bl2_stage_init 0xc1
514 19:39:52.066420 bl2_stage_init 0x02
515 19:39:52.066824
516 19:39:52.071163 L0:00000000
517 19:39:52.071645 L1:20000703
518 19:39:52.072088 L2:00008067
519 19:39:52.072495 L3:14000000
520 19:39:52.076847 B2:00402000
521 19:39:52.077335 B1:e0f83180
522 19:39:52.077771
523 19:39:52.078188 TE: 58124
524 19:39:52.078611
525 19:39:52.082299 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
526 19:39:52.082821
527 19:39:52.083253 Board ID = 1
528 19:39:52.088051 Set A53 clk to 24M
529 19:39:52.088552 Set A73 clk to 24M
530 19:39:52.088991 Set clk81 to 24M
531 19:39:52.093703 A53 clk: 1200 MHz
532 19:39:52.094210 A73 clk: 1200 MHz
533 19:39:52.094638 CLK81: 166.6M
534 19:39:52.095078 smccc: 00012a92
535 19:39:52.099195 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
536 19:39:52.104698 board id: 1
537 19:39:52.109767 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
538 19:39:52.121050 fw parse done
539 19:39:52.126070 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
540 19:39:52.168691 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
541 19:39:52.180518 PIEI prepare done
542 19:39:52.181043 fastboot data load
543 19:39:52.181461 fastboot data verify
544 19:39:52.186157 verify result: 266
545 19:39:52.191775 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
546 19:39:52.192324 LPDDR4 probe
547 19:39:52.192780 ddr clk to 1584MHz
548 19:39:52.199765 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
549 19:39:52.237092
550 19:39:52.237679 dmc_version 0001
551 19:39:52.243678 Check phy result
552 19:39:52.249516 INFO : End of CA training
553 19:39:52.250027 INFO : End of initialization
554 19:39:52.255157 INFO : Training has run successfully!
555 19:39:52.255651 Check phy result
556 19:39:52.260779 INFO : End of initialization
557 19:39:52.261278 INFO : End of read enable training
558 19:39:52.266316 INFO : End of fine write leveling
559 19:39:52.271965 INFO : End of Write leveling coarse delay
560 19:39:52.272511 INFO : Training has run successfully!
561 19:39:52.272923 Check phy result
562 19:39:52.277529 INFO : End of initialization
563 19:39:52.277989 INFO : End of read dq deskew training
564 19:39:52.283117 INFO : End of MPR read delay center optimization
565 19:39:52.288786 INFO : End of write delay center optimization
566 19:39:52.294326 INFO : End of read delay center optimization
567 19:39:52.294795 INFO : End of max read latency training
568 19:39:52.300031 INFO : Training has run successfully!
569 19:39:52.300563 1D training succeed
570 19:39:52.309071 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
571 19:39:52.356775 Check phy result
572 19:39:52.357360 INFO : End of initialization
573 19:39:52.378379 INFO : End of 2D read delay Voltage center optimization
574 19:39:52.398488 INFO : End of 2D read delay Voltage center optimization
575 19:39:52.450393 INFO : End of 2D write delay Voltage center optimization
576 19:39:52.499635 INFO : End of 2D write delay Voltage center optimization
577 19:39:52.505156 INFO : Training has run successfully!
578 19:39:52.505703
579 19:39:52.506132 channel==0
580 19:39:52.510790 RxClkDly_Margin_A0==88 ps 9
581 19:39:52.511317 TxDqDly_Margin_A0==98 ps 10
582 19:39:52.516419 RxClkDly_Margin_A1==88 ps 9
583 19:39:52.516961 TxDqDly_Margin_A1==88 ps 9
584 19:39:52.517399 TrainedVREFDQ_A0==74
585 19:39:52.522002 TrainedVREFDQ_A1==74
586 19:39:52.522535 VrefDac_Margin_A0==25
587 19:39:52.522942 DeviceVref_Margin_A0==40
588 19:39:52.527806 VrefDac_Margin_A1==25
589 19:39:52.528422 DeviceVref_Margin_A1==40
590 19:39:52.528862
591 19:39:52.529287
592 19:39:52.529722 channel==1
593 19:39:52.533168 RxClkDly_Margin_A0==98 ps 10
594 19:39:52.533690 TxDqDly_Margin_A0==98 ps 10
595 19:39:52.538767 RxClkDly_Margin_A1==98 ps 10
596 19:39:52.539320 TxDqDly_Margin_A1==88 ps 9
597 19:39:52.544396 TrainedVREFDQ_A0==77
598 19:39:52.544934 TrainedVREFDQ_A1==77
599 19:39:52.545349 VrefDac_Margin_A0==22
600 19:39:52.549970 DeviceVref_Margin_A0==37
601 19:39:52.550480 VrefDac_Margin_A1==22
602 19:39:52.555539 DeviceVref_Margin_A1==37
603 19:39:52.556054
604 19:39:52.556494 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
605 19:39:52.556933
606 19:39:52.589028 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000018 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 0000005f
607 19:39:52.589443 2D training succeed
608 19:39:52.594609 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
609 19:39:52.600217 auto size-- 65535DDR cs0 size: 2048MB
610 19:39:52.600485 DDR cs1 size: 2048MB
611 19:39:52.605813 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
612 19:39:52.606075 cs0 DataBus test pass
613 19:39:52.611428 cs1 DataBus test pass
614 19:39:52.611905 cs0 AddrBus test pass
615 19:39:52.612363 cs1 AddrBus test pass
616 19:39:52.612785
617 19:39:52.617026 100bdlr_step_size ps== 420
618 19:39:52.617594 result report
619 19:39:52.622758 boot times 0Enable ddr reg access
620 19:39:52.628064 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
621 19:39:52.641431 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
622 19:39:53.213651 0.0;M3 CHK:0;cm4_sp_mode 0
623 19:39:53.214668 MVN_1=0x00000000
624 19:39:53.219102 MVN_2=0x00000000
625 19:39:53.224908 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
626 19:39:53.225781 OPS=0x10
627 19:39:53.226686 ring efuse init
628 19:39:53.227477 chipver efuse init
629 19:39:53.230390 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
630 19:39:53.236034 [0.018961 Inits done]
631 19:39:53.236772 secure task start!
632 19:39:53.237456 high task start!
633 19:39:53.240526 low task start!
634 19:39:53.241276 run into bl31
635 19:39:53.247142 NOTICE: BL31: v1.3(release):4fc40b1
636 19:39:53.255052 NOTICE: BL31: Built : 15:58:17, May 22 2019
637 19:39:53.255865 NOTICE: BL31: G12A normal boot!
638 19:39:53.280321 NOTICE: BL31: BL33 decompress pass
639 19:39:53.286106 ERROR: Error initializing runtime service opteed_fast
640 19:39:54.518921
641 19:39:54.519355
642 19:39:54.527322 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
643 19:39:54.527765
644 19:39:54.528220 Model: Libre Computer AML-A311D-CC Alta
645 19:39:54.735800 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
646 19:39:54.759179 DRAM: 2 GiB (effective 3.8 GiB)
647 19:39:54.902203 Core: 408 devices, 31 uclasses, devicetree: separate
648 19:39:54.907934 WDT: Not starting watchdog@f0d0
649 19:39:54.940337 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
650 19:39:54.952656 Loading Environment from FAT... Card did not respond to voltage select! : -110
651 19:39:54.957634 ** Bad device specification mmc 0 **
652 19:39:54.968111 Card did not respond to voltage select! : -110
653 19:39:54.975642 ** Bad device specification mmc 0 **
654 19:39:54.976444 Couldn't find partition mmc 0
655 19:39:54.983951 Card did not respond to voltage select! : -110
656 19:39:54.989540 ** Bad device specification mmc 0 **
657 19:39:54.990298 Couldn't find partition mmc 0
658 19:39:54.994509 Error: could not access storage.
659 19:39:55.337013 Net: eth0: ethernet@ff3f0000
660 19:39:55.337604 starting USB...
661 19:39:55.588883 Bus usb@ff500000: Register 3000140 NbrPorts 3
662 19:39:55.589304 Starting the controller
663 19:39:55.595728 USB XHCI 1.10
664 19:39:57.309873 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
665 19:39:57.310544 bl2_stage_init 0x01
666 19:39:57.311045 bl2_stage_init 0x81
667 19:39:57.315316 hw id: 0x0000 - pwm id 0x01
668 19:39:57.315831 bl2_stage_init 0xc1
669 19:39:57.316354 bl2_stage_init 0x02
670 19:39:57.316818
671 19:39:57.320982 L0:00000000
672 19:39:57.321311 L1:20000703
673 19:39:57.321534 L2:00008067
674 19:39:57.321742 L3:14000000
675 19:39:57.323976 B2:00402000
676 19:39:57.324296 B1:e0f83180
677 19:39:57.324515
678 19:39:57.324726 TE: 58159
679 19:39:57.324933
680 19:39:57.335104 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
681 19:39:57.335433
682 19:39:57.335653 Board ID = 1
683 19:39:57.335860 Set A53 clk to 24M
684 19:39:57.336100 Set A73 clk to 24M
685 19:39:57.340731 Set clk81 to 24M
686 19:39:57.341033 A53 clk: 1200 MHz
687 19:39:57.341251 A73 clk: 1200 MHz
688 19:39:57.344270 CLK81: 166.6M
689 19:39:57.344577 smccc: 00012ab5
690 19:39:57.349724 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
691 19:39:57.355327 board id: 1
692 19:39:57.361254 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
693 19:39:57.371048 fw parse done
694 19:39:57.377030 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
695 19:39:57.419693 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
696 19:39:57.430591 PIEI prepare done
697 19:39:57.430921 fastboot data load
698 19:39:57.431154 fastboot data verify
699 19:39:57.436186 verify result: 266
700 19:39:57.441765 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
701 19:39:57.442094 LPDDR4 probe
702 19:39:57.442324 ddr clk to 1584MHz
703 19:39:57.449800 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
704 19:39:57.487119
705 19:39:57.487513 dmc_version 0001
706 19:39:57.493725 Check phy result
707 19:39:57.499638 INFO : End of CA training
708 19:39:57.500019 INFO : End of initialization
709 19:39:57.505210 INFO : Training has run successfully!
710 19:39:57.505549 Check phy result
711 19:39:57.510808 INFO : End of initialization
712 19:39:57.511266 INFO : End of read enable training
713 19:39:57.516402 INFO : End of fine write leveling
714 19:39:57.521985 INFO : End of Write leveling coarse delay
715 19:39:57.522312 INFO : Training has run successfully!
716 19:39:57.522529 Check phy result
717 19:39:57.527624 INFO : End of initialization
718 19:39:57.528123 INFO : End of read dq deskew training
719 19:39:57.533242 INFO : End of MPR read delay center optimization
720 19:39:57.538800 INFO : End of write delay center optimization
721 19:39:57.544410 INFO : End of read delay center optimization
722 19:39:57.544765 INFO : End of max read latency training
723 19:39:57.550111 INFO : Training has run successfully!
724 19:39:57.550671 1D training succeed
725 19:39:57.558640 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
726 19:39:57.606730 Check phy result
727 19:39:57.607117 INFO : End of initialization
728 19:39:57.627415 INFO : End of 2D read delay Voltage center optimization
729 19:39:57.648542 INFO : End of 2D read delay Voltage center optimization
730 19:39:57.700399 INFO : End of 2D write delay Voltage center optimization
731 19:39:57.749700 INFO : End of 2D write delay Voltage center optimization
732 19:39:57.755150 INFO : Training has run successfully!
733 19:39:57.755469
734 19:39:57.755694 channel==0
735 19:39:57.760796 RxClkDly_Margin_A0==88 ps 9
736 19:39:57.761139 TxDqDly_Margin_A0==98 ps 10
737 19:39:57.766362 RxClkDly_Margin_A1==88 ps 9
738 19:39:57.766679 TxDqDly_Margin_A1==98 ps 10
739 19:39:57.766902 TrainedVREFDQ_A0==74
740 19:39:57.771967 TrainedVREFDQ_A1==74
741 19:39:57.772328 VrefDac_Margin_A0==25
742 19:39:57.772553 DeviceVref_Margin_A0==40
743 19:39:57.777600 VrefDac_Margin_A1==25
744 19:39:57.777916 DeviceVref_Margin_A1==40
745 19:39:57.778132
746 19:39:57.778343
747 19:39:57.783136 channel==1
748 19:39:57.783451 RxClkDly_Margin_A0==98 ps 10
749 19:39:57.783670 TxDqDly_Margin_A0==88 ps 9
750 19:39:57.788782 RxClkDly_Margin_A1==88 ps 9
751 19:39:57.789099 TxDqDly_Margin_A1==88 ps 9
752 19:39:57.794385 TrainedVREFDQ_A0==76
753 19:39:57.794710 TrainedVREFDQ_A1==77
754 19:39:57.794943 VrefDac_Margin_A0==22
755 19:39:57.799973 DeviceVref_Margin_A0==38
756 19:39:57.800376 VrefDac_Margin_A1==24
757 19:39:57.805848 DeviceVref_Margin_A1==37
758 19:39:57.806171
759 19:39:57.806404 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
760 19:39:57.806719
761 19:39:57.839249 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000018 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
762 19:39:57.839930 2D training succeed
763 19:39:57.844713 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
764 19:39:57.850404 auto size-- 65535DDR cs0 size: 2048MB
765 19:39:57.850942 DDR cs1 size: 2048MB
766 19:39:57.855883 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
767 19:39:57.856467 cs0 DataBus test pass
768 19:39:57.861586 cs1 DataBus test pass
769 19:39:57.862065 cs0 AddrBus test pass
770 19:39:57.862502 cs1 AddrBus test pass
771 19:39:57.862939
772 19:39:57.867101 100bdlr_step_size ps== 420
773 19:39:57.867601 result report
774 19:39:57.872710 boot times 0Enable ddr reg access
775 19:39:57.877973 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
776 19:39:57.891366 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
777 19:39:58.463395 0.0;M3 CHK:0;cm4_sp_mode 0
778 19:39:58.463821 MVN_1=0x00000000
779 19:39:58.469040 MVN_2=0x00000000
780 19:39:58.474803 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
781 19:39:58.475373 OPS=0x10
782 19:39:58.475831 ring efuse init
783 19:39:58.476311 chipver efuse init
784 19:39:58.480326 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
785 19:39:58.486035 [0.018961 Inits done]
786 19:39:58.486513 secure task start!
787 19:39:58.486956 high task start!
788 19:39:58.490565 low task start!
789 19:39:58.491057 run into bl31
790 19:39:58.497279 NOTICE: BL31: v1.3(release):4fc40b1
791 19:39:58.504926 NOTICE: BL31: Built : 15:58:17, May 22 2019
792 19:39:58.505453 NOTICE: BL31: G12A normal boot!
793 19:39:58.530354 NOTICE: BL31: BL33 decompress pass
794 19:39:58.535999 ERROR: Error initializing runtime service opteed_fast
795 19:39:59.768922
796 19:39:59.769594
797 19:39:59.777274 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
798 19:39:59.777792
799 19:39:59.778253 Model: Libre Computer AML-A311D-CC Alta
800 19:39:59.985696 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
801 19:40:00.009094 DRAM: 2 GiB (effective 3.8 GiB)
802 19:40:00.152130 Core: 408 devices, 31 uclasses, devicetree: separate
803 19:40:00.157898 WDT: Not starting watchdog@f0d0
804 19:40:00.190192 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
805 19:40:00.202638 Loading Environment from FAT... Card did not respond to voltage select! : -110
806 19:40:00.207596 ** Bad device specification mmc 0 **
807 19:40:00.217962 Card did not respond to voltage select! : -110
808 19:40:00.225614 ** Bad device specification mmc 0 **
809 19:40:00.226114 Couldn't find partition mmc 0
810 19:40:00.233926 Card did not respond to voltage select! : -110
811 19:40:00.239471 ** Bad device specification mmc 0 **
812 19:40:00.239961 Couldn't find partition mmc 0
813 19:40:00.244511 Error: could not access storage.
814 19:40:00.587103 Net: eth0: ethernet@ff3f0000
815 19:40:00.587520 starting USB...
816 19:40:00.838997 Bus usb@ff500000: Register 3000140 NbrPorts 3
817 19:40:00.839655 Starting the controller
818 19:40:00.844975 USB XHCI 1.10
819 19:40:03.011488 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
820 19:40:03.011914 bl2_stage_init 0x01
821 19:40:03.012155 bl2_stage_init 0x81
822 19:40:03.016942 hw id: 0x0000 - pwm id 0x01
823 19:40:03.017260 bl2_stage_init 0xc1
824 19:40:03.017473 bl2_stage_init 0x02
825 19:40:03.017672
826 19:40:03.022478 L0:00000000
827 19:40:03.022773 L1:20000703
828 19:40:03.022994 L2:00008067
829 19:40:03.023215 L3:14000000
830 19:40:03.028106 B2:00402000
831 19:40:03.028513 B1:e0f83180
832 19:40:03.028816
833 19:40:03.029130 TE: 58124
834 19:40:03.029361
835 19:40:03.033697 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
836 19:40:03.033982
837 19:40:03.034202 Board ID = 1
838 19:40:03.039340 Set A53 clk to 24M
839 19:40:03.039629 Set A73 clk to 24M
840 19:40:03.039839 Set clk81 to 24M
841 19:40:03.045041 A53 clk: 1200 MHz
842 19:40:03.045316 A73 clk: 1200 MHz
843 19:40:03.045536 CLK81: 166.6M
844 19:40:03.045752 smccc: 00012a92
845 19:40:03.050429 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
846 19:40:03.056011 board id: 1
847 19:40:03.061875 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
848 19:40:03.072689 fw parse done
849 19:40:03.078630 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
850 19:40:03.121306 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
851 19:40:03.132179 PIEI prepare done
852 19:40:03.132712 fastboot data load
853 19:40:03.133175 fastboot data verify
854 19:40:03.137789 verify result: 266
855 19:40:03.143383 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
856 19:40:03.143892 LPDDR4 probe
857 19:40:03.144443 ddr clk to 1584MHz
858 19:40:03.151323 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
859 19:40:03.187711
860 19:40:03.188305 dmc_version 0001
861 19:40:03.194451 Check phy result
862 19:40:03.201356 INFO : End of CA training
863 19:40:03.201939 INFO : End of initialization
864 19:40:03.206764 INFO : Training has run successfully!
865 19:40:03.207275 Check phy result
866 19:40:03.212402 INFO : End of initialization
867 19:40:03.212975 INFO : End of read enable training
868 19:40:03.215683 INFO : End of fine write leveling
869 19:40:03.221132 INFO : End of Write leveling coarse delay
870 19:40:03.226751 INFO : Training has run successfully!
871 19:40:03.227253 Check phy result
872 19:40:03.227707 INFO : End of initialization
873 19:40:03.232404 INFO : End of read dq deskew training
874 19:40:03.235714 INFO : End of MPR read delay center optimization
875 19:40:03.241395 INFO : End of write delay center optimization
876 19:40:03.246863 INFO : End of read delay center optimization
877 19:40:03.247414 INFO : End of max read latency training
878 19:40:03.252512 INFO : Training has run successfully!
879 19:40:03.253052 1D training succeed
880 19:40:03.259851 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
881 19:40:03.307390 Check phy result
882 19:40:03.307936 INFO : End of initialization
883 19:40:03.329175 INFO : End of 2D read delay Voltage center optimization
884 19:40:03.349437 INFO : End of 2D read delay Voltage center optimization
885 19:40:03.402532 INFO : End of 2D write delay Voltage center optimization
886 19:40:03.451824 INFO : End of 2D write delay Voltage center optimization
887 19:40:03.457339 INFO : Training has run successfully!
888 19:40:03.457883
889 19:40:03.458300 channel==0
890 19:40:03.462953 RxClkDly_Margin_A0==88 ps 9
891 19:40:03.463507 TxDqDly_Margin_A0==98 ps 10
892 19:40:03.468542 RxClkDly_Margin_A1==88 ps 9
893 19:40:03.469092 TxDqDly_Margin_A1==98 ps 10
894 19:40:03.469518 TrainedVREFDQ_A0==74
895 19:40:03.474139 TrainedVREFDQ_A1==74
896 19:40:03.474668 VrefDac_Margin_A0==25
897 19:40:03.475109 DeviceVref_Margin_A0==40
898 19:40:03.479773 VrefDac_Margin_A1==24
899 19:40:03.480379 DeviceVref_Margin_A1==40
900 19:40:03.480782
901 19:40:03.481195
902 19:40:03.485340 channel==1
903 19:40:03.485865 RxClkDly_Margin_A0==98 ps 10
904 19:40:03.486268 TxDqDly_Margin_A0==88 ps 9
905 19:40:03.490912 RxClkDly_Margin_A1==88 ps 9
906 19:40:03.491411 TxDqDly_Margin_A1==88 ps 9
907 19:40:03.496513 TrainedVREFDQ_A0==77
908 19:40:03.497036 TrainedVREFDQ_A1==77
909 19:40:03.497323 VrefDac_Margin_A0==22
910 19:40:03.502080 DeviceVref_Margin_A0==37
911 19:40:03.502437 VrefDac_Margin_A1==24
912 19:40:03.507672 DeviceVref_Margin_A1==37
913 19:40:03.508076
914 19:40:03.508344 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
915 19:40:03.508593
916 19:40:03.541303 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000018 00000019 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
917 19:40:03.541724 2D training succeed
918 19:40:03.546877 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
919 19:40:03.552460 auto size-- 65535DDR cs0 size: 2048MB
920 19:40:03.552807 DDR cs1 size: 2048MB
921 19:40:03.558048 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
922 19:40:03.558387 cs0 DataBus test pass
923 19:40:03.563661 cs1 DataBus test pass
924 19:40:03.564047 cs0 AddrBus test pass
925 19:40:03.564317 cs1 AddrBus test pass
926 19:40:03.564538
927 19:40:03.569315 100bdlr_step_size ps== 420
928 19:40:03.569680 result report
929 19:40:03.574815 boot times 0Enable ddr reg access
930 19:40:03.580092 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
931 19:40:03.593512 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
932 19:40:04.167408 0.0;M3 CHK:0;cm4_sp_mode 0
933 19:40:04.168092 MVN_1=0x00000000
934 19:40:04.172897 MVN_2=0x00000000
935 19:40:04.178633 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
936 19:40:04.179139 OPS=0x10
937 19:40:04.179544 ring efuse init
938 19:40:04.179936 chipver efuse init
939 19:40:04.184255 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
940 19:40:04.189856 [0.018961 Inits done]
941 19:40:04.190378 secure task start!
942 19:40:04.190778 high task start!
943 19:40:04.194457 low task start!
944 19:40:04.194993 run into bl31
945 19:40:04.201062 NOTICE: BL31: v1.3(release):4fc40b1
946 19:40:04.208874 NOTICE: BL31: Built : 15:58:17, May 22 2019
947 19:40:04.209401 NOTICE: BL31: G12A normal boot!
948 19:40:04.234225 NOTICE: BL31: BL33 decompress pass
949 19:40:04.239856 ERROR: Error initializing runtime service opteed_fast
950 19:40:05.472602
951 19:40:05.473053
952 19:40:05.481003 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
953 19:40:05.481477
954 19:40:05.481820 Model: Libre Computer AML-A311D-CC Alta
955 19:40:05.689574 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
956 19:40:05.712974 DRAM: 2 GiB (effective 3.8 GiB)
957 19:40:05.855959 Core: 408 devices, 31 uclasses, devicetree: separate
958 19:40:05.861883 WDT: Not starting watchdog@f0d0
959 19:40:05.894048 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
960 19:40:05.906403 Loading Environment from FAT... Card did not respond to voltage select! : -110
961 19:40:05.911442 ** Bad device specification mmc 0 **
962 19:40:05.921813 Card did not respond to voltage select! : -110
963 19:40:05.929464 ** Bad device specification mmc 0 **
964 19:40:05.930011 Couldn't find partition mmc 0
965 19:40:05.937844 Card did not respond to voltage select! : -110
966 19:40:05.943353 ** Bad device specification mmc 0 **
967 19:40:05.943935 Couldn't find partition mmc 0
968 19:40:05.948313 Error: could not access storage.
969 19:40:06.290925 Net: eth0: ethernet@ff3f0000
970 19:40:06.291549 starting USB...
971 19:40:06.542626 Bus usb@ff500000: Register 3000140 NbrPorts 3
972 19:40:06.543063 Starting the controller
973 19:40:06.549553 USB XHCI 1.10
974 19:40:08.411540 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
975 19:40:08.411967 bl2_stage_init 0x01
976 19:40:08.412213 bl2_stage_init 0x81
977 19:40:08.417073 hw id: 0x0000 - pwm id 0x01
978 19:40:08.417632 bl2_stage_init 0xc1
979 19:40:08.418058 bl2_stage_init 0x02
980 19:40:08.418480
981 19:40:08.422508 L0:00000000
982 19:40:08.422984 L1:20000703
983 19:40:08.423397 L2:00008067
984 19:40:08.423797 L3:14000000
985 19:40:08.425432 B2:00402000
986 19:40:08.425929 B1:e0f83180
987 19:40:08.426368
988 19:40:08.426777 TE: 58159
989 19:40:08.427181
990 19:40:08.436554 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
991 19:40:08.437046
992 19:40:08.437457 Board ID = 1
993 19:40:08.437853 Set A53 clk to 24M
994 19:40:08.438247 Set A73 clk to 24M
995 19:40:08.442275 Set clk81 to 24M
996 19:40:08.442767 A53 clk: 1200 MHz
997 19:40:08.443177 A73 clk: 1200 MHz
998 19:40:08.447825 CLK81: 166.6M
999 19:40:08.448336 smccc: 00012ab5
1000 19:40:08.453389 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
1001 19:40:08.453868 board id: 1
1002 19:40:08.462038 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
1003 19:40:08.472670 fw parse done
1004 19:40:08.478675 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
1005 19:40:08.521192 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
1006 19:40:08.532201 PIEI prepare done
1007 19:40:08.532559 fastboot data load
1008 19:40:08.532799 fastboot data verify
1009 19:40:08.537748 verify result: 266
1010 19:40:08.543376 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
1011 19:40:08.543738 LPDDR4 probe
1012 19:40:08.544015 ddr clk to 1584MHz
1013 19:40:08.551316 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
1014 19:40:08.588647
1015 19:40:08.589026 dmc_version 0001
1016 19:40:08.595204 Check phy result
1017 19:40:08.601067 INFO : End of CA training
1018 19:40:08.601332 INFO : End of initialization
1019 19:40:08.606647 INFO : Training has run successfully!
1020 19:40:08.606908 Check phy result
1021 19:40:08.612245 INFO : End of initialization
1022 19:40:08.612506 INFO : End of read enable training
1023 19:40:08.618015 INFO : End of fine write leveling
1024 19:40:08.623589 INFO : End of Write leveling coarse delay
1025 19:40:08.624129 INFO : Training has run successfully!
1026 19:40:08.624557 Check phy result
1027 19:40:08.629183 INFO : End of initialization
1028 19:40:08.629728 INFO : End of read dq deskew training
1029 19:40:08.634705 INFO : End of MPR read delay center optimization
1030 19:40:08.640369 INFO : End of write delay center optimization
1031 19:40:08.645959 INFO : End of read delay center optimization
1032 19:40:08.646502 INFO : End of max read latency training
1033 19:40:08.651532 INFO : Training has run successfully!
1034 19:40:08.652099 1D training succeed
1035 19:40:08.660687 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1036 19:40:08.708383 Check phy result
1037 19:40:08.708923 INFO : End of initialization
1038 19:40:08.730091 INFO : End of 2D read delay Voltage center optimization
1039 19:40:08.750385 INFO : End of 2D read delay Voltage center optimization
1040 19:40:08.802405 INFO : End of 2D write delay Voltage center optimization
1041 19:40:08.851831 INFO : End of 2D write delay Voltage center optimization
1042 19:40:08.857383 INFO : Training has run successfully!
1043 19:40:08.857930
1044 19:40:08.858391 channel==0
1045 19:40:08.862975 RxClkDly_Margin_A0==88 ps 9
1046 19:40:08.863515 TxDqDly_Margin_A0==98 ps 10
1047 19:40:08.868519 RxClkDly_Margin_A1==88 ps 9
1048 19:40:08.869050 TxDqDly_Margin_A1==98 ps 10
1049 19:40:08.869495 TrainedVREFDQ_A0==74
1050 19:40:08.874224 TrainedVREFDQ_A1==74
1051 19:40:08.874746 VrefDac_Margin_A0==25
1052 19:40:08.875191 DeviceVref_Margin_A0==40
1053 19:40:08.879717 VrefDac_Margin_A1==25
1054 19:40:08.880300 DeviceVref_Margin_A1==40
1055 19:40:08.880748
1056 19:40:08.881208
1057 19:40:08.885372 channel==1
1058 19:40:08.885887 RxClkDly_Margin_A0==98 ps 10
1059 19:40:08.886306 TxDqDly_Margin_A0==88 ps 9
1060 19:40:08.890928 RxClkDly_Margin_A1==88 ps 9
1061 19:40:08.891421 TxDqDly_Margin_A1==88 ps 9
1062 19:40:08.896513 TrainedVREFDQ_A0==77
1063 19:40:08.897001 TrainedVREFDQ_A1==77
1064 19:40:08.897412 VrefDac_Margin_A0==22
1065 19:40:08.902211 DeviceVref_Margin_A0==37
1066 19:40:08.902702 VrefDac_Margin_A1==24
1067 19:40:08.907711 DeviceVref_Margin_A1==37
1068 19:40:08.908228
1069 19:40:08.908643 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1070 19:40:08.909046
1071 19:40:08.941261 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000016 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
1072 19:40:08.941836 2D training succeed
1073 19:40:08.946977 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1074 19:40:08.952562 auto size-- 65535DDR cs0 size: 2048MB
1075 19:40:08.953060 DDR cs1 size: 2048MB
1076 19:40:08.958263 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1077 19:40:08.958760 cs0 DataBus test pass
1078 19:40:08.963757 cs1 DataBus test pass
1079 19:40:08.964285 cs0 AddrBus test pass
1080 19:40:08.964701 cs1 AddrBus test pass
1081 19:40:08.965107
1082 19:40:08.969352 100bdlr_step_size ps== 420
1083 19:40:08.969860 result report
1084 19:40:08.974953 boot times 0Enable ddr reg access
1085 19:40:08.980239 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1086 19:40:08.993654 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1087 19:40:09.567310 0.0;M3 CHK:0;cm4_sp_mode 0
1088 19:40:09.567765 MVN_1=0x00000000
1089 19:40:09.572679 MVN_2=0x00000000
1090 19:40:09.578409 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1091 19:40:09.578693 OPS=0x10
1092 19:40:09.578916 ring efuse init
1093 19:40:09.579128 chipver efuse init
1094 19:40:09.584001 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1095 19:40:09.589575 [0.018960 Inits done]
1096 19:40:09.589845 secure task start!
1097 19:40:09.590062 high task start!
1098 19:40:09.594201 low task start!
1099 19:40:09.594476 run into bl31
1100 19:40:09.600834 NOTICE: BL31: v1.3(release):4fc40b1
1101 19:40:09.608767 NOTICE: BL31: Built : 15:58:17, May 22 2019
1102 19:40:09.609306 NOTICE: BL31: G12A normal boot!
1103 19:40:09.634303 NOTICE: BL31: BL33 decompress pass
1104 19:40:09.639874 ERROR: Error initializing runtime service opteed_fast
1105 19:40:10.872733
1106 19:40:10.873394
1107 19:40:10.881133 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1108 19:40:10.881626
1109 19:40:10.882051 Model: Libre Computer AML-A311D-CC Alta
1110 19:40:11.089637 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1111 19:40:11.112939 DRAM: 2 GiB (effective 3.8 GiB)
1112 19:40:11.255972 Core: 408 devices, 31 uclasses, devicetree: separate
1113 19:40:11.261810 WDT: Not starting watchdog@f0d0
1114 19:40:11.294061 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1115 19:40:11.306470 Loading Environment from FAT... Card did not respond to voltage select! : -110
1116 19:40:11.311554 ** Bad device specification mmc 0 **
1117 19:40:11.321843 Card did not respond to voltage select! : -110
1118 19:40:11.329553 ** Bad device specification mmc 0 **
1119 19:40:11.330031 Couldn't find partition mmc 0
1120 19:40:11.337838 Card did not respond to voltage select! : -110
1121 19:40:11.343308 ** Bad device specification mmc 0 **
1122 19:40:11.343613 Couldn't find partition mmc 0
1123 19:40:11.348374 Error: could not access storage.
1124 19:40:11.692145 Net: eth0: ethernet@ff3f0000
1125 19:40:11.692805 starting USB...
1126 19:40:11.943695 Bus usb@ff500000: Register 3000140 NbrPorts 3
1127 19:40:11.944154 Starting the controller
1128 19:40:11.950620 USB XHCI 1.10
1129 19:40:13.505057 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1130 19:40:13.513415 scanning usb for storage devices... 0 Storage Device(s) found
1132 19:40:13.565209 Hit any key to stop autoboot: 1
1133 19:40:13.566534 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1134 19:40:13.567458 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1135 19:40:13.568037 Setting prompt string to ['=>']
1136 19:40:13.568549 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1137 19:40:13.580892 0
1138 19:40:13.581890 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1139 19:40:13.582396 Sending with 10 millisecond of delay
1141 19:40:14.717429 => setenv autoload no
1142 19:40:14.728252 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1143 19:40:14.733189 setenv autoload no
1144 19:40:14.733935 Sending with 10 millisecond of delay
1146 19:40:16.535453 => setenv initrd_high 0xffffffff
1147 19:40:16.546039 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1148 19:40:16.546644 setenv initrd_high 0xffffffff
1149 19:40:16.547118 Sending with 10 millisecond of delay
1151 19:40:18.163042 => setenv fdt_high 0xffffffff
1152 19:40:18.173589 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1153 19:40:18.174113 setenv fdt_high 0xffffffff
1154 19:40:18.174575 Sending with 10 millisecond of delay
1156 19:40:18.466008 => dhcp
1157 19:40:18.476585 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1158 19:40:18.477108 dhcp
1159 19:40:18.477348 Speed: 1000, full duplex
1160 19:40:18.477559 BOOTP broadcast 1
1161 19:40:18.725412 DHCP client bound to address 192.168.6.27 (248 ms)
1162 19:40:18.726066 Sending with 10 millisecond of delay
1164 19:40:20.404034 => setenv serverip 192.168.6.2
1165 19:40:20.414644 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1166 19:40:20.415256 setenv serverip 192.168.6.2
1167 19:40:20.415725 Sending with 10 millisecond of delay
1169 19:40:24.140892 => tftpboot 0x01080000 967934/tftp-deploy-azjqtwi5/kernel/uImage
1170 19:40:24.151764 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1171 19:40:24.152814 tftpboot 0x01080000 967934/tftp-deploy-azjqtwi5/kernel/uImage
1172 19:40:24.153289 Speed: 1000, full duplex
1173 19:40:24.153748 Using ethernet@ff3f0000 device
1174 19:40:24.154532 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1175 19:40:24.160052 Filename '967934/tftp-deploy-azjqtwi5/kernel/uImage'.
1176 19:40:24.163680 Load address: 0x1080000
1177 19:40:27.091292 Loading: *################################################## 43.6 MiB
1178 19:40:27.091910 14.9 MiB/s
1179 19:40:27.092387 done
1180 19:40:27.095708 Bytes transferred = 45713984 (2b98a40 hex)
1181 19:40:27.096490 Sending with 10 millisecond of delay
1183 19:40:31.782938 => tftpboot 0x08000000 967934/tftp-deploy-azjqtwi5/ramdisk/ramdisk.cpio.gz.uboot
1184 19:40:31.793745 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1185 19:40:31.794612 tftpboot 0x08000000 967934/tftp-deploy-azjqtwi5/ramdisk/ramdisk.cpio.gz.uboot
1186 19:40:31.795037 Speed: 1000, full duplex
1187 19:40:31.795434 Using ethernet@ff3f0000 device
1188 19:40:31.796629 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1189 19:40:31.808320 Filename '967934/tftp-deploy-azjqtwi5/ramdisk/ramdisk.cpio.gz.uboot'.
1190 19:40:31.808826 Load address: 0x8000000
1191 19:40:38.789741 Loading: *################T ################################# UDP wrong checksum 00000005 00008ed9
1192 19:40:43.790605 T UDP wrong checksum 00000005 00008ed9
1193 19:40:53.793640 T T UDP wrong checksum 00000005 00008ed9
1194 19:40:58.949435 T UDP wrong checksum 000000ff 0000f8c4
1195 19:40:58.981067 UDP wrong checksum 000000ff 000091b7
1196 19:41:13.797817 T T T UDP wrong checksum 00000005 00008ed9
1197 19:41:28.800718 T T
1198 19:41:28.801358 Retry count exceeded; starting again
1200 19:41:28.802854 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1203 19:41:28.804910 end: 2.4 uboot-commands (duration 00:01:52) [common]
1205 19:41:28.806331 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1207 19:41:28.807364 end: 2 uboot-action (duration 00:01:52) [common]
1209 19:41:28.808925 Cleaning after the job
1210 19:41:28.809482 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/967934/tftp-deploy-azjqtwi5/ramdisk
1211 19:41:28.810840 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/967934/tftp-deploy-azjqtwi5/kernel
1212 19:41:28.837987 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/967934/tftp-deploy-azjqtwi5/dtb
1213 19:41:28.839466 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/967934/tftp-deploy-azjqtwi5/nfsrootfs
1214 19:41:28.878425 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/967934/tftp-deploy-azjqtwi5/modules
1215 19:41:28.885933 start: 4.1 power-off (timeout 00:00:30) [common]
1216 19:41:28.886595 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1217 19:41:28.917774 >> OK - accepted request
1218 19:41:28.919788 Returned 0 in 0 seconds
1219 19:41:29.020546 end: 4.1 power-off (duration 00:00:00) [common]
1221 19:41:29.021517 start: 4.2 read-feedback (timeout 00:10:00) [common]
1222 19:41:29.022189 Listened to connection for namespace 'common' for up to 1s
1223 19:41:30.022717 Finalising connection for namespace 'common'
1224 19:41:30.023437 Disconnecting from shell: Finalise
1225 19:41:30.023977 =>
1226 19:41:30.125096 end: 4.2 read-feedback (duration 00:00:01) [common]
1227 19:41:30.125810 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/967934
1228 19:41:33.162759 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/967934
1229 19:41:33.163384 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.