Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 19:41:57.481086 lava-dispatcher, installed at version: 2024.01
2 19:41:57.482057 start: 0 validate
3 19:41:57.482636 Start time: 2024-11-09 19:41:57.482599+00:00 (UTC)
4 19:41:57.483297 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 19:41:57.483934 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 19:41:57.521401 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 19:41:57.521984 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-679-gc8994e7b0f32%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 19:41:57.552499 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 19:41:57.553137 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-679-gc8994e7b0f32%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 19:41:57.586690 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 19:41:57.587201 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 19:41:57.623452 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 19:41:57.624163 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-679-gc8994e7b0f32%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 19:41:57.664466 validate duration: 0.18
16 19:41:57.665319 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 19:41:57.665648 start: 1.1 download-retry (timeout 00:10:00) [common]
18 19:41:57.665964 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 19:41:57.666550 Not decompressing ramdisk as can be used compressed.
20 19:41:57.666995 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 19:41:57.667275 saving as /var/lib/lava/dispatcher/tmp/967951/tftp-deploy-fqfej2nx/ramdisk/initrd.cpio.gz
22 19:41:57.667543 total size: 5628140 (5 MB)
23 19:41:57.706448 progress 0 % (0 MB)
24 19:41:57.710662 progress 5 % (0 MB)
25 19:41:57.715006 progress 10 % (0 MB)
26 19:41:57.718763 progress 15 % (0 MB)
27 19:41:57.723452 progress 20 % (1 MB)
28 19:41:57.727735 progress 25 % (1 MB)
29 19:41:57.732067 progress 30 % (1 MB)
30 19:41:57.736290 progress 35 % (1 MB)
31 19:41:57.739917 progress 40 % (2 MB)
32 19:41:57.744011 progress 45 % (2 MB)
33 19:41:57.747658 progress 50 % (2 MB)
34 19:41:57.751739 progress 55 % (2 MB)
35 19:41:57.755814 progress 60 % (3 MB)
36 19:41:57.759443 progress 65 % (3 MB)
37 19:41:57.763516 progress 70 % (3 MB)
38 19:41:57.767289 progress 75 % (4 MB)
39 19:41:57.771430 progress 80 % (4 MB)
40 19:41:57.775081 progress 85 % (4 MB)
41 19:41:57.779073 progress 90 % (4 MB)
42 19:41:57.783052 progress 95 % (5 MB)
43 19:41:57.786346 progress 100 % (5 MB)
44 19:41:57.786992 5 MB downloaded in 0.12 s (44.94 MB/s)
45 19:41:57.787565 end: 1.1.1 http-download (duration 00:00:00) [common]
47 19:41:57.788483 end: 1.1 download-retry (duration 00:00:00) [common]
48 19:41:57.788776 start: 1.2 download-retry (timeout 00:10:00) [common]
49 19:41:57.789043 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 19:41:57.789528 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-679-gc8994e7b0f32/arm64/defconfig/gcc-12/kernel/Image
51 19:41:57.789770 saving as /var/lib/lava/dispatcher/tmp/967951/tftp-deploy-fqfej2nx/kernel/Image
52 19:41:57.789978 total size: 45713920 (43 MB)
53 19:41:57.790188 No compression specified
54 19:41:57.832265 progress 0 % (0 MB)
55 19:41:57.859854 progress 5 % (2 MB)
56 19:41:57.888025 progress 10 % (4 MB)
57 19:41:57.916011 progress 15 % (6 MB)
58 19:41:57.943770 progress 20 % (8 MB)
59 19:41:57.971282 progress 25 % (10 MB)
60 19:41:57.998979 progress 30 % (13 MB)
61 19:41:58.027679 progress 35 % (15 MB)
62 19:41:58.055680 progress 40 % (17 MB)
63 19:41:58.083131 progress 45 % (19 MB)
64 19:41:58.111561 progress 50 % (21 MB)
65 19:41:58.140040 progress 55 % (24 MB)
66 19:41:58.168482 progress 60 % (26 MB)
67 19:41:58.196412 progress 65 % (28 MB)
68 19:41:58.224832 progress 70 % (30 MB)
69 19:41:58.253867 progress 75 % (32 MB)
70 19:41:58.282777 progress 80 % (34 MB)
71 19:41:58.310924 progress 85 % (37 MB)
72 19:41:58.339574 progress 90 % (39 MB)
73 19:41:58.369041 progress 95 % (41 MB)
74 19:41:58.397442 progress 100 % (43 MB)
75 19:41:58.398066 43 MB downloaded in 0.61 s (71.70 MB/s)
76 19:41:58.398589 end: 1.2.1 http-download (duration 00:00:01) [common]
78 19:41:58.399442 end: 1.2 download-retry (duration 00:00:01) [common]
79 19:41:58.399721 start: 1.3 download-retry (timeout 00:09:59) [common]
80 19:41:58.400008 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 19:41:58.400791 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-679-gc8994e7b0f32/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 19:41:58.401135 saving as /var/lib/lava/dispatcher/tmp/967951/tftp-deploy-fqfej2nx/dtb/meson-g12b-a311d-libretech-cc.dtb
83 19:41:58.401350 total size: 54703 (0 MB)
84 19:41:58.401560 No compression specified
85 19:41:58.453528 progress 59 % (0 MB)
86 19:41:58.454452 progress 100 % (0 MB)
87 19:41:58.455064 0 MB downloaded in 0.05 s (0.97 MB/s)
88 19:41:58.455581 end: 1.3.1 http-download (duration 00:00:00) [common]
90 19:41:58.456585 end: 1.3 download-retry (duration 00:00:00) [common]
91 19:41:58.456897 start: 1.4 download-retry (timeout 00:09:59) [common]
92 19:41:58.457185 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 19:41:58.457908 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 19:41:58.458228 saving as /var/lib/lava/dispatcher/tmp/967951/tftp-deploy-fqfej2nx/nfsrootfs/full.rootfs.tar
95 19:41:58.458451 total size: 474398908 (452 MB)
96 19:41:58.458706 Using unxz to decompress xz
97 19:41:58.495454 progress 0 % (0 MB)
98 19:41:59.669017 progress 5 % (22 MB)
99 19:42:01.168702 progress 10 % (45 MB)
100 19:42:01.639009 progress 15 % (67 MB)
101 19:42:02.455231 progress 20 % (90 MB)
102 19:42:03.037393 progress 25 % (113 MB)
103 19:42:03.388188 progress 30 % (135 MB)
104 19:42:03.997721 progress 35 % (158 MB)
105 19:42:04.837348 progress 40 % (181 MB)
106 19:42:05.576867 progress 45 % (203 MB)
107 19:42:06.148590 progress 50 % (226 MB)
108 19:42:06.802528 progress 55 % (248 MB)
109 19:42:08.005678 progress 60 % (271 MB)
110 19:42:09.418255 progress 65 % (294 MB)
111 19:42:11.042850 progress 70 % (316 MB)
112 19:42:14.175777 progress 75 % (339 MB)
113 19:42:16.614814 progress 80 % (361 MB)
114 19:42:19.542843 progress 85 % (384 MB)
115 19:42:22.760191 progress 90 % (407 MB)
116 19:42:26.020035 progress 95 % (429 MB)
117 19:42:29.522193 progress 100 % (452 MB)
118 19:42:29.536325 452 MB downloaded in 31.08 s (14.56 MB/s)
119 19:42:29.537297 end: 1.4.1 http-download (duration 00:00:31) [common]
121 19:42:29.539043 end: 1.4 download-retry (duration 00:00:31) [common]
122 19:42:29.539621 start: 1.5 download-retry (timeout 00:09:28) [common]
123 19:42:29.540249 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 19:42:29.541119 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-679-gc8994e7b0f32/arm64/defconfig/gcc-12/modules.tar.xz
125 19:42:29.541631 saving as /var/lib/lava/dispatcher/tmp/967951/tftp-deploy-fqfej2nx/modules/modules.tar
126 19:42:29.542077 total size: 11612124 (11 MB)
127 19:42:29.542537 Using unxz to decompress xz
128 19:42:29.589789 progress 0 % (0 MB)
129 19:42:29.656108 progress 5 % (0 MB)
130 19:42:29.729936 progress 10 % (1 MB)
131 19:42:29.825938 progress 15 % (1 MB)
132 19:42:29.921682 progress 20 % (2 MB)
133 19:42:30.002121 progress 25 % (2 MB)
134 19:42:30.078635 progress 30 % (3 MB)
135 19:42:30.158292 progress 35 % (3 MB)
136 19:42:30.231719 progress 40 % (4 MB)
137 19:42:30.309237 progress 45 % (5 MB)
138 19:42:30.394773 progress 50 % (5 MB)
139 19:42:30.474635 progress 55 % (6 MB)
140 19:42:30.566664 progress 60 % (6 MB)
141 19:42:30.663874 progress 65 % (7 MB)
142 19:42:30.753203 progress 70 % (7 MB)
143 19:42:30.832609 progress 75 % (8 MB)
144 19:42:30.916929 progress 80 % (8 MB)
145 19:42:30.997538 progress 85 % (9 MB)
146 19:42:31.077918 progress 90 % (9 MB)
147 19:42:31.158181 progress 95 % (10 MB)
148 19:42:31.236922 progress 100 % (11 MB)
149 19:42:31.248573 11 MB downloaded in 1.71 s (6.49 MB/s)
150 19:42:31.249156 end: 1.5.1 http-download (duration 00:00:02) [common]
152 19:42:31.249972 end: 1.5 download-retry (duration 00:00:02) [common]
153 19:42:31.250242 start: 1.6 prepare-tftp-overlay (timeout 00:09:26) [common]
154 19:42:31.250509 start: 1.6.1 extract-nfsrootfs (timeout 00:09:26) [common]
155 19:42:47.732860 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/967951/extract-nfsrootfs-id18tvc3
156 19:42:47.733465 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 19:42:47.733791 start: 1.6.2 lava-overlay (timeout 00:09:10) [common]
158 19:42:47.734594 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej
159 19:42:47.735133 makedir: /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin
160 19:42:47.735559 makedir: /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/tests
161 19:42:47.735951 makedir: /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/results
162 19:42:47.736342 Creating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin/lava-add-keys
163 19:42:47.736888 Creating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin/lava-add-sources
164 19:42:47.737486 Creating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin/lava-background-process-start
165 19:42:47.738071 Creating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin/lava-background-process-stop
166 19:42:47.738654 Creating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin/lava-common-functions
167 19:42:47.739163 Creating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin/lava-echo-ipv4
168 19:42:47.739758 Creating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin/lava-install-packages
169 19:42:47.740318 Creating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin/lava-installed-packages
170 19:42:47.740812 Creating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin/lava-os-build
171 19:42:47.741299 Creating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin/lava-probe-channel
172 19:42:47.741816 Creating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin/lava-probe-ip
173 19:42:47.742301 Creating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin/lava-target-ip
174 19:42:47.742783 Creating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin/lava-target-mac
175 19:42:47.743292 Creating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin/lava-target-storage
176 19:42:47.743820 Creating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin/lava-test-case
177 19:42:47.744368 Creating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin/lava-test-event
178 19:42:47.744859 Creating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin/lava-test-feedback
179 19:42:47.745337 Creating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin/lava-test-raise
180 19:42:47.745811 Creating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin/lava-test-reference
181 19:42:47.746330 Creating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin/lava-test-runner
182 19:42:47.746819 Creating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin/lava-test-set
183 19:42:47.747436 Creating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin/lava-test-shell
184 19:42:47.747955 Updating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin/lava-install-packages (oe)
185 19:42:47.748611 Updating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/bin/lava-installed-packages (oe)
186 19:42:47.749098 Creating /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/environment
187 19:42:47.749511 LAVA metadata
188 19:42:47.749773 - LAVA_JOB_ID=967951
189 19:42:47.749987 - LAVA_DISPATCHER_IP=192.168.6.2
190 19:42:47.750349 start: 1.6.2.1 ssh-authorize (timeout 00:09:10) [common]
191 19:42:47.751339 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 19:42:47.751652 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:10) [common]
193 19:42:47.751857 skipped lava-vland-overlay
194 19:42:47.752122 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 19:42:47.752377 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:10) [common]
196 19:42:47.752593 skipped lava-multinode-overlay
197 19:42:47.752831 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 19:42:47.753078 start: 1.6.2.4 test-definition (timeout 00:09:10) [common]
199 19:42:47.753324 Loading test definitions
200 19:42:47.753599 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:10) [common]
201 19:42:47.753818 Using /lava-967951 at stage 0
202 19:42:47.755042 uuid=967951_1.6.2.4.1 testdef=None
203 19:42:47.755353 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 19:42:47.755616 start: 1.6.2.4.2 test-overlay (timeout 00:09:10) [common]
205 19:42:47.757448 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 19:42:47.758242 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:10) [common]
208 19:42:47.760478 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 19:42:47.761309 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:10) [common]
211 19:42:47.763416 runner path: /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/0/tests/0_v4l2-decoder-conformance-h265 test_uuid 967951_1.6.2.4.1
212 19:42:47.764017 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 19:42:47.764778 Creating lava-test-runner.conf files
215 19:42:47.764977 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/967951/lava-overlay-0rh6_9ej/lava-967951/0 for stage 0
216 19:42:47.765390 - 0_v4l2-decoder-conformance-h265
217 19:42:47.765745 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 19:42:47.766018 start: 1.6.2.5 compress-overlay (timeout 00:09:10) [common]
219 19:42:47.787483 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 19:42:47.787864 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:10) [common]
221 19:42:47.788159 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 19:42:47.788426 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 19:42:47.788687 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:10) [common]
224 19:42:48.433908 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 19:42:48.434352 start: 1.6.4 extract-modules (timeout 00:09:09) [common]
226 19:42:48.434599 extracting modules file /var/lib/lava/dispatcher/tmp/967951/tftp-deploy-fqfej2nx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/967951/extract-nfsrootfs-id18tvc3
227 19:42:49.790694 extracting modules file /var/lib/lava/dispatcher/tmp/967951/tftp-deploy-fqfej2nx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/967951/extract-overlay-ramdisk-l_0onr1v/ramdisk
228 19:42:51.172936 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 19:42:51.173415 start: 1.6.5 apply-overlay-tftp (timeout 00:09:06) [common]
230 19:42:51.173690 [common] Applying overlay to NFS
231 19:42:51.173901 [common] Applying overlay /var/lib/lava/dispatcher/tmp/967951/compress-overlay-uop464mh/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/967951/extract-nfsrootfs-id18tvc3
232 19:42:51.202836 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 19:42:51.203207 start: 1.6.6 prepare-kernel (timeout 00:09:06) [common]
234 19:42:51.203474 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:06) [common]
235 19:42:51.203698 Converting downloaded kernel to a uImage
236 19:42:51.204023 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/967951/tftp-deploy-fqfej2nx/kernel/Image /var/lib/lava/dispatcher/tmp/967951/tftp-deploy-fqfej2nx/kernel/uImage
237 19:42:51.677922 output: Image Name:
238 19:42:51.678350 output: Created: Sat Nov 9 19:42:51 2024
239 19:42:51.678560 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 19:42:51.678764 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 19:42:51.678966 output: Load Address: 01080000
242 19:42:51.679165 output: Entry Point: 01080000
243 19:42:51.679361 output:
244 19:42:51.679697 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 19:42:51.679965 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 19:42:51.680309 start: 1.6.7 configure-preseed-file (timeout 00:09:06) [common]
247 19:42:51.680567 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 19:42:51.680825 start: 1.6.8 compress-ramdisk (timeout 00:09:06) [common]
249 19:42:51.681082 Building ramdisk /var/lib/lava/dispatcher/tmp/967951/extract-overlay-ramdisk-l_0onr1v/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/967951/extract-overlay-ramdisk-l_0onr1v/ramdisk
250 19:42:53.832549 >> 166827 blocks
251 19:43:02.977329 Adding RAMdisk u-boot header.
252 19:43:02.978043 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/967951/extract-overlay-ramdisk-l_0onr1v/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/967951/extract-overlay-ramdisk-l_0onr1v/ramdisk.cpio.gz.uboot
253 19:43:03.249993 output: Image Name:
254 19:43:03.250406 output: Created: Sat Nov 9 19:43:02 2024
255 19:43:03.250615 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 19:43:03.250820 output: Data Size: 23436353 Bytes = 22887.06 KiB = 22.35 MiB
257 19:43:03.251020 output: Load Address: 00000000
258 19:43:03.251217 output: Entry Point: 00000000
259 19:43:03.251414 output:
260 19:43:03.252156 rename /var/lib/lava/dispatcher/tmp/967951/extract-overlay-ramdisk-l_0onr1v/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/967951/tftp-deploy-fqfej2nx/ramdisk/ramdisk.cpio.gz.uboot
261 19:43:03.252952 end: 1.6.8 compress-ramdisk (duration 00:00:12) [common]
262 19:43:03.253578 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
263 19:43:03.254192 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:54) [common]
264 19:43:03.254693 No LXC device requested
265 19:43:03.255239 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 19:43:03.255798 start: 1.8 deploy-device-env (timeout 00:08:54) [common]
267 19:43:03.256376 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 19:43:03.256832 Checking files for TFTP limit of 4294967296 bytes.
269 19:43:03.259743 end: 1 tftp-deploy (duration 00:01:06) [common]
270 19:43:03.260407 start: 2 uboot-action (timeout 00:05:00) [common]
271 19:43:03.260985 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 19:43:03.261534 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 19:43:03.262084 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 19:43:03.262664 Using kernel file from prepare-kernel: 967951/tftp-deploy-fqfej2nx/kernel/uImage
275 19:43:03.263362 substitutions:
276 19:43:03.263809 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 19:43:03.264288 - {DTB_ADDR}: 0x01070000
278 19:43:03.264727 - {DTB}: 967951/tftp-deploy-fqfej2nx/dtb/meson-g12b-a311d-libretech-cc.dtb
279 19:43:03.265164 - {INITRD}: 967951/tftp-deploy-fqfej2nx/ramdisk/ramdisk.cpio.gz.uboot
280 19:43:03.265599 - {KERNEL_ADDR}: 0x01080000
281 19:43:03.266031 - {KERNEL}: 967951/tftp-deploy-fqfej2nx/kernel/uImage
282 19:43:03.266464 - {LAVA_MAC}: None
283 19:43:03.266937 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/967951/extract-nfsrootfs-id18tvc3
284 19:43:03.267373 - {NFS_SERVER_IP}: 192.168.6.2
285 19:43:03.267801 - {PRESEED_CONFIG}: None
286 19:43:03.268264 - {PRESEED_LOCAL}: None
287 19:43:03.268694 - {RAMDISK_ADDR}: 0x08000000
288 19:43:03.269120 - {RAMDISK}: 967951/tftp-deploy-fqfej2nx/ramdisk/ramdisk.cpio.gz.uboot
289 19:43:03.269546 - {ROOT_PART}: None
290 19:43:03.269973 - {ROOT}: None
291 19:43:03.270398 - {SERVER_IP}: 192.168.6.2
292 19:43:03.270825 - {TEE_ADDR}: 0x83000000
293 19:43:03.271247 - {TEE}: None
294 19:43:03.271670 Parsed boot commands:
295 19:43:03.272108 - setenv autoload no
296 19:43:03.272536 - setenv initrd_high 0xffffffff
297 19:43:03.272959 - setenv fdt_high 0xffffffff
298 19:43:03.273382 - dhcp
299 19:43:03.273806 - setenv serverip 192.168.6.2
300 19:43:03.274227 - tftpboot 0x01080000 967951/tftp-deploy-fqfej2nx/kernel/uImage
301 19:43:03.274652 - tftpboot 0x08000000 967951/tftp-deploy-fqfej2nx/ramdisk/ramdisk.cpio.gz.uboot
302 19:43:03.275073 - tftpboot 0x01070000 967951/tftp-deploy-fqfej2nx/dtb/meson-g12b-a311d-libretech-cc.dtb
303 19:43:03.275498 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/967951/extract-nfsrootfs-id18tvc3,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 19:43:03.275935 - bootm 0x01080000 0x08000000 0x01070000
305 19:43:03.276572 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 19:43:03.278220 start: 2.3 connect-device (timeout 00:05:00) [common]
308 19:43:03.278681 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 19:43:03.293989 Setting prompt string to ['lava-test: # ']
310 19:43:03.295618 end: 2.3 connect-device (duration 00:00:00) [common]
311 19:43:03.296310 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 19:43:03.296915 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 19:43:03.297500 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 19:43:03.298728 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 19:43:03.336423 >> OK - accepted request
316 19:43:03.338742 Returned 0 in 0 seconds
317 19:43:03.439939 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 19:43:03.441711 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 19:43:03.442316 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 19:43:03.442888 Setting prompt string to ['Hit any key to stop autoboot']
322 19:43:03.443436 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 19:43:03.445200 Trying 192.168.56.21...
324 19:43:03.445725 Connected to conserv1.
325 19:43:03.446187 Escape character is '^]'.
326 19:43:03.446644
327 19:43:03.447101 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 19:43:03.447560
329 19:43:14.830614 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 19:43:14.831294 bl2_stage_init 0x01
331 19:43:14.831745 bl2_stage_init 0x81
332 19:43:14.836336 hw id: 0x0000 - pwm id 0x01
333 19:43:14.836823 bl2_stage_init 0xc1
334 19:43:14.837260 bl2_stage_init 0x02
335 19:43:14.837689
336 19:43:14.841851 L0:00000000
337 19:43:14.842328 L1:20000703
338 19:43:14.842762 L2:00008067
339 19:43:14.843188 L3:14000000
340 19:43:14.844805 B2:00402000
341 19:43:14.845281 B1:e0f83180
342 19:43:14.845709
343 19:43:14.846139 TE: 58124
344 19:43:14.846565
345 19:43:14.856042 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 19:43:14.856511
347 19:43:14.856944 Board ID = 1
348 19:43:14.857366 Set A53 clk to 24M
349 19:43:14.857786 Set A73 clk to 24M
350 19:43:14.861563 Set clk81 to 24M
351 19:43:14.862018 A53 clk: 1200 MHz
352 19:43:14.862444 A73 clk: 1200 MHz
353 19:43:14.865095 CLK81: 166.6M
354 19:43:14.865548 smccc: 00012a92
355 19:43:14.870663 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 19:43:14.876270 board id: 1
357 19:43:14.881454 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 19:43:14.891881 fw parse done
359 19:43:14.897842 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 19:43:14.940476 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 19:43:14.951415 PIEI prepare done
362 19:43:14.951883 fastboot data load
363 19:43:14.952371 fastboot data verify
364 19:43:14.956940 verify result: 266
365 19:43:14.962533 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 19:43:14.962987 LPDDR4 probe
367 19:43:14.963415 ddr clk to 1584MHz
368 19:43:14.970535 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 19:43:15.007872
370 19:43:15.008367 dmc_version 0001
371 19:43:15.014532 Check phy result
372 19:43:15.020422 INFO : End of CA training
373 19:43:15.020886 INFO : End of initialization
374 19:43:15.025927 INFO : Training has run successfully!
375 19:43:15.026382 Check phy result
376 19:43:15.031638 INFO : End of initialization
377 19:43:15.032127 INFO : End of read enable training
378 19:43:15.037199 INFO : End of fine write leveling
379 19:43:15.042795 INFO : End of Write leveling coarse delay
380 19:43:15.043251 INFO : Training has run successfully!
381 19:43:15.043680 Check phy result
382 19:43:15.048394 INFO : End of initialization
383 19:43:15.048856 INFO : End of read dq deskew training
384 19:43:15.053940 INFO : End of MPR read delay center optimization
385 19:43:15.059591 INFO : End of write delay center optimization
386 19:43:15.065172 INFO : End of read delay center optimization
387 19:43:15.065630 INFO : End of max read latency training
388 19:43:15.070796 INFO : Training has run successfully!
389 19:43:15.071261 1D training succeed
390 19:43:15.080059 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 19:43:15.127610 Check phy result
392 19:43:15.128153 INFO : End of initialization
393 19:43:15.150043 INFO : End of 2D read delay Voltage center optimization
394 19:43:15.170061 INFO : End of 2D read delay Voltage center optimization
395 19:43:15.222136 INFO : End of 2D write delay Voltage center optimization
396 19:43:15.271286 INFO : End of 2D write delay Voltage center optimization
397 19:43:15.276765 INFO : Training has run successfully!
398 19:43:15.277221
399 19:43:15.277671 channel==0
400 19:43:15.282456 RxClkDly_Margin_A0==88 ps 9
401 19:43:15.282914 TxDqDly_Margin_A0==98 ps 10
402 19:43:15.288018 RxClkDly_Margin_A1==88 ps 9
403 19:43:15.288474 TxDqDly_Margin_A1==98 ps 10
404 19:43:15.288910 TrainedVREFDQ_A0==74
405 19:43:15.293573 TrainedVREFDQ_A1==74
406 19:43:15.294029 VrefDac_Margin_A0==25
407 19:43:15.294460 DeviceVref_Margin_A0==40
408 19:43:15.299257 VrefDac_Margin_A1==25
409 19:43:15.299709 DeviceVref_Margin_A1==40
410 19:43:15.300169
411 19:43:15.300601
412 19:43:15.304845 channel==1
413 19:43:15.305302 RxClkDly_Margin_A0==98 ps 10
414 19:43:15.305733 TxDqDly_Margin_A0==88 ps 9
415 19:43:15.310468 RxClkDly_Margin_A1==98 ps 10
416 19:43:15.310920 TxDqDly_Margin_A1==88 ps 9
417 19:43:15.316077 TrainedVREFDQ_A0==76
418 19:43:15.316537 TrainedVREFDQ_A1==77
419 19:43:15.316971 VrefDac_Margin_A0==22
420 19:43:15.321622 DeviceVref_Margin_A0==38
421 19:43:15.322091 VrefDac_Margin_A1==22
422 19:43:15.327269 DeviceVref_Margin_A1==37
423 19:43:15.327726
424 19:43:15.328191 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 19:43:15.328620
426 19:43:15.360779 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 00000019 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
427 19:43:15.361335 2D training succeed
428 19:43:15.366376 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 19:43:15.371966 auto size-- 65535DDR cs0 size: 2048MB
430 19:43:15.372472 DDR cs1 size: 2048MB
431 19:43:15.377573 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 19:43:15.378036 cs0 DataBus test pass
433 19:43:15.383191 cs1 DataBus test pass
434 19:43:15.383654 cs0 AddrBus test pass
435 19:43:15.384121 cs1 AddrBus test pass
436 19:43:15.384549
437 19:43:15.388773 100bdlr_step_size ps== 420
438 19:43:15.389239 result report
439 19:43:15.394346 boot times 0Enable ddr reg access
440 19:43:15.399782 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 19:43:15.413223 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 19:43:15.985297 0.0;M3 CHK:0;cm4_sp_mode 0
443 19:43:15.985983 MVN_1=0x00000000
444 19:43:15.990760 MVN_2=0x00000000
445 19:43:15.996454 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 19:43:15.996927 OPS=0x10
447 19:43:15.997376 ring efuse init
448 19:43:15.997817 chipver efuse init
449 19:43:16.002100 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 19:43:16.007676 [0.018960 Inits done]
451 19:43:16.008195 secure task start!
452 19:43:16.008641 high task start!
453 19:43:16.012206 low task start!
454 19:43:16.012683 run into bl31
455 19:43:16.018833 NOTICE: BL31: v1.3(release):4fc40b1
456 19:43:16.026629 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 19:43:16.027113 NOTICE: BL31: G12A normal boot!
458 19:43:16.052033 NOTICE: BL31: BL33 decompress pass
459 19:43:16.056767 ERROR: Error initializing runtime service opteed_fast
460 19:43:17.290669
461 19:43:17.291328
462 19:43:17.299010 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 19:43:17.299536
464 19:43:17.300030 Model: Libre Computer AML-A311D-CC Alta
465 19:43:17.507522 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 19:43:17.530799 DRAM: 2 GiB (effective 3.8 GiB)
467 19:43:17.673830 Core: 408 devices, 31 uclasses, devicetree: separate
468 19:43:17.679659 WDT: Not starting watchdog@f0d0
469 19:43:17.711908 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 19:43:17.724376 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 19:43:17.729350 ** Bad device specification mmc 0 **
472 19:43:17.739682 Card did not respond to voltage select! : -110
473 19:43:17.747316 ** Bad device specification mmc 0 **
474 19:43:17.747798 Couldn't find partition mmc 0
475 19:43:17.755669 Card did not respond to voltage select! : -110
476 19:43:17.761260 ** Bad device specification mmc 0 **
477 19:43:17.761778 Couldn't find partition mmc 0
478 19:43:17.766329 Error: could not access storage.
479 19:43:19.030937 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 19:43:19.031600 bl2_stage_init 0x01
481 19:43:19.032115 bl2_stage_init 0x81
482 19:43:19.036442 hw id: 0x0000 - pwm id 0x01
483 19:43:19.036934 bl2_stage_init 0xc1
484 19:43:19.037391 bl2_stage_init 0x02
485 19:43:19.037835
486 19:43:19.042022 L0:00000000
487 19:43:19.042500 L1:20000703
488 19:43:19.042945 L2:00008067
489 19:43:19.043386 L3:14000000
490 19:43:19.047627 B2:00402000
491 19:43:19.048136 B1:e0f83180
492 19:43:19.048585
493 19:43:19.049026 TE: 58159
494 19:43:19.049468
495 19:43:19.053247 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 19:43:19.053731
497 19:43:19.054176 Board ID = 1
498 19:43:19.058859 Set A53 clk to 24M
499 19:43:19.059335 Set A73 clk to 24M
500 19:43:19.059776 Set clk81 to 24M
501 19:43:19.064421 A53 clk: 1200 MHz
502 19:43:19.064911 A73 clk: 1200 MHz
503 19:43:19.065357 CLK81: 166.6M
504 19:43:19.065799 smccc: 00012ab5
505 19:43:19.070049 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 19:43:19.075634 board id: 1
507 19:43:19.081490 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 19:43:19.092174 fw parse done
509 19:43:19.098189 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 19:43:19.140783 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 19:43:19.151686 PIEI prepare done
512 19:43:19.152234 fastboot data load
513 19:43:19.152690 fastboot data verify
514 19:43:19.157456 verify result: 266
515 19:43:19.162921 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 19:43:19.163393 LPDDR4 probe
517 19:43:19.163837 ddr clk to 1584MHz
518 19:43:19.170916 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 19:43:19.208211
520 19:43:19.208720 dmc_version 0001
521 19:43:19.214835 Check phy result
522 19:43:19.220699 INFO : End of CA training
523 19:43:19.221176 INFO : End of initialization
524 19:43:19.226310 INFO : Training has run successfully!
525 19:43:19.226817 Check phy result
526 19:43:19.231900 INFO : End of initialization
527 19:43:19.232408 INFO : End of read enable training
528 19:43:19.237516 INFO : End of fine write leveling
529 19:43:19.243101 INFO : End of Write leveling coarse delay
530 19:43:19.243593 INFO : Training has run successfully!
531 19:43:19.244069 Check phy result
532 19:43:19.248732 INFO : End of initialization
533 19:43:19.249202 INFO : End of read dq deskew training
534 19:43:19.254293 INFO : End of MPR read delay center optimization
535 19:43:19.259869 INFO : End of write delay center optimization
536 19:43:19.265501 INFO : End of read delay center optimization
537 19:43:19.265972 INFO : End of max read latency training
538 19:43:19.271107 INFO : Training has run successfully!
539 19:43:19.271601 1D training succeed
540 19:43:19.280273 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 19:43:19.327858 Check phy result
542 19:43:19.328395 INFO : End of initialization
543 19:43:19.349610 INFO : End of 2D read delay Voltage center optimization
544 19:43:19.369896 INFO : End of 2D read delay Voltage center optimization
545 19:43:19.421956 INFO : End of 2D write delay Voltage center optimization
546 19:43:19.471266 INFO : End of 2D write delay Voltage center optimization
547 19:43:19.476877 INFO : Training has run successfully!
548 19:43:19.477366
549 19:43:19.477832 channel==0
550 19:43:19.482487 RxClkDly_Margin_A0==88 ps 9
551 19:43:19.482975 TxDqDly_Margin_A0==98 ps 10
552 19:43:19.488095 RxClkDly_Margin_A1==88 ps 9
553 19:43:19.488584 TxDqDly_Margin_A1==98 ps 10
554 19:43:19.489038 TrainedVREFDQ_A0==74
555 19:43:19.493646 TrainedVREFDQ_A1==74
556 19:43:19.494130 VrefDac_Margin_A0==25
557 19:43:19.494570 DeviceVref_Margin_A0==40
558 19:43:19.499236 VrefDac_Margin_A1==25
559 19:43:19.499546 DeviceVref_Margin_A1==40
560 19:43:19.499763
561 19:43:19.499971
562 19:43:19.504894 channel==1
563 19:43:19.505435 RxClkDly_Margin_A0==98 ps 10
564 19:43:19.505896 TxDqDly_Margin_A0==98 ps 10
565 19:43:19.510502 RxClkDly_Margin_A1==88 ps 9
566 19:43:19.510993 TxDqDly_Margin_A1==98 ps 10
567 19:43:19.516127 TrainedVREFDQ_A0==76
568 19:43:19.516628 TrainedVREFDQ_A1==78
569 19:43:19.517091 VrefDac_Margin_A0==22
570 19:43:19.521648 DeviceVref_Margin_A0==38
571 19:43:19.522137 VrefDac_Margin_A1==24
572 19:43:19.527269 DeviceVref_Margin_A1==36
573 19:43:19.527768
574 19:43:19.528274 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 19:43:19.532879
576 19:43:19.560888 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
577 19:43:19.561453 2D training succeed
578 19:43:19.566517 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 19:43:19.572070 auto size-- 65535DDR cs0 size: 2048MB
580 19:43:19.572582 DDR cs1 size: 2048MB
581 19:43:19.577660 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 19:43:19.578163 cs0 DataBus test pass
583 19:43:19.583258 cs1 DataBus test pass
584 19:43:19.583764 cs0 AddrBus test pass
585 19:43:19.584259 cs1 AddrBus test pass
586 19:43:19.584712
587 19:43:19.588855 100bdlr_step_size ps== 420
588 19:43:19.589379 result report
589 19:43:19.594524 boot times 0Enable ddr reg access
590 19:43:19.599896 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 19:43:19.613395 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 19:43:20.187054 0.0;M3 CHK:0;cm4_sp_mode 0
593 19:43:20.187759 MVN_1=0x00000000
594 19:43:20.192611 MVN_2=0x00000000
595 19:43:20.198388 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 19:43:20.199017 OPS=0x10
597 19:43:20.199504 ring efuse init
598 19:43:20.200040 chipver efuse init
599 19:43:20.203865 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 19:43:20.209574 [0.018960 Inits done]
601 19:43:20.210118 secure task start!
602 19:43:20.210557 high task start!
603 19:43:20.214015 low task start!
604 19:43:20.214532 run into bl31
605 19:43:20.220683 NOTICE: BL31: v1.3(release):4fc40b1
606 19:43:20.228479 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 19:43:20.229009 NOTICE: BL31: G12A normal boot!
608 19:43:20.253897 NOTICE: BL31: BL33 decompress pass
609 19:43:20.259666 ERROR: Error initializing runtime service opteed_fast
610 19:43:21.492691
611 19:43:21.493345
612 19:43:21.501111 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 19:43:21.501675
614 19:43:21.502150 Model: Libre Computer AML-A311D-CC Alta
615 19:43:21.709482 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 19:43:21.732853 DRAM: 2 GiB (effective 3.8 GiB)
617 19:43:21.875744 Core: 408 devices, 31 uclasses, devicetree: separate
618 19:43:21.881715 WDT: Not starting watchdog@f0d0
619 19:43:21.914043 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 19:43:21.926319 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 19:43:21.931370 ** Bad device specification mmc 0 **
622 19:43:21.941739 Card did not respond to voltage select! : -110
623 19:43:21.949327 ** Bad device specification mmc 0 **
624 19:43:21.949842 Couldn't find partition mmc 0
625 19:43:21.957714 Card did not respond to voltage select! : -110
626 19:43:21.963151 ** Bad device specification mmc 0 **
627 19:43:21.963668 Couldn't find partition mmc 0
628 19:43:21.968220 Error: could not access storage.
629 19:43:22.311816 Net: eth0: ethernet@ff3f0000
630 19:43:22.312518 starting USB...
631 19:43:22.563624 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 19:43:22.564293 Starting the controller
633 19:43:22.570651 USB XHCI 1.10
634 19:43:24.281297 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 19:43:24.281978 bl2_stage_init 0x01
636 19:43:24.282446 bl2_stage_init 0x81
637 19:43:24.287275 hw id: 0x0000 - pwm id 0x01
638 19:43:24.287834 bl2_stage_init 0xc1
639 19:43:24.288362 bl2_stage_init 0x02
640 19:43:24.288816
641 19:43:24.292518 L0:00000000
642 19:43:24.293031 L1:20000703
643 19:43:24.293481 L2:00008067
644 19:43:24.293922 L3:14000000
645 19:43:24.298157 B2:00402000
646 19:43:24.298659 B1:e0f83180
647 19:43:24.299105
648 19:43:24.299545 TE: 58159
649 19:43:24.300012
650 19:43:24.303631 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 19:43:24.304184
652 19:43:24.304641 Board ID = 1
653 19:43:24.309295 Set A53 clk to 24M
654 19:43:24.309804 Set A73 clk to 24M
655 19:43:24.310252 Set clk81 to 24M
656 19:43:24.314921 A53 clk: 1200 MHz
657 19:43:24.315425 A73 clk: 1200 MHz
658 19:43:24.315872 CLK81: 166.6M
659 19:43:24.316361 smccc: 00012ab5
660 19:43:24.320506 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 19:43:24.326027 board id: 1
662 19:43:24.332099 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 19:43:24.342643 fw parse done
664 19:43:24.348598 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 19:43:24.391091 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 19:43:24.402062 PIEI prepare done
667 19:43:24.402625 fastboot data load
668 19:43:24.403083 fastboot data verify
669 19:43:24.407714 verify result: 266
670 19:43:24.413310 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 19:43:24.413850 LPDDR4 probe
672 19:43:24.414309 ddr clk to 1584MHz
673 19:43:24.421425 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 19:43:24.458561
675 19:43:24.459113 dmc_version 0001
676 19:43:24.465247 Check phy result
677 19:43:24.471066 INFO : End of CA training
678 19:43:24.471578 INFO : End of initialization
679 19:43:24.476696 INFO : Training has run successfully!
680 19:43:24.477210 Check phy result
681 19:43:24.482423 INFO : End of initialization
682 19:43:24.482933 INFO : End of read enable training
683 19:43:24.485607 INFO : End of fine write leveling
684 19:43:24.491138 INFO : End of Write leveling coarse delay
685 19:43:24.496766 INFO : Training has run successfully!
686 19:43:24.497275 Check phy result
687 19:43:24.497727 INFO : End of initialization
688 19:43:24.502373 INFO : End of read dq deskew training
689 19:43:24.508006 INFO : End of MPR read delay center optimization
690 19:43:24.508535 INFO : End of write delay center optimization
691 19:43:24.513617 INFO : End of read delay center optimization
692 19:43:24.519140 INFO : End of max read latency training
693 19:43:24.519656 INFO : Training has run successfully!
694 19:43:24.524761 1D training succeed
695 19:43:24.530757 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 19:43:24.578329 Check phy result
697 19:43:24.578892 INFO : End of initialization
698 19:43:24.600911 INFO : End of 2D read delay Voltage center optimization
699 19:43:24.621172 INFO : End of 2D read delay Voltage center optimization
700 19:43:24.673177 INFO : End of 2D write delay Voltage center optimization
701 19:43:24.722583 INFO : End of 2D write delay Voltage center optimization
702 19:43:24.728225 INFO : Training has run successfully!
703 19:43:24.728742
704 19:43:24.729194 channel==0
705 19:43:24.733762 RxClkDly_Margin_A0==88 ps 9
706 19:43:24.734272 TxDqDly_Margin_A0==98 ps 10
707 19:43:24.739438 RxClkDly_Margin_A1==88 ps 9
708 19:43:24.739947 TxDqDly_Margin_A1==98 ps 10
709 19:43:24.740452 TrainedVREFDQ_A0==74
710 19:43:24.744953 TrainedVREFDQ_A1==74
711 19:43:24.745463 VrefDac_Margin_A0==24
712 19:43:24.745913 DeviceVref_Margin_A0==40
713 19:43:24.750533 VrefDac_Margin_A1==24
714 19:43:24.751036 DeviceVref_Margin_A1==40
715 19:43:24.751486
716 19:43:24.751928
717 19:43:24.756170 channel==1
718 19:43:24.756674 RxClkDly_Margin_A0==98 ps 10
719 19:43:24.757121 TxDqDly_Margin_A0==98 ps 10
720 19:43:24.761819 RxClkDly_Margin_A1==98 ps 10
721 19:43:24.762342 TxDqDly_Margin_A1==88 ps 9
722 19:43:24.767499 TrainedVREFDQ_A0==76
723 19:43:24.768056 TrainedVREFDQ_A1==77
724 19:43:24.768523 VrefDac_Margin_A0==22
725 19:43:24.773044 DeviceVref_Margin_A0==38
726 19:43:24.773599 VrefDac_Margin_A1==22
727 19:43:24.779638 DeviceVref_Margin_A1==37
728 19:43:24.780264
729 19:43:24.780741 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 19:43:24.784152
731 19:43:24.812032 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000019 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
732 19:43:24.812705 2D training succeed
733 19:43:24.817651 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 19:43:24.823325 auto size-- 65535DDR cs0 size: 2048MB
735 19:43:24.823839 DDR cs1 size: 2048MB
736 19:43:24.828830 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 19:43:24.829341 cs0 DataBus test pass
738 19:43:24.834387 cs1 DataBus test pass
739 19:43:24.834888 cs0 AddrBus test pass
740 19:43:24.835334 cs1 AddrBus test pass
741 19:43:24.835772
742 19:43:24.840023 100bdlr_step_size ps== 420
743 19:43:24.840543 result report
744 19:43:24.845584 boot times 0Enable ddr reg access
745 19:43:24.851058 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 19:43:24.864494 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 19:43:25.438148 0.0;M3 CHK:0;cm4_sp_mode 0
748 19:43:25.438798 MVN_1=0x00000000
749 19:43:25.443784 MVN_2=0x00000000
750 19:43:25.449454 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 19:43:25.449952 OPS=0x10
752 19:43:25.450396 ring efuse init
753 19:43:25.450826 chipver efuse init
754 19:43:25.455011 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 19:43:25.460529 [0.018961 Inits done]
756 19:43:25.461008 secure task start!
757 19:43:25.461443 high task start!
758 19:43:25.465094 low task start!
759 19:43:25.465561 run into bl31
760 19:43:25.471787 NOTICE: BL31: v1.3(release):4fc40b1
761 19:43:25.479576 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 19:43:25.480086 NOTICE: BL31: G12A normal boot!
763 19:43:25.505076 NOTICE: BL31: BL33 decompress pass
764 19:43:25.510623 ERROR: Error initializing runtime service opteed_fast
765 19:43:26.743645
766 19:43:26.744348
767 19:43:26.751894 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 19:43:26.752435
769 19:43:26.752899 Model: Libre Computer AML-A311D-CC Alta
770 19:43:26.960341 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 19:43:26.983678 DRAM: 2 GiB (effective 3.8 GiB)
772 19:43:27.126679 Core: 408 devices, 31 uclasses, devicetree: separate
773 19:43:27.132572 WDT: Not starting watchdog@f0d0
774 19:43:27.164794 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 19:43:27.177284 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 19:43:27.182316 ** Bad device specification mmc 0 **
777 19:43:27.192598 Card did not respond to voltage select! : -110
778 19:43:27.200237 ** Bad device specification mmc 0 **
779 19:43:27.200728 Couldn't find partition mmc 0
780 19:43:27.208601 Card did not respond to voltage select! : -110
781 19:43:27.214115 ** Bad device specification mmc 0 **
782 19:43:27.214600 Couldn't find partition mmc 0
783 19:43:27.219148 Error: could not access storage.
784 19:43:27.561669 Net: eth0: ethernet@ff3f0000
785 19:43:27.562104 starting USB...
786 19:43:27.813477 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 19:43:27.814121 Starting the controller
788 19:43:27.820440 USB XHCI 1.10
789 19:43:29.981334 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 19:43:29.981984 bl2_stage_init 0x01
791 19:43:29.982451 bl2_stage_init 0x81
792 19:43:29.986897 hw id: 0x0000 - pwm id 0x01
793 19:43:29.987389 bl2_stage_init 0xc1
794 19:43:29.987843 bl2_stage_init 0x02
795 19:43:29.988352
796 19:43:29.992577 L0:00000000
797 19:43:29.993067 L1:20000703
798 19:43:29.993514 L2:00008067
799 19:43:29.993954 L3:14000000
800 19:43:29.998011 B2:00402000
801 19:43:29.998489 B1:e0f83180
802 19:43:29.998935
803 19:43:29.999378 TE: 58124
804 19:43:29.999822
805 19:43:30.003744 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 19:43:30.004267
807 19:43:30.004717 Board ID = 1
808 19:43:30.009317 Set A53 clk to 24M
809 19:43:30.009797 Set A73 clk to 24M
810 19:43:30.010239 Set clk81 to 24M
811 19:43:30.015143 A53 clk: 1200 MHz
812 19:43:30.015643 A73 clk: 1200 MHz
813 19:43:30.016127 CLK81: 166.6M
814 19:43:30.016572 smccc: 00012a92
815 19:43:30.020614 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 19:43:30.026084 board id: 1
817 19:43:30.032163 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 19:43:30.042625 fw parse done
819 19:43:30.048570 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 19:43:30.091106 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 19:43:30.102036 PIEI prepare done
822 19:43:30.102523 fastboot data load
823 19:43:30.102979 fastboot data verify
824 19:43:30.107666 verify result: 266
825 19:43:30.113272 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 19:43:30.113755 LPDDR4 probe
827 19:43:30.114202 ddr clk to 1584MHz
828 19:43:30.121312 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 19:43:30.158533
830 19:43:30.159054 dmc_version 0001
831 19:43:30.165211 Check phy result
832 19:43:30.171067 INFO : End of CA training
833 19:43:30.171548 INFO : End of initialization
834 19:43:30.176659 INFO : Training has run successfully!
835 19:43:30.177143 Check phy result
836 19:43:30.182281 INFO : End of initialization
837 19:43:30.182758 INFO : End of read enable training
838 19:43:30.185606 INFO : End of fine write leveling
839 19:43:30.191126 INFO : End of Write leveling coarse delay
840 19:43:30.196751 INFO : Training has run successfully!
841 19:43:30.197229 Check phy result
842 19:43:30.197673 INFO : End of initialization
843 19:43:30.202344 INFO : End of read dq deskew training
844 19:43:30.208061 INFO : End of MPR read delay center optimization
845 19:43:30.208544 INFO : End of write delay center optimization
846 19:43:30.213492 INFO : End of read delay center optimization
847 19:43:30.219138 INFO : End of max read latency training
848 19:43:30.219607 INFO : Training has run successfully!
849 19:43:30.224759 1D training succeed
850 19:43:30.230685 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 19:43:30.278276 Check phy result
852 19:43:30.278799 INFO : End of initialization
853 19:43:30.300769 INFO : End of 2D read delay Voltage center optimization
854 19:43:30.320839 INFO : End of 2D read delay Voltage center optimization
855 19:43:30.372708 INFO : End of 2D write delay Voltage center optimization
856 19:43:30.421967 INFO : End of 2D write delay Voltage center optimization
857 19:43:30.427517 INFO : Training has run successfully!
858 19:43:30.428054
859 19:43:30.428521 channel==0
860 19:43:30.433077 RxClkDly_Margin_A0==88 ps 9
861 19:43:30.433568 TxDqDly_Margin_A0==98 ps 10
862 19:43:30.436416 RxClkDly_Margin_A1==88 ps 9
863 19:43:30.436906 TxDqDly_Margin_A1==98 ps 10
864 19:43:30.441958 TrainedVREFDQ_A0==74
865 19:43:30.442436 TrainedVREFDQ_A1==74
866 19:43:30.447528 VrefDac_Margin_A0==25
867 19:43:30.448102 DeviceVref_Margin_A0==40
868 19:43:30.448566 VrefDac_Margin_A1==24
869 19:43:30.453158 DeviceVref_Margin_A1==40
870 19:43:30.453677
871 19:43:30.454109
872 19:43:30.454538 channel==1
873 19:43:30.454957 RxClkDly_Margin_A0==98 ps 10
874 19:43:30.458827 TxDqDly_Margin_A0==98 ps 10
875 19:43:30.459302 RxClkDly_Margin_A1==88 ps 9
876 19:43:30.464363 TxDqDly_Margin_A1==88 ps 9
877 19:43:30.464839 TrainedVREFDQ_A0==77
878 19:43:30.465273 TrainedVREFDQ_A1==77
879 19:43:30.470091 VrefDac_Margin_A0==22
880 19:43:30.470563 DeviceVref_Margin_A0==37
881 19:43:30.475595 VrefDac_Margin_A1==24
882 19:43:30.476093 DeviceVref_Margin_A1==37
883 19:43:30.476526
884 19:43:30.481134 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 19:43:30.481597
886 19:43:30.509075 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000018 00000017 00000019 00000018 0000001a 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000018 00000017 dram_vref_reg_value 0x 00000060
887 19:43:30.514613 2D training succeed
888 19:43:30.520260 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 19:43:30.520729 auto size-- 65535DDR cs0 size: 2048MB
890 19:43:30.525887 DDR cs1 size: 2048MB
891 19:43:30.526447 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 19:43:30.531431 cs0 DataBus test pass
893 19:43:30.531896 cs1 DataBus test pass
894 19:43:30.532417 cs0 AddrBus test pass
895 19:43:30.537069 cs1 AddrBus test pass
896 19:43:30.537535
897 19:43:30.537972 100bdlr_step_size ps== 420
898 19:43:30.538408 result report
899 19:43:30.542661 boot times 0Enable ddr reg access
900 19:43:30.550378 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 19:43:30.562843 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 19:43:31.136054 0.0;M3 CHK:0;cm4_sp_mode 0
903 19:43:31.136743 MVN_1=0x00000000
904 19:43:31.141302 MVN_2=0x00000000
905 19:43:31.147095 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 19:43:31.147592 OPS=0x10
907 19:43:31.148088 ring efuse init
908 19:43:31.148580 chipver efuse init
909 19:43:31.152729 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 19:43:31.158294 [0.018961 Inits done]
911 19:43:31.158789 secure task start!
912 19:43:31.159240 high task start!
913 19:43:31.162850 low task start!
914 19:43:31.163331 run into bl31
915 19:43:31.169478 NOTICE: BL31: v1.3(release):4fc40b1
916 19:43:31.177288 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 19:43:31.177782 NOTICE: BL31: G12A normal boot!
918 19:43:31.202611 NOTICE: BL31: BL33 decompress pass
919 19:43:31.208294 ERROR: Error initializing runtime service opteed_fast
920 19:43:32.441157
921 19:43:32.441812
922 19:43:32.449566 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 19:43:32.450098
924 19:43:32.450565 Model: Libre Computer AML-A311D-CC Alta
925 19:43:32.657954 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 19:43:32.681326 DRAM: 2 GiB (effective 3.8 GiB)
927 19:43:32.824349 Core: 408 devices, 31 uclasses, devicetree: separate
928 19:43:32.830280 WDT: Not starting watchdog@f0d0
929 19:43:32.862477 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 19:43:32.874922 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 19:43:32.879896 ** Bad device specification mmc 0 **
932 19:43:32.890270 Card did not respond to voltage select! : -110
933 19:43:32.897886 ** Bad device specification mmc 0 **
934 19:43:32.898382 Couldn't find partition mmc 0
935 19:43:32.906298 Card did not respond to voltage select! : -110
936 19:43:32.911756 ** Bad device specification mmc 0 **
937 19:43:32.912276 Couldn't find partition mmc 0
938 19:43:32.916803 Error: could not access storage.
939 19:43:33.259314 Net: eth0: ethernet@ff3f0000
940 19:43:33.259958 starting USB...
941 19:43:33.511155 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 19:43:33.511805 Starting the controller
943 19:43:33.518039 USB XHCI 1.10
944 19:43:35.381121 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
945 19:43:35.381796 bl2_stage_init 0x01
946 19:43:35.382264 bl2_stage_init 0x81
947 19:43:35.386633 hw id: 0x0000 - pwm id 0x01
948 19:43:35.387129 bl2_stage_init 0xc1
949 19:43:35.387587 bl2_stage_init 0x02
950 19:43:35.388133
951 19:43:35.392240 L0:00000000
952 19:43:35.392719 L1:20000703
953 19:43:35.393169 L2:00008067
954 19:43:35.393610 L3:14000000
955 19:43:35.397838 B2:00402000
956 19:43:35.398309 B1:e0f83180
957 19:43:35.398750
958 19:43:35.399191 TE: 58167
959 19:43:35.399633
960 19:43:35.403415 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
961 19:43:35.403897
962 19:43:35.404389 Board ID = 1
963 19:43:35.409042 Set A53 clk to 24M
964 19:43:35.409521 Set A73 clk to 24M
965 19:43:35.409967 Set clk81 to 24M
966 19:43:35.414637 A53 clk: 1200 MHz
967 19:43:35.415129 A73 clk: 1200 MHz
968 19:43:35.415573 CLK81: 166.6M
969 19:43:35.416044 smccc: 00012abe
970 19:43:35.420221 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
971 19:43:35.425828 board id: 1
972 19:43:35.431689 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
973 19:43:35.442371 fw parse done
974 19:43:35.448416 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
975 19:43:35.490966 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
976 19:43:35.502038 PIEI prepare done
977 19:43:35.502510 fastboot data load
978 19:43:35.502942 fastboot data verify
979 19:43:35.507675 verify result: 266
980 19:43:35.513212 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
981 19:43:35.513679 LPDDR4 probe
982 19:43:35.514103 ddr clk to 1584MHz
983 19:43:35.521347 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
984 19:43:35.558605
985 19:43:35.559172 dmc_version 0001
986 19:43:35.565289 Check phy result
987 19:43:35.570986 INFO : End of CA training
988 19:43:35.571451 INFO : End of initialization
989 19:43:35.576650 INFO : Training has run successfully!
990 19:43:35.577180 Check phy result
991 19:43:35.582299 INFO : End of initialization
992 19:43:35.582774 INFO : End of read enable training
993 19:43:35.585808 INFO : End of fine write leveling
994 19:43:35.591281 INFO : End of Write leveling coarse delay
995 19:43:35.596853 INFO : Training has run successfully!
996 19:43:35.597323 Check phy result
997 19:43:35.597765 INFO : End of initialization
998 19:43:35.602374 INFO : End of read dq deskew training
999 19:43:35.606015 INFO : End of MPR read delay center optimization
1000 19:43:35.611591 INFO : End of write delay center optimization
1001 19:43:35.612096 INFO : End of read delay center optimization
1002 19:43:35.617144 INFO : End of max read latency training
1003 19:43:35.622741 INFO : Training has run successfully!
1004 19:43:35.623211 1D training succeed
1005 19:43:35.630599 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
1006 19:43:35.678169 Check phy result
1007 19:43:35.678689 INFO : End of initialization
1008 19:43:35.699924 INFO : End of 2D read delay Voltage center optimization
1009 19:43:35.720217 INFO : End of 2D read delay Voltage center optimization
1010 19:43:35.772267 INFO : End of 2D write delay Voltage center optimization
1011 19:43:35.821641 INFO : End of 2D write delay Voltage center optimization
1012 19:43:35.827116 INFO : Training has run successfully!
1013 19:43:35.827594
1014 19:43:35.828096 channel==0
1015 19:43:35.832850 RxClkDly_Margin_A0==88 ps 9
1016 19:43:35.833338 TxDqDly_Margin_A0==98 ps 10
1017 19:43:35.838296 RxClkDly_Margin_A1==88 ps 9
1018 19:43:35.838771 TxDqDly_Margin_A1==98 ps 10
1019 19:43:35.839223 TrainedVREFDQ_A0==74
1020 19:43:35.843971 TrainedVREFDQ_A1==74
1021 19:43:35.844483 VrefDac_Margin_A0==25
1022 19:43:35.844933 DeviceVref_Margin_A0==40
1023 19:43:35.849626 VrefDac_Margin_A1==25
1024 19:43:35.850135 DeviceVref_Margin_A1==40
1025 19:43:35.850576
1026 19:43:35.851009
1027 19:43:35.855172 channel==1
1028 19:43:35.855643 RxClkDly_Margin_A0==88 ps 9
1029 19:43:35.856117 TxDqDly_Margin_A0==88 ps 9
1030 19:43:35.860841 RxClkDly_Margin_A1==88 ps 9
1031 19:43:35.861311 TxDqDly_Margin_A1==88 ps 9
1032 19:43:35.866400 TrainedVREFDQ_A0==76
1033 19:43:35.866877 TrainedVREFDQ_A1==77
1034 19:43:35.867324 VrefDac_Margin_A0==22
1035 19:43:35.872008 DeviceVref_Margin_A0==38
1036 19:43:35.872480 VrefDac_Margin_A1==24
1037 19:43:35.877627 DeviceVref_Margin_A1==37
1038 19:43:35.878091
1039 19:43:35.878536 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1040 19:43:35.878972
1041 19:43:35.911195 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
1042 19:43:35.911699 2D training succeed
1043 19:43:35.916879 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1044 19:43:35.922268 auto size-- 65535DDR cs0 size: 2048MB
1045 19:43:35.922741 DDR cs1 size: 2048MB
1046 19:43:35.927823 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1047 19:43:35.928335 cs0 DataBus test pass
1048 19:43:35.933449 cs1 DataBus test pass
1049 19:43:35.933914 cs0 AddrBus test pass
1050 19:43:35.934357 cs1 AddrBus test pass
1051 19:43:35.934793
1052 19:43:35.938983 100bdlr_step_size ps== 420
1053 19:43:35.939458 result report
1054 19:43:35.944724 boot times 0Enable ddr reg access
1055 19:43:35.949793 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1056 19:43:35.963330 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1057 19:43:36.537049 0.0;M3 CHK:0;cm4_sp_mode 0
1058 19:43:36.537735 MVN_1=0x00000000
1059 19:43:36.542372 MVN_2=0x00000000
1060 19:43:36.548131 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1061 19:43:36.548627 OPS=0x10
1062 19:43:36.549084 ring efuse init
1063 19:43:36.549528 chipver efuse init
1064 19:43:36.556389 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1065 19:43:36.556983 [0.018961 Inits done]
1066 19:43:36.564063 secure task start!
1067 19:43:36.564595 high task start!
1068 19:43:36.565060 low task start!
1069 19:43:36.565511 run into bl31
1070 19:43:36.570673 NOTICE: BL31: v1.3(release):4fc40b1
1071 19:43:36.578429 NOTICE: BL31: Built : 15:58:17, May 22 2019
1072 19:43:36.578971 NOTICE: BL31: G12A normal boot!
1073 19:43:36.603840 NOTICE: BL31: BL33 decompress pass
1074 19:43:36.609493 ERROR: Error initializing runtime service opteed_fast
1075 19:43:37.842434
1076 19:43:37.843059
1077 19:43:37.850890 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1078 19:43:37.851439
1079 19:43:37.851907 Model: Libre Computer AML-A311D-CC Alta
1080 19:43:38.059326 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1081 19:43:38.082682 DRAM: 2 GiB (effective 3.8 GiB)
1082 19:43:38.225607 Core: 408 devices, 31 uclasses, devicetree: separate
1083 19:43:38.231491 WDT: Not starting watchdog@f0d0
1084 19:43:38.263760 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1085 19:43:38.276190 Loading Environment from FAT... Card did not respond to voltage select! : -110
1086 19:43:38.281207 ** Bad device specification mmc 0 **
1087 19:43:38.291542 Card did not respond to voltage select! : -110
1088 19:43:38.299175 ** Bad device specification mmc 0 **
1089 19:43:38.299719 Couldn't find partition mmc 0
1090 19:43:38.307511 Card did not respond to voltage select! : -110
1091 19:43:38.313072 ** Bad device specification mmc 0 **
1092 19:43:38.313602 Couldn't find partition mmc 0
1093 19:43:38.318163 Error: could not access storage.
1094 19:43:38.661575 Net: eth0: ethernet@ff3f0000
1095 19:43:38.662194 starting USB...
1096 19:43:38.913411 Bus usb@ff500000: Register 3000140 NbrPorts 3
1097 19:43:38.914000 Starting the controller
1098 19:43:38.920375 USB XHCI 1.10
1099 19:43:40.477563 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1100 19:43:40.485823 scanning usb for storage devices... 0 Storage Device(s) found
1102 19:43:40.537538 Hit any key to stop autoboot: 1
1103 19:43:40.538405 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1104 19:43:40.539234 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1105 19:43:40.539754 Setting prompt string to ['=>']
1106 19:43:40.540351 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1107 19:43:40.553284 0
1108 19:43:40.554269 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1109 19:43:40.554801 Sending with 10 millisecond of delay
1111 19:43:41.689744 => setenv autoload no
1112 19:43:41.700602 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1113 19:43:41.706020 setenv autoload no
1114 19:43:41.706839 Sending with 10 millisecond of delay
1116 19:43:43.504095 => setenv initrd_high 0xffffffff
1117 19:43:43.514948 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1118 19:43:43.515903 setenv initrd_high 0xffffffff
1119 19:43:43.516713 Sending with 10 millisecond of delay
1121 19:43:45.133395 => setenv fdt_high 0xffffffff
1122 19:43:45.144231 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1123 19:43:45.145112 setenv fdt_high 0xffffffff
1124 19:43:45.145867 Sending with 10 millisecond of delay
1126 19:43:45.437791 => dhcp
1127 19:43:45.448555 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1128 19:43:45.449432 dhcp
1129 19:43:45.449905 Speed: 1000, full duplex
1130 19:43:45.450356 BOOTP broadcast 1
1131 19:43:45.603462 DHCP client bound to address 192.168.6.27 (155 ms)
1132 19:43:45.604427 Sending with 10 millisecond of delay
1134 19:43:47.281312 => setenv serverip 192.168.6.2
1135 19:43:47.292168 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1136 19:43:47.293167 setenv serverip 192.168.6.2
1137 19:43:47.293930 Sending with 10 millisecond of delay
1139 19:43:51.018947 => tftpboot 0x01080000 967951/tftp-deploy-fqfej2nx/kernel/uImage
1140 19:43:51.030681 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1141 19:43:51.031605 tftpboot 0x01080000 967951/tftp-deploy-fqfej2nx/kernel/uImage
1142 19:43:51.032084 Speed: 1000, full duplex
1143 19:43:51.032297 Using ethernet@ff3f0000 device
1144 19:43:51.032619 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1145 19:43:51.038180 Filename '967951/tftp-deploy-fqfej2nx/kernel/uImage'.
1146 19:43:51.042079 Load address: 0x1080000
1147 19:43:53.899873 Loading: *################################################## 43.6 MiB
1148 19:43:53.900528 15.2 MiB/s
1149 19:43:53.900957 done
1150 19:43:53.904286 Bytes transferred = 45713984 (2b98a40 hex)
1151 19:43:53.905000 Sending with 10 millisecond of delay
1153 19:43:58.592128 => tftpboot 0x08000000 967951/tftp-deploy-fqfej2nx/ramdisk/ramdisk.cpio.gz.uboot
1154 19:43:58.603148 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1155 19:43:58.604294 tftpboot 0x08000000 967951/tftp-deploy-fqfej2nx/ramdisk/ramdisk.cpio.gz.uboot
1156 19:43:58.604892 Speed: 1000, full duplex
1157 19:43:58.605415 Using ethernet@ff3f0000 device
1158 19:43:58.606019 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1159 19:43:58.617661 Filename '967951/tftp-deploy-fqfej2nx/ramdisk/ramdisk.cpio.gz.uboot'.
1160 19:43:58.618210 Load address: 0x8000000
1161 19:44:03.286085 Loading: *################## UDP wrong checksum 000000ff 0000f308
1162 19:44:03.387862 UDP wrong checksum 000000ff 00007efb
1163 19:44:03.395641 UDP wrong checksum 000000ff 000080b7
1164 19:44:03.457778 UDP wrong checksum 000000ff 00001baa
1165 19:44:05.672673 T ############################### UDP wrong checksum 00000005 000092dc
1166 19:44:10.673536 T UDP wrong checksum 00000005 000092dc
1167 19:44:20.675335 T T UDP wrong checksum 00000005 000092dc
1168 19:44:23.517727 UDP wrong checksum 000000ff 00007af1
1169 19:44:23.558593 UDP wrong checksum 000000ff 00000de4
1170 19:44:40.679316 T T T T UDP wrong checksum 00000005 000092dc
1171 19:44:55.683500 T T
1172 19:44:55.684374 Retry count exceeded; starting again
1174 19:44:55.686244 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1177 19:44:55.688749 end: 2.4 uboot-commands (duration 00:01:52) [common]
1179 19:44:55.690534 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1181 19:44:55.691829 end: 2 uboot-action (duration 00:01:52) [common]
1183 19:44:55.693845 Cleaning after the job
1184 19:44:55.694533 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/967951/tftp-deploy-fqfej2nx/ramdisk
1185 19:44:55.696288 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/967951/tftp-deploy-fqfej2nx/kernel
1186 19:44:55.743240 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/967951/tftp-deploy-fqfej2nx/dtb
1187 19:44:55.744288 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/967951/tftp-deploy-fqfej2nx/nfsrootfs
1188 19:44:55.952539 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/967951/tftp-deploy-fqfej2nx/modules
1189 19:44:55.977441 start: 4.1 power-off (timeout 00:00:30) [common]
1190 19:44:55.978253 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1191 19:44:56.014826 >> OK - accepted request
1192 19:44:56.017177 Returned 0 in 0 seconds
1193 19:44:56.118427 end: 4.1 power-off (duration 00:00:00) [common]
1195 19:44:56.119648 start: 4.2 read-feedback (timeout 00:10:00) [common]
1196 19:44:56.120478 Listened to connection for namespace 'common' for up to 1s
1197 19:44:57.121426 Finalising connection for namespace 'common'
1198 19:44:57.122027 Disconnecting from shell: Finalise
1199 19:44:57.122397 =>
1200 19:44:57.223312 end: 4.2 read-feedback (duration 00:00:01) [common]
1201 19:44:57.224174 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/967951
1202 19:44:59.928946 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/967951
1203 19:44:59.929560 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.