Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 13:49:38.831370 lava-dispatcher, installed at version: 2024.01
2 13:49:38.832163 start: 0 validate
3 13:49:38.832642 Start time: 2024-11-10 13:49:38.832612+00:00 (UTC)
4 13:49:38.833176 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 13:49:38.833702 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 13:49:38.868434 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 13:49:38.868976 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-686-gd5c38c200807%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 13:49:38.901167 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 13:49:38.901766 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-686-gd5c38c200807%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 13:49:38.933616 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 13:49:38.934352 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-686-gd5c38c200807%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
12 13:49:38.978268 validate duration: 0.15
14 13:49:38.979127 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 13:49:38.979462 start: 1.1 download-retry (timeout 00:10:00) [common]
16 13:49:38.979766 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 13:49:38.980373 Not decompressing ramdisk as can be used compressed.
18 13:49:38.980808 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 13:49:38.981047 saving as /var/lib/lava/dispatcher/tmp/970693/tftp-deploy-k0hw4cy2/ramdisk/rootfs.cpio.gz
20 13:49:38.981310 total size: 47897469 (45 MB)
21 13:49:39.021114 progress 0 % (0 MB)
22 13:49:39.052078 progress 5 % (2 MB)
23 13:49:39.082265 progress 10 % (4 MB)
24 13:49:39.112082 progress 15 % (6 MB)
25 13:49:39.142007 progress 20 % (9 MB)
26 13:49:39.171643 progress 25 % (11 MB)
27 13:49:39.201708 progress 30 % (13 MB)
28 13:49:39.231219 progress 35 % (16 MB)
29 13:49:39.260851 progress 40 % (18 MB)
30 13:49:39.290607 progress 45 % (20 MB)
31 13:49:39.320235 progress 50 % (22 MB)
32 13:49:39.349950 progress 55 % (25 MB)
33 13:49:39.379917 progress 60 % (27 MB)
34 13:49:39.409976 progress 65 % (29 MB)
35 13:49:39.439972 progress 70 % (32 MB)
36 13:49:39.469734 progress 75 % (34 MB)
37 13:49:39.500158 progress 80 % (36 MB)
38 13:49:39.532946 progress 85 % (38 MB)
39 13:49:39.564768 progress 90 % (41 MB)
40 13:49:39.594862 progress 95 % (43 MB)
41 13:49:39.623952 progress 100 % (45 MB)
42 13:49:39.624740 45 MB downloaded in 0.64 s (71.00 MB/s)
43 13:49:39.625302 end: 1.1.1 http-download (duration 00:00:01) [common]
45 13:49:39.626181 end: 1.1 download-retry (duration 00:00:01) [common]
46 13:49:39.626475 start: 1.2 download-retry (timeout 00:09:59) [common]
47 13:49:39.626747 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 13:49:39.627242 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-686-gd5c38c200807/arm64/defconfig/gcc-12/kernel/Image
49 13:49:39.627504 saving as /var/lib/lava/dispatcher/tmp/970693/tftp-deploy-k0hw4cy2/kernel/Image
50 13:49:39.627714 total size: 45713920 (43 MB)
51 13:49:39.627923 No compression specified
52 13:49:39.667353 progress 0 % (0 MB)
53 13:49:39.701046 progress 5 % (2 MB)
54 13:49:39.729927 progress 10 % (4 MB)
55 13:49:39.758950 progress 15 % (6 MB)
56 13:49:39.787938 progress 20 % (8 MB)
57 13:49:39.816448 progress 25 % (10 MB)
58 13:49:39.845143 progress 30 % (13 MB)
59 13:49:39.873871 progress 35 % (15 MB)
60 13:49:39.902987 progress 40 % (17 MB)
61 13:49:39.931500 progress 45 % (19 MB)
62 13:49:39.960444 progress 50 % (21 MB)
63 13:49:39.989846 progress 55 % (24 MB)
64 13:49:40.018736 progress 60 % (26 MB)
65 13:49:40.047363 progress 65 % (28 MB)
66 13:49:40.076047 progress 70 % (30 MB)
67 13:49:40.105077 progress 75 % (32 MB)
68 13:49:40.133973 progress 80 % (34 MB)
69 13:49:40.162385 progress 85 % (37 MB)
70 13:49:40.191450 progress 90 % (39 MB)
71 13:49:40.220032 progress 95 % (41 MB)
72 13:49:40.247846 progress 100 % (43 MB)
73 13:49:40.248400 43 MB downloaded in 0.62 s (70.24 MB/s)
74 13:49:40.248882 end: 1.2.1 http-download (duration 00:00:01) [common]
76 13:49:40.249704 end: 1.2 download-retry (duration 00:00:01) [common]
77 13:49:40.249975 start: 1.3 download-retry (timeout 00:09:59) [common]
78 13:49:40.250238 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 13:49:40.250705 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-686-gd5c38c200807/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
80 13:49:40.250974 saving as /var/lib/lava/dispatcher/tmp/970693/tftp-deploy-k0hw4cy2/dtb/meson-g12b-a311d-libretech-cc.dtb
81 13:49:40.251182 total size: 54703 (0 MB)
82 13:49:40.251390 No compression specified
83 13:49:40.289441 progress 59 % (0 MB)
84 13:49:40.290344 progress 100 % (0 MB)
85 13:49:40.290914 0 MB downloaded in 0.04 s (1.31 MB/s)
86 13:49:40.291427 end: 1.3.1 http-download (duration 00:00:00) [common]
88 13:49:40.292336 end: 1.3 download-retry (duration 00:00:00) [common]
89 13:49:40.292610 start: 1.4 download-retry (timeout 00:09:59) [common]
90 13:49:40.292875 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 13:49:40.293363 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-686-gd5c38c200807/arm64/defconfig/gcc-12/modules.tar.xz
92 13:49:40.293616 saving as /var/lib/lava/dispatcher/tmp/970693/tftp-deploy-k0hw4cy2/modules/modules.tar
93 13:49:40.293859 total size: 11611892 (11 MB)
94 13:49:40.294080 Using unxz to decompress xz
95 13:49:40.334814 progress 0 % (0 MB)
96 13:49:40.404149 progress 5 % (0 MB)
97 13:49:40.482114 progress 10 % (1 MB)
98 13:49:40.582843 progress 15 % (1 MB)
99 13:49:40.676329 progress 20 % (2 MB)
100 13:49:40.756311 progress 25 % (2 MB)
101 13:49:40.832888 progress 30 % (3 MB)
102 13:49:40.913100 progress 35 % (3 MB)
103 13:49:40.987590 progress 40 % (4 MB)
104 13:49:41.067424 progress 45 % (5 MB)
105 13:49:41.151626 progress 50 % (5 MB)
106 13:49:41.229574 progress 55 % (6 MB)
107 13:49:41.316260 progress 60 % (6 MB)
108 13:49:41.397731 progress 65 % (7 MB)
109 13:49:41.479685 progress 70 % (7 MB)
110 13:49:41.559362 progress 75 % (8 MB)
111 13:49:41.644110 progress 80 % (8 MB)
112 13:49:41.725122 progress 85 % (9 MB)
113 13:49:41.804854 progress 90 % (9 MB)
114 13:49:41.888920 progress 95 % (10 MB)
115 13:49:41.967348 progress 100 % (11 MB)
116 13:49:41.980140 11 MB downloaded in 1.69 s (6.57 MB/s)
117 13:49:41.981066 end: 1.4.1 http-download (duration 00:00:02) [common]
119 13:49:41.982640 end: 1.4 download-retry (duration 00:00:02) [common]
120 13:49:41.983160 start: 1.5 prepare-tftp-overlay (timeout 00:09:57) [common]
121 13:49:41.983669 start: 1.5.1 extract-nfsrootfs (timeout 00:09:57) [common]
122 13:49:41.984271 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 13:49:41.984777 start: 1.5.2 lava-overlay (timeout 00:09:57) [common]
124 13:49:41.985773 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd
125 13:49:41.986626 makedir: /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin
126 13:49:41.987291 makedir: /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/tests
127 13:49:41.987904 makedir: /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/results
128 13:49:41.988561 Creating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin/lava-add-keys
129 13:49:41.989516 Creating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin/lava-add-sources
130 13:49:41.990428 Creating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin/lava-background-process-start
131 13:49:41.991350 Creating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin/lava-background-process-stop
132 13:49:41.992342 Creating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin/lava-common-functions
133 13:49:41.993253 Creating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin/lava-echo-ipv4
134 13:49:41.994137 Creating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin/lava-install-packages
135 13:49:41.995010 Creating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin/lava-installed-packages
136 13:49:41.995883 Creating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin/lava-os-build
137 13:49:41.996806 Creating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin/lava-probe-channel
138 13:49:41.997703 Creating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin/lava-probe-ip
139 13:49:41.998589 Creating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin/lava-target-ip
140 13:49:41.999456 Creating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin/lava-target-mac
141 13:49:42.000374 Creating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin/lava-target-storage
142 13:49:42.001275 Creating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin/lava-test-case
143 13:49:42.002262 Creating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin/lava-test-event
144 13:49:42.003149 Creating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin/lava-test-feedback
145 13:49:42.004057 Creating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin/lava-test-raise
146 13:49:42.004965 Creating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin/lava-test-reference
147 13:49:42.005864 Creating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin/lava-test-runner
148 13:49:42.006743 Creating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin/lava-test-set
149 13:49:42.007616 Creating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin/lava-test-shell
150 13:49:42.008565 Updating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin/lava-install-packages (oe)
151 13:49:42.009521 Updating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/bin/lava-installed-packages (oe)
152 13:49:42.010339 Creating /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/environment
153 13:49:42.011043 LAVA metadata
154 13:49:42.011521 - LAVA_JOB_ID=970693
155 13:49:42.011943 - LAVA_DISPATCHER_IP=192.168.6.2
156 13:49:42.012721 start: 1.5.2.1 ssh-authorize (timeout 00:09:57) [common]
157 13:49:42.014522 end: 1.5.2.1 ssh-authorize (duration 00:00:00) [common]
158 13:49:42.015118 start: 1.5.2.2 lava-vland-overlay (timeout 00:09:57) [common]
159 13:49:42.015528 skipped lava-vland-overlay
160 13:49:42.016038 end: 1.5.2.2 lava-vland-overlay (duration 00:00:00) [common]
161 13:49:42.016553 start: 1.5.2.3 lava-multinode-overlay (timeout 00:09:57) [common]
162 13:49:42.016978 skipped lava-multinode-overlay
163 13:49:42.017461 end: 1.5.2.3 lava-multinode-overlay (duration 00:00:00) [common]
164 13:49:42.017959 start: 1.5.2.4 test-definition (timeout 00:09:57) [common]
165 13:49:42.018430 Loading test definitions
166 13:49:42.018975 start: 1.5.2.4.1 inline-repo-action (timeout 00:09:57) [common]
167 13:49:42.019410 Using /lava-970693 at stage 0
168 13:49:42.020972 uuid=970693_1.5.2.4.1 testdef=None
169 13:49:42.021310 end: 1.5.2.4.1 inline-repo-action (duration 00:00:00) [common]
170 13:49:42.021584 start: 1.5.2.4.2 test-overlay (timeout 00:09:57) [common]
171 13:49:42.023332 end: 1.5.2.4.2 test-overlay (duration 00:00:00) [common]
173 13:49:42.024177 start: 1.5.2.4.3 test-install-overlay (timeout 00:09:57) [common]
174 13:49:42.026376 end: 1.5.2.4.3 test-install-overlay (duration 00:00:00) [common]
176 13:49:42.027249 start: 1.5.2.4.4 test-runscript-overlay (timeout 00:09:57) [common]
177 13:49:42.029378 runner path: /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/0/tests/0_igt-gpu-panfrost test_uuid 970693_1.5.2.4.1
178 13:49:42.029956 end: 1.5.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
180 13:49:42.030764 Creating lava-test-runner.conf files
181 13:49:42.030971 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/970693/lava-overlay-1448b2vd/lava-970693/0 for stage 0
182 13:49:42.031315 - 0_igt-gpu-panfrost
183 13:49:42.031665 end: 1.5.2.4 test-definition (duration 00:00:00) [common]
184 13:49:42.031944 start: 1.5.2.5 compress-overlay (timeout 00:09:57) [common]
185 13:49:42.055592 end: 1.5.2.5 compress-overlay (duration 00:00:00) [common]
186 13:49:42.056014 start: 1.5.2.6 persistent-nfs-overlay (timeout 00:09:57) [common]
187 13:49:42.056287 end: 1.5.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
188 13:49:42.056557 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
189 13:49:42.056822 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:57) [common]
190 13:49:49.001632 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:07) [common]
191 13:49:49.002101 start: 1.5.4 extract-modules (timeout 00:09:50) [common]
192 13:49:49.002348 extracting modules file /var/lib/lava/dispatcher/tmp/970693/tftp-deploy-k0hw4cy2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/970693/extract-overlay-ramdisk-z9bdjo5h/ramdisk
193 13:49:50.415286 end: 1.5.4 extract-modules (duration 00:00:01) [common]
194 13:49:50.415769 start: 1.5.5 apply-overlay-tftp (timeout 00:09:49) [common]
195 13:49:50.416073 [common] Applying overlay /var/lib/lava/dispatcher/tmp/970693/compress-overlay-pem4bdyu/overlay-1.5.2.5.tar.gz to ramdisk
196 13:49:50.416294 [common] Applying overlay /var/lib/lava/dispatcher/tmp/970693/compress-overlay-pem4bdyu/overlay-1.5.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/970693/extract-overlay-ramdisk-z9bdjo5h/ramdisk
197 13:49:50.446079 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
198 13:49:50.446456 start: 1.5.6 prepare-kernel (timeout 00:09:49) [common]
199 13:49:50.446728 start: 1.5.6.1 uboot-prepare-kernel (timeout 00:09:49) [common]
200 13:49:50.446957 Converting downloaded kernel to a uImage
201 13:49:50.447259 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/970693/tftp-deploy-k0hw4cy2/kernel/Image /var/lib/lava/dispatcher/tmp/970693/tftp-deploy-k0hw4cy2/kernel/uImage
202 13:49:50.928034 output: Image Name:
203 13:49:50.928449 output: Created: Sun Nov 10 13:49:50 2024
204 13:49:50.928656 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
205 13:49:50.928861 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
206 13:49:50.929063 output: Load Address: 01080000
207 13:49:50.929262 output: Entry Point: 01080000
208 13:49:50.929460 output:
209 13:49:50.929791 end: 1.5.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
210 13:49:50.930053 end: 1.5.6 prepare-kernel (duration 00:00:00) [common]
211 13:49:50.930319 start: 1.5.7 configure-preseed-file (timeout 00:09:48) [common]
212 13:49:50.930571 end: 1.5.7 configure-preseed-file (duration 00:00:00) [common]
213 13:49:50.930825 start: 1.5.8 compress-ramdisk (timeout 00:09:48) [common]
214 13:49:50.931086 Building ramdisk /var/lib/lava/dispatcher/tmp/970693/extract-overlay-ramdisk-z9bdjo5h/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/970693/extract-overlay-ramdisk-z9bdjo5h/ramdisk
215 13:49:58.094672 >> 502414 blocks
216 13:50:18.905564 Adding RAMdisk u-boot header.
217 13:50:18.905994 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/970693/extract-overlay-ramdisk-z9bdjo5h/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/970693/extract-overlay-ramdisk-z9bdjo5h/ramdisk.cpio.gz.uboot
218 13:50:19.587157 output: Image Name:
219 13:50:19.587828 output: Created: Sun Nov 10 13:50:18 2024
220 13:50:19.588363 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
221 13:50:19.588831 output: Data Size: 65715481 Bytes = 64175.27 KiB = 62.67 MiB
222 13:50:19.589281 output: Load Address: 00000000
223 13:50:19.589726 output: Entry Point: 00000000
224 13:50:19.590171 output:
225 13:50:19.591230 rename /var/lib/lava/dispatcher/tmp/970693/extract-overlay-ramdisk-z9bdjo5h/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/970693/tftp-deploy-k0hw4cy2/ramdisk/ramdisk.cpio.gz.uboot
226 13:50:19.592267 end: 1.5.8 compress-ramdisk (duration 00:00:29) [common]
227 13:50:19.593017 end: 1.5 prepare-tftp-overlay (duration 00:00:38) [common]
228 13:50:19.593633 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:19) [common]
229 13:50:19.594140 No LXC device requested
230 13:50:19.594700 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
231 13:50:19.595266 start: 1.7 deploy-device-env (timeout 00:09:19) [common]
232 13:50:19.595818 end: 1.7 deploy-device-env (duration 00:00:00) [common]
233 13:50:19.596311 Checking files for TFTP limit of 4294967296 bytes.
234 13:50:19.599328 end: 1 tftp-deploy (duration 00:00:41) [common]
235 13:50:19.599972 start: 2 uboot-action (timeout 00:05:00) [common]
236 13:50:19.600650 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
237 13:50:19.601224 end: 2.1 uboot-from-media (duration 00:00:00) [common]
238 13:50:19.602009 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
239 13:50:19.602636 Using kernel file from prepare-kernel: 970693/tftp-deploy-k0hw4cy2/kernel/uImage
240 13:50:19.603344 substitutions:
241 13:50:19.603806 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
242 13:50:19.604299 - {DTB_ADDR}: 0x01070000
243 13:50:19.604752 - {DTB}: 970693/tftp-deploy-k0hw4cy2/dtb/meson-g12b-a311d-libretech-cc.dtb
244 13:50:19.605202 - {INITRD}: 970693/tftp-deploy-k0hw4cy2/ramdisk/ramdisk.cpio.gz.uboot
245 13:50:19.605645 - {KERNEL_ADDR}: 0x01080000
246 13:50:19.606084 - {KERNEL}: 970693/tftp-deploy-k0hw4cy2/kernel/uImage
247 13:50:19.606525 - {LAVA_MAC}: None
248 13:50:19.607007 - {PRESEED_CONFIG}: None
249 13:50:19.607451 - {PRESEED_LOCAL}: None
250 13:50:19.607890 - {RAMDISK_ADDR}: 0x08000000
251 13:50:19.608357 - {RAMDISK}: 970693/tftp-deploy-k0hw4cy2/ramdisk/ramdisk.cpio.gz.uboot
252 13:50:19.608801 - {ROOT_PART}: None
253 13:50:19.609236 - {ROOT}: None
254 13:50:19.609672 - {SERVER_IP}: 192.168.6.2
255 13:50:19.610112 - {TEE_ADDR}: 0x83000000
256 13:50:19.610547 - {TEE}: None
257 13:50:19.610981 Parsed boot commands:
258 13:50:19.611407 - setenv autoload no
259 13:50:19.611839 - setenv initrd_high 0xffffffff
260 13:50:19.612302 - setenv fdt_high 0xffffffff
261 13:50:19.612734 - dhcp
262 13:50:19.613170 - setenv serverip 192.168.6.2
263 13:50:19.613600 - tftpboot 0x01080000 970693/tftp-deploy-k0hw4cy2/kernel/uImage
264 13:50:19.614033 - tftpboot 0x08000000 970693/tftp-deploy-k0hw4cy2/ramdisk/ramdisk.cpio.gz.uboot
265 13:50:19.614467 - tftpboot 0x01070000 970693/tftp-deploy-k0hw4cy2/dtb/meson-g12b-a311d-libretech-cc.dtb
266 13:50:19.614901 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/ram0 console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
267 13:50:19.615338 - bootm 0x01080000 0x08000000 0x01070000
268 13:50:19.615883 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
270 13:50:19.617738 start: 2.3 connect-device (timeout 00:05:00) [common]
271 13:50:19.618239 [common] connect-device Connecting to device using 'telnet conserv1 3007'
272 13:50:19.633537 Setting prompt string to ['lava-test: # ']
273 13:50:19.635149 end: 2.3 connect-device (duration 00:00:00) [common]
274 13:50:19.635834 start: 2.4 uboot-commands (timeout 00:05:00) [common]
275 13:50:19.636531 start: 2.4.1 reset-device (timeout 00:05:00) [common]
276 13:50:19.637140 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
277 13:50:19.638430 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
278 13:50:19.673067 >> OK - accepted request
279 13:50:19.675099 Returned 0 in 0 seconds
280 13:50:19.776333 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
282 13:50:19.778090 end: 2.4.1 reset-device (duration 00:00:00) [common]
283 13:50:19.778720 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
284 13:50:19.779273 Setting prompt string to ['Hit any key to stop autoboot']
285 13:50:19.779774 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
286 13:50:19.781531 Trying 192.168.56.21...
287 13:50:19.782053 Connected to conserv1.
288 13:50:19.782516 Escape character is '^]'.
289 13:50:19.782978
290 13:50:19.783448 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [] (Debian GNU/Linux)
291 13:50:19.783923
292 13:50:31.107958 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
293 13:50:31.108679 bl2_stage_init 0x01
294 13:50:31.109181 bl2_stage_init 0x81
295 13:50:31.113457 hw id: 0x0000 - pwm id 0x01
296 13:50:31.114011 bl2_stage_init 0xc1
297 13:50:31.114464 bl2_stage_init 0x02
298 13:50:31.114900
299 13:50:31.119018 L0:00000000
300 13:50:31.119495 L1:20000703
301 13:50:31.119923 L2:00008067
302 13:50:31.120390 L3:14000000
303 13:50:31.121933 B2:00402000
304 13:50:31.122389 B1:e0f83180
305 13:50:31.122815
306 13:50:31.123241 TE: 58124
307 13:50:31.123665
308 13:50:31.133058 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
309 13:50:31.133527
310 13:50:31.133957 Board ID = 1
311 13:50:31.134379 Set A53 clk to 24M
312 13:50:31.134797 Set A73 clk to 24M
313 13:50:31.138688 Set clk81 to 24M
314 13:50:31.139142 A53 clk: 1200 MHz
315 13:50:31.139567 A73 clk: 1200 MHz
316 13:50:31.142128 CLK81: 166.6M
317 13:50:31.142579 smccc: 00012a92
318 13:50:31.147689 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
319 13:50:31.153298 board id: 1
320 13:50:31.158663 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
321 13:50:31.169035 fw parse done
322 13:50:31.174992 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
323 13:50:31.217621 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
324 13:50:31.228545 PIEI prepare done
325 13:50:31.228996 fastboot data load
326 13:50:31.229427 fastboot data verify
327 13:50:31.234200 verify result: 266
328 13:50:31.239698 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
329 13:50:31.240241 LPDDR4 probe
330 13:50:31.240684 ddr clk to 1584MHz
331 13:50:31.247698 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
332 13:50:31.284970
333 13:50:31.285451 dmc_version 0001
334 13:50:31.291762 Check phy result
335 13:50:31.297473 INFO : End of CA training
336 13:50:31.297970 INFO : End of initialization
337 13:50:31.303210 INFO : Training has run successfully!
338 13:50:31.303675 Check phy result
339 13:50:31.308760 INFO : End of initialization
340 13:50:31.309299 INFO : End of read enable training
341 13:50:31.314385 INFO : End of fine write leveling
342 13:50:31.319954 INFO : End of Write leveling coarse delay
343 13:50:31.320456 INFO : Training has run successfully!
344 13:50:31.320904 Check phy result
345 13:50:31.325508 INFO : End of initialization
346 13:50:31.325972 INFO : End of read dq deskew training
347 13:50:31.331225 INFO : End of MPR read delay center optimization
348 13:50:31.336717 INFO : End of write delay center optimization
349 13:50:31.342341 INFO : End of read delay center optimization
350 13:50:31.342888 INFO : End of max read latency training
351 13:50:31.348097 INFO : Training has run successfully!
352 13:50:31.348590 1D training succeed
353 13:50:31.356341 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
354 13:50:31.404702 Check phy result
355 13:50:31.405199 INFO : End of initialization
356 13:50:31.425945 INFO : End of 2D read delay Voltage center optimization
357 13:50:31.446675 INFO : End of 2D read delay Voltage center optimization
358 13:50:31.498706 INFO : End of 2D write delay Voltage center optimization
359 13:50:31.548141 INFO : End of 2D write delay Voltage center optimization
360 13:50:31.553594 INFO : Training has run successfully!
361 13:50:31.554077
362 13:50:31.554528 channel==0
363 13:50:31.559205 RxClkDly_Margin_A0==88 ps 9
364 13:50:31.559671 TxDqDly_Margin_A0==98 ps 10
365 13:50:31.564756 RxClkDly_Margin_A1==88 ps 9
366 13:50:31.565227 TxDqDly_Margin_A1==98 ps 10
367 13:50:31.565671 TrainedVREFDQ_A0==74
368 13:50:31.570384 TrainedVREFDQ_A1==74
369 13:50:31.570865 VrefDac_Margin_A0==25
370 13:50:31.571296 DeviceVref_Margin_A0==40
371 13:50:31.575934 VrefDac_Margin_A1==25
372 13:50:31.576423 DeviceVref_Margin_A1==40
373 13:50:31.576863
374 13:50:31.577307
375 13:50:31.581539 channel==1
376 13:50:31.582003 RxClkDly_Margin_A0==98 ps 10
377 13:50:31.582441 TxDqDly_Margin_A0==88 ps 9
378 13:50:31.587234 RxClkDly_Margin_A1==98 ps 10
379 13:50:31.587720 TxDqDly_Margin_A1==88 ps 9
380 13:50:31.592752 TrainedVREFDQ_A0==76
381 13:50:31.593222 TrainedVREFDQ_A1==77
382 13:50:31.593663 VrefDac_Margin_A0==22
383 13:50:31.598391 DeviceVref_Margin_A0==38
384 13:50:31.598854 VrefDac_Margin_A1==22
385 13:50:31.603955 DeviceVref_Margin_A1==37
386 13:50:31.604445
387 13:50:31.604883 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
388 13:50:31.605317
389 13:50:31.637631 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000018 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000016 00000018 00000017 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
390 13:50:31.638214 2D training succeed
391 13:50:31.643236 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
392 13:50:31.648709 auto size-- 65535DDR cs0 size: 2048MB
393 13:50:31.649173 DDR cs1 size: 2048MB
394 13:50:31.654398 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
395 13:50:31.654860 cs0 DataBus test pass
396 13:50:31.660034 cs1 DataBus test pass
397 13:50:31.660511 cs0 AddrBus test pass
398 13:50:31.660952 cs1 AddrBus test pass
399 13:50:31.661388
400 13:50:31.665554 100bdlr_step_size ps== 420
401 13:50:31.666027 result report
402 13:50:31.671224 boot times 0Enable ddr reg access
403 13:50:31.676500 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
404 13:50:31.690003 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
405 13:50:32.263842 0.0;M3 CHK:0;cm4_sp_mode 0
406 13:50:32.264544 MVN_1=0x00000000
407 13:50:32.269301 MVN_2=0x00000000
408 13:50:32.275046 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
409 13:50:32.275524 OPS=0x10
410 13:50:32.275972 ring efuse init
411 13:50:32.276453 chipver efuse init
412 13:50:32.280546 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
413 13:50:32.286301 [0.018961 Inits done]
414 13:50:32.286770 secure task start!
415 13:50:32.287208 high task start!
416 13:50:32.289796 low task start!
417 13:50:32.290262 run into bl31
418 13:50:32.297472 NOTICE: BL31: v1.3(release):4fc40b1
419 13:50:32.305289 NOTICE: BL31: Built : 15:58:17, May 22 2019
420 13:50:32.305777 NOTICE: BL31: G12A normal boot!
421 13:50:32.331119 NOTICE: BL31: BL33 decompress pass
422 13:50:32.336789 ERROR: Error initializing runtime service opteed_fast
423 13:50:33.569737
424 13:50:33.570191
425 13:50:33.578251 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
426 13:50:33.578845
427 13:50:33.579206 Model: Libre Computer AML-A311D-CC Alta
428 13:50:33.786599 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
429 13:50:33.809920 DRAM: 2 GiB (effective 3.8 GiB)
430 13:50:33.953014 Core: 408 devices, 31 uclasses, devicetree: separate
431 13:50:33.958864 WDT: Not starting watchdog@f0d0
432 13:50:33.991117 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
433 13:50:34.003562 Loading Environment from FAT... Card did not respond to voltage select! : -110
434 13:50:34.008665 ** Bad device specification mmc 0 **
435 13:50:34.018869 Card did not respond to voltage select! : -110
436 13:50:34.026581 ** Bad device specification mmc 0 **
437 13:50:34.026937 Couldn't find partition mmc 0
438 13:50:34.034867 Card did not respond to voltage select! : -110
439 13:50:34.040386 ** Bad device specification mmc 0 **
440 13:50:34.040691 Couldn't find partition mmc 0
441 13:50:34.045388 Error: could not access storage.
442 13:50:35.308427 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.�!,K��х��}���с0x01
443 13:50:35.309021 bl2_stage_init 0x81
444 13:50:35.313985 hw id: 0x0000 - pwm id 0x01
445 13:50:35.314303 bl2_stage_init 0xc1
446 13:50:35.314515 bl2_stage_init 0x02
447 13:50:35.314717
448 13:50:35.319584 L0:00000000
449 13:50:35.319889 L1:20000703
450 13:50:35.320133 L2:00008067
451 13:50:35.320342 L3:14000000
452 13:50:35.320560 B2:00402000
453 13:50:35.325185 B1:e0f83180
454 13:50:35.325471
455 13:50:35.325680 TE: 58150
456 13:50:35.325895
457 13:50:35.330792 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
458 13:50:35.331186
459 13:50:35.331508 Board ID = 1
460 13:50:35.336377 Set A53 clk to 24M
461 13:50:35.336653 Set A73 clk to 24M
462 13:50:35.336859 Set clk81 to 24M
463 13:50:35.341959 A53 clk: 1200 MHz
464 13:50:35.342362 A73 clk: 1200 MHz
465 13:50:35.342691 CLK81: 166.6M
466 13:50:35.343000 smccc: 00012aac
467 13:50:35.347575 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
468 13:50:35.353159 board id: 1
469 13:50:35.358958 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
470 13:50:35.369641 fw parse done
471 13:50:35.375586 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
472 13:50:35.418215 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
473 13:50:35.429119 PIEI prepare done
474 13:50:35.429402 fastboot data load
475 13:50:35.429605 fastboot data verify
476 13:50:35.434759 verify result: 266
477 13:50:35.440300 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
478 13:50:35.440679 LPDDR4 probe
479 13:50:35.440901 ddr clk to 1584MHz
480 13:50:35.448316 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
481 13:50:35.485640
482 13:50:35.485940 dmc_version 0001
483 13:50:35.492216 Check phy result
484 13:50:35.498087 INFO : End of CA training
485 13:50:35.498376 INFO : End of initialization
486 13:50:35.503776 INFO : Training has run successfully!
487 13:50:35.504085 Check phy result
488 13:50:35.509301 INFO : End of initialization
489 13:50:35.509585 INFO : End of read enable training
490 13:50:35.514920 INFO : End of fine write leveling
491 13:50:35.520513 INFO : End of Write leveling coarse delay
492 13:50:35.520785 INFO : Training has run successfully!
493 13:50:35.520986 Check phy result
494 13:50:35.526337 INFO : End of initialization
495 13:50:35.526897 INFO : End of read dq deskew training
496 13:50:35.531771 INFO : End of MPR read delay center optimization
497 13:50:35.537278 INFO : End of write delay center optimization
498 13:50:35.542872 INFO : End of read delay center optimization
499 13:50:35.543354 INFO : End of max read latency training
500 13:50:35.548548 INFO : Training has run successfully!
501 13:50:35.549036 1D training succeed
502 13:50:35.557701 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
503 13:50:35.605305 Check phy result
504 13:50:35.605799 INFO : End of initialization
505 13:50:35.627802 INFO : End of 2D read delay Voltage center optimization
506 13:50:35.647247 INFO : End of 2D read delay Voltage center optimization
507 13:50:35.699291 INFO : End of 2D write delay Voltage center optimization
508 13:50:35.748589 INFO : End of 2D write delay Voltage center optimization
509 13:50:35.754167 INFO : Training has run successfully!
510 13:50:35.754652
511 13:50:35.755097 channel==0
512 13:50:35.759749 RxClkDly_Margin_A0==88 ps 9
513 13:50:35.760292 TxDqDly_Margin_A0==98 ps 10
514 13:50:35.765346 RxClkDly_Margin_A1==88 ps 9
515 13:50:35.765816 TxDqDly_Margin_A1==98 ps 10
516 13:50:35.766253 TrainedVREFDQ_A0==74
517 13:50:35.770962 TrainedVREFDQ_A1==74
518 13:50:35.771448 VrefDac_Margin_A0==25
519 13:50:35.771880 DeviceVref_Margin_A0==40
520 13:50:35.776562 VrefDac_Margin_A1==25
521 13:50:35.777034 DeviceVref_Margin_A1==40
522 13:50:35.777465
523 13:50:35.777894
524 13:50:35.782171 channel==1
525 13:50:35.782635 RxClkDly_Margin_A0==98 ps 10
526 13:50:35.783063 TxDqDly_Margin_A0==88 ps 9
527 13:50:35.787793 RxClkDly_Margin_A1==88 ps 9
528 13:50:35.788298 TxDqDly_Margin_A1==88 ps 9
529 13:50:35.793373 TrainedVREFDQ_A0==76
530 13:50:35.793842 TrainedVREFDQ_A1==77
531 13:50:35.794269 VrefDac_Margin_A0==22
532 13:50:35.798958 DeviceVref_Margin_A0==38
533 13:50:35.799418 VrefDac_Margin_A1==24
534 13:50:35.804564 DeviceVref_Margin_A1==37
535 13:50:35.805022
536 13:50:35.805452 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
537 13:50:35.805877
538 13:50:35.838174 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000016 00000017 00000019 00000018 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
539 13:50:35.838713 2D training succeed
540 13:50:35.843770 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
541 13:50:35.849355 auto size-- 65535DDR cs0 size: 2048MB
542 13:50:35.849839 DDR cs1 size: 2048MB
543 13:50:35.854978 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
544 13:50:35.855448 cs0 DataBus test pass
545 13:50:35.860588 cs1 DataBus test pass
546 13:50:35.861060 cs0 AddrBus test pass
547 13:50:35.861485 cs1 AddrBus test pass
548 13:50:35.861907
549 13:50:35.866138 100bdlr_step_size ps== 420
550 13:50:35.866618 result report
551 13:50:35.871766 boot times 0Enable ddr reg access
552 13:50:35.877022 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
553 13:50:35.890630 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
554 13:50:36.464388 0.0;M3 CHK:0;cm4_sp_mode 0
555 13:50:36.465019 MVN_1=0x00000000
556 13:50:36.470032 MVN_2=0x00000000
557 13:50:36.475684 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
558 13:50:36.476298 OPS=0x10
559 13:50:36.476761 ring efuse init
560 13:50:36.477246 chipver efuse init
561 13:50:36.483972 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
562 13:50:36.484560 [0.018960 Inits done]
563 13:50:36.491512 secure task start!
564 13:50:36.492096 high task start!
565 13:50:36.492531 low task start!
566 13:50:36.492952 run into bl31
567 13:50:36.498057 NOTICE: BL31: v1.3(release):4fc40b1
568 13:50:36.505878 NOTICE: BL31: Built : 15:58:17, May 22 2019
569 13:50:36.506363 NOTICE: BL31: G12A normal boot!
570 13:50:36.531308 NOTICE: BL31: BL33 decompress pass
571 13:50:36.536857 ERROR: Error initializing runtime service opteed_fast
572 13:50:37.769854
573 13:50:37.770469
574 13:50:37.778349 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
575 13:50:37.778843
576 13:50:37.779295 Model: Libre Computer AML-A311D-CC Alta
577 13:50:37.986669 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
578 13:50:38.010081 DRAM: 2 GiB (effective 3.8 GiB)
579 13:50:38.153081 Core: 408 devices, 31 uclasses, devicetree: separate
580 13:50:38.158877 WDT: Not starting watchdog@f0d0
581 13:50:38.191297 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
582 13:50:38.203634 Loading Environment from FAT... Card did not respond to voltage select! : -110
583 13:50:38.207856 ** Bad device specification mmc 0 **
584 13:50:38.218931 Card did not respond to voltage select! : -110
585 13:50:38.226565 ** Bad device specification mmc 0 **
586 13:50:38.227075 Couldn't find partition mmc 0
587 13:50:38.234964 Card did not respond to voltage select! : -110
588 13:50:38.240498 ** Bad device specification mmc 0 **
589 13:50:38.240983 Couldn't find partition mmc 0
590 13:50:38.246411 Error: could not access storage.
591 13:50:38.588081 Net: eth0: ethernet@ff3f0000
592 13:50:38.588717 starting USB...
593 13:50:38.840017 Bus usb@ff500000: Register 3000140 NbrPorts 3
594 13:50:38.840602 Starting the controller
595 13:50:38.846694 USB XHCI 1.10
596 13:50:40.557388 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
597 13:50:40.558057 bl2_stage_init 0x01
598 13:50:40.558532 bl2_stage_init 0x81
599 13:50:40.563157 hw id: 0x0000 - pwm id 0x01
600 13:50:40.563669 bl2_stage_init 0xc1
601 13:50:40.564174 bl2_stage_init 0x02
602 13:50:40.564623
603 13:50:40.568426 L0:00000000
604 13:50:40.568918 L1:20000703
605 13:50:40.569364 L2:00008067
606 13:50:40.569803 L3:14000000
607 13:50:40.571330 B2:00402000
608 13:50:40.571806 B1:e0f83180
609 13:50:40.572286
610 13:50:40.572727 TE: 58124
611 13:50:40.573160
612 13:50:40.582773 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
613 13:50:40.583283
614 13:50:40.583735 Board ID = 1
615 13:50:40.584211 Set A53 clk to 24M
616 13:50:40.584650 Set A73 clk to 24M
617 13:50:40.588057 Set clk81 to 24M
618 13:50:40.588549 A53 clk: 1200 MHz
619 13:50:40.588991 A73 clk: 1200 MHz
620 13:50:40.593633 CLK81: 166.6M
621 13:50:40.594124 smccc: 00012a92
622 13:50:40.599352 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
623 13:50:40.599836 board id: 1
624 13:50:40.607844 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
625 13:50:40.618575 fw parse done
626 13:50:40.623910 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
627 13:50:40.667050 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
628 13:50:40.677953 PIEI prepare done
629 13:50:40.678456 fastboot data load
630 13:50:40.678905 fastboot data verify
631 13:50:40.683543 verify result: 266
632 13:50:40.689161 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
633 13:50:40.689659 LPDDR4 probe
634 13:50:40.690098 ddr clk to 1584MHz
635 13:50:40.697114 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
636 13:50:40.734412
637 13:50:40.734945 dmc_version 0001
638 13:50:40.741074 Check phy result
639 13:50:40.746906 INFO : End of CA training
640 13:50:40.747383 INFO : End of initialization
641 13:50:40.752539 INFO : Training has run successfully!
642 13:50:40.753011 Check phy result
643 13:50:40.758086 INFO : End of initialization
644 13:50:40.758560 INFO : End of read enable training
645 13:50:40.763704 INFO : End of fine write leveling
646 13:50:40.769300 INFO : End of Write leveling coarse delay
647 13:50:40.769775 INFO : Training has run successfully!
648 13:50:40.770217 Check phy result
649 13:50:40.774857 INFO : End of initialization
650 13:50:40.775334 INFO : End of read dq deskew training
651 13:50:40.780564 INFO : End of MPR read delay center optimization
652 13:50:40.786150 INFO : End of write delay center optimization
653 13:50:40.791715 INFO : End of read delay center optimization
654 13:50:40.792242 INFO : End of max read latency training
655 13:50:40.797321 INFO : Training has run successfully!
656 13:50:40.797799 1D training succeed
657 13:50:40.806679 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
658 13:50:40.854103 Check phy result
659 13:50:40.854676 INFO : End of initialization
660 13:50:40.875671 INFO : End of 2D read delay Voltage center optimization
661 13:50:40.895807 INFO : End of 2D read delay Voltage center optimization
662 13:50:40.947821 INFO : End of 2D write delay Voltage center optimization
663 13:50:40.997096 INFO : End of 2D write delay Voltage center optimization
664 13:50:41.002721 INFO : Training has run successfully!
665 13:50:41.003231
666 13:50:41.003684 channel==0
667 13:50:41.008194 RxClkDly_Margin_A0==88 ps 9
668 13:50:41.008707 TxDqDly_Margin_A0==98 ps 10
669 13:50:41.011591 RxClkDly_Margin_A1==88 ps 9
670 13:50:41.012134 TxDqDly_Margin_A1==98 ps 10
671 13:50:41.017154 TrainedVREFDQ_A0==74
672 13:50:41.017673 TrainedVREFDQ_A1==74
673 13:50:41.018129 VrefDac_Margin_A0==25
674 13:50:41.022762 DeviceVref_Margin_A0==40
675 13:50:41.023289 VrefDac_Margin_A1==25
676 13:50:41.028397 DeviceVref_Margin_A1==40
677 13:50:41.028942
678 13:50:41.029401
679 13:50:41.029842 channel==1
680 13:50:41.030275 RxClkDly_Margin_A0==98 ps 10
681 13:50:41.032028 TxDqDly_Margin_A0==98 ps 10
682 13:50:41.037748 RxClkDly_Margin_A1==88 ps 9
683 13:50:41.038481 TxDqDly_Margin_A1==88 ps 9
684 13:50:41.038988 TrainedVREFDQ_A0==77
685 13:50:41.043264 TrainedVREFDQ_A1==77
686 13:50:41.043844 VrefDac_Margin_A0==22
687 13:50:41.048755 DeviceVref_Margin_A0==37
688 13:50:41.049302 VrefDac_Margin_A1==24
689 13:50:41.049771 DeviceVref_Margin_A1==37
690 13:50:41.050222
691 13:50:41.054516 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
692 13:50:41.055057
693 13:50:41.088101 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
694 13:50:41.088504 2D training succeed
695 13:50:41.093767 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
696 13:50:41.099083 auto size-- 65535DDR cs0 size: 2048MB
697 13:50:41.099515 DDR cs1 size: 2048MB
698 13:50:41.104654 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
699 13:50:41.104943 cs0 DataBus test pass
700 13:50:41.105153 cs1 DataBus test pass
701 13:50:41.110334 cs0 AddrBus test pass
702 13:50:41.110762 cs1 AddrBus test pass
703 13:50:41.111100
704 13:50:41.115877 100bdlr_step_size ps== 420
705 13:50:41.116328 result report
706 13:50:41.116568 boot times 0Enable ddr reg access
707 13:50:41.125375 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
708 13:50:41.138863 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
709 13:50:41.710857 0.0;M3 CHK:0;cm4_sp_mode 0
710 13:50:41.711250 MVN_1=0x00000000
711 13:50:41.716638 MVN_2=0x00000000
712 13:50:41.722128 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
713 13:50:41.722412 OPS=0x10
714 13:50:41.722621 ring efuse init
715 13:50:41.722820 chipver efuse init
716 13:50:41.727767 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
717 13:50:41.733375 [0.018960 Inits done]
718 13:50:41.733641 secure task start!
719 13:50:41.733841 high task start!
720 13:50:41.737944 low task start!
721 13:50:41.738204 run into bl31
722 13:50:41.744616 NOTICE: BL31: v1.3(release):4fc40b1
723 13:50:41.752443 NOTICE: BL31: Built : 15:58:17, May 22 2019
724 13:50:41.752715 NOTICE: BL31: G12A normal boot!
725 13:50:41.778281 NOTICE: BL31: BL33 decompress pass
726 13:50:41.783976 ERROR: Error initializing runtime service opteed_fast
727 13:50:43.016934
728 13:50:43.017341
729 13:50:43.025306 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
730 13:50:43.025655
731 13:50:43.025875 Model: Libre Computer AML-A311D-CC Alta
732 13:50:43.232827 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
733 13:50:43.256218 DRAM: 2 GiB (effective 3.8 GiB)
734 13:50:43.400394 Core: 408 devices, 31 uclasses, devicetree: separate
735 13:50:43.405120 WDT: Not starting watchdog@f0d0
736 13:50:43.438325 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
737 13:50:43.450674 Loading Environment from FAT... Card did not respond to voltage select! : -110
738 13:50:43.454765 ** Bad device specification mmc 0 **
739 13:50:43.466038 Card did not respond to voltage select! : -110
740 13:50:43.472728 ** Bad device specification mmc 0 **
741 13:50:43.473035 Couldn't find partition mmc 0
742 13:50:43.481999 Card did not respond to voltage select! : -110
743 13:50:43.487512 ** Bad device specification mmc 0 **
744 13:50:43.487801 Couldn't find partition mmc 0
745 13:50:43.491542 Error: could not access storage.
746 13:50:43.835067 Net: eth0: ethernet@ff3f0000
747 13:50:43.835461 starting USB...
748 13:50:44.087820 Bus usb@ff500000: Register 3000140 NbrPorts 3
749 13:50:44.088274 Starting the controller
750 13:50:44.094784 USB XHCI 1.10
751 13:50:46.256939 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
752 13:50:46.257496 bl2_stage_init 0x01
753 13:50:46.257737 bl2_stage_init 0x81
754 13:50:46.262496 hw id: 0x0000 - pwm id 0x01
755 13:50:46.262790 bl2_stage_init 0xc1
756 13:50:46.263012 bl2_stage_init 0x02
757 13:50:46.263227
758 13:50:46.268075 L0:00000000
759 13:50:46.268477 L1:20000703
760 13:50:46.268800 L2:00008067
761 13:50:46.269115 L3:14000000
762 13:50:46.273661 B2:00402000
763 13:50:46.273942 B1:e0f83180
764 13:50:46.274149
765 13:50:46.274351 TE: 58167
766 13:50:46.274564
767 13:50:46.279507 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
768 13:50:46.279932
769 13:50:46.280275 Board ID = 1
770 13:50:46.284861 Set A53 clk to 24M
771 13:50:46.285139 Set A73 clk to 24M
772 13:50:46.285344 Set clk81 to 24M
773 13:50:46.290472 A53 clk: 1200 MHz
774 13:50:46.290750 A73 clk: 1200 MHz
775 13:50:46.290958 CLK81: 166.6M
776 13:50:46.291156 smccc: 00012abe
777 13:50:46.296074 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
778 13:50:46.301679 board id: 1
779 13:50:46.307530 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
780 13:50:46.318253 fw parse done
781 13:50:46.323211 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
782 13:50:46.366949 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
783 13:50:46.377814 PIEI prepare done
784 13:50:46.378346 fastboot data load
785 13:50:46.378811 fastboot data verify
786 13:50:46.383391 verify result: 266
787 13:50:46.388969 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
788 13:50:46.389491 LPDDR4 probe
789 13:50:46.389953 ddr clk to 1584MHz
790 13:50:46.397028 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
791 13:50:46.434238
792 13:50:46.434758 dmc_version 0001
793 13:50:46.440909 Check phy result
794 13:50:46.446767 INFO : End of CA training
795 13:50:46.447257 INFO : End of initialization
796 13:50:46.452344 INFO : Training has run successfully!
797 13:50:46.452838 Check phy result
798 13:50:46.457942 INFO : End of initialization
799 13:50:46.458426 INFO : End of read enable training
800 13:50:46.463498 INFO : End of fine write leveling
801 13:50:46.469332 INFO : End of Write leveling coarse delay
802 13:50:46.469826 INFO : Training has run successfully!
803 13:50:46.470280 Check phy result
804 13:50:46.475044 INFO : End of initialization
805 13:50:46.475551 INFO : End of read dq deskew training
806 13:50:46.480931 INFO : End of MPR read delay center optimization
807 13:50:46.486123 INFO : End of write delay center optimization
808 13:50:46.491749 INFO : End of read delay center optimization
809 13:50:46.492277 INFO : End of max read latency training
810 13:50:46.497626 INFO : Training has run successfully!
811 13:50:46.498130 1D training succeed
812 13:50:46.506479 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
813 13:50:46.554077 Check phy result
814 13:50:46.554466 INFO : End of initialization
815 13:50:46.575783 INFO : End of 2D read delay Voltage center optimization
816 13:50:46.595206 INFO : End of 2D read delay Voltage center optimization
817 13:50:46.647558 INFO : End of 2D write delay Voltage center optimization
818 13:50:46.696791 INFO : End of 2D write delay Voltage center optimization
819 13:50:46.702234 INFO : Training has run successfully!
820 13:50:46.702534
821 13:50:46.702760 channel==0
822 13:50:46.707744 RxClkDly_Margin_A0==88 ps 9
823 13:50:46.708206 TxDqDly_Margin_A0==108 ps 11
824 13:50:46.711231 RxClkDly_Margin_A1==88 ps 9
825 13:50:46.711625 TxDqDly_Margin_A1==98 ps 10
826 13:50:46.716858 TrainedVREFDQ_A0==74
827 13:50:46.717189 TrainedVREFDQ_A1==74
828 13:50:46.717408 VrefDac_Margin_A0==25
829 13:50:46.722528 DeviceVref_Margin_A0==40
830 13:50:46.722809 VrefDac_Margin_A1==25
831 13:50:46.728034 DeviceVref_Margin_A1==40
832 13:50:46.728342
833 13:50:46.728556
834 13:50:46.728760 channel==1
835 13:50:46.728958 RxClkDly_Margin_A0==98 ps 10
836 13:50:46.733562 TxDqDly_Margin_A0==88 ps 9
837 13:50:46.733832 RxClkDly_Margin_A1==88 ps 9
838 13:50:46.739216 TxDqDly_Margin_A1==88 ps 9
839 13:50:46.739495 TrainedVREFDQ_A0==76
840 13:50:46.739705 TrainedVREFDQ_A1==77
841 13:50:46.744711 VrefDac_Margin_A0==23
842 13:50:46.744996 DeviceVref_Margin_A0==38
843 13:50:46.750398 VrefDac_Margin_A1==24
844 13:50:46.750690 DeviceVref_Margin_A1==37
845 13:50:46.750889
846 13:50:46.755870 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
847 13:50:46.756148
848 13:50:46.783858 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000018 dram_vref_reg_value 0x 0000005f
849 13:50:46.789507 2D training succeed
850 13:50:46.795108 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
851 13:50:46.795380 auto size-- 65535DDR cs0 size: 2048MB
852 13:50:46.800678 DDR cs1 size: 2048MB
853 13:50:46.800929 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
854 13:50:46.806353 cs0 DataBus test pass
855 13:50:46.806608 cs1 DataBus test pass
856 13:50:46.806805 cs0 AddrBus test pass
857 13:50:46.811912 cs1 AddrBus test pass
858 13:50:46.812230
859 13:50:46.812435 100bdlr_step_size ps== 420
860 13:50:46.812633 result report
861 13:50:46.817478 boot times 0Enable ddr reg access
862 13:50:46.825016 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
863 13:50:46.839181 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
864 13:50:47.412292 0.0;M3 CHK:0;cm4_sp_mode 0
865 13:50:47.412728 MVN_1=0x00000000
866 13:50:47.417614 MVN_2=0x00000000
867 13:50:47.423384 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
868 13:50:47.423850 OPS=0x10
869 13:50:47.424173 ring efuse init
870 13:50:47.424390 chipver efuse init
871 13:50:47.428918 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
872 13:50:47.434539 [0.018961 Inits done]
873 13:50:47.435044 secure task start!
874 13:50:47.435427 high task start!
875 13:50:47.439092 low task start!
876 13:50:47.439421 run into bl31
877 13:50:47.445737 NOTICE: BL31: v1.3(release):4fc40b1
878 13:50:47.453548 NOTICE: BL31: Built : 15:58:17, May 22 2019
879 13:50:47.454006 NOTICE: BL31: G12A normal boot!
880 13:50:47.478917 NOTICE: BL31: BL33 decompress pass
881 13:50:47.484600 ERROR: Error initializing runtime service opteed_fast
882 13:50:48.717609
883 13:50:48.718035
884 13:50:48.725792 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
885 13:50:48.726128
886 13:50:48.726349 Model: Libre Computer AML-A311D-CC Alta
887 13:50:48.934276 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
888 13:50:48.957649 DRAM: 2 GiB (effective 3.8 GiB)
889 13:50:49.100627 Core: 408 devices, 31 uclasses, devicetree: separate
890 13:50:49.106529 WDT: Not starting watchdog@f0d0
891 13:50:49.138789 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
892 13:50:49.151218 Loading Environment from FAT... Card did not respond to voltage select! : -110
893 13:50:49.156150 ** Bad device specification mmc 0 **
894 13:50:49.166526 Card did not respond to voltage select! : -110
895 13:50:49.174141 ** Bad device specification mmc 0 **
896 13:50:49.174466 Couldn't find partition mmc 0
897 13:50:49.182507 Card did not respond to voltage select! : -110
898 13:50:49.188011 ** Bad device specification mmc 0 **
899 13:50:49.188319 Couldn't find partition mmc 0
900 13:50:49.193044 Error: could not access storage.
901 13:50:49.535677 Net: eth0: ethernet@ff3f0000
902 13:50:49.536298 starting USB...
903 13:50:49.787356 Bus usb@ff500000: Register 3000140 NbrPorts 3
904 13:50:49.787773 Starting the controller
905 13:50:49.794298 USB XHCI 1.10
906 13:50:51.657506 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
907 13:50:51.657928 bl2_stage_init 0x01
908 13:50:51.658147 bl2_stage_init 0x81
909 13:50:51.663142 hw id: 0x0000 - pwm id 0x01
910 13:50:51.663573 bl2_stage_init 0xc1
911 13:50:51.663914 bl2_stage_init 0x02
912 13:50:51.664276
913 13:50:51.668766 L0:00000000
914 13:50:51.669173 L1:20000703
915 13:50:51.669417 L2:00008067
916 13:50:51.669625 L3:14000000
917 13:50:51.674321 B2:00402000
918 13:50:51.674601 B1:e0f83180
919 13:50:51.674822
920 13:50:51.675033 TE: 58167
921 13:50:51.675235
922 13:50:51.679847 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
923 13:50:51.680153
924 13:50:51.680368 Board ID = 1
925 13:50:51.685523 Set A53 clk to 24M
926 13:50:51.685957 Set A73 clk to 24M
927 13:50:51.686321 Set clk81 to 24M
928 13:50:51.691055 A53 clk: 1200 MHz
929 13:50:51.691533 A73 clk: 1200 MHz
930 13:50:51.691791 CLK81: 166.6M
931 13:50:51.692024 smccc: 00012abd
932 13:50:51.697615 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
933 13:50:51.702237 board id: 1
934 13:50:51.708190 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
935 13:50:51.718892 fw parse done
936 13:50:51.724898 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
937 13:50:51.767444 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
938 13:50:51.778349 PIEI prepare done
939 13:50:51.778643 fastboot data load
940 13:50:51.778854 fastboot data verify
941 13:50:51.784050 verify result: 266
942 13:50:51.789572 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
943 13:50:51.789832 LPDDR4 probe
944 13:50:51.790037 ddr clk to 1584MHz
945 13:50:51.797569 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
946 13:50:51.834915
947 13:50:51.835242 dmc_version 0001
948 13:50:51.841510 Check phy result
949 13:50:51.847377 INFO : End of CA training
950 13:50:51.847623 INFO : End of initialization
951 13:50:51.852990 INFO : Training has run successfully!
952 13:50:51.853286 Check phy result
953 13:50:51.858575 INFO : End of initialization
954 13:50:51.858828 INFO : End of read enable training
955 13:50:51.862058 INFO : End of fine write leveling
956 13:50:51.867580 INFO : End of Write leveling coarse delay
957 13:50:51.873136 INFO : Training has run successfully!
958 13:50:51.873389 Check phy result
959 13:50:51.873592 INFO : End of initialization
960 13:50:51.878768 INFO : End of read dq deskew training
961 13:50:51.884301 INFO : End of MPR read delay center optimization
962 13:50:51.884674 INFO : End of write delay center optimization
963 13:50:51.890003 INFO : End of read delay center optimization
964 13:50:51.895417 INFO : End of max read latency training
965 13:50:51.895679 INFO : Training has run successfully!
966 13:50:51.901080 1D training succeed
967 13:50:51.907293 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
968 13:50:51.954746 Check phy result
969 13:50:51.955083 INFO : End of initialization
970 13:50:51.976346 INFO : End of 2D read delay Voltage center optimization
971 13:50:51.996649 INFO : End of 2D read delay Voltage center optimization
972 13:50:52.048679 INFO : End of 2D write delay Voltage center optimization
973 13:50:52.098148 INFO : End of 2D write delay Voltage center optimization
974 13:50:52.103513 INFO : Training has run successfully!
975 13:50:52.103778
976 13:50:52.104008 channel==0
977 13:50:52.109188 RxClkDly_Margin_A0==88 ps 9
978 13:50:52.109440 TxDqDly_Margin_A0==98 ps 10
979 13:50:52.112516 RxClkDly_Margin_A1==88 ps 9
980 13:50:52.112868 TxDqDly_Margin_A1==98 ps 10
981 13:50:52.118055 TrainedVREFDQ_A0==74
982 13:50:52.118448 TrainedVREFDQ_A1==74
983 13:50:52.118675 VrefDac_Margin_A0==25
984 13:50:52.123699 DeviceVref_Margin_A0==40
985 13:50:52.123954 VrefDac_Margin_A1==25
986 13:50:52.129314 DeviceVref_Margin_A1==40
987 13:50:52.129560
988 13:50:52.129770
989 13:50:52.129966 channel==1
990 13:50:52.130159 RxClkDly_Margin_A0==98 ps 10
991 13:50:52.132807 TxDqDly_Margin_A0==98 ps 10
992 13:50:52.138464 RxClkDly_Margin_A1==88 ps 9
993 13:50:52.138866 TxDqDly_Margin_A1==88 ps 9
994 13:50:52.139096 TrainedVREFDQ_A0==76
995 13:50:52.144111 TrainedVREFDQ_A1==77
996 13:50:52.144365 VrefDac_Margin_A0==22
997 13:50:52.149684 DeviceVref_Margin_A0==38
998 13:50:52.150154 VrefDac_Margin_A1==24
999 13:50:52.150514 DeviceVref_Margin_A1==37
1000 13:50:52.150738
1001 13:50:52.155227 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
1002 13:50:52.155484
1003 13:50:52.188836 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000018 00000016 00000018 00000016 00000018 00000019 00000017 00000019 00000018 00000019 0000001a 00000018 00000016 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
1004 13:50:52.189298 2D training succeed
1005 13:50:52.194480 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
1006 13:50:52.199950 auto size-- 65535DDR cs0 size: 2048MB
1007 13:50:52.200270 DDR cs1 size: 2048MB
1008 13:50:52.205491 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
1009 13:50:52.205893 cs0 DataBus test pass
1010 13:50:52.206223 cs1 DataBus test pass
1011 13:50:52.211087 cs0 AddrBus test pass
1012 13:50:52.211364 cs1 AddrBus test pass
1013 13:50:52.211571
1014 13:50:52.216720 100bdlr_step_size ps== 420
1015 13:50:52.217136 result report
1016 13:50:52.217465 boot times 0Enable ddr reg access
1017 13:50:52.226414 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
1018 13:50:52.240047 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
1019 13:50:52.813568 0.0;M3 CHK:0;cm4_sp_mode 0
1020 13:50:52.813990 MVN_1=0x00000000
1021 13:50:52.819022 MVN_2=0x00000000
1022 13:50:52.824819 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
1023 13:50:52.825217 OPS=0x10
1024 13:50:52.825447 ring efuse init
1025 13:50:52.825654 chipver efuse init
1026 13:50:52.830378 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
1027 13:50:52.835997 [0.018961 Inits done]
1028 13:50:52.836363 secure task start!
1029 13:50:52.836669 high task start!
1030 13:50:52.840543 low task start!
1031 13:50:52.840801 run into bl31
1032 13:50:52.847207 NOTICE: BL31: v1.3(release):4fc40b1
1033 13:50:52.855336 NOTICE: BL31: Built : 15:58:17, May 22 2019
1034 13:50:52.855701 NOTICE: BL31: G12A normal boot!
1035 13:50:52.880439 NOTICE: BL31: BL33 decompress pass
1036 13:50:52.886303 ERROR: Error initializing runtime service opteed_fast
1037 13:50:54.119078
1038 13:50:54.119738
1039 13:50:54.127417 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
1040 13:50:54.127919
1041 13:50:54.128421 Model: Libre Computer AML-A311D-CC Alta
1042 13:50:54.335835 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
1043 13:50:54.359339 DRAM: 2 GiB (effective 3.8 GiB)
1044 13:50:54.503169 Core: 408 devices, 31 uclasses, devicetree: separate
1045 13:50:54.508188 WDT: Not starting watchdog@f0d0
1046 13:50:54.542001 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
1047 13:50:54.552847 Loading Environment from FAT... Card did not respond to voltage select! : -110
1048 13:50:54.557828 ** Bad device specification mmc 0 **
1049 13:50:54.568246 Card did not respond to voltage select! : -110
1050 13:50:54.575812 ** Bad device specification mmc 0 **
1051 13:50:54.576334 Couldn't find partition mmc 0
1052 13:50:54.584092 Card did not respond to voltage select! : -110
1053 13:50:54.589613 ** Bad device specification mmc 0 **
1054 13:50:54.590091 Couldn't find partition mmc 0
1055 13:50:54.594656 Error: could not access storage.
1056 13:50:54.937180 Net: eth0: ethernet@ff3f0000
1057 13:50:54.937769 starting USB...
1058 13:50:55.189141 Bus usb@ff500000: Register 3000140 NbrPorts 3
1059 13:50:55.189735 Starting the controller
1060 13:50:55.196021 USB XHCI 1.10
1061 13:50:56.753193 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
1062 13:50:56.761458 scanning usb for storage devices... 0 Storage Device(s) found
1064 13:50:56.813055 Hit any key to stop autoboot: 1
1065 13:50:56.813869 end: 2.4.2 bootloader-interrupt (duration 00:00:37) [common]
1066 13:50:56.814535 start: 2.4.3 bootloader-commands (timeout 00:04:23) [common]
1067 13:50:56.814993 Setting prompt string to ['=>']
1068 13:50:56.815454 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:23)
1069 13:50:56.828937 0
1070 13:50:56.829841 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
1071 13:50:56.830315 Sending with 10 millisecond of delay
1073 13:50:57.965503 => setenv autoload no
1074 13:50:57.976310 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:22)
1075 13:50:57.981219 setenv autoload no
1076 13:50:57.981970 Sending with 10 millisecond of delay
1078 13:50:59.780503 => setenv initrd_high 0xffffffff
1079 13:50:59.791322 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:20)
1080 13:50:59.792380 setenv initrd_high 0xffffffff
1081 13:50:59.793238 Sending with 10 millisecond of delay
1083 13:51:01.409679 => setenv fdt_high 0xffffffff
1084 13:51:01.420511 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1085 13:51:01.421416 setenv fdt_high 0xffffffff
1086 13:51:01.422198 Sending with 10 millisecond of delay
1088 13:51:01.714059 => dhcp
1089 13:51:01.724834 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
1090 13:51:01.725691 dhcp
1091 13:51:01.726171 Speed: 1000, full duplex
1092 13:51:01.726624 BOOTP broadcast 1
1093 13:51:01.733891 DHCP client bound to address 192.168.6.27 (9 ms)
1094 13:51:01.734648 Sending with 10 millisecond of delay
1096 13:51:03.411275 => setenv serverip 192.168.6.2
1097 13:51:03.422174 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:16)
1098 13:51:03.423165 setenv serverip 192.168.6.2
1099 13:51:03.423911 Sending with 10 millisecond of delay
1101 13:51:07.148154 => tftpboot 0x01080000 970693/tftp-deploy-k0hw4cy2/kernel/uImage
1102 13:51:07.158971 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:12)
1103 13:51:07.159838 tftpboot 0x01080000 970693/tftp-deploy-k0hw4cy2/kernel/uImage
1104 13:51:07.160380 Speed: 1000, full duplex
1105 13:51:07.160835 Using ethernet@ff3f0000 device
1106 13:51:07.161997 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1107 13:51:07.167918 Filename '970693/tftp-deploy-k0hw4cy2/kernel/uImage'.
1108 13:51:07.171098 Load address: 0x1080000
1109 13:51:10.124281 Loading: *################################################## 43.6 MiB
1110 13:51:10.124941 14.7 MiB/s
1111 13:51:10.125413 done
1112 13:51:10.128532 Bytes transferred = 45713984 (2b98a40 hex)
1113 13:51:10.129365 Sending with 10 millisecond of delay
1115 13:51:14.815640 => tftpboot 0x08000000 970693/tftp-deploy-k0hw4cy2/ramdisk/ramdisk.cpio.gz.uboot
1116 13:51:14.826229 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:05)
1117 13:51:14.826736 tftpboot 0x08000000 970693/tftp-deploy-k0hw4cy2/ramdisk/ramdisk.cpio.gz.uboot
1118 13:51:14.826971 Speed: 1000, full duplex
1119 13:51:14.827180 Using ethernet@ff3f0000 device
1120 13:51:14.828810 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1121 13:51:14.843130 Filename '970693/tftp-deploy-k0hw4cy2/ramdisk/ramdisk.cpio.gz.uboot'.
1122 13:51:14.843562 Load address: 0x8000000
1123 13:51:24.089048 Loading: *######T ########################################### UDP wrong checksum 0000000f 00009818
1124 13:51:29.089616 T UDP wrong checksum 0000000f 00009818
1125 13:51:39.093167 T T UDP wrong checksum 0000000f 00009818
1126 13:51:59.097001 T T T T UDP wrong checksum 0000000f 00009818
1127 13:52:14.101171 T T
1128 13:52:14.101601 Retry count exceeded; starting again
1130 13:52:14.104550 end: 2.4.3 bootloader-commands (duration 00:01:17) [common]
1133 13:52:14.105460 end: 2.4 uboot-commands (duration 00:01:54) [common]
1135 13:52:14.106150 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1137 13:52:14.106695 end: 2 uboot-action (duration 00:01:55) [common]
1139 13:52:14.107478 Cleaning after the job
1140 13:52:14.107780 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/970693/tftp-deploy-k0hw4cy2/ramdisk
1141 13:52:14.108567 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/970693/tftp-deploy-k0hw4cy2/kernel
1142 13:52:14.135338 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/970693/tftp-deploy-k0hw4cy2/dtb
1143 13:52:14.136180 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/970693/tftp-deploy-k0hw4cy2/modules
1144 13:52:14.158801 start: 4.1 power-off (timeout 00:00:30) [common]
1145 13:52:14.159854 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1146 13:52:14.207408 >> OK - accepted request
1147 13:52:14.209329 Returned 0 in 0 seconds
1148 13:52:14.310331 end: 4.1 power-off (duration 00:00:00) [common]
1150 13:52:14.311262 start: 4.2 read-feedback (timeout 00:10:00) [common]
1151 13:52:14.311913 Listened to connection for namespace 'common' for up to 1s
1152 13:52:15.312830 Finalising connection for namespace 'common'
1153 13:52:15.313490 Disconnecting from shell: Finalise
1154 13:52:15.314000 =>
1155 13:52:15.414959 end: 4.2 read-feedback (duration 00:00:01) [common]
1156 13:52:15.415604 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/970693
1157 13:52:16.049546 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/970693
1158 13:52:16.050157 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.