Boot log: meson-g12b-a311d-libretech-cc
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Boot result: UNKNOWN
- Kernel Errors: 0
1 13:46:18.728926 lava-dispatcher, installed at version: 2024.01
2 13:46:18.729755 start: 0 validate
3 13:46:18.730248 Start time: 2024-11-10 13:46:18.730216+00:00 (UTC)
4 13:46:18.730793 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
5 13:46:18.731363 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 13:46:18.771760 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
7 13:46:18.772356 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-686-gd5c38c200807%2Farm64%2Fdefconfig%2Fgcc-12%2Fkernel%2FImage exists
8 13:46:18.804939 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
9 13:46:18.805579 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-686-gd5c38c200807%2Farm64%2Fdefconfig%2Fgcc-12%2Fdtbs%2Famlogic%2Fmeson-g12b-a311d-libretech-cc.dtb exists
10 13:46:18.837908 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
11 13:46:18.838415 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-gst-fluster%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 13:46:18.871892 Using caching service: 'http://192.168.56.18:8001/api/v1/fetch?url=%s'
13 13:46:18.872479 Validating that http://192.168.56.18:8001/api/v1/fetch?url=http%3A%2F%2Fstorage.kernelci.org%2Ftip%2Fmaster%2Fv6.12-rc6-686-gd5c38c200807%2Farm64%2Fdefconfig%2Fgcc-12%2Fmodules.tar.xz exists
14 13:46:18.912325 validate duration: 0.18
16 13:46:18.913206 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 13:46:18.913546 start: 1.1 download-retry (timeout 00:10:00) [common]
18 13:46:18.913872 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 13:46:18.914477 Not decompressing ramdisk as can be used compressed.
20 13:46:18.914939 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/initrd.cpio.gz
21 13:46:18.915230 saving as /var/lib/lava/dispatcher/tmp/970691/tftp-deploy-ja1izsd_/ramdisk/initrd.cpio.gz
22 13:46:18.915506 total size: 5628140 (5 MB)
23 13:46:18.961191 progress 0 % (0 MB)
24 13:46:18.968888 progress 5 % (0 MB)
25 13:46:18.977052 progress 10 % (0 MB)
26 13:46:18.983920 progress 15 % (0 MB)
27 13:46:18.991678 progress 20 % (1 MB)
28 13:46:18.995597 progress 25 % (1 MB)
29 13:46:18.999636 progress 30 % (1 MB)
30 13:46:19.003697 progress 35 % (1 MB)
31 13:46:19.007390 progress 40 % (2 MB)
32 13:46:19.011340 progress 45 % (2 MB)
33 13:46:19.015043 progress 50 % (2 MB)
34 13:46:19.019054 progress 55 % (2 MB)
35 13:46:19.023112 progress 60 % (3 MB)
36 13:46:19.026725 progress 65 % (3 MB)
37 13:46:19.030693 progress 70 % (3 MB)
38 13:46:19.034232 progress 75 % (4 MB)
39 13:46:19.038348 progress 80 % (4 MB)
40 13:46:19.041920 progress 85 % (4 MB)
41 13:46:19.045887 progress 90 % (4 MB)
42 13:46:19.049734 progress 95 % (5 MB)
43 13:46:19.053050 progress 100 % (5 MB)
44 13:46:19.053724 5 MB downloaded in 0.14 s (38.84 MB/s)
45 13:46:19.054318 end: 1.1.1 http-download (duration 00:00:00) [common]
47 13:46:19.055250 end: 1.1 download-retry (duration 00:00:00) [common]
48 13:46:19.055572 start: 1.2 download-retry (timeout 00:10:00) [common]
49 13:46:19.055865 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 13:46:19.056380 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-686-gd5c38c200807/arm64/defconfig/gcc-12/kernel/Image
51 13:46:19.056643 saving as /var/lib/lava/dispatcher/tmp/970691/tftp-deploy-ja1izsd_/kernel/Image
52 13:46:19.056865 total size: 45713920 (43 MB)
53 13:46:19.057091 No compression specified
54 13:46:19.098412 progress 0 % (0 MB)
55 13:46:19.126655 progress 5 % (2 MB)
56 13:46:19.154876 progress 10 % (4 MB)
57 13:46:19.183000 progress 15 % (6 MB)
58 13:46:19.211035 progress 20 % (8 MB)
59 13:46:19.241081 progress 25 % (10 MB)
60 13:46:19.271335 progress 30 % (13 MB)
61 13:46:19.299563 progress 35 % (15 MB)
62 13:46:19.327951 progress 40 % (17 MB)
63 13:46:19.355853 progress 45 % (19 MB)
64 13:46:19.384162 progress 50 % (21 MB)
65 13:46:19.413022 progress 55 % (24 MB)
66 13:46:19.441117 progress 60 % (26 MB)
67 13:46:19.468715 progress 65 % (28 MB)
68 13:46:19.496589 progress 70 % (30 MB)
69 13:46:19.524700 progress 75 % (32 MB)
70 13:46:19.552810 progress 80 % (34 MB)
71 13:46:19.580504 progress 85 % (37 MB)
72 13:46:19.608404 progress 90 % (39 MB)
73 13:46:19.636355 progress 95 % (41 MB)
74 13:46:19.667505 progress 100 % (43 MB)
75 13:46:19.668159 43 MB downloaded in 0.61 s (71.32 MB/s)
76 13:46:19.668685 end: 1.2.1 http-download (duration 00:00:01) [common]
78 13:46:19.669590 end: 1.2 download-retry (duration 00:00:01) [common]
79 13:46:19.669895 start: 1.3 download-retry (timeout 00:09:59) [common]
80 13:46:19.670186 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 13:46:19.670678 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-686-gd5c38c200807/arm64/defconfig/gcc-12/dtbs/amlogic/meson-g12b-a311d-libretech-cc.dtb
82 13:46:19.670985 saving as /var/lib/lava/dispatcher/tmp/970691/tftp-deploy-ja1izsd_/dtb/meson-g12b-a311d-libretech-cc.dtb
83 13:46:19.671206 total size: 54703 (0 MB)
84 13:46:19.671426 No compression specified
85 13:46:19.710565 progress 59 % (0 MB)
86 13:46:19.711484 progress 100 % (0 MB)
87 13:46:19.712131 0 MB downloaded in 0.04 s (1.28 MB/s)
88 13:46:19.712660 end: 1.3.1 http-download (duration 00:00:00) [common]
90 13:46:19.713538 end: 1.3 download-retry (duration 00:00:00) [common]
91 13:46:19.713836 start: 1.4 download-retry (timeout 00:09:59) [common]
92 13:46:19.714131 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 13:46:19.714676 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-gst-fluster/20240313.0/arm64/full.rootfs.tar.xz
94 13:46:19.714959 saving as /var/lib/lava/dispatcher/tmp/970691/tftp-deploy-ja1izsd_/nfsrootfs/full.rootfs.tar
95 13:46:19.715180 total size: 474398908 (452 MB)
96 13:46:19.715404 Using unxz to decompress xz
97 13:46:19.754366 progress 0 % (0 MB)
98 13:46:21.019333 progress 5 % (22 MB)
99 13:46:22.470233 progress 10 % (45 MB)
100 13:46:22.910204 progress 15 % (67 MB)
101 13:46:23.697955 progress 20 % (90 MB)
102 13:46:24.236293 progress 25 % (113 MB)
103 13:46:24.606854 progress 30 % (135 MB)
104 13:46:25.219213 progress 35 % (158 MB)
105 13:46:26.110123 progress 40 % (181 MB)
106 13:46:26.890547 progress 45 % (203 MB)
107 13:46:27.559964 progress 50 % (226 MB)
108 13:46:28.196369 progress 55 % (248 MB)
109 13:46:29.429275 progress 60 % (271 MB)
110 13:46:30.974524 progress 65 % (294 MB)
111 13:46:32.645163 progress 70 % (316 MB)
112 13:46:35.749430 progress 75 % (339 MB)
113 13:46:38.208355 progress 80 % (361 MB)
114 13:46:41.198017 progress 85 % (384 MB)
115 13:46:44.387140 progress 90 % (407 MB)
116 13:46:47.637333 progress 95 % (429 MB)
117 13:46:50.859096 progress 100 % (452 MB)
118 13:46:50.873854 452 MB downloaded in 31.16 s (14.52 MB/s)
119 13:46:50.874754 end: 1.4.1 http-download (duration 00:00:31) [common]
121 13:46:50.876394 end: 1.4 download-retry (duration 00:00:31) [common]
122 13:46:50.876911 start: 1.5 download-retry (timeout 00:09:28) [common]
123 13:46:50.877418 start: 1.5.1 http-download (timeout 00:09:28) [common]
124 13:46:50.878297 downloading http://storage.kernelci.org/tip/master/v6.12-rc6-686-gd5c38c200807/arm64/defconfig/gcc-12/modules.tar.xz
125 13:46:50.878782 saving as /var/lib/lava/dispatcher/tmp/970691/tftp-deploy-ja1izsd_/modules/modules.tar
126 13:46:50.879190 total size: 11611892 (11 MB)
127 13:46:50.879605 Using unxz to decompress xz
128 13:46:50.918262 progress 0 % (0 MB)
129 13:46:50.986308 progress 5 % (0 MB)
130 13:46:51.063239 progress 10 % (1 MB)
131 13:46:51.163676 progress 15 % (1 MB)
132 13:46:51.256775 progress 20 % (2 MB)
133 13:46:51.337138 progress 25 % (2 MB)
134 13:46:51.414149 progress 30 % (3 MB)
135 13:46:51.493293 progress 35 % (3 MB)
136 13:46:51.570767 progress 40 % (4 MB)
137 13:46:51.651463 progress 45 % (5 MB)
138 13:46:51.739882 progress 50 % (5 MB)
139 13:46:51.821230 progress 55 % (6 MB)
140 13:46:51.909989 progress 60 % (6 MB)
141 13:46:51.994363 progress 65 % (7 MB)
142 13:46:52.078311 progress 70 % (7 MB)
143 13:46:52.158820 progress 75 % (8 MB)
144 13:46:52.256897 progress 80 % (8 MB)
145 13:46:52.341865 progress 85 % (9 MB)
146 13:46:52.425282 progress 90 % (9 MB)
147 13:46:52.505317 progress 95 % (10 MB)
148 13:46:52.584543 progress 100 % (11 MB)
149 13:46:52.597512 11 MB downloaded in 1.72 s (6.44 MB/s)
150 13:46:52.598475 end: 1.5.1 http-download (duration 00:00:02) [common]
152 13:46:52.600304 end: 1.5 download-retry (duration 00:00:02) [common]
153 13:46:52.600896 start: 1.6 prepare-tftp-overlay (timeout 00:09:26) [common]
154 13:46:52.601488 start: 1.6.1 extract-nfsrootfs (timeout 00:09:26) [common]
155 13:47:09.029050 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/970691/extract-nfsrootfs-0xggvkgj
156 13:47:09.029668 end: 1.6.1 extract-nfsrootfs (duration 00:00:16) [common]
157 13:47:09.029957 start: 1.6.2 lava-overlay (timeout 00:09:10) [common]
158 13:47:09.030689 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg
159 13:47:09.031185 makedir: /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin
160 13:47:09.031528 makedir: /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/tests
161 13:47:09.031851 makedir: /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/results
162 13:47:09.032219 Creating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin/lava-add-keys
163 13:47:09.032762 Creating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin/lava-add-sources
164 13:47:09.033333 Creating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin/lava-background-process-start
165 13:47:09.033847 Creating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin/lava-background-process-stop
166 13:47:09.034381 Creating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin/lava-common-functions
167 13:47:09.034877 Creating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin/lava-echo-ipv4
168 13:47:09.035370 Creating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin/lava-install-packages
169 13:47:09.035905 Creating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin/lava-installed-packages
170 13:47:09.036455 Creating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin/lava-os-build
171 13:47:09.036955 Creating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin/lava-probe-channel
172 13:47:09.037450 Creating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin/lava-probe-ip
173 13:47:09.037942 Creating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin/lava-target-ip
174 13:47:09.038425 Creating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin/lava-target-mac
175 13:47:09.038912 Creating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin/lava-target-storage
176 13:47:09.039408 Creating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin/lava-test-case
177 13:47:09.039892 Creating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin/lava-test-event
178 13:47:09.040442 Creating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin/lava-test-feedback
179 13:47:09.040942 Creating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin/lava-test-raise
180 13:47:09.041493 Creating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin/lava-test-reference
181 13:47:09.041996 Creating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin/lava-test-runner
182 13:47:09.042489 Creating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin/lava-test-set
183 13:47:09.042977 Creating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin/lava-test-shell
184 13:47:09.043515 Updating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin/lava-install-packages (oe)
185 13:47:09.044085 Updating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/bin/lava-installed-packages (oe)
186 13:47:09.044553 Creating /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/environment
187 13:47:09.044937 LAVA metadata
188 13:47:09.045196 - LAVA_JOB_ID=970691
189 13:47:09.045413 - LAVA_DISPATCHER_IP=192.168.6.2
190 13:47:09.045778 start: 1.6.2.1 ssh-authorize (timeout 00:09:10) [common]
191 13:47:09.046798 end: 1.6.2.1 ssh-authorize (duration 00:00:00) [common]
192 13:47:09.047116 start: 1.6.2.2 lava-vland-overlay (timeout 00:09:10) [common]
193 13:47:09.047324 skipped lava-vland-overlay
194 13:47:09.047564 end: 1.6.2.2 lava-vland-overlay (duration 00:00:00) [common]
195 13:47:09.047820 start: 1.6.2.3 lava-multinode-overlay (timeout 00:09:10) [common]
196 13:47:09.048094 skipped lava-multinode-overlay
197 13:47:09.048343 end: 1.6.2.3 lava-multinode-overlay (duration 00:00:00) [common]
198 13:47:09.048598 start: 1.6.2.4 test-definition (timeout 00:09:10) [common]
199 13:47:09.048848 Loading test definitions
200 13:47:09.049128 start: 1.6.2.4.1 inline-repo-action (timeout 00:09:10) [common]
201 13:47:09.049353 Using /lava-970691 at stage 0
202 13:47:09.050540 uuid=970691_1.6.2.4.1 testdef=None
203 13:47:09.050850 end: 1.6.2.4.1 inline-repo-action (duration 00:00:00) [common]
204 13:47:09.051115 start: 1.6.2.4.2 test-overlay (timeout 00:09:10) [common]
205 13:47:09.052917 end: 1.6.2.4.2 test-overlay (duration 00:00:00) [common]
207 13:47:09.053719 start: 1.6.2.4.3 test-install-overlay (timeout 00:09:10) [common]
208 13:47:09.056023 end: 1.6.2.4.3 test-install-overlay (duration 00:00:00) [common]
210 13:47:09.056866 start: 1.6.2.4.4 test-runscript-overlay (timeout 00:09:10) [common]
211 13:47:09.059015 runner path: /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/0/tests/0_v4l2-decoder-conformance-h265 test_uuid 970691_1.6.2.4.1
212 13:47:09.059581 end: 1.6.2.4.4 test-runscript-overlay (duration 00:00:00) [common]
214 13:47:09.060365 Creating lava-test-runner.conf files
215 13:47:09.060572 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/970691/lava-overlay-iimqphlg/lava-970691/0 for stage 0
216 13:47:09.060923 - 0_v4l2-decoder-conformance-h265
217 13:47:09.061272 end: 1.6.2.4 test-definition (duration 00:00:00) [common]
218 13:47:09.061547 start: 1.6.2.5 compress-overlay (timeout 00:09:10) [common]
219 13:47:09.083241 end: 1.6.2.5 compress-overlay (duration 00:00:00) [common]
220 13:47:09.083654 start: 1.6.2.6 persistent-nfs-overlay (timeout 00:09:10) [common]
221 13:47:09.083913 end: 1.6.2.6 persistent-nfs-overlay (duration 00:00:00) [common]
222 13:47:09.084208 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
223 13:47:09.084476 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:10) [common]
224 13:47:09.721427 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:01) [common]
225 13:47:09.721894 start: 1.6.4 extract-modules (timeout 00:09:09) [common]
226 13:47:09.722145 extracting modules file /var/lib/lava/dispatcher/tmp/970691/tftp-deploy-ja1izsd_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/970691/extract-nfsrootfs-0xggvkgj
227 13:47:11.106400 extracting modules file /var/lib/lava/dispatcher/tmp/970691/tftp-deploy-ja1izsd_/modules/modules.tar to /var/lib/lava/dispatcher/tmp/970691/extract-overlay-ramdisk-e0k__ue5/ramdisk
228 13:47:12.543279 end: 1.6.4 extract-modules (duration 00:00:03) [common]
229 13:47:12.543767 start: 1.6.5 apply-overlay-tftp (timeout 00:09:06) [common]
230 13:47:12.544069 [common] Applying overlay to NFS
231 13:47:12.544291 [common] Applying overlay /var/lib/lava/dispatcher/tmp/970691/compress-overlay-pte_9iaw/overlay-1.6.2.5.tar.gz to directory /var/lib/lava/dispatcher/tmp/970691/extract-nfsrootfs-0xggvkgj
232 13:47:12.573927 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
233 13:47:12.574370 start: 1.6.6 prepare-kernel (timeout 00:09:06) [common]
234 13:47:12.574645 start: 1.6.6.1 uboot-prepare-kernel (timeout 00:09:06) [common]
235 13:47:12.574875 Converting downloaded kernel to a uImage
236 13:47:12.575190 mkimage -A arm64 -O linux -T kernel -C none -a 0x1080000 -e 0x1080000 -d /var/lib/lava/dispatcher/tmp/970691/tftp-deploy-ja1izsd_/kernel/Image /var/lib/lava/dispatcher/tmp/970691/tftp-deploy-ja1izsd_/kernel/uImage
237 13:47:13.068950 output: Image Name:
238 13:47:13.069373 output: Created: Sun Nov 10 13:47:12 2024
239 13:47:13.069585 output: Image Type: AArch64 Linux Kernel Image (uncompressed)
240 13:47:13.069792 output: Data Size: 45713920 Bytes = 44642.50 KiB = 43.60 MiB
241 13:47:13.069996 output: Load Address: 01080000
242 13:47:13.070197 output: Entry Point: 01080000
243 13:47:13.070396 output:
244 13:47:13.070733 end: 1.6.6.1 uboot-prepare-kernel (duration 00:00:00) [common]
245 13:47:13.070999 end: 1.6.6 prepare-kernel (duration 00:00:00) [common]
246 13:47:13.071269 start: 1.6.7 configure-preseed-file (timeout 00:09:06) [common]
247 13:47:13.071526 end: 1.6.7 configure-preseed-file (duration 00:00:00) [common]
248 13:47:13.071784 start: 1.6.8 compress-ramdisk (timeout 00:09:06) [common]
249 13:47:13.072084 Building ramdisk /var/lib/lava/dispatcher/tmp/970691/extract-overlay-ramdisk-e0k__ue5/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/970691/extract-overlay-ramdisk-e0k__ue5/ramdisk
250 13:47:15.493845 >> 166827 blocks
251 13:47:23.248558 Adding RAMdisk u-boot header.
252 13:47:23.248982 mkimage -A arm64 -T ramdisk -C none -d /var/lib/lava/dispatcher/tmp/970691/extract-overlay-ramdisk-e0k__ue5/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/970691/extract-overlay-ramdisk-e0k__ue5/ramdisk.cpio.gz.uboot
253 13:47:23.493472 output: Image Name:
254 13:47:23.493894 output: Created: Sun Nov 10 13:47:23 2024
255 13:47:23.494106 output: Image Type: AArch64 Linux RAMDisk Image (uncompressed)
256 13:47:23.494310 output: Data Size: 23437029 Bytes = 22887.72 KiB = 22.35 MiB
257 13:47:23.494510 output: Load Address: 00000000
258 13:47:23.494708 output: Entry Point: 00000000
259 13:47:23.494902 output:
260 13:47:23.495649 rename /var/lib/lava/dispatcher/tmp/970691/extract-overlay-ramdisk-e0k__ue5/ramdisk.cpio.gz.uboot to /var/lib/lava/dispatcher/tmp/970691/tftp-deploy-ja1izsd_/ramdisk/ramdisk.cpio.gz.uboot
261 13:47:23.496155 end: 1.6.8 compress-ramdisk (duration 00:00:10) [common]
262 13:47:23.496720 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
263 13:47:23.497277 start: 1.7 lxc-create-udev-rule-action (timeout 00:08:55) [common]
264 13:47:23.497733 No LXC device requested
265 13:47:23.498229 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
266 13:47:23.498729 start: 1.8 deploy-device-env (timeout 00:08:55) [common]
267 13:47:23.499215 end: 1.8 deploy-device-env (duration 00:00:00) [common]
268 13:47:23.499626 Checking files for TFTP limit of 4294967296 bytes.
269 13:47:23.502334 end: 1 tftp-deploy (duration 00:01:05) [common]
270 13:47:23.502934 start: 2 uboot-action (timeout 00:05:00) [common]
271 13:47:23.503455 start: 2.1 uboot-from-media (timeout 00:05:00) [common]
272 13:47:23.503947 end: 2.1 uboot-from-media (duration 00:00:00) [common]
273 13:47:23.504491 start: 2.2 bootloader-overlay (timeout 00:05:00) [common]
274 13:47:23.505021 Using kernel file from prepare-kernel: 970691/tftp-deploy-ja1izsd_/kernel/uImage
275 13:47:23.505648 substitutions:
276 13:47:23.506051 - {BOOTX}: bootm 0x01080000 0x08000000 0x01070000
277 13:47:23.506450 - {DTB_ADDR}: 0x01070000
278 13:47:23.506845 - {DTB}: 970691/tftp-deploy-ja1izsd_/dtb/meson-g12b-a311d-libretech-cc.dtb
279 13:47:23.507237 - {INITRD}: 970691/tftp-deploy-ja1izsd_/ramdisk/ramdisk.cpio.gz.uboot
280 13:47:23.507630 - {KERNEL_ADDR}: 0x01080000
281 13:47:23.508051 - {KERNEL}: 970691/tftp-deploy-ja1izsd_/kernel/uImage
282 13:47:23.508451 - {LAVA_MAC}: None
283 13:47:23.508887 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/970691/extract-nfsrootfs-0xggvkgj
284 13:47:23.509284 - {NFS_SERVER_IP}: 192.168.6.2
285 13:47:23.509672 - {PRESEED_CONFIG}: None
286 13:47:23.510057 - {PRESEED_LOCAL}: None
287 13:47:23.510443 - {RAMDISK_ADDR}: 0x08000000
288 13:47:23.510823 - {RAMDISK}: 970691/tftp-deploy-ja1izsd_/ramdisk/ramdisk.cpio.gz.uboot
289 13:47:23.511206 - {ROOT_PART}: None
290 13:47:23.511591 - {ROOT}: None
291 13:47:23.511975 - {SERVER_IP}: 192.168.6.2
292 13:47:23.512390 - {TEE_ADDR}: 0x83000000
293 13:47:23.512777 - {TEE}: None
294 13:47:23.513163 Parsed boot commands:
295 13:47:23.513539 - setenv autoload no
296 13:47:23.513920 - setenv initrd_high 0xffffffff
297 13:47:23.514336 - setenv fdt_high 0xffffffff
298 13:47:23.514727 - dhcp
299 13:47:23.515109 - setenv serverip 192.168.6.2
300 13:47:23.515487 - tftpboot 0x01080000 970691/tftp-deploy-ja1izsd_/kernel/uImage
301 13:47:23.515870 - tftpboot 0x08000000 970691/tftp-deploy-ja1izsd_/ramdisk/ramdisk.cpio.gz.uboot
302 13:47:23.516282 - tftpboot 0x01070000 970691/tftp-deploy-ja1izsd_/dtb/meson-g12b-a311d-libretech-cc.dtb
303 13:47:23.516666 - setenv bootargs 'console=ttyAML0,115200n8 root=/dev/nfs rw nfsroot=192.168.6.2:/var/lib/lava/dispatcher/tmp/970691/extract-nfsrootfs-0xggvkgj,tcp,hard console_msg_format=syslog earlycon deferred_probe_timeout=60 ip=dhcp'
304 13:47:23.517060 - bootm 0x01080000 0x08000000 0x01070000
305 13:47:23.517557 end: 2.2 bootloader-overlay (duration 00:00:00) [common]
307 13:47:23.519035 start: 2.3 connect-device (timeout 00:05:00) [common]
308 13:47:23.519452 [common] connect-device Connecting to device using 'telnet conserv1 3007'
309 13:47:23.534788 Setting prompt string to ['lava-test: # ']
310 13:47:23.536354 end: 2.3 connect-device (duration 00:00:00) [common]
311 13:47:23.536969 start: 2.4 uboot-commands (timeout 00:05:00) [common]
312 13:47:23.537512 start: 2.4.1 reset-device (timeout 00:05:00) [common]
313 13:47:23.538048 start: 2.4.1.1 pdu-reboot (timeout 00:05:00) [common]
314 13:47:23.539172 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/reboot?hostname=cambrionix&port=alta-01'
315 13:47:23.576929 >> OK - accepted request
316 13:47:23.579384 Returned 0 in 0 seconds
317 13:47:23.680534 end: 2.4.1.1 pdu-reboot (duration 00:00:00) [common]
319 13:47:23.682120 end: 2.4.1 reset-device (duration 00:00:00) [common]
320 13:47:23.682673 start: 2.4.2 bootloader-interrupt (timeout 00:05:00) [common]
321 13:47:23.683192 Setting prompt string to ['Hit any key to stop autoboot']
322 13:47:23.683652 bootloader-interrupt: Wait for prompt ['Hit any key to stop autoboot'] (timeout 00:05:00)
323 13:47:23.685268 Trying 192.168.56.21...
324 13:47:23.685741 Connected to conserv1.
325 13:47:23.686155 Escape character is '^]'.
326 13:47:23.686566
327 13:47:23.686980 ser2net port telnet,3007 device serialdev, /dev/serial/by-path/platform-fd500000.pcie-pci-0000:01:00.0-usb-0:1.2.4.4:1.0-port0, 115200n81, local=false [,115200N81] (Debian GNU/Linux)
328 13:47:23.687396
329 13:47:35.235111 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
330 13:47:35.235545 bl2_stage_init 0x01
331 13:47:35.235775 bl2_stage_init 0x81
332 13:47:35.240701 hw id: 0x0000 - pwm id 0x01
333 13:47:35.240984 bl2_stage_init 0xc1
334 13:47:35.241199 bl2_stage_init 0x02
335 13:47:35.241403
336 13:47:35.246238 L0:00000000
337 13:47:35.246502 L1:20000703
338 13:47:35.246714 L2:00008067
339 13:47:35.246916 L3:14000000
340 13:47:35.249168 B2:00402000
341 13:47:35.249421 B1:e0f83180
342 13:47:35.249628
343 13:47:35.249834 TE: 58167
344 13:47:35.250038
345 13:47:35.260392 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
346 13:47:35.260668
347 13:47:35.260880 Board ID = 1
348 13:47:35.261083 Set A53 clk to 24M
349 13:47:35.261284 Set A73 clk to 24M
350 13:47:35.266023 Set clk81 to 24M
351 13:47:35.266269 A53 clk: 1200 MHz
352 13:47:35.266476 A73 clk: 1200 MHz
353 13:47:35.269590 CLK81: 166.6M
354 13:47:35.269833 smccc: 00012abd
355 13:47:35.275011 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
356 13:47:35.280633 board id: 1
357 13:47:35.285707 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
358 13:47:35.296296 fw parse done
359 13:47:35.302153 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
360 13:47:35.344782 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
361 13:47:35.355866 PIEI prepare done
362 13:47:35.356161 fastboot data load
363 13:47:35.356374 fastboot data verify
364 13:47:35.361307 verify result: 266
365 13:47:35.366937 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
366 13:47:35.367201 LPDDR4 probe
367 13:47:35.367412 ddr clk to 1584MHz
368 13:47:35.375103 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
369 13:47:35.412368
370 13:47:35.412944 dmc_version 0001
371 13:47:35.419064 Check phy result
372 13:47:35.424807 INFO : End of CA training
373 13:47:35.425143 INFO : End of initialization
374 13:47:35.430372 INFO : Training has run successfully!
375 13:47:35.430708 Check phy result
376 13:47:35.435944 INFO : End of initialization
377 13:47:35.436456 INFO : End of read enable training
378 13:47:35.441665 INFO : End of fine write leveling
379 13:47:35.447239 INFO : End of Write leveling coarse delay
380 13:47:35.447764 INFO : Training has run successfully!
381 13:47:35.448251 Check phy result
382 13:47:35.452893 INFO : End of initialization
383 13:47:35.453426 INFO : End of read dq deskew training
384 13:47:35.458427 INFO : End of MPR read delay center optimization
385 13:47:35.464053 INFO : End of write delay center optimization
386 13:47:35.469630 INFO : End of read delay center optimization
387 13:47:35.470154 INFO : End of max read latency training
388 13:47:35.475229 INFO : Training has run successfully!
389 13:47:35.475760 1D training succeed
390 13:47:35.484355 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
391 13:47:35.532039 Check phy result
392 13:47:35.532448 INFO : End of initialization
393 13:47:35.554623 INFO : End of 2D read delay Voltage center optimization
394 13:47:35.574885 INFO : End of 2D read delay Voltage center optimization
395 13:47:35.627086 INFO : End of 2D write delay Voltage center optimization
396 13:47:35.676306 INFO : End of 2D write delay Voltage center optimization
397 13:47:35.681797 INFO : Training has run successfully!
398 13:47:35.682140
399 13:47:35.682413 channel==0
400 13:47:35.687394 RxClkDly_Margin_A0==88 ps 9
401 13:47:35.687724 TxDqDly_Margin_A0==98 ps 10
402 13:47:35.692991 RxClkDly_Margin_A1==88 ps 9
403 13:47:35.693330 TxDqDly_Margin_A1==88 ps 9
404 13:47:35.693592 TrainedVREFDQ_A0==74
405 13:47:35.698548 TrainedVREFDQ_A1==74
406 13:47:35.698870 VrefDac_Margin_A0==25
407 13:47:35.699123 DeviceVref_Margin_A0==40
408 13:47:35.704190 VrefDac_Margin_A1==25
409 13:47:35.704521 DeviceVref_Margin_A1==40
410 13:47:35.704770
411 13:47:35.705010
412 13:47:35.705242 channel==1
413 13:47:35.709768 RxClkDly_Margin_A0==88 ps 9
414 13:47:35.710092 TxDqDly_Margin_A0==98 ps 10
415 13:47:35.715367 RxClkDly_Margin_A1==98 ps 10
416 13:47:35.715693 TxDqDly_Margin_A1==88 ps 9
417 13:47:35.720992 TrainedVREFDQ_A0==77
418 13:47:35.721329 TrainedVREFDQ_A1==77
419 13:47:35.721581 VrefDac_Margin_A0==22
420 13:47:35.726551 DeviceVref_Margin_A0==37
421 13:47:35.726873 VrefDac_Margin_A1==22
422 13:47:35.732203 DeviceVref_Margin_A1==37
423 13:47:35.732535
424 13:47:35.732789 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
425 13:47:35.733031
426 13:47:35.765746 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000018 00000016 00000018 00000018 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000019 00000017 dram_vref_reg_value 0x 00000060
427 13:47:35.766169 2D training succeed
428 13:47:35.771361 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
429 13:47:35.776981 auto size-- 65535DDR cs0 size: 2048MB
430 13:47:35.777308 DDR cs1 size: 2048MB
431 13:47:35.782556 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
432 13:47:35.782876 cs0 DataBus test pass
433 13:47:35.788191 cs1 DataBus test pass
434 13:47:35.788521 cs0 AddrBus test pass
435 13:47:35.788778 cs1 AddrBus test pass
436 13:47:35.789017
437 13:47:35.793774 100bdlr_step_size ps== 420
438 13:47:35.794112 result report
439 13:47:35.799387 boot times 0Enable ddr reg access
440 13:47:35.804634 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
441 13:47:35.818134 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
442 13:47:36.391780 0.0;M3 CHK:0;cm4_sp_mode 0
443 13:47:36.392611 MVN_1=0x00000000
444 13:47:36.397231 MVN_2=0x00000000
445 13:47:36.403060 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
446 13:47:36.403571 OPS=0x10
447 13:47:36.404077 ring efuse init
448 13:47:36.404543 chipver efuse init
449 13:47:36.408561 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
450 13:47:36.414243 [0.018960 Inits done]
451 13:47:36.414757 secure task start!
452 13:47:36.415223 high task start!
453 13:47:36.418823 low task start!
454 13:47:36.419326 run into bl31
455 13:47:36.425391 NOTICE: BL31: v1.3(release):4fc40b1
456 13:47:36.433189 NOTICE: BL31: Built : 15:58:17, May 22 2019
457 13:47:36.433699 NOTICE: BL31: G12A normal boot!
458 13:47:36.458528 NOTICE: BL31: BL33 decompress pass
459 13:47:36.464219 ERROR: Error initializing runtime service opteed_fast
460 13:47:37.697291
461 13:47:37.697970
462 13:47:37.705492 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
463 13:47:37.705992
464 13:47:37.706453 Model: Libre Computer AML-A311D-CC Alta
465 13:47:37.913966 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
466 13:47:37.937308 DRAM: 2 GiB (effective 3.8 GiB)
467 13:47:38.080357 Core: 408 devices, 31 uclasses, devicetree: separate
468 13:47:38.086195 WDT: Not starting watchdog@f0d0
469 13:47:38.118458 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
470 13:47:38.130928 Loading Environment from FAT... Card did not respond to voltage select! : -110
471 13:47:38.135866 ** Bad device specification mmc 0 **
472 13:47:38.146261 Card did not respond to voltage select! : -110
473 13:47:38.153873 ** Bad device specification mmc 0 **
474 13:47:38.154370 Couldn't find partition mmc 0
475 13:47:38.162245 Card did not respond to voltage select! : -110
476 13:47:38.167722 ** Bad device specification mmc 0 **
477 13:47:38.168239 Couldn't find partition mmc 0
478 13:47:38.172781 Error: could not access storage.
479 13:47:39.435832 G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
480 13:47:39.436519 bl2_stage_init 0x01
481 13:47:39.436998 bl2_stage_init 0x81
482 13:47:39.441331 hw id: 0x0000 - pwm id 0x01
483 13:47:39.441835 bl2_stage_init 0xc1
484 13:47:39.442297 bl2_stage_init 0x02
485 13:47:39.442744
486 13:47:39.446844 L0:00000000
487 13:47:39.447321 L1:20000703
488 13:47:39.447767 L2:00008067
489 13:47:39.448277 L3:14000000
490 13:47:39.452541 B2:00402000
491 13:47:39.453095 B1:e0f83180
492 13:47:39.453548
493 13:47:39.453994 TE: 58159
494 13:47:39.454433
495 13:47:39.458085 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
496 13:47:39.458581
497 13:47:39.459032 Board ID = 1
498 13:47:39.463678 Set A53 clk to 24M
499 13:47:39.464205 Set A73 clk to 24M
500 13:47:39.464653 Set clk81 to 24M
501 13:47:39.469319 A53 clk: 1200 MHz
502 13:47:39.469802 A73 clk: 1200 MHz
503 13:47:39.470245 CLK81: 166.6M
504 13:47:39.470684 smccc: 00012ab5
505 13:47:39.474859 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
506 13:47:39.480480 board id: 1
507 13:47:39.486386 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
508 13:47:39.496983 fw parse done
509 13:47:39.502969 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
510 13:47:39.545620 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
511 13:47:39.556491 PIEI prepare done
512 13:47:39.556993 fastboot data load
513 13:47:39.557255 fastboot data verify
514 13:47:39.562170 verify result: 266
515 13:47:39.567777 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
516 13:47:39.568197 LPDDR4 probe
517 13:47:39.568480 ddr clk to 1584MHz
518 13:47:39.575713 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
519 13:47:39.613030
520 13:47:39.613558 dmc_version 0001
521 13:47:39.619654 Check phy result
522 13:47:39.625564 INFO : End of CA training
523 13:47:39.626035 INFO : End of initialization
524 13:47:39.631136 INFO : Training has run successfully!
525 13:47:39.631599 Check phy result
526 13:47:39.636737 INFO : End of initialization
527 13:47:39.637209 INFO : End of read enable training
528 13:47:39.642483 INFO : End of fine write leveling
529 13:47:39.647964 INFO : End of Write leveling coarse delay
530 13:47:39.648557 INFO : Training has run successfully!
531 13:47:39.649025 Check phy result
532 13:47:39.653553 INFO : End of initialization
533 13:47:39.654067 INFO : End of read dq deskew training
534 13:47:39.659118 INFO : End of MPR read delay center optimization
535 13:47:39.664705 INFO : End of write delay center optimization
536 13:47:39.670372 INFO : End of read delay center optimization
537 13:47:39.670861 INFO : End of max read latency training
538 13:47:39.675893 INFO : Training has run successfully!
539 13:47:39.676434 1D training succeed
540 13:47:39.685125 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
541 13:47:39.732920 Check phy result
542 13:47:39.733575 INFO : End of initialization
543 13:47:39.754515 INFO : End of 2D read delay Voltage center optimization
544 13:47:39.774782 INFO : End of 2D read delay Voltage center optimization
545 13:47:39.826781 INFO : End of 2D write delay Voltage center optimization
546 13:47:39.876127 INFO : End of 2D write delay Voltage center optimization
547 13:47:39.881696 INFO : Training has run successfully!
548 13:47:39.882203
549 13:47:39.882684 channel==0
550 13:47:39.887277 RxClkDly_Margin_A0==88 ps 9
551 13:47:39.887784 TxDqDly_Margin_A0==98 ps 10
552 13:47:39.890583 RxClkDly_Margin_A1==88 ps 9
553 13:47:39.891073 TxDqDly_Margin_A1==98 ps 10
554 13:47:39.896113 TrainedVREFDQ_A0==74
555 13:47:39.896633 TrainedVREFDQ_A1==74
556 13:47:39.901692 VrefDac_Margin_A0==25
557 13:47:39.902171 DeviceVref_Margin_A0==40
558 13:47:39.902615 VrefDac_Margin_A1==25
559 13:47:39.907322 DeviceVref_Margin_A1==40
560 13:47:39.907825
561 13:47:39.908320
562 13:47:39.908797 channel==1
563 13:47:39.909245 RxClkDly_Margin_A0==98 ps 10
564 13:47:39.912930 TxDqDly_Margin_A0==98 ps 10
565 13:47:39.913449 RxClkDly_Margin_A1==98 ps 10
566 13:47:39.918571 TxDqDly_Margin_A1==88 ps 9
567 13:47:39.919072 TrainedVREFDQ_A0==77
568 13:47:39.919520 TrainedVREFDQ_A1==77
569 13:47:39.924110 VrefDac_Margin_A0==22
570 13:47:39.924603 DeviceVref_Margin_A0==37
571 13:47:39.929709 VrefDac_Margin_A1==22
572 13:47:39.930194 DeviceVref_Margin_A1==37
573 13:47:39.930639
574 13:47:39.935323 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
575 13:47:39.935817
576 13:47:39.963324 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000018 00000019 00000018 00000018 00000018 00000016 00000017 00000016 00000018 00000019 00000018 00000019 00000018 00000019 0000001a 00000018 00000017 00000018 00000018 00000019 00000018 00000018 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
577 13:47:39.968898 2D training succeed
578 13:47:39.974583 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
579 13:47:39.975083 auto size-- 65535DDR cs0 size: 2048MB
580 13:47:39.980114 DDR cs1 size: 2048MB
581 13:47:39.980610 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
582 13:47:39.985728 cs0 DataBus test pass
583 13:47:39.986248 cs1 DataBus test pass
584 13:47:39.986696 cs0 AddrBus test pass
585 13:47:39.991308 cs1 AddrBus test pass
586 13:47:39.991798
587 13:47:39.992304 100bdlr_step_size ps== 420
588 13:47:39.992766 result report
589 13:47:39.996892 boot times 0Enable ddr reg access
590 13:47:40.004733 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
591 13:47:40.018253 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
592 13:47:40.592245 0.0;M3 CHK:0;cm4_sp_mode 0
593 13:47:40.592669 MVN_1=0x00000000
594 13:47:40.597472 MVN_2=0x00000000
595 13:47:40.603303 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
596 13:47:40.603643 OPS=0x10
597 13:47:40.603859 ring efuse init
598 13:47:40.604096 chipver efuse init
599 13:47:40.608840 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
600 13:47:40.614431 [0.018960 Inits done]
601 13:47:40.614666 secure task start!
602 13:47:40.614864 high task start!
603 13:47:40.619069 low task start!
604 13:47:40.619298 run into bl31
605 13:47:40.625736 NOTICE: BL31: v1.3(release):4fc40b1
606 13:47:40.633519 NOTICE: BL31: Built : 15:58:17, May 22 2019
607 13:47:40.634020 NOTICE: BL31: G12A normal boot!
608 13:47:40.658997 NOTICE: BL31: BL33 decompress pass
609 13:47:40.664777 ERROR: Error initializing runtime service opteed_fast
610 13:47:41.897733
611 13:47:41.898437
612 13:47:41.906055 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
613 13:47:41.906588
614 13:47:41.907052 Model: Libre Computer AML-A311D-CC Alta
615 13:47:42.114511 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
616 13:47:42.137812 DRAM: 2 GiB (effective 3.8 GiB)
617 13:47:42.280919 Core: 408 devices, 31 uclasses, devicetree: separate
618 13:47:42.286782 WDT: Not starting watchdog@f0d0
619 13:47:42.318872 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
620 13:47:42.331294 Loading Environment from FAT... Card did not respond to voltage select! : -110
621 13:47:42.336246 ** Bad device specification mmc 0 **
622 13:47:42.346557 Card did not respond to voltage select! : -110
623 13:47:42.354279 ** Bad device specification mmc 0 **
624 13:47:42.354819 Couldn't find partition mmc 0
625 13:47:42.362529 Card did not respond to voltage select! : -110
626 13:47:42.368092 ** Bad device specification mmc 0 **
627 13:47:42.368632 Couldn't find partition mmc 0
628 13:47:42.373229 Error: could not access storage.
629 13:47:42.715734 Net: eth0: ethernet@ff3f0000
630 13:47:42.716454 starting USB...
631 13:47:42.967475 Bus usb@ff500000: Register 3000140 NbrPorts 3
632 13:47:42.968150 Starting the controller
633 13:47:42.974426 USB XHCI 1.10
634 13:47:44.685842 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
635 13:47:44.686546 bl2_stage_init 0x01
636 13:47:44.687025 bl2_stage_init 0x81
637 13:47:44.691419 hw id: 0x0000 - pwm id 0x01
638 13:47:44.691933 bl2_stage_init 0xc1
639 13:47:44.692641 bl2_stage_init 0x02
640 13:47:44.693090
641 13:47:44.696963 L0:00000000
642 13:47:44.697435 L1:20000703
643 13:47:44.697850 L2:00008067
644 13:47:44.698259 L3:14000000
645 13:47:44.702598 B2:00402000
646 13:47:44.703078 B1:e0f83180
647 13:47:44.703497
648 13:47:44.703908 TE: 58124
649 13:47:44.704359
650 13:47:44.708237 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
651 13:47:44.708724
652 13:47:44.709149 Board ID = 1
653 13:47:44.714719 Set A53 clk to 24M
654 13:47:44.716229 Set A73 clk to 24M
655 13:47:44.716693 Set clk81 to 24M
656 13:47:44.717111 A53 clk: 1200 MHz
657 13:47:44.717515 A73 clk: 1200 MHz
658 13:47:44.721768 CLK81: 166.6M
659 13:47:44.722325 smccc: 00012a92
660 13:47:44.727396 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
661 13:47:44.727902 board id: 1
662 13:47:44.735500 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
663 13:47:44.747086 fw parse done
664 13:47:44.753094 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
665 13:47:44.795549 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
666 13:47:44.806536 PIEI prepare done
667 13:47:44.807054 fastboot data load
668 13:47:44.807489 fastboot data verify
669 13:47:44.812182 verify result: 266
670 13:47:44.817724 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
671 13:47:44.818207 LPDDR4 probe
672 13:47:44.818632 ddr clk to 1584MHz
673 13:47:44.825715 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
674 13:47:44.862945
675 13:47:44.863426 dmc_version 0001
676 13:47:44.869595 Check phy result
677 13:47:44.875497 INFO : End of CA training
678 13:47:44.876027 INFO : End of initialization
679 13:47:44.881114 INFO : Training has run successfully!
680 13:47:44.881607 Check phy result
681 13:47:44.886660 INFO : End of initialization
682 13:47:44.887138 INFO : End of read enable training
683 13:47:44.892276 INFO : End of fine write leveling
684 13:47:44.897860 INFO : End of Write leveling coarse delay
685 13:47:44.898347 INFO : Training has run successfully!
686 13:47:44.898760 Check phy result
687 13:47:44.903442 INFO : End of initialization
688 13:47:44.903911 INFO : End of read dq deskew training
689 13:47:44.909094 INFO : End of MPR read delay center optimization
690 13:47:44.914636 INFO : End of write delay center optimization
691 13:47:44.920264 INFO : End of read delay center optimization
692 13:47:44.920730 INFO : End of max read latency training
693 13:47:44.925852 INFO : Training has run successfully!
694 13:47:44.926313 1D training succeed
695 13:47:44.935025 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
696 13:47:44.982686 Check phy result
697 13:47:44.983201 INFO : End of initialization
698 13:47:45.005289 INFO : End of 2D read delay Voltage center optimization
699 13:47:45.025596 INFO : End of 2D read delay Voltage center optimization
700 13:47:45.077581 INFO : End of 2D write delay Voltage center optimization
701 13:47:45.126939 INFO : End of 2D write delay Voltage center optimization
702 13:47:45.132456 INFO : Training has run successfully!
703 13:47:45.132950
704 13:47:45.133361 channel==0
705 13:47:45.138040 RxClkDly_Margin_A0==88 ps 9
706 13:47:45.138526 TxDqDly_Margin_A0==98 ps 10
707 13:47:45.143623 RxClkDly_Margin_A1==88 ps 9
708 13:47:45.144150 TxDqDly_Margin_A1==98 ps 10
709 13:47:45.144579 TrainedVREFDQ_A0==74
710 13:47:45.149250 TrainedVREFDQ_A1==74
711 13:47:45.149734 VrefDac_Margin_A0==24
712 13:47:45.150147 DeviceVref_Margin_A0==40
713 13:47:45.154831 VrefDac_Margin_A1==24
714 13:47:45.155303 DeviceVref_Margin_A1==40
715 13:47:45.155713
716 13:47:45.156155
717 13:47:45.160435 channel==1
718 13:47:45.160921 RxClkDly_Margin_A0==98 ps 10
719 13:47:45.161329 TxDqDly_Margin_A0==88 ps 9
720 13:47:45.166000 RxClkDly_Margin_A1==98 ps 10
721 13:47:45.166472 TxDqDly_Margin_A1==88 ps 9
722 13:47:45.171648 TrainedVREFDQ_A0==76
723 13:47:45.172164 TrainedVREFDQ_A1==77
724 13:47:45.172584 VrefDac_Margin_A0==22
725 13:47:45.177224 DeviceVref_Margin_A0==38
726 13:47:45.177701 VrefDac_Margin_A1==22
727 13:47:45.182835 DeviceVref_Margin_A1==37
728 13:47:45.183310
729 13:47:45.183719 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
730 13:47:45.184160
731 13:47:45.216412 soc_vref_reg_value 0x 00000019 0000001a 00000017 00000019 00000017 00000019 00000018 00000017 00000018 00000016 00000017 00000015 00000017 00000019 00000017 00000019 00000018 00000019 00000019 00000018 00000017 00000018 00000018 00000019 00000018 00000017 00000019 00000019 0000001a 00000016 00000018 00000017 dram_vref_reg_value 0x 00000060
732 13:47:45.216949 2D training succeed
733 13:47:45.222009 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
734 13:47:45.227614 auto size-- 65535DDR cs0 size: 2048MB
735 13:47:45.228116 DDR cs1 size: 2048MB
736 13:47:45.233251 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
737 13:47:45.233732 cs0 DataBus test pass
738 13:47:45.238830 cs1 DataBus test pass
739 13:47:45.239301 cs0 AddrBus test pass
740 13:47:45.239709 cs1 AddrBus test pass
741 13:47:45.240189
742 13:47:45.244502 100bdlr_step_size ps== 420
743 13:47:45.244987 result report
744 13:47:45.250046 boot times 0Enable ddr reg access
745 13:47:45.255463 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
746 13:47:45.268917 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
747 13:47:45.843119 0.0;M3 CHK:0;cm4_sp_mode 0
748 13:47:45.843589 MVN_1=0x00000000
749 13:47:45.848058 MVN_2=0x00000000
750 13:47:45.853885 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
751 13:47:45.854329 OPS=0x10
752 13:47:45.854609 ring efuse init
753 13:47:45.854841 chipver efuse init
754 13:47:45.859474 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
755 13:47:45.864991 [0.018961 Inits done]
756 13:47:45.865392 secure task start!
757 13:47:45.865629 high task start!
758 13:47:45.869606 low task start!
759 13:47:45.870027 run into bl31
760 13:47:45.876297 NOTICE: BL31: v1.3(release):4fc40b1
761 13:47:45.884134 NOTICE: BL31: Built : 15:58:17, May 22 2019
762 13:47:45.884564 NOTICE: BL31: G12A normal boot!
763 13:47:45.909555 NOTICE: BL31: BL33 decompress pass
764 13:47:45.915211 ERROR: Error initializing runtime service opteed_fast
765 13:47:47.148260
766 13:47:47.148744
767 13:47:47.156493 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
768 13:47:47.156949
769 13:47:47.157225 Model: Libre Computer AML-A311D-CC Alta
770 13:47:47.364944 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
771 13:47:47.388351 DRAM: 2 GiB (effective 3.8 GiB)
772 13:47:47.531319 Core: 408 devices, 31 uclasses, devicetree: separate
773 13:47:47.537081 WDT: Not starting watchdog@f0d0
774 13:47:47.569397 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
775 13:47:47.581893 Loading Environment from FAT... Card did not respond to voltage select! : -110
776 13:47:47.586799 ** Bad device specification mmc 0 **
777 13:47:47.597735 Card did not respond to voltage select! : -110
778 13:47:47.604797 ** Bad device specification mmc 0 **
779 13:47:47.605284 Couldn't find partition mmc 0
780 13:47:47.613102 Card did not respond to voltage select! : -110
781 13:47:47.618643 ** Bad device specification mmc 0 **
782 13:47:47.619160 Couldn't find partition mmc 0
783 13:47:47.624194 Error: could not access storage.
784 13:47:47.966259 Net: eth0: ethernet@ff3f0000
785 13:47:47.966867 starting USB...
786 13:47:48.218028 Bus usb@ff500000: Register 3000140 NbrPorts 3
787 13:47:48.218560 Starting the controller
788 13:47:48.224910 USB XHCI 1.10
789 13:47:50.387213 scanning bus usb@ff500000 for devices... G12B:BL:6e7c85:2a3b91;FEAT:E0F83180:402000;POC:B;RCY:0;SPINOR:0;0.
790 13:47:50.387820 bl2_stage_init 0x01
791 13:47:50.388293 bl2_stage_init 0x81
792 13:47:50.392726 hw id: 0x0000 - pwm id 0x01
793 13:47:50.393162 bl2_stage_init 0xc1
794 13:47:50.393569 bl2_stage_init 0x02
795 13:47:50.393964
796 13:47:50.398381 L0:00000000
797 13:47:50.398805 L1:20000703
798 13:47:50.399206 L2:00008067
799 13:47:50.399598 L3:14000000
800 13:47:50.401338 B2:00402000
801 13:47:50.401766 B1:e0f83180
802 13:47:50.402165
803 13:47:50.402565 TE: 58167
804 13:47:50.402959
805 13:47:50.412495 BL2 Built : 15:22:05, Aug 28 2019. g12b g1bf2b53 - luan.yuan@droid15-sz
806 13:47:50.412948
807 13:47:50.413356 Board ID = 1
808 13:47:50.413752 Set A53 clk to 24M
809 13:47:50.414146 Set A73 clk to 24M
810 13:47:50.418173 Set clk81 to 24M
811 13:47:50.418611 A53 clk: 1200 MHz
812 13:47:50.419011 A73 clk: 1200 MHz
813 13:47:50.421717 CLK81: 166.6M
814 13:47:50.422144 smccc: 00012abd
815 13:47:50.427260 DDR driver_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 15:22:01
816 13:47:50.432854 board id: 1
817 13:47:50.437785 Load FIP HDR from SPI, src: 0x00010000, des: 0xfffd0000, size: 0x00004000, part: 0
818 13:47:50.448354 fw parse done
819 13:47:50.454382 Load ddrfw from SPI, src: 0x00030000, des: 0xfffd0000, size: 0x0000c000, part: 0
820 13:47:50.497110 Load ddrfw from SPI, src: 0x00014000, des: 0xfffd0000, size: 0x00004000, part: 0
821 13:47:50.507935 PIEI prepare done
822 13:47:50.508416 fastboot data load
823 13:47:50.508826 fastboot data verify
824 13:47:50.513510 verify result: 266
825 13:47:50.519143 Cfg max: 1, cur: 1. Board id: 255. Force loop cfg
826 13:47:50.519573 LPDDR4 probe
827 13:47:50.519974 ddr clk to 1584MHz
828 13:47:50.527148 Load ddrfw from SPI, src: 0x00018000, des: 0xfffd0000, size: 0x0000c000, part: 0
829 13:47:50.564349
830 13:47:50.564807 dmc_version 0001
831 13:47:50.571148 Check phy result
832 13:47:50.576910 INFO : End of CA training
833 13:47:50.577336 INFO : End of initialization
834 13:47:50.582509 INFO : Training has run successfully!
835 13:47:50.582932 Check phy result
836 13:47:50.588133 INFO : End of initialization
837 13:47:50.588555 INFO : End of read enable training
838 13:47:50.593690 INFO : End of fine write leveling
839 13:47:50.599316 INFO : End of Write leveling coarse delay
840 13:47:50.599748 INFO : Training has run successfully!
841 13:47:50.600180 Check phy result
842 13:47:50.604912 INFO : End of initialization
843 13:47:50.605334 INFO : End of read dq deskew training
844 13:47:50.610532 INFO : End of MPR read delay center optimization
845 13:47:50.616083 INFO : End of write delay center optimization
846 13:47:50.621701 INFO : End of read delay center optimization
847 13:47:50.622138 INFO : End of max read latency training
848 13:47:50.627338 INFO : Training has run successfully!
849 13:47:50.627761 1D training succeed
850 13:47:50.636524 Load ddrfw from SPI, src: 0x00024000, des: 0xfffd0000, size: 0x0000c000, part: 0
851 13:47:50.684190 Check phy result
852 13:47:50.684632 INFO : End of initialization
853 13:47:50.705861 INFO : End of 2D read delay Voltage center optimization
854 13:47:50.726223 INFO : End of 2D read delay Voltage center optimization
855 13:47:50.778100 INFO : End of 2D write delay Voltage center optimization
856 13:47:50.827595 INFO : End of 2D write delay Voltage center optimization
857 13:47:50.833170 INFO : Training has run successfully!
858 13:47:50.833598
859 13:47:50.834004 channel==0
860 13:47:50.838711 RxClkDly_Margin_A0==88 ps 9
861 13:47:50.839139 TxDqDly_Margin_A0==98 ps 10
862 13:47:50.844345 RxClkDly_Margin_A1==88 ps 9
863 13:47:50.844765 TxDqDly_Margin_A1==98 ps 10
864 13:47:50.845180 TrainedVREFDQ_A0==74
865 13:47:50.849991 TrainedVREFDQ_A1==74
866 13:47:50.850457 VrefDac_Margin_A0==25
867 13:47:50.850860 DeviceVref_Margin_A0==40
868 13:47:50.855453 VrefDac_Margin_A1==25
869 13:47:50.855897 DeviceVref_Margin_A1==40
870 13:47:50.856309
871 13:47:50.856690
872 13:47:50.861171 channel==1
873 13:47:50.861587 RxClkDly_Margin_A0==98 ps 10
874 13:47:50.861970 TxDqDly_Margin_A0==88 ps 9
875 13:47:50.866717 RxClkDly_Margin_A1==98 ps 10
876 13:47:50.867125 TxDqDly_Margin_A1==88 ps 9
877 13:47:50.872302 TrainedVREFDQ_A0==76
878 13:47:50.872712 TrainedVREFDQ_A1==77
879 13:47:50.873095 VrefDac_Margin_A0==22
880 13:47:50.877972 DeviceVref_Margin_A0==38
881 13:47:50.878378 VrefDac_Margin_A1==22
882 13:47:50.883560 DeviceVref_Margin_A1==37
883 13:47:50.883966
884 13:47:50.884376 dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0004
885 13:47:50.884753
886 13:47:50.917162 soc_vref_reg_value 0x 00000019 00000019 00000017 00000019 00000018 00000019 00000018 00000017 00000017 00000016 00000017 00000015 00000018 00000019 00000017 00000019 00000018 0000001a 00000019 00000018 00000016 00000018 00000018 0000001a 00000018 00000018 00000019 00000019 0000001a 00000017 00000019 00000017 dram_vref_reg_value 0x 00000060
887 13:47:50.917604 2D training succeed
888 13:47:50.922734 aml_ddr_fw_vesion: LPDDR4_PHY_V_0_1_18 build time: Aug 28 2019 13:54:19
889 13:47:50.928189 auto size-- 65535DDR cs0 size: 2048MB
890 13:47:50.928596 DDR cs1 size: 2048MB
891 13:47:50.933825 DMC_DDR_CTRL: 00e00024DDR size: 3928MB
892 13:47:50.934238 cs0 DataBus test pass
893 13:47:50.939383 cs1 DataBus test pass
894 13:47:50.939793 cs0 AddrBus test pass
895 13:47:50.940214 cs1 AddrBus test pass
896 13:47:50.940590
897 13:47:50.945062 100bdlr_step_size ps== 420
898 13:47:50.945480 result report
899 13:47:50.950580 boot times 0Enable ddr reg access
900 13:47:50.956026 Load FIP HDR from SPI, src: 0x00010000, des: 0x01700000, size: 0x00004000, part: 0
901 13:47:50.969427 Load BL3X from SPI, src: 0x0003c000, des: 0x0172c000, size: 0x000c0000, part: 0
902 13:47:51.542562 0.0;M3 CHK:0;cm4_sp_mode 0
903 13:47:51.542993 MVN_1=0x00000000
904 13:47:51.547932 MVN_2=0x00000000
905 13:47:51.553744 [Image: g12b_v1.1.3390-6ac5299 2019-09-26 14:10:05 luan.yuan@droid15-sz]
906 13:47:51.554270 OPS=0x10
907 13:47:51.554737 ring efuse init
908 13:47:51.555189 chipver efuse init
909 13:47:51.559334 29 0b 10 00 01 05 19 00 00 17 38 33 33 42 42 50
910 13:47:51.564965 [0.018960 Inits done]
911 13:47:51.565461 secure task start!
912 13:47:51.565919 high task start!
913 13:47:51.569508 low task start!
914 13:47:51.570005 run into bl31
915 13:47:51.576161 NOTICE: BL31: v1.3(release):4fc40b1
916 13:47:51.584075 NOTICE: BL31: Built : 15:58:17, May 22 2019
917 13:47:51.584579 NOTICE: BL31: G12A normal boot!
918 13:47:51.609336 NOTICE: BL31: BL33 decompress pass
919 13:47:51.615048 ERROR: Error initializing runtime service opteed_fast
920 13:47:52.847953
921 13:47:52.848655
922 13:47:52.856238 U-Boot 2024.01-rc4+ (Dec 14 2023 - 01:31:33 -0500) Libre Computer AML-A311D-CC
923 13:47:52.856750
924 13:47:52.857217 Model: Libre Computer AML-A311D-CC Alta
925 13:47:53.064739 SoC: Amlogic Meson G12B (A311D) Revision 29:b (10:2)
926 13:47:53.088085 DRAM: 2 GiB (effective 3.8 GiB)
927 13:47:53.231578 Core: 408 devices, 31 uclasses, devicetree: separate
928 13:47:53.237855 WDT: Not starting watchdog@f0d0
929 13:47:53.271463 MMC: mmc@ffe05000: 1, mmc@ffe07000: 0
930 13:47:53.282613 Loading Environment from FAT... Card did not respond to voltage select! : -110
931 13:47:53.286993 ** Bad device specification mmc 0 **
932 13:47:53.297244 Card did not respond to voltage select! : -110
933 13:47:53.304809 ** Bad device specification mmc 0 **
934 13:47:53.305385 Couldn't find partition mmc 0
935 13:47:53.313164 Card did not respond to voltage select! : -110
936 13:47:53.318757 ** Bad device specification mmc 0 **
937 13:47:53.319355 Couldn't find partition mmc 0
938 13:47:53.323750 Error: could not access storage.
939 13:47:53.666122 Net: eth0: ethernet@ff3f0000
940 13:47:53.666566 starting USB...
941 13:47:53.917830 Bus usb@ff500000: Register 3000140 NbrPorts 3
942 13:47:53.918251 Starting the controller
943 13:47:53.924845 USB XHCI 1.10
944 13:47:55.479009 scanning bus usb@ff500000 for devices... 3 USB Device(s) found
945 13:47:55.487235 scanning usb for storage devices... 0 Storage Device(s) found
947 13:47:55.538793 Hit any key to stop autoboot: 1
948 13:47:55.539640 end: 2.4.2 bootloader-interrupt (duration 00:00:32) [common]
949 13:47:55.540407 start: 2.4.3 bootloader-commands (timeout 00:04:28) [common]
950 13:47:55.540964 Setting prompt string to ['=>']
951 13:47:55.541460 bootloader-commands: Wait for prompt ['=>'] (timeout 00:04:28)
952 13:47:55.554745 0
953 13:47:55.555705 Setting prompt string to ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image']
954 13:47:55.556247 Sending with 10 millisecond of delay
956 13:47:56.690990 => setenv autoload no
957 13:47:56.701767 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:27)
958 13:47:56.706624 setenv autoload no
959 13:47:56.707344 Sending with 10 millisecond of delay
961 13:47:58.504293 => setenv initrd_high 0xffffffff
962 13:47:58.515092 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:25)
963 13:47:58.516042 setenv initrd_high 0xffffffff
964 13:47:58.516776 Sending with 10 millisecond of delay
966 13:48:00.135189 => setenv fdt_high 0xffffffff
967 13:48:00.146037 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
968 13:48:00.146990 setenv fdt_high 0xffffffff
969 13:48:00.147755 Sending with 10 millisecond of delay
971 13:48:00.440029 => dhcp
972 13:48:00.450613 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:23)
973 13:48:00.451233 dhcp
974 13:48:00.451473 Speed: 1000, full duplex
975 13:48:00.451687 BOOTP broadcast 1
976 13:48:00.458243 DHCP client bound to address 192.168.6.27 (8 ms)
977 13:48:00.458831 Sending with 10 millisecond of delay
979 13:48:02.138256 => setenv serverip 192.168.6.2
980 13:48:02.149136 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:21)
981 13:48:02.150139 setenv serverip 192.168.6.2
982 13:48:02.150896 Sending with 10 millisecond of delay
984 13:48:05.879840 => tftpboot 0x01080000 970691/tftp-deploy-ja1izsd_/kernel/uImage
985 13:48:05.890689 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:18)
986 13:48:05.891290 tftpboot 0x01080000 970691/tftp-deploy-ja1izsd_/kernel/uImage
987 13:48:05.891551 Speed: 1000, full duplex
988 13:48:05.891757 Using ethernet@ff3f0000 device
989 13:48:05.893342 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
990 13:48:05.898646 Filename '970691/tftp-deploy-ja1izsd_/kernel/uImage'.
991 13:48:05.902710 Load address: 0x1080000
992 13:48:08.925597 Loading: *################################################## 43.6 MiB
993 13:48:08.926038 14.4 MiB/s
994 13:48:08.926262 done
995 13:48:08.929400 Bytes transferred = 45713984 (2b98a40 hex)
996 13:48:08.929936 Sending with 10 millisecond of delay
998 13:48:13.616325 => tftpboot 0x08000000 970691/tftp-deploy-ja1izsd_/ramdisk/ramdisk.cpio.gz.uboot
999 13:48:13.627196 bootloader-commands: Wait for prompt ['=>', 'Resetting CPU', 'Must RESET board to recover', 'TIMEOUT', 'Retry count exceeded', 'Retry time exceeded; starting again', 'ERROR: The remote end did not respond in time.', 'File not found', 'Bad Linux ARM64 Image magic!', 'Wrong Ramdisk Image Format', 'Ramdisk image is corrupt or invalid', 'ERROR: Failed to allocate', 'TFTP error: trying to overwrite reserved memory', 'Bad Linux RISCV Image magic!', 'Wrong Image Format for boot', 'ERROR: Did not find a cmdline Flattened Device Tree', 'ERROR: RD image overlaps OS image'] (timeout 00:04:10)
1000 13:48:13.628213 tftpboot 0x08000000 970691/tftp-deploy-ja1izsd_/ramdisk/ramdisk.cpio.gz.uboot
1001 13:48:13.628730 Speed: 1000, full duplex
1002 13:48:13.629201 Using ethernet@ff3f0000 device
1003 13:48:13.630179 TFTP from server 192.168.6.2; our IP address is 192.168.6.27
1004 13:48:13.642020 Filename '970691/tftp-deploy-ja1izsd_/ramdisk/ramdisk.cpio.gz.uboot'.
1005 13:48:13.642649 Load address: 0x8000000
1006 13:48:20.206531 Loading: *################T ################################# UDP wrong checksum 00000005 0000849d
1007 13:48:25.206957 T UDP wrong checksum 00000005 0000849d
1008 13:48:35.210225 T T UDP wrong checksum 00000005 0000849d
1009 13:48:39.378485 UDP wrong checksum 000000ff 0000aac8
1010 13:48:39.419051 UDP wrong checksum 000000ff 000034bb
1011 13:48:55.213232 T T T UDP wrong checksum 00000005 0000849d
1012 13:49:10.219270 T T T
1013 13:49:10.219897 Retry count exceeded; starting again
1015 13:49:10.221387 end: 2.4.3 bootloader-commands (duration 00:01:15) [common]
1018 13:49:10.223234 end: 2.4 uboot-commands (duration 00:01:47) [common]
1020 13:49:10.224649 uboot-action failed: 1 of 1 attempts. 'matched a bootloader error message: 'Retry count exceeded' (4)'
1022 13:49:10.225760 end: 2 uboot-action (duration 00:01:47) [common]
1024 13:49:10.227252 Cleaning after the job
1025 13:49:10.227790 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/970691/tftp-deploy-ja1izsd_/ramdisk
1026 13:49:10.229205 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/970691/tftp-deploy-ja1izsd_/kernel
1027 13:49:10.264378 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/970691/tftp-deploy-ja1izsd_/dtb
1028 13:49:10.265786 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/970691/tftp-deploy-ja1izsd_/nfsrootfs
1029 13:49:10.409794 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/970691/tftp-deploy-ja1izsd_/modules
1030 13:49:10.422200 start: 4.1 power-off (timeout 00:00:30) [common]
1031 13:49:10.422926 Calling: 'curl' 'http://conserv1.mayfield.sirena.org.uk:16421/power/control/off?hostname=cambrionix&port=alta-01'
1032 13:49:10.458179 >> OK - accepted request
1033 13:49:10.460628 Returned 0 in 0 seconds
1034 13:49:10.561499 end: 4.1 power-off (duration 00:00:00) [common]
1036 13:49:10.562556 start: 4.2 read-feedback (timeout 00:10:00) [common]
1037 13:49:10.563272 Listened to connection for namespace 'common' for up to 1s
1038 13:49:11.564211 Finalising connection for namespace 'common'
1039 13:49:11.564710 Disconnecting from shell: Finalise
1040 13:49:11.564976 =>
1041 13:49:11.665663 end: 4.2 read-feedback (duration 00:00:01) [common]
1042 13:49:11.666127 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/970691
1043 13:49:14.184129 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/970691
1044 13:49:14.184735 InfrastructureError: The Infrastructure is not working correctly. Please report this error to LAVA admins.